WO2022082631A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022082631A1
WO2022082631A1 PCT/CN2020/122895 CN2020122895W WO2022082631A1 WO 2022082631 A1 WO2022082631 A1 WO 2022082631A1 CN 2020122895 W CN2020122895 W CN 2020122895W WO 2022082631 A1 WO2022082631 A1 WO 2022082631A1
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WIPO (PCT)
Prior art keywords
pin
test
sub
power supply
power
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PCT/CN2020/122895
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English (en)
French (fr)
Inventor
周宏军
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/425,949 priority Critical patent/US20220320241A1/en
Priority to PCT/CN2020/122895 priority patent/WO2022082631A1/zh
Priority to CN202080002427.9A priority patent/CN114667504A/zh
Publication of WO2022082631A1 publication Critical patent/WO2022082631A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • An embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area surrounding the display area, the peripheral area including a circuit board pin area and a test pin area located on at least one side of the display area;
  • the display substrate includes:
  • a first power line located in the display area, and electrically connected to the plurality of sub-pixels
  • At least one first bound power supply pin located in the circuit board pin area, electrically connected to the first power supply line, and configured to transmit a first power supply signal to the plurality of sub-pixels in a display stage;
  • a second power line located in the peripheral area and surrounding the display area;
  • At least one second bound power supply pin located in the circuit board pin area, electrically connected to the second power supply line, and configured to transmit a second power supply signal to the plurality of sub-pixels during a display stage;
  • At least one test power pin located in the test pin area, electrically connected to at least one of the first power line and the second power line, the at least one test power pin is configured to be in the test phase At least one of the first power supply signal and the second power supply signal is transmitted to the plurality of subpixels.
  • the at least one test power pin includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, the The second test power pin is electrically connected to the second power line.
  • the second test power pin is located on a side of the first test power pin close to the display area.
  • the display substrate further includes a first bound power lead and a second bound power lead, the first bound power lead electrically connecting the first power line and the first bound lead a fixed power supply pin, the second bound power supply lead is electrically connected to the second power supply line and the second bound power supply pin;
  • the display substrate further includes a first connection line and a second connection line, the first test power supply pin is electrically connected to the first bound power supply lead through the first connection line, and the second test power supply pin is electrically connected.
  • the pin is electrically connected to the second binding power lead through the second connecting wire.
  • the display substrate further includes first and second test power leads, the first test power leads extending along a first direction, and the second test power leads extending along the first direction extending, the first connection line extends along the second direction, the second connection line extends along the second direction, the first test power lead is electrically connected to the first connection line and the first test power pin connected, the second test power lead is electrically connected to the second connection line and the second test power pin.
  • the display substrate in a plane perpendicular to the display substrate, includes a base and a first insulating layer, an active layer, a second insulating layer, and a first gate metal stacked on the base. layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer;
  • At least part of the first connection line is disposed in the same layer as at least one of the first gate metal layer, the second gate metal layer or the first source-drain metal layer.
  • the display substrate in a plane perpendicular to the display substrate, includes a base and a first insulating layer, an active layer, a second insulating layer, and a first gate metal stacked on the base. layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer;
  • the first connection line includes a first sub-connection line and a second sub-connection line, the first sub-connection line and the first gate metal layer are arranged in the same layer, and the second sub-connection line and the second sub-connection line are arranged in the same layer.
  • the gate metal layer is arranged in the same layer, and the first sub-connection line and the second sub-connection line are connected in parallel and electrically, and the first sub-connection line is connected with the first binding power lead and the second binding power supply.
  • the leads at least partially overlap, and the second sub-connection line at least partially overlaps with the first bound power lead and the second bound power lead; or,
  • the first connection line includes a first sub-connection line and a third sub-connection line, the first sub-connection line and the third sub-connection line are electrically connected, and the first sub-connection line and the first sub-connection line are The bound power lead and the second bound power lead at least partially overlap, the third sub-connection line does not overlap the first bound power lead and the second bound power lead, and the first sub-connection
  • the third sub-connection line is arranged in the same layer as the first gate metal layer, and the third sub-connection line is arranged in the same layer as the first source-drain metal layer.
  • the first test power pin includes a first sublayer and a second sublayer, and the first sublayer and the second sublayer are electrically connected.
  • the second test power pin includes a third sublayer and a fourth sublayer, and the third sublayer and the fourth sublayer are electrically connected.
  • the display substrate in a plane perpendicular to the display substrate, includes a base and a first insulating layer, an active layer, a second insulating layer, and a first gate metal stacked on the base. layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer;
  • the first sublayer and the third sublayer are arranged in the same layer as the first source-drain metal layer, and the second sublayer and the fourth sublayer are arranged in the same layer as the first gate metal layer .
  • the first bound power pin includes a first sub-pin and a second sub-pin
  • the second bound power pin includes a third sub-pin and a fourth sub-pin pin
  • the third sub-pin is located on the side of the first sub-pin away from the second sub-pin
  • the fourth sub-pin is located in the second sub-pin away from the first sub-pin side of the pin.
  • the test power pin includes a first test power pin and a second test power pin
  • the first test power pin includes a fifth sub-pin and a sixth sub-pin
  • the second test power pin includes a seventh sub-pin and an eighth sub-pin
  • the seventh sub-pin is located on the side of the fifth sub-pin away from the circuit board pin area
  • the The eighth sub-pin is located on the side of the sixth sub-pin away from the pin area of the circuit board.
  • the display substrate further includes a first power bus, the first power bus is located on a side of the display area close to the pin area of the circuit board, and the first power bus is electrically connected The first binding power pin and the first power line.
  • the display substrate further includes a plurality of test units, at least one test data signal line and at least one test control signal line, at least one of the plurality of test units and the plurality of data lines At least one of the at least one test data signal line and the at least one test control signal line is electrically connected, and is configured to connect the at least one test data signal line to the at least one test data signal line according to a signal transmitted by the at least one test control signal line The transmitted signal is passed to the at least one data line.
  • the test pin area further includes at least one first test pin and at least one second test pin, the first test pin is located at the seventh sub-pin away from the On one side of the circuit board pin area, the second test pin is located on the side of the eighth sub-pin away from the circuit board pin area.
  • the substrate is a rigid substrate or a flexible substrate.
  • Embodiments of the present disclosure also provide a display device, including the display substrate described in any preceding item.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, the display substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a circuit board pin area located on one side of the display area and a test pin area, the display area includes a first power supply line and a plurality of sub-pixels, the peripheral area includes a second power supply line, and the circuit board pin area includes at least one first bound power supply pin and at least one The second binding power pin, the test pin area includes at least one test power pin, and the preparation method includes:
  • first insulating layer an active layer, a second insulating layer, a first gate metal layer, a third insulating layer and a second gate metal layer on the substrate in sequence;
  • At least one of the test power pins includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, the The second test power pin is electrically connected to the second power line.
  • a first connection line is formed on the second insulating layer or the third insulating layer, and the first connection line is the same as the first gate metal layer or the second gate metal layer layer settings;
  • a first test power supply lead and a second test power supply lead are formed on the fourth insulating layer, and the first test power supply lead and the second test power supply lead are arranged in the same layer as the first source-drain metal layer, and the A test power lead is electrically connected to the first connection line and the first test power pin, and the first test power pin is electrically connected to the first bound power lead through the first connection line, The second test power lead is electrically connected to the second bound power lead and the second test power pin.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 2 is one of the structural schematic diagrams of the peripheral region in the display substrate according to the exemplary embodiment of the present disclosure
  • 3A is a second structural schematic diagram of a peripheral region in a display substrate according to an exemplary embodiment of the disclosure.
  • FIG. 3B is a third structural schematic diagram showing a peripheral region in a substrate according to an exemplary embodiment of the present disclosure
  • Fig. 4 is a cross-sectional schematic diagram of a sub-pixel of the display area in Fig. 1 and the AA' area in Fig. 3B;
  • FIG. 5 is a schematic cross-sectional view of a sub-pixel of the display area in FIG. 1 and the BB' area in FIG. 3B;
  • FIG. 6 is a fourth schematic diagram showing the structure of a peripheral region in a substrate according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a fifth structural schematic diagram showing a peripheral region in a substrate according to an exemplary embodiment of the present disclosure.
  • Fig. 8 is a cross-sectional schematic diagram of a sub-pixel of the display area in Fig. 1 and the CC' area in Fig. 7;
  • Fig. 9 is a cross-sectional schematic diagram of a sub-pixel of the display area in Fig. 1 and the DD' area in Fig. 7;
  • FIG. 10 is a schematic circuit diagram of a test unit in a display substrate according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a test unit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a sixth structural schematic diagram showing a peripheral region in a substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is a seventh schematic diagram showing the structure of a peripheral region in a substrate according to an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • an exemplary embodiment of the present disclosure provides a display substrate including a display area 10 and a peripheral area 30 surrounding the display area 10 , and the peripheral area 30 includes a circuit board lead located on one side of the display area 10 .
  • the display substrate includes:
  • the first power line 411 is located in the display area 10 and is electrically connected to the plurality of sub-pixels 1;
  • the second power line 412 is located in the peripheral area 30 and surrounds the display area 10;
  • At least one test power supply pin located in the test pin area 32, is electrically connected to at least one of the first power supply line 411 and the second power supply line 412, and the at least one test power supply pin is configured to supply power to the plurality of sub-pixels 1 during the test phase. At least one of the first power supply signal and the second power supply signal is transmitted.
  • the OLED display device After the OLED display device has completed the backplane circuit fabrication, luminescent material evaporation, and water-permeable oxygen packaging processes, a cell test needs to be performed to filter out defective products and prevent defective products from flowing into the back-end process, causing back-end process materials. of waste.
  • a cell test needs to be performed to filter out defective products and prevent defective products from flowing into the back-end process, causing back-end process materials. of waste.
  • the bound power supply pins in the circuit board pin area are prevented from being scratched or bound due to the bound power supply pins in the common circuit board pin area for unit tests. problems, etc.
  • At least one test power pin includes a first test power pin 321 and a second test power pin 322 , and the first test power pin 321 is electrically connected The first power line 411 and the second test power pin 322 are electrically connected to the second power line 412 .
  • the second test power supply pin 322 is located on a side of the first test power supply pin 321 close to the display area 10 .
  • the display substrate further includes a first bound power lead 313 and a second bound power lead 314 , and the first bound power lead 313 is electrically connected to the first power line 411 and the second power lead 314 .
  • the first bound power supply pin 311 and the second bound power supply lead 314 are electrically connected to the second power supply line 412 and the second bound power supply pin 312;
  • the display substrate further includes a first connection line 303 and a second connection line 304.
  • the first test power supply pin 321 is electrically connected to the first binding power supply lead 313 through the first connection line 303
  • the second test power supply pin 322 is electrically connected to the first binding power supply lead 313 through the first connection line 303.
  • the connecting wire 304 is electrically connected to the second binding power lead 314 .
  • the display substrate further includes a first power bus 411a, the first power bus 411a is located on the side of the display area 10 close to the circuit board pin area 31, and the first power bus 411a The first bound power pin 311 and the first power line 411 are electrically connected.
  • the display substrate further includes a first test power lead 323 and a second test power lead 324, the first test power lead 323 extends along the first direction 991, and the first test power lead 323 extends along the first direction 991.
  • the two test power leads 324 extend along the first direction 991 , the first connection wires 303 extend along the second direction 992 , the second connection wires 304 extend along the second direction 304 , the first test power leads 323 are connected to the first connection wires 303 and the second A test power supply pin 321 is electrically connected, and the second test power supply lead 324 is electrically connected with the second connection wire 304 and the second test power supply pin 322 .
  • the first direction and the second direction intersect, and optionally, the first direction and the second direction are perpendicular.
  • the circuit board pin area 31 includes a first bound power lead 313 and a second bound power lead 314 , and the first bound power lead 313 is electrically connected The first power line 411 and the first bound power pin 311, and the second bound power lead 314 is electrically connected to the second power line 412 and the second bound power pin 312;
  • the test pin area 32 includes a first test power supply pin 321 , a second test power supply pin 322 , a first test power supply lead 323 connected to the first test power supply pin 321 , and a first test power supply lead 323 connected to the second test power supply pin 322 .
  • Two test power leads 324 are two test power leads 324 .
  • the display substrate further includes a first connection line 303 and a second connection line 304, the first connection line 303 is electrically connected to the first bound power supply lead 313 and the first test power supply lead 323, and the second connection line 304 is electrically connected to the second bound power supply Lead 314 and second test power lead 324.
  • the display area 10 includes: a plurality of sub-pixels 1; a plurality of data lines 11 extending along a first direction 991, each data line 11 is connected to a plurality of sub-pixels 1; There are gate lines 12 extending in a second direction 992 crossing the first direction 991 , each gate line 12 connecting a plurality of sub-pixels 1 .
  • the peripheral region 30 includes a plurality of driving units 21 and driving signal lines 413 connected to the driving units 21 , and the driving units 21 are configured to provide driving signals to the gate lines 12 .
  • the peripheral area further includes a plurality of test units 22 , at least one test data signal line 3412 and at least one test control signal line 3411 , among the plurality of test units 22
  • At least one of the plurality of data lines 11 is electrically connected to at least one of the plurality of data lines 11, at least one test data signal line 3412 and at least one test control signal line 3411, and is configured to connect the at least one test control signal line 3411 according to a signal transmitted by the at least one test control signal line 3411.
  • the signal transmitted by the test data signal line 3412 is transmitted to at least one data line 11 .
  • the display substrate in a plane perpendicular to the display substrate, may include: a substrate 100 and a first insulating layer disposed on the substrate 100 layer 200, the active layer 300 disposed on the first insulating layer 200, the second insulating layer 400 disposed on the active layer 300, the first gate metal layer 500 disposed on the second insulating layer 400, the A third insulating layer 600 on the gate metal layer 500, a second gate metal layer 700 on the third insulating layer 600, a fourth insulating layer 800 on the second gate metal layer 700, on the fourth insulating layer The first source-drain metal layer 900 on the layer 800 .
  • At least part of the first connection line 303 is connected to at least one of the first gate metal layer 500 , the second gate metal layer 700 or the first source-drain metal layer 900 Same layer setting.
  • the first bonding power pin 311 , the second bonding power pin 312 , the first test power pin 321 and the second test power pin 322 are all connected to the first source-drain metal layer 900 same-level settings.
  • the first connection line 303 and the first test power supply lead 323 are both disposed on the same layer as the second gate metal layer 700 , the first bound power supply lead 313 , the second bound power supply lead 314 , the second connection line 304 and the second test power supply
  • the leads 324 are all arranged in the same layer as the first source-drain metal layer 900 , the first connection line 303 is connected to the first power supply lead 313 through the via hole on the fourth insulating layer 800 , and the first test power lead 323 is connected to the first power supply lead 313 through the fourth insulating layer 800 .
  • the vias on the layer 800 are connected to the first test power pins 321 .
  • a and B are arranged in the same layer means that A and B are simultaneously formed through the same patterning process.
  • the first connection wire 303 and the first test power lead 323 may be an integral structure.
  • the first bound power pin 311 and the first bound power lead 313 may be an integral structure.
  • the second bonding power pin 312 and the second bonding power lead 314 may be an integral structure.
  • the second test power pins 322 , the second test power leads 324 and the second connection wires 304 may be integral structures.
  • the first power line 411 is a positive voltage power line (ELVDD), and the second power line 412 is a negative voltage power line (ELVSS).
  • ELVDD positive voltage power line
  • EVSS negative voltage power line
  • the first bound power supply pin 311 , the second bound power supply pin 312 , the first test power supply pin 321 and the second test power supply pin 311 are all disposed in the same layer as the first source-drain metal layer 900 .
  • the first connection line 303 and the first test power supply lead 323 are both disposed on the same layer as the first gate metal layer 500 , the first bound power supply lead 313 , the second bound power supply lead 314 , the second connection line 304 and the second test power supply
  • the leads 324 are all disposed in the same layer as the first source-drain metal layer 900
  • the first connection line 303 is connected to the first power supply lead 313 through vias penetrating the third insulating layer 600 and the fourth insulating layer 800
  • the leads 323 are connected to the first test power pins 321 through via holes penetrating the third insulating layer 600 and the fourth insulating layer 800 .
  • the first bonding power pin 311 , the second bonding power pin 312 , the first test power pin 321 and the second test power pin 322 are all connected to the first source-drain metal
  • the layer 900 is arranged on the same layer; the first connecting wire 303 is arranged on the same layer as the first gate metal layer 500 , the first binding power lead 313 , the second binding power lead 314 , the second connecting wire 304 , and the first test power lead 323
  • the second test power lead 324 and the first source-drain metal layer 900 are arranged in the same layer.
  • the first connection line 303 is connected to the first binding power lead 313 and the first test power lead 323 through via holes penetrating through the third insulating layer 600 and the fourth insulating layer 800 , respectively.
  • the circuit board pin area 31 includes a first bound power lead 313 and a second bound power lead 314 , and the first bound power lead 313 is electrically connected to the first The power line 411 is connected to the first bound power pin 311, and the second bound power lead 314 is electrically connected to the second power line 412 and the second bound power pin 312;
  • the test pin area 32 includes a first test power supply pin 321 , a second test power supply pin 322 , a first test power supply lead 323 connected to the first test power supply pin 321 , and a first test power supply lead 323 connected to the second test power supply pin 322 .
  • Two test power leads 324 are two test power leads 324 .
  • the display substrate further includes a first connecting wire 303 , and the first connecting wire 303 is electrically connected to the first binding power lead 313 and the first test power lead 323 .
  • the display substrate may further include a fifth insulating layer and a first flat layer disposed on the first source-drain metal layer 900, and a second source-drain metal layer disposed on the first flat layer.
  • the second connection line 304 , the first test power supply lead 323 and the second test power supply lead 324 may also be provided in the same layer as the second source-drain metal layer, and the first connection line 303 may be arranged with the first source-drain metal layer 900 and the second gate
  • the metal layer 700 or the first gate metal layer 500 is disposed in the same layer, which is not limited in the present disclosure.
  • the width of the first connection line 303 is greater than the first width.
  • the first width may be 200 microns. If the resistance at the overlapping position of the first connection line 303 and the second power supply lead 314 is too large, it is easy to cause current concentration during the high-brightness process, thereby generating a large amount of heat, so that the organic layers such as the upper insulating layer or the flat layer are generated. Burns, carbonization, severe shedding, and easy entry of water vapor, resulting in poor reliability.
  • the metal wiring resistance at the changing position is minimized, and the organic wiring such as the upper insulating layer or the flat layer caused by the large wiring resistance is avoided.
  • the layer is burnt, carbonized, and seriously peeled off, which further causes problems such as poor reliability.
  • the width of the second connection line 304 is about 50 micrometers to 1000 micrometers.
  • the width of the second connection line 304 is determined according to the size of the wiring space.
  • the orthographic projection of the edge of the first connecting wire 303 on the side close to the first test power lead 323 connected thereto on the substrate 100 is the same as the second binding power lead 314 close to the first test power lead 314.
  • the distance between the orthographic projections of the edge of one side of the power lead 323 on the substrate 100 is smaller than the first distance.
  • the size of the first distance can be determined according to the width of the cross connection between the first test power lead 323 and the first connection line 303 .
  • the first test power lead 323 with a smaller square resistance is jumped back as soon as possible, so that the wire changing position can be reduced as much as possible.
  • Metal wiring resistance to avoid burns, carbonization, serious shedding, and further problems of poor reliability caused by organic layers such as the upper insulating layer or flat layer due to large wiring resistance.
  • the first connection line 303 includes a first sub-connection line 3031 and a second sub-connection line 3032 , the first sub-connection line 3031 and the first gate metal layer 500 are arranged in the same layer, and the second sub-connection line
  • the line 3032 and the second gate metal layer 700 are disposed in the same layer, and the first sub-connection line 3031 and the second sub-connection line 3032 are connected in parallel and electrically.
  • the first sub-connection line 3031 at least partially overlaps with the first bound power lead 313 and the second bound power lead 314
  • the second sub-connection 3032 at least partially overlaps with the first bound power lead 313 and the second bound power lead 314 . Partially overlapping.
  • the first sub-connection line 3031 on the first gate metal layer 500 and the second sub-connection line 3032 on the second gate metal layer 700 are used for parallel wiring, so as to further reduce the metal wiring resistance at the switching position. , to avoid burns, carbonization of the organic layers such as the upper insulating layer or the flat layer due to the large wiring resistance, serious shedding, and further problems such as poor reliability.
  • the first connection line 303 includes a first sub-connection line 3031 and a third sub-connection line 3033 , the first sub-connection line 3031 and the third sub-connection line 3033 are electrically connected, and the first sub-connection line 3033 is electrically connected.
  • the line 3031 at least partially overlaps with the first bound power lead 313 and the second bound power lead 314.
  • the third sub-connection line 3033 does not overlap with the first bound power lead 313 and the second bound power lead 314.
  • a sub-connection line 3031 is provided in the same layer as the first gate metal layer 500
  • the third sub-connection line 3033 is provided in the same layer as the first source-drain metal layer 900 .
  • the first test power pin 321 includes a first sublayer 321a and a second sublayer 321b, and the first sublayer 321a may be electrically connected to the second sublayer 321b,
  • the first sub-layer 321 a may be disposed in the same layer as the first gate metal layer 500
  • the second sub-layer 321 b may be disposed in the same layer as the first source-drain metal layer 900 .
  • the height of the first test power supply pin 321 can be raised, so as to facilitate the unit test (CellTest).
  • the signal leads of the power supply pins 321 are usually drawn out from the first gate metal layer 500 , and the provided first sub-layer 321 a is also beneficial to lead out the signal leads of the first test power supply pins 321 .
  • the second test power pin 322 includes a third sublayer 322a and a fourth sublayer 322b, the third sublayer 322a and the fourth sublayer 322b are electrically connected, and the third sublayer 322a and the fourth sublayer 322b are electrically connected.
  • the three sub-layers 322 a may be disposed in the same layer as the first gate metal layer 500
  • the fourth sub-layer 322 b may be disposed in the same layer as the first source-drain metal layer 900 .
  • the height of the second test power pin 322 can be raised, thereby facilitating cell testing (CellTest).
  • the signal leads of the pins 322 are usually drawn out from the first gate metal layer 500 , and the third sub-layer 322 a is also beneficial to lead out the signal leads of the second test power pins 322 .
  • the second bonding power pin 312 includes a fifth sublayer 312a and a sixth sublayer 312b, and the fifth sublayer 312a may be electrically connected to the sixth sublayer 312b , the fifth sub-layer 312 a may be disposed in the same layer as the first gate metal layer 500 , and the sixth sub-layer 312 b may be disposed in the same layer as the first source-drain metal layer 900 .
  • the display substrate of the embodiment of the present disclosure by arranging the fifth sublayer 312a and the sixth sublayer 312b, the height of the second bound power supply pin 312 can be raised, thereby facilitating signal binding.
  • the second bound power supply The signal leads of the pins 312 are usually drawn out from the first gate metal layer 500 , and the provided fifth sub-layer 312 a is also beneficial to lead out the signal leads of the second bound power pins 312 .
  • the first bound power pin 311 includes a seventh sublayer 311a and an eighth sublayer 311b, and the seventh sublayer 311a and the eighth sublayer 311b are electrically connected,
  • the seventh sub-layer 311 a may be disposed in the same layer as the first gate metal layer 500
  • the eighth sub-layer 311 b may be disposed in the same layer as the first source-drain metal layer 900 .
  • the display substrate of the embodiment of the present disclosure by arranging the seventh sublayer 311a and the eighth sublayer 311b, the height of the first bound power supply pin 311 can be raised, thereby facilitating signal binding.
  • the first bound power supply The signal leads of the pins 311 are usually drawn out from the first gate metal layer 500 , and the seventh sub-layer 311 a provided is also beneficial to lead out the signal leads of the first bound power pins 311 .
  • the first sub-layer 321a, the third sub-layer 322a, the fifth sub-layer 312a, and the seventh sub-layer 311a may also be disposed in the same layer as the second gate metal layer 700, and the present disclosure is for this purpose No restrictions apply.
  • the display substrate further includes a plurality of test signal lines 341 .
  • the test pin area 32 further includes a plurality of test pins 325 and a plurality of test connection wires 326 connected to the test pins 325 in a one-to-one correspondence.
  • the display substrate of the embodiment of the present disclosure is divided into a plurality of regions, the display region 10 (or AA region) for displaying is located in the middle, and the sub-pixel 1 (or sub-pixel) for displaying is set. in the display area 10 .
  • each unit (including the driving unit 21 , the test unit 22 , etc.) and the sub-pixel 1 in FIG. 1 are only schematically represented by “rectangles”, and the area occupied by them is not necessarily a rectangle.
  • each unit (including the driving unit 21, the testing unit 22, etc.) only corresponds to a small part of the peripheral area, so in the subsequent drawings, many structures at the local part of each unit are approximately treated as straight lines .
  • the sub-pixel 1 refers to the smallest structure that can be used to independently display the desired content, that is, the smallest "dot" that can be independently controlled in the display device.
  • the specific forms of the sub-pixels 1 are various, as long as independent display can be realized.
  • an organic light emitting diode OLED can be used as a light emitting device, which is specifically an organic light emitting diode display substrate.
  • different sub-pixels 1 can have different colors, so that color display can be realized by light mixing of different sub-pixels 1 .
  • a plurality of sub-pixels 1 of different colors arranged together can form a "pixel (or pixel unit)", that is, the light emitted by these sub-pixels 1 is mixed together to form a visual "pixel". point”; for example, three sub-pixels 1 of three colors, red, green, and blue, form one pixel.
  • there may be no definite pixels (or pixel units) and color display may be realized by “common” between adjacent sub-pixels 1 .
  • the data lines 11 extending along the first direction 991 and the gate lines 12 extending along the second direction 992 are further provided, wherein the first direction 991 intersects the second direction 992 ( (that is, not parallel to each other), so that each intersection of the data line 11 and the gate line 12 can define a sub-pixel 1, and through the joint control of the gate line 12 and the data line 11, the intersection of the two can be Subpixel 1 is displayed.
  • the first direction 991 is perpendicular to the second direction 992 , that is, the first direction 991 may be a column direction (the longitudinal direction in FIG. 1 ), and the second direction 992 may be a row direction ( FIG. 1 ) that is perpendicular to the column direction. in the horizontal direction).
  • first direction 991 and the second direction 992 are actually only two opposite directions corresponding to the data line 11 and the gate line 12 , which are not necessarily the column direction and the row direction, and are different from the direction of the display substrate (or display device). There is no necessary relationship between the shape, location, placement, etc.
  • the sub-pixels 1 in the display area 10 may be arranged in an array, that is, the sub-pixels 1 may be arranged in multiple rows and columns, wherein each row of sub-pixels 1 is connected to one gate line 12 , and each column of sub-pixels 1 is connected to A data line 11.
  • the sub-pixels 1 are not necessarily arranged in an array, and each data line 11 and each gate line 12 are not necessarily connected to the sub-pixels 1 in the same column and row.
  • a pin (Pad or Pin) in the embodiment of the present disclosure refers to a structure in the display substrate that can acquire other signals and introduce signals into signal lines.
  • the pins can be used to connect with a flexible circuit board (FPC) or a driver chip (Bonding) to obtain signals from the FPC or the driver chip.
  • FPC flexible circuit board
  • Driver chip Driver chip
  • the pins can also be used to make contact with test probes of the test device to obtain signals from the test probes.
  • the peripheral area 30 may be divided into first and second half areas “(left and right half areas in FIG. 1 )” opposite to both sides of the display area 10 along the second direction 992 .
  • the driving units 21 in the first half area can It is a gate driving unit 211 that provides gate driving signals to a plurality of gate lines 12, so that the gate driving unit 211 is connected to the corresponding gate lines 12 nearby.
  • each gate driving unit 211 may be one gate shift register (GOA), and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers may A plurality of gate lines 12 provide driving signals.
  • GOA gate shift register
  • the display area 10 further includes a plurality of gate lines 13 extending along the second direction 992, and each gate line 13 is connected to a plurality of sub-pixels 1;
  • the driving unit 21 located in the second half area is the gate driving unit 212 , and the gate driving unit 212 is configured to provide gate driving signals to the plurality of gate lines 13 .
  • the display area 10 may further be provided with control electrode lines 13 that also extend along the second direction 992 , and each control electrode line 13 may also be connected to one or two rows of sub-pixels 1 .
  • the driving units 21 in the second half area can It is a gate driving unit 212 that provides gate driving signals to a plurality of gate lines 13 , so that the gate driving unit 212 is connected to the corresponding gate lines 13 nearby.
  • the specific form of the above driving unit 21 is not a limitation to the embodiments of the present disclosure.
  • the driving units 21 in the two half regions can also be gate driving units 211, and provide gate driving signals for different gate lines 12 respectively, or provide gate driving signals for each gate line 12 from both sides at the same time Gate drive signal (ie, double-sided drive).
  • each gate driving unit 212 may be one gate shift register (EM GOA), and multiple gate shift registers are cascaded, so that multiple gate shift registers may be respectively Driving signals are supplied to the plurality of gate lines 12 .
  • EM GOA gate shift register
  • the test signal line 341 includes a test control line 3411 and a test data line 3412; at least one test unit 22 includes a plurality of test transistors 220; the gate of each test transistor 220 is connected to a test control line 3411, the first The pole is connected to a data line 11 , and the second pole is connected to a test data line 3412 ; each test data line 3412 is connected to a plurality of test units 22 .
  • the display substrate of this embodiment has three test data signal lines 3412 and three test control signal lines 3411 in total, and each test unit 22 includes six test transistors for controlling four data lines 11 ( Corresponding to the above 4 columns of sub-pixels 1, in every 4 columns of sub-pixels 1, two columns of sub-pixels 1 are green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, The two sub-pixels 1 in any row are blue and red respectively), and each test unit 22 includes a first test transistor 220a, a second test transistor 220b, a third test transistor 220c, a fourth test transistor 220d, and a fifth test transistor 220e and the sixth test transistor 220f, wherein the drains of the first test transistor 220a and the second test transistor 220b are connected to a column of sub-pixels 1 in which red and blue are mixed, and the drains of the fourth test transistor 220d and the fifth test transistor
  • the first test The sources of the transistor 220a and the fourth test transistor 220d are connected to the first test data signal line CTDR, the sources of the second test transistor 220b and the fifth test transistor 220e are connected to the second test data signal line CTDB, and the third test transistor 220c and the third test transistor 220c are connected to the second test data signal line CTDB.
  • the sources of the six test transistors 220f are connected to the third test data signal line CTDG, the gates of the first test transistor 220a and the fifth test transistor 220e are connected to the third test control signal line SWBR, the second test transistor 220b and the fourth test transistor 220d
  • the gates of the third test transistors 220c and the sixth test transistors 220f are connected to the first test control signal line SWG.
  • the first test data signal line CTDR and the second test data signal line CTDB can respectively control the blue color by providing the turn-on signal to the second test control signal line SWRB and the third test control signal line SWBR in turn. and red sub-pixels 1, while the first test control signal line SWG and the third test data signal line CTDG control all green sub-pixels 1, so that sub-pixels 1 of the same color display the same brightness.
  • two columns of sub-pixels 1 may be green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, any row
  • the two sub-pixels 1 are blue and red, respectively.
  • each pin of the test pin area 32 (including the test pin 325 , the first test power pin 321 and the second test power pin 322 ) is A square, and the distance a between the center points of adjacent pins is greater than the preset first distance, and the width b of each pin is greater than the preset second width.
  • test pin area 32 may perform unit testing by means of crimping or pinning.
  • the spacing between the center points of adjacent pins is between 500 and 1200 microns, and the width of each pin is between 200 and 800 microns between.
  • the spacing between the center points of adjacent pins is between 150 and 300 microns, and the width of each pin is between 100 and 300 microns. between 220 microns.
  • the pinning method Compared with the crimping method, the pinning method requires a larger width of the test pin area. If the space allows, the pinning method can be used for unit testing.
  • the substrate 100 is a rigid substrate or a flexible substrate.
  • the first bonding power pin 311 , the second bonding power pin 312 , the first test power pin 321 and the second test power pin 322 are all connected to the first source-drain metal layer 900 are set on the same layer;
  • the first connecting wire 303 and the first test power lead 323 are set on the same layer as the first gate metal layer 500, the first binding power lead 313, the second binding power lead 314, the second connecting wire 304 and
  • the second test power leads 324 are arranged in the same layer as the first source-drain metal layer 900;
  • the first connection wire 303 is connected to the first binding power lead 313 through the via holes on the third insulating layer 600 and the fourth insulating layer 800 , and the first test power pin 321 passes through the third insulating layer 600 and the fourth insulating layer 800
  • the vias on the upper part are connected to the first test power lead 323 .
  • the display substrate in a plane perpendicular to the display substrate, includes a substrate 100 and a first insulating layer 200 , an active layer 300 , a second insulating layer 400 , a first insulating layer 200 , an active layer 300 , a second insulating layer 400 , a first insulating layer 200 , an Gate metal layer 500, third insulating layer 600, second gate metal layer 700, fourth insulating layer 800, first source-drain metal layer 900, fifth insulating layer, first flat layer and anode layer; test pin area 32 Including the first test power connection electrode and the second test power connection electrode, the circuit board pin area 31 includes the first bound power supply connection electrode, the second bound power supply connection electrode, the first test power connection electrode, the second test power connection electrode The electrodes, the first bound power supply connection electrodes, and the second bound power supply connection electrodes are arranged in the same layer as the anode layer.
  • the first binding power supply pin 311 , the second binding power supply pin 312 , the first testing power supply pin 321 and the second testing power supply pin 322 are all arranged in the same layer as the first source-drain metal layer 900 , and the first binding The power supply connection electrode is connected to the first bound power supply pin 311 through the first connection electrode, the second bound power supply connection electrode is connected to the second bound power supply pin 312 through the second connection electrode, and the first test power supply connection electrode is connected to the second bound power supply pin 312 through the second connection electrode.
  • the three connection electrodes are connected to the first test power supply pin 321, the second test power supply connection electrode is connected to the second test power supply pin 322 through the fourth connection electrode; the first connection line 303 is arranged in the same layer as the first gate metal layer 500, The first bound power lead 313 , the second bound power lead 314 , the second connection line 304 , the first test power lead 323 and the second test power lead 324 are all disposed on the same layer as the first source-drain metal layer 900 .
  • the first connection wires 303 are respectively connected to the first binding power lead 313 and the first test power lead 323 through the via holes on the fourth insulating layer 800 .
  • the first bound power pin 311 includes a first sub-pin 3111 and a second sub-pin 3112
  • the second bound power pin 312 includes a third sub-pin
  • the pin 3121 and the fourth sub-pin 3122, the third sub-pin 3121 is located on the side of the first sub-pin 3111 away from the second sub-pin 3112, and the fourth sub-pin 3122 is located in the second sub-pin 3112 A side away from the first sub-pin 3111.
  • the test power supply pins include a first test power supply pin 321 and a second test power supply pin 322 , and the first test power supply pin 321 includes a fifth sub-pin 3211 and the sixth sub-pin 3212, the second test power supply pin 322 includes a seventh sub-pin 3221 and an eighth sub-pin 3222, the seventh sub-pin 3221 is located in the fifth sub-pin 3211 away from the circuit board pin area 31 The eighth sub-pin 3222 is located on the side of the sixth sub-pin 3212 away from the pin area 31 of the circuit board.
  • the test pin area 32 further includes at least one first test pin 3251 and at least one second test pin 3252 , and the first test pin 3251 is located in the seventh sub-pin
  • the pin 3221 is located on the side away from the circuit board pin area 31
  • the second test pin 3252 is located on the side of the eighth sub-pin 3222 away from the circuit board pin area 31 .
  • the display substrate of the embodiment of the present disclosure is a substrate used in a display device, for example, an array substrate provided with a thin film transistor (TFT) array.
  • the binding area 30 may further include an anti-static circuit configured to eliminate static electricity, an isolation dam configured to block water vapor from entering the display area 10 , and other wiring areas, which are not limited herein.
  • circuit board pin area 31 may also be provided with other pins, which are not limited in the present disclosure.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A is the same as the boundary of the orthographic projection of B.
  • the projected boundaries overlap.
  • the substrate 100 is prepared on a glass carrier.
  • the substrate 100 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and curing to form a film Then, a first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then an amorphous layer is deposited on the first barrier layer A silicon film to form an amorphous silicon (a-si) layer covering the first barrier layer; then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; Then, a barrier film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate 100 is completed.
  • the substrate 100 may be a rigid substrate.
  • the circuit board lead area 31 and the test lead area 32 include the first insulating layer 200 disposed on the substrate 100 .
  • the second gate metal layer 700 pattern on the layer 600, the second gate metal layer 700 pattern at least includes the second capacitor electrode and the first connection line 303, the third capacitor electrode is formed in the display area 10, and the position of the second capacitor electrode is the same as that of the third capacitor electrode.
  • the first connection line 303 is formed in the peripheral region 30 .
  • the first connecting wire 303 is configured to connect the first bound power lead 313 and the first test power lead 323 formed later, so that the first bound power lead 313 and the first test power lead 323 are connected through the first connecting wire 303 at the same time. , to ensure the transmission of the signal.
  • the plurality of vias include at least two first active vias and two first vias.
  • two first active via holes are formed in the display area 10, and the fourth insulating layer 800, the third insulating layer 600 and the second insulating layer 400 in the two first active via holes are etched etched away to expose the surface of the first active layer.
  • two first via holes are formed in the peripheral region 30 , and the fourth insulating layer 800 in the first via holes is etched away to expose the surface of the first connection line 303 .
  • the two first active via holes are configured to connect the subsequently formed first source electrode and the first drain electrode with the first active layer, respectively.
  • the two first via holes are configured to connect the first binding power lead 313 and the first test power line formed subsequently to the first connection line 303 respectively, so as to realize the connection between the first test power pin 321 and the first power line. Connection.
  • the first source-drain metal layer 900 at least includes the first source-drain metal layer 900 .
  • the first source electrode and the first drain electrode are formed in the display area 10 and are respectively connected to the first active layer through the first active via hole.
  • the first power line 411 is formed in the display area 10
  • the second power line 412 is formed in the peripheral area 30
  • the first power line 411 extends from the display area 10 to the peripheral area 30 and is connected to the first binding power lead 313, the second power supply Line 412 is connected to second bound power lead 314 .
  • the first bound power supply pin 311 , the second bound power supply pin 312 , the first bound power supply lead 313 , and the second bound power supply lead 314 are formed in the circuit board pin area 31 , and the first bound power supply pin 311
  • the first binding power lead 313 may be an integral structure, and the second binding power pin 312 and the second binding power lead 314 may be an integrated structure.
  • the first binding power lead 313 is connected to the first test power lead 323 through the first via hole.
  • a first test power supply pin 321, a second test power supply pin 322, a first test power supply lead 323, and a second test power supply lead 324 are formed in the test pin area 32.
  • the first test power supply pin 321 and the first test power supply lead 323 can be an integral structure, and the second binding power lead 314 is connected to the second test power lead 324 through the second connecting wire 304 .
  • the second test power supply pin 322, the second test power supply lead 324 and the second connection wire 304 may have an integrated structure.
  • a fifth insulating film is first deposited, and then a first flat film of organic material is coated to form a fifth insulating layer covering the entire substrate 100 and disposed on the fifth insulating film.
  • the first flat (PLN) layer on the layer through the patterning process of masking, exposing and developing, an anode via hole is formed on the first flat layer, and the anode via hole is formed in the display area 10.
  • a planarization layer and a fifth insulating layer are removed, exposing the surface of the first drain electrode of the first transistor.
  • the fifth insulating layer and the first planarization layer are referred to as composite insulating layers.
  • the composite insulating layer may include only the fifth insulating layer, or only the first planarization layer.
  • the first planar layer can be directly formed on the substrate 100 on which the aforementioned pattern is formed, and the first planar layer can be formed on the circuit board pin area 31 and the test pin area 32 .
  • the driving structure layer pattern is prepared on the substrate 100 .
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute a driving transistor in the pixel driving circuit
  • the first capacitor electrode and the second capacitor electrode constitute a storage device in the pixel driving circuit capacitance.
  • the display substrate further includes an anode, a pixel definition (PDL) layer, a spacer post (PS), an organic light emitting layer, a cathode, and an encapsulation layer formed in the display area 10, and the encapsulation layer may include a stacked first An encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.
  • PDL pixel definition
  • PS spacer post
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride Any one or more of (SiON), which may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • the first metal film, the second metal film, the third metal film and the fourth metal film can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • any one or more of the above metals, or alloy materials of the above metals can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc. .
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • the exemplary embodiment of the present disclosure makes the display substrate turn on by arranging the first test power supply pin and the second test power supply pin in the test pin area. During the test, the first bound power supply pin and the second bound power supply pin in the pin area of the circuit board will not be damaged, which improves the reliability of signal input.
  • Exemplary embodiments of the present disclosure show the structure of the substrate and the fabrication process thereof are merely illustrative. In the exemplary embodiment, the corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • the circuit board pin area 31 includes a first bound power supply pin 311 , a second bound power supply pin 312 , a first bound power supply lead 313 connected to the first bound power supply pin 311 , and The second bound power lead 314 is connected to the second bound power pin 312 , the first power line 411 is connected to the first bound power lead 313 , and the second power line 412 is connected to the second bound power lead 314 .
  • the test pin area 32 includes a first test power supply pin 321 , a second test power supply pin 322 , a first test power supply lead 323 connected to the first test power supply pin 321 , and a first test power supply lead 323 connected to the second test power supply pin 322 .
  • Two test power leads 324, the test pin area 32 also includes a plurality of test pins 325 and a plurality of test connection lines 326 connected to the test pins 325 in one-to-one correspondence, the test pins 325 and the test connection lines 326 are connected to the first source
  • the drain metal layer 900 is disposed in the same layer.
  • the first connecting wire 303 is electrically connected to the first binding power lead 313 and the first test power lead 323 .
  • the present disclosure also provides a preparation method of a display substrate, the display substrate includes a display area and a peripheral area surrounding the display area, the peripheral area includes a circuit board pin area and a test pin area on one side of the display area, and the display area includes a first a power supply line and a plurality of sub-pixels, the peripheral area includes a second power supply line, the circuit board pin area includes at least one first bound power supply pin and at least one second bound power supply pin, and the test pin area includes at least one test pin area power supply pin.
  • the preparation method includes:
  • first insulating layer an active layer, a second insulating layer, a first gate metal layer, a third insulating layer and a second gate metal layer on the substrate in sequence;
  • a first source-drain metal layer, a first power supply line, a second power supply line, a first binding power supply pin, a second binding power supply pin and a test power supply pin are formed on the fourth insulating layer; the first power supply line is connected to the The first bound power supply pin is electrically connected, the second power supply line is electrically connected with the second bound power supply pin, and the test power supply pin is electrically connected with at least one of the first power supply line and the second power supply line.
  • the test power pin includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, and the second test power pin is electrically connected to the second power supply Wire.
  • the preparation method further comprises:
  • a first connection line is formed on the second insulating layer or the third insulating layer, and the first connection line is arranged in the same layer as the first gate metal layer or the second gate metal layer;
  • a first test power lead and a second test power lead are formed on the fourth insulating layer.
  • the first test power lead and the second test power lead are arranged on the same layer as the first source-drain metal layer, and the first test power lead is connected to the first
  • the wire is electrically connected with the first test power supply pin
  • the first test power supply pin is electrically connected with the first bound power supply lead through the first connecting line
  • the second test power supply lead is electrically connected with the second bound power supply lead and the second test power supply lead. electrical connection.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiments.
  • the display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区和周边区，周边区包括位于显示区至少一侧的电路板引脚区和测试引脚区。显示基板还包括：多个子像素以及与多个子像素电连接的第一电源线；至少一个第一绑定电源引脚，位于电路板引脚区，与第一电源线电连接，被配置为在显示阶段向多个子像素传输第一电源信号；第二电源线，位于周边区且围绕显示区；至少一个第二绑定电源引脚，位于电路板引脚区，与第二电源线电连接，被配置为在显示阶段向多个子像素传输第二电源信号；至少一个测试电源引脚，位于测试引脚区，电连接至第一电源线和第二电源线中的至少一个，被配置为在测试阶段向多个子像素传输第一电源信号和第二电源信号中的至少之一。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区至少一侧的电路板引脚区和测试引脚区；所述显示基板包括：
多个子像素，位于所述显示区；
第一电源线，位于所述显示区，且与所述多个子像素电连接；
至少一个第一绑定电源引脚，位于所述电路板引脚区，与所述第一电源线电连接，被配置为在显示阶段向所述多个子像素传输第一电源信号；
第二电源线，位于所述周边区且围绕所述显示区；
至少一个第二绑定电源引脚，位于所述电路板引脚区，与所述第二电源线电连接，被配置为在显示阶段向所述多个子像素传输第二电源信号；
至少一个测试电源引脚，位于所述测试引脚区，电连接至所述第一电源 线和所述第二电源线中的至少一个，所述至少一个测试电源引脚被配置为在测试阶段向所述多个子像素传输所述第一电源信号和所述第二电源信号中的至少之一。
在一些示例性实施例中，所述至少一个测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚电连接所述第一电源线，所述第二测试电源引脚电连接所述第二电源线。
在一些示例性实施例中，所述第二测试电源引脚位于所述第一测试电源引脚靠近所述显示区的一侧。
在一些示例性实施例中，所述显示基板还包括第一绑定电源引线和第二绑定电源引线，所述第一绑定电源引线电连接所述第一电源线和所述第一绑定电源引脚，所述第二绑定电源引线电连接第二电源线和第二绑定电源引脚；
所述显示基板还包括第一连接线和第二连接线，所述第一测试电源引脚通过所述第一连接线与所述第一绑定电源引线电连接，所述第二测试电源引脚通过所述第二连接线与所述第二绑定电源引线电连接。
在一些示例性实施例中，所述显示基板还包括第一测试电源引线和第二测试电源引线，所述第一测试电源引线沿第一方向延伸，所述第二测试电源引线沿第一方向延伸，所述第一连接线沿第二方向延伸，所述第二连接线沿第二方向延伸，所述第一测试电源引线与所述第一连接线和所述第一测试电源引脚电连接，所述第二测试电源引线与所述第二连接线和所述第二测试电源引脚电连接。
在一些示例性实施例中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
至少部分所述第一连接线与所述第一栅金属层、所述第二栅金属或所述第一源漏金属层中的至少一层同层设置。
在一些示例性实施例中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
所述第一连接线包括第一子连接线和第二子连接线，所述第一子连接线与所述第一栅金属层同层设置，所述第二子连接线与所述第二栅金属层同层设置，且所述第一子连接线和所述第二子连接线并联且电连接，所述第一子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠，所述第二子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠；或，
所述第一连接线包括第一子连接线和第三子连接线，所述第一子连接线和所述第三子连接线电连接，且所述第一子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠，所述第三子连接线与所述第一绑定电源引线、第二绑定电源引线不交叠，所述第一子连接线与所述第一栅金属层同层设置，所述第三子连接线与所述第一源漏金属层同层设置。
在一些示例性实施例中，所述第一测试电源引脚包括第一子层和第二子层，所述第一子层和所述第二子层电连接。
在一些示例性实施例中，所述第二测试电源引脚包括第三子层和第四子层，所述第三子层和所述第四子层电连接。
在一些示例性实施例中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
所述第一子层和所述第三子层与所述第一源漏金属层同层设置，所述第二子层和所述第四子层与所述第一栅金属层同层设置。
在一些示例性实施例中，所述第一绑定电源引脚包括第一子引脚和第二子引脚，所述第二绑定电源引脚包括第三子引脚和第四子引脚，所述第三子引脚位于所述第一子引脚远离所述第二子引脚的一侧，所述第四子引脚位于所述第二子引脚远离所述第一子引脚的一侧。
在一些示例性实施例中，所述测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚包括第五子引脚和第六子引脚，所述第二测试电源引脚包括第七子引脚和第八子引脚，所述第七子引脚位于所述第五子引脚远离所述电路板引脚区的一侧，所述第八子引脚位于所述第六子引脚远离所述电路板引脚区的一侧。
在一些示例性实施例中，所述显示基板还包括第一电源总线，所述第一电源总线位于所述显示区靠近所述电路板引脚区的一侧，所述第一电源总线电连接所述第一绑定电源引脚与所述第一电源线。
在一些示例性实施例中，所述显示基板还包括多个测试单元、至少一条测试数据信号线和至少一条测试控制信号线，所述多个测试单元中的至少一个与所述多条数据线中的至少一条、所述至少一条测试数据信号线和所述至少一条测试控制信号线电连接，并被配置为根据所述至少一条测试控制信号线传输的信号将所述至少一条测试数据信号线传输的信号传递给所述至少一条数据线。
在一些示例性实施例中，所述测试引脚区还包括至少一个第一测试引脚和至少一个第二测试引脚，所述第一测试引脚位于所述第七子引脚远离所述电路板引脚区的一侧，所述第二测试引脚位于所述第八子引脚远离所述电路板引脚区的一侧。
在一些示例性实施例中，所述基底为刚性基底或柔性基底。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区一侧的电路板引脚区和测试引脚区，所述显示区包括第一电源线和多个子像素，所述周边区包括第二电源线，所述电路板引脚区包括至少一个第一绑定电源引脚及至少一个第二绑定电源引脚，所述测试引脚区包括至少一个测试电源引脚，所述制备方法包括：
在基底上依次形成第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层和第二栅金属层；
在所述第二栅金属层上形成第四绝缘层；
在所述第四绝缘层上形成第一源漏金属层、所述第一电源线、所述第二电源线、所述第一绑定电源引脚、所述第二绑定电源引脚和至少一个所述测试电源引脚；所述第一电源线与所述第一绑定电源引脚电连接，所述第二电源线与所述第二绑定电源引脚电连接，至少一个所述测试电源引脚与所述第 一电源线和所述第二电源线中的至少一个电连接。
在一些示例性实施例中，至少一个所述测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚电连接所述第一电源线，所述第二测试电源引脚电连接所述第二电源线。
在一些示例性实施例中，在所述第二绝缘层或第三绝缘层上形成第一连接线，所述第一连接线与所述第一栅金属层或所述第二栅金属层同层设置；
在所述第四绝缘层上形成第一测试电源引线和第二测试电源引线，所述第一测试电源引线和第二测试电源引线与所述第一源漏金属层同层设置，所述第一测试电源引线与所述第一连接线和所述第一测试电源引脚电连接，所述第一测试电源引脚通过所述第一连接线与所述第一绑定电源引线电连接，所述第二测试电源引线与所述第二绑定电源引线和所述第二测试电源引脚电连接。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开示例性实施例显示基板的结构示意图；
图2为本公开示例性实施例显示基板中周边区的结构示意图之一；
图3A为本公开示例性实施例显示基板中周边区的结构示意图之二；
图3B为本公开示例性实施例显示基板中周边区的结构示意图之三；
图4为图1中显示区的一个子像素和图3B中的AA’区的剖面示意图；
图5为图1中显示区的一个子像素和图3B中的BB’区的剖面示意图；
图6为本公开示例性实施例显示基板中周边区的结构示意图之四；
图7为本公开示例性实施例显示基板中周边区的结构示意图之五；
图8为图1中显示区的一个子像素和图7中的CC’区的剖面示意图；
图9为图1中显示区的一个子像素和图7中的DD’区的剖面示意图；
图10本公开实施例一种显示基板中的测试单元的电路示意图；
图11本公开实施例一种显示基板中的测试单元结构示意图；
图12为本公开示例性实施例显示基板中周边区的结构示意图之六；
图13为本公开示例性实施例显示基板中周边区的结构示意图之七。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根 据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
如图1和图2所示，本公开示例性实施例提供了一种显示基板，包括显示区10以及围绕显示区10的周边区30，周边区30包括位于显示区10一侧的电路板引脚区31和测试引脚区32。
该显示基板包括：
多个子像素1，位于显示区10；
第一电源线411，位于显示区10，且与多个子像素1电连接；
至少一个第一绑定电源引脚311，位于电路板引脚区31，与第一电源线电连接411，被配置为在显示阶段向多个子像素1传输第一电源信号；
第二电源线412，位于周边区30且围绕显示区10；
至少一个第二绑定电源引脚312，位于电路板引脚区31，与第二电源线412电连接，被配置为在显示阶段向多个子像素1传输第二电源信号；
至少一个测试电源引脚，位于测试引脚区32，电连接至第一电源线411和第二电源线412中的至少一个，至少一个测试电源引脚被配置为在测试阶段向多个子像素1传输第一电源信号和第二电源信号中的至少之一。
OLED显示装置在完成背板电路制作、发光材料蒸镀、隔水氧封装工艺之后，需进行单元测试(Cell Test)，以过滤不良品，防止不良品流入后端工艺中，造成后端工艺资材的浪费。本公开实施例的显示基板，通过设置单独的测试电源引脚，避免因单元测试共用电路板引脚区的绑定电源引脚造成电路板引脚区的绑定电源引脚划伤或绑定不良等问题。
在一种示例性实施例中，如图1和图2所示，至少一个测试电源引脚包括第一测试电源引脚321和第二测试电源引脚322，第一测试电源引脚321电连接第一电源线411，第二测试电源引脚322电连接第二电源线412。
在一种示例性实施例中，如图6所示，第二测试电源引脚322位于第一测试电源引脚321靠近显示区10的一侧。
在一种示例性实施例中，如图3A所示，显示基板还包括第一绑定电源引线313和第二绑定电源引线314，第一绑定电源引线313电连接第一电源线411和第一绑定电源引脚311，第二绑定电源引线314电连接第二电源线 412和第二绑定电源引脚312；
显示基板还包括第一连接线303和第二连接线304，第一测试电源引脚321通过第一连接线303与第一绑定电源引线313电连接，第二测试电源引脚322通过第二连接线304与第二绑定电源引线314电连接。
在一种示例性实施例中，如图2所示，显示基板还包括第一电源总线411a，第一电源总线411a位于显示区10靠近电路板引脚区31的一侧，第一电源总线411a电连接第一绑定电源引脚311与第一电源线411。
在一种示例性实施例中，如图2和图3B所示，显示基板还包括第一测试电源引线323和第二测试电源引线324，第一测试电源引线323沿第一方向991延伸，第二测试电源引线324沿第一方向991延伸，第一连接线303沿第二方向992延伸，第二连接线304沿第二方向304延伸，第一测试电源引线323与第一连接线303和第一测试电源引脚321电连接，第二测试电源引线324与第二连接线304和第二测试电源引脚322电连接。所述第一方向和所述第二方向交叉，可选地，所述第一方向和所述第二方向垂直。
在一种示例性实施例中，如图2和图3B所示，电路板引脚区31包括第一绑定电源引线313和第二绑定电源引线314，第一绑定电源引线313电连接第一电源线411和第一绑定电源引脚311，第二绑定电源引线314电连接第二电源线412和第二绑定电源引脚312；
测试引脚区32包括第一测试电源引脚321、第二测试电源引脚322、与第一测试电源引脚321连接的第一测试电源引线323以及与第二测试电源引脚322连接的第二测试电源引线324。
显示基板还包括第一连接线303和第二连接线304，第一连接线303电连接第一绑定电源引线313和第一测试电源引线323，第二连接线304电连接第二绑定电源引线314和第二测试电源引线324。
在一种示例性实施方式中，如图1所示，显示区10包括：多个子像素1；多条沿第一方向991延伸的数据线11，每条数据线11连接多个子像素1；多条沿与第一方向991交叉的第二方向992延伸的栅极线12，每条栅极线12连接多个子像素1。
周边区30包括多个驱动单元21以及与驱动单元21连接的驱动信号线413，驱动单元21配置为向栅极线12提供驱动信号。
在一种示例性实施方式中，如图1和图11所示，周边区还包括多个测试单元22、至少一条测试数据信号线3412和至少一条测试控制信号线3411，多个测试单元22中的至少一个与多条数据线11中的至少一条、至少一条测试数据信号线3412和至少一条测试控制信号线3411电连接，并被配置为根据至少一条测试控制信号线3411传输的信号将至少一条测试数据信号线3412传输的信号传递给至少一条数据线11。
在一种示例性实施方式中，如图4至图5、图7至图8所示，在垂直于显示基板的平面内，显示基板可以包括：基底100，设置在基底100上的第一绝缘层200，设置在第一绝缘层200上的有源层300，设置在有源层300上的第二绝缘层400，设置在第二绝缘层400上的第一栅金属层500，设置在第一栅金属层500上的第三绝缘层600，设置在第三绝缘层600上的第二栅金属层700，设置在第二栅金属层700上的第四绝缘层800，设置在第四绝缘层800上的第一源漏金属层900。
在一种示例性实施例中，如图3A和图6所示，至少部分第一连接线303与第一栅金属层500、第二栅金属层700或第一源漏金属层900中的至少一层同层设置。
在一种示例性实施例中，第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322均与第一源漏金属层900同层设置。第一连接线303和第一测试电源引线323均与第二栅金属层700同层设置，第一绑定电源引线313、第二绑定电源引线314、第二连接线304和第二测试电源引线324均与第一源漏金属层900同层设置，第一连接线303通过第四绝缘层800上的过孔与第一绑定电源引线313连接，第一测试电源引线323通过第四绝缘层800上的过孔与第一测试电源引脚321连接。
本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成。
在一种示例性实施例中，第一连接线303和第一测试电源引线323可以 为一体结构。
在一种示例性实施例中，第一绑定电源引脚311和第一绑定电源引线313可以为一体结构。
在一种示例性实施例中，第二绑定电源引脚312和第二绑定电源引线314可以为一体结构。
在一种示例性实施例中，第二测试电源引脚322、第二测试电源引线324和第二连接线304可以为一体结构。
在一种示例性实施例中，第一电源线411为正电压电源线(ELVDD)，第二电源线412为负电压电源线(ELVSS)。
在另一种示例性实施例中，如图3至图5所示，第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322均与第一源漏金属层900同层设置。第一连接线303和第一测试电源引线323均与第一栅金属层500同层设置，第一绑定电源引线313、第二绑定电源引线314、第二连接线304和第二测试电源引线324均与第一源漏金属层900同层设置，第一连接线303通过贯穿第三绝缘层600和第四绝缘层800的过孔与第一绑定电源引线313连接，第一测试电源引线323通过贯穿第三绝缘层600和第四绝缘层800的过孔与第一测试电源引脚321连接。
在又一种示例性实施例中，第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322均与第一源漏金属层900同层设置；第一连接线303与第一栅金属层500同层设置，第一绑定电源引线313、第二绑定电源引线314、第二连接线304、第一测试电源引线323和第二测试电源引线324均与第一源漏金属层900同层设置。第一连接线303通过贯穿第三绝缘层600和第四绝缘层800的过孔分别与第一绑定电源引线313和第一测试电源引线323连接。
在又一种示例性实施例中，如图6所示，电路板引脚区31包括第一绑定电源引线313和第二绑定电源引线314，第一绑定电源引线313电连接第一电源线411和第一绑定电源引脚311，第二绑定电源引线314电连接第二电源线412和第二绑定电源引脚312；
测试引脚区32包括第一测试电源引脚321、第二测试电源引脚322、与第一测试电源引脚321连接的第一测试电源引线323以及与第二测试电源引脚322连接的第二测试电源引线324。
显示基板还包括第一连接线303，第一连接线303电连接第一绑定电源引线313和第一测试电源引线323。
在一种示例性实施例中，显示基板还可以包括设置在第一源漏金属层900上的第五绝缘层和第一平坦层，设置在第一平坦层上的第二源漏金属层。第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322、第一绑定电源引线313、第二绑定电源引线314、第二连接线304、第一测试电源引线323和第二测试电源引线324也可以与第二源漏金属层同层设置，第一连接线303可以与第一源漏金属层900、第二栅金属层700、或第一栅金属层500同层设置，本公开对此不作限制。
在一种示例性实施例中，第一连接线303的宽度大于第一宽度。示例性的，第一宽度可以为200微米。若第一连接线303与第二绑定电源引线314的交叠位置电阻过大，在高亮度工艺时易造成电流集中，从而产生较大热量，从而使得上层绝缘层或平坦层等有机层产生灼伤、碳化，严重的产生脱落，进而容易进入水汽产生信赖性不良。本公开实施例通过将第一连接线303设计得尽量宽，利用尽量多的空间走线，尽量减小换线位置金属走线电阻，避免因走线电阻大造成上层绝缘层或平坦层等有机层产生灼伤、碳化，严重的产生脱落，进一步引起的信赖性不良等问题。
在一种示例性实施例中，第二连接线304的宽度约为50微米至1000微米。第二连接线304的宽度根据走线空间的大小决定。
在一种示例性实施例中，第一连接线303在靠近与其连接的第一测试电源引线323一侧的边缘在基底100上的正投影，与第二绑定电源引线314在靠近第一测试电源引线323一侧的边缘在基底100上的正投影之间的距离小于第一距离。第一距离的大小可以根据第一测试电源引线323与第一连接线303之间的交叉连接宽度决定。本公开实施例通过在第一连接线303跨过所避开的第二绑定电源引线314之后，尽早跳线换回方阻小的第一测试电源引 线323，也可以尽量减小换线位置金属走线电阻，避免因走线电阻大造成上层绝缘层或平坦层等有机层产生灼伤、碳化，严重的产生脱落，进一步引起的信赖性不良等问题。
如图7和图8所示，第一连接线303包括第一子连接线3031和第二子连接线3032，第一子连接线3031与第一栅金属层500同层设置，第二子连接线3032与第二栅金属层700同层设置，且第一子连接线3031和第二子连接线3032并联且电连接。第一子连接线3031与第一绑定电源引线313、第二绑定电源引线314至少部分交叠，第二子连接线3032与第一绑定电源引线313、第二绑定电源引线314至少部分交叠。
本公开实施例通过利用第一栅金属层500上的第一子连接线3031和第二栅金属层700上的第二子连接线3032并联走线，进一步减小换线位置的金属走线电阻，避免因走线电阻大造成上层绝缘层或平坦层等有机层产生灼伤、碳化，严重的产生脱落，进一步引起的信赖性不良等问题。
如图3A和图6所示，第一连接线303包括第一子连接线3031和第三子连接线3033，第一子连接线3031和第三子连接线3033电连接，且第一子连接线3031与第一绑定电源引线313、第二绑定电源引线314至少部分交叠，第三子连接线3033与第一绑定电源引线313、第二绑定电源引线314不交叠，第一子连接线3031与第一栅金属层500同层设置，第三子连接线3033与第一源漏金属层900同层设置。
在一种示例性实施例中，如图9所示，第一测试电源引脚321包括第一子层321a和第二子层321b，第一子层321a可以与第二子层321b电连接，第一子层321a可以与第一栅金属层500同层设置，第二子层321b可以与第一源漏金属层900同层设置。本公开实施例的显示基板，通过设置第一子层321a和和第二子层321b，可以垫高第一测试电源引脚321的高度，从而利于单元测试(CellTest)，此外，由于第一测试电源引脚321的信号引线通常由第一栅金属层500引出，设置的第一子层321a也利于引出第一测试电源引脚321的信号引线。
在一种示例性实施例中，如图9所示，第二测试电源引脚322包括第三 子层322a和第四子层322b，第三子层322a和第四子层322b电连接，第三子层322a可以与第一栅金属层500同层设置，第四子层322b可以与第一源漏金属层900同层设置。本公开实施例的显示基板，通过设置第三子层322a和第四子层322b，可以垫高第二测试电源引脚322的高度，从而利于单元测试(CellTest)，此外，由于第二测试电源引脚322的信号引线通常由第一栅金属层500引出，设置的第三子层322a也利于引出第二测试电源引脚322的信号引线。
在一种示例性实施例中，如图9所示，第二绑定电源引脚312包括第五子层312a和第六子层312b，第五子层312a可以与第六子层312b电连接，第五子层312a可以与第一栅金属层500同层设置，第六子层312b可以与第一源漏金属层900同层设置。本公开实施例的显示基板，通过设置第五子层312a和第六子层312b，可以垫高第二绑定电源引脚312的高度，从而利于信号绑定，此外，由于第二绑定电源引脚312的信号引线通常由第一栅金属层500引出，设置的第五子层312a也利于引出第二绑定电源引脚312的信号引线。
在一种示例性实施例中，如图9所示，第一绑定电源引脚311包括第七子层311a和第八子层311b，第七子层311a和第八子层311b电连接，第七子层311a可以与第一栅金属层500同层设置，第八子层311b可以与第一源漏金属层900同层设置。本公开实施例的显示基板，通过设置第七子层311a和第八子层311b，可以垫高第一绑定电源引脚311的高度，从而利于信号绑定，此外，由于第一绑定电源引脚311的信号引线通常由第一栅金属层500引出，设置的第七子层311a也利于引出第一绑定电源引脚311的信号引线。
在另一种示例性实施例中，第一子层321a、第三子层322a、第五子层312a、第七子层311a也可以与第二栅金属层700同层设置，本公开对此不作限制。在一种示例性实施例中，如图7所示，显示基板还包括多根测试信号线341。测试引脚区32还包括多个测试引脚325以及多根与测试引脚325一一对应连接的测试连接线326。
参照图1，本公开实施例的显示基板分为多个区域，位于中部的是用于进行显示的显示区10(或AA区)，用于进行显示的子像素1(或称亚像素) 设于该显示区10中。应当理解，图1中各单元(包括驱动单元21、测试单元22等)和子像素1用“矩形”表示只是示意性的，其占据的区域并不一定是矩形。对于实际的显示基板，每个单元(包括驱动单元21、测试单元22等)仅对应周边区的很小一部分，故在后续部分附图中，将每个单元局部处的许多结构近似处理为直线。应当理解，基于面积的限制，本公开实施例的许多附图中，子像素1引线(如信号线)、接头、单元、区域等各种结构的形状、尺寸、尺寸比例、个数、个数比例、位置等都只是示例性的，而不是对本公开实施例的限定。例如，实际的测试信号线341、驱动信号线413等的数量应比图1中示出的更多。
本公开实施例中，子像素1是指可用于独立显示所需内容的最小的结构，即是显示装置中可独立的控制的最小的“点”。子像素1的具体形式是多样的，只要能实现独立的显示即可。
也就是说，本公开实施例的显示基板的各子像素1中，可用有机发光二极管OLED作为发光器件，其具体是有机发光二极管显示基板。
其中，不同的子像素1可具有不同的颜色，从而通过不同子像素1的混光可实现彩色显示。其中，当要实现彩色显示时，可以是多个排在一起的不同颜色的子像素1组成一个“像素(或像素单元)”，即这些子像素1发出的光混在一起成为视觉上的一个“点”；例如，可以是红色、绿色、蓝色三种颜色的三个子像素1组成一个像素。或者，也可不存在明确的像素(或像素单元)，而是通过临近子像素1间的“公用”实现彩色显示。
参照图1，显示区10中，还设有沿第一方向991延伸的数据线11，以及沿第二方向992延伸的栅极线12，其中，第一方向991是与第二方向992交叉(即不相互平行)的，从而数据线11与栅极线12的每个交叉处可限定出一个子像素1，而通过栅极线12与数据线11的共同控制，可使二者交叉处的子像素1进行显示。
在一些实施例中，第一方向991垂直于第二方向992，即第一方向991可为列方向(图1中为纵向)，第二方向992可为与列方向垂直的行方向(图1中为横向)。
应当理解，第一方向991、第二方向992实际只是对应数据线11和栅极 线12的两个相对方向，二者不一定是列方向、行方向，且与显示基板(或显示装置)的形状、所处位置、放置方式等没有必然的关系。
在一些实施例中，显示区10中的子像素1可排成阵列，即子像素1可排成多行、多列，其中每行子像素1连接一条栅极线12，每列子像素1连接一条数据线11。子像素1不一定排成阵列，每条数据线11、栅极线12也不一定连接同列、同行的子像素1。
本公开实施例中的引脚(Pad或Pin)是指显示基板中的可获取其它信号并将信号引入信号线的结构。引脚可用于与柔性线路板(FPC)或驱动芯片绑定(Bonding)连接，从而获取来自柔性线路板或驱动芯片的信号。或者，引脚也可用于与测试装置的测试探针接触，从而获得来自测试探针的信号。
参照图1，周边区30可分为沿第二方向992在显示区10的两侧相对的第一半区和第二半区“(图1中的左半区和右半区)”。其中，由于栅极线12是沿第二方向992延伸的，故所有栅极线12均对应第一半区(图1中的左半区)，因此，第一半区中的驱动单元21可为向多条栅极线12提供栅极驱动信号的栅极驱动单元211，以便栅极驱动单元211就近连接对应的栅极线12。
在一种示例性实施例中，每个栅极驱动单元211可为一个栅极移位寄存器(GOA)，而多个栅极移位寄存器级联，从而多个栅极移位寄存器可分别向多条栅极线12提供驱动信号。
在一些实施例中，显示区10还包括多条沿第二方向992延伸的控制极线13，每条控制极线13与多个子像素1连接；
位于第二半区的驱动单元21为控制极驱动单元212，控制极驱动单元212配置为向多条控制极线13提供控制极驱动信号。
参照图1，显示区10中还可设有同样沿第二方向992延伸的控制极线13，每条控制极线13也可连接一行或两行子像素1。
其中，由于控制极线13也是沿第二方向992延伸的，故所有控制极线13均对应第二半区(图1中的右半区)，因此，第二半区中的驱动单元21可为向多条控制极线13提供控制极驱动信号的控制极驱动单元212，以便控 制极驱动单元212就近连接对应的控制极线13。
当然，以上驱动单元21的具体形式不是对本公开实施例的限定。例如，两个半区中的驱动单元21也可均为栅极驱动单元211，并分别为不同的栅极线12提供栅极驱动信号，或者是为每条栅极线12从两侧同时提供栅极驱动信号(即双侧驱动)。
在一种示例性实施例中，每个控制极驱动单元212可为一个控制极移位寄存器(EM GOA)，而多个控制极移位寄存器级联，从而多个控制极移位寄存器可分别向多条控制极线12提供驱动信号。
在一些实施例中，测试信号线341包括测试控制线3411和测试数据线3412；至少一个测试单元22包括多个测试晶体管220；每个测试晶体管220的栅极连接一条测试控制线3411，第一极连接一条数据线11，第二极连接一条测试数据线3412；每条测试数据线3412与多个测试单元22连接。
参照图10和图11，本实施例的显示基板共有3条测试数据信号线3412和3条测试控制信号线3411，每个测试单元22包括6个测试晶体管，用于控制4条数据线11(对应以上4列子像素1，每4列子像素1中，两列子像素1为绿色，剩余两列子像素1的每一列中，红色和蓝色的子像素1交替排列，且该两列子像素1中，任意同行的两个子像素1分别为蓝色和红色)，每个测试单元22包括第一测试晶体管220a、第二测试晶体管220b、第三测试晶体管220c、第四测试晶体管220d、第五测试晶体管220e和第六测试晶体管220f，其中，第一测试晶体管220a和第二测试晶体管220b的漏极连接一列红色和蓝色混排的子像素1，第四测试晶体管220d和第五测试晶体管220e的漏极连接另一列红色和蓝色混排的子像素1，第三测试晶体管220c的漏极连接一列绿色的子像素1，第六测试晶体管220f的漏极连接另一列绿色的子像素1，第一测试晶体管220a和第四测试晶体管220d的源极连接第一测试数据信号线CTDR，第二测试晶体管220b和第五测试晶体管220e的源极连接第二测试数据信号线CTDB，第三测试晶体管220c和第六测试晶体管220f的源极连接第三测试数据信号线CTDG，第一测试晶体管220a和第五测试晶体管220e的栅极连接第三测试控制信号线SWBR，第二测试晶体管220b和第四测试晶体管220d的栅极连接第二测试控制信号线SWRB；第 三测试晶体管220c和第六测试晶体管220f的栅极连接第一测试控制信号线SWG。
通过以上设置可见，通过轮流向第二测试控制信号线SWRB和第三测试控制信号线SWBR提供导通信号，即可使第一测试数据信号线CTDR和第二测试数据信号线CTDB分别控制蓝色和红色的子像素1，而第一测试控制信号线SWG和第三测试数据信号线CTDG则控制所有绿色的子像素1，以实现同种颜色的子像素1显示相同亮度。
参照图10，每4列子像素1中，两列子像素1可以为绿色，剩余两列子像素1的每一列中，红色和蓝色的子像素1交替排列，且该两列子像素1中，任意同行的两个子像素1分别为蓝色和红色。
在一种示例性实施例中，如图12所示，测试引脚区32的各个引脚(包括测试引脚325、第一测试电源引脚321以及第二测试电源引脚322)的形状为正方形，且相邻引脚的中心点之间的间距a大于预设第一间距，每个引脚的宽度b大于预设第二宽度。
本公开实施例中，测试引脚区32可以通过压接方式或扎针方式进行单元测试。
在一种示例性实施例中，当使用扎针方式进行单元测试时，相邻引脚的中心点之间的间距在500到1200微米之间，所述每个引脚的宽度在200到800微米之间。
在另一种示例性实施例中，当使用压接方式进行单元测试时，相邻引脚的中心点之间的间距在150到300微米之间，所述每个引脚的宽度在100到220微米之间。
扎针方式与压接方式相比，扎针方式所需的测试引脚区宽度较大，在空间允许的情况下，可以使用扎针方式进行单元测试。
在一种示例性实施例中，基底100为刚性基底或柔性基底。
在一种示例性实施例中，第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322均与第一源漏金属层900同 层设置；第一连接线303和第一测试电源引线323与第一栅金属层500同层设置，第一绑定电源引线313、第二绑定电源引线314、第二连接线304和第二测试电源引线324均与第一源漏金属层900同层设置；
第一连接线303通过第三绝缘层600和第四绝缘层800上的过孔与第一绑定电源引线313连接，第一测试电源引脚321通过第三绝缘层600和第四绝缘层800上的过孔与第一测试电源引线323连接。
在一种示例性实施例中，在垂直于显示基板的平面内，显示基板包括基底100以及在基底100上叠设的第一绝缘层200、有源层300、第二绝缘层400、第一栅金属层500、第三绝缘层600、第二栅金属层700、第四绝缘层800、第一源漏金属层900、第五绝缘层、第一平坦层和阳极层；测试引脚区32包括第一测试电源连接电极和第二测试电源连接电极，电路板引脚区31包括第一绑定电源连接电极、第二绑定电源连接电极，第一测试电源连接电极、第二测试电源连接电极、第一绑定电源连接电极、第二绑定电源连接电极与阳极层同层设置。
第一绑定电源引脚311、第二绑定电源引脚312、第一测试电源引脚321和第二测试电源引脚322均与第一源漏金属层900同层设置，第一绑定电源连接电极通过第一连接电极与第一绑定电源引脚311连接，第二绑定电源连接电极通过第二连接电极与第二绑定电源引脚312连接，第一测试电源连接电极通过第三连接电极与第一测试电源引脚321连接，第二测试电源连接电极通过第四连接电极与第二测试电源引脚322连接；第一连接线303与第一栅金属层500同层设置，第一绑定电源引线313、第二绑定电源引线314、第二连接线304、第一测试电源引线323和第二测试电源引线324均与第一源漏金属层900同层设置。第一连接线303通过第四绝缘层800上的过孔分别与第一绑定电源引线313和第一测试电源引线323连接。
在一种示例性实施例中，如图12所示，第一绑定电源引脚311包括第一子引脚3111和第二子引脚3112，第二绑定电源引脚312包括第三子引脚3121和第四子引脚3122，所述第三子引脚3121位于第一子引脚3111远离第二子引脚3112的一侧，第四子引脚3122位于第二子引脚3112远离第一子引脚3111的一侧。
在一种示例性实施例中，如图12所示，测试电源引脚包括第一测试电源引脚321和第二测试电源引脚322，第一测试电源引脚321包括第五子引脚3211和第六子引脚3212，第二测试电源引脚322包括第七子引脚3221和第八子引脚3222，第七子引脚3221位于第五子引脚3211远离电路板引脚区31的一侧，第八子引脚3222位于第六子引脚3212远离电路板引脚区31的一侧。
在一种示例性实施例中，如图12所示，测试引脚区32还包括至少一个第一测试引脚3251和至少一个第二测试引脚3252，第一测试引脚3251位于第七子引脚3221远离电路板引脚区31的一侧，第二测试引脚3252位于第八子引脚3222远离电路板引脚区31的一侧。
本公开实施例的显示基板是用于显示装置中的基板，例如是设有薄膜晶体管(TFT)阵列的阵列基板。在示例性实施方式中，绑定区30还可以包括配置为消除静电的防静电电路、配置为阻隔水汽进入显示区10的隔离坝以及其它布线区，本公开在此不做限定。
在示例性实施方式中，电路板引脚区31还可以设置有其它引脚，本公开在此不做限定。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)在玻璃载板上制备基底100。在示例性实施方式中，基底100可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底100的制备。
在示例性实施方式中，基底100可以是硬质基底。
(2)在基底100上依次沉积第一绝缘薄膜和有源层薄膜，通过图案化工艺对有源层薄膜进行图案化处理，形成覆盖整个基底100的第一绝缘层200，以及设置在第一绝缘层200上的有源层300图案。本次图案化工艺后，电路板引脚区31和测试引脚区32包括设置在基底100上的第一绝缘层200。
(3)依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化处理，形成覆盖有源层图案的第二绝缘层400，以及设置在第二绝缘层400上的第一栅金属层500图案，第一栅金属层500图案至少包括第一栅电极、第一电容电极和测试信号线，第一栅电极和第一电容电极形成在显示区10，测试信号线形成在测试引脚区32。
(4)依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化处理，形成覆盖第一栅金属层500的第三绝缘层600，以及设置在第三绝缘层600上的第二栅金属层700图案，第二栅金属层700图案至少包括第二电容电极和第一连接线303，第三电容电极形成在显示区10，第二电容电极的位置与第一电容电极的位置相对应，第一连接线303形成在 周边区30。第一连接线303配置为连接后续形成的第一绑定电源引线313与第一测试电源引线323，使得第一绑定电源引线313与第一测试电源引线323同时通过第一连接线303实现连接，保证信号的传输。
(5)沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化处理，形成覆盖第二栅金属层700的第四绝缘层800图案，第四绝缘层800上开设有多个过孔，多个过孔至少包括两个第一有源过孔和两个第一过孔。
在示例性实施方式中，两个第一有源过孔形成在显示区10，两个第一有源过孔内的第四绝缘层800、第三绝缘层600和第二绝缘层400被刻蚀掉，暴露出第一有源层的表面。
在示例性实施方式中，两个第一过孔形成在周边区30，第一过孔内的第四绝缘层800被刻蚀掉，暴露出第一连接线303的表面。
在示例性实施方式中，两个第一有源过孔配置为使后续形成的第一源电极和第一漏电极分别与第一有源层连接。两个第一过孔配置为使后续形成的第一绑定电源引线313与第一测试电源线分别与第一连接线303连接，从而实现第一测试电源引脚321与第一电源线之间的连接。
(6)沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化处理，在第四绝缘层800上形成第一源漏金属层900图案，第一源漏金属层900至少包括第一源电极、第一漏电极、第一绑定电源引脚311、第二绑定电源引脚312、第一绑定电源引线313、第二绑定电源引线314、第一电源线411、第二电源线412、第一测试电源引脚321、第二测试电源引脚322、第一测试电源引线323、第二测试电源引线324、第二连接线304，如图3B、图4和图5所示。
第一源电极和第一漏电极形成在显示区10，分别通过第一有源过孔与第一有源层连接。第一电源线411形成在显示区10，第二电源线412形成在周边区30，第一电源线411从显示区10延伸至周边区30并与第一绑定电源引线313连接，第二电源线412与第二绑定电源引线314连接。
第一绑定电源引脚311、第二绑定电源引脚312、第一绑定电源引线313、第二绑定电源引线314形成在电路板引脚区31，第一绑定电源引脚311与第 一绑定电源引线313可以为一体结构，第二绑定电源引脚312与第二绑定电源引线314可以为一体结构。第一绑定电源引线313通过第一过孔与第一测试电源引线323连接。
第一测试电源引脚321、第二测试电源引脚322、第一测试电源引线323、第二测试电源引线324形成在测试引脚区32，第一测试电源引脚321与第一测试电源引线323可以为一体结构，第二绑定电源引线314通过第二连接线304与第二测试电源引线324连接。第二测试电源引脚322、第二测试电源引线324和第二连接线304可以为一体结构。
(7)在形成前述图案的基底100上，先沉积一层第五绝缘薄膜，后涂覆一层有机材料的第一平坦薄膜，形成覆盖整个基底100的第五绝缘层和设置在第五绝缘层上的第一平坦(PLN)层，通过掩膜、曝光、显影的图案化工艺，在第一平坦层上形成有阳极过孔，阳极过孔形成在显示区10，阳极过孔内的第一平坦层和第五绝缘层被去掉，暴露出第一晶体管的第一漏电极的表面。在示例性实施方式中，第五绝缘层和第一平坦层称为复合绝缘层。
在示例性实施方式中，复合绝缘层可以只包括第五绝缘层，或者只包括第一平坦层。对于复合绝缘层只包括第一平坦层情况，可以在形成前述图案的基底100上直接形成第一平坦层，第一平坦层可以形成在电路板引脚区31和测试引脚区32。
至此，在基底100上制备完成驱动结构层图案。在显示区10，第一有源层、第一栅电极、第一源电极和第一漏电极组成像素驱动电路中的驱动晶体管，第一电容电极和第二电容电极组成像素驱动电路中的存储电容。
在示例性实施方式中，显示基板还包括形成在显示区10的阳极、像素定义(PDL)层、隔垫柱(PS)、有机发光层、阴极和封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层采用无机材料，第二封装层采用有机材料。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘 层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，本公开示例性实施例通过在测试引脚区设置第一测试电源引脚和第二测试电源引脚，使得显示基板点灯测试时不会损伤电路板引脚区的第一绑定电源引脚和第二绑定电源引脚，提高了信号输入的可靠性。
本公开示例性实施例显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
图13为本公开示例性实施例电路板引脚区和测试引脚区的平面示意图。如图13所示，电路板引脚区31包括第一绑定电源引脚311、第二绑定电源引脚312、与第一绑定电源引脚311连接的第一绑定电源引线313以及与第二绑定电源引脚312连接的第二绑定电源引线314，第一电源线411与第一绑定电源引线313连接，第二电源线412与第二绑定电源引线314连接。测试引脚区32包括第一测试电源引脚321、第二测试电源引脚322、与第一测试电源引脚321连接的第一测试电源引线323以及与第二测试电源引脚322连接的第二测试电源引线324，测试引脚区32还包括多个测试引脚325以及多根与测试引脚325一一对应连接的测试连接线326，测试引脚325和测试连接线326与第一源漏金属层900同层设置。第一连接线303电连接第一绑定电源引线313和第一测试电源引线323。
本公开还提供了一种显示基板的制备方法，显示基板包括显示区以及环 绕显示区的周边区，周边区包括位于显示区一侧的电路板引脚区和测试引脚区，显示区包括第一电源线和多个子像素，周边区包括第二电源线，电路板引脚区包括至少一个第一绑定电源引脚及至少一个第二绑定电源引脚，测试引脚区包括至少一个测试电源引脚。在示例性实施方式中，所述制备方法包括：
在基底上依次形成第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层和第二栅金属层；
在第二栅金属层上形成第四绝缘层；
在第四绝缘层上形成第一源漏金属层、第一电源线、第二电源线、第一绑定电源引脚、第二绑定电源引脚和测试电源引脚；第一电源线与第一绑定电源引脚电连接，第二电源线与第二绑定电源引脚电连接，测试电源引脚与第一电源线和第二电源线中的至少一个电连接。
在示例性实施方式中，测试电源引脚包括第一测试电源引脚和第二测试电源引脚，第一测试电源引脚电连接第一电源线，第二测试电源引脚电连接第二电源线。
在示例性实施方式中，所述制备方法还包括：
在第二绝缘层或第三绝缘层上形成第一连接线，第一连接线与第一栅金属层或第二栅金属层同层设置；
在第四绝缘层上形成第一测试电源引线和第二测试电源引线，第一测试电源引线和第二测试电源引线与第一源漏金属层同层设置，第一测试电源引线与第一连接线和第一测试电源引脚电连接，第一测试电源引脚通过第一连接线与第一绑定电源引线电连接，第二测试电源引线与第二绑定电源引线和第二测试电源引脚电连接。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。 在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区至少一侧的电路板引脚区和测试引脚区；所述显示基板包括：
    多个子像素，位于所述显示区；
    第一电源线，位于所述显示区，且与所述多个子像素电连接；
    至少一个第一绑定电源引脚，位于所述电路板引脚区，与所述第一电源线电连接，被配置为在显示阶段向所述多个子像素传输第一电源信号；
    第二电源线，位于所述周边区且围绕所述显示区；
    至少一个第二绑定电源引脚，位于所述电路板引脚区，与所述第二电源线电连接，被配置为在显示阶段向所述多个子像素传输第二电源信号；
    至少一个测试电源引脚，位于所述测试引脚区，电连接至所述第一电源线和所述第二电源线中的至少一个，所述至少一个测试电源引脚被配置为在测试阶段向所述多个子像素传输所述第一电源信号和所述第二电源信号中的至少之一。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚电连接所述第一电源线，所述第二测试电源引脚电连接所述第二电源线。
  3. 根据权利要求2所述的显示基板，其中，所述第二测试电源引脚位于所述第一测试电源引脚靠近所述显示区的一侧。
  4. 根据权利要求2所述的显示基板，其中，所述显示基板还包括第一绑定电源引线和第二绑定电源引线，所述第一绑定电源引线电连接所述第一电源线和所述第一绑定电源引脚，所述第二绑定电源引线电连接第二电源线和第二绑定电源引脚；
    所述显示基板还包括第一连接线和第二连接线，所述第一测试电源引脚通过所述第一连接线与所述第一绑定电源引线电连接，所述第二测试电源引 脚通过所述第二连接线与所述第二绑定电源引线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板还包括第一测试电源引线和第二测试电源引线，所述第一测试电源引线沿第一方向延伸，所述第二测试电源引线沿第一方向延伸，所述第一连接线沿第二方向延伸，所述第二连接线沿第二方向延伸，所述第一方向和所述第二方向交叉；
    所述第一测试电源引线与所述第一连接线和所述第一测试电源引脚电连接，所述第二测试电源引线与所述第二连接线和所述第二测试电源引脚电连接。
  6. 根据权利要求4所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
    至少部分所述第一连接线与所述第一栅金属层、所述第二栅金属层或所述第一源漏金属层中的至少一层同层设置。
  7. 根据权利要求6所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
    所述第一连接线包括第一子连接线和第二子连接线，所述第一子连接线与所述第一栅金属层同层设置，所述第二子连接线与所述第二栅金属层同层设置，且所述第一子连接线和所述第二子连接线并联且电连接，所述第一子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠，所述第二子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠；或，
    所述第一连接线包括第一子连接线和第三子连接线，所述第一子连接线和所述第三子连接线电连接，且所述第一子连接线与所述第一绑定电源引线、第二绑定电源引线至少部分交叠，所述第三子连接线与所述第一绑定电源引线、第二绑定电源引线不交叠，所述第一子连接线与所述第一栅金属层同层 设置，所述第三子连接线与所述第一源漏金属层同层设置。
  8. 根据权利要求6所述的显示基板，其中，所述基底为刚性基底或柔性基底。
  9. 根据权利要求2至8任一项所述的显示基板，其中，所述第一测试电源引脚包括第一子层和第二子层，所述第一子层和所述第二子层电连接。
  10. 根据权利要求9所述的显示基板，其中，所述第二测试电源引脚包括第三子层和第四子层，所述第三子层和所述第四子层电连接。
  11. 根据权利要求10所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括基底以及在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层；
    所述第一子层和所述第三子层与所述第一源漏金属层同层设置，所述第二子层和所述第四子层与所述第一栅金属层同层设置。
  12. 根据权利要求1所述的显示基板，其中，所述第一绑定电源引脚包括第一子引脚和第二子引脚，所述第二绑定电源引脚包括第三子引脚和第四子引脚，所述第三子引脚位于所述第一子引脚远离所述第二子引脚的一侧，所述第四子引脚位于所述第二子引脚远离所述第一子引脚的一侧。
  13. 根据权利要求1所述的显示基板，其中，所述测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚包括第五子引脚和第六子引脚，所述第二测试电源引脚包括第七子引脚和第八子引脚，所述第七子引脚位于所述第五子引脚远离所述电路板引脚区的一侧，所述第八子引脚位于所述第六子引脚远离所述电路板引脚区的一侧。
  14. 根据权利要求13所述的显示基板，其中，所述测试引脚区还包括至少一个第一测试引脚和至少一个第二测试引脚，所述第一测试引脚位于所述第七子引脚远离所述电路板引脚区的一侧，所述第二测试引脚位于所述第八子引脚远离所述电路板引脚区的一侧。
  15. 根据权利要求1所述的显示基板，其中，所述显示基板还包括第一 电源总线，所述第一电源总线位于所述显示区靠近所述电路板引脚区的一侧，所述第一电源总线电连接所述第一绑定电源引脚与所述第一电源线。
  16. 根据权利要求1至15任一所述的显示基板，其中，所述显示基板还包括多个测试单元、至少一条测试数据信号线和至少一条测试控制信号线，所述多个测试单元中的至少一个与多条数据线中的至少一条、所述至少一条测试数据信号线和所述至少一条测试控制信号线电连接，并被配置为根据所述至少一条测试控制信号线传输的信号将所述至少一条测试数据信号线传输的信号传递给至少一条数据线。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，所述显示基板包括显示区和围绕所述显示区的周边区，所述周边区包括位于所述显示区一侧的电路板引脚区和测试引脚区，所述显示区包括第一电源线和多个子像素，所述周边区包括第二电源线，所述电路板引脚区包括至少一个第一绑定电源引脚及至少一个第二绑定电源引脚，所述测试引脚区包括至少一个测试电源引脚，所述制备方法包括：
    在基底上依次形成第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层和第二栅金属层；
    在所述第二栅金属层上形成第四绝缘层；
    在所述第四绝缘层上形成第一源漏金属层、所述第一电源线、所述第二电源线、所述第一绑定电源引脚、所述第二绑定电源引脚和至少一个所述测试电源引脚；所述第一电源线与所述第一绑定电源引脚电连接，所述第二电源线与所述第二绑定电源引脚电连接，至少一个所述测试电源引脚与所述第一电源线和所述第二电源线中的至少一个电连接。
  19. 根据权利要求18所述的制备方法，其中，至少一个所述测试电源引脚包括第一测试电源引脚和第二测试电源引脚，所述第一测试电源引脚电连接所述第一电源线，所述第二测试电源引脚电连接所述第二电源线。
  20. 根据权利要求18所述的制备方法，其中，所述方法还包括：
    在所述第二绝缘层或第三绝缘层上形成第一连接线，所述第一连接线与所述第一栅金属层或所述第二栅金属层同层设置；
    在所述第四绝缘层上形成第一测试电源引线和第二测试电源引线，所述第一测试电源引线和第二测试电源引线与所述第一源漏金属层同层设置，所述第一测试电源引线与所述第一连接线和所述第一测试电源引脚电连接，所述第一测试电源引脚通过所述第一连接线与所述第一绑定电源引线电连接，所述第二测试电源引线与所述第二绑定电源引线和所述第二测试电源引脚电连接。
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