WO2023060581A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023060581A1
WO2023060581A1 PCT/CN2021/124177 CN2021124177W WO2023060581A1 WO 2023060581 A1 WO2023060581 A1 WO 2023060581A1 CN 2021124177 W CN2021124177 W CN 2021124177W WO 2023060581 A1 WO2023060581 A1 WO 2023060581A1
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WIPO (PCT)
Prior art keywords
metal layer
area
layer
wiring
source
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PCT/CN2021/124177
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English (en)
French (fr)
Inventor
张顺
张元其
何帆
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/124177 priority Critical patent/WO2023060581A1/zh
Priority to CN202180002937.0A priority patent/CN116264846A/zh
Publication of WO2023060581A1 publication Critical patent/WO2023060581A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, especially to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • An embodiment of the present disclosure provides a display substrate.
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a source-drain metal layer on a base, an insulating layer on the source-drain metal layer, and an insulating layer on the source-drain metal layer.
  • the touch metal layer on the insulating layer, the source-drain metal layer includes a first wiring, the touch metal layer includes a second wiring, and the orthographic projection of the first wiring on the substrate is the same as that of the second wiring.
  • the orthographic projections of the two wirings on the substrate have overlapping areas, and the first wiring and the second wiring form a double-layer wiring structure.
  • the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, and the binding area includes a first fan-out area and a Binding pin area;
  • the first wiring includes a first power supply line
  • the second wiring includes a first auxiliary power supply line
  • the first power supply line is located in the frame area and the first fan-out area, and connects from the first fan-out area
  • the output area extends to the binding pin area
  • the first auxiliary power line is located in the frame area and the first fan-out area
  • the orthographic projection of the first power line on the substrate is consistent with the first auxiliary power line
  • the orthographic projection of the line on the base has an overlapping area;
  • the first power line and the first auxiliary power line are electrically connected through a groove or a via hole penetrating through the insulating layer.
  • the touch metal layer includes a first touch metal layer and a second touch metal layer
  • the first auxiliary power line is set on the same layer as the first touch metal layer; or,
  • the first auxiliary power line is set on the same layer as the second touch metal layer; or,
  • the first auxiliary power line includes a first sub-wire and a second sub-wire, the first sub-wire is set on the same layer as the first touch metal layer, and the second sub-wire is connected to the The second touch metal layer is set on the same layer.
  • the bezel area includes at least one isolation dam disposed around the display area;
  • the orthographic projection of the first auxiliary power line on the base does not overlap with the orthographic projection of the isolation dam on the base, and the distance between the first auxiliary power line and the display area is greater than that between the isolation dam and the display area. The distance of the area.
  • the bezel area includes at least one isolation dam disposed around the display area;
  • the orthographic projection of the first auxiliary power line on the base covers at least part of the orthographic projection of the isolation dam on the base.
  • the insulating layer includes an encapsulation structure layer, a buffer layer, and a touch insulating layer; the groove includes a first groove and a third groove, and the first groove runs through the touch The insulating layer and the buffer layer, the third groove penetrates through the packaging structure layer.
  • the orthographic projection of the first groove on the substrate covers the orthographic projection of the third groove on the substrate.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer;
  • the first power line is set on the same layer as the first source-drain metal layer; or,
  • the first power line is set on the same layer as the second source-drain metal layer; or,
  • the first power line includes a third sub-wire and a fourth sub-wire, the third sub-wire is set on the same layer as the first source-drain metal layer, and the fourth sub-wire is connected to the first
  • the two source-drain metal layers are arranged in the same layer.
  • the display substrate includes a display area, and a binding area located on one side of the display area, and the binding area sequentially includes a first fan-out area, a curved Folding area, driver chip area and binding pin area;
  • the first wiring includes a second power supply line
  • the second wiring includes a second auxiliary power supply line
  • the second power supply line is located in the display area and the first fan-out area, and connects from the first fan-out area
  • the outlet area extends to the binding pin area
  • the second auxiliary power line is located in the binding area and on the side of the bending area away from the display area, and the second power line is on the base
  • the second power line and the second auxiliary power line are electrically connected through a groove or a via hole penetrating through the insulating layer.
  • the touch metal layer includes a first touch metal layer and a second touch metal layer
  • the second auxiliary power line is set on the same layer as the first touch metal layer; or,
  • the second auxiliary power line is set on the same layer as the second touch metal layer; or,
  • the second auxiliary power line includes a fifth sub-wire and a sixth sub-wire, the fifth sub-wire is set on the same layer as the first touch metal layer, and the sixth sub-wire is connected to the The second touch metal layer is set on the same layer.
  • the second power cord in the binding area, includes a first lateral connection portion extending along a first direction and a first vertical connection portion extending along a second direction;
  • the second auxiliary The power cord includes a second transverse connecting portion extending along the first direction and a second longitudinal connecting portion extending along the second direction;
  • Both the first lateral connection part and the second lateral connection part are arranged between the bending area and the driver chip area, and the orthographic projection of the first lateral connection part on the substrate is identical to the second lateral connection part.
  • the orthographic projection of the portion on the base has an overlapping area; the orthographic projection of the first longitudinal connecting portion on the base and the orthographic projection of the second longitudinal connecting portion on the base have an overlapping area.
  • the first longitudinal connection portion includes a plurality of first branches and a plurality of second branches, the first branches extending from an end portion of the first transverse connection portion in the first direction to the binding pin area, the second branch extends from the first transverse connection to the display area, and the second longitudinal connection extends from the second transverse connection along the first direction
  • the end portion of the first branch extends to the binding pin area, and there is an overlapping area between the orthographic projection of the first branch on the base and the orthographic projection of the second longitudinal connection portion on the base.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer;
  • the second power line is set on the same layer as the first source-drain metal layer; or,
  • the second power line is set on the same layer as the second source-drain metal layer; or,
  • the second power line includes a seventh sub-wire and an eighth sub-wire, the seventh sub-wire is set on the same layer as the first source-drain metal layer, the eighth sub-wire is connected to the first The two source-drain metal layers are arranged in the same layer.
  • the display substrate includes a display area, a binding area located on one side of the display area, the binding area includes a driving chip area and a binding pin area, and a binding area located between the driving chip area and Input and output wiring between the binding pin areas;
  • the driver chip area includes driver chip pins, the binding pin area includes binding pins, and the input and output wiring is connected to the driver chip pins and the bound pins;
  • the first wiring includes a first input and output wiring
  • the second wiring includes a second input and output wiring
  • the orthographic projection of the first input and output wiring on the substrate is the same as that of the second input and output wiring.
  • the orthographic projections of the lines onto the base have overlapping regions.
  • the touch metal layer includes a first touch metal layer and a second touch metal layer
  • the second input and output wiring is set on the same layer as the first touch metal layer; or,
  • the second input and output wiring is set on the same layer as the second touch metal layer; or,
  • the second input and output wiring includes a ninth sub-wiring and a tenth sub-wiring, the ninth sub-wiring is set on the same layer as the first touch metal layer, and the tenth sub-wiring is connected to the first touch metal layer.
  • the second touch metal layer is set on the same layer.
  • an insulating layer is included between the source-drain metal layer and the touch metal layer, and the first input-output wiring and the second input-output wiring pass through a groove or a pass through the insulating layer. hole electrical connection.
  • an insulating layer is included between the source-drain metal layer and the touch metal layer, and the first input-output wiring and the second input-output wiring are isolated by the insulating layer and passed through the The pins of the driving chip are electrically connected to the binding pins.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer;
  • the first input and output wiring is set on the same layer as the first source-drain metal layer; or,
  • the first input and output wiring is set on the same layer as the second source-drain metal layer; or,
  • the first input and output wiring includes an eleventh sub-wiring and a twelfth sub-wiring, the eleventh sub-wiring is set on the same layer as the first source-drain metal layer, and the twelfth sub-wiring The wiring is set on the same layer as the second source-drain metal layer.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described in any one of the preceding items.
  • An embodiment of the present disclosure also provides a method for preparing a display substrate, including:
  • the source-drain metal layer includes a first wiring
  • a touch metal layer is formed on the insulating layer, the touch metal layer includes a second wiring, the orthographic projection of the first wiring on the substrate and the orthographic projection of the second wiring on the substrate exist In the overlapping area, the first wiring and the second wiring form a double-layer wiring structure.
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic structural view of a display substrate
  • FIG. 3 is a schematic structural view showing a binding region and a frame region in a substrate
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a working timing diagram of a pixel driving circuit
  • Fig. 7a is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • Fig. 7b to Fig. 7g are the cross-sectional views of A-A' region in Fig. 7a;
  • Fig. 7h to Fig. 7j are the sectional views of B-B' area in Fig. 7a;
  • Fig. 8a is a schematic diagram after forming a light emitting structure layer pattern according to an exemplary embodiment of the present disclosure
  • Fig. 8 b is the sectional view of A-A ' area among Fig. 8 a;
  • Fig. 8c is the sectional view of B-B' region among Fig. 8a;
  • FIG. 9 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a package structure layer pattern
  • Fig. 10a is a schematic diagram after forming a touch insulating layer pattern according to an exemplary embodiment of the present disclosure
  • Figure 10b is a cross-sectional view of A-A' area in Figure 10a;
  • Fig. 10c is a sectional view of B-B' region among Fig. 10a;
  • Fig. 11a is a schematic diagram of patterning the encapsulation structure layer in the first groove according to an exemplary embodiment of the present disclosure
  • Fig. 11b is a cross-sectional view of A-A' region in Fig. 11a;
  • FIG. 12a is a schematic plan view of a touch electrode and a touch lead after forming a second touch metal layer pattern according to an exemplary embodiment of the present disclosure
  • Figure 12b is a cross-sectional view of the D-D' region in Figure 12a;
  • FIG. 12c and FIG. 12d are structural schematic diagrams of the first groove and the second groove region after forming the second touch metal layer pattern according to an exemplary embodiment of the present disclosure
  • Fig. 13a is a schematic plan view showing the binding pin area and the driver chip pin area in the substrate according to an exemplary embodiment of the present disclosure
  • Figures 13b to 13e are cross-sectional views of the region C-C' in Figure 13a.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data signal driver, a scanning signal driver, a light emitting signal driver and a pixel array, the timing controller is connected to the data signal driver, the scanning signal driver and the light emitting signal driver respectively, and the data signal driver They are respectively connected to a plurality of data signal lines (D1 to Dn), the scanning signal drivers are respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting signal drivers are respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scanning signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light emitting signal line and a pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver. To the scan signal driver, a clock signal suitable for the specification of the light emission signal driver, an emission stop signal, etc.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • the lighting signal driver may generate emission signals to be supplied to the lighting signal lines E1, E2, E3, . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission signal driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting signal driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 and a non-display area located around the display area 100
  • the non-display area may include a binding area 200 located on one side of the display area 100 and a border area located on the other side of the display area 100 300.
  • the display area 100 may include a plurality of sub-pixels arranged in a matrix, the sub-pixels may include pixel driving circuits and light emitting devices, and the bonding area 200 may at least include isolation dams and signal lines connecting the plurality of sub-pixels A bonding circuit connected to an external driving device, the frame area 300 may at least include an isolation dam, a gate driver on array (Gate Driver on Array, GOA for short) and a power line for transmitting voltage signals to multiple sub-pixels, the bonding area 200 and the frame
  • the isolation dams of the area 300 form a ring structure surrounding the display area 100 .
  • Fig. 3 is a schematic diagram showing the structure of the binding area and the border area in the substrate.
  • the binding area 200 in a plane parallel to the display substrate, can be located on one side of the display area 100 , and the binding area 200 can include sequentially along the direction away from the display area 100 .
  • the first fan-out area 211 , the bending area 212 , the second fan-out area 213 , the anti-static area 214 , the driving chip area 215 and the binding pin area 216 are provided.
  • the first fan-out area 211 may at least include a plurality of data connection lines, a plurality of touch control wires, a second power supply line and a first power supply line, and the plurality of data connection lines are arranged in a fan-out (Fanout) routing manner
  • a plurality of touch leads are configured as touch electrodes connected to the display area 100
  • a first power line (VSS) is configured as a low-voltage power line connected to the frame area 300
  • the second Two power lines (VDD) are configured as high voltage power lines connected to the display area 100 .
  • the bending area 212 may include a composite insulating layer provided with grooves, configured to bend the binding area 200 to the back of the display area 100 .
  • the second fan-out area 213 may include a plurality of data connection lines drawn out in a fan-out routing manner.
  • the antistatic area 214 may include an antistatic circuit configured to prevent static electricity damage of the display substrate by eliminating static electricity.
  • the driving chip area 215 may include an integrated circuit (Integrated Circuit, IC for short), which is configured to be connected to a plurality of data connection lines.
  • the bonding pin area 216 may include a plurality of bonding pads (Bonding Pads), which are configured to be bonded and connected to an external flexible circuit board (Flexible Printed Circuit, FPC for short).
  • the isolation dam may include a first isolation dam 410 and a second isolation dam 420, at least part of the first isolation dam 410 and the second isolation dam 420 may be disposed in the first fan-out region 211, and the first isolation The dam 410 and the second isolation dam 420 may extend along a direction parallel to the edge of the display area, the distance between the first isolation dam 410 and the edge of the display area is smaller than the distance between the second isolation dam 420 and the edge 110 of the display area, and the configuration is for encapsulation structure The organic layer in the layer is blocked to prevent the organic layer from flowing to the bending region.
  • the bezel area 300 may include a circuit area, an isolation dam area, and a crack dam area arranged in sequence along a direction away from the display area 100 .
  • the circuit area may at least include a gate driving circuit, and the gate driving circuit is connected to the first scanning line and the second scanning line of the pixel driving circuit in the display area 100 .
  • the isolation dam region may at least include a first power supply line, a first isolation dam 410 and a second isolation dam 420, the first power supply line may extend along a direction parallel to the edge of the display area, and the first power line of the pixel driving circuit in the display area 100.
  • the power line VSS is connected, the first isolation dam 410 and the second isolation dam 420 extend along a direction parallel to the edge of the display area, the first isolation dam 410 and the second isolation dam 420 of the frame area 300 are connected to the first isolation dam 420 of the binding area 200
  • the isolation dam 410 and the second isolation dam 420 are integral structures, and are manufactured synchronously through the same patterning process to form a ring structure surrounding the display area 100 .
  • the crack dam area includes a plurality of cracks arranged on the composite insulating layer, and the plurality of cracks are configured to reduce the stress on the display area 100 and the circuit area during the cutting process, and the cracks are transmitted to the display area 100 and the circuit area to avoid impact The film layer structure of the display area 100 and the circuit area.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • each sub-pixel in the display area may include a driving structure layer 501 disposed on the substrate 10, a light emitting structure layer 502 disposed on the side of the driving structure layer 501 away from the substrate, and The encapsulation structure layer 503 disposed on the side of the light emitting structure layer 502 away from the substrate.
  • the driving structure layer 501 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the driving structure layer 501 may include: a first insulating layer disposed on the substrate, a semiconductor layer disposed on the first insulating layer, a second insulating layer covering the semiconductor layer, disposed on the second insulating layer The first gate metal layer on the first gate metal layer, the third insulating layer covering the first gate metal layer, the second gate metal layer disposed on the third insulating layer, the fourth insulating layer covering the second gate metal layer, disposed on the fourth The source-drain metal layer on the insulating layer, and the planar layer covering the source-drain metal layer.
  • the semiconductor layer may include at least a plurality of transistors
  • the first gate metal layer may include at least the gate electrodes of the plurality of transistors and the first plate of the storage capacitor
  • the second gate metal layer may include at least the second plate of the storage capacitor
  • the source-drain metal layer may at least include first electrodes and second electrodes of a plurality of transistors.
  • the light-emitting structure layer 502 of each sub-pixel may include a light-emitting device composed of multiple film layers, and the multiple film layers may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24, and the anode 21 is connected to the pixel driving circuit, the organic light-emitting layer 23 is connected to the anode 21 , the cathode 24 is connected to the organic light-emitting layer 23 , and the organic light-emitting layer 23 emits light of a corresponding color under the drive of the anode 21 and the cathode 24 .
  • the encapsulation structure layer 503 may include a stacked first encapsulation layer 31, a second encapsulation layer 32 and a third encapsulation layer 33, the first encapsulation layer 31 and the third encapsulation layer 33 may be made of inorganic materials, and the second encapsulation layer 32 may be made of The organic material, the second encapsulation layer 32 is disposed between the first encapsulation layer 31 and the third encapsulation layer 33 , which can ensure that external water vapor cannot enter the light emitting structure layer 502 .
  • the display area may further include a touch structure layer
  • the touch structure layer may include: a buffer layer disposed on the third encapsulation layer, a first touch metal layer disposed on the buffer layer, covering the second A touch insulation layer of a touch metal layer, a second touch metal layer arranged on the touch insulation layer, and a touch protection layer covering the second touch metal layer.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 5, the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, Two scanning signal lines S2, light emitting signal lines E, initial signal lines INIT, first power supply lines VSS and second power supply lines VDD).
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the second power line VDD, the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3 Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the second power line VDD and the first power line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the second power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the second power line VDD and the first power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the second pole of the light emitting device is connected to the first power line VSS, the signal of the first power line VSS is a low level signal, and the signal of the second power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, and the initial signal line INIT extend along the horizontal direction
  • the first power line VSS, the second power line VDD, and the data signal line D extends in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 6 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 5.
  • the pixel driving circuit in FIG. signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, second power supply line VDD and first power supply line VSS), 7 transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the second power supply line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the second power line VDD.
  • Luminance uniformity is an index that characterizes the difference in luminance displayed in different areas of the panel under 255 gray scales, and is an important parameter for evaluating display quality.
  • the brightness uniformity is often evaluated by "9-point method” and "135-point method”. The closer to 1, the better the uniformity.
  • Brightness uniformity is positively correlated with the load (RC Loading) of the panel, the greater the load, the worse the uniformity.
  • AMOLED customers put forward more and more stringent requirements for LRU, and display products are developing towards larger sizes, and the panel load continues to increase. How to effectively reduce the panel load is particularly important.
  • the voltage (VSS) required by the pixel drive circuit in the display area 100 is introduced from the bonding pad of the bonding area 200, enters the frame area 300 after passing through the bonding area 200, and is delivered to each pixel through the ring-shaped power line of the frame area 300
  • the first power supply line VSS of the driving circuit Because there is a certain impedance in the power line, there is a voltage drop in the voltage signal transmission, so the voltage of the power line farther away from the binding area 200 will be lower than the voltage of the power line closer to the binding area 200, and the voltage loss of the power line is reduced.
  • the uniformity of display brightness in the display area has become an important factor affecting high-quality display.
  • the present disclosure provides a display substrate.
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a source-drain metal layer on the base, an insulating layer on the source-drain metal layer, and an insulating layer on the
  • the touch metal layer on the upper surface, the source and drain metal layer includes the first trace, the touch metal layer includes the second trace, the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the second trace on the substrate region, the first routing and the second routing form a double-layer routing structure.
  • the display substrate on a plane parallel to the display substrate, includes a display area 100, a binding area 200 located on one side of the display area 100, and a binding area located on the display area 100. frame area 300 on the other side;
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a source-drain metal layer on the substrate 10, an insulating layer on the source-drain metal layer, and a touch metal layer on the insulating layer.
  • the source-drain metal layer includes the first power supply Line VSS
  • the touch metal layer includes a first auxiliary power line 506, the first power line VSS is located in the frame area 300 and the first fan-out area, and extends from the first fan-out area 211 to the binding pin area 216, the first The auxiliary power line 506 is located in the frame area 300 and the first fan-out area 211, and the orthographic projection of the first power line VSS on the substrate 10 overlaps with the orthographic projection of the first auxiliary power line 506 on the substrate 10; the first power line VSS and the first auxiliary power line 506 are electrically connected through grooves or vias penetrating the insulating layer.
  • the first power line VSS and the first auxiliary power line 506 form a double-layer wiring structure, thereby reducing wiring resistance, further reducing panel loading, and improving panel uniformity.
  • the touch metal layer includes a first touch metal layer and a second touch metal layer
  • the first touch metal layer includes a connecting bridge 600
  • the second touch metal layer The metal layer includes a first electrode and a second electrode
  • the first electrode includes a plurality of first sub-electrodes 601 arranged along the first direction D1, and along the first direction D1, two adjacent first sub-electrodes 601 are connected to one
  • the bridge 600 is electrically connected through a via hole
  • the second electrode includes a plurality of second sub-electrodes 602 arranged along the second direction D2, and along the second direction D2, two adjacent second sub-electrodes 602 are connected to each other.
  • the first direction D1 and the second direction D2 intersect.
  • connection bridge 600 may also be disposed on the second touch metal layer, and the first electrode and the second electrode may be disposed on the first touch metal layer, which is not limited in the present disclosure.
  • the first electrode may be a driving electrode, and the second electrode may be a sensing electrode; or, the first electrode may be a sensing electrode, and the second electrode may be a driving electrode, which is not limited in the present disclosure.
  • both the first electrode and the second electrode are formed using a metal grid structure.
  • the patterns of the metal grids of the first electrode and the second electrode are the same.
  • the same pattern of the metal grid means that the metal traces of the metal grid have the same direction and the same line width.
  • the first electrode and the second electrode may be made of at least one of copper Cu, silver Ag, aluminum Al, titanium Ti or nickel Ni, which is not limited in this embodiment of the present disclosure.
  • the metal grid is used as the touch electrode.
  • the metal material has better ductility and is not easy to break, so the bending performance of the touch display substrate can be improved, so that The touch substrate is more suitable for realizing the flexible touch function, and can also reduce the cost.
  • the first electrode and the second electrode are set on the same layer and the same material, and have the same pattern, so that the substrate 10 is covered with metal grids with the same pattern, which can improve the elimination of interference caused by the mutual interference of different layers of metal grids due to differences in line width and the like. It has a good effect of eliminating shadows and optical moiré.
  • connection bridge 600 may be a metal grid structure, and the number of the connection bridge 600 is limited according to actual requirements, which is not limited in this embodiment of the present disclosure.
  • the metal grid is used as the connecting bridge.
  • the metal material has better ductility and is not easy to break, so the bending performance of the touch display substrate can be improved, so that the touch
  • the control substrate is more suitable for realizing the flexible touch function, and it can also reduce the cost and avoid the shadow disappearing problem of using solid metal.
  • the first auxiliary power line 506 is arranged on the same layer as the first touch metal layer, and an encapsulation structure is arranged between the first touch metal layer and the source-drain metal layer.
  • the layer 503 and the buffer layer 504 , the first power line VSS and the first auxiliary power line 506 are electrically connected through grooves or vias penetrating through the packaging structure layer 503 and the buffer layer 504 .
  • the packaging structure layer through which the groove or the via hole penetrates here includes the stacked first packaging layer and the third packaging layer.
  • the encapsulation layer is a laminated structure of inorganic material/inorganic material, excluding the second encapsulation layer.
  • the groove includes a fourth groove (not shown in the figure), and the fourth groove penetrates the buffer layer 504 and the packaging structure layer 503; or, the via hole includes a sixth via hole (not shown in the figure). out), the sixth via penetrates through the buffer layer 504 and the encapsulation structure layer 503 .
  • the frame area 300 includes a first isolation dam 410 and a second isolation dam 420, the first isolation dam 410 and the second isolation dam 420 are arranged around the display area 100, the first isolation dam 410 and the display area The distance of 100 is smaller than the distance between the second isolation dam 420 and the display area 100 .
  • the orthographic projection of the fourth groove (or the sixth via hole) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam and the second isolation dam on the substrate 10, and the fourth groove ( Or the distance between the sixth via hole) and the display area 100 is greater than the distance between the second isolation dam and the display area 100 .
  • the first auxiliary power line 506 is arranged on the same layer as the second touch metal layer, and an encapsulation structure is arranged between the second touch metal layer and the source-drain metal layer.
  • the layer 503 , the buffer layer 504 and the touch insulating layer 505 , the first power line VSS and the first auxiliary power line 506 are electrically connected through grooves or vias passing through the packaging structure layer 503 , the buffer layer 504 and the touch insulating layer 505 .
  • the grooves include a first groove (not shown in the figure) and a third groove (not shown in the figure), the first groove penetrates the touch insulating layer 505 and the buffer layer 504, the second groove Three grooves penetrate the encapsulation structure layer 503; or, the via holes include a third via hole (not shown in the figure) and a fifth via hole (not shown in the figure), and the third via hole penetrates the touch insulating layer 505 and the buffer Layer 504 , the fifth via penetrates through the packaging structure layer 503 .
  • the orthographic projection of the first groove on the substrate 10 covers the orthographic projection of the third groove on the substrate 10; or, the orthographic projection of the third via on the substrate 10 covers the orthographic projection of the fifth via on the substrate 10. Orthographic projection on substrate 10.
  • the orthographic projection of the first groove (or the third via hole) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10, and the first recess
  • the distance between the groove (or the third via hole) and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100 .
  • the first auxiliary power line 506 includes a first sub-wire 5061 and a second sub-wire 5062, and the first sub-wire 5061 and the first touch metal layer Set on the same layer, the second sub-wire 5062 is set on the same layer as the second touch metal layer, the packaging structure layer 503 and the buffer layer 504 are set between the first touch metal layer and the source-drain metal layer, the first touch metal layer A touch insulation layer 505 is arranged between the layer and the second touch metal layer, and the first power line VSS and the first sub-wire 5061 are electrically connected through a groove or a via hole penetrating through the packaging structure layer 503 and the buffer layer 504. The first sub-wire 5061 and the second sub-wire 5062 are electrically connected through a groove or a via hole penetrating through the touch insulating layer 505 .
  • the groove includes a fourth groove (not shown in the figure), and the fourth groove penetrates the buffer layer 504 and the packaging structure layer 503; or, the via hole includes a sixth via hole (not shown in the figure). out), the sixth via penetrates through the buffer layer 504 and the packaging structure layer 503;
  • the groove also includes a fifth groove (not shown in the figure), and the fifth groove penetrates through the touch insulating layer 505; or, the via hole includes a seventh via hole (not shown in the figure), and the seventh via hole penetrates the contact control insulating layer 505.
  • the orthographic projection of the fourth groove (or the sixth via hole) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10, and the fourth groove
  • the distance between the groove (or the sixth via hole) and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100;
  • the orthographic projection of the fifth groove (or the seventh via hole) on the substrate 10 does not overlap with the orthographic projections of the first isolation dam and the second isolation dam on the substrate 10, and the fifth groove (or the seventh via hole) and the The distance between the display area 100 is greater than the distance between the second isolation dam and the display area 100 .
  • the orthographic projection of the fourth groove on the substrate 10 covers the orthographic projection of the fifth groove on the substrate 10; or, the orthographic projection of the sixth via on the substrate 10 covers the orthographic projection of the seventh via on the substrate 10. Orthographic projection on substrate 10.
  • the orthographic projection of the first auxiliary power line 506 on the substrate 10 is different from the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10. Overlapping, the distance between the first auxiliary power line 506 and the display area 100 is greater than the distance between the second isolation dam 420 and the display area 100 .
  • the orthographic projection of the first auxiliary power line 506 on the substrate 10 covers the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate 10. .
  • the source-drain metal layer includes a single-layer source-drain metal layer.
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer (not shown in the figures).
  • the first power supply line VSS may be set on the same layer as the first source-drain metal layer; or,
  • the first power supply line VSS can be set on the same layer as the second source-drain metal layer; or,
  • the first power line VSS may include a third sub-wire and a fourth sub-wire, the third sub-wire is arranged on the same layer as the first source-drain metal layer, and the fourth sub-wire is arranged on the same layer as the second source-drain metal layer .
  • the present disclosure also provides a display substrate, as shown in FIG. 7a, FIG. 7h to FIG.
  • the binding area 200 on one side includes the first fan-out area 211 , the bending area 212 , the driving chip area 215 and the binding pin area 216 in sequence along the direction away from the display area 100 .
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a source-drain metal layer on the substrate 10, an insulating layer on the source-drain metal layer, and a touch metal layer on the insulating layer.
  • the source-drain metal layer includes a second power supply Line VDD
  • the touch metal layer includes a second auxiliary power line 507
  • the second power line VDD is located in the display area 100 and the first fan-out area 211, and extends from the first fan-out area 211 to the binding pin area 216
  • the second auxiliary power line 507 is located in the binding area 200 and on the side of the bending area 212 away from the display area 100 , the orthographic projection of the second power line VDD on the substrate 10 and the orthographic projection of the second auxiliary power line 507 on the substrate 10 There are overlapping areas;
  • the second power line VDD and the second auxiliary power line 507 are electrically connected through grooves or via holes penetrating the insulating layer.
  • the second power line VDD and the second auxiliary power line 507 form a double-layer wiring structure, thereby reducing wiring resistance, further reducing panel loading, and improving panel uniformity.
  • the display substrate can only use the first power line VSS and the first auxiliary power line 506 to form a double-layer wiring structure; in other exemplary embodiments, the display substrate can only use the second power line VDD and the second auxiliary power line 507 form a double-layer wiring structure; in some other exemplary embodiments, the display substrate can use the first power line VSS and the first auxiliary power line 506 to form a double-layer wiring structure, and The power line VDD and the second auxiliary power line 507 form a double-layer wiring structure, which is not limited in the present disclosure.
  • the second auxiliary power line 507 is provided on the same layer as the first touch metal layer, and a buffer layer 504 is provided between the first touch metal layer and the source-drain metal layer.
  • the second power line VDD and the second auxiliary power line 507 are electrically connected through a groove or a via hole penetrating the buffer layer 504 .
  • the second auxiliary power line 507 is arranged on the same layer as the second touch metal layer, and a buffer layer 504 and a touch pad are arranged between the second touch metal layer and the source-drain metal layer.
  • the control insulating layer 505 , the second power line VDD and the second auxiliary power line are electrically connected through grooves or vias penetrating through the buffer layer 504 and the touch insulating layer 505 .
  • the second auxiliary power line 507 includes a fifth sub-wire 5071 and a sixth sub-wire 5072, and the fifth sub-wire 5071 is set on the same layer as the first touch metal layer.
  • the sixth sub-wire 5072 is arranged on the same layer as the second touch metal layer
  • a buffer layer 504 is arranged between the first touch metal layer and the source-drain metal layer
  • the second power line VDD and the fifth sub-wire 5071 pass through
  • the groove or the via hole running through the buffer layer 504 is electrically connected
  • the touch insulating layer 505 is arranged between the second touch metal layer and the first touch metal layer
  • the fifth sub-wire 5071 and the sixth sub-wire 5072 pass through The groove or the via hole penetrating through the touch insulation layer 505 is electrically connected.
  • the second power line VDD includes a first lateral connection portion extending along the first direction D1 and a second connection portion extending along the second direction D2 .
  • An extended first vertical connection portion; the second auxiliary power cord 507 includes a second horizontal connection portion extending along the first direction D1 and a second vertical connection portion extending along the second direction D2;
  • Both the first lateral connection part and the second lateral connection part are arranged between the bending area 212 and the driver chip area 215, and the orthographic projection of the first lateral connection part on the substrate 10 is the same as the orthographic projection of the second lateral connection part on the substrate 10.
  • the projections have overlapping areas;
  • the first longitudinal connection part includes a plurality of first branches and a plurality of second branches, and the first branches extend from the end of the first transverse connection part along the first direction D1 to the binding pin area 216 , the second branch extends from the first transverse connection part to the display area, the second longitudinal connection part extends from the end of the second transverse connection part along the first direction D1 to the binding pin area 216, and the first branch is on the substrate 10 There is an overlapping area between the orthographic projection of and the orthographic projection of the second longitudinal connection portion on the substrate 10 .
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer;
  • the second power line VDD may be set on the same layer as the first source-drain metal layer; or,
  • the second power line VDD may be set on the same layer as the second source-drain metal layer; or,
  • the second power line VDD may include a seventh sub-wire and an eighth sub-wire, the seventh sub-wire is arranged on the same layer as the first source-drain metal layer, and the eighth sub-wire is arranged on the same layer as the second source-drain metal layer .
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of B's orthographic projection.
  • the display substrate includes a display area 100 and a non-display area located around the display area 100, and the non-display area may include a binding area 200 located on one side of the display area 100 and a frame area located on the other side of the display area 100 300.
  • the preparation process of the display substrate may include the following operations.
  • the driving structure layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines vertically intersect to define a plurality of pixel units arranged in a matrix, and each pixel unit includes at least 3
  • Each sub-pixel includes one or more thin film transistors (Thin Film Transistor, TFT).
  • TFT Thin Film Transistor
  • one pixel unit may include three sub-pixels, which are red sub-pixel R, green sub-pixel G and blue sub-pixel B, respectively.
  • the solution of this embodiment is also applicable to the case where one pixel unit includes 4 sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B and white sub-pixel W).
  • the preparation process of the driving structure layer may include:
  • a first insulating film and a semiconductor film are sequentially deposited on the substrate, and the semiconductor film is patterned by a patterning process to form a first insulating layer covering the entire substrate, and a semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern including at least a first active layer.
  • the second insulating film and the first metal film are deposited in sequence, and the first metal film is patterned by a patterning process to form a second insulating layer covering the pattern of the semiconductor layer, and a first gate disposed on the second insulating layer.
  • the metal layer pattern, the first gate metal layer pattern at least includes a first gate electrode and a first capacitor electrode.
  • a third insulating film and a second metal film are deposited in sequence, and the second metal film is patterned through a patterning process to form a third insulating layer covering the first gate metal layer, and a third insulating layer disposed on the third insulating layer.
  • Two gate metal layer patterns, the second gate metal layer pattern at least includes a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.
  • a fourth insulating film is deposited, and a plurality of first via hole patterns are formed through a patterning process.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole are etched away, exposing two ends of the first active layer.
  • the source-drain metal layer pattern may include: a first source electrode and a first drain electrode pole, the first power line VSS and the second power line VDD, the first power line VSS is located in the frame area and surrounds the display area, the second power line VDD is located in the display area, and is electrically connected to a plurality of sub-pixels, the first power line VSS and The second power line VDD is led to the bonding area and correspondingly connected to the corresponding bonding pin, and the first power line VSS and the second power line VDD are configured to be respectively connected to a low-voltage signal and a high-voltage signal.
  • the first source electrode and the first drain electrode are respectively connected to the first active layer through the first via hole.
  • the source-drain metal layer may also include a plurality of binding pins (FPC on Plastic Pad, FOP Pad) located in the binding pin area 216, and a plurality of driver chip pins located in the driver chip area 215.
  • multiple binding pins include at least the first binding power supply pin and the second binding power supply pin, the first binding power supply pin The pin is electrically connected to the first power supply line VSS, and the second binding power supply pin is electrically connected to the second power supply line VDD.
  • both the binding pins and the driving chip pins can be formed by multiple metal film layers, and the multiple metal film layers can include gate metal layers (the first gate metal layer and/or the second gate metal layer metal layer), source-drain metal layer, etc. (first source-drain metal layer and/or second source-drain metal layer).
  • the display substrate in the embodiments of the present disclosure is illustrated by taking the source-drain metal layer including only one layer structure as an example.
  • the source-drain metal layer may also include the first source-drain metal layer and the second source-drain metal layer.
  • the first power line VSS and the second power line VDD can be located in the first source-drain metal layer, or in the second source-drain metal layer, or in both the first source-drain metal layer and the second Two source-drain metal layers form double-layer wiring.
  • a flat film is coated, and the flat film is patterned through a patterning process to form a flat layer PLN, on which the second via hole, the partition and the first dam foundation pattern are formed.
  • the flat layer in the second via hole is removed, exposing the surface of the first drain electrode of the first transistor.
  • the flat layer in the partition is removed to expose the surface of the first power line VSS, and the first dam is formed on the first power line VSS in the partition.
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute a thin film transistor
  • the first capacitor electrode and the second capacitor electrode constitute a storage capacitor
  • the thin film transistor may have a bottom gate structure or a top gate structure, may be an amorphous silicon (a-Si) thin film transistor, may also be a low temperature polysilicon (LTPS) thin film transistor or an oxide (Oxide) thin film transistor, here No limit.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • the preparation process of the light emitting structure layer may include:
  • a transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form an anode pattern.
  • the anode of each sub-pixel is connected to the drain electrode of the thin film transistor in the sub-pixel through the second via hole on the flat layer.
  • a pixel-defining film is coated on the substrate on which the foregoing pattern is formed, and the pixel-defining film is patterned by a patterning process to form a pixel-defining (PDL) layer and a second dam foundation pattern.
  • PDL pixel-defining
  • the isolation dam may include a first isolation dam 410 and a second isolation dam 420 , and the distance between the first isolation dam 410 and the display area 100 is smaller than the distance between the second isolation dam 420 and the display area 100 .
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL), wherein the hole transport layer (HTL), light emitting layer (EML), electron transport layer (ETL) and electron injection layer (EIL) are sequentially disposed on the hole injection layer.
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EML emission layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the light-emitting structure layer pattern is prepared on the substrate, as shown in Figure 8a, Figure 8b and Figure 8c
  • Figure 8b is a cross-sectional view of the AA' area in Figure 8a
  • Figure 8c is a cross-sectional view of the BB' area in Figure 8a
  • 11 is a composite insulating layer, which may include a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the substrate 10 . Since the organic light emitting layer is connected to the anode, and the anode is connected to the drain electrode of the thin film transistor, the connection between the organic light emitting layer and the drain electrode of the thin film transistor is realized.
  • the encapsulation structure layer 503 includes the stacked first encapsulation layer, the second encapsulation layer and the third encapsulation layer, forming a laminated structure of inorganic materials/organic materials/inorganic materials.
  • the isolation dam area that is, the area where the first power line VSS is located
  • the packaging structure layer includes the stacked first packaging layer and the third packaging layer, forming a laminated structure of inorganic materials/inorganic materials, which can further ensure the integrity of the packaging. Effectively isolate the external water and oxygen.
  • the bonding area 200 has no encapsulation structure layer pattern.
  • the first encapsulation layer and the third encapsulation layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single Layer, multi-layer or composite layer can ensure that outside water and oxygen cannot enter the light-emitting structure layer.
  • the second encapsulation layer can use organic materials, such as resin, etc., to play the role of covering each film layer of the display substrate, so as to improve structural stability and flatness.
  • a buffer layer 504 and a first touch metal layer pattern are sequentially formed.
  • the material of the buffer layer 504 can be silicon oxide (SiOx), silicon nitride (SiNx) and Any one or more types of silicon oxynitride (SiON), the first touch metal layer may include a plurality of connecting bridges (not shown in the figure) arranged at intervals and first touch leads (not shown in the figure) )wait.
  • forming the first touch metal layer pattern may include: depositing a first conductive film on the substrate, coating a layer of photoresist on the first conductive film, and using a mask to process the photoresist. Expose and develop, form an unexposed area at the position of the connecting bridge and the touch lead pattern, retain the photoresist, form a fully exposed area at other positions, remove the photoresist, etch and peel off the conductive film in the fully exposed area The remaining photoresist forms the first touch metal layer pattern.
  • the first conductive film can be made of metal material, or can be made of transparent conductive material, such as indium tin oxide ITO, indium zinc oxide IZO, carbon nanotubes or graphene.
  • the touch insulation layer 505 may include an eighth via hole (not shown in the figure) and a ninth via hole (not shown in the figure), the eighth via hole Located at both ends of the connection bridge, the touch insulation layer in the eighth via hole is etched away, exposing both ends of the connection bridge, and the first sub-electrode for subsequent formation is electrically connected to the connection bridge through the via hole.
  • the ninth via hole is located in the area where the first touch wire is located, and the touch insulation layer in the ninth via hole is etched away to expose the first touch wire, which is used to connect the first touch wire with the subsequently formed second wire.
  • the touch leads form double-layer touch traces.
  • the touch insulating layer 505 may further include a first groove H1, the first groove H1 is located in the frame region 300 and the first fan-out region in the binding region 200, the first groove H1 is in the base
  • the orthographic projection on the substrate has an overlapping area with the orthographic projection of the first power line VSS on the substrate, the orthographic projection of the first groove H1 on the substrate, and the orthographic projection of the first isolation dam 410 and the second isolation dam 420 on the substrate The projections do not overlap, and the distance between the first groove H1 and the display area is greater than the distance between the second isolation dam 420 and the display area.
  • the touch insulation layer and the buffer layer in the first groove H1 are etched away, exposing the surface of the packaging structure layer (due to over-etching, a part of the packaging structure layer may be etched away).
  • the first groove H1 may also be replaced by a plurality of discontinuous third via holes (not shown in the figure), that is, the third via holes are located in the frame area 300 and the bonding area 200 In the first fan-out area, the orthographic projection of the third via hole on the substrate overlaps with the orthographic projection of the first power line VSS on the substrate, and the orthographic projection of the third via hole on the substrate overlaps with the first isolation dam
  • the orthographic projections of 410 and the second isolation dam 420 on the substrate do not overlap, and the distance between the third via hole and the display area is greater than the distance between the second isolation dam 420 and the display area.
  • the touch insulation layer and the buffer layer in the third via hole are etched away, exposing the surface of the packaging structure layer (due to over-etching, a part of the packaging structure layer may be etched away).
  • the touch insulating layer 505 may further include a second groove H2, the second groove H2 is located in the binding area 200, and the second groove H2 is located on the side of the bending area 212 away from the display area 100,
  • the orthographic projection of the second groove H2 on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate.
  • the touch insulation layer and buffer layer in the second groove H2 are etched away, exposing the first The surface of the second power supply line VDD.
  • the second groove H2 may also be replaced by a plurality of discontinuous fourth via holes (not shown in the figure), that is, the fourth via holes are located in the bonding area 200, and the fourth via holes The hole is located on the side of the bending area 212 away from the display area 100, the orthographic projection of the fourth via hole on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate, and the touch insulation in the fourth via hole layer and the buffer layer are etched away, exposing the surface of the second power line VDD.
  • the third groove H3 is formed on the packaging structure layer, the orthographic projection of the third groove H3 on the substrate is within the range of the orthographic projection of the first groove H1 on the substrate, and the third The encapsulation structure layer in the groove H3 is etched away, exposing the surface of the first power line VSS, as shown in FIG. 11a and FIG. 11b , and FIG. 11b is a cross-sectional view of the region AA' in FIG. 11a .
  • the third groove H3 may also be replaced by a plurality of discontinuous fifth via holes (not shown in the figure), that is, the fifth via holes are located in the frame area 300 and the bonding area 200 In the first fan-out area, the orthographic projection of the fifth via hole on the substrate is located within the range of the orthographic projection of the first groove H1 (or the third via hole) on the substrate, and the package in the fifth via hole
  • the structural layer is etched away, exposing the surface of the first power line VSS.
  • the second touch metal layer may include a first electrode, a second electrode and Patterns such as the second touch lead 603, the first electrode includes a plurality of first sub-electrodes 601 arranged along the first direction D1, two adjacent first sub-electrodes 601 and a connecting bridge 600 along the first direction D1 Electrically connected through the eighth via hole; the second electrode includes a plurality of second sub-electrodes 602 arranged along the second direction D2, and along the second direction D2, two adjacent second sub-electrodes 602 are connected to each other, the second electrode The first direction D1 and the second direction D2 intersect.
  • both the first direction D1 and the second direction D2 are perpendicular to the thickness direction of the encapsulation structure layer.
  • the embodiment of the present application does not limit the size of the angle included between the first direction D1 and the second direction D2, for example, the two may be perpendicular.
  • both the first sub-electrode 601 and the second sub-electrode 602 have a grid structure, at least one sub-pixel is arranged in the grid, and the materials of the first sub-electrode 601 and the second sub-electrode 602 are both metal materials . Due to the low resistance, good conductivity and high sensitivity of the metal material, transmission delay of electric signals in the first sub-electrode 601 and the second sub-electrode 602 can be avoided, and the touch effect can be improved.
  • the shape of the grid in the grid structure can be a regular polygon or an irregular polygon.
  • the second touch metal layer may further include a first auxiliary power line 506, the first auxiliary power line 506 is located in the frame area 300 and the first fan-out area in the binding area 200, the first auxiliary power line
  • the orthographic projection of line 506 on the substrate overlaps with the orthographic projection of the first power supply line VSS on the substrate, and the orthographic projection of the first auxiliary power supply line 506 on the substrate overlaps with the first isolation dam 410 and the second isolation dam 420
  • the orthographic projections on the substrate do not overlap, the distance between the first auxiliary power line 506 and the display area is greater than the distance between the second isolation dam 420 and the display area, and the first auxiliary power line 506 passes through the first groove H1 (or the third via hole ) and the third groove H3 (or the fifth via hole) are electrically connected to the first power line VSS.
  • the second touch metal layer may further include a second auxiliary power line 507, the second auxiliary power line 507 is located in the binding area 200, and the second auxiliary power line 507 is located in the bending area 212 away from the display area 100
  • the orthographic projection of the second auxiliary power line 507 on the substrate overlaps with the orthographic projection of the second power line VDD on the substrate, and the second auxiliary power line 507 passes through the second groove H2 and the second power line VDD electrical connection.
  • the protective layer can be made of polyimide (PI) or other materials, and it mainly plays a role of insulating and protecting the touch electrodes and peripheral wirings.
  • PI polyimide
  • the preparation process of the display substrate may also include processes such as peeling off the peel-off substrate, attaching a back film, cutting, etc., which are not limited in this disclosure.
  • the exemplary embodiment of the present disclosure makes the first power supply
  • the line VSS and the first auxiliary power line 506 form a double-layer wiring structure, which reduces the wiring resistance, thereby reducing panel loading and improving panel uniformity.
  • the second power line VDD and the second auxiliary power line 507 also form a double-layer wiring structure, which also reduces the wiring resistance. , thereby reducing panel loading and improving panel uniformity.
  • the exemplary embodiment of the present disclosure shows that the preparation process of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield rate.
  • the structure of the substrate shown in the exemplary embodiments of the present disclosure and the manufacturing process thereof are merely exemplary illustrations.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • Fig. 13a is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure
  • Fig. 13b to Fig. 13e are several cross-sectional views of the C-C' region in Fig. 13a.
  • the display substrate includes a display area, a binding area located on one side of the display area, the binding area includes a driver chip area 215 and a binding pin area 216, and a binding area located at the driver chip area 215 and the binding pin area
  • the driver chip area 215 includes the driver chip pin 2151
  • the binding pin area 216 includes the binding pin 2161, and the input and output wiring 217 connects the driver chip pin 2151 and the binding pin 2161;
  • the input and output wiring 217 includes a first input and output wiring 2171 and a second input and output wiring 2172.
  • the projections have overlapping areas;
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a source-drain metal layer and a touch metal layer on the substrate 10, the first input and output lines 2171 are arranged on the same layer as the source-drain metal layer, and the second input and output lines 2172 It is set on the same layer as the touch metal layer.
  • Exemplary embodiments of the present disclosure form a double-layer wiring structure through the first input and output wiring 2171 and the second input and output wiring 2172, thereby reducing wiring resistance, thereby reducing panel loading and improving panel uniformity. .
  • the second input and output wiring 2172 is arranged on the same layer as the first touch metal layer, and the first input and output wiring 2171 and the second input and output wiring 2172 pass through the buffer The grooves or vias of layer 504 are electrically connected.
  • the second input and output wiring 2172 is arranged on the same layer as the second touch metal layer, and the first input and output wiring 2171 and the second input and output wiring 2172 pass through
  • the buffer layer 504 is electrically connected to the groove or the via hole of the touch insulation layer 505 .
  • the second input and output wiring 2172 includes a ninth sub-wiring 21721 and a tenth sub-wiring 21722, and the ninth sub-wiring 21721 and the first touch metal layer Arranged on the same layer, the tenth sub-wire 21722 is arranged on the same layer as the second touch metal layer, the first input-output wire 2171 and the ninth sub-wire 21721 are electrically connected through a groove or a via hole penetrating the buffer layer 504 , the second The nine sub-wires 21721 and the tenth sub-wires 21722 are electrically connected through grooves or via holes penetrating the touch insulating layer 505 .
  • an insulating layer is included between the source-drain metal layer and the touch metal layer, and the first input and output wiring 2171 and the second input and output wiring 2172 are separated by the insulating layer. And electrically connected through the driver chip pin 2151 and the binding pin 2161 . Since the driver chip pins 2151 and the binding pins 2161 have a touch metal layer, the first input and output wiring 2171 does not need to remove the flat layer PLN, the buffer layer 504, the touch insulating layer 505 and other films. layer, that is, the first input and output wiring 2171 and the second input and output wiring 2172 are isolated by an insulating layer, and are electrically connected through the driver chip pin 2151 and the binding pin 2161 .
  • the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer (not shown in the figure);
  • the first input and output wiring is arranged on the same layer as the first source-drain metal layer; or,
  • the first input and output lines are arranged on the same layer as the second source-drain metal layer; or,
  • the first input and output wiring includes the eleventh sub-wiring and the twelfth sub-wiring, the eleventh sub-wiring is set on the same layer as the first source-drain metal layer, and the twelfth sub-wiring and the second Layer same layer settings.
  • Exemplary embodiments of the present disclosure also provide a method for preparing a display substrate
  • the source-drain metal layer includes a first wiring
  • a touch metal layer is formed on the insulating layer, the touch metal layer includes a second wiring, the orthographic projection of the first wiring on the substrate and the orthographic projection of the second wiring on the substrate exist In the overlapping area, the first wiring and the second wiring form a double-layer wiring structure.
  • the source-drain metal layer including a first power line, the first power line is located in the frame area and the first fan-out area, and extends from the first fan-out area to the binding Fixed pin area;
  • a touch metal layer is formed on the insulating layer, the touch metal layer includes a first auxiliary power line, the first auxiliary power line is located in the frame area and the first fan-out area, and the first power line There is an overlapping area between the orthographic projection on the substrate and the orthographic projection of the first auxiliary power line on the substrate, and the first power line and the first auxiliary power line are electrically connected through the groove or the via hole.
  • the display substrate includes a display area, and a binding area located on one side of the display area, and the binding area sequentially includes a first fan-out area, a curved folding area, driver chip area and binding pin area; the preparation method includes:
  • the source-drain metal layer including a second power line, the second power line is located in the display area and the first fan-out area, and extends from the first fan-out area to the binding Fixed pin area;
  • a touch metal layer is formed on the insulating layer, the touch metal layer includes a second auxiliary power line, the second auxiliary power line is located in the binding area and is located in the bending area away from the display area
  • the orthographic projection of the second power line on the base overlaps with the orthographic projection of the second auxiliary power line on the base, and the second power line and the second auxiliary power line pass through the The grooves or vias are electrically connected.
  • the display substrate includes a display area, a binding area located on one side of the display area, the binding area includes a driver chip area and a binding pin area; the driver chip area includes a driver Chip pins, the binding pin area includes binding pins; the preparation method includes:
  • the source-drain metal layer includes a first input-output wiring, the first input-output wiring is located between the driver chip area and the bonding pin area, and the first input-output wiring Connect the driver chip pin and the binding pin with a wire;
  • a touch metal layer is formed on the insulating layer, the touch metal layer includes a second input and output wiring, and the orthographic projection of the first input and output wiring on the substrate is in line with the second input and output wiring. Orthographic projections on the base have overlapping regions.
  • Embodiments of the present disclosure also provide a display device, including the display panel of the foregoing embodiments.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，在垂直于显示基板的平面上，显示基板包括位于基底(10)上的源漏金属层、位于源漏金属层上的绝缘层以及位于绝缘层上的触控金属层，源漏金属层包括第一走线，触控金属层包括第二走线，第一走线在基底(10)上的正投影与第二走线在基底(10)上的正投影存在重叠区域；第一走线和第二走线形成双层走线结构。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，在垂直于所述显示基板的平面上，所述显示基板包括位于基底上的源漏金属层、位于所述源漏金属层上的绝缘层以及位于所述绝缘层上的触控金属层，所述源漏金属层包括第一走线，所述触控金属层包括第二走线，所述第一走线在基底上的正投影与所述第二走线在基底上的正投影存在重叠区域，所述第一走线和第二走线形成双层走线结构。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域以及位于所述显示区域其他侧的边框区域，所述绑定区域包括第一扇出区和绑定引脚区；
所述第一走线包括第一电源线，所述第二走线包括第一辅助电源线，所 述第一电源线位于所述边框区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区，所述第一辅助电源线位于所述边框区域和第一扇出区，所述第一电源线在基底上的正投影与所述第一辅助电源线在基底上的正投影存在重叠区域；
所述第一电源线和所述第一辅助电源线通过贯穿所述绝缘层的凹槽或过孔电连接。
在示例性实施例中，所述触控金属层包括第一触控金属层和第二触控金属层；
所述第一辅助电源线与所述第一触控金属层同层设置；或者，
所述第一辅助电源线与所述第二触控金属层同层设置；或者，
所述第一辅助电源线包括第一子走线和第二子走线，所述第一子走线与所述第一触控金属层同层设置，所述第二子走线与所述第二触控金属层同层设置。
在示例性实施例中，所述边框区域包括至少一个隔离坝，所述隔离坝围绕所述显示区域设置；
所述第一辅助电源线在基底上的正投影与所述隔离坝在基底上的正投影不重叠，所述第一辅助电源线与所述显示区域的距离大于所述隔离坝与所述显示区域的距离。
在示例性实施例中，所述边框区域包括至少一个隔离坝，所述隔离坝围绕所述显示区域设置；
所述第一辅助电源线在基底上的正投影至少覆盖部分所述隔离坝在基底上的正投影。
在示例性实施例中，所述绝缘层包括封装结构层、缓冲层和触控绝缘层；所述凹槽包括第一凹槽和第三凹槽，所述第一凹槽贯穿所述触控绝缘层和缓冲层，所述第三凹槽贯穿所述封装结构层。
在示例性实施例中，所述第一凹槽在基底上的正投影覆盖所述第三凹槽在基底上的正投影。
在示例性实施例中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
所述第一电源线与所述第一源漏金属层同层设置；或者，
所述第一电源线与所述第二源漏金属层同层设置；或者，
所述第一电源线包括第三子走线和第四子走线，所述第三子走线与所述第一源漏金属层同层设置，所述第四子走线与所述第二源漏金属层同层设置。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域沿远离所述显示区域的方向，依次包括第一扇出区、弯折区、驱动芯片区和绑定引脚区；
所述第一走线包括第二电源线，所述第二走线包括第二辅助电源线，所述第二电源线位于所述显示区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区，所述第二辅助电源线位于所述绑定区域且位于所述弯折区远离所述显示区域的一侧，所述第二电源线在基底上的正投影与所述第二辅助电源线在基底上的正投影存在重叠区域；
所述第二电源线和所述第二辅助电源线通过贯穿所述绝缘层的凹槽或过孔电连接。
在示例性实施例中，所述触控金属层包括第一触控金属层和第二触控金属层；
所述第二辅助电源线与所述第一触控金属层同层设置；或者，
所述第二辅助电源线与所述第二触控金属层同层设置；或者，
所述第二辅助电源线包括第五子走线和第六子走线，所述第五子走线与所述第一触控金属层同层设置，所述第六子走线与所述第二触控金属层同层设置。
在示例性实施例中，在所述绑定区域，所述第二电源线包括沿第一方向延伸的第一横向连接部和沿第二方向延伸的第一纵向连接部；所述第二辅助电源线包括沿所述第一方向延伸的第二横向连接部和沿所述第二方向延伸的第二纵向连接部；
所述第一横向连接部与第二横向连接部均设置在所述弯折区和所述驱动芯片区之间，所述第一横向连接部在基底上的正投影与所述第二横向连接部在基底上的正投影存在重叠区域；所述第一纵向连接部在基底上的正投影与所述第二纵向连接部在基底上的正投影存在重叠区域。
在示例性实施例中，所述第一纵向连接部包括多个第一分支和多个第二分支，所述第一分支从所述第一横向连接部沿所述第一方向的端部延伸至所述绑定引脚区，所述第二分支从所述第一横向连接部延伸至所述显示区，所述第二纵向连接部从所述第二横向连接部沿所述第一方向的端部延伸至所述绑定引脚区，所述第一分支在基底上的正投影与所述第二纵向连接部在基底上的正投影存在重叠区域。
在示例性实施例中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
所述第二电源线与所述第一源漏金属层同层设置；或者，
所述第二电源线与所述第二源漏金属层同层设置；或者，
所述第二电源线包括第七子走线和第八子走线，所述第七子走线与所述第一源漏金属层同层设置，所述第八子走线与所述第二源漏金属层同层设置。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域包括驱动芯片区和绑定引脚区以及位于所述驱动芯片区和所述绑定引脚区之间的输入输出走线；所述驱动芯片区包括驱动芯片引脚，所述绑定引脚区包括绑定引脚，所述输入输出走线连接所述驱动芯片引脚和所述绑定引脚；
所述第一走线包括第一输入输出走线，所述第二走线包括第二输入输出走线，所述第一输入输出走线在基底上的正投影与所述第二输入输出走线在基底上的正投影存在重叠区域。
在示例性实施例中，所述触控金属层包括第一触控金属层和第二触控金属层；
所述第二输入输出走线与所述第一触控金属层同层设置；或者，
所述第二输入输出走线与所述第二触控金属层同层设置；或者，
所述第二输入输出走线包括第九子走线和第十子走线，所述第九子走线与所述第一触控金属层同层设置，所述第十子走线与所述第二触控金属层同层设置。
在示例性实施例中，所述源漏金属层和触控金属层之间包括绝缘层，所述第一输入输出走线和第二输入输出走线通过贯穿所述绝缘层的凹槽或过孔电连接。
在示例性实施例中，所述源漏金属层和触控金属层之间包括绝缘层，所述第一输入输出走线和第二输入输出走线通过所述绝缘层隔离，并通过所述驱动芯片引脚和所述绑定引脚电连接。
在示例性实施例中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
所述第一输入输出走线与所述第一源漏金属层同层设置；或者，
所述第一输入输出走线与所述第二源漏金属层同层设置；或者，
所述第一输入输出走线包括第十一子走线和第十二子走线，所述第十一子走线与所述第一源漏金属层同层设置，所述第十二子走线与所述第二源漏金属层同层设置。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，包括：
形成源漏金属层，所述源漏金属层包括第一走线；
在所述源漏金属层上形成绝缘层；
在所述绝缘层上形成触控金属层，所述触控金属层包括第二走线，所述第一走线在基底上的正投影与所述第二走线在基底上的正投影存在重叠区域，所述第一走线和第二走线形成双层走线结构。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部 分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中绑定区域和边框区域的结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7a为本公开示例性实施例一种显示基板的平面结构示意图；
图7b至图7g为图7a中A-A’区域的剖视图；
图7h至图7j为图7a中B-B’区域的剖视图；
图8a为本公开示例性实施例形成发光结构层图案后的示意图；
图8b为图8a中A-A’区域的剖视图；
图8c为图8a中B-B’区域的剖视图；
图9为本公开示例性实施例形成封装结构层图案后的示意图；
图10a为本公开示例性实施例形成触控绝缘层图案后的示意图；
图10b为图10a中A-A’区域的剖视图；
图10c为图10a中B-B’区域的剖视图；
图11a为本公开示例性实施例对第一凹槽内的封装结构层进行图案化后的示意图；
图11b为图11a中A-A’区域的剖视图；
图12a为本公开示例性实施例形成第二触控金属层图案后触控电极和触控引线的平面结构示意图；
图12b为图12a中D-D’区域的剖视图；
图12c和图12d为本公开示例性实施例形成第二触控金属层图案后第一凹槽和第二凹槽区域的结构示意图；
图13a为本公开示例性实施例一种显示基板中绑定引脚区和驱动芯片引脚区的平面结构示意图；
图13b至图13e为图13a中C-C’区域的剖视图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构 造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，时序控制器分别与数据信号驱动器、扫描信号驱动器和发光信号驱动器连接，数据信号驱动器分别与多个数据信号线(D1到Dn)连接，扫描信号驱动器分别与多个扫描信号线(S1到Sm)连接，发光信号驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号 驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100和位于显示区域100周边的非显示区域，非显示区域可以包括位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以包括以矩阵方式排布的多个子像素，子像素可以包括像素驱动电路和发光器件，绑定区域200可以至少包括隔离坝和将多个子像素的信号线连接至外部驱动装置的绑定电路，边框区域300可以至少包括隔离坝、栅极驱动电路(Gate Driver on Array，简称GOA)和向多个子像素传输电压信号的电源线，绑定区域200和边框区域300的隔离坝形成环绕显示区域100的环形结构。
图3为一种显示基板中绑定区域和边框区域的结构示意图。如图3所示，在示例性实施方式中，在平行于显示基板的平面内，绑定区域200可以位于显示区域100的一侧，绑定区域200可以包括沿着远离显示区域100的方向依次设置的第一扇出区211、弯折区212、第二扇出区213、防静电区214、驱动芯片区215和绑定引脚区216。其中，第一扇出区211可以至少包括多条数据连接线、多条触控引线、第二电源线和第一电源线，多条数据连接线被配置为以扇出(Fanout)走线方式连接显示区域100的数据线(Data Line)，多条触控引线被配置为连接显示区域100的触控电极，第一电源线(VSS)被配置为连接边框区域300的低电压电源线，第二电源线(VDD)被配置为连接显示区域100的高电压电源线。弯折区212可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区213可以包括扇出走线方式引出的多条数据连接线。防静电区214可以包括防静电电路，被配置为通过消除静电防止显示基板的静电损伤。驱动芯片区215可以包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据连接线连接。绑定引脚区216可以包括多个绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，隔离坝可以包括第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420的至少部分可以设置在第一扇出区211，第一隔离坝410和第二隔离坝420可以沿着平行于显示区域边缘的方向延伸，第一隔离坝410与显示区域边缘的距离小于第二隔离坝420与显示区域边缘110的距离，配置为对封装结构层中的有机层进行阻挡，以防止有机层流向弯折区。
在示例性实施方式中，在平行于显示基板的平面内，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、隔离坝区和裂缝坝区。其中，电路区可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描线和第二扫描线连接。隔离坝区可以至少包括第一电源线、第一隔离坝410和第二隔离坝420，第一电源线可以沿着平行于显示区域边缘的方向延伸，与显示区域100中像素驱动电路的第一电源线VSS连接，第一隔离坝410和第二隔离坝420沿着平行于显示区域边缘的方向延伸，边框区域300的第一隔离坝410和第二隔离坝420与绑定区域200的第一隔离坝410和第二隔离坝420为一体结构，且通过相同的图案化工艺同步制备，形成环绕显示区域100的环形结构。裂缝坝区包括在复合绝缘层上设置的多个裂缝，多个裂缝配置为在切割过程中减小显示区域100和电路区的受力，截断裂纹向显示区域100和电路区方向传递，避免影响显示区域100和电路区的膜层结构。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示区域中每个子像素可以包括设置在基底10上的驱动结构层501、设置在驱动结构层501远离基底一侧的发光结构层502以及设置在发光结构层502远离基底一侧的封装结构层503。
在示例性实施方式中，每个子像素的驱动结构层501可以包括由多个晶体管和存储电容构成的像素驱动电路。在示例性实施方式中，驱动结构层501可以包括：设置在基底上的第一绝缘层，设置在第一绝缘层上的半导体层，覆盖半导体层的第二绝缘层，设置在第二绝缘层上的第一栅金属层，覆盖第一栅金属层的第三绝缘层，设置在第三绝缘层上的第二栅金属层，覆盖第二 栅金属层的第四绝缘层，设置在第四绝缘层上的源漏金属层，以及覆盖源漏金属层的平坦层。其中，半导体层可以至少包括多个晶体管，第一栅金属层可以至少包括多个晶体管的栅电极和存储电容的第一极板，第二栅金属层可以至少包括存储电容的第二极板，源漏金属层可以至少包括多个晶体管的第一极和第二极。
在示例性实施方式中，每个子像素的发光结构层502可以包括由多个膜层构成的发光器件，多个膜层可以包括阳极21、像素定义层22、有机发光层23和阴极24，阳极21与像素驱动电路连接，有机发光层23与阳极21连接，阴极24与有机发光层23连接，有机发光层23在阳极21和阴极24驱动下出射相应颜色的光线。封装结构层503可以包括叠设的第一封装层31、第二封装层32和第三封装层33，第一封装层31和第三封装层33可以采用无机材料，第二封装层32可以采用有机材料，第二封装层32设置在第一封装层31和第三封装层33之间，可以保证外界水汽无法进入发光结构层502。
在示例性实施方式中，显示区域还可以包括触控结构层，触控结构层可以包括：设置在第三封装层上的缓冲层，设置在缓冲层上的第一触控金属层，覆盖第一触控金属层的触控绝缘层，设置在触控绝缘层上的第二触控金属层，以及覆盖第二触控金属层的触控保护层。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图5为一种像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VSS和第二电源线VDD)。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第二电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第二电源线VDD与第一电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第二电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第二电源线VDD与第一电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第一电源线VSS连接，第一电源线VSS的信号为低电平信号，第二电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第一电源线VSS、第二电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第二电源线VDD和第一电源线VSS)，7个晶体管均为P 型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第二电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第二电源线VDD输出的电源电压。
亮度均一性(LRU，long range uniformity)是表征面板内255灰阶下不同区域显示亮度差异性的指标，是评价显示质量的重要参数。亮度均一性常用“9点法”和“135点法”进行评价，例如，“9点法”是将面板内指定九个点的亮度最小值与最大值的比值用来评价均一性，比值越接近1，表示均一性越好。亮度均一性与面板的负载(RC Loading)正相关，负载越大，均一性越差。随着AMOLED的发展，客户对LRU提出越来越苛刻的要求，加上显示产品朝着大尺寸方向发展，面板负载不断增加。如何有效降低面板负载，显得尤为重要。
显示区域100中像素驱动电路所需的电压(VSS)从绑定区域200的绑定焊盘引入，经过绑定区域200后进入边框区域300，通过边框区域300环形的电源线输送给每个像素驱动电路的第一电源线VSS。由于电源线存在一定的阻抗，电压信号传输存在压降，因此距离绑定区域200较远的电源线的电压会低于距离绑定区域200较近的电源线的电压，电源线的电压损失降低了显示区域的显示亮度均一性，已经成为影响高品质显示的重要因素。
为了提高显示亮度均一性，本公开提供了一种显示基板，在垂直于显示基板的平面上，显示基板包括位于基底上的源漏金属层、位于源漏金属层上的绝缘层以及位于绝缘层上的触控金属层，源漏金属层包括第一走线，触控金属层包括第二走线，第一走线在基底上的正投影与第二走线在基底上的正投影存在重叠区域，第一走线和第二走线形成双层走线结构。
在一些示例性实施例中，如图7a至图7g所示，在平行于显示基板的平 面上，该显示基板包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其他侧的边框区域300；
在垂直于显示基板的平面上，显示基板包括位于基底10上的源漏金属层、位于源漏金属层上的绝缘层以及位于绝缘层上的触控金属层，源漏金属层包括第一电源线VSS，触控金属层包括第一辅助电源线506，第一电源线VSS位于边框区域300和第一扇出区，并从第一扇出区211延伸至绑定引脚区216，第一辅助电源线506位于边框区域300和第一扇出区211，第一电源线VSS在基底10上的正投影与第一辅助电源线506在基底10上的正投影存在重叠区域；第一电源线VSS和第一辅助电源线506通过贯穿绝缘层的凹槽或过孔电连接。
本公开实施例的显示基板，通过使第一电源线VSS和第一辅助电源线506形成双层走线结构，降低了走线电阻，进而降低了面板负载(loading)，提高了面板均一性。
在示例性实施例中，如图12a和图12b所示，触控金属层包括第一触控金属层和第二触控金属层，第一触控金属层包括连接桥600，第二触控金属层包括第一电极和第二电极，第一电极包括多个沿第一方向D1排列的第一子电极601，沿第一方向D1上、相邻的两个第一子电极601与一个连接桥600通过过孔电连接；第二电极包括多个沿第二方向D2排列的第二子电极602，且沿第二方向D2上、相邻两个第二子电极602之间相互连接，第一方向D1和第二方向D2交叉。
在另一些示例性实施例中，也可以将连接桥600设置在第二触控金属层，第一电极和第二电极设置在第一触控金属层，本公开对此不作限制。
在示例性实施例中，第一电极可以为驱动电极，第二电极可以为感应电极；或者，第一电极可以为感应电极，第二电极可以为驱动电极，本公开对此不作限制。
在示例性实施例中，第一电极和第二电极均采用金属网格结构构成。在示例性实施例中，第一电极和第二电极的金属网格的图案相同。其中，金属网格的图案相同指的是金属网格的金属走线的走向一致、线宽一致。
在示例性实施例中，第一电极和第二电极的制作材料可以为铜Cu、银Ag、铝Al、钛Ti或者镍Ni中的至少一种，本公开实施例对此不作任何限定。
本实施例中，采用金属网格作为触控电极，相比相关技术中的氧化铟锡材料，金属材料具有更好的延展性，不易断裂，因而能够提高触控显示基板的弯折性能，使得触控基板更适合实现柔性触控功能，另外还能够降低成本。并且第一电极和第二电极同层同材料设置，且图案相同，这样在基底10上布满图案相同的金属网格，可以改善不同层金属网格由于线宽等差异产生相互干涉导致的消影不良和光学摩尔纹问题，具有较好的消影效果。
在示例性实施例中，连接桥600可以为金属网格结构，连接桥600的数量根据实际需求限定，本公开实施例对此不作任何限定。
本实施例中，采用金属网格作为连接桥，相比相关技术中的氧化铟锡材料，金属材料具有更好的延展性，不易断裂，因而能够提高触控显示基板的弯折性能，使得触控基板更适合实现柔性触控功能，另外还能够降低成本，并且避免采用实心金属的消影问题。
在示例性实施例中，如图7b和图7e所示，第一辅助电源线506与第一触控金属层同层设置，第一触控金属层和源漏金属层之间设置有封装结构层503和缓冲层504，第一电源线VSS和第一辅助电源线506通过贯穿封装结构层503和缓冲层504的凹槽或过孔电连接。如图7b至图7e所示，由于凹槽或过孔位于隔离坝远离显示区域的一侧，因此，此处凹槽或过孔贯穿的封装结构层包括叠设的第一封装层和第三封装层，即为无机材料/无机材料的叠层结构，不包括第二封装层。
在示例性实施例中，凹槽包括第四凹槽(图中未示出)，第四凹槽贯穿缓冲层504和封装结构层503；或者，过孔包括第六过孔(图中未示出)，第六过孔贯穿缓冲层504和封装结构层503。
在一些示例性实施例中，边框区域300包括第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420均围绕显示区域100设置，第一隔离坝410与显示区域100的距离小于第二隔离坝420与显示区域100的距离。
在示例性实施例中，第四凹槽(或者第六过孔)在基底10上的正投影与第一隔离坝和第二隔离坝在基底10上的正投影不重叠，第四凹槽(或者第六过孔)与显示区域100的距离大于第二隔离坝与显示区域100的距离。
在示例性实施例中，如图7c和图7f所示，第一辅助电源线506与第二触控金属层同层设置，第二触控金属层和源漏金属层之间设置有封装结构层503、缓冲层504和触控绝缘层505，第一电源线VSS和第一辅助电源线506通过贯穿封装结构层503、缓冲层504和触控绝缘层505的凹槽或过孔电连接。
在示例性实施例中，凹槽包括第一凹槽(图中未示出)和第三凹槽(图中未示出)，第一凹槽贯穿触控绝缘层505和缓冲层504，第三凹槽贯穿封装结构层503；或者，过孔包括第三过孔(图中未示出)和第五过孔(图中未示出)，第三过孔贯穿触控绝缘层505和缓冲层504，第五过孔贯穿封装结构层503。
在示例性实施例中，第一凹槽在基底10上的正投影覆盖第三凹槽在基底10上的正投影；或者，第三过孔在基底10上的正投影覆盖第五过孔在基底10上的正投影。
在示例性实施例中，第一凹槽(或者第三过孔)在基底10上的正投影与第一隔离坝410和第二隔离坝420在基底10上的正投影不重叠，第一凹槽(或者第三过孔)与显示区域100的距离大于第二隔离坝420与显示区域100的距离。
在示例性实施例中，如图7d和图7g所示，第一辅助电源线506包括第一子走线5061和第二子走线5062，第一子走线5061与第一触控金属层同层设置，第二子走线5062与第二触控金属层同层设置，第一触控金属层和源漏金属层之间设置有封装结构层503和缓冲层504，第一触控金属层和第二触控金属层之间设置有触控绝缘层505，第一电源线VSS和第一子走线5061通过贯穿封装结构层503和缓冲层504的凹槽或过孔电连接，第一子走线5061和第二子走线5062通过贯穿触控绝缘层505的凹槽或过孔电连接。
在示例性实施例中，凹槽包括第四凹槽(图中未示出)，第四凹槽贯穿 缓冲层504和封装结构层503；或者，过孔包括第六过孔(图中未示出)，第六过孔贯穿缓冲层504和封装结构层503；
凹槽还包括第五凹槽(图中未示出)，第五凹槽贯穿触控绝缘层505；或者，过孔包括第七过孔(图中未示出)，第七过孔贯穿触控绝缘层505。
在示例性实施例中，第四凹槽(或者第六过孔)在基底10上的正投影与第一隔离坝410和第二隔离坝420在基底10上的正投影不重叠，第四凹槽(或者第六过孔)与显示区域100的距离大于第二隔离坝420与显示区域100的距离；
第五凹槽(或者第七过孔)在基底10上的正投影与第一隔离坝和第二隔离坝在基底10上的正投影不重叠，第五凹槽(或者第七过孔)与显示区域100的距离大于第二隔离坝与显示区域100的距离。
在示例性实施例中，第四凹槽在基底10上的正投影覆盖第五凹槽在基底10上的正投影；或者，第六过孔在基底10上的正投影覆盖第七过孔在基底10上的正投影。
在一些示例性实施例中，如图7b至图7d所示，第一辅助电源线506在基底10上的正投影与第一隔离坝410和第二隔离坝420在基底10上的正投影不重叠，第一辅助电源线506与显示区域100的距离大于第二隔离坝420与显示区域100的距离。
在另一些示例性实施例中，如图7e至图7g所示，第一辅助电源线506在基底10上的正投影覆盖第一隔离坝410和第二隔离坝420在基底10上的正投影。
在一些示例性实施例中，如图7b至图7g所示，源漏金属层包括单层源漏金属层。
在另一些示例性实施例中，源漏金属层包括第一源漏金属层和第二源漏金属层(图中未示出)。
第一电源线VSS可以与第一源漏金属层同层设置；或者，
第一电源线VSS可以与第二源漏金属层同层设置；或者，
第一电源线VSS可以包括第三子走线和第四子走线，第三子走线与第一源漏金属层同层设置，第四子走线与第二源漏金属层同层设置。
为了提高显示亮度均一性，本公开还提供了一种显示基板，如图7a、图7h至图7j所示，在平行于显示基板的平面上，该显示基板包括显示区域100、位于显示区域100一侧的绑定区域200，绑定区域200沿远离显示区域100的方向，依次包括第一扇出区211、弯折区212、驱动芯片区215和绑定引脚区216。
在垂直于显示基板的平面上，显示基板包括位于基底10上的源漏金属层、位于源漏金属层上的绝缘层以及位于绝缘层上的触控金属层，源漏金属层包括第二电源线VDD，触控金属层包括第二辅助电源线507，第二电源线VDD位于显示区域100和第一扇出区211，并从第一扇出区211延伸至绑定引脚区216，第二辅助电源线507位于绑定区域200且位于弯折区212远离显示区域100的一侧，第二电源线VDD在基底10上的正投影与第二辅助电源线507在基底10上的正投影存在重叠区域；
第二电源线VDD和第二辅助电源线507通过贯穿绝缘层的凹槽或过孔电连接。
本公开实施例的显示基板，通过使第二电源线VDD和第二辅助电源线507形成双层走线结构，降低了走线电阻，进而降低了面板负载(loading)，提高了面板均一性。
在一些示例性实施例中，显示基板可以只采用第一电源线VSS和第一辅助电源线506形成双层走线结构；在另一些示例性实施例中，显示基板可以只采用第二电源线VDD和第二辅助电源线507形成双层走线结构；在又一些示例性实施例中，显示基板可以采用第一电源线VSS和第一辅助电源线506形成双层走线结构，且第二电源线VDD和第二辅助电源线507形成双层走线结构，本公开对此不作限制。
在示例性实施例中，如图7h所示，第二辅助电源线507与第一触控金属层同层设置，第一触控金属层和源漏金属层之间设置有缓冲层504，第二电 源线VDD和第二辅助电源线507通过贯穿缓冲层504的凹槽或过孔电连接。
在示例性实施例中，如图7i所示，第二辅助电源线507与第二触控金属层同层设置，第二触控金属层和源漏金属层之间设置有缓冲层504和触控绝缘层505，第二电源线VDD和第二辅助电源线通过贯穿缓冲层504和触控绝缘层505的凹槽或过孔电连接。
在示例性实施例中，如图7j所示，第二辅助电源线507包括第五子走线5071和第六子走线5072，第五子走线5071与第一触控金属层同层设置，第六子走线5072与第二触控金属层同层设置，第一触控金属层和源漏金属层之间设置有缓冲层504，第二电源线VDD和第五子走线5071通过贯穿缓冲层504的凹槽或过孔电连接，第二触控金属层和第一触控金属层之间设置有触控绝缘层505，第五子走线5071与第六子走线5072通过贯穿触控绝缘层505的凹槽或过孔电连接。
在示例性实施例中，如图7a所示，在弯折区212远离显示区域100的一侧，第二电源线VDD包括沿第一方向D1延伸的第一横向连接部和沿第二方向D2延伸的第一纵向连接部；第二辅助电源线507包括沿第一方向D1延伸的第二横向连接部和沿第二方向D2延伸的第二纵向连接部；
第一横向连接部与第二横向连接部均设置在弯折区212和驱动芯片区215之间，第一横向连接部在基底10上的正投影与第二横向连接部在基底10上的正投影存在重叠区域；
第一纵向连接部在基底10上的正投影与第二纵向连接部在基底10上的正投影存在重叠区域。
在示例性实施例中，第一纵向连接部包括多个第一分支和多个第二分支，第一分支从第一横向连接部沿第一方向D1的端部延伸至绑定引脚区216，第二分支从第一横向连接部延伸至显示区，第二纵向连接部从第二横向连接部沿第一方向D1的端部延伸至绑定引脚区216，第一分支在基底10上的正投影与第二纵向连接部在基底10上的正投影存在重叠区域。
在示例性实施例中，源漏金属层包括第一源漏金属层和第二源漏金属层；
第二电源线VDD可以与第一源漏金属层同层设置；或者，
第二电源线VDD可以与第二源漏金属层同层设置；或者，
第二电源线VDD可以包括第七子走线和第八子走线，第七子走线与第一源漏金属层同层设置，第八子走线与第二源漏金属层同层设置。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板包括显示区域100和位于显示区域100周边的非显示区域，非显示区域可以包括位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边框区域300。显示基板的制备过程可以包括如下操作。
(1)在基底上依次形成驱动结构层和发光结构层图案。在示例性实施例中，驱动结构层包括多条栅线和多条数据线，多条栅线和多条数据线垂直交叉限定出多个矩阵排布的像素单元，每个像素单元包括至少3个子像素，每个子像素包括一个或多个薄膜晶体管(Thin Film Transistor，TFT)。本实施例中，一个像素单元可以包括3个子像素，分别为红色子像素R、绿色子像素G和蓝色子像素B。当然，本实施例方案也适用于一个像素单元包括4个子像素(红色子像素R、绿色子像素G、蓝色子像素B和白色子像素W)的 情形。
在示例性实施方式中，驱动结构层的制备过程可以包括：
在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括第一有源层。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一栅金属层图案，第一栅金属层图案至少包括第一栅电极和第一电容电极。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一栅金属层的第三绝缘层，以及设置在第三绝缘层上的第二栅金属层图案，第二栅金属层图案至少包括第二电容电极，第二电容电极的位置与第一电容电极的位置相对应。
随后，沉积第四绝缘薄膜，通过图案化工艺形成多个第一过孔图案。第一过孔内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的两端。
随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成源漏金属层图案，源漏金属层图案可以包括：第一源电极和第一漏电极、第一电源线VSS和第二电源线VDD，第一电源线VSS位于边框区域且围绕显示区域，第二电源线VDD位于显示区域，且与多个子像素电连接，第一电源线VSS和第二电源线VDD被引到绑定区，并与相应的绑定引脚对应连接，第一电源线VSS和第二电源线VDD配置为分别连接低电压信号和高电压信号。第一源电极和第一漏电极分别通过第一过孔与第一有源层连接。在示例性实施例中，源漏金属层还可以包括位于绑定引脚区216的多个绑定引脚(FPC on Plastic Pad，FOP Pad)、位于驱动芯片区215的多个驱动芯片引脚(Chip on Plastic Pad，COP Pad)、位于绑定引脚区216和驱动芯片区215之间的输入输出走线(由于该输入输出走线位于显示基板上的外引线接合(Outer Lead Bonding，OLB)区域，因此，该输入输出走线又可以称为OLB走线)等，多个绑定引脚至少包括第一绑定电源引脚和第二 绑定电源引脚，第一绑定电源引脚与第一电源线VSS电连接，第二绑定电源引脚与第二电源线VDD电连接。在另一些示例性实施例中，绑定引脚和驱动芯片引脚均可以由多个金属膜层形成，多个金属膜层可以包括栅金属层(第一栅金属层和/或第二栅金属层)、源漏金属层等(第一源漏金属层和/或第二源漏金属层)。本公开实施例的显示基板以源漏金属层只包括一层结构为例进行举例说明，在另一些示例性实施例中，源漏金属层也可以包括第一源漏金属层和第二源漏金属层两层结构，此时，第一电源线VSS和第二电源线VDD可以位于第一源漏金属层，也可以位于第二源漏金属层，或者同时位于第一源漏金属层和第二源漏金属层，即形成双层走线。
随后，涂覆平坦薄膜，通过图案化工艺对平坦薄膜进行图案化，形成平坦层PLN，平坦层上形成有第二过孔、隔断和第一坝基图案。第二过孔内的平坦层被去掉，暴露出第一晶体管的第一漏电极的表面。隔断内的平坦层被去掉，暴露出第一电源线VSS的表面，第一坝基形成在隔断内的第一电源线VSS上。
至此，在基底上制备完成驱动结构层图案。在示例性实施方式中，第一有源层、第一栅电极、第一源电极和第一漏电极组成薄膜晶体管，第一电容电极和第二电容电极组成存储电容。其中，薄膜晶体管可以是底栅结构，也可以是顶栅结构，可以是非晶硅(a-Si)薄膜晶体管，也可以是低温多晶硅(LTPS)薄膜晶体管或氧化物(Oxide)薄膜晶体管，在此不做限定。
在示例性实施方式中，发光结构层的制备过程可以包括：
在形成前述图案的基底上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成阳极图案。每个子像素的阳极通过平坦层上的第二过孔与该子像素中薄膜晶体管的漏电极连接。
随后，在形成前述图案的基底上涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义(PDL)层和第二坝基图案。
随后，在形成前述图案的基底上涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，形成隔离柱(PS)图案。第一坝基、第二坝基和隔离柱(PS)形成隔离坝(DAM)，隔离坝围绕显示区域设置。隔离坝可以包括第一隔离坝410和第二隔离坝420，第一隔离坝410与显示区域100的距离小于第二隔离 坝420与显示区域100的距离。
随后，在形成前述图案的基底上依次形成有机发光层和阴极，有机发光层形成在显示区域的像素开口内，实现有机发光层与阳极连接。有机发光层可以包括叠设的空穴注入层(HIL)、空穴传输层(HTL)、发光层(EML)、电子传输层(ETL)和电子注入层(EIL)，其中，空穴传输层(HTL)、发光层(EML)、电子传输层(ETL)和电子注入层(EIL)依次设置在空穴注入层上。
至此，在基底上制备完成发光结构层图案，如图8a、图8b和图8c所示，图8b为图8a中AA’区域的剖视图，图8c为图8a中BB’区域的剖视图，其中，11为复合绝缘层，可以包括在基底10上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。由于有机发光层与阳极连接，阳极与薄膜晶体管的漏电极连接，因而实现了有机发光层与薄膜晶体管的漏电极的连接。
(2)在发光结构层远离基底一侧的表面形成封装结构层503图案，如图9所示。在显示区域以及边框区域的电路区，封装结构层503包括叠设的第一封装层、第二封装层和第三封装层，形成无机材料/有机材料/无机材料的叠层结构，在边框区域的隔离坝区(即第一电源线VSS所在区域)，封装结构层包括叠设的第一封装层和第三封装层，形成无机材料/无机材料的叠层结构，可以进一步保证封装完整性，有效隔绝外界水氧。绑定区域200没有封装结构层图案。
在示例性实施方式中，第一封装层和第三封装层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，可以保证外界水氧无法进入发光结构层。第二封装层可以采用有机材料，如树脂等，起到包覆显示基板各个膜层的作用，以提高结构稳定性和平坦性。
(3)在封装结构层503远离基底一侧的表面，依次形成缓冲层504和第一触控金属层图案，缓冲层504的材料可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，第一触控金属层可以包括多个间隔设置的连接桥(图中未示出)以及第一触控引线(图中未示出)等。
在示例性实施方式中，形成第一触控金属层图案可以包括：在基底上沉积第一导电薄膜，在第一导电薄膜上涂覆一层光刻胶，采用掩膜版对光刻胶进行曝光并显影，在连接桥以及触控引线图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的导电薄膜进行刻蚀并剥离剩余的光刻胶，形成第一触控金属层图案。其中，第一导电薄膜可以采用金属材料，也可以采用透明导电材料，如氧化铟锡ITO、氧化铟锌IZO、碳纳米管或者石墨烯等。
(3)在第一触控金属层远离基底10一侧的表面，形成触控绝缘层(TLD)505图案，如图10a、图10b和图10c所示，图10b为图10a中AA’区域的剖视图，图10c为图10a中BB’区域的剖视图，触控绝缘层505可以包括第八过孔(图中未示出)和第九过孔(图中未示出)，第八过孔位于连接桥的两端位置，第八过孔内的触控绝缘层被刻蚀掉，暴露出连接桥的两端，用于后续形成的第一子电极通过该过孔与连接桥电连接，第九过孔位于第一触控引线所在区域，第九过孔内的触控绝缘层被刻蚀掉，暴露出第一触控引线，用于使第一触控引线与后续形成的第二触控引线形成双层触控走线。
在示例性实施例中，触控绝缘层505还可以包括第一凹槽H1，第一凹槽H1位于边框区域300以及绑定区域200中的第一扇出区，第一凹槽H1在基底上的正投影，与第一电源线VSS在基底上的正投影存在重叠区域，第一凹槽H1在基底上的正投影，与第一隔离坝410和第二隔离坝420在基底上的正投影不重叠，第一凹槽H1与显示区域的距离大于第二隔离坝420与显示区域的距离。第一凹槽H1内的触控绝缘层和缓冲层被刻蚀掉，暴露出封装结构层的表面(由于过刻，封装结构层可能会被刻蚀掉一部分)。
在另一些示例性实施例中，第一凹槽H1也可以用多个不连续的第三过孔(图中未示出)代替，即，第三过孔位于边框区域300以及绑定区域200中的第一扇出区，第三过孔在基底上的正投影，与第一电源线VSS在基底上的正投影存在重叠区域，第三过孔在基底上的正投影与第一隔离坝410和第二隔离坝420在基底上的正投影不重叠，第三过孔与显示区域的距离大于第二隔离坝420与显示区域的距离。第三过孔内的触控绝缘层和缓冲层被刻蚀掉，暴露出封装结构层的表面(由于过刻，封装结构层可能会被刻蚀掉一部 分)。
在示例性实施例中，触控绝缘层505还可以包括第二凹槽H2，第二凹槽H2位于绑定区域200，第二凹槽H2位于弯折区212远离显示区域100的一侧，第二凹槽H2在基底上的正投影，与第二电源线VDD在基底上的正投影存在重叠区域，第二凹槽H2内的触控绝缘层和缓冲层被刻蚀掉，暴露出第二电源线VDD的表面。
在另一些示例性实施例中，第二凹槽H2也可以用多个不连续的第四过孔(图中未示出)代替，即，第四过孔位于绑定区域200，第四过孔位于弯折区212远离显示区域100的一侧，第四过孔在基底上的正投影，与第二电源线VDD在基底上的正投影存在重叠区域，第四过孔内的触控绝缘层和缓冲层被刻蚀掉，暴露出第二电源线VDD的表面。
(4)通过图案化工艺，在封装结构层上形成第三凹槽H3，第三凹槽H3在基底上的正投影位于第一凹槽H1在基底上的正投影的范围之内，第三凹槽H3内的封装结构层被刻蚀掉，暴露出第一电源线VSS的表面，如图11a和图11b所示，图11b为图11a中AA’区域的剖视图。
在另一些示例性实施例中，第三凹槽H3也可以用多个不连续的第五过孔(图中未示出)代替，即，第五过孔位于边框区域300以及绑定区域200中的第一扇出区，第五过孔在基底上的正投影，位于第一凹槽H1(或者第三过孔)在基底上的正投影的范围之内，第五过孔内的封装结构层被刻蚀掉，暴露出第一电源线VSS的表面。
(5)在触控绝缘层505远离基底一侧的表面，形成第二触控金属层图案，如图12a至图12d所示，第二触控金属层可以包括第一电极、第二电极以及第二触控引线603等图案，第一电极包括多个沿第一方向D1排列的第一子电极601，沿第一方向D1上、相邻的两个第一子电极601与一个连接桥600通过第八过孔电连接；第二电极包括多个沿第二方向D2排列的第二子电极602，且沿第二方向D2上、相邻两个第二子电极602之间相互连接，第一方向D1和第二方向D2交叉。
本实施例中，第一方向D1和第二方向D2均垂直于封装结构层的厚度方 向。本申请实施例对第一方向D1和第二方向D2夹角的大小不做限定，例如二者可以垂直。
本实施例中，第一子电极601和第二子电极602均呈网格结构，至少一个子像素设置在网格中，且第一子电极601和第二子电极602的材料均为金属材料。由于金属材料的电阻低，导电性良好，灵敏度高，可以避免电信号在第一子电极601和第二子电极602中的传输延迟，提升触控效果。该网格结构中网格的形状可以为规则多边形或不规则多边形形状。
在示例性实施方式中，第二触控金属层还可以包括第一辅助电源线506，第一辅助电源线506位于边框区域300以及绑定区域200中的第一扇出区，第一辅助电源线506在基底上的正投影，与第一电源线VSS在基底上的正投影存在重叠区域，第一辅助电源线506在基底上的正投影，与第一隔离坝410和第二隔离坝420在基底上的正投影不重叠，第一辅助电源线506与显示区域的距离大于第二隔离坝420与显示区域的距离，第一辅助电源线506通过第一凹槽H1(或者第三过孔)和第三凹槽H3(或者第五过孔)与第一电源线VSS电连接。
在示例性实施方式中，第二触控金属层还可以包括第二辅助电源线507，第二辅助电源线507位于绑定区域200，第二辅助电源线507位于弯折区212远离显示区域100的一侧，第二辅助电源线507在基底上的正投影与第二电源线VDD在基底上的正投影存在重叠区域，第二辅助电源线507通过第二凹槽H2与第二电源线VDD电连接。
(5)在第二触控金属层远离基底一侧的表面，形成保护层508图案，如图7c和图7i所示。保护层的材料可以为聚酰亚胺(PI)等材料，主要对触控电极及外围走线起绝缘保护作用。
在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程还可以包括剥离剥离衬底、贴附背膜、切割等工艺，本公开在此不做限定。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，本公开示例性实施例通过形成第一凹槽H1、第三凹槽H3和第一辅助电源线506，使第一电源线VSS和第一辅助电源线506形成双层走线结构，降低了走线电 阻，进而降低了面板负载(loading)，提高了面板均一性。另外，本公开示例性实施例通过形成第二凹槽H2和第二辅助电源线507，使第二电源线VDD和第二辅助电源线507也形成双层走线结构，也降低了走线电阻，进而降低了面板负载(loading)，提高了面板均一性。本公开示例性实施例显示基板的制备过程具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开示例性实施例显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
图13a为本公开示例性实施例另一种显示基板的结构示意图，图13b至图13e为图13a中C-C’区域的几种剖视图。在示例性实施方式中，显示基板包括显示区域、位于显示区域一侧的绑定区域，绑定区域包括驱动芯片区215和绑定引脚区216以及位于驱动芯片区215和绑定引脚区216之间的输入输出走线217；驱动芯片区215包括驱动芯片引脚2151，绑定引脚区216包括绑定引脚2161，输入输出走线217连接驱动芯片引脚2151和绑定引脚2161；
输入输出走线217包括第一输入输出走线2171和第二输入输出走线2172，第一输入输出走线2171在基底10上的正投影与第二输入输出走线2172在基底10上的正投影存在重叠区域；
在垂直于显示基板的平面上，显示基板包括位于基底10上的源漏金属层和触控金属层，第一输入输出走线2171与源漏金属层同层设置，第二输入输出走线2172与触控金属层同层设置。
本公开示例性实施例通过使第一输入输出走线2171和第二输入输出走线2172形成双层走线结构，降低了走线电阻，进而降低了面板负载(loading)，提高了面板均一性。
在一些示例性实施方式中，如图13b所示，第二输入输出走线2172与第一触控金属层同层设置，第一输入输出走线2171与第二输入输出走线2172通过贯穿缓冲层504的凹槽或过孔电连接。
在另一些示例性实施方式中，如图13c所示，第二输入输出走线2172与第二触控金属层同层设置，第一输入输出走线2171与第二输入输出走线2172通过贯穿缓冲层504和触控绝缘层505的凹槽或过孔电连接。
在又一些示例性实施方式中，如图13d所示，第二输入输出走线2172包括第九子走线21721和第十子走线21722，第九子走线21721与第一触控金属层同层设置，第十子走线21722与第二触控金属层同层设置，第一输入输出走线2171与第九子走线21721通过贯穿缓冲层504的凹槽或过孔电连接，第九子走线21721与第十子走线21722通过贯穿触控绝缘层505的凹槽或过孔电连接。
在又一些示例性实施方式中，如图13e所示，源漏金属层和触控金属层之间包括绝缘层，第一输入输出走线2171和第二输入输出走线2172通过绝缘层隔离，并通过驱动芯片引脚2151和绑定引脚2161电连接。由于驱动芯片引脚2151和绑定引脚2161上均有触控金属层膜层，因此第一输入输出走线2171上也可以不去除平坦层PLN、缓冲层504、触控绝缘层505等膜层，即第一输入输出走线2171和第二输入输出走线2172通过绝缘层隔离，并通过驱动芯片引脚2151和绑定引脚2161电连接。
在又一些示例性实施方式中，源漏金属层包括第一源漏金属层和第二源漏金属层(图中未示出)；
第一输入输出走线与第一源漏金属层同层设置；或者，
第一输入输出走线与第二源漏金属层同层设置；或者，
第一输入输出走线包括第十一子走线和第十二子走线，第十一子走线与第一源漏金属层同层设置，第十二子走线与第二源漏金属层同层设置。
本公开示例性实施例还提供了一种显示基板的制备方法，
形成源漏金属层，所述源漏金属层包括第一走线；
在所述源漏金属层上形成绝缘层；
在所述绝缘层上形成触控金属层，所述触控金属层包括第二走线，所述第一走线在基底上的正投影与所述第二走线在基底上的正投影存在重叠区域， 所述第一走线和第二走线形成双层走线结构。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域以及位于所述显示区域其他侧的边框区域，所述绑定区域包括第一扇出区和绑定引脚区；所述制备方法包括：
形成源漏金属层，所述源漏金属层包括第一电源线，所述第一电源线位于所述边框区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区；
在所述源漏金属层上形成绝缘层，并在所述绝缘层上形成贯穿所述绝缘层的凹槽或过孔，所述凹槽或过孔暴露出所述第一电源线；
在所述绝缘层上形成触控金属层，所述触控金属层包括第一辅助电源线，所述第一辅助电源线位于所述边框区域和第一扇出区，所述第一电源线在基底上的正投影与所述第一辅助电源线在基底上的正投影存在重叠区域，所述第一电源线和第一辅助电源线通过所述凹槽或过孔电连接。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域沿远离所述显示区域的方向，依次包括第一扇出区、弯折区、驱动芯片区和绑定引脚区；所述制备方法包括：
形成源漏金属层，所述源漏金属层包括第二电源线，所述第二电源线位于所述显示区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区；
在所述源漏金属层上形成绝缘层，并在所述绝缘层上形成贯穿所述绝缘层的凹槽或过孔，所述凹槽或过孔暴露出所述第二电源线；
在所述绝缘层上形成触控金属层，所述触控金属层包括第二辅助电源线，所述第二辅助电源线位于所述绑定区域且位于所述弯折区远离所述显示区域的一侧，所述第二电源线在基底上的正投影与所述第二辅助电源线在基底上的正投影存在重叠区域，所述第二电源线和所述第二辅助电源线通过所述凹槽或过孔电连接。
在示例性实施例中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域包括驱动芯片区和绑定引脚区；所述驱动芯片区包括驱动芯片引脚，所述绑定引脚区包括绑定引脚；所述制备方法包括：
形成源漏金属层，所述源漏金属层包括第一输入输出走线，第一输入输出走线位于所述驱动芯片区和所述绑定引脚区之间，所述第一输入输出走线连接所述驱动芯片引脚和所述绑定引脚；
在所述源漏金属层上形成绝缘层；
在所述绝缘层上形成触控金属层，所述触控金属层包括第二输入输出走线，所述第一输入输出走线在基底上的正投影与所述第二输入输出走线在基底上的正投影存在重叠区域。
本公开实施例还提供了一种显示装置，包括前述实施例的显示面板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，在垂直于所述显示基板的平面上，所述显示基板包括位于基底上的源漏金属层、位于所述源漏金属层上的绝缘层以及位于所述绝缘层上的触控金属层，所述源漏金属层包括第一走线，所述触控金属层包括第二走线，所述第一走线在基底上的正投影与所述第二走线在基底上的正投影存在重叠区域，所述第一走线和第二走线形成双层走线结构。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域以及位于所述显示区域其他侧的边框区域，所述绑定区域包括第一扇出区和绑定引脚区；
    所述第一走线包括第一电源线，所述第二走线包括第一辅助电源线，所述第一电源线位于所述边框区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区，所述第一辅助电源线位于所述边框区域和第一扇出区，所述第一电源线在基底上的正投影与所述第一辅助电源线在基底上的正投影存在重叠区域；
    所述第一电源线和所述第一辅助电源线通过贯穿所述绝缘层的凹槽或过孔电连接。
  3. 根据权利要求2所述的显示基板，其中，所述触控金属层包括第一触控金属层和第二触控金属层；
    所述第一辅助电源线与所述第一触控金属层同层设置；或者，
    所述第一辅助电源线与所述第二触控金属层同层设置；或者，
    所述第一辅助电源线包括第一子走线和第二子走线，所述第一子走线与所述第一触控金属层同层设置，所述第二子走线与所述第二触控金属层同层设置。
  4. 根据权利要求2所述的显示基板，其中，所述边框区域包括至少一个隔离坝，所述隔离坝围绕所述显示区域设置；
    所述第一辅助电源线在基底上的正投影与所述隔离坝在基底上的正投影 不重叠，所述第一辅助电源线与所述显示区域的距离大于所述隔离坝与所述显示区域的距离。
  5. 根据权利要求2所述的显示基板，其中，所述边框区域包括至少一个隔离坝，所述隔离坝围绕所述显示区域设置；
    所述第一辅助电源线在基底上的正投影至少覆盖部分所述隔离坝在基底上的正投影。
  6. 根据权利要求2所述的显示基板，其中，所述绝缘层包括封装结构层、缓冲层和触控绝缘层；所述凹槽包括第一凹槽和第三凹槽，所述第一凹槽贯穿所述触控绝缘层和缓冲层，所述第三凹槽贯穿所述封装结构层。
  7. 根据权利要求6所述的显示基板，其中，所述第一凹槽在基底上的正投影覆盖所述第三凹槽在基底上的正投影。
  8. 根据权利要求2至7任一所述的显示基板，其中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
    所述第一电源线与所述第一源漏金属层同层设置；或者，
    所述第一电源线与所述第二源漏金属层同层设置；或者，
    所述第一电源线包括第三子走线和第四子走线，所述第三子走线与所述第一源漏金属层同层设置，所述第四子走线与所述第二源漏金属层同层设置。
  9. 根据权利要求1或2所述的显示基板，其中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域沿远离所述显示区域的方向，依次包括第一扇出区、弯折区、驱动芯片区和绑定引脚区；
    所述第一走线包括第二电源线，所述第二走线包括第二辅助电源线，所述第二电源线位于所述显示区域和第一扇出区，并从所述第一扇出区延伸至所述绑定引脚区，所述第二辅助电源线位于所述绑定区域且位于所述弯折区远离所述显示区域的一侧，所述第二电源线在基底上的正投影与所述第二辅助电源线在基底上的正投影存在重叠区域；
    所述第二电源线和所述第二辅助电源线通过贯穿所述绝缘层的凹槽或过 孔电连接。
  10. 根据权利要求9所述的显示基板，其中，所述触控金属层包括第一触控金属层和第二触控金属层；
    所述第二辅助电源线与所述第一触控金属层同层设置；或者，
    所述第二辅助电源线与所述第二触控金属层同层设置；或者，
    所述第二辅助电源线包括第五子走线和第六子走线，所述第五子走线与所述第一触控金属层同层设置，所述第六子走线与所述第二触控金属层同层设置。
  11. 根据权利要求9所述的显示基板，其中，在所述绑定区域，所述第二电源线包括沿第一方向延伸的第一横向连接部和沿第二方向延伸的第一纵向连接部；所述第二辅助电源线包括沿所述第一方向延伸的第二横向连接部和沿所述第二方向延伸的第二纵向连接部；
    所述第一横向连接部与第二横向连接部均设置在所述弯折区和所述驱动芯片区之间，所述第一横向连接部在基底上的正投影与所述第二横向连接部在基底上的正投影存在重叠区域；所述第一纵向连接部在基底上的正投影与所述第二纵向连接部在基底上的正投影存在重叠区域。
  12. 根据权利要求11所述的显示基板，其中，所述第一纵向连接部包括多个第一分支和多个第二分支，所述第一分支从所述第一横向连接部沿所述第一方向的端部延伸至所述绑定引脚区，所述第二分支从所述第一横向连接部延伸至所述显示区，所述第二纵向连接部从所述第二横向连接部沿所述第一方向的端部延伸至所述绑定引脚区，所述第一分支在基底上的正投影与所述第二纵向连接部在基底上的正投影存在重叠区域。
  13. 根据权利要求9至12任一所述的显示基板，其中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
    所述第二电源线与所述第一源漏金属层同层设置；或者，
    所述第二电源线与所述第二源漏金属层同层设置；或者，
    所述第二电源线包括第七子走线和第八子走线，所述第七子走线与所述第一源漏金属层同层设置，所述第八子走线与所述第二源漏金属层同层设置。
  14. 根据权利要求1或9所述的显示基板，其中，所述显示基板包括显示区域、位于所述显示区域一侧的绑定区域，所述绑定区域包括驱动芯片区和绑定引脚区以及位于所述驱动芯片区和所述绑定引脚区之间的输入输出走线；所述驱动芯片区包括驱动芯片引脚，所述绑定引脚区包括绑定引脚，所述输入输出走线连接所述驱动芯片引脚和所述绑定引脚；
    所述第一走线包括第一输入输出走线，所述第二走线包括第二输入输出走线，所述第一输入输出走线在基底上的正投影与所述第二输入输出走线在基底上的正投影存在重叠区域。
  15. 根据权利要求14所述的显示基板，其中，所述触控金属层包括第一触控金属层和第二触控金属层；
    所述第二输入输出走线与所述第一触控金属层同层设置；或者，
    所述第二输入输出走线与所述第二触控金属层同层设置；或者，
    所述第二输入输出走线包括第九子走线和第十子走线，所述第九子走线与所述第一触控金属层同层设置，所述第十子走线与所述第二触控金属层同层设置。
  16. 根据权利要求14所述的显示基板，其中，所述源漏金属层和触控金属层之间包括绝缘层，所述第一输入输出走线和第二输入输出走线通过贯穿所述绝缘层的凹槽或过孔电连接。
  17. 根据权利要求14所述的显示基板，其中，所述源漏金属层和触控金属层之间包括绝缘层，所述第一输入输出走线和第二输入输出走线通过所述绝缘层隔离，并通过所述驱动芯片引脚和所述绑定引脚电连接。
  18. 根据权利要求14至17任一所述的显示基板，其中，所述源漏金属层包括第一源漏金属层和第二源漏金属层；
    所述第一输入输出走线与所述第一源漏金属层同层设置；或者，
    所述第一输入输出走线与所述第二源漏金属层同层设置；或者，
    所述第一输入输出走线包括第十一子走线和第十二子走线，所述第十一子走线与所述第一源漏金属层同层设置，所述第十二子走线与所述第二源漏金属层同层设置。
  19. 一种显示装置，包括如权利要求1至18任一项所述的显示基板。
  20. 一种显示基板的制备方法，包括：
    形成源漏金属层，所述源漏金属层包括第一走线；
    在所述源漏金属层上形成绝缘层；
    在所述绝缘层上形成触控金属层，所述触控金属层包括第二走线，所述第一走线在基底上的正投影与所述第二走线在基底上的正投影存在重叠区域，所述第一走线和第二走线形成双层走线结构。
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