WO2024099009A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024099009A1
WO2024099009A1 PCT/CN2023/123536 CN2023123536W WO2024099009A1 WO 2024099009 A1 WO2024099009 A1 WO 2024099009A1 CN 2023123536 W CN2023123536 W CN 2023123536W WO 2024099009 A1 WO2024099009 A1 WO 2024099009A1
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WIPO (PCT)
Prior art keywords
area
layer
sub
routing
line
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PCT/CN2023/123536
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English (en)
French (fr)
Inventor
吴刘
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Publication of WO2024099009A1 publication Critical patent/WO2024099009A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • PDP plasma display panel
  • FED field emission display
  • Embodiments of the present disclosure provide a display panel and a display device.
  • the present embodiment provides a display panel, comprising: a substrate, a display structure layer, a packaging structure layer and a plurality of signal lead lines.
  • the substrate comprises: a display area, a signal access area located on one side of the display area, and a peripheral routing area located between the display area and the signal access area.
  • the display structure layer is located in the display area.
  • the packaging structure layer is located on a side of the display structure layer away from the substrate.
  • the packaging structure layer extends from the display area to the peripheral routing area.
  • the peripheral routing area comprises: a first area located on a side of the packaging boundary of the packaging structure layer close to the signal access area.
  • a plurality of signal lead lines are located in the peripheral routing area. At least one signal lead line comprises a first routing line located in the first area, and the first routing line is a double-layer routing line.
  • the peripheral routing area further includes: a second area located on a side of a packaging boundary of the packaging structure layer close to the display area; and a length of the first routing line extending to the second area is less than or equal to 300 micrometers.
  • the first routing includes: a first sub-routing and a second sub-routing electrically connected to each other, the first sub-routing is located on a side of the second sub-routing away from the substrate; and the orthographic projections of the first sub-routing and the second sub-routing on the substrate at least partially overlap.
  • the resistivity of the material of the first sub-routing is less than the resistivity of the material of the second sub-routing.
  • materials of the first sub-routing and the second sub-routing are both metal materials.
  • the first sub-line is a stacked structure of titanium, aluminum and titanium, and the material of the second sub-line includes molybdenum.
  • At least one insulating layer is disposed between the first sub-route and the second sub-route, the at least one insulating layer is provided with a plurality of via holes arranged in an array, and the first sub-route is electrically connected to the second sub-route through the plurality of via holes.
  • the peripheral routing area also includes: a second area located on a side of the packaging boundary of the packaging structure layer close to the display area; the at least one first signal lead-out line also includes: a second routing located in the second area, and the second routing is an integrated structure with the first sub-routing of the first routing.
  • the signal access area includes a plurality of signal access pins, and the second sub-route is electrically connected to at least one signal access pin.
  • the display panel in a direction perpendicular to the display panel, includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially disposed on the substrate, wherein the first sub-wire is located in the first source-drain metal layer, and the second sub-wire is located in the first gate metal layer or the second gate metal layer.
  • a first planarization layer and a first passivation layer are sequentially disposed between the first source-drain metal layer and the second source-drain metal layer, and a second passivation layer and a planarization layer are sequentially disposed on a side of the second source-drain metal layer away from the substrate.
  • the peripheral routing area has a first isolation area, at least one of the first flat layer and the second flat layer in the first isolation area is removed, and the first isolation area partially overlaps with the packaging structure layer; the first routing partially overlaps with the first isolation area.
  • the plurality of signal lead-out lines include: a plurality of data fan-out lines; or include: a plurality of data fan-out lines and a plurality of driving control lines.
  • the base substrate is a rigid substrate.
  • an embodiment of the present disclosure provides a display device, including the display panel as described above.
  • FIG1 is a schematic diagram of the appearance of a display device
  • FIG2 is a schematic diagram of the structure of a display device
  • FIG3 is an equivalent circuit diagram of a pixel circuit
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a display area of a display panel according to at least one embodiment of the present disclosure
  • FIG5 is a schematic diagram of a first peripheral region of a display panel according to at least one embodiment of the present disclosure
  • FIG6 is a partial schematic diagram of a first peripheral area according to at least one embodiment of the present disclosure.
  • FIG. 7 and 8 are schematic diagrams of local film layers in the first peripheral region of at least one embodiment of the present disclosure.
  • FIG9 is a partial schematic diagram of a peripheral wiring area of at least one embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the first source-drain metal layer in FIG9 ;
  • FIG11 is a schematic diagram of the first gate metal layer in FIG9 ;
  • FIG12 is a partial schematic diagram of a first region of at least one embodiment of the present disclosure.
  • FIG13 is a schematic partial cross-sectional view along the Q-Q' direction in FIG12;
  • FIG14 is a schematic diagram of the first gate metal layer in FIG12 ;
  • FIG. 15 is a partial schematic diagram of the first region after the second insulating layer is formed in FIG. 12 .
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region where current mainly flows.
  • the first electrode in order to distinguish the two electrodes of a transistor except the gate, one of the electrodes is called the first electrode and the other electrode is called the second electrode.
  • the first electrode can be a source electrode or a drain electrode
  • the second electrode can be a drain electrode or a source electrode.
  • the gate electrode of the transistor is called a control electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” can be interchanged.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • triangle, rectangle, trapezoid, pentagon or hexagon are not strictly defined and can be Approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., may have some small deformations caused by tolerances, and may have chamfers, arc edges and deformations.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means “the main part of A extends along direction B".
  • FIG1 is a schematic diagram of the appearance of a display device, which has a rectangular rounded corner shape.
  • the display device may include: a display panel.
  • the display panel may be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges.
  • at least some corners of the display panel may be curves.
  • the portion where adjacent linear edges meet each other may be replaced by a curve with a predetermined curvature.
  • the curvature may be set according to the position of the curve. For example, the curvature may be changed according to the position where the curve starts, the length of the curve, etc.
  • the display panel may include a display area AA and a peripheral area BB located around the display area AA.
  • the display area AA may include a first edge (lower edge) and a second edge (upper edge) relatively arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) relatively arranged in the first direction X. Adjacent edges may be connected by arc-shaped chamfers to form a rounded quadrilateral shape.
  • the peripheral area BB may include: a first peripheral area (lower frame) B1 and a second peripheral area (upper frame) B2 relatively arranged in the second direction Y, and a third peripheral area (left frame) B3 and a fourth peripheral area (right frame) B4 relatively arranged in the first direction X.
  • the first peripheral area B1 is connected to the third peripheral area B3 and the fourth peripheral area B4, and the second peripheral area B2 is connected to the third peripheral area B3 and the fourth peripheral area B4.
  • the display area AA includes at least a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D.
  • the plurality of gate lines G may extend along a first direction X
  • the plurality of data lines D may extend along a second direction Y.
  • the orthographic projections of the plurality of gate lines G and the plurality of data lines D on the display panel may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX is disposed in each sub-pixel region.
  • the plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G may be configured to provide gate control signals to the plurality of sub-pixels PX.
  • the gate control signal may include a scan signal, or may include a scan signal and a light emitting control signal.
  • the first direction X may be the extension direction (row direction) of the gate lines G in the display area AA
  • the second direction Y may be the extension direction (column direction) of the data lines D in the display area AA.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.
  • this embodiment is not limited to this.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C structure, a 7T1C structure, a 5T1C structure, an 8T1C structure, or an 8T2C structure, etc., wherein T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • multiple transistors in the pixel circuit may use low temperature polysilicon thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon).
  • LTPS Low Temperature Poly-Silicon
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging.
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • FIG2 is a schematic diagram of the structure of a display device.
  • the display device may include: a timing controller 21, a data driver 22, a scan drive circuit 23, a light-emitting drive circuit 24, and a display panel 25.
  • the display area of the display panel 25 may include a plurality of sub-pixels PX arranged regularly.
  • the timing controller 21 may provide the grayscale value and control signal suitable for the specification of the data driver 22 to the data driver 22; the timing controller 21 may provide the scan clock signal, the scan start signal, etc. suitable for the specification of the scan drive circuit 23 to the scan drive circuit 23; the timing controller 21 may provide the light emitting clock signal, the light emitting start signal, etc. suitable for the specification of the light emitting drive circuit 24 to the light emitting drive circuit 24.
  • the data driver 22 may generate the data voltage to be provided to the data lines D1 to Dn using the grayscale value and the control signal received from the timing controller 21.
  • the data driver 22 may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of sub-pixel rows.
  • the scan drive circuit 23 may generate the scan signal to be provided to the scan lines S1 to Sm by the scan clock signal, the scan start signal, etc. received from the timing controller 21.
  • the scan drive circuit 23 may sequentially provide the scan signal having an on-level pulse to the scan lines.
  • the scan drive circuit 23 may include a shift register, and the scan signal may be generated by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next level circuit under the control of the scan clock signal.
  • the light-emitting drive circuit 24 may generate a light-emitting control signal to be provided to the light-emitting control lines E1 to Eo by receiving the light-emitting clock signal, the light-emitting start signal, etc. from the timing controller 21. For example, the light-emitting drive circuit 24 may sequentially provide the light-emitting start signal with an off-level pulse to the light-emitting control line.
  • the light-emitting drive circuit 24 may include a shift register, and the light-emitting control signal may be generated by sequentially transmitting the light-emitting start signal provided in the form of an off-level pulse to the next level circuit under the control of the light-emitting clock signal.
  • n, m and o are all natural numbers.
  • the scan drive circuit and the light emitting drive circuit may be directly disposed on the display panel.
  • the scan drive circuit may be disposed in the third peripheral region of the display panel, and the light emitting drive circuit may be disposed in the first peripheral region of the display panel.
  • the third peripheral area and the fourth peripheral area of the display panel can both be provided with a scanning drive circuit and a light emitting drive circuit.
  • the scanning drive circuit and the light emitting drive circuit can be formed together with the sub-pixel in the process of forming the pixel circuit of the sub-pixel.
  • the data driver may be disposed on a separate chip or printed circuit board to be connected to the sub-pixel through a signal access pin on the display panel.
  • the data driver may be formed by a chip on glass, a chip on plastic, a chip on a film, etc., disposed in a first peripheral area of the display panel to be connected to the signal access pin.
  • the timing controller may be disposed separately from the data driver or integrally with the data driver. However, this embodiment is not limited to this. In some examples, the data driver may be disposed directly on the display panel.
  • FIG3 is an equivalent circuit diagram of a pixel circuit.
  • the pixel circuit of this example may include seven transistors (i.e., the first transistor T1 to the seventh transistor T7) and a storage capacitor Cst.
  • the gate of the third transistor T3 is electrically connected to the first node N1
  • the first electrode of the third transistor T3 is electrically connected to the second node N2
  • the second electrode of the third transistor T3 is electrically connected to the third node N3.
  • the third transistor T3 can also be referred to as a driving transistor.
  • the gate of the fourth transistor T4 is electrically connected to the first scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3.
  • the fourth transistor T4 can also be referred to as a data write transistor.
  • the gate of the second transistor T2 is electrically connected to the first scan line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3.
  • the second transistor T2 can also be referred to as a threshold compensation transistor.
  • the gate of the fifth transistor T5 is electrically connected to the light emitting control line EML, the first electrode of the fifth transistor T5 is electrically connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the gate of the sixth transistor T6 is electrically connected to the light emitting control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL.
  • the fifth transistor T5 and the sixth transistor T6 can also be called light emitting control transistors.
  • the first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3.
  • the seventh transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL.
  • the gate of the first transistor T1 is electrically connected to the second scanning line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3.
  • the gate of the seventh transistor T7 is electrically connected to the third scan line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL.
  • the first transistor T1 and the seventh transistor T7 can also be called reset control transistors.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the second power line VDD.
  • the first node N1 is the connection point of the storage capacitor Cst
  • the first transistor T1, the third transistor T3 and the second transistor T2 the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3,
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the second power line VDD can be configured to provide a constant second voltage signal to the pixel circuit
  • the first power line VSS can be configured to provide a constant first voltage signal to the pixel circuit
  • the second voltage signal can be greater than the first voltage signal.
  • the first scan line GL can be configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL can be configured to provide a data signal DATA to the pixel circuit
  • the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit
  • the second scan line RST1 can be configured to provide a first reset control signal to the pixel circuit.
  • Signal RESET1 the third scan line RST2 can be configured to provide a second reset control signal RESET2 to the pixel circuit.
  • the second scan line RST1 electrically connected to the n-th row of pixel circuits can be electrically connected to the first scan line GL of the n-1-th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) and the scan signal SCAN(n-1) can be the same.
  • the third scan line RST2 of the n-th row of pixel circuits can be electrically connected to the first scan line GL of the n-th row of pixel circuits to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) and the scan signal SCAN(n) can be the same.
  • n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be realized.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal can be different from the second initial signal.
  • the first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto.
  • the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.
  • the signal routing in the first peripheral area may have poor signal transmission.
  • the inventor of the present application has found through research that in the preparation process of the LTPS display panel, the signal routing in the first peripheral area is prepared using a metal material with a higher resistivity (e.g., molybdenum (Mo), the impedance of molybdenum per unit area is about 0.5 ohms ( ⁇ )), and there is a situation where the routing impedance is large and affects the signal transmission effect; after the signal routing is prepared using a material with a lower resistivity (e.g., a titanium/aluminum/titanium stacked structure, the impedance of the titanium/aluminum/titanium stacked structure per unit area is about 0.05 ⁇ ), although the routing impedance can be reduced, it is limited by the preparation process, and there is a situation where aluminum oxidation causes the top layer of titanium to collapse and affects signal transmission.
  • a metal material with a higher resistivity e.g., moly
  • the flat layer is prepared after the titanium/aluminum/titanium stacked structure is prepared.
  • the glue coating process of the flat layer aluminum is easily oxidized, resulting in the collapse of the titanium on the aluminum layer.
  • the display panel is prone to routing damage during the reliability test.
  • the present embodiment provides a display panel, comprising: a substrate, a display structure layer, a packaging structure layer and a plurality of signal lead-out lines.
  • the substrate comprises: a display area, a signal access area located on one side of the display area, and a peripheral routing area located between the display area and the signal access area.
  • the display structure layer is located in the display area.
  • the packaging structure layer is located on a side of the display structure layer away from the substrate.
  • the packaging structure layer extends from the display area to the peripheral routing area.
  • the peripheral routing area comprises: a first area located on a side of the packaging boundary of the packaging structure layer close to the signal access area.
  • the display panel provided in this embodiment can improve the signal transmission effect of the peripheral wiring area by arranging the signal lead-out lines of the peripheral wiring area to adopt double-layer wiring in the first area, thereby improving the display effect.
  • the peripheral routing area also includes: a second area located on the packaging boundary of the packaging structure layer close to the display area.
  • the length of the first routing line of the signal lead-out line extending to the second area may be less than or equal to 300 microns.
  • the length of the first routing line extending to the second area may be approximately 300 microns.
  • the first routing may include: a first sub-routing and a second sub-routing electrically connected to each other, the first sub-routing may be located on a side of the second sub-routing away from the substrate substrate, and the orthographic projections of the first sub-routing and the second sub-routing on the substrate substrate may at least partially overlap.
  • the orthographic projection of the first sub-routing on the substrate substrate may coincide with the orthographic projection of the second sub-routing on the substrate substrate.
  • the resistivity of the material of the first sub-routing may be less than the resistivity of the material of the second sub-routing.
  • the materials of the first sub-routing and the second sub-routing may both be metal materials.
  • the first sub-routing may adopt a stacked structure of titanium, aluminum and titanium, and the material of the second sub-routing may include molybdenum.
  • the impedance of the signal lead-out line can be reduced, and the influence of the routing of the titanium, aluminum and titanium stacked structure due to the collapse of the top layer of titanium caused by aluminum oxidation on the signal transmission can be improved, thereby ensuring the display effect of the display panel.
  • it can be This is to prevent the display panel from having its wiring damaged during the reliability test.
  • At least one insulating layer may be provided between the first sub-route and the second sub-route, and the at least one insulating layer may be provided with a plurality of vias arranged in an array, and the first sub-route may be electrically connected to the second sub-route through the plurality of vias.
  • the first sub-route and the second sub-route of this example are electrically connected through the plurality of vias arranged in an array, and a parallel connection between the first sub-route and the second sub-route may be achieved, thereby reducing the impedance of the signal lead-out line and improving the display effect.
  • the peripheral routing area may further include: a second area located at a side of the packaging boundary of the packaging structure layer close to the display area.
  • At least one signal lead may further include: a second routing located in the second area, and the second routing and the first sub-routing of the first routing may be an integrated structure.
  • the second routing of the second area and the first sub-routing are set to the same layer, for example, a titanium-aluminum-titanium stacking structure is used, which is conducive to reducing the impedance of the signal lead, thereby improving the display effect.
  • the display panel of this embodiment is described below by means of some examples.
  • FIG4 is a schematic diagram of a partial cross-sectional structure of a display area of a display panel of at least one embodiment of the present disclosure.
  • FIG4 illustrates the structure of a sub-pixel in the display area.
  • the display panel in a direction perpendicular to the display panel, may include: a base substrate 101, and a display structure layer and an encapsulation structure layer 104 sequentially disposed on the base substrate 101.
  • the display structure layer may include: a circuit structure layer 102 and a light-emitting structure layer 103 sequentially disposed on the base substrate 101.
  • the display panel may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate.
  • this embodiment is not limited thereto.
  • the circuit structure layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit
  • FIG4 is taken as an example to illustrate a transistor (e.g., transistor 201) and a storage capacitor (e.g., storage capacitor 202) included in the pixel circuit of a sub-pixel.
  • the transistor 201 may be the sixth transistor or the seventh transistor in the aforementioned pixel circuit
  • the storage capacitor 202 may be the storage capacitor Cst in the aforementioned pixel circuit.
  • the circuit structure layer 102 of a sub-pixel may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 101.
  • a buffer layer 210 may be disposed between the semiconductor layer and the substrate 101;
  • a first insulating layer 211 may be disposed between the semiconductor layer and the first gate metal layer;
  • a second insulating layer 212 may be disposed between the first gate metal layer and the second gate metal layer;
  • a third insulating layer 213 may be disposed between the second gate metal layer and the first source-drain metal layer.
  • a first flat layer 214 and a first passivation layer 215 may be disposed between the first source-drain metal layer and the second source-drain metal layer.
  • the first passivation layer 215 may be located on a side of the first flat layer 214 away from the substrate 101.
  • a second passivation layer 216 and a second flat layer 217 may be disposed in sequence on a side of the second source-drain metal layer away from the substrate 101.
  • the second source-drain metal layer is disposed between the first passivation layer 215 and the second passivation layer 216 , which can avoid the situation where the second source-drain metal layer cannot be deposited during the preparation process, and can ensure the display effect of the display panel.
  • the semiconductor layer may include at least: an active layer of the transistor 201; the first gate metal layer may include at least: a gate of the transistor 201 and a first capacitor plate of the storage capacitor 202; the second gate metal layer may include at least: a second capacitor plate of the storage capacitor 202, and the orthographic projection of the second capacitor plate on the substrate 101 may overlap with the orthographic projection of the first capacitor plate on the substrate 101; the first source-drain metal layer may include at least: a first electrode and a second electrode of the transistor 201; the second source-drain metal layer may include at least: an anode connection electrode 203, and the anode connection electrode 203 may electrically connect the second electrode of the transistor 201 and the anode 301 of the light-emitting element.
  • the active layer, the gate, the first electrode and the second electrode may constitute the transistor 201, and the first capacitor plate and the second capacitor plate may constitute the storage capacitor 202.
  • the buffer layer 210, the first insulating layer 211, the second insulating layer 212, the third The insulating layer 213, the first passivation layer 215 and the second passivation layer 217 may be inorganic insulating layers.
  • the buffer layer 210, the first insulating layer 211, the second insulating layer 212, the third insulating layer 213, the first passivation layer 215 and the second passivation layer 217 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer 211 and the second insulating layer 212 may be referred to as a gate insulating (GI) layer, and the third insulating layer 213 may be referred to as an interlayer insulating (ILD) layer.
  • the first planar layer 214 and the second planar layer 216 may be organic insulating layers.
  • the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium
  • the material of the first gate metal layer and the second gate metal layer may be molybdenum, and the material of the first source-drain metal layer may be a stacked structure of titanium, aluminum and titanium.
  • the semiconductor layer may be made of materials such as polysilicon (p-Si).
  • the light emitting structure layer 103 may include an anode layer, a pixel definition layer 304, an organic light emitting layer 302, and a cathode layer.
  • the anode layer may include an anode 301 of a light emitting element
  • the cathode layer may include a cathode 303 of a light emitting element.
  • the anode 301 may be disposed on the second flat layer 217, and electrically connected to the anode connection electrode 203 through a via hole provided on the second flat layer 217.
  • the pixel definition layer 304 may be disposed on the anode layer and the second flat layer 217, and a pixel opening may be provided on the pixel definition layer 304, and the pixel opening may expose at least part of the surface of the anode 301.
  • the organic light emitting layer 302 is at least partially disposed in the pixel opening, and the organic light emitting layer 302 is connected to the anode 301.
  • the cathode 303 is disposed on the organic light emitting layer 302, and the cathode 303 is connected to the organic light emitting layer 302.
  • the organic light emitting layer 302 emits light of corresponding color under the drive of the anode 301 and the cathode 302.
  • the organic light-emitting layer 302 may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode 301.
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may overlap slightly, or may be isolated
  • the hole blocking layer may be a common layer connected together.
  • this embodiment is not limited to this.
  • the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer 103 .
  • FIG5 is a schematic diagram of the first peripheral area of the display panel of at least one embodiment of the present disclosure.
  • the first peripheral area of the display panel may include: a signal access area B13 located on one side of the display area AA, and a peripheral wiring area B12 and a peripheral circuit area B11 located between the display area AA and the signal access area B13.
  • the peripheral circuit area B11 may be located on the side of the peripheral wiring area B12 close to the display area AA.
  • the first peripheral area may include: a peripheral circuit area B11, a peripheral wiring area B12, and a signal access area B13 arranged in sequence in a direction away from the display area AA.
  • the signal access area B13 may include a plurality of signal access pins arranged side by side in parallel, and the plurality of signal access pins may be arranged in sequence along the first direction X.
  • the plurality of signal access pins may be configured to be bound and connected to a flexible circuit board or a driver chip to obtain a signal from the flexible circuit board or the driver chip.
  • the signal access area B13 may be provided with a plurality of driver chips (e.g., driver chips 40a, 40b, 40c, and 40d).
  • the plurality of driver chips may be arranged in sequence along the first direction X in the signal access area B13.
  • this embodiment is not limited to this.
  • the peripheral circuit area B11 may be provided with a multiplexing circuit and an electrostatic discharge circuit (ESD) (not shown).
  • the electrostatic discharge circuit may be located on a side of the multiplexing circuit away from the display area AA.
  • the multiplexing circuit may include a plurality of multiplexing units, each of which may be electrically connected to a plurality of data lines in the display area AA, and may be configured to enable a signal source to provide data signals to the plurality of data lines.
  • each multiplexing unit may be electrically connected to a plurality of data lines in the display area AA.
  • the element can be electrically connected to a multiplexed data line, and a signal source providing a data signal can be electrically connected through the multiplexed data line.
  • the multiplexed data line can be electrically connected to an electrostatic discharge circuit to discharge static electricity.
  • a plurality of signal lead-out lines may be provided in the peripheral routing area B12, and the plurality of signal lead-out lines may include a plurality of data fan-out lines 31.
  • the plurality of data fan-out lines 31 may be electrically connected to the plurality of multiplexed data lines in the peripheral circuit area B11.
  • the plurality of data fan-out lines 31 may be electrically connected to the plurality of multiplexed data lines in a one-to-one correspondence.
  • the plurality of data fan-out lines 31 may extend to the signal access area B13, and may be electrically connected to the plurality of signal access pins in the signal access area B13 in a corresponding manner.
  • the data fan-out lines 31 may be electrically connected to the signal access pins in a one-to-one correspondence.
  • the plurality of signal lead lines may further include a plurality of drive control lines 33.
  • the plurality of drive control lines 33 may be located on both sides of the plurality of data fan-out lines 31 along the first direction X.
  • the plurality of drive control lines 33 may be electrically connected to the leftmost drive chip (e.g., drive chip 40a) and the rightmost drive chip (e.g., drive chip 40d).
  • the drive control line 33 electrically connected to the drive chip 40a may extend to the third peripheral area to provide a control signal to the scan drive circuit of the third peripheral area; the drive control line 33 electrically connected to the drive chip 40d may extend to the fourth peripheral area to provide a control signal to the light-emitting drive circuit of the fourth peripheral area.
  • this embodiment is not limited to this.
  • FIG6 is a partial schematic diagram of the first peripheral area of at least one embodiment of the present disclosure.
  • FIG6 is a partial schematic diagram of the first peripheral area in FIG5 that is closest to the third peripheral area.
  • multiple data fan-out lines 31 extend to the signal access area B13 in a fan-out routing manner.
  • the peripheral routing area B12 is also provided with a first power line 321 and a second power line 322.
  • the first power line and the second power line can be located on one side of the multiple data fan-out lines 31 electrically connected to the driver chip close to the center line of the display panel along the first direction X; for a driver chip with adjacent driver chips on both sides along the first direction X, the first power line and the second power line can be located on both sides of the multiple data fan-out lines 31 electrically connected to the driver chip.
  • the first power line 321 and the second power line 322 may be located on the side of the plurality of data fan-out lines 31 electrically connected to the driver chip 40a close to the fourth peripheral area, and the plurality of drive control lines 33 may be located on the side of the plurality of data fan-out lines 31 electrically connected to the driver chip 40a close to the third peripheral area.
  • one end of the first power line 321 may extend to the signal access area B13 and be electrically connected to the driver chip 40a through the signal access pin, and the other end may extend to the display area and be electrically connected to the sub-pixel.
  • One end of the second power line 322 may extend to the signal access area B13 and be electrically connected to the driver chip 40a through the signal access pin, and the other end may extend to the display area and be electrically connected to the sub-pixel.
  • the second power line 322 may be located on the side of the first power line 321 away from the plurality of data fan-out lines 31.
  • the line width of the first power line 321 and the second power line 322 may be greater than the line width of the data fan-out line 31, or greater than the line width of the drive control line 33.
  • the line width refers to the length of the line in the direction perpendicular to the extension direction in the plane of the line extension.
  • the encapsulation structure layer may extend from the display area AA to the first peripheral area.
  • the encapsulation boundary F1 of the encapsulation structure layer in the first peripheral area may be a boundary of an inorganic encapsulation layer of the encapsulation structure layer.
  • the peripheral routing area B12 may include: a first area B121 and a second area B122.
  • the first area B121 may be an area on the side of the encapsulation boundary F1 close to the signal access area B13
  • the second area B122 may be an area on the side of the encapsulation boundary F1 close to the display area AA.
  • the encapsulation boundary F1 of the encapsulation structure layer may divide the peripheral routing area B12 into a first area B121 and a second area B122. There is no encapsulation structure layer in the first area B121, and a encapsulation structure layer may be provided in the second area B122.
  • the shaded area shown in FIG. 7 is a hole-digging area of the pixel definition layer.
  • the pixel definition layer in the shaded area of FIG. 7 is removed.
  • the pixel definition layer in the first peripheral region can be removed.
  • the shaded area shown in FIG. 8 is the first isolation region.
  • At least one of the first flat layer and the second flat layer in the first isolation region can be removed.
  • both the first flat layer and the second flat layer in the first isolation region can be removed.
  • the encapsulation boundary F1 of the encapsulation structure layer is on the substrate substrate.
  • the orthographic projection may be located in the first isolation area.
  • the first isolation area may be located at the junction of the first area B121 and the second area B122 of the peripheral wiring area B12, and overlap with the first area B121 and the second area B122 respectively.
  • the length of the first isolation area along the second direction Y may be approximately 270 microns to 330 microns, for example, approximately 300 microns.
  • the data fan-out line 31 and the drive control line 33 may be arranged in the first area B121 as double-layered lines.
  • the overlapping area between the second area B122 and the first isolation area is provided with a packaging structure layer to ensure the packaging effect.
  • the overlapping area between the first area B121 and the first isolation area is not provided with a packaging structure layer and a flat layer.
  • the first power line 321 and the second power line 322 in the first area B121 adopt a single-layered line, which can still ensure the signal transmission effect.
  • this embodiment is not limited to this.
  • the first power line and the second power line in the first area may adopt a double-layered line to further ensure the signal transmission effect.
  • FIG. 9 is a partial schematic diagram of the peripheral wiring area of at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the first source-drain metal layer in FIG. 9.
  • FIG. 11 is a schematic diagram of the first gate metal layer in FIG. 9.
  • FIG. 12 is a partial schematic diagram of the first area of at least one embodiment of the present disclosure.
  • FIG. 13 is a partial cross-sectional schematic diagram along the Q-Q’ direction in FIG. 12.
  • FIG. 14 is a schematic diagram of the first gate metal layer in FIG. 12.
  • FIG. 15 is a partial schematic diagram of the first area after the second insulating layer is formed in FIG.
  • the data fan-out line 31 may include a first routing line 311 located in the first area B121 and a second routing line 312 located in the second area B122.
  • the first routing line 311 may be a double-layer routing line, for example, it may include a first sub-routing line 311a and a second sub-routing line 311b electrically connected to each other.
  • the first sub-routing line 311a may be located on a side of the second sub-routing line 311b away from the substrate substrate.
  • the orthographic projections of the first sub-routing line 311a and the second sub-routing line 311b on the substrate substrate may at least partially overlap.
  • the orthographic projection of the first sub-routing line 311a on the substrate substrate may coincide with the orthographic projection of the second sub-routing line 311b on the substrate substrate, or the orthographic projection of the first sub-routing line 311a on the substrate substrate may be located within the orthographic projection range of the second sub-routing line 311b on the substrate substrate.
  • the second routing line 312 may be a single-layer routing line.
  • the second routing line 312 may be electrically connected to the first sub-routing line 311a, for example, it may be an integrated structure.
  • the second sub-line 311b may be electrically connected to the signal access pin 41 in the signal access area B13.
  • the second sub-line 311b and the connected signal access pin 41 may be an integral structure.
  • the first routing line 311 may extend into the second area B122.
  • the extension length L1 of the first routing line 311 in the second area B122 may be less than or equal to 300 microns, such as approximately 300 microns.
  • the first gate metal layer in the peripheral routing area may include: a second sub-routing 311b of a first routing 311 of a plurality of data fan-out lines 31.
  • the plurality of second sub-routings 311b may extend along the second direction Y and be arranged in sequence along the first direction X.
  • a plurality of vias V1 may be provided in the third insulating layer 213 in the peripheral routing area.
  • the third insulating layer 213 and the second insulating layer 212 in the plurality of vias V1 may be removed to expose the surface of the second sub-routing 311b located in the first gate metal layer.
  • the plurality of vias V1 may be arranged in an array.
  • the plurality of vias V1 corresponding to a first sub-routing 311a may be arranged in two columns along the first direction X and in multiple rows along the second direction Y.
  • the first source-drain metal layer in the peripheral routing area may include: a first sub-routing 311a of a plurality of data fan-out lines 31.
  • the plurality of first sub-routings 311a may extend along the second direction Y and be arranged in sequence along the first direction X.
  • the first sub-route 311a is arranged in sequence in the first direction X.
  • the first sub-route 311a can be electrically connected to the second sub-route 311b through a plurality of vias V1 opened in the third insulating layer 213.
  • the electrical connection between the first sub-route and the second sub-route is achieved by opening a plurality of vias, which is equivalent to connecting a plurality of parts of the first sub-route and the second sub-route in parallel, which is beneficial to reducing the impedance of the first route and improving the display effect.
  • this embodiment is not limited to this.
  • the second sub-route of the first route of the data fan-out line can be located in the second gate metal layer, and the second sub-route can be electrically connected to the first sub-route located in the first source and drain metal layer through a via opened in the third insulating layer.
  • the signal access pin 41 of the signal access area B13 can be located in the first gate metal layer. At least one signal access pin 41 is electrically connected to the second sub-route 311b of the first route 311 of the data fan-out line 31.
  • the second route 312 of the second area B122 can be located in the first source and drain metal layer and electrically connected to the first sub-route 311a of the first route 311.
  • this embodiment is not limited to this.
  • the signal access pin of the signal access area B13 can be a double-layer structure, for example, it can include a first sub-pin located in the first gate metal layer and a second sub-pin located in the first source and drain metal layer, the second sub-pin can be electrically connected to the first sub-route of the first route of the data fan-out line, for example, it can be an integrated structure; the first sub-pin can be electrically connected to the second sub-route of the first route of the data fan-out line, for example, it can be an integrated structure.
  • the first power line and the second power line in the peripheral routing area may be located in the first source-drain metal layer.
  • the resistivity of the material of the first sub-route 311a of the first route 311 of the data fan-out line 31 can be less than the resistivity of the material of the second sub-route 311b, thereby reducing the route impedance and reducing the signal transmission load.
  • the first sub-route can adopt a stacked structure of titanium (Ti)/aluminum (Al)/Ti
  • the material of the second sub-route can be molybdenum (Mo). Since the flat layer of the overlapping area of the first isolation region and the first region B121 will be removed, it is easy to cause the aluminum oxidation top titanium of the first source and drain metal layer to collapse during the preparation process, affecting the signal transmission.
  • the situation that the aluminum oxidation causes the top titanium to collapse and affects the signal transmission during the preparation process can be improved.
  • the first gate metal layer and the first source and drain metal layer are used to transmit the signal, which can ensure the signal transmission effect to ensure the display effect.
  • the first area is not covered by the packaging structure layer, which can easily cause damage to the routing of the titanium/aluminum/titanium stacked structure (for example, routing damage is likely to occur during the trust test). After improving the routing settings of the peripheral routing area, this example can meet the requirements of the trust test and reduce the routing damage caused during the trust test.
  • the following is an example of the preparation process of the display panel.
  • the "patterning process” mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist.
  • Deposition can be carried out by any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more selected from spraying and spin coating, and etching can be carried out by any one or more selected from dry etching and wet etching.
  • Thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process.
  • the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”.
  • the "thin film” still requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the "layer” after the patterning process contains at least one "pattern”.
  • a and B are of the same layer structure
  • a and B are formed simultaneously by the same patterning process.
  • the same layer does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the manufacturing process of the display panel of this embodiment may include the following steps.
  • the base substrate may be a rigid substrate, such as a glass substrate.
  • a buffer film and a semiconductor film are sequentially deposited on a substrate, and the semiconductor film is patterned by a patterning process to form a semiconductor layer.
  • the semiconductor layer in the display area may include: an active layer of a transistor of a pixel circuit.
  • a first gate metal layer Prepares a first gate metal layer.
  • a first insulating film and a first metal film are sequentially deposited on a substrate substrate forming the aforementioned structure, and the first metal film is patterned by a patterning process to form a first insulating layer covering the semiconductor layer and a first gate metal layer disposed on the first insulating layer.
  • the first gate metal layer in the display area may include: a gate of a transistor of a pixel circuit and a first capacitor plate of a storage capacitor; the first gate metal layer in the first peripheral area may include: a second sub-line of a first line of a signal lead-out line (for example, a data fan-out line, a drive control line) located in a first area of the peripheral wiring area, and a plurality of signal access pins located in a signal access area.
  • a signal lead-out line for example, a data fan-out line, a drive control line
  • a second gate metal layer a second insulating film and a second metal film are sequentially deposited on the substrate substrate forming the aforementioned structure, and the second metal film is patterned by a patterning process to form a second insulating layer covering the first gate metal layer and a second gate metal layer disposed on the second insulating layer.
  • the second gate metal layer in the display area may include: a second capacitor plate of a storage capacitor of a pixel circuit.
  • a third insulating film is deposited on the substrate substrate forming the aforementioned structure, and the third insulating film is patterned by a patterning process to form a third insulating layer.
  • the third insulating layer in the display area is provided with a plurality of pixel vias; the plurality of pixel vias can expose the surface of the semiconductor layer, the first gate metal layer or the second gate metal layer.
  • the third insulating layer in the first peripheral area is provided with a plurality of vias, and the third insulating layer and the second insulating layer in the plurality of vias can be removed to expose a portion of the surface of the second sub-line located in the first gate metal layer.
  • a third metal film is deposited on a substrate substrate forming the aforementioned structure, and the third metal film is patterned by a patterning process to form a first source-drain metal layer.
  • the first source-drain metal layer in the display area may include: a first electrode and a second electrode of a transistor of a pixel circuit.
  • the first source-drain metal layer in the first peripheral area may include: a second routing of a signal lead-out line (for example, including a data fan-out line and a drive control line) located in the peripheral routing area and a first sub-routing of the first routing, a first power line, and a second power line.
  • a first flat film is coated on the base substrate forming the aforementioned structure, and a first flat layer is formed by a patterning process; then a first passivation film is deposited, and a first passivation layer is formed by a patterning process; then a fourth metal film is deposited, and the fourth metal film is patterned by a patterning process to form a second source-drain metal layer.
  • the second source-drain metal layer in the display area may include: an anode connection electrode, and the anode connection electrode may connect the pixel circuit and the anode of the light-emitting element.
  • a second passivation film is deposited, and a second passivation layer is formed by a patterning process; subsequently, a second flat film is coated, and a second flat layer is formed by a patterning process.
  • the first flat layer and the second flat layer in the first isolation area of the first peripheral area can be removed.
  • an anode film is deposited on a substrate substrate forming the aforementioned structure, and the anode film is patterned by a patterning process to form an anode layer; then, a pixel definition film is coated, and a pixel definition layer pattern is formed by masking, exposure, and development processes. The pixel definition layer is formed in the display area. Subsequently, an organic light-emitting layer and a cathode layer are sequentially formed on the substrate substrate forming the aforementioned pattern.
  • the organic light-emitting layer includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are formed in a pixel opening in the display area to achieve connection between the organic light-emitting layer and the anode.
  • a portion of the cathode layer is formed on the organic light-emitting layer.
  • the packaging structure layer can be a stacked structure of inorganic material/organic material/inorganic material.
  • an inorganic packaging layer can be formed by depositing inorganic materials by chemical vapor deposition.
  • the packaging boundary of the packaging structure layer in the first peripheral area can be located in the aforementioned first isolation area. In the overlapping area of the first isolation area and the first area of the peripheral wiring area, no flat layer and packaging structure layer are set.
  • the wiring located in the first source and drain metal layer adopts a stacked structure of titanium, aluminum and titanium, during the preparation process, aluminum oxidation occurs, which can cause the top layer of titanium to collapse and cause poor signal transmission.
  • the wiring in the first area to a double-layer structure (located in the first gate metal layer and the first source and drain metal layer), the poor signal transmission caused by the collapse of the top layer of titanium due to aluminum oxidation can be improved, the signal transmission effect can be guaranteed, and the wiring impedance can be reduced to improve the display effect.
  • the preparation process of this exemplary embodiment can be realized by using existing mature preparation equipment, and can be well compatible with existing preparation processes.
  • the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.
  • the structure of the display panel of this exemplary embodiment and its preparation process are merely exemplary.
  • the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the second sub-line of the first line of the signal lead-out line in the first peripheral area may be located in the second gate metal layer.
  • the plurality of signal lead-out lines may include: a plurality of data fan-out lines, and a plurality of drive control lines may use a single-layer line. This embodiment is not limited to this.
  • the embodiment of the present disclosure further provides a display device, including the display panel of the above embodiment.
  • the display panel may be an OLED display panel.
  • the display device may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, or any other product or component with a display function.
  • the embodiment is not limited thereto.

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Abstract

一种显示面板，包括：衬底基板、显示结构层、封装结构层以及多条信号引出线。衬底基板包括：显示区域、位于显示区域一侧的信号接入区域、以及位于显示区域和信号接入区域之间的周边走线区域。封装结构层从显示区域延伸至周边走线区域。周边走线区域包括：位于封装结构层的封装边界靠近信号接入区域一侧的第一区域。多条信号引出线位于周边走线区域。至少一条信号引出线包括位于第一区域的第一走线，第一走线为双层走线。

Description

显示面板及显示装置
本申请要求于2022年11月10日提交中国专利局、申请号为202211407849.1、发明名称为“显示面板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板及显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，例如，液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、场发射显示器(FED，Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及显示装置。
一方面，本实施例提供一种显示面板，包括：衬底基板、显示结构层、封装结构层以及多条信号引出线。衬底基板包括：显示区域、位于显示区域一侧的信号接入区域、以及位于显示区域和信号接入区域之间的周边走线区域。显示结构层位于显示区域。封装结构层位于显示结构层远离衬底基板的一侧。封装结构层从显示区域延伸至周边走线区域。周边走线区域包括：位于封装结构层的封装边界靠近信号接入区域一侧的第一区域。多条信号引出线位于周边走线区域。至少一条信号引出线包括位于第一区域的第一走线，第一走线为双层走线。
在一些示例性实施方式中，所述周边走线区域还包括：位于所述封装结构层的封装边界靠近所述显示区域一侧的第二区域；所述第一走线延伸至所述第二区域的长度小于或等于300微米。
在一些示例性实施方式中，所述第一走线包括：相互电连接的第一子走线和第二子走线，所述第一子走线位于所述第二子走线远离所述衬底基板的一侧；所述第一子走线和所述第二子走线在所述衬底基板的正投影至少部分交叠。
在一些示例性实施方式中，所述第一子走线的材料的电阻率小于所述第二子走线的材料的电阻率。
在一些示例性实施方式中，所述第一子走线和第二子走线的材料均为金属材料。
在一些示例性实施方式中，所述第一子走线为钛铝钛的层叠结构，所述第二子走线的材料包括钼。
在一些示例性实施方式中，所述第一子走线和第二子走线之间设置至少一个绝缘层，所述至少一个绝缘层开设有阵列排布的多个过孔，所述第一子走线通过所述多个过孔与所述第二子走线电连接。
在一些示例性实施方式中，所述周边走线区域还包括：位于所述封装结构层的封装边界靠近所述显示区域一侧的第二区域；所述至少一条第一信号引出线还包括：位于所述第二区域的第二走线，所述第二走线与所述第一走线的第一子走线为一体结构。
在一些示例性实施方式中，所述信号接入区域包括多个信号接入引脚，所述第二子走线与至少一个信号接入引脚电连接。
在一些示例性实施方式中，在垂直于所述显示面板的方向上，所述显示面板包括：依次设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。其中，所述第一子走线位于所述第一源漏金属层，所述第二子走线位于所述第一栅金属层或第二栅金属层。
在一些示例性实施方式中，所述第一源漏金属层和第二源漏金属层之间依次设置第一平坦层和第一钝化层，所述第二源漏金属层远离所述衬底基板一侧依次设置第二钝化层和第二平坦层。
在一些示例性实施方式中，所述周边走线区域具有第一隔离区域，所述第一隔离区域内的第一平坦层和第二平坦层中的至少之一被去除，所述第一隔离区域与所述封装结构层部分交叠；所述第一走线与所述第一隔离区域部分交叠。
在一些示例性实施方式中，所述多条信号引出线包括：多条数据扇出线；或者包括：多条数据扇出线和多条驱动控制线。
在一些示例性实施方式中，所述衬底基板为刚性基板。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的外形示意图；
图2为一种显示装置的结构示意图；
图3为一种像素电路的等效电路图；
图4为本公开至少一实施例的显示面板的显示区域的局部剖面结构示意图；
图5为本公开至少一实施例的显示面板的第一周边区域的示意图；
图6为本公开至少一实施例的第一周边区域的局部示意图；
图7和图8为本公开至少一实施例的第一周边区域的局部膜层示意图；
图9为本公开至少一实施例的周边走线区域的局部示意图；
图10为图9中的第一源漏金属层的示意图；
图11为图9中的第一栅金属层的示意图；
图12为本公开至少一实施例的第一区域的局部示意图；
图13为图12中沿Q-Q’方向的局部剖面示意图；
图14为图12中的第一栅金属层的示意图；
图15为图12中形成第二绝缘层后的第一区域的局部示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极，另外，将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是 近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
图1为一种显示装置的外形示意图，外形为一种矩形倒圆角形状。显示装置可以包括：显示面板。在一些示例中，显示面板可以为包括线性边的闭合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中，当显示面板具有线性边时，显示面板的至少一些拐角可以为曲线。当显示面板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例中，如图1所示，显示面板可以包括显示区域AA和位于显示区域AA周边的周边区域BB。在一些示例中，显示区域AA可以包括在第二方向Y上相对设置的第一边缘(下边缘)和第二边缘(上边缘)，以及在第一方向X上相对设置的第三边缘(左边缘)和第四边缘(右边缘)。相邻边缘之间可以通过弧形的倒角连接，形成倒圆角的四边形形状。在一些示例中，周边区域BB可以包括：在第二方向Y上相对设置的第一周边区域(下边框)B1和第二周边区域(上边框)B2，在第一方向X上相对设置的第三周边区域(左边框)B3和第四周边区域(右边框)B4。第一周边区域B1与第三周边区域B3和第四周边区域B4连通，第二周边区域B2与第三周边区域B3和第四周边区域B4连通。
在一些示例中，如图1所示，显示区域AA至少包括多个子像素PX、多条栅线G以及多条数据线D。多条栅线G可以沿第一方向X延伸，多条数据线D可以沿第二方向Y延伸。多条栅线G和多条数据线D在显示面板的正投影可以交叉形成多个子像素区域，每个子像素区域内设置一个子像素PX。多条数据线D与多个子像素PX电连接，多条数据线D可以被配置为向多个子像素PX提供数据信号。多条栅线G与多个子像素PX电连接，多条栅线G可以被配置为向多个子像素PX提供栅极控制信号。在一些示例中，栅极控制信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号。
在一些示例中，如图1所示，第一方向X可以是显示区域AA中栅线G的延伸方向(行方向)，第二方向Y可以是显示区域AA中数据线D的延伸方向(列方向)。第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，子像素可以包括：像素电路以及与像素电路连接的发光元件。像素电 路可以包括多个晶体管和至少一个电容。例如，像素电路可以为3T1C结构、7T1C结构、5T1C结构、8T1C结构或者8T2C结构等，其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为一种显示装置的结构示意图。在一些示例中，如图2所示，显示装置可以包括：时序控制器21、数据驱动器22、扫描驱动电路23、发光驱动电路24以及显示面板25。在一些示例中，显示面板25的显示区域可以包括规则排布的多个子像素PX。扫描驱动电路23可以配置为沿扫描线将扫描信号提供到子像素PX；数据驱动器22可以配置为沿数据线将数据电压提供到子像素PX；发光驱动电路24可以配置为沿发光控制线将发光控制信号提供到子像素PX；时序控制器21可以配置为控制扫描驱动电路23、发光驱动电路24和数据驱动器22。
在一些示例中，如图2所示，时序控制器21可以将适于数据驱动器22的规格的灰度值和控制信号提供到数据驱动器22；时序控制器21可以将适于扫描驱动电路23的规格的扫描时钟信号、扫描起始信号等提供到扫描驱动电路23；时序控制器21可以将适于发光驱动电路24的规格的发光时钟信号、发光起始信号等提供到发光驱动电路24。数据驱动器22可以利用从时序控制器21接收的灰度值和控制信号来产生将提供到数据线D1至Dn的数据电压。例如，数据驱动器22可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn。扫描驱动电路23可以通过从时序控制器21接收的扫描时钟信号、扫描起始信号等来产生将提供到扫描线S1至Sm的扫描信号。例如，扫描驱动电路23可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线。在一些示例中，扫描驱动电路23可以包括移位寄存器，可以在扫描时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动电路24可以通过从时序控制器21接收的发光时钟信号、发光起始信号等来产生将提供到发光控制线E1至Eo的发光控制信号。例如，发光驱动电路24可以将具有截止电平脉冲的发光起始信号顺序地提供到发光控制线。发光驱动电路24可以包括移位寄存器，以在发光时钟信号的控制下顺序地将截止电平脉冲形式提供的发光起始信号传输到下一级电路的方式产生发光控制信号。其中，n、m和o均为自然数。
在一些示例中，扫描驱动电路和发光驱动电路可以直接设置在显示面板上。例如，扫描驱动电路可以设置在显示面板的第三周边区域，发光驱动电路可以设置在显示面板的第 四周边区域；或者，显示面板的第三周边区域和第四周边区域均可以设置扫描驱动电路和发光驱动电路。在一些示例中，扫描驱动电路和发光驱动电路可以在形成子像素的像素电路的工艺中与子像素一起形成。
在一些示例中，数据驱动器可以设置在单独的芯片或印刷电路板上，以通过显示面板上的信号接入引脚连接到子像素。例如，数据驱动器可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在显示面板的第一周边区域，以连接到信号接入引脚。时序控制器可以与数据驱动器分开设置或者与数据驱动器一体设置。然而，本实施例对此并不限定。在一些示例中，数据驱动器可以直接设置在显示面板上。
图3为一种像素电路的等效电路图。在一些示例中，如图3所示，本示例的像素电路可以包括七个晶体管(即第一晶体管T1至第七晶体管T7)和一个存储电容Cst。其中，第三晶体管T3的栅极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第三晶体管T3还可以称为驱动晶体管。第四晶体管T4的栅极与第一扫描线GL电连接，第四晶体管T4的第一极与数据线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第四晶体管T4还可以称为数据写入晶体管。第二晶体管T2的栅极与第一扫描线GL电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第二晶体管T2还可以称为阈值补偿晶体管。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第二电源线VDD电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光元件EL的阳极电连接。第五晶体管T5和第六晶体管T6还可以称为发光控制晶体管。第一晶体管T1与第三晶体管T3的栅极电连接，并配置为对第三晶体管T3的栅极进行复位，第七晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一晶体管T1的栅极与第二扫描线RST1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连接。第七晶体管T7的栅极与第三扫描线RST2电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与发光元件EL的阳极电连接。第一晶体管T1和第七晶体管T7还可以称为复位控制晶体管。存储电容Cst的第一电容极板与第三晶体管T3的栅极电连接，存储电容Cst的第二电容极板与第二电源线VDD电连接。
在本示例中，第一节点N1为存储电容Cst、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件EL的连接点。
在一些示例中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一些示例中，第二电源线VDD可以配置为向像素电路提供恒定的第二电压信号，第一电源线VSS可以配置为向像素电路提供恒定的第一电压信号，并且第二电压信号可以大于第一电压信号。第一扫描线GL可以配置为向像素电路提供扫描信号SCAN，数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM，第二扫描线RST1可以配置为向像素电路提供第一复位控制 信号RESET1，第三扫描线RST2可以配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，第n行像素电路电连接的第二扫描线RST1可以与第n-1行像素电路的第一扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)可以相同。第n行像素电路的第三扫描线RST2可以与第n行像素电路的第一扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)可以相同。其中，n为大于0的整数。如此，可以减少显示基板的信号线，实现显示基板的窄边框设计。然而，本实施例对此并不限定。
在一些示例中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号和第二电压信号之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些实现方式中，在LTPS显示面板的制备过程中，第一周边区域的信号走线会出现信号传输不良的情况。本申请发明人经过研究发现，在LTPS显示面板的制备工艺中，第一周边区域的信号走线采用较高电阻率的金属材料(例如钼(Mo)，单位面积内钼的阻抗约为0.5欧姆(Ω))制备，存在走线阻抗较大影响信号传输效果的情况；在信号走线改用较小电阻率的材料(例如，钛/铝/钛层叠结构，单位面积内钛/铝/钛层叠结构的阻抗约为0.05Ω)制备后，虽然可以降低走线阻抗，但是受限于制备工艺，存在铝氧化导致顶层钛坍塌影响信号传输的情况。比如，在显示面板的制备过程中，在钛/铝/钛层叠结构制备之后进行平坦层的制备，一旦平坦层的涂胶工艺过程出现问题，铝容易发生氧化从而导致铝上层的钛发生坍塌。另外，显示面板在信赖性测试过程中容易产生走线受损情况。
本实施例提供一种显示面板，包括：衬底基板、显示结构层、封装结构层以及多条信号引出线。衬底基板包括：显示区域、位于显示区域一侧的信号接入区域、以及位于显示区域和信号接入区域之间的周边走线区域。显示结构层位于显示区域。封装结构层位于显示结构层远离衬底基板的一侧。封装结构层从显示区域延伸至周边走线区域。周边走线区域包括：位于封装结构层的封装边界靠近信号接入区域一侧的第一区域。多条信号引出线位于周边走线区域。至少一条信号引出线包括：位于第一区域的第一走线，第一走线为双层走线。
本实施例提供的显示面板，通过设置周边走线区域的信号引出线在第一区域采用双层走线，可以改善周边走线区域的信号传输效果，从而提高显示效果。
在一些示例性实施方式中，周边走线区域还包括：位于封装结构层的封装边界靠近显示区域一侧的第二区域。信号引出线的第一走线延伸至第二区域的长度可以小于或等于300微米。例如，第一走线延伸至第二区域的长度可以约为300微米。本示例通过设置第一走线延伸至存在封装结构层的第二区域，且延伸长度小于或等于300微米，可以匹配显示面板的封装方式，保证显示面板的封装效果。
在一些示例性实施方式中，第一走线可以包括：相互电连接的第一子走线和第二子走线，第一子走线可以位于第二子走线远离衬底基板的一侧，第一子走线和第二子走线在衬底基板的正投影可以至少部分交叠。例如，第一子走线在衬底基板的正投影可以与第二子走线在衬底基板的正投影重合。在一些示例中，第一子走线的材料的电阻率可以小于第二子走线的材料的电阻率。例如，第一子走线和第二子走线的材料可以均为金属材料。比如，第一子走线可以采用钛铝钛的层叠结构，第二子走线的材料可以包括钼。本示例通过设置第一走线为双层走线，可以减小信号引出线的阻抗，而且可以改善钛铝钛的层叠结构的走线在铝氧化导致顶层钛坍塌对信号传输的影响，从而保证显示面板的显示效果。另外，可 以避免显示面板在信赖性测试过程中产生走线受损情况。
在一些示例性实施方式中，第一子走线和第二子走线之间可以设置至少一个绝缘层，至少一个绝缘层开设有阵列排布的多个过孔，第一子走线可以通过所述多个过孔与第二子走线电连接。本示例的第一子走线和第二子走线通过阵列排布的多个过孔进行电连接，可以实现第一子走线和第二子走线之间的并联连接，从而降低信号引出线的阻抗，改善显示效果。
在一些示例性实施方式中，周边走线区域还可以包括：位于封装结构层的封装边界靠近显示区域一侧的第二区域。至少一条信号引出线还可以包括：位于第二区域的第二走线，第二走线与第一走线的第一子走线可以为一体结构。本示例将第二区域的第二走线与第一子走线设置为同层，例如采用钛铝钛的层叠结构，有利于降低信号引出线的阻抗，从而改善显示效果。
下面通过一些示例对本实施例的显示面板进行举例说明。
图4为本公开至少一实施例的显示面板的显示区域的局部剖面结构示意图。图4示意了显示区域的一个子像素的结构。在一些示例中，如图4所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、以及依次设置在衬底基板101上的显示结构层和封装结构层104。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。在一些可能的实现方式中，显示面板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例中，衬底基板101可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。
在一些示例中，每个子像素的电路结构层102可以包括构成像素电路的多个晶体管和存储电容，图4中以一个子像素的像素电路包括的一个晶体管(例如晶体管201)和一个存储电容(例如，存储电容202)为例进行示意。例如，晶体管201可以为前述像素电路中的第六晶体管或第七晶体管，存储电容202可以为前述像素电路中的存储电容Cst。
在一些示例中，如图4所示，一个子像素的电路结构层102可以包括：设置在衬底基板101上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层。其中，半导体层和衬底基板101之间可以设置缓冲层210；半导体层和第一栅金属层之间可以设置第一绝缘层211；第一栅金属层和第二栅金属层之间可以设置第二绝缘层212；第二栅金属层和第一源漏金属层之间可以设置第三绝缘层213。第一源漏金属层和第二源漏金属层之间可以设置第一平坦层214和第一钝化层215。第一钝化层215可以位于第一平坦层214远离衬底基板101的一侧。第二源漏金属层远离衬底基板101一侧可以依次设置第二钝化层216和第二平坦层217。本示例将第二源漏金属层设置在第一钝化层215和第二钝化层216之间，可以避免制备过程中第二源漏金属层无法沉积的情况，可以保证显示面板的显示效果。
在一些示例中，如图4所示，半导体层可以至少包括：晶体管201的有源层；第一栅金属层可以至少包括：晶体管201的栅极和存储电容202的第一电容极板；第二栅金属层可以至少包括：存储电容202的第二电容极板，第二电容极板在衬底基板101的正投影与第一电容极板在衬底基板101的正投影可以存在交叠；第一源漏金属层可以至少包括：晶体管201的第一极和第二极；第二源漏金属层可以至少包括：阳极连接电极203，阳极连接电极203可以电连接晶体管201的第二极和发光元件的阳极301。有源层、栅极、第一极和第二极可以组成晶体管201，第一电容极板和第二电容极板可以组成存储电容202。
在一些示例中，如图4所示，缓冲层210、第一绝缘层211、第二绝缘层212、第三 绝缘层213、第一钝化层215和第二钝化层217可以为无机绝缘层。例如，缓冲层210、第一绝缘层211、第二绝缘层212、第三绝缘层213、第一钝化层215和第二钝化层217可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。其中，第一绝缘层211和第二绝缘层212可称之为栅绝缘(GI)层，第三绝缘层213可称之为层间绝缘(ILD)层。第一平坦层214和第二平坦层216可以为有机绝缘层。第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。例如，第一栅金属层和第二栅金属层的材料可以为钼，第一源漏金属层的材料可以为钛铝钛的层叠结构。半导体层可以采用多晶硅(p-Si)等材料。
在一些示例中，如图4所示，发光结构层103可以包括阳极层、像素定义层304、有机发光层302和阴极层。阳极层可以包括发光元件的阳极301，阴极层可以包括发光元件的阴极303。阳极301可以设置在第二平坦层217上，通过第二平坦层217上开设的过孔与阳极连接电极203电连接。像素定义层304可以设置在阳极层和第二平坦层217上，像素定义层304上设置有像素开口，像素开口可以暴露出阳极301的至少部分表面。有机发光层302至少部分设置在像素开口内，有机发光层302与阳极301连接。阴极303设置在有机发光层302上，阴极303与有机发光层302连接。有机发光层302在阳极301和阴极302的驱动下出射相应颜色的光线。
在一些示例中，有机发光层302可以至少包括在阳极301上叠设的空穴注入层、空穴传输层、发光层和空穴阻挡层。在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层可以是连接在一起的共通层。然而，本实施例对此并不限定。
在一些示例中，如图4所示，封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层103。
图5为本公开至少一实施例的显示面板的第一周边区域的示意图。在一些示例中，如图5所示，显示面板的第一周边区域可以包括：位于显示区域AA一侧的信号接入区域B13、以及位于显示区域AA和信号接入区域B13之间的周边走线区域B12和周边电路区域B11。周边电路区域B11可以位于周边走线区域B12靠近显示区域AA的一侧。在第二方向Y上，第一周边区域可以包括：沿远离显示区域AA的方向依次排布的周边电路区域B11、周边走线区域B12和信号接入区域B13。
在一些示例中，信号接入区域B13可以包括多个并排平行设置的信号接入引脚，多个信号接入引脚可以沿第一方向X依次排布。多个信号接入引脚可以被配置为与柔性线路板或驱动芯片绑定连接，从而获取来自柔性线路板或驱动芯片的信号。例如，信号接入区域B13可以设置多个驱动芯片(比如，驱动芯片40a、40b、40c和40d)。多个驱动芯片可以在信号接入区域B13沿第一方向X依次排布。然而，本实施例对此并不限定。
在一些示例中，如图5所示，周边电路区域B11可以设置多路复用电路和静电释放电路(ESD)(图未示)。静电释放电路可以位于多路复用电路远离显示区域AA的一侧。多路复用电路可以包括多个复用单元，每个复用单元可以与显示区域AA内的多条数据线电连接，可以被配置为使一个信号源为所述多条数据线提供数据信号。例如，每个复用单 元可以电连接一条复用数据线，通过复用数据线可以电连接提供数据信号的信号源。复用数据线可以与静电释放电路电连接，以便释放静电。
在一些示例中，如图5所示，周边走线区域B12可以设置多条信号引出线，多条信号引出线可以包括多条数据扇出线31。多条数据扇出线31可以与周边电路区域B11的多条复用数据线电连接。例如，多条数据扇出线31与多条复用数据线可以一一对应电连接。多条数据扇出线31可以延伸至信号接入区域B13，并与信号接入区域B13内的多个信号接入引脚对应电连接。例如，数据扇出线31与信号接入引脚可以一一对应电连接。
在一些示例中，如图5所示，多条信号引出线还可以包括多条驱动控制线33。多条驱动控制线33可以位于多条数据扇出线31沿第一方向X的两侧。多条驱动控制线33可以与最左侧的驱动芯片(例如驱动芯片40a)和最右侧的驱动芯片(例如驱动芯片40d)电连接。例如，与驱动芯片40a电连接的驱动控制线33可以延伸至第三周边区域，给第三周边区域的扫描驱动电路提供控制信号；与驱动芯片40d电连接的驱动控制线33可以延伸至第四周边区域，给第四周边区域的发光驱动电路提供控制信号。然而，本实施例对此并不限定。
图6为本公开至少一实施例的第一周边区域的局部示意图。图6所示为图5中第一周边区域最靠近第三周边区域的局部的示意图。在一些示例中，如图6所示，在周边走线区域B12内，多条数据扇出线31以扇出走线方式延伸至信号接入区域B13。周边走线区域B12还设置有第一电源线321和第二电源线322。针对沿第一方向X上位于边缘的驱动芯片，第一电源线和第二电源线可以位于与该驱动芯片电连接的多条数据扇出线31靠近显示面板沿第一方向X的中线的一侧；针对沿第一方向X的两侧均有相邻驱动芯片的驱动芯片，第一电源线和第二电源线可以位于与该驱动芯片电连接的多条数据扇出线31的两侧。例如，第一电源线321和第二电源线322可以位于与驱动芯片40a电连接的多条数据扇出线31靠近第四周边区域的一侧，多条驱动控制线33可以位于与驱动芯片40a电连接的多条数据扇出线31靠近第三周边区域的一侧。例如，第一电源线321的一端可以延伸至信号接入区域B13并通过信号接入引脚与驱动芯片40a电连接，另一端可以延伸至显示区域与子像素电连接。第二电源线322的一端可以延伸至信号接入区域B13并通过信号接入引脚与驱动芯片40a电连接，另一端可以延伸至显示区域与子像素电连接。第二电源线322可以位于第一电源线321远离多条数据扇出线31的一侧。
在一些示例中，如图6所示，第一电源线321和第二电源线322的线宽可以大于数据扇出线31的线宽，也可以大于驱动控制线33的线宽。本示例中，线宽表示在走线延伸平面内，走线在延伸方向的垂直方向的长度。
在一些示例中，如图6所示，封装结构层可以从显示区域AA延伸至第一周边区域。封装结构层在第一周边区域的封装边界F1可以为封装结构层的无机封装层的边界。周边走线区域B12可以包括：第一区域B121和第二区域B122。第一区域B121可以为封装边界F1靠近信号接入区域B13一侧的区域，第二区域B122可以为封装边界F1靠近显示区域AA一侧的区域。换言之，封装结构层的封装边界F1可以将周边走线区域B12划分为第一区域B121和第二区域B122。第一区域B121没有封装结构层，第二区域B122可以设置封装结构层。
图7和图8为本公开至少一实施例的第一周边区域的局部膜层示意图。在一些示例中，图7所示的阴影区域为像素定义层的挖孔区域。图7的阴影区域内的像素定义层被去掉。例如，第一周边区域内的像素定义层可以被去掉。图8所示的阴影区域为第一隔离区域。第一隔离区域内的第一平坦层和第二平坦层中的至少一项可以被去掉。例如，第一隔离区域内的第一平坦层和第二平坦层均可以被去掉。封装结构层的封装边界F1在衬底基板的 正投影可以位于第一隔离区域。第一隔离区域可以位于周边走线区域B12的第一区域B121和第二区域B122的交界处，并与第一区域B121和第二区域B122分别存在交叠。在一些示例中，第一隔离区域沿第二方向Y的长度可以约为270微米至330微米，例如可以约为300微米。本示例通过在周边走线区域设置第一隔离区域，可以阻隔水汽进入显示区域，避免影响显示效果。
在一些示例中，如图6至图8所示，数据扇出线31和驱动控制线33位于第一区域B121内的走线可以为双层走线。第二区域B122与第一隔离区域的交叠区域设置有封装结构层可以保证封装效果，第一区域B121和第一隔离区域的交叠区域没有设置封装结构层和平坦层，通过设置信号引出线为双层走线可以保证信号传输效果，还可以匹配显示面板的封装方式。在一些示例中，由于第一电源线321和第二电源线322的线宽较大，第一电源线321和第二电源线322在第一区域B121内的走线采用单层走线，仍可以保证信号传输效果。然而，本实施例对此并不限定。在另一些示例中，第一电源线和第二电源线在第一区域内的走线可以采用双层走线，以进一步确保信号传输效果。
下面以数据扇出线为例来说明信号引出线在周边走线区域的结构。
图9为本公开至少一实施例的周边走线区域的局部示意图。图10为图9中的第一源漏金属层的示意图。图11为图9中的第一栅金属层的示意图。图12为本公开至少一实施例的第一区域的局部示意图。图13为图12中沿Q-Q’方向的局部剖面示意图。图14为图12中的第一栅金属层的示意图。图15为图12中形成第二绝缘层后的第一区域的局部示意图。
在一些示例中，如图9至图11所示，数据扇出线31可以包括位于第一区域B121的第一走线311和位于第二区域B122的第二走线312。第一走线311可以为双层走线，例如可以包括相互电连接的第一子走线311a和第二子走线311b。第一子走线311a可以位于第二子走线311b远离衬底基板的一侧。第一子走线311a和第二子走线311b在衬底基板的正投影可以至少部分交叠。例如，第一子走线311a在衬底基板的正投影可以与第二子走线311b在衬底基板的正投影重合，或者，第一子走线311a在衬底基板的正投影可以位于第二子走线311b在衬底基板的正投影范围内。第二走线312可以为单层走线。第二走线312可以与第一子走线311a电连接，例如可以为一体结构。第二子走线311b可以与信号接入区域B13内的信号接入引脚41电连接。例如，第二子走线311b和所连接的信号接入引脚41可以为一体结构。
在一些示例中，如图9所示，第一走线311可以延伸至第二区域B122内。例如，第一走线311在第二区域B122的延伸长度L1可以小于或等于300微米，比如可以约为300微米。在一些示例中，在显示面板的制备过程中封装结构层的封装边界存在一定的误差范围，通过设置第一走线的部分长度延伸至第二区域，可以使得走线排布较好地匹配封装方式，避免由于封装边界的误差导致第一区域和第二区域交界处产生封装不良情况，从而确保信号传输效果。
在一些示例中，如图14所示，周边走线区域的第一栅金属层可以包括：多条数据扇出线31的第一走线311的第二子走线311b。多条第二子走线311b可以沿第二方向Y延伸，并沿第一方向X依次排布。如图15所示，周边走线区域的第三绝缘层213可以开设有多个过孔V1。多个过孔V1内的第三绝缘层213和第二绝缘层212可以被去掉，暴露出位于第一栅金属层的第二子走线311b的表面。多个过孔V1可以阵列排布。例如，一条第一子走线311a对应的多个过孔V1可以沿第一方向X排布为两列，沿第二方向Y排布为多行。如图12所示，周边走线区域的第一源漏金属层可以包括：多条数据扇出线31的第一走线311的第一子走线311a。多条第一子走线311a可以沿第二方向Y延伸，并沿 第一方向X依次排布。第一子走线311a可以通过第三绝缘层213开设的多个过孔V1与第二子走线311b电连接。本示例通过开设多个过孔来实现第一子走线和第二子走线的电连接，相当于将第一子走线和第二子走线的多个部分进行并联连接，有利于减少第一走线的阻抗，改善显示效果。然而，本实施例对此并不限定。在另一些示例中，数据扇出线的第一走线的第二子走线可以位于第二栅金属层，第二子走线可以通过第三绝缘层开设的过孔与位于第一源漏金属层的第一子走线电连接。
在一些示例中，如图9至图15所示，信号接入区域B13的信号接入引脚41可以位于第一栅金属层。至少一个信号接入引脚41与数据扇出线31的第一走线311的第二子走线311b电连接。第二区域B122的第二走线312可以位于第一源漏金属层，并与第一走线311的第一子走线311a电连接。然而，本实施例对此并不限定。在另一些示例中，信号接入区域B13的信号接入引脚可以为双层结构，例如可以包括位于第一栅金属层的第一子引脚和位于第一源漏金属层的第二子引脚，第二子引脚可以与数据扇出线的第一走线的第一子走线电连接，例如可以为一体结构；第一子引脚可以与数据扇出线的第一走线的第二子走线电连接，例如可以为一体结构。
在一些示例中，周边走线区域的第一电源线和第二电源线可以位于第一源漏金属层。
在一些示例中，数据扇出线31的第一走线311的第一子走线311a的材料的电阻率可以小于第二子走线311b的材料的电阻率，从而可以降低走线阻抗，降低信号传输负载。例如，第一子走线可以采用钛(Ti)/铝(Al)/Ti的层叠结构，第二子走线的材料可以为钼(Mo)。由于第一隔离区域和第一区域B121的交叠区域的平坦层会被去掉，容易导致在制备过程中造成第一源漏金属层的铝氧化顶层钛坍塌影响信号传输的情况，本示例通过在第一区域排布双层走线，可以改善制备工艺过程中铝氧化导致顶层钛坍塌影响信号传输的情况，采用第一栅金属层和第一源漏金属层传输信号，可以保证信号传输效果以确保显示效果。而且，第一区域没有封装结构层覆盖，容易造成钛/铝/钛层叠结构的走线受损(例如在信赖性测试过程中容易产生走线受损情况)，本示例对周边走线区域的走线设置进行改进之后，可以满足信赖性测试的要求，减少在信赖性测试过程中产生的走线受损情况。
下面通过显示面板的制备过程进行示例说明。本公开所说的“图案化工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本公开中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例中，本实施例的显示面板的制备过程可以包括以下步骤。
(1)、提供衬底基板。在一些示例中，衬底基板可以为刚性基板，例如玻璃基板。
(2)、制备半导体层。在一些示例中，在衬底基板上依次沉积缓冲薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层。例如，显示区域的半导体层可以包括：像素电路的晶体管的有源层。
(3)、制备第一栅金属层。在一些示例中，在形成前述结构的衬底基板上，依次沉积第一绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层的第一绝缘层以及设置在第一绝缘层上的第一栅金属层。例如，显示区域的第一栅金属层可以包括：像素电路的晶体管的栅极和存储电容的第一电容极板；第一周边区域的第一栅金属层可以包括：位于周边走线区域的第一区域的信号引出线(例如包括数据扇出线、驱动控制线)的第一走线的第二子走线、以及位于信号接入区域的多个信号接入引脚。
(4)、制备第二栅金属层。在一些示例中，在形成前述结构的衬底基板上，依次沉积第二绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一栅金属层的第二绝缘层以及设置在第二绝缘层上的第二栅金属层。例如，显示区域的第二栅金属层可以包括：像素电路的存储电容的第二电容极板。
(5)、制备第三绝缘层。在一些示例中，在形成前述结构的衬底基板上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层。例如，显示区域的第三绝缘层开设有多个像素过孔；多个像素过孔可以暴露出半导体层、第一栅金属层或第二栅金属层的表面。第一周边区域的第三绝缘层开设有多个过孔，多个过孔内的第三绝缘层和第二绝缘层可以被去掉，暴露出位于第一栅金属层的第二子走线的部分表面。
(6)、制备第一源漏金属层。在一些示例中，在形成前述结构的衬底基板上，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，形成第一源漏金属层。例如，显示区域的第一源漏金属层可以包括：像素电路的晶体管的第一极和第二极。第一周边区域的第一源漏金属层可以包括：位于周边走线区域的信号引出线(例如包括数据扇出线和驱动控制线)的第二走线和第一走线的第一子走线、第一电源线和第二电源线。
(7)、制备第二源漏金属层。在一些示例中，在形成前述结构的衬底基板上涂覆第一平坦薄膜，通过图案化工艺形成第一平坦层；随后沉积第一钝化薄膜，通过图案化工艺形成第一钝化层；随后沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化，形成第二源漏金属层。例如，显示区域的第二源漏金属层可以包括：阳极连接电极，阳极连接电极可以连接像素电路和发光元件的阳极。随后，沉积第二钝化薄膜，通过图案化工艺形成第二钝化层；随后，涂覆第二平坦薄膜，通过图案化工艺形成第二平坦层。其中，第一周边区域的第一隔离区域内的第一平坦层和第二平坦层可以被去除。
(8)、制备发光结构层。在一些示例中，在形成前述结构的衬底基板上，沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层；随后，涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层图案。像素定义层形成在显示区域。随后，在形成前述图案的衬底基板上依次形成有机发光层和阴极层。例如，有机发光层包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域的像素开口内，实现有机发光层与阳极连接。阴极层的一部分形成在有机发光层上。
(9)、制备封装结构层。在一些示例中，封装结构层可以为无机材料/有机材料/无机材料的层叠结构。例如，可以采用化学气相沉积方式沉积无机材料形成无机封装层。封装结构层在第一周边区域的封装边界可以位于前述第一隔离区域。在第一隔离区域与周边走线区域的第一区域的交叠区域内，没有平坦层和封装结构层设置，位于第一源漏金属层的走线采用钛铝钛的层叠结构时，在制备工艺过程中，发生铝氧化会导致顶层钛坍塌带来信号传输不良，本示例通过设置第一区域的走线为双层结构(位于第一栅金属层和第一源漏金属层)，可以改善铝氧化导致顶层钛坍塌带来的信号传输不良，可以保证信号传输效果，而且可以降低走线阻抗，改善显示效果。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本示例性实施例的显示面板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一周边区域的信号引出线的第一走线的第二子走线可以位于第二栅金属层。又如，多条信号引出线可以包括：多条数据扇出线，多条驱动控制线可以采用单层走线。本实施例对此并不限定。
本公开实施例还提供一种显示装置，包括前述实施例的显示面板。显示面板可以为OLED显示面板。显示装置可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种显示面板，包括：
    衬底基板，至少包括：显示区域、位于所述显示区域一侧的信号接入区域、以及位于所述显示区域和所述信号接入区域之间的周边走线区域；
    显示结构层，位于所述显示区域；
    封装结构层，位于所述显示结构层远离所述衬底基板一侧，所述封装结构层从所述显示区域延伸至所述周边走线区域；所述周边走线区域包括：位于所述封装结构层的封装边界靠近所述信号接入区域一侧的第一区域；
    多条信号引出线，位于所述周边走线区域，至少一条信号引出线包括：位于所述第一区域的第一走线，所述第一走线为双层走线。
  2. 根据权利要求1所述的显示面板，其中，所述周边走线区域还包括：位于所述封装结构层的封装边界靠近所述显示区域一侧的第二区域；所述第一走线延伸至所述第二区域的长度小于或等于300微米。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一走线包括：相互电连接的第一子走线和第二子走线，所述第一子走线位于所述第二子走线远离所述衬底基板的一侧；所述第一子走线和所述第二子走线在所述衬底基板的正投影至少部分交叠。
  4. 根据权利要求3所述的显示面板，其中，所述第一子走线的材料的电阻率小于所述第二子走线的材料的电阻率。
  5. 根据权利要求4所述的显示面板，其中，所述第一子走线和第二子走线的材料均为金属材料。
  6. 根据权利要求5所述的显示面板，其中，所述第一子走线为钛铝钛的层叠结构，所述第二子走线的材料包括钼。
  7. 根据权利要求3至5中任一项所述的显示面板，其中，所述第一子走线和第二子走线之间设置至少一个绝缘层，所述至少一个绝缘层开设有阵列排布的多个过孔，所述第一子走线通过所述多个过孔与所述第二子走线电连接。
  8. 根据权利要求3至7中任一项所述的显示面板，其中，所述周边走线区域还包括：位于所述封装结构层的封装边界靠近所述显示区域一侧的第二区域；所述至少一条信号引出线还包括：位于所述第二区域的第二走线，所述第二走线与所述第一走线的第一子走线为一体结构。
  9. 根据权利要求3至8中任一项所述的显示面板，其中，所述信号接入区域包括多个信号接入引脚，所述第二子走线与至少一个信号接入引脚电连接。
  10. 根据权利要求3至9中任一项所述的显示面板，其中，在垂直于所述显示面板的方向上，所述显示面板包括：依次设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层；
    其中，所述第一子走线位于所述第一源漏金属层，所述第二子走线位于所述第一栅金属层或第二栅金属层。
  11. 根据权利要求10所述的显示面板，其中，所述第一源漏金属层和第二源漏金属层之间依次设置第一平坦层和第一钝化层，所述第二源漏金属层远离所述衬底基板一侧依次设置第二钝化层和第二平坦层。
  12. 根据权利要求11所述的显示面板，其中，所述周边走线区域具有第一隔离区域，所述第一隔离区域内的第一平坦层和第二平坦层中的至少之一被去除，所述第一隔离区域与所述封装结构层部分交叠；所述第一走线与所述第一隔离区域部分交叠。
  13. 根据权利要求1至12中任一项所述的显示面板，其中，所述多条信号引出线包括：多条数据扇出线；或者包括：多条数据扇出线和多条驱动控制线。
  14. 根据权利要求1至13中任一项所述的显示面板，其中，所述衬底基板为刚性基板。
  15. 一种显示装置，包括如权利要求1至14中任一项所述的显示面板。
PCT/CN2023/123536 2022-11-10 2023-10-09 显示面板及显示装置 WO2024099009A1 (zh)

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CN113078195A (zh) * 2021-03-25 2021-07-06 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
CN113809133A (zh) * 2021-08-20 2021-12-17 武汉天马微电子有限公司 显示面板及显示装置
CN115581098A (zh) * 2022-11-10 2023-01-06 合肥京东方卓印科技有限公司 显示面板及显示装置

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KR20210081701A (ko) * 2019-12-24 2021-07-02 엘지디스플레이 주식회사 터치 스크린 일체형 발광 표시 장치
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