WO2022222407A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022222407A1
WO2022222407A1 PCT/CN2021/127145 CN2021127145W WO2022222407A1 WO 2022222407 A1 WO2022222407 A1 WO 2022222407A1 CN 2021127145 W CN2021127145 W CN 2021127145W WO 2022222407 A1 WO2022222407 A1 WO 2022222407A1
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WIPO (PCT)
Prior art keywords
connection
base substrate
display panel
pixel circuit
insulating layer
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Application number
PCT/CN2021/127145
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English (en)
French (fr)
Inventor
黄耀
王彬艳
邱远游
刘聪
吴超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2022222407A1 publication Critical patent/WO2022222407A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED display panels have been widely used due to their advantages of self-luminescence, low driving voltage, and fast response speed.
  • the OLED display panel includes a plurality of pixel units, and each pixel unit includes a light-emitting unit and a pixel circuit unit connected with the light-emitting unit.
  • the present application provides a display panel and a display device, and the technical solutions are as follows:
  • a display panel comprising:
  • the base substrate has an adjacent first display area and a second display area;
  • the plurality of first light-emitting units are located in the first display area;
  • each of the first pixel circuit groups is electrically connected to at least one of the first light-emitting units
  • the plurality of second light-emitting units are located in the second display area;
  • the plurality of second pixel circuit groups are located in the first display area
  • one end of at least one of the first connection wires of the plurality of first connection wires is electrically connected to the at least one second light-emitting unit, and the other end of the first connection wire is electrically connected to the dummy the electrode pattern is electrically connected to the second pixel circuit group;
  • the plurality of first connection traces and the plurality of dummy electrode patterns are located at different layers.
  • the display panel further includes: a plurality of second connection wires;
  • One end of at least one of the plurality of second connection lines is electrically connected to at least one of the second light-emitting units, and the other end of the second connection line is electrically connected to the dummy electrode pattern and the second pixel circuit group electrical connection;
  • the plurality of second connection wires, the plurality of first connection wires, and the plurality of dummy electrode patterns are located in different layers.
  • the sum of the number of the plurality of first connection lines and the plurality of second connection lines included in the display panel is the same as the number of the dummy electrode patterns, and corresponds to each other one by one.
  • Each of the first connection traces and the plurality of second connection traces is electrically connected to a corresponding one of the dummy electrode patterns.
  • At least one of the dummy electrode patterns includes a main body portion and a first connection portion, the first connection portion extends along a first direction, and both the first connection trace and the second connection trace are along the first connection. Extending in two directions, the first direction and the second direction intersect;
  • the first connection portion is electrically connected to at least one of the plurality of first connection wires and the plurality of second connection wires through a via hole at the intersection.
  • each of the second pixel circuit groups includes: a source-drain metal layer on the base substrate, and the source-drain metal layer includes a source electrode and a drain electrode arranged at intervals; the display panel further includes : the first insulating layer, the second insulating layer and the third insulating layer;
  • the dummy electrode patterns are sequentially stacked in a direction away from the base substrate.
  • the plurality of dummy electrode patterns include at least: a first dummy electrode pattern and a second dummy electrode pattern;
  • the second insulating layer has a plurality of first via holes and a plurality of second via holes;
  • the three insulating layers have a plurality of third via holes corresponding to the plurality of first via holes one-to-one, and a plurality of fourth via holes corresponding to the plurality of second via holes one-to-one;
  • each of the first via holes on the base substrate at least partially overlaps with the orthographic projection of the corresponding third via hole on the base substrate, and each of the first via holes for exposing one of the first connection traces, and at least part of the first connection part in the first dummy electrode pattern is connected to the first connection trace through the third via hole and the first via hole electrical connection;
  • each of the second connection traces is located in the second via hole, each of the fourth via holes is used to expose one of the second connection traces, and the second connection trace in the second dummy electrode pattern At least part of the first connection portion is electrically connected to the second connection trace through the fourth via hole.
  • the orthographic projection of the intersection on the base substrate overlaps with the orthographic projection of the first connection portion on the base substrate.
  • the display panel further includes: a plurality of second connection parts, the second connection parts extend along a first direction, and both the first connection line and the second connection line are along the second direction extending, the first direction and the second direction intersect;
  • the second connection part and the dummy electrode pattern are located in different layers, and the second connection part is electrically connected to one of the dummy electrode patterns through a via hole, and the second connection part is also connected to the plurality of first The connection traces and at least one of the plurality of second connection traces are electrically connected through via holes at the intersection.
  • each of the second pixel circuit groups includes: a source-drain metal layer located on the base substrate, and the second connection portion is located at the same layer as the source-drain metal layer.
  • the display panel further includes: a first insulating layer, a second insulating layer and a third insulating layer;
  • the dummy electrode patterns are sequentially stacked in a direction away from the base substrate.
  • the first insulating layer has a plurality of fifth via holes, each of the fifth via holes is used to expose one of the second connection parts, and at least part of one of the first connection traces passes through a the fifth via hole is electrically connected to the second connection part;
  • the first insulating layer and the second insulating layer have a plurality of sixth via holes, each of the sixth via holes is used to expose one of the second connection parts, and at least one of the second connection traces. Part of the sixth via hole is electrically connected to the second connection part.
  • the orthographic projection of the intersection on the base substrate does not overlap with the orthographic projection of any of the dummy electrode patterns on the base substrate;
  • intersection is located in an orthographic projection of the base substrate, within an orthographic projection of the dummy electrode pattern on the base substrate.
  • each of the second pixel circuit groups includes: a source-drain metal layer on the base substrate, and the source-drain metal layer includes a source electrode and a drain electrode arranged at intervals;
  • the display panel further includes : the first insulating layer, the second insulating layer and the third insulating layer; the source-drain metal layer, the first insulating layer, the plurality of first connecting lines, the second insulating layer, the plurality of a second connection trace, the third insulating layer and the dummy electrode pattern are stacked in sequence along the direction away from the base substrate;
  • the second insulating layer has a plurality of seventh via holes and a plurality of eighth via holes
  • the third insulating layer has a plurality of ninth via holes corresponding to the plurality of seventh via holes one-to-one, and a plurality of ninth via holes corresponding to the plurality of seventh via holes.
  • the plurality of eighth via holes one-to-one corresponding to the plurality of tenth via holes;
  • each of the seventh via holes on the base substrate at least partially overlaps with the orthographic projection of the corresponding ninth via hole on the base substrate, and each of the seventh via holes for exposing one of the first connection wires, and the first electrode of at least one of the second light-emitting units is electrically connected to the first connection wire through the seventh via hole and the ninth via hole;
  • each of the second connection traces is located in the eighth via hole, each of the tenth via holes is used to expose one of the second connection traces, and at least one of the second light-emitting units The first electrode is electrically connected to the second connection trace through the tenth via hole.
  • the first insulating layer has a plurality of eleventh via holes
  • the second insulating layer has a plurality of twelfth via holes corresponding to the plurality of eleventh via holes one-to-one
  • the The third insulating layer has a plurality of thirteenth via holes one-to-one corresponding to the plurality of twelfth via holes
  • the orthographic projection of each of the eleventh via holes on the base substrate corresponds to the corresponding
  • the orthographic projection of the twelfth via hole on the base substrate at least partially overlaps
  • the orthographic projection of each twelfth via hole on the base substrate is the same as that of the corresponding thirteenth via hole.
  • the orthographic projections of the holes on the base substrate at least partially overlap
  • the display panel further includes: a plurality of first connection patterns and a plurality of second connection patterns corresponding to the plurality of first connection patterns one-to-one;
  • Each of the eleventh via holes is used for exposing the drain electrode of a transistor in one of the second pixel circuit groups, and at least part of one of the first connection patterns is connected to the drain electrode through the eleventh via hole Electrical connection; each of the twelfth via holes is used for exposing one of the first connection patterns, and at least part of one of the second connection patterns corresponding to one of the first connection patterns passes through the twelfth via The holes are electrically connected to the first connection patterns; each of the thirteenth via holes is used to expose one of the second connection patterns, and at least part of a dummy electrode pattern is connected to the first connection pattern through the thirteenth via holes Two connection pattern connection;
  • the plurality of first connection patterns and the plurality of first connection wirings are located on the same layer, and the plurality of second connection patterns and the plurality of second connection wirings are located on the same layer.
  • the orthographic projections of the plurality of first connection wires on the base substrate do not overlap with the orthographic projections of the plurality of second connection wires on the base substrate.
  • the orthographic projection of the plurality of first connection wires on the base substrate and the orthographic projection of the plurality of second connection wires on the base substrate are on the first side of the display panel.
  • the two directions are staggered.
  • the base substrate includes: two first display areas, and the two first display areas are located on both sides of the second display area along the first direction; the base substrate further includes : a first peripheral area and a second peripheral area, the first peripheral area and the second peripheral area are respectively located on both sides of the two first display areas; the display panel further includes: a first row driver circuit in the peripheral area and a second row driver circuit located in the second peripheral area;
  • the first row driver circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in one of the first display areas, and the second row driver circuit is electrically connected to the other of the first display areas
  • the first pixel circuit group and the second pixel circuit group in the region are electrically connected.
  • the display panel further includes: a plurality of first scan signal lines located in one of the first display areas, and a plurality of second scan signal lines located in another of the first display areas;
  • the first row driving circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in one of the first display areas through the plurality of first scanning signal lines, and the second row the driving circuit is electrically connected with the first pixel circuit group and the second pixel circuit group in the other first display area through the plurality of second scanning signal lines;
  • the plurality of first scanning signal lines and the plurality of second scanning signal lines are located in the same layer, and the orthographic projections of the plurality of first scanning signal lines on the base substrate and the plurality of Orthographic projections of the second scanning signal lines on the base substrate are all located outside the second display area.
  • the base substrate further includes: a third display area located on the same side of the first display area and the second display area; the first peripheral area and the second peripheral area are located in the The two sides of the third display area along the first direction; the display panel further includes: a plurality of third light-emitting units located in the third display area, and connected to the plurality of third light-emitting units in a one-to-one correspondence a plurality of third pixel circuit groups;
  • Both the first row driving circuit and the second row driving circuit are connected to the third pixel circuit group in the third display area.
  • the density of the plurality of third light-emitting units is greater than the density of the plurality of first light-emitting units, and is greater than the density of the plurality of second light-emitting units.
  • the shape of the second display area is a rectangle; the display panel further includes: a plurality of data lines;
  • the orthographic projection of the portion of each of the data lines located in the second display area on the base substrate is a straight line or a folded line, and is located in an area of the second display area close to the first display area.
  • each of the second light-emitting units includes: a first electrode, a light-emitting layer and a second electrode stacked in sequence along a distance away from the base substrate;
  • the plurality of dummy electrode patterns and the first electrodes are located in the same layer.
  • the orthographic projection of each dummy electrode pattern on the base substrate at least partially overlaps with the orthographic projection of at least one of the second pixel circuit groups on the base substrate, and each The orthographic projection of the dummy electrode pattern on the base substrate does not overlap with the orthographic projection of any one of the first light-emitting units on the base substrate.
  • connection between each dummy electrode pattern and the second pixel circuit group is an orthographic projection on the base substrate, and the connection with the plurality of first connection lines is on the base substrate.
  • the orthographic projections of the second connection traces do not overlap, and do not overlap with the orthographic projections of the plurality of second connection traces on the base substrate.
  • a display device comprising: a power supply assembly and the display panel according to the above aspect;
  • the power supply assembly is used for supplying power to the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a top view of a base substrate provided by an embodiment of the present application.
  • FIG. 4 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a dummy electrode pattern provided by an embodiment of the present application.
  • FIG. 6 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • Fig. 7 is the sectional view along AA direction of Fig. 6;
  • FIG. 8 is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a first connection trace and a dummy electrode pattern provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a second connection wiring and a second insulating layer provided by an embodiment of the present application.
  • FIG. 12 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a second connection trace and a dummy electrode pattern provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a second connection portion and a first insulating layer provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a second connection part and a first connection wiring provided by an embodiment of the present application.
  • 16 is a schematic diagram of a second connection portion, a first insulating layer and a second insulating layer provided by an embodiment of the present application;
  • 17 is a schematic diagram of a second connection wiring and a second connection part provided by an embodiment of the present application.
  • FIG. 18 is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application.
  • FIG. 19 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • 20 is a schematic diagram of a first connection wiring and a first electrode of a second light-emitting unit provided by an embodiment of the present application;
  • 21 is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application.
  • FIG. 22 is a schematic diagram of another third insulating layer provided by an embodiment of the present application.
  • FIG. 23 is a schematic diagram of a second connection wiring and a first electrode of a second light-emitting unit provided in an embodiment of the present application;
  • FIG. 24 is a schematic diagram of a first insulating layer and a first connection pattern provided by an embodiment of the present application.
  • 25 is a schematic diagram of a second insulating layer and a second connection pattern provided by an embodiment of the present application.
  • FIG. 26 is a schematic diagram of yet another third insulating layer provided by an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of a first light-emitting unit provided by an embodiment of the present application.
  • FIG. 28 is a schematic diagram of a first light-emitting unit and a dummy electrode pattern provided by an embodiment of the present application;
  • 29 is a schematic diagram of a second light-emitting unit and a dummy electrode pattern provided by an embodiment of the present application.
  • FIG. 30 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 31 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 32 is a partial schematic diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 33 is a partial schematic diagram of a first connection wiring and a second connection wiring provided by an embodiment of the present application.
  • 34 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • 35 is a schematic diagram of another first light-emitting unit and a dummy electrode pattern provided by an embodiment of the present application.
  • 36 is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided by an embodiment of the present application;
  • FIG. 37 is a schematic partial plane structure diagram of the active semiconductor layer of the pixel circuit in the first display area provided by the embodiment of the present application.
  • 39 is a partial schematic diagram of the second conductive layer in the first display area provided by an embodiment of the present application.
  • FIG. 40 is a partial schematic diagram of a source-drain metal layer of a first display area provided by an embodiment of the present application.
  • 41 is a schematic diagram of stacking an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer in the first display area provided by an embodiment of the present application;
  • FIG. 42 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the camera of the display device may be arranged in the display area of the display panel.
  • the pixel circuits of each light-emitting unit in the area where the camera is located are usually arranged in the non-camera area.
  • the pixel circuit located in the non-camera area is connected to the light emitting unit located in the camera area through the connecting wires, so as to provide driving signals for the light emitting unit located in the camera area.
  • Words like “include” or “include” mean that the elements or items appearing before “including” or “including” cover the elements or items listed after “including” or “including” and their equivalents, and do not exclude other component or object.
  • Words like “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial schematic diagram of a display panel provided by an embodiment of the present application. 1 and 2, the display panel 10 may include: a base substrate 101, a plurality of first light-emitting units 102, a plurality of first pixel circuit groups 103, a plurality of second light-emitting units 104, a plurality of first light-emitting units 104, Two pixel circuit groups 105 , a plurality of dummy electrode patterns 106 and a plurality of first connection wires 107 . Wherein, each pixel circuit group is not shown in FIG. 2 .
  • FIG. 3 is a top view of a base substrate provided by an embodiment of the present application. Referring to FIG. 3, it can be seen that the base substrate 101 has adjacent first display areas 101a and second display areas 101b. Two first display areas 101a and one second display area 101b are shown in FIG. 3 .
  • the second display area 101b may be an area provided with a camera.
  • a plurality of first light emitting units 102 are located in the first display area 101a, and a plurality of first pixel circuit groups 103 are located in the first display area 101a.
  • Each first pixel circuit group 103 is connected to at least one first light-emitting unit 102, and each first pixel circuit group 103 is used to provide a driving signal for at least one first light-emitting unit 102 connected thereto, and the driving signal is used for driving The first light emitting unit 102 emits light.
  • a plurality of second light emitting units 104 are located in the second display area 101b, and a plurality of second pixel circuit groups 105 are located in the first display area 101a.
  • a plurality of dummy electrode patterns 106 are located in the first display area 101a.
  • One end of at least one of the first connection wires 107 is electrically connected to the at least one second light emitting unit 104 , and the other end is electrically connected to the dummy electrode pattern 106 and the second pixel circuit group 105 . That is, one end of each first connecting wire 107 may be located in the second display area 101b, and the other end may be located in the first display area 101a.
  • the second pixel circuit group 105 located in the first display area 101a can be electrically connected to the second light-emitting unit 104 located in the second display area 101b, so that the second pixel circuit group 105 is the second light-emitting unit connected thereto.
  • 104 provides a driving signal for driving the second light-emitting unit 104 to emit light.
  • the plurality of first connection traces 107 and the plurality of dummy electrode patterns 106 are located in different layers. That is, the plurality of first connection traces 107 and the plurality of dummy electrode patterns 106 can be separately prepared by two patterning processes.
  • the first display area 101a is provided with the dummy electrode pattern 106, the first display area 101a can be provided with the area of the first light emitting unit 102 and the overlapping capacitance of the first connection trace 107, and the area where the dummy electrode pattern 106 is provided and The overlapping capacitances of the first connection traces 107 are consistent to ensure the display effect of the display panel 10 .
  • the embodiments of the present application provide a display panel, in which a first display area in the display panel is provided with a dummy electrode pattern, and the dummy electrode pattern and the first connection wiring are located on different layers. Therefore, it is convenient to make the overlapping capacitances between the regions where each pixel circuit group of the first display area is located and the first connection wirings consistent, thereby ensuring the display effect of the display panel.
  • FIG. 4 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • the display panel 10 may further include: a plurality of second connection wires 108 .
  • One end of at least one second connection wire 108 in the plurality of second connection wires 108 may be electrically connected to the at least one second light emitting unit 104, and the other end of the at least one second connection wire 108 may be electrically connected to the dummy electrode pattern 106 and the second pixel circuit group 105.
  • the plurality of second connection wires 108 , the plurality of first connection wires 107 and the plurality of dummy electrode patterns 106 are located in different layers. That is, any two of the following structures are located at different layers: a plurality of first connection wires 107 , a plurality of second connection wires 108 , and a plurality of dummy electrode patterns 106 .
  • the plurality of first connection traces 107 , the plurality of second connection traces 108 , and the plurality of dummy electrode patterns 106 need to be separately prepared by three patterning processes.
  • the space of the display panel 10 is limited, the number of the first connection wires 107 that can be arranged on the same layer is limited. Therefore, by arranging a plurality of first connection wires 107 and a plurality of second connection wires 108 on different layers, part of the second pixel circuit group 105 in the first display area 101a can pass through the first connection wires 107 It is connected to a part of the second light emitting units 104 in the second display area 101b, so as to drive the part of the second light emitting units 104 in the second display area 101b to emit light.
  • another part of the second pixel circuit group 105 in the first display area 101a can be connected to another part of the second light-emitting units 104 in the second display area 101b through the second connecting wire 108, so as to drive the pixels located in the second display area 101b.
  • the other part of the second light emitting unit 104 emits light.
  • the solution of the embodiment of the present application can increase the number of the second light-emitting units 104 that can be arranged in the second display area 101b without increasing the number of the first connection wires 107, thereby ensuring the second display area in the display panel 10. 101b display effect.
  • the second display area 101b can be provided with a large number of second light-emitting units 104, the second display area 101b can allow a larger size camera to be provided, which requires less manufacturing precision of the display panel 10.
  • the materials of the first connection traces 107 and the second connection traces 108 may be transparent materials to prevent the first connection traces 107 and the second connection traces 108 from passing through the second display area 101b rate affects.
  • the material of the first connection wire 107 and the second connection wire 108 may be indium tin oxide (ITO).
  • the extension directions of the plurality of first connection wires 107 and the plurality of second connection wires 108 may both be the second direction Y.
  • the second direction Y may be the pixel row direction of the display panel 10 .
  • the display panel 10 in the embodiment of the present application may further include a plurality of third connection wires.
  • any two of the following structures are located in different layers: a plurality of first connection wires 107 , a plurality of second connection wires 108 , a plurality of third connection wires and a plurality of dummy electrode patterns 106 .
  • the plurality of first connection traces 107 , the plurality of second connection traces 108 , the plurality of third connection traces and the plurality of dummy electrode patterns 106 are respectively prepared by four patterning processes.
  • the display panel 10 may include three layers of connection wires, and the three layers of connection wires are: a plurality of first connection wires 107 , a plurality of second connection wires 108 , and a plurality of third connection wires Wire.
  • the display panel 10 may further include more layers of connection lines, which are not limited in the embodiment of the present application.
  • the display panel 10 includes two layers of connection wires as an example for description, that is, the display panel 10 includes a plurality of first connection wires 107 and a plurality of second connection wires 108 as an example.
  • the sum of the number of the plurality of first connection lines 107 and the plurality of second connection lines 108 included in the display panel 10 may be the same as the number of the dummy electrode patterns 106 included in the display panel 10 and correspond one-to-one.
  • Each of the plurality of first connection wires 107 and the plurality of second connection wires 108 may be electrically connected to a corresponding one of the dummy electrode patterns 106 .
  • the orthographic projection of each dummy electrode pattern 106 on the base substrate 101 may at least partially overlap with the orthographic projection of the at least one second pixel circuit group 105 on the base substrate 101 .
  • the same small square is used to represent the two overlapping structures.
  • the same small square is used to represent the overlapping first light-emitting unit 102 and the first pixel circuit group 103, and is marked with 102/103.
  • the same small square is used to represent the overlapping second pixel circuit group 105 and the dummy electrode pattern 106, and is marked with 105/106.
  • the orthographic projection of each dummy electrode pattern 106 on the base substrate 101 may at least partially overlap with the orthographic projection of a second pixel circuit group 105 on the base substrate 101 .
  • each dummy electrode pattern 106 on the base substrate 101 does not overlap with the orthographic projection of any first light emitting unit 102 on the base substrate 101 .
  • the dummy electrode pattern 106 does not overlap with the first light-emitting unit 102 , which can prevent the dummy electrode pattern 106 from affecting the first light-emitting unit 102 and ensure the light-emitting effect of the first light-emitting unit 102 .
  • the second display area 101b may include a center area 101b1 and an edge area 101b2 surrounding the center area 101b1 .
  • FIG. 3 schematically shows that the shape of the second display area 101b is a rectangle, the shape of the center area 101b1 of the second display area 101b is a circle, and the edge area 101b2 is an area located in the rectangle except for the center area of the circle .
  • the center area 101b1 and the edge area 101b2 of the second display area 101b may also be in other shapes, which may be set according to actual product requirements, which are not limited in this embodiment of the present application.
  • the central area 101b can be used as an under-screen camera area, the central area 101b1 is provided with a second light-emitting unit 104, and the second pixel circuit group 105 driving the second light-emitting unit 104 to emit light is provided in the first display area 101a.
  • the central area 101b1 can be made to have a high light transmittance to realize the imaging function, and can also be connected with the pixel circuit groups in other areas (the first display area 101a) to realize light emission, without affecting the display function of the screen. .
  • the second light-emitting unit 104 in the second display area 101b may be controlled in half left and right, and the two first display areas are axisymmetric with respect to the center line extending in the first direction X
  • the second pixel circuit group 105 in 101a is controlled separately.
  • the second light emitting unit 104 located on the left side of the center line is controlled by the second pixel circuit group 105 in the first display area 101a located on the left side of the center line
  • the second light emitting unit 104 located on the right side of the center line is controlled by the second pixel circuit group 105 located on the left side of the center line.
  • the first direction X may be the pixel column direction of the display panel 10 .
  • the orthographic projections of the plurality of first connection wires 107 on the base substrate 101 do not overlap with the orthographic projections of the plurality of second connection wires 108 on the base substrate 101 . Therefore, the possibility of overlapping capacitances between the plurality of first connection wires 107 and the plurality of second connection wires 108 can be reduced, thereby avoiding signal crosstalk.
  • the orthographic projections of the plurality of first connection wires 107 on the base substrate 101 and the orthographic projections of the plurality of second connection wires 108 on the base substrate 101 are alternately arranged in the first direction X. Therefore, the distance between the plurality of first connection traces 107 located in the same layer along the first direction X and the distance between the plurality of second connection traces 108 located in the same layer along the first direction X can be compared It can avoid the mutual influence of the connection lines on the same layer and ensure the reliability of signal transmission.
  • the orthographic projections of the plurality of first connection wires 107 on the base substrate 101 and the orthographic projections of the plurality of second connection wires 108 on the base substrate 101 may be arranged in other ways. This is not limited.
  • FIG. 5 is a schematic diagram of a dummy electrode pattern provided by an embodiment of the present application.
  • at least one dummy electrode pattern 106 includes a main body part 1061 and a first connection part 1062 , and the first connection part 1062 may extend along the first direction X.
  • the extension direction (first direction X) of the first connection portion 1062 and the extension direction (second direction Y) of the connection traces (the first connection trace 107 and the second connection trace 108) ) intersects, so the first connection portion 1062 has an intersection with at least one of the plurality of first connection wires 107 and the plurality of second connection wires 108 .
  • the first connection portion 1062 is connected to at least one of the plurality of first connection wires 107 and the plurality of second connection wires 108 through a via hole at the intersection.
  • the at least one connection trace can be electrically connected to the dummy electrode pattern 106 .
  • the dummy electrode pattern 106 can also be electrically connected to the second pixel circuit group 105 , so the at least one connection wire can be electrically connected to the second pixel circuit group 105 through the dummy electrode pattern 106 .
  • FIG. 6 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • Fig. 7 is a cross-sectional view taken along the AA direction of Fig. 6 .
  • each second pixel circuit group 105 may include: a source-drain metal layer on the base substrate 101 .
  • the source-drain metal layer includes a source electrode and a drain electrode arranged at intervals (only the drain electrode A of one transistor in the second pixel circuit group 105 is shown in FIG. 7 ).
  • the display panel 10 may further include: a first insulating layer 109 , a second insulating layer 110 and a third insulating layer 111 .
  • the first connection pattern 112 shown in FIG. 7 is located on the same layer as the plurality of first connection traces 107
  • the second connection pattern 113 shown in FIG. 7 is located at the same layer as the plurality of second connection traces 108 .
  • the source-drain metal layer, the first insulating layer 109 , the plurality of first connecting lines 107 , the second insulating layer 110 , the plurality of second connecting lines 108 , the third insulating layer 111 and the dummy electrode pattern 106 are formed along the The layers are sequentially stacked in the direction away from the base substrate 101 .
  • the first insulating layer 109 is located on the side of the source-drain metal layer away from the base substrate 101
  • the plurality of first connection traces 107 are located on the side of the first insulating layer 109 away from the base substrate 101
  • the second insulating The layer 110 is located on the side of the plurality of first connection traces 107 away from the base substrate 101
  • the plurality of second connection traces 108 is located on the side of the second insulating layer 110 away from the base substrate 101
  • the third insulating layer 111 is located on the side of the multiple layers.
  • the second connection traces 108 are located on a side away from the base substrate 101
  • the dummy electrode pattern 106 is located at a side of the third insulating layer 111 away from the plurality of second connection traces 108 .
  • the plurality of dummy electrode patterns 106 at least include: a first dummy electrode pattern and a second dummy electrode pattern. Wherein, the first dummy electrode pattern and the second dummy electrode pattern are two different dummy electrode patterns.
  • FIG. 8 is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application.
  • the second insulating layer 110 may have a plurality of first via holes (one first via hole 110 a is shown in FIG. 8 ).
  • the first via hole 110a can be used to expose a first connection trace 107 located on the side of the second insulating layer 110 close to the base substrate 101 .
  • FIG. 9 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • the third insulating layer 111 may have third via holes 111 a (one third via hole 111 a is shown in FIG. 9 ) corresponding to the plurality of first via holes 110 a one-to-one.
  • each first via hole 110 a on the base substrate 101 may at least partially overlap with the orthographic projection of the corresponding third via hole 111 a on the base substrate 101 .
  • the orthographic projection of the third via hole 111 a on the base substrate 101 is located within the orthographic projection of the corresponding first via hole 110 a on the base substrate 101 .
  • FIG. 10 is a schematic diagram of a first connection trace and a dummy electrode pattern provided by an embodiment of the present application.
  • at least part of the first connection portion 1062 of the first dummy electrode pattern of the plurality of dummy electrode patterns 106 may be located in the third via hole 111 a and the first via hole 110 a , and pass through the third via hole 111 a and the first via hole 110 a
  • the three via holes 111 a and the first via hole 110 a are electrically connected to the first connection traces 107 .
  • FIG. 11 is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application.
  • the second insulating layer 110 may have a plurality of second via holes 110b (one second via hole 110b is shown in FIG. 11 ). Also, at least a portion of each second connection trace 108 may be located in the second via hole 110b.
  • FIG. 12 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • the third insulating layer 111 may have fourth via holes 111 b (one fourth via hole 111 b is shown in FIG. 12 ) corresponding to the plurality of second via holes 110 b one-to-one. The fourth via hole 111b is used to expose a second connection trace 108 .
  • FIG. 13 is a schematic diagram of a second connection trace and a dummy electrode pattern provided by an embodiment of the present application. 11 to 13 , at least part of the first connection portion 1062 of the second dummy electrode pattern of the plurality of dummy electrode patterns 106 may be located in the fourth via hole 111b, and communicate with the fourth via hole 111b through the fourth via hole 111b. The two connection traces 108 are electrically connected.
  • the second connection trace 108 is located on the side of the second insulating layer 110 away from the base substrate 101 , whether the second via hole 110 b is provided in the second insulating layer 110 will not affect the The second connection trace 108 is connected to the first connection portion 1062 of the second dummy electrode pattern.
  • the second insulating layer 110 and the third insulating layer 111 can be manufactured by using the same mask. Therefore, the third insulating layer 111 has the fourth via hole 111b at the position, and the second insulating layer 110 also has the second via hole 110b at the corresponding position.
  • the orthographic projection of each second via hole 110 b on the base substrate 101 may at least partially overlap with the orthographic projection of the corresponding fourth via hole 111 b on the base substrate 101 .
  • the orthographic projection of the fourth via hole 111 b on the base substrate 101 is located within the orthographic projection of the corresponding second via hole 110 b on the base substrate 101 .
  • the second dummy electrode pattern can be electrically connected to a portion of the second connection trace 108 located in the second via hole 110b.
  • the second insulating layer 110 can be directly formed with a plurality of second connection traces 108 on the side of the second insulating layer 110 away from the base substrate 101 without providing a plurality of second via holes 110b. That's it.
  • part of the dummy electrode patterns (for example, the first dummy electrode pattern) in the plurality of dummy electrode patterns 106 can be electrically connected to the first connection part 1062 through the via hole, and the other part of the dummy electrode pattern can be electrically connected to the first connection trace 107
  • the first connection portion 1062 eg, the second dummy electrode pattern
  • first connection portion 1062 of the first dummy electrode pattern and the first connection trace 107 are electrically connected through the via hole, there is an intersection between the first connection portion 1062 of the first dummy electrode pattern and the first connection trace 107, and The orthographic projection of the intersection on the base substrate may overlap with the orthographic projection of the first connection portion 1062 of the first dummy electrode pattern on the base substrate.
  • first connection portion 1062 of the second dummy electrode pattern is electrically connected to the second connection trace 108 through the via hole, the first connection portion 1062 of the second dummy electrode pattern and the second connection trace 108 have an intersection.
  • the orthographic projection of the intersection on the base substrate may overlap with the orthographic projection of the first connection portion 1062 of the second dummy electrode pattern on the base substrate.
  • the orthographic projection of the intersection on the base substrate 101 may overlap with the orthographic projection of the first connection portion 1062 on the base substrate 101 .
  • the display panel 10 may further include: a plurality of second connection parts 114 .
  • the second connecting portion 114 extends along the first direction X. Since the extending direction (the first direction X) of the second connecting portion 114 intersects the extending direction (the second direction Y) of the connecting wires (the first connecting wire 107 and the second connecting wire 108 ), the second The connection portion 114 has an intersection with at least one of the plurality of first connection wires 107 and the plurality of second connection wires 108 .
  • the second connection portion 114 is electrically connected to at least one of the plurality of first connection wires 107 and the plurality of second connection wires 108 through the via hole at the intersection, and the at least one connection can be realized
  • the traces are electrically connected to the second connection portion 114 .
  • the second connection portion 114 may be located at the same layer as the source-drain metal layer of the second pixel circuit group 105 . That is, the second connecting portion 114 and the source-drain metal layer of the second pixel circuit group 105 can be prepared based on the same material and using the same patterning process.
  • the second connection part 114 and the source-drain metal layer can be prepared before At the time, the second connection portion 114 and the drain of a transistor are integrated into a structure. In this way, at least one connection wire can be electrically connected to the second pixel circuit group 105 through the second connection portion 114 .
  • the second connection portion 114 and the dummy electrode pattern 106 are located at different layers. And the second connection portion 114 can be electrically connected to a dummy electrode pattern 106 through a via hole. That is, the signal transmitted in the one dummy electrode pattern 106 may be the same as the signal transmitted in the second connection part 114 .
  • FIG. 14 is a schematic diagram of a second connection part and a first insulating layer provided by an embodiment of the present application.
  • the first insulating layer 109 may have a plurality of fifth via holes 109a (one fifth via hole 109a is shown in FIG. 14).
  • the fifth via hole 109a can be used to expose a second connection portion 114 located on the side of the first insulating layer 109 close to the base substrate 101 .
  • FIG. 15 is a schematic diagram of a second connection part and a first connection wiring according to an embodiment of the present application. Referring to FIG. 15 , at least a part of the first connection trace 107 may be located in the fifth via hole 109a and electrically connected to the second connection portion 114 through the fifth via hole 109a.
  • FIG. 16 is a schematic diagram of a second connection part, a first insulating layer and a second insulating layer provided by an embodiment of the present application.
  • the first insulating layer 109 has a plurality of sixth via holes 109b
  • the second insulating layer 110 also has a plurality of sixth via holes 110c.
  • the plurality of sixth via holes 109b in the first insulating layer 109 correspond to the plurality of sixth via holes 110c in the second insulating layer 110 one-to-one.
  • each sixth via hole 109b in the first insulating layer 109 at least partially overlaps with a corresponding one sixth via hole 110c in the second insulating layer 110 .
  • FIG. 17 is a schematic diagram of a second connection trace and a second connection portion provided by an embodiment of the present application. Referring to FIGS. 16 and 17 , at least a part of the second connection portion 114 may be located in the sixth via hole and electrically connected to the second connection trace 108 through the sixth via hole.
  • the second connection portion 114 and the connection trace (the first connection trace 107 or the second connection trace 108 ) have an intersection, and the orthographic projection of the intersection on the base substrate 101 may be with any dummy electrode pattern
  • the orthographic projections of 106 on the base substrate 101 do not overlap (eg, the intersection w1 in FIG. 6 ).
  • the orthographic projection of the intersection on the base substrate 101 is located within the orthographic projection of a dummy electrode pattern 106 on the base substrate 101 (eg, the intersection w2 in FIG. 6 ).
  • FIG. 18 is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application.
  • the second insulating layer 110 may have a plurality of seventh via holes 110d (one seventh via hole 110d is shown in FIG. 18 ).
  • the seventh via hole 110d can be used to expose a first connection trace 107 located on the side of the second insulating layer 110 close to the base substrate 101 .
  • FIG. 19 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application.
  • the third insulating layer 111 may have ninth via holes 111c (one ninth via hole 111c is shown in FIG. 19 ) corresponding to the plurality of seventh via holes 110d one-to-one.
  • each seventh via hole 110 d on the base substrate 101 may at least partially overlap with the orthographic projection of the corresponding ninth via hole 111 c on the base substrate 101 .
  • the orthographic projection of the ninth via hole 111 c on the base substrate 101 is located within the orthographic projection of the corresponding seventh via hole 110 d on the base substrate 101 .
  • FIG. 20 is a schematic diagram of a first connection line and a first electrode of a second light-emitting unit provided by an embodiment of the present application. 18 to 20 , at least part of the first electrode 1041 of at least one second light emitting unit 104 may be located in the seventh via hole 110d and the ninth via hole 111c and pass through the seventh via hole 110d and the ninth via hole 110d The hole 111c is electrically connected to the first connection trace 107 .
  • FIG. 21 is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application.
  • the second insulating layer 110 may have a plurality of eighth via holes 110e (one eighth via hole 110e is shown in FIG. 21 ). Also, at least a part of each of the second connection traces 108 may be located in the eighth via hole 110e.
  • FIG. 22 is a schematic diagram of another third insulating layer provided by an embodiment of the present application. Referring to FIG. 22 , the third insulating layer 111 may have tenth via holes 111d (one tenth via hole 111d is shown in FIG. 22 ) corresponding to the plurality of eighth via holes 110e one-to-one. The tenth via hole 111d is used to expose a second connection trace 108 .
  • FIG. 23 is a schematic diagram of a second connection wiring and a first electrode of a second light-emitting unit provided by an embodiment of the present application. 21 to 23 , at least part of the first electrode 1041 of the at least one second light emitting unit 104 may be located in the tenth via hole 111d and electrically connected to the second connection trace 108 through the tenth via hole 111d.
  • the second connection trace 108 is located on the side of the second insulating layer 110 away from the base substrate 101 , whether or not the eighth via hole 110 e is provided in the second insulating layer 110 will not affect the The second connection trace 108 is connected to the first electrode of the second light emitting unit 104 .
  • the second insulating layer 110 and the third insulating layer 111 can be manufactured by using the same mask. Therefore, the third insulating layer 111 has the tenth via hole 111d at the position, and the corresponding position in the second insulating layer 110 also has the eighth via hole 110e.
  • the orthographic projection of each eighth via hole 110 e on the base substrate 101 may at least partially overlap with the orthographic projection of the corresponding tenth via hole 111 d on the base substrate 101 .
  • the orthographic projection of the eighth via hole 110 e on the base substrate 101 is located within the orthographic projection of the corresponding tenth via hole 111 d on the base substrate 101 .
  • the first electrode 1041 of the second light emitting unit 104 can be electrically connected to a portion of the second connection trace 108 located in the eighth via hole 110e.
  • some of the first electrodes 1041 of the second light-emitting units 104 in the plurality of second light-emitting units 104 can be electrically connected to the first connection traces 107 through vias, and the first electrodes 1041 of another part of the second light-emitting units 104
  • the electrode 1041 may be electrically connected to the second connection trace 108 through a via hole.
  • the display panel 10 may further include: a plurality of first connection patterns 112 and a plurality of second connection patterns 113 corresponding to the plurality of first connection patterns 112 one-to-one.
  • One first connection pattern 112 and one second connection pattern 113 are shown in FIG. 7 .
  • FIG. 24 is a schematic diagram of a first insulating layer and a first connection pattern provided by an embodiment of the present application.
  • FIG. 25 is a schematic diagram of a second insulating layer and a second connection pattern provided by an embodiment of the present application.
  • Fig. 26 is a schematic diagram of still another third insulating layer provided by an embodiment of the present application. 24 to 26 , the first insulating layer 109 may have a plurality of eleventh via holes 109c, and the second insulating layer 110 may have a plurality of eleventh via holes 109c corresponding to the plurality of eleventh via holes 109c one-to-one.
  • the third insulating layer 111 has a plurality of thirteenth via holes 111e corresponding to the plurality of twelfth via holes 110f one-to-one.
  • the orthographic projection of each eleventh via hole 109 c on the base substrate 101 at least partially overlaps with the orthographic projection of the corresponding twelfth via hole 110 f on the base substrate 101 .
  • the orthographic projection of each twelfth via hole 110f on the base substrate 101 at least partially overlaps with the orthographic projection of the corresponding thirteenth via hole 111e on the base substrate 101 .
  • each eleventh via hole 109c is used to expose the drain of a transistor in a second pixel circuit group 105, and at least part of a first connection pattern 112 is located in the eleventh via hole 109c. inside the hole 109c and electrically connected to the drain A through the eleventh via hole 109c.
  • Each twelfth via hole 110f is used to expose a first connection pattern 112, and at least a part of a second connection pattern 113 corresponding to the first connection pattern 112 may be located in the twelfth via hole 110f and pass through the twelfth via hole 110f.
  • the twelfth via hole 110f is electrically connected to the first connection pattern 112 .
  • Each thirteenth via hole 111e is used to expose a second connection pattern 113, and at least a portion of a dummy electrode pattern 106 is located in the thirteenth via hole 111e, and is connected to the second connection pattern through the thirteenth via hole 111e 113 connections. That is, the dummy electrode pattern 106 may be connected to the drain electrode A of the second pixel circuit group 105 through the second connection pattern 113 and the first connection pattern 112 .
  • the orthographic projection of the twelfth via hole 110f on the base substrate 101 is located within the orthographic projection of the eleventh via hole 109c on the base substrate 101 , and the thirteenth via hole 111e is on the base substrate 101 The orthographic projection of is located in the orthographic projection of the twelfth via hole 110f on the base substrate 101 .
  • the first pixel circuit group 103 may also include: a source-drain metal layer located on the base substrate 101 .
  • the source-drain metal layer includes spaced source and drain electrodes.
  • FIG. 27 is a schematic structural diagram of a first light-emitting unit provided by an embodiment of the present application.
  • the first light emitting unit 102 may include a first electrode a1 , a light emitting layer a2 and a second electrode a3 stacked in sequence along a direction away from the base substrate 101 .
  • the first electrode a1 may be an anode
  • the second electrode a3 may be a cathode.
  • the drain electrode of the first pixel circuit group 103 may be electrically connected to the first electrode a1 of the first light emitting unit 102 .
  • the plurality of dummy electrode patterns 106 may be located in the same layer as the first electrode a1 in the first light emitting unit 102 . That is, the dummy electrode pattern 106 may be a dummy anode pattern.
  • the connection between the drain of a transistor in the first pixel circuit group 103 and the first electrode a1 of the first light emitting unit 102 can be referred to in FIG. 7 .
  • FIG. 7 can be used for Indicates the connection relationship between the drain of a transistor in the first pixel circuit group 103 and the first electrode a1 of the first light-emitting unit 102 .
  • the first light emitting unit 102 may further include: a pixel defining layer a4 located between the first electrode a1 and the light emitting layer a2.
  • the pixel defining layer a4 may have a plurality of openings a41 , and each opening a41 may be used to expose the first electrode a1 of a first light emitting unit 102 .
  • the orthographic projections of the plurality of openings a41 on the base substrate 101 do not overlap with the orthographic projections of any dummy electrode pattern 106 on the base substrate 101 .
  • the first electrode a1 of the first light emitting unit 102 can be brought into contact with the light emitting layer a2 to achieve light emission. Since the orthographic projections of the plurality of openings a41 on the base substrate 101 do not overlap with the orthographic projections of any dummy electrode pattern 106 on the base substrate 101 , the dummy electrode pattern 106 does not emit light.
  • the light-emitting layer and the cathode layer are not shown in the top view provided by the embodiments of the present application, and only the opening a41 of the pixel defining layer a4 is used to distinguish the first electrode a1 and the dummy electrode of the first light-emitting unit 102 Pattern 106 .
  • the pattern of the opening a41 with the pixel definition layer a4 is the first electrode a1
  • the pattern of the opening a41 without the pixel definition layer a4 is the dummy electrode pattern 106 .
  • the plurality of first light-emitting units 102 include: a plurality of first light-emitting units of a first color, a plurality of first light-emitting units of a second color, and a plurality of first light-emitting units of a third color.
  • at least one first light emitting unit of a first color, at least one first light emitting unit of a second color and at least one first light emitting unit of a third color among the plurality of first light emitting units 102 constitute a light emitting unit group b.
  • the first color, the second color and the third color may be three primary colors.
  • the first color is red (red, R)
  • the second color is green (green, G)
  • the third color is blue (blue, B).
  • the plurality of dummy electrode patterns 106 constitute at least one dummy electrode pattern group c.
  • the number of dummy electrode patterns 106 included in each dummy electrode pattern group c is equal to the number of first light-emitting units 102 included in one light-emitting unit group b.
  • each light-emitting unit group b includes: a first light-emitting unit b1 of a first color, two first light-emitting units (b21 and b22) of a second color, and a first light-emitting unit of a third color Light-emitting unit b3.
  • the two first light-emitting units (b21 and b22) of the second color may be collectively referred to as the pair of first light-emitting units of the second color b2. That is, each light-emitting unit group b includes four first light-emitting units 102 , then each dummy electrode pattern group c may also include four dummy electrode patterns 106 .
  • each dummy electrode pattern group c may be in one-to-one correspondence with the plurality of first light emitting units 102 in one light emitting unit group b, and each dummy electrode pattern 106 is associated with The shape and area of the first electrode a1 in the corresponding first light-emitting unit 102 are the same.
  • the overlapping area of the first electrode a1 and the connection traces in the first display area 101a can be made equal to that of the dummy electrode pattern.
  • 106 and the connecting lines have the same overlapping area, so that the first electrode a1 of the first display area 101a and the dummy electrode pattern 106 have the same overlapping capacitance with the connecting lines, thereby ensuring the display effect of the display panel 10 .
  • the first connection wiring 107 and the second connection wiring 108 are collectively referred to as connection wirings.
  • the plurality of second light emitting units 104 may also include: a plurality of second light emitting units of a first color, a plurality of second light emitting units of a second color, and a plurality of third color light emitting units the second light-emitting unit.
  • at least one second light emitting unit of the first color, at least one second light emitting unit of the second color and at least one second light emitting unit of the third color among the plurality of second light emitting units 104 may also constitute a light emitting unit group b.
  • each light-emitting unit group b includes: a second light-emitting unit b1 of a first color, two second light-emitting units (b21 and b22) of a second color, and a second light-emitting unit b3 of a third color.
  • the two second light emitting units (b21 and b22) of the second color may be collectively referred to as the second light emitting unit pair b2 of the second color.
  • the base substrate 101 includes two first display areas 101a.
  • the two first display areas 101a are located on two sides of the second display area 101b, respectively.
  • the base substrate 101 further includes: a first peripheral area 101d and a second peripheral area 101e.
  • the first peripheral area 101d and the second peripheral area 101e are located on two sides of the two first display areas 101a, respectively. That is, the first peripheral area 101d, the first display area 101a, the second display area 101b, the other first display area 101a, and the second peripheral area 101e are arranged along the second direction Y.
  • the first peripheral area 101d is located on the left side of the axis of the base substrate 101 along the first direction X
  • the second peripheral area 101e is located on the right side of the axis of the base substrate 101 along the first direction X.
  • FIG. 30 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the display panel 10 may further include: a first row driving circuit 115 located in the first peripheral area 101d and a second row driving circuit 116 located in the second peripheral area 101e.
  • the first row driving circuit 115 is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in a first display area 101a.
  • the second row driving circuit 116 is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in the other first display area 101a.
  • the first display area 101a where the first pixel circuit group 103 and the second pixel circuit group 105 are electrically connected to the first row driving circuit 115 is located on the left side of the axis of the base substrate 101 along the first direction X.
  • Another first display area 101a where the first pixel circuit group 103 and the second pixel circuit group 105 are electrically connected by the second row driving circuit 116 is located on the right side of the axis of the base substrate 101 along the first direction X.
  • one first display area 101a located on the left side of the axis of the base substrate 101 along the first direction X may be referred to as the left first display area 101a, and the one located on the left side of the base substrate 101 along the first direction X
  • the other first display area 101a on the right side of the axis is referred to as the right side first display area 101a.
  • the first row driving circuit 115 may be electrically connected to each pixel circuit group in the left first display area 101a to provide row driving for each pixel circuit group in the left first display area 101a Signal.
  • the first row driving circuit 115 is not electrically connected to any pixel circuit group in the right first display area 101a.
  • the second row driving circuit 116 may be electrically connected to each pixel circuit group in the right first display area 101a, so as to provide row driving signals for each pixel circuit group in the right first display area 101a. Moreover, the second row driving circuit 116 is not electrically connected to any pixel circuit group in the left first display area 101a.
  • the pixel circuit group in the first display area 101a on the left and the pixel circuit group in the first display area 101a on the right are driven by different row driving circuits, and are provided to two The row driving signals of the pixel circuit groups in the first display area 101a do not affect each other.
  • the display panel 10 may further include: a plurality of first scan signal lines 117 located in one first display area 101a, and a plurality of second scan signal lines located in another first display area 101a 118.
  • the plurality of first scan signal lines 117 and the plurality of second scan signal lines 118 may both extend along the second direction Y.
  • the first row driving circuit 115 can be electrically connected to a plurality of first scanning signal lines 117 and is connected to the first pixel circuit group 103 and the second pixel circuit group of a first display area 101a through the plurality of first scanning signal lines 117 105 Electrical connections.
  • the second row driving circuit 116 can be electrically connected to a plurality of second scanning signal lines 118 and is connected to the first pixel circuit group 103 and the second pixel circuit of another first display area 101a through the plurality of second scanning signal lines 118 Group 105 is electrically connected.
  • the plurality of first scanning signal lines 117 and the plurality of second scanning signal lines 118 may be located in the same layer, and the orthographic projections of the plurality of first scanning signal lines 117 on the base substrate 101 and the plurality of second scanning signal lines The orthographic projections of 118 on the base substrate 101 are all located outside the second display area 101b. That is, the plurality of first scanning signal lines 117 and the plurality of second scanning signal lines 118 are not located in the second display area 101b, thereby ensuring the transmittance of the second display area 101b.
  • the number of the first scan signal lines 117 included in the display panel 10 may be the same as the number of the first pixel circuit group 103 and the second pixel circuit group in one first display area 101a (left first display area 101a ) 105 includes the same number of rows of pixel circuits.
  • the number of the second scan signal lines 118 included in the display panel 10 may be the same as that of the pixel circuits included in the first pixel circuit group 103 and the second pixel circuit group 105 in the other first display area 101a (the first display area 101a on the right side).
  • the number of rows is the same.
  • the base substrate 101 may further include: a third display area 101c and a third peripheral area 101f.
  • the third display area 101c is located on the same side of the first display area 101a and the second display area 101b, and the third peripheral area 101f is located on the same side of the first display area 101a and the second display area 101b.
  • the first peripheral area 101d and the second peripheral area 101e are located on both sides of the third display area 101c along the second direction Y.
  • the base substrate 101 includes two first display areas 101a.
  • the shapes of the first display area 101a and the second display area 101b are both rectangular.
  • the first display area 101a and the second display area 101b are both located at the edge of the display area.
  • the first display area 101a, the second display area 101b and the third display area 101c are collectively referred to as display areas.
  • the edges of the first display area 101a and the second display area 101b away from the third display area 101c are in contact with the third peripheral area 101f.
  • One edge of the second display area 101b extending along the second direction Y is connected to the third display area 101c, and the other edge is connected to the third peripheral area 101f.
  • the two edges of the second display area 101b extending along the first direction X are respectively connected to the two first display areas 101a.
  • the display panel 10 may further include: a plurality of third light emitting units 119 located in the third display area 101c, and a plurality of third pixel circuit groups 120 connected to the plurality of third light emitting units 119 in a one-to-one correspondence.
  • the first row driving circuit 115 in the first peripheral area 101d and the second row driving circuit 116 in the second peripheral area 101e are both connected to the third pixel circuit group 120 in the third display area 101c. That is, both the first row driving circuit 115 and the second row driving circuit 116 can provide row driving signals for the third pixel circuit group 120, and the third pixel circuit group 120 in the third display area 101c can be driven by two rows circuit to drive.
  • the display panel 10 may include a plurality of third scan signal lines 121 .
  • One end of each third scanning signal line 121 is connected to the first row driving circuit 115 , the other end is connected to the second row driving circuit 116 , and the third scanning signal is also connected to the third pixel circuit group 120 .
  • the density of the plurality of third light-emitting units 119 is greater than the density of the plurality of first light-emitting units 102 , and is greater than the density of the plurality of second light-emitting units 104 .
  • the density (ie pixel density) of the second light-emitting units 104 in the under-screen camera area (the central area 101b1 of the second display area 101b ) is lower than the density of the third light-emitting units 119 in the normal display area (the third display area 101c ), then Cameras can be placed below areas of low pixel density that allow more light to pass through.
  • the density of the third light-emitting units 119 is greater than the density of the first light-emitting units 102 and greater than the density of the second light-emitting units 104" means that the number of the third light-emitting units 119 is greater than that of the second light-emitting units under the same area
  • the number of 104 is greater than the number of the first light-emitting units 102 .
  • the third display area 101c is the main display area and has a high resolution (pixel per inch, PPI), that is, the third display area 101c is arranged with high-density display elements
  • the third light-emitting unit 119 corresponds to a third pixel circuit group 120 , and each third light-emitting unit 119 is driven to emit light by a corresponding third pixel circuit group 120 .
  • the second display area 101b can allow the light incident from the display side of the display panel 10 to pass through the display panel 10 and reach the back side of the display panel 10, so that the sensors and other components located on the back side of the display panel 10 can work normally.
  • the example is not limited to this.
  • the second display area 101b may also allow light emitted from the back side of the display panel 10 to pass through the display panel 10 to reach the display side of the display panel 10 .
  • the first display area 101a and the second display area 101b also include a plurality of light emitting units for display.
  • the pixel circuit group that drives the light-emitting unit to emit light is usually opaque, in order to improve the transmittance of the central area 101b1 of the second display area 101b, the light-emitting unit of the second display area 101b and the pixel driving the light-emitting unit can be connected Circuit groups are physically separated.
  • the second pixel circuit group 105 connected to the light emitting unit in the second display area 101b may be disposed in the first display area 101a. That is, the second pixel circuit group 105 will occupy part of the space of the first display area 101a.
  • the remaining space of the first display area 101a is used to set the first light emitting unit 102 and the first pixel circuit group 103 of the first display area 101a.
  • each dot-filled box in the first display area 101a in FIG. 1 represents a pixel circuit group.
  • the filled box may also represent the first light-emitting unit 102 .
  • the first pixel circuit group 103 (or the first light-emitting unit 102) in the first display area 101a and the second pixel circuit group 105 connected to the second light-emitting unit 104 in the second display area 101b are in the first display area 101b.
  • Arrays are arranged in a display area 101a.
  • the resolutions of the first display area 101a and the second display area 101b are lower than the resolution of the third display area 101c, that is, the pixel density of the third display area 101c is greater than that of the first display area 101a and greater than that of the third display area 101c.
  • the pixel density of the second display area 101b is lower than the resolution of the third display area 101c, that is, the pixel density of the third display area 101c is greater than that of the first display area 101a and greater than that of the third display area 101c.
  • the display panel 10 may further include: a plurality of data lines 122 .
  • the orthographic projection of the portion of each data line 122 located in the second display area 101b on the base substrate 101 may be a straight line or a folded line, and is located close to the second display area 101b
  • the orthographic projection of the portion of each data line 122 located in the second display area 101b on the base substrate 101 may include a first line segment 1221 , a second line segment 1222 and The third line segment 1223.
  • the extension direction of the first line segment 1221 and the extension direction of the third line segment 1223 are both the second direction Y, and the extension direction of the second line segment 1222 is the first direction X.
  • first line segment 1221 is located on the side of the second display area 101b close to the third display area 101c
  • second line segment 1222 is located on the side of the second display area 101b close to the first display area 101a
  • third line segment 1223 is located on the side of the second display area 101b close to the first display area 101a.
  • the second display area 101b is close to one side of the third peripheral area 101f.
  • each data line 122 may also be located in the third peripheral area 101f, and a portion of each data line 122 located in the third peripheral area 101f may be in contact with the third line segment 1223 of the data line 122 .
  • FIG. 33 is a partial schematic diagram of a first connection wiring and a second connection wiring provided by an embodiment of the present application. Referring to FIG. 33 , it can be seen that the connections of the other ends of the plurality of first connection traces 107 and the connections of the other ends of the plurality of second connection traces 108 are both away from the first display area 101a and the second display area 101b The edges of the first display area 101a are parallel to each other, and the connections between the other ends of the plurality of first connection traces 107 and the connection between the other ends of the plurality of second connection traces 108 and the edge of the first display area 101a away from the second display area 101b The distance between them is less than the distance threshold.
  • the other end of the first connection wire 107 may be one end of the two ends of the first connection wire 107 away from the second display area 101b.
  • the other end of the second connection wire 108 may be one end of the two ends of the second connection wire 108 away from the second display area 101b.
  • the distance between the other ends of the plurality of first connection wires 107 and the edge of the first display area 101a away from the second display area 101b is designed to be small, and the other ends of the plurality of second connection wires 108 are designed to be smaller.
  • the distance between the connection line and the edge of the first display area 101a away from the second display area 101b is designed to be small, so that there are connection lines everywhere in the first display area 101a.
  • connections of the other ends of the plurality of first connection wires 107 and the connections of the other ends of the plurality of second connection wires 108 shown in FIG. 33 are collinear, and are represented by the same reference numeral e.
  • connection between the other ends of the plurality of first connection wires 107, the connection between the other ends of the plurality of second connection wires 108 and the edge of the first display area 101a away from the second display area 101b may be approximately parallel to the first direction X.
  • the connections of the other ends of the plurality of first connection wires 107 , the connections of the other ends of the plurality of second connection wires 108 and the edges of the first display area 101 a away from the second display area 101 b are collinear. That is, the other ends of the plurality of first connection wires 107 and the other ends of the plurality of second connection wires 108 can both extend to the edge of the first display area 101a away from the second display area 101b.
  • substantially refers to an allowable error range within 15%.
  • substantially parallel may mean that the included angle between the two is between 0 degrees and 30 degrees, such as 0 degrees to 10 degrees, 0 degrees to 15 degrees, and the like.
  • each first light-emitting unit 102 can be driven by at least two pixel circuits, thereby improving the brightness of the first light-emitting unit 102 and ensuring the first display area 101a.
  • the display effect of 101c is consistent with the display effect of the third display area 101c.
  • the first pixel circuit group 103 may include: a first pixel circuit 1031 .
  • the first pixel circuits 1031 in each of the first pixel circuit groups 103 are configured to be electrically connected to the at least one first light emitting unit 102 .
  • the second pixel circuit group 105 may include: a second pixel circuit 1051 .
  • the second pixel circuits 1052 included in each of the second pixel circuit groups 105 are configured to be electrically connected to the at least one second light emitting unit 104 .
  • the first pixel circuit group 103 only includes the first pixel circuit 1031 and does not include other pixel circuits, and the first pixel circuit is configured to be electrically connected to a first light-emitting unit 102, the first light-emitting unit 102 can be A pixel circuit is driven.
  • the second pixel circuit group 105 only includes the second pixel circuit 1051 and does not include other pixel circuits, and the second pixel circuit is configured to be electrically connected to a second light-emitting unit 104, the second light-emitting unit 104 can be driven by one pixel circuit.
  • the first pixel circuit group 103 only includes the first pixel circuit 1031 and does not include other pixel circuits, and the first pixel circuit is configured to be electrically connected to a plurality of first light-emitting units 102 (eg, two first light-emitting units 102 ) connected, the plurality of first light emitting units 102 can be driven by the same pixel circuit.
  • a plurality of first light-emitting units 102 eg, two first light-emitting units 102
  • the second pixel circuit group 105 only includes the second pixel circuit 1051 and does not include other pixel circuits, and the second pixel circuit is configured to be connected with a plurality of second light-emitting units 104 (for example, two second light-emitting units 104) are electrically connected, then the plurality of second light-emitting units 104 can be driven by the same pixel circuit.
  • each first pixel circuit group 103 may further include: at least one third pixel circuit 1032 . At least two pixel circuits in each first pixel circuit group 103 are configured to be electrically connected to the same first light emitting unit 103 .
  • Each second pixel circuit group 105 may further include: at least one fourth pixel circuit 1052 . At least two pixel circuits in each second pixel circuit group 105 are configured to be electrically connected to the same second light emitting unit 104 .
  • the first pixel circuit group 103 includes a first pixel circuit 1031 and a third pixel circuit 1032, and the first pixel circuit 1031 and the third pixel circuit 1032 are configured to be electrically connected to the same first light-emitting unit 102, Then the first light emitting unit 102 can be driven by two pixel circuits.
  • the first and second pixel circuits 1051 and the fourth pixel circuit 1052 are configured to be electrically connected to one second light-emitting unit 104, the second light-emitting unit 104 can be driven by two pixel circuits.
  • the first pixel circuit group 103 includes a first pixel circuit 1031 and a plurality of third pixel circuits 1032, and the first pixel circuit 1031 and the plurality of third pixel circuits 1032 are configured as the same first light-emitting unit 102 is electrically connected, then the first light-emitting unit 102 can be driven by a plurality of pixel circuits.
  • the second pixel circuit group 105 includes a second pixel circuit 1051 and a plurality of fourth pixel circuits 1052, and the second pixel circuit 1051 and the fourth pixel circuit 1052 are configured as the same second light-emitting unit 104 is electrically connected, then the second light-emitting unit 104 can be driven by a plurality of pixel circuits.
  • the electrical connection between the pixel circuit and the light-emitting unit may refer to: the pixel circuit is electrically connected to the first electrode of the light-emitting unit.
  • the pixel circuit is electrically connected to the first electrode of the light-emitting unit.
  • that at least two pixel circuits in the first pixel circuit group 103 are configured to be electrically connected to the same first light-emitting unit 102 may refer to: at least two pixel circuits in the first pixel circuit group 103 are configured to be It is electrically connected to the first electrode a1 of the same first light-emitting unit 102 .
  • the first pixel circuit group 103 includes a first pixel circuit 1031 and a third pixel circuit 1032
  • the second pixel circuit group 105 includes a second pixel circuit 1051 and a fourth pixel circuit 1052 as an example for description. .
  • the first electrode a1 of the first light emitting unit 102 includes a first pattern 102-1 and a second pattern 102-2.
  • the second pattern 102 - 2 may be used for electrical connection with at least two pixel circuits in the first pixel circuit group 103 .
  • the second pattern 102 - 2 is the connection between the first electrode a1 of the first light-emitting unit 102 and the first pixel circuit group 103 .
  • the orthographic projection of the connection between the first electrode a1 of the first light-emitting unit 102 and the first pixel circuit group 103 (the second pattern 102 - 2 ) on the base substrate 101 is aligned with the plurality of first connection traces 107
  • the orthographic projections on the base substrate 101 do not overlap, and do not overlap with the orthographic projections of the plurality of second connection traces 108 on the base substrate 101 . Therefore, the connection between the first electrode a1 and the first pixel circuit group 103 can be ensured that the connection with the first pixel circuit group 103 will not be affected by the first connection wiring 107 and the second connection wiring 108 .
  • the first light emitting unit 102 emits light normally.
  • each second light-emitting unit 104 can be driven by at least two pixel circuits, thereby improving the brightness of the second light-emitting unit 104 and ensuring the second display area 101b.
  • the display effect of 101c is consistent with the display effect of the third display area 101c.
  • the dummy electrode pattern 106 includes a third pattern 106-1 and a fourth pattern 106-2.
  • the fourth pattern 106 - 2 may be used for electrical connection with at least two pixel circuits in the second pixel circuit group 105 .
  • the fourth pattern 106 - 2 is the connection between the dummy electrode pattern 106 and the first pixel circuit group 103 .
  • the orthographic projection of the connection between the dummy electrode pattern 106 and the second pixel circuit group 105 (the fourth pattern 106 - 2 ) on the base substrate 101 , and the orthographic projection of the plurality of first connection traces 107 on the base substrate 101 The projections do not overlap, and do not overlap with the orthographic projections of the plurality of second connecting wires 108 on the base substrate 101 .
  • the connection between the dummy electrode pattern 106 and the first pixel circuit group 103 can be prevented from being affected by the first connection wiring 107 and the second connection wiring 108, and it can be ensured that the second pixel circuit group 105 passes through the
  • the dummy electrode pattern 106 drives the second light emitting unit 104 to emit light normally.
  • the structures of the first pixel circuit group 103 and the second pixel circuit group 105 may be the same, for example, both include two pixel circuits, and both the first pixel circuit group 103 and the second pixel circuit group 105 may be referred to as Pixel circuit pair f.
  • Pixel circuit pair f the two pixel circuits included in each of the first pixel circuit group 103 and the second pixel circuit group 105 may be referred to as a first pixel circuit and a second pixel circuit.
  • the third pixel circuit 1032 included in the first pixel circuit group 103 may be referred to as a second pixel circuit
  • the second pixel circuit 1051 included in the second pixel circuit group 105 may be referred to as a first pixel circuit
  • the fourth pixel circuit 1052 included in the second pixel circuit group 105 may be referred to as a second pixel circuit.
  • FIG. 36 is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided by an embodiment of the present application. Referring to FIG. 36 , at least two pixel circuits in the first pixel circuit group 103 are configured to be electrically connected to the same first light emitting unit 102 . At least two pixel circuits in the second pixel circuit group 105 are configured to be electrically connected to the same second light emitting unit 104 .
  • each pixel circuit (the first pixel circuit f1 and the second pixel circuit f2) includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7.
  • the pixel circuit of each pixel unit further includes a storage capacitor C, a first light emission control transistor T6, a second light emission control transistor T5 and a second reset transistor T1.
  • the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first pole of the storage capacitor C is electrically connected to the power signal line, and the second pole of the storage capacitor C is electrically connected to the gate of the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal;
  • the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset;
  • the first reset transistor T1 The pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive reset control signal Reset;
  • the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM;
  • the second pole of T5 is electrically connected to the second pole of the driving transistor T3, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM.
  • the above-mentioned power signal line refers to the signal line for outputting the voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the threshold compensation transistor
  • the gate of T2 is electrically connected to the second scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line may be the same or different, so that the gate of the data writing transistor T3 and the threshold compensation transistor T2 It can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the light-emitting control signals input to the first light-emitting control transistor T6 and the second light-emitting control transistor T5 may be the same, that is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may be electrically connected to The same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may also be electrically connected to different light-emitting control signal lines respectively, and the signals transmitted by different light-emitting control signal lines may be the same or different.
  • the reset control signals input to the first reset transistor T7 and the second reset transistor T1 may be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may be electrically connected to the same signal line.
  • the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines, respectively.
  • the signals on different reset control signal lines may be the same or different.
  • the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage, the same data signal Data is written through two connected data
  • the transistor T4, the two drive transistors T3 and the two threshold compensation transistors T2 respectively connected to the two connected data write transistors T4 are stored in the two N1 nodes of the two pixel circuits; in the third light-emitting stage, the two pixels
  • the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 in the circuit ie, the pixel circuit pair f composed of the first pixel circuit f1 and or the second pixel circuit f2 are all turned on, so as to transmit the same data signal It is transmitted to two N4 nodes.
  • the N4 nodes of the two pixel circuits are connected to jointly drive the same light-emitting unit B to emit light, which can achieve the purpose of increasing current and brightness.
  • the light-emitting unit B may be the first light-emitting unit 102 in the first display area 101a, or may be the second light-emitting unit 104 in the second display area 101b.
  • the pixel circuits included in the pixel circuit group may also include other numbers of transistors. , such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in this embodiment of the present application. It is only necessary to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to jointly drive the same light-emitting unit to emit light.
  • FIG. 37 is a schematic diagram of an active semiconductor layer of a pixel circuit in a first display area provided by an embodiment of the present application.
  • the active semiconductor layer 123 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 123 can be used to fabricate the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6 and first reset control transistor Active layer of T7.
  • the active semiconductor layer 123 includes the active layer pattern (channel region) and the doping region pattern (source-drain doping region) of each transistor of each pixel unit, and the active layer pattern and doping region of each transistor in the same pixel circuit.
  • the miscellaneous area pattern is set as one.
  • the active layer may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductive by doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer 123 of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source regions and drain regions) and an active layer. pattern, and the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer 123 can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 38 is a partial schematic diagram of the first conductive layer in the first display area provided by the embodiment of the present application.
  • the display panel includes a gate insulating layer on the side of the active semiconductor layer 123 away from the base substrate to insulate the above-mentioned active semiconductor layer 123 from the subsequently formed first conductive layer 124 (ie, the gate metal layer).
  • FIG. 38 shows the first conductive layer 124 included in the display panel.
  • the first conductive layer 124 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 123 .
  • the first conductive layer 124 may include the second pole CC2 of the capacitor C, a plurality of scan signal lines g1 extending along the second direction Y, a plurality of reset control signal lines g2, and a plurality of light emission control signal lines g3.
  • the first conductive layer 124 may also include a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6 and a first reset control transistor gate of transistor T7.
  • the gate of the data writing transistor T3 may be the portion where the scanning signal line g1 and the active semiconductor layer 123 overlap; the gate of the first light-emitting control transistor T6 may be the intersection of the light-emitting control signal line g3 and the active semiconductor layer 123
  • the gate of the second light-emitting control transistor T5 may be another part where the light-emitting control signal line g3 overlaps with the active semiconductor layer 123 .
  • the gate of the second reset transistor T1 is a part of the reset control signal line g2 that overlaps the active semiconductor layer 123
  • the gate of the first reset control transistor T7 is another part of the reset control signal line g2 that overlaps the active semiconductor layer 123 .
  • the threshold compensation transistor T2 may be a thin film transistor with a double gate structure, the first gate of the threshold compensation transistor T2 may be the portion where the scanning signal line g1 and the active semiconductor layer 123 overlap, and the second gate of the threshold compensation transistor T2 It may be a portion where the protruding structure P protruding from the scan signal line g1 overlaps with the active semiconductor layer 123 .
  • the gate of the driving transistor T1 can be the second electrode CC2 of the capacitor C.
  • each transistor the active semiconductor layers 123 on both sides of each channel region are conductorized by processes such as ion doping to serve as the first electrode and the second electrode of each transistor.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • one of the electrodes in addition to the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. Therefore, all or some of the transistors in the embodiments of the present application have the first electrode. and the second pole are interchangeable as required.
  • the scanning signal line g1, the reset control signal line g2 and the light emission control signal line g3 are arranged in the column direction Y.
  • the scan signal line g1 is located between the reset control signal line g2 and the light emission control signal line g3.
  • the second electrode CC2 of the capacitor C (that is, the gate electrode of the driving transistor T1) is located between the scanning signal line g1 and the light emission control signal line g3.
  • the protruding structure P protruding from the scan signal line g1 is located on the side of the scan signal line g1 away from the light emission control signal line g3.
  • a first insulating layer is formed on the above-mentioned first conductive layer 124 for insulating the above-mentioned first conductive layer 124 from the second conductive layer 125 formed subsequently.
  • FIG. 39 is a partial schematic diagram of the second conductive layer in the first display area provided by the embodiment of the present application.
  • the second conductive layer 125 includes the first pole CC1 of the capacitor C and a plurality of reset power signal lines g4 extending along the second direction Y.
  • the first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • a second insulating layer is formed on the above-mentioned second conductive layer 125 to insulate the above-mentioned second conductive layer 125 from the source-drain metal layer 126 formed subsequently.
  • FIG. 40 is a partial schematic diagram of a source-drain metal layer of the first display region provided by an embodiment of the present application.
  • FIG. 28 is a schematic diagram of stacking an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer in the first display area provided by an embodiment of the present application.
  • the source-drain metal layer 126 includes the data line 122 extending along the first direction X and the power signal line g5.
  • the data line 122 is electrically connected to the second electrode of the data writing transistor T2 through via holes penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal line g5 is electrically connected to the first electrode of the second light emission control transistor T5 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal line g5 and the data line 122 are alternately arranged along the second direction Y.
  • the power signal line g5 is electrically connected to the first electrode CC1 of the capacitor C through a via hole penetrating the second insulating layer.
  • a passivation layer and a flat layer may be provided on the side of the source-drain metal layer 126 far from the base substrate 101 to protect the source-drain metal layer 126 .
  • the first pixel circuit group 103 and the second pixel circuit group 105 may include two pixel circuits arranged along the second direction Y, that is, including one pixel circuit pair f.
  • the third pixel circuit group 120 does not include the above-mentioned pixel circuit pair f (not shown), but only includes one pixel circuit.
  • Two adjacent pixel circuits in the third pixel circuit group 120 arranged along the second direction Y respectively drive a third light emitting unit 119 to emit light, and the two data writing transistors in the two adjacent pixel circuits are independent of each other , and connect to different data lines respectively.
  • the embodiments of the present application provide a display panel, in which a first display area in the display panel is provided with a dummy electrode pattern, and the dummy electrode pattern and the first connection wiring are located on different layers. Therefore, it is convenient to make the overlapping capacitances between the regions where each pixel circuit group of the first display area is located and the first connection wirings consistent, thereby ensuring the display effect of the display panel.
  • FIG. 42 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: a power supply assembly 20 and the display panel 10 provided in the above-mentioned embodiments.
  • the power supply assembly 20 can be used to supply power to the display panel 10 .
  • the display device may be a curved display device.
  • the display device can be an organic light-emitting diode (organic light-emitting diode, OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator and any other device with display function. And products or parts with fingerprint recognition function.
  • OLED organic light-emitting diode

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Abstract

本申请公开了一种显示面板及显示装置，涉及显示技术领域。该显示面板中的第一显示区设置有虚设电极图案，该虚设电极图案与第一连接走线位于不同层。由此可以便于使得第一显示区的各个像素电路组所在区域与第一连接走线之间的交叠电容一致，进而能够保证显示面板的显示效果。

Description

显示面板及显示装置
本公开要求于2021年4月23日提交的申请号为202110443185.3、发明名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度快等优点而得到了广泛的应用。该OLED显示面板包括多个像素单元，每个像素单元包括发光单元以及与该发光单元连接的像素电路单元。
发明内容
本申请提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有相邻的第一显示区和第二显示区；
多个第一发光单元，所述多个第一发光单元位于所述第一显示区；
多个第一像素电路组，所述多个第一像素电路组位于所述第一显示区，且每个所述第一像素电路组与至少一个所述第一发光单元电连接；
多个第二发光单元，所述多个第二发光单元位于所述第二显示区；
多个第二像素电路组，所述多个第二像素电路组位于所述第一显示区；
多个虚设电极图案，位于所述第一显示区；
以及，多个第一连接走线，所述多个第一连接走线中的至少一个所述第一连接走线的一端与至少一个所述第二发光单元电连接，另一端与所述虚设电极图案和所述第二像素电路组电连接；
其中，所述多个第一连接走线和所述多个虚设电极图案位于不同层。
可选的，所述显示面板还包括：多个第二连接走线；
所述多个第二连接走线中的至少一个所述第二连接走线的一端与至少一个所述第二发光单元电连接，另一端与所述虚设电极图案和所述第二像素电路组电连接；
其中，所述多个第二连接走线和所述多个第一连接走线以及所述多个虚设电极图案均位于不同层。
可选的，所述显示面板包括的多个第一连接走线和多个第二连接走线的个数之和，与所述虚设电极图案的个数相同，且一一对应，所述多个第一连接走线和所述多个第二连接走线中的每个与对应的一个所述虚设电极图案电连接。
可选的，至少一个所述虚设电极图案包括主体部和第一连接部，所述第一连接部沿第一方向延伸，所述第一连接走线和所述第二连接走线均沿第二方向延伸，所述第一方向和所述第二方向相交；
所述第一连接部与所述多个第一连接走线和所述多个第二连接走线中的至少一个在相交处通过过孔电连接。
可选的，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述源漏金属层包括间隔设置的源极和漏极；所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；
所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层，所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠。
可选的，所述多个虚设电极图案至少包括：第一虚设电极图案以及第二虚设电极图案；所述第二绝缘层具有多个第一过孔和多个第二过孔，所述第三绝缘层具有与所述多个第一过孔一一对应的多个第三过孔，以及与所述多个第二过孔一一对应的多个第四过孔；
每个所述第一过孔在所述衬底基板上的正投影，与对应的所述第三过孔在所述衬底基板上的正投影至少部分重叠，每个所述第一过孔用于露出一个所述第一连接走线，所述第一虚设电极图案中的第一连接部的至少部分通过所述第三过孔和所述第一过孔与所述第一连接走线电连接；
每个所述第二连接走线的至少部分位于所述第二过孔内，每个所述第四过孔用于露出一个所述第二连接走线，所述第二虚设电极图案中的第一连接部的至少部分通过所述第四过孔与所述第二连接走线电连接。
可选的，所述相交处在所述衬底基板上的正投影，与所述第一连接部在所 述衬底基板上的正投影重叠。
可选的，所述显示面板还包括：多个第二连接部，所述第二连接部沿第一方向延伸，所述第一连接走线和所述第二连接走线均沿第二方向延伸，所述第一方向和所述第二方向相交；
所述第二连接部与所述虚设电极图案位于不同层，且所述第二连接部与一个所述虚设电极图案通过过孔电连接，所述第二连接部还和所述多个第一连接走线以及所述多个第二连接走线中的至少一个在相交处通过过孔电连接。
可选的，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述第二连接部与所述源漏金属层位于同层。
可选的，所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；
所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层，所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠。
可选的，所述第一绝缘层具有多个第五过孔，每个所述第五过孔用于露出一个所述第二连接部，一个所述第一连接走线的至少部分通过一个所述第五过孔与所述第二连接部电连接；
所述第一绝缘层和所述第二绝缘层具有多个第六过孔，每个所述第六过孔用于露出一个所述第二连接部，一个所述第二连接走线的至少部分通过一个所述第六过孔与所述第二连接部电连接。
可选的，所述相交处在所述衬底基板上的正投影，与任一所述虚设电极图案在所述衬底基板上的正投影不重叠；
或者，所述相交处在所述衬底基板上的正投影，位于一个所述虚设电极图案在所述衬底基板上的正投影内。
可选的，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述源漏金属层包括间隔设置的源极和漏极；所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层，所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠；
所述第二绝缘层具有多个第七过孔和多个第八过孔，所述第三绝缘层具有与所述多个第七过孔一一对应的多个第九过孔，以及与所述多个第八过孔一一对应的多个第十过孔；
每个所述第七过孔在所述衬底基板上的正投影，与对应的所述第九过孔在所述衬底基板上的正投影至少部分重叠，每个所述第七过孔用于露出一个所述第一连接走线，至少一个所述第二发光单元的第一电极通过所述第七过孔和所述第九过孔与所述第一连接走线电连接；
每个所述第二连接走线的至少部分位于所述第八过孔内，每个所述第十过孔用于露出一个所述第二连接走线，至少一个所述第二发光单元的第一电极通过所述第十过孔与所述第二连接走线电连接。
可选的，所述第一绝缘层具有多个第十一过孔，所述第二绝缘层具有与所述多个第十一过孔一一对应的多个第十二过孔，所述第三绝缘层具有与所述多个第十二过孔一一对应的多个第十三过孔；每个所述第十一过孔在所述衬底基板上的正投影，与对应的所述第十二过孔在所述衬底基板上的正投影至少部分重叠，每个所述第十二过孔在所述衬底基板上的正投影，与对应的所述第十三过孔在所述衬底基板上的正投影至少部分重叠；所述显示面板还包括：多个第一连接图案以及与所述多个第一连接图案一一对应的多个第二连接图案；
每个所述第十一过孔用于露出一个所述第二像素电路组中一个晶体管的漏极，一个所述第一连接图案的至少部分通过所述第十一过孔与所述漏极电连接；每个所述第十二过孔用于露出一个所述第一连接图案，与一个所述第一连接图案对应的一个所述第二连接图案的至少部分通过所述第十二过孔与所述第一连接图案电连接；每个所述第十三过孔用于露出一个所述第二连接图案，一个虚设电极图案的至少部分通过所述第十三过孔与所述第二连接图案连接；
其中，所述多个第一连接图案与所述多个第一连接走线位于同层，所述多个第二连接图案与所述多个第二连接走线位于同层。
可选的，所述多个第一连接走线在所述衬底基板上的正投影与所述多个第二连接走线在所述衬底基板上的正投影不重叠。
可选的，所述多个第一连接走线在所述衬底基板上的正投影与所述多个第二连接走线在所述衬底基板上的正投影在所述显示面板的第二方向上交错排布。
可选的，所述衬底基板包括：两个所述第一显示区，两个所述第一显示区位于所述第二显示区沿第一方向的两侧；所述衬底基板还包括：第一周边区和第二周边区，所述第一周边区和所述第二周边区分别位于两个所述第一显示区的两侧；所述显示面板还包括：位于所述第一周边区的第一行驱动电路和位于 所述第二周边区的第二行驱动电路；
所述第一行驱动电路与一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接，所述第二行驱动电路与另一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接。
可选的，所述显示面板还包括：位于一个所述第一显示区的多个第一扫描信号线，以及位于另一个所述第一显示区的多个第二扫描信号线；
所述第一行驱动电路通过所述多个第一扫描信号线与一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接，所述第二行驱动电路通过所述多个第二扫描信号线与另一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接；
其中，所述多个第一扫描信号线与所述多个第二扫描信号线位于同层，且所述多个第一扫描信号线在所述衬底基板上的正投影以及所述多个第二扫描信号线在所述衬底基板上的正投影均位于所述第二显示区之外。
可选的，所述衬底基板还包括：位于所述第一显示区和所述第二显示区同一侧的第三显示区；所述第一周边区和所述第二周边区位于所述第三显示区沿所述第一方向的两侧；所述显示面板还包括：位于所述第三显示区的多个第三发光单元，以及与所述多个第三发光单元一一对应连接的多个第三像素电路组；
所述第一行驱动电路和所述第二行驱动电路均与所述第三显示区中的所述第三像素电路组连接。
可选的，所述多个第三发光单元的密度大于所述多个第一发光单元的密度，且大于所述多个第二发光单元的密度。
可选的，所述第二显示区的形状为矩形；所述显示面板还包括：多个数据线；
每个所述数据线位于所述第二显示区的部分在所述衬底基板上的正投影呈直线或折线，且位于所述第二显示区靠近所述第一显示区的区域。
可选的，每个所述第二发光单元包括：沿远离所述衬底基板的依次层叠的第一电极，发光层以及第二电极；
其中，所述多个虚设电极图案与所述第一电极位于同层。
可选的，每个所述虚设电极图案在所述衬底基板上的正投影，与至少一个所述第二像素电路组在所述衬底基板上的正投影至少部分重叠，且每个所述虚设电极图案在所述衬底基板上的正投影与任一所述第一发光单元在所述衬底基 板上的正投影不重叠。
可选的，每个所述虚设电极图案与所述第二像素电路组的连接处在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，且与所述多个第二连接走线在所述衬底基板上的正投影不重叠。
另一方面，提供了一种显示装置，所述显示装置包括：供电组件以及如上述方面所述的显示面板；
所述供电组件用于为所述显示面板供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的一种显示面板的局部示意图；
图3是本申请实施例提供的一种衬底基板的俯视图；
图4是本申请实施例提供的另一种显示面板的局部示意图；
图5是本申请实施例提供的一种虚设电极图案的示意图；
图6是本申请实施例提供的又一种显示面板的局部示意图；
图7是图6沿AA方向的截面图；
图8是本申请实施例提供的第一连接走线和第二绝缘层的局部示意图；
图9是本申请实施例提供的一种第三绝缘层的局部示意图；
图10是本申请实施例提供的一种第一连接走线与虚设电极图案的示意图；
图11是本申请实施例提供的一种第二连接走线和第二绝缘层的示意图；
图12是本申请实施例提供的一种第三绝缘层的局部示意图；
图13是本申请实施例提供的一种第二连接走线与虚设电极图案的示意图；
图14是本申请实施例提供的一种第二连接部和第一绝缘层的示意图；
图15是本申请实施例提供的一种第二连接部和第一连接走线的示意图；
图16是本申请实施例提供的一种第二连接部，第一绝缘层和第二绝缘层的示意图；
图17是本申请实施例提供的一种第二连接走线与第二连接部的示意图；
图18是本申请实施例提供的第一连接走线和第二绝缘层的局部示意图；
图19是本申请实施例提供的一种第三绝缘层的局部示意图；
图20是本申请实施例提供的一种第一连接走线与第二发光单元的第一电极的示意图；
图21是本申请实施例提供的一种第二连接走线和第二绝缘层的示意图；
图22是本申请实施例提供的另一种第三绝缘层的示意图；
图23是本申请实施例提供的一种第二连接走线和第二发光单元的第一电极的示意图；
图24是本申请实施例提供的一种第一绝缘层和第一连接图案的示意图；
图25是本申请实施例提供的一种第二绝缘层和第二连接图案的示意图；
图26是本申请实施例提供的又一种第三绝缘层的示意图；
图27是本申请实施例提供的一种第一发光单元的结构示意图；
图28是本申请实施例提供的一种第一发光单元和虚设电极图案的示意图；
图29是本申请实施例提供的一种第二发光单元和虚设电极图案的示意图；
图30是本申请实施例提供的另一种显示面板的结构示意图；
图31是本申请实施例提供的再一种显示面板的局部示意图；
图32是本申请实施例提供的再一种显示面板的局部示意图；
图33是本申请实施例提供的一种第一连接走线和第二连接走线的局部示意图；
图34是本申请实施例提供的又一种显示面板的结构示意图；
图35是本申请实施例提供的另一种第一发光单元和虚设电极图案的示意图；
图36是本申请实施例提供的一种第一像素电路组或第二像素电路组的等效电路图；
图37是本申请实施例提供的第一显示区内的像素电路的有源半导体层的局部平面结构示意图；
图38是本申请实施例提供的第一显示区内的第一导电层的局部示意图；
图39是本申请实施例提供的第一显示区内的第二导电层的局部示意图；
图40是本申请实施例提供的第一显示区的源漏金属层的局部示意图；
图41是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层以及源漏金属层的层叠示意图；
图42是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，为了提高显示面板的屏占比，可以将显示装置的摄像头设置在显示面板的显示区域。并且，为了增大摄像头所在区域的透过率，通常将该摄像头所在区域中各发光单元的像素电路设置在非摄像头区域。位于非摄像头区域的像素电路通过连接走线与位于摄像头区域的发光单元连接，从而为位于摄像头区域的发光单元提供驱动信号。
但是，由于位于非摄像头区域各个像素电路所在区域与连接走线之间的交叠电容不一致，因此会导致显示面板的显示效果较差。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
图1是本申请实施例提供的一种显示面板的结构示意图。图2是本申请实施例提供的一种显示面板的局部示意图。结合图1和图2可以看出，该显示面板10可以包括：衬底基板101，多个第一发光单元102，多个第一像素电路组103，多个第二发光单元104，多个第二像素电路组105，多个虚设电极图案106以及多个第一连接走线107。其中，图2中未示出各个像素电路组。
图3是本申请实施例提供的一种衬底基板的俯视图。参考图3可以看出，该衬底基板101具有相邻的第一显示区101a和第二显示区101b。图3中示出了两个第一显示区101a和一个第二显示区101b。该第二显示区101b可以为设置有摄像头的区域。
结合图1至图3，多个第一发光单元102位于第一显示区101a，多个第一像素电路组103位于第一显示区101a。每个第一像素电路组103与至少一个第一发光单元102连接，且每个第一像素电路组103用于为与其连接的至少一个第一发光单元102提供驱动信号，该驱动信号用于驱动该第一发光单元102发光。
并且，结合图1至图3，多个第二发光单元104位于第二显示区101b，多个第二像素电路组105位于第一显示区101a。多个虚设电极图案106位于第一显示区101a。多个第一连接走线107中的至少一个第一连接走线107的一端与至少一个第二发光单元104电连接，另一端与虚设电极图案106和第二像素电路组105电连接。也即是，每个第一连接走线107的一端可以位于第二显示区101b，另一端可以位于第一显示区101a。由此实现位于第一显示区101a的第二像素电路组105可以与位于第二显示区101b的第二发光单元104电连接，进而使得该第二像素电路组105为与其连接的第二发光单元104提供驱动信号，该驱动信号用于驱动该第二发光单元104发光。
在本申请实施例中，多个第一连接走线107和多个虚设电极图案106位于不同层。也即是，该多个第一连接走线107，以及多个虚设电极图案106可以采用两次构图工艺分别制备。
由于第一显示区101a设置有虚设电极图案106，因此可以使得第一显示区101a设置第一发光单元102的区域和第一连接走线107的交叠电容，以及设置虚设电极图案106的区域和第一连接走线107的交叠电容一致，保证显示面板10的显示效果。
综上所述，本申请实施例提供了一种显示面板，该显示面板中的第一显示区设置有虚设电极图案，该虚设电极图案与第一连接走线位于不同层。由此可以便于使得第一显示区的各个像素电路组所在区域与第一连接走线之间的交叠电容一致，进而能够保证显示面板的显示效果。
图4是本申请实施例提供的另一种显示面板的局部示意图。参考图4可以看出，该显示面板10还可以包括：多个第二连接走线108。该多个第二连接走 线108中的至少一个第二连接走线108的一端可以与至少一个第二发光单元104电连接，另一端与虚设电极图案106和第二像素电路组105电连接。
其中，该多个第二连接走线108和多个第一连接走线107以及多个虚设电极图案106均位于不同层。也即是，下述结构中任意两个结构位于不同层：多个第一连接走线107，多个第二连接走线108，以及多个虚设电极图案106。该多个第一连接走线107，多个第二连接走线108，以及多个虚设电极图案106需采用三次构图工艺分别制备。
由于显示面板10的空间有限，因此在同层所能够设置的第一连接走线107的数量有限。由此，通过设置位于不同层的多个第一连接走线107和多个第二连接走线108，使得第一显示区101a的部分第二像素电路组105可以通过该第一连接走线107与第二显示区101b的部分第二发光单元104连接，从而驱动位于第二显示区101b的这一部分第二发光单元104发光。并且，第一显示区101a的另一部分第二像素电路组105可以通过该第二连接走线108与第二显示区101b的另一部分第二发光单元104连接，从而驱动位于第二显示区101b的这另一部分第二发光单元104发光。
本申请实施例的方案可以在不增加第一连接走线107的数量的前提下，增加第二显示区101b所能够设置的第二发光单元104的数量，进而保证显示面板10中第二显示区101b的显示效果。并且，由于第二显示区101b所能够设置的第二发光单元104的数量较多，因此该第二显示区101b可以允许设置较大尺寸的摄像头，对显示面板10的制造精度的要求较低。
可选的，该第一连接走线107和第二连接走线108的材料可以为透明材料，以避免该第一连接走线107和第二连接走线108对第二显示区101b的透过率造成影响。示例的，该第一连接走线107和第二连接走线108的材料可以为氧化铟锡(indium tin oxide，ITO)。另外，该多个第一连接走线107和多个第二连接走线108的延伸方向可以均为第二方向Y。该第二方向Y可以为显示面板10的像素行方向。
需要说明的是，本申请实施例中的显示面板10还可以包括多个第三连接走线。并且，下述结构中任意两个结构位于不同层：多个第一连接走线107，多个第二连接走线108，多个第三连接走线以及多个虚设电极图案106。该多个第一连接走线107，多个第二连接走线108，多个第三连接走线以及多个虚设电极图案106需采用四次构图工艺分别制备。也即是，该显示面板10可以包括三层连 接走线，该三层连接走线分别为：多个第一连接走线107，多个第二连接走线108，以及多个第三连接走线。当然，该显示面板10还可以包括更多层的连接走线，本申请实施例对此不做限定。
在本申请实施例中，以显示面板10包括两层连接走线为例进行说明，即以显示面板10包括多个第一连接走线107和多个第二连接走线108为例。该显示面板10包括的多个第一连接走线107和多个第二连接走线108的个数之和，可以与显示面板10包括的虚设电极图案106的个数相同，且一一对应。多个第一连接走线107和多个第二连接走线108中的每个连接走线均可以与对应的一个虚设电极图案106电连接。
在本申请实施例中，参考图1，每个虚设电极图案106在衬底基板101上的正投影，可以与至少一个第二像素电路组105在衬底基板101上的正投影至少部分重叠。其中，图1中采用同一个小方块表示重叠的两个结构。例如采用同一个小方块表示重叠的第一发光单元102和第一像素电路组103，并采用102/103进行标注。又例如采用同一个小方块表示重叠的第二像素电路组105和虚设电极图案106，并采用105/106进行标注。可选的，每个虚设电极图案106在衬底基板101上的正投影，可以与一个第二像素电路组105在衬底基板101上的正投影至少部分重叠。
并且，每个虚设电极图案106在衬底基板101上的正投影与任一第一发光单元102在衬底基板101上的正投影不重叠。该虚设电极图案106与第一发光单元102不重叠，可以避免该虚设电极图案106对第一发光单元102造成影响，保证该第一发光单元102的发光效果。
在本申请实施例中，参考图1和图3，该第二显示区101b可以包括中心区101b1以及围绕该中心区101b1的边缘区101b2。例如，图3示意性的示出第二显示区101b的形状为矩形，第二显示区101b的中心区101b1的形状为圆形，则边缘区101b2为位于矩形中除圆形中心区以外的区域。当然，第二显示区101b的中心区101b1以及边缘区101b2还可以为其他形状，可以根据实际产品需求进行设置，本申请实施例对此不做限定。
可选的，该中心区101b可以作为屏下摄像区，该中心区101b1设置第二发光单元104，驱动该第二发光单元104发光的第二像素电路组105设置在第一显示区101a。由此，可以使得该中心区101b1具有较高的光透过率以实现摄像功能，又可以通过与其他区域(第一显示区101a)的像素电路组连接而实现发光， 不影响屏幕的显示功能。
在本申请实施例中，参考图1，第二显示区101b中的第二发光单元104可以采用左右对半控制的方式，由关于第一方向X延伸的中心线轴对称的两个第一显示区101a中的第二像素电路组105分别进行控制。例如，位于上述中心线左侧的第二发光单元104由位于中心线左侧的第一显示区101a内的第二像素电路组105控制，位于上述中心线右侧的第二发光单元104由位于中心线右侧的第一显示区101a内的第二像素电路组105控制。其中，该第一方向X可以为显示面板10的像素列方向。
参考图4可以看出，该多个第一连接走线107在衬底基板101上的正投影与多个第二连接走线108在衬底基板101上的正投影不重叠。由此，可以减小多个第一连接走线107和多个第二连接走线108之间产生交叠电容的可能性，进而避免信号串扰。
示例的，该多个第一连接走线107在衬底基板101上的正投影与多个第二连接走线108在衬底基板101上的正投影在第一方向X上交错排布。由此，可以使得位于同层的多个第一连接走线107沿第一方向X之间的距离，以及位于同层的多个第二连接走线108沿第一方向X之间的距离较大，从而可以避免位于同层的连接走线互相影响，保证信号传输的可靠性。当然，该多个第一连接走线107在衬底基板101上的正投影与多个第二连接走线108在衬底基板101上的正投影可以以其他方式排布，本申请实施例对此不做限定。
图5是本申请实施例提供的一种虚设电极图案的示意图。参考图5，至少一个虚设电极图案106包括：主体部1061和第一连接部1062，该第一连接部1062可以沿第一方向X延伸。结合图4和图5，由于该第一连接部1062的延伸方向(第一方向X)与连接走线(第一连接走线107以及第二连接走线108)的延伸方向(第二方向Y)相交，因此该第一连接部1062与多个第一连接走线107和多个第二连接走线108中的至少一个连接走线存在相交处。
其中，该第一连接部1062与多个第一连接走线107和多个第二连接走线108中的至少一个连接走线在相交处通过过孔连接。由此即可实现该至少一个连接走线与虚设电极图案106电连接。并且，虚设电极图案106还可以与第二像素电路组105电连接，因此该至少一个连接走线可以通过虚设电极图案106与第二像素电路组105电连接。
图6是本申请实施例提供的又一种显示面板的局部示意图。图7是图6沿 AA方向的截面图。参考图6和图7可以看出，每个第二像素电路组105可以包括：位于衬底基板101上的源漏金属层。该源漏金属层包括间隔设置的源极和漏极(图7中仅示出了第二像素电路组105中一个晶体管的漏极A)。该显示面板10还可以包括：第一绝缘层109，第二绝缘层110以及第三绝缘层111。
可选的，图7中示意的第一连接图案112与多个第一连接走线107位于同层，且图7中示意的第二连接图案113与多个第二连接走线108位于同层。由此，该源漏金属层，第一绝缘层109，多个第一连接走线107，第二绝缘层110，多个第二连接走线108，第三绝缘层111以及虚设电极图案106沿远离衬底基板101的方向依次层叠。也即是，该第一绝缘层109位于源漏金属层远离衬底基板101的一侧，多个第一连接走线107位于第一绝缘层109远离衬底基板101的一侧，第二绝缘层110位于多个第一连接走线107远离衬底基板101的一侧，多个第二连接走线108位于第二绝缘层110远离衬底基板101的一侧，第三绝缘层111位于多个第二连接走线108远离衬底基板101的一侧，虚设电极图案106位于第三绝缘层111远离多个第二连接走线108的一侧。
在本申请实施例中，多个虚设电极图案106至少包括：第一虚设电极图案以及第二虚设电极图案。其中，该第一虚设电极图案和第二虚设电极图案为不同的两个虚设电极图案。
图8是本申请实施例提供的第一连接走线和第二绝缘层的局部示意图。参考图8，该第二绝缘层110可以具有多个第一过孔(图8中示出了一个第一过孔110a)。并且，该第一过孔110a可以用于露出位于该第二绝缘层110靠近衬底基板101的一侧的一个第一连接走线107。图9是本申请实施例提供的一种第三绝缘层的局部示意图。参考图9，该第三绝缘层111可以具有与多个第一过孔110a一一对应的第三过孔111a(图9中示出了一个第三过孔111a)。
其中，每个第一过孔110a在衬底基板101上的正投影，可以与对应的第三过孔111a在衬底基板101上的正投影至少部分重叠。例如结合图8和图9，第三过孔111a在衬底基板101上的正投影位于对应的第一过孔110a在衬底基板101上的正投影内。
图10是本申请实施例提供的一种第一连接走线与虚设电极图案的示意图。结合图8至图9，该多个虚设电极图案106中的第一虚设电极图案的第一连接部1062的至少部分可以位于该第三过孔111a和第一过孔110a内，并通过该第三过孔111a和第一过孔110a与第一连接走线107电连接。
图11是本申请实施例提供的一种第二连接走线和第二绝缘层的示意图。参考图11，该第二绝缘层110可以具有多个第二过孔110b(图11中示出了一个第二过孔110b)。并且，每个第二连接走线108的至少部分可以位于该第二过孔110b内。图12是本申请实施例提供的一种第三绝缘层的局部示意图。参考图12，该第三绝缘层111可以具有与多个第二过孔110b一一对应的第四过孔111b(图12中示出了一个第四过孔111b)。该第四过孔111b用于露出一个第二连接走线108。
图13是本申请实施例提供的一种第二连接走线与虚设电极图案的示意图。结合图11至图13，该多个虚设电极图案106中的第二虚设电极图案的第一连接部1062的至少部分可以位于该第四过孔111b内，并通过该第四过孔111b与第二连接走线108电连接。
在本申请实施例中，由于第二连接走线108位于第二绝缘层110远离衬底基板101的一侧，因此第二绝缘层110中是否设置有第二过孔110b，并不会影响该第二连接走线108与第二虚设电极图案的第一连接部1062的连接。但是为了节省显示面板10的制备成本，可以使得第二绝缘层110和第三绝缘层111采用同一个掩膜板制备。由此，第三绝缘层111中具有第四过孔111b的位置，该第二绝缘层110中对应位置也具有第二过孔110b。
也即是，结合图11至图13，每个第二过孔110b在衬底基板101上的正投影，可以与对应的第四过孔111b在衬底基板101上的正投影至少部分重叠。例如，第四过孔111b在衬底基板101上的正投影位于对应的第二过孔110b在衬底基板101上的正投影内。由此，第二虚设电极图案可以与第二连接走线108中位于第二过孔110b内的部分电连接。
当然，若不考虑制备成本，该第二绝缘层110中可以无需设置多个第二过孔110b，直接在第二绝缘层110远离衬底基板101的一侧形成多个第二连接走线108即可。
根据上述描述可知，多个虚设电极图案106中的部分虚设电极图案(例如第一虚设电极图案)的第一连接部1062可以与第一连接走线107通过过孔电连接，另一部分虚设电极图案(例如第二虚设电极图案)的第一连接部1062可以与第二连接走线108通过过孔电连接。
由于第一虚设电极图案的第一连接部1062与第一连接走线107通过过孔电连接，因此该第一虚设电极图案的第一连接部1062与第一连接走线107存在相 交处，且该相交处在衬底基板上的正投影，可以与该第一虚设电极图案的第一连接部1062在衬底基板上的正投影重叠。并且，由于第二虚设电极图案第一连接部1062与第二连接走线108通过过孔电连接，因此该第二虚设电极图案的第一连接部1062与第二连接走线108存在相交处，且该相交处在衬底基板上的正投影，可以与该第二虚设电极图案的第一连接部1062在衬底基板上的正投影重叠。
也即是，相交处在衬底基板101上的正投影可以与第一连接部1062在衬底基板101上的正投影重叠。
参考图6还可以看出，该显示面板10还可以包括：多个第二连接部114。该第二连接部114沿第一方向X延伸。由于该第二连接部114的延伸方向(第一方向X)与连接走线(第一连接走线107以及第二连接走线108)的延伸方向(第二方向Y)相交，因此该第二连接部114与多个第一连接走线107和多个第二连接走线108中的至少一个连接走线存在相交处。由此，该第二连接部114与多个第一连接走线107和多个第二连接走线108中的至少一个连接走线在相交处通过过孔电连接，即可实现该至少一个连接走线与第二连接部114电连接。
在本申请实施例中，该第二连接部114可以与第二像素电路组105的源漏金属层位于同层。也即是，该第二连接部114与第二像素电路组105的源漏金属层可以基于相同材料并采用同一次构图工艺制备得到。
为了实现第二像素电路组105和多个第一连接走线107以及多个第二连接走线108中的至少一个连接走线的连接，可以在制备该第二连接部114和源漏金属层时，使得该第二连接部114与一个晶体管的漏极为一体结构。由此即可实现至少一个连接走线通过第二连接部114与第二像素电路组105电连接。
在本申请实施例中，该第二连接部114与虚设电极图案106位于不同层。且该第二连接部114可以与一个虚设电极图案106通过过孔电连接。也即是，该一个虚设电极图案106中传输的信号可以与第二连接部114中传输的信号相同。
图14是本申请实施例提供的一种第二连接部和第一绝缘层的示意图。参考图14，该第一绝缘层109可以具有多个第五过孔109a(图14中示出了一个第五过孔109a)。并且，该第五过孔109a可以用于露出位于该第一绝缘层109靠近衬底基板101的一侧的一个第二连接部114。图15是本申请实施例提供的一种第二连接部和第一连接走线的示意图。参考图15，该第一连接走线107的至 少部分可以位于该第五过孔109a内，并通过该第五过孔109a与第二连接部114电连接。
图16是本申请实施例提供的一种第二连接部，第一绝缘层和第二绝缘层的示意图。参考图16，该第一绝缘层109具有多个第六过孔109b，该第二绝缘层110也具有多个第六过孔110c。该第一绝缘层109中的多个第六过孔109b，与第二绝缘层110中的多个第六过孔110c一一对应。并且，第一绝缘层109中的每个第六过孔109b，与第二绝缘层110中的对应的一个第六过孔110c至少部分重叠。
为了便于表述，将第一绝缘层109中的第六过孔109b，与第二绝缘层110中的对应的一个第六过孔110c统称为第六过孔。该第六过孔(109b和110c)用于露出一个第二连接部114。图17是本申请实施例提供的一种第二连接走线与第二连接部的示意图。结合图16和图17，该第二连接部114的至少部分可以位于该第六过孔内，并通过该第六过孔与第二连接走线108电连接。
该第二连接部114与连接走线(第一连接走线107或者第二连接走线108)存在相交处，且该相交处在衬底基板101上的正投影，可以与任一虚设电极图案106在衬底基板101上的正投影不重叠(例如图6中的相交处w1)。或者，该相交处在衬底基板101上的正投影，位于一个虚设电极图案106在衬底基板101上的正投影内(例如图6中的相交处w2)。
图18是本申请实施例提供的第一连接走线和第二绝缘层的局部示意图。参考图18，该第二绝缘层110可以具有多个第七过孔110d(图18中示出了一个第七过孔110d)。并且，该第七过孔110d可以用于露出位于该第二绝缘层110靠近衬底基板101的一侧的一个第一连接走线107。图19是本申请实施例提供的一种第三绝缘层的局部示意图。参考图19，该第三绝缘层111可以具有与多个第七过孔110d一一对应的第九过孔111c(图19中示出了一个第九过孔111c)。
其中，每个第七过孔110d在衬底基板101上的正投影，可以与对应的第九过孔111c在衬底基板101上的正投影至少部分重叠。例如结合图18和图19，第九过孔111c在衬底基板101上的正投影位于对应的第七过孔110d在衬底基板101上的正投影内。
图20是本申请实施例提供的一种第一连接走线与第二发光单元的第一电极的示意图。结合图18至图20，至少一个第二发光单元104的第一电极1041的至少部分可以位于该第七过孔110d和第九过孔111c内，并通过该第七过孔110d 和第九过孔111c与第一连接走线107电连接。
图21是本申请实施例提供的一种第二连接走线和第二绝缘层的示意图。参考图21，该第二绝缘层110可以具有多个第八过孔110e(图21中示出了一个第八过孔110e)。并且，每个第二连接走线108的至少部分可以位于该第八过孔110e内。图22是本申请实施例提供的另一种第三绝缘层的示意图。参考图22，该第三绝缘层111可以具有与多个第八过孔110e一一对应的第十过孔111d(图22中示出了一个第十过孔111d)。该第十过孔111d用于露出一个第二连接走线108。
图23是本申请实施例提供的一种第二连接走线和第二发光单元的第一电极的示意图。结合图21至图23，至少一个第二发光单元104的第一电极1041的至少部分可以位于该第十过孔111d内，并通过该第十过孔111d与第二连接走线108电连接。
在本申请实施例中，由于第二连接走线108位于第二绝缘层110远离衬底基板101的一侧，因此第二绝缘层110中是否设置有第八过孔110e，并不会影响该第二连接走线108与第二发光单元104的第一电极的连接。但是为了节省显示面板10的制备成本，可以使得第二绝缘层110和第三绝缘层111采用同一个掩膜板制备。由此，第三绝缘层111中具有第十过孔111d的位置，该第二绝缘层110中对应位置也具有第八过孔110e。
也即是，结合图21至图23，每个第八过孔110e在衬底基板101上的正投影，可以与对应的第十过孔111d在衬底基板101上的正投影至少部分重叠。例如，第八过孔110e在衬底基板101上的正投影位于对应的第十过孔111d在衬底基板101上的正投影内。由此，第二发光单元104的第一电极1041可以与第二连接走线108中位于第八过孔110e内的部分电连接。
根据上述描述可知，多个第二发光单元104中的部分第二发光单104元的第一电极1041可以与第一连接走线107通过过孔电连接，另一部分第二发光单元104的第一电极1041可以与第二连接走线108通过过孔电连接。
参考图7，该显示面板10还可以包括：多个第一连接图案112以及与多个第一连接图案112一一对应的多个第二连接图案113。图7中示出了一个第一连接图案112和一个第二连接图案113。
图24是本申请实施例提供的一种第一绝缘层和第一连接图案的示意图。图25是本申请实施例提供的一种第二绝缘层和第二连接图案的示意图。图26是本 申请实施例提供的又一种第三绝缘层的示意图。参考图24至图26可以看出，该第一绝缘层109可以具有多个第十一过孔109c，第二绝缘层110可以具有与多个第十一过孔109c一一对应的多个第十二过孔110f，第三绝缘层111具有与多个第十二过孔110f一一对应的多个第十三过孔111e。其中，每个第十一过孔109c在衬底基板101上的正投影，与对应的第十二过孔110f在衬底基板101上的正投影至少部分重叠。每个第十二过孔110f在衬底基板101上的正投影，与对应的第十三过孔111e在衬底基板101上的正投影至少部分重叠。
结合图7，以及图24至图26，每个第十一过孔109c用于露出一个第二像素电路组105中一个晶体管的漏极，一个第一连接图案112的至少部分位于第十一过孔109c内，且通过该第十一过孔109c与漏极A电连接。每个第十二过孔110f用于露出一个第一连接图案112，与该一个第一连接图案112对应的一个第二连接图案113的至少部分可以位于该第十二过孔110f内，并通过该第十二过孔110f与第一连接图案112电连接。每个第十三过孔111e用于露出一个第二连接图案113，一个虚设电极图案106的至少部分位于该第十三过孔111e内，并通过该第十三过孔111e与第二连接图案113连接。也即是，虚设电极图案106可以通过第二连接图案113和第一连接图案112与第二像素电路组105的漏极A连接。
可选的，第十二过孔110f在衬底基板101上的正投影位于第十一过孔109c在衬底基板101上的正投影内，且第十三过孔111e在衬底基板101上的正投影位于第十二过孔110f在衬底基板101上的正投影内。
在本申请实施例中，第一像素电路组103也可以包括：位于衬底基板101上的源漏金属层。该源漏金属层包括间隔设置的源极和漏极。图27是本申请实施例提供的一种第一发光单元的结构示意图。参考图27，第一发光单元102可以包括沿远离衬底基板101的方向依次层叠的第一电极a1，发光层a2以及第二电极a3。其中，该第一电极a1可以为阳极，第二电极a3可以为阴极。第一像素电路组103的漏极可以与第一发光单元102的第一电极a1电连接。
可选的，多个虚设电极图案106可以与该第一发光单元102中的第一电极a1位于同层。也即是，该虚设电极图案106可以为虚设阳极图案。此种情况下，第一像素电路组103中一个晶体管的漏极与第一发光单元102的第一电极a1的连接示意可以参考上述图7。例如，将图7中的第二像素电路组105替换为第一像素电路组103，并将图7中虚设电极图案106替换为第一发光单元102的第一 电极a1之后，图7即可用于表示第一像素电路组103中一个晶体管的漏极与第一发光单元102的第一电极a1的连接关系。
参考图27可以看出，第一发光单元102还可以包括：位于第一电极a1和发光层a2之间的像素界定层a4。参考图2，图4和图6，该像素界定层a4可以具有多个开口a41，每个开口a41可以用于露出一个第一发光单元102的第一电极a1。并且，多个开口a41在衬底基板101上的正投影与任一虚设电极图案106在衬底基板101上的正投影不重叠。
通过使得像素界定层a4的开口a41露出第一发光单元102的第一电极a1，能够使得第一发光单元102的第一电极a1与发光层a2接触而实现发光。由于多个开口a41在衬底基板101上的正投影与任一虚设电极图案106在衬底基板101上的正投影不重叠，因此该虚设电极图案106处不发光。
需要说明的是，为了便于示意，本申请实施例提供的俯视图中均未示出发光层和阴极层，仅采用像素界定层a4的开口a41区分第一发光单元102的第一电极a1和虚设电极图案106。例如图2中，具有像素界定层a4的开口a41的图案为第一电极a1，不具有像素界定层a4的开口a41的图案为虚设电极图案106。
在本申请实施例中，多个第一发光单元102包括：多个第一颜色的第一发光单元，多个第二颜色的第一发光单元，以及多个第三颜色的第一发光单元。其中，多个第一发光单元102中的至少一个第一颜色的第一发光单元，至少一个第二颜色的第一发光单元以及至少一个第三颜色的第一发光单元构成一个发光单元组b。其中，该第一颜色，第二颜色和第三颜色可以为三基色。例如第一颜色为红色(red，R)，第二颜色为绿色(green，G)，第三颜色为蓝色(blue，B)。
并且，多个虚设电极图案106构成至少一个虚设电极图案组c。每个虚设电极图案组c包括的虚设电极图案106的个数，与一个发光单元组b包括的第一发光单元102的个数相等。
示例的，参考图28，每个发光单元组b包括：一个第一颜色的第一发光单元b1，两个第二颜色的第一发光单元(b21和b22)，以及一个第三颜色的第一发光单元b3。其中，两个第二颜色的第一发光单元(b21和b22)可以统称为第二颜色的第一发光单元对b2。也即是，每个发光单元组b包括四个第一发光单元102，则每个虚设电极图案组c也可以包括四个虚设电极图案106。
在本申请实施例中，每个虚设电极图案组c包括的多个虚设电极图案106 可以与一个发光单元组b中的多个第一发光单元102一一对应，且每个虚设电极图案106与对应的第一发光单元102中的第一电极a1的形状和面积相同。
由于虚设电极图案106与对应的第一发光单元102中第一电极a1的形状和面积均相同，因此可以使得第一显示区101a的第一电极a1和连接走线的重叠面积，与虚设电极图案106和连接走线的重叠面积相同，进而使得第一显示区101a的第一电极a1以及虚设电极图案106与连接走线的交叠电容一致，保证显示面板10的显示效果。其中，第一连接走线107和第二连接走线108统称为连接走线。
在本申请实施例中，参考图29，多个第二发光单元104也可以包括：多个第一颜色的第二发光单元，多个第二颜色的第二发光单元，以及多个第三颜色的第二发光单元。其中，多个第二发光单元104中的至少一个第一颜色的第二发光单元，至少一个第二颜色的第二发光单元以及至少一个第三颜色的第二发光单元也可以构成一个发光单元组b。
其中，每个虚设电极图案组c包括的虚设电极图案106的个数，还可以与一个发光单元组b包括的第二发光单元104的个数相等。示例的，每个发光单元组b包括：一个第一颜色的第二发光单元b1，两个第二颜色的第二发光单元(b21和b22)，以及一个第三颜色的第二发光单元b3。其中，两个第二颜色的第二发光单元(b21和b22)可以统称为第二颜色的第二发光单元对b2。
在本申请实施例中，参考图3，衬底基板101包括两个第一显示区101a。两个第一显示区101a分别位于第二显示区101b的两侧。该衬底基板101还包括：第一周边区101d和第二周边区101e。该第一周边区101d和第二周边区101e分别位于两个第一显示区101a的两侧。也即是，第一周边区101d，一个第一显示区101a，第二显示区101b，另一个第一显示区101a，以及第二周边区101e沿第二方向Y排布。例如，该第一周边区101d位于衬底基板101沿第一方向X的轴线的左侧，第二周边区101e位于衬底基板101沿第一方向X的轴线的右侧。
图30是本申请实施例提供的另一种显示面板的结构示意图。参考图30可以看出，该显示面板10还可以包括：位于第一周边区101d的第一行驱动电路115和位于第二周边区101e的第二行驱动电路116。该第一行驱动电路115与一个第一显示区101a中的第一像素电路组103和第二像素电路组105电连接。该第二行驱动电路116与另一个第一显示区101a中的第一像素电路组103和第二像素电路组105电连接。其中，第一行驱动电路115电连接的第一像素电路组 103和第二像素电路组105所在的一个第一显示区101a位于衬底基板101沿第一方向X的轴线的左侧。第二行驱动电路116电连接的第一像素电路组103和第二像素电路组105所在的另一个第一显示区101a位于衬底基板101沿第一方向X的轴线的右侧。
为了便于理解，可以将位于衬底基板101沿第一方向X的轴线的左侧的一个第一显示区101a称为左侧第一显示区101a，将位于衬底基板101沿第一方向X的轴线的右侧的另一个第一显示区101a称为右侧第一显示区101a。参考图30，该第一行驱动电路115可以与左侧第一显示区101a中的每个像素电路组电连接，从而为该左侧第一显示区101a中的每个像素电路组提供行驱动信号。并且，第一行驱动电路115不与右侧第一显示区101a中的任一像素电路组电连接。该第二行驱动电路116可以与右侧第一显示区101a中的每个像素电路组电连接，从而为该右侧第一显示区101a中的每个像素电路组提供行驱动信号。并且，第二行驱动电路116不与左侧第一显示区101a中的任一像素电路组电连接。
也即是，在本申请实施例中，左侧第一显示区101a中的像素电路组和右侧第一显示区101a中的像素电路组通过不同的行驱动电路进行驱动，且提供给两个第一显示区101a中的像素电路组的行驱动信号互不影响。
参考图30还可以看出，该显示面板10还可以包括：位于一个第一显示区101a的多个第一扫描信号线117，以及位于另一个第一显示区101a的多个第二扫描信号线118。其中，该多个第一扫描信号线117以及多个第二扫描信号线118均可以沿第二方向Y延伸。
该第一行驱动电路115可以与多个第一扫描信号线117电连接，并通过多个第一扫描信号线117与一个第一显示区101a的第一像素电路组103和第二像素电路组105电连接。该第二行驱动电路116可以与多个第二扫描信号线118电连接，并通过多个第二扫描信号线118与另一个第一显示区101a的第一像素电路组103和第二像素电路组105电连接。
其中，多个第一扫描信号线117可以与多个第二扫描信号线118位于同层，且多个第一扫描信号线117在衬底基板101上的正投影以及多个第二扫描信号线118在衬底基板101上的正投影均位于第二显示区101b之外。也即是，多个第一扫描信号线117和多个第二扫描信号线118均不位于第二显示区101b，由此可以保证该第二显示区101b的透过率。
在本申请实施例中，显示面板10包括的第一扫描信号线117的数量可以与 一个第一显示区101a(左侧第一显示区101a)中第一像素电路组103和第二像素电路组105包括的像素电路的行数相同。显示面板10包括的第二扫描信号线118的数量可以与另一个第一显示区101a(右侧第一显示区101a)中第一像素电路组103和第二像素电路组105包括的像素电路的行数相同。
参考图3还可以看出，该衬底基板101还可以包括：第三显示区101c以及第三周边区101f。该第三显示区101c位于第一显示区101a和第二显示区101b的同一侧，且第三周边区101f位于第一显示区101a和第二显示区101b的同一侧。并且，第一周边区101d和第二周边区101e位于第三显示区101c沿第二方向Y的两侧。
参考图3，衬底基板101包括两个第一显示区101a。第一显示区101a和第二显示区101b的形状均为矩形。其中，第一显示区101a和第二显示区101b均位于显示区的边缘。第一显示区101a，第二显示区101b以及第三显示区101c统称为显示区。第一显示区101a和第二显示区101b远离第三显示区101c的边缘与第三周边区101f相接。第二显示区101b沿第二方向Y延伸的一个边缘与第三显示区101c相接，另一个边缘与第三周边区101f相接。第二显示区101b沿第一方向X延伸的两个边缘分别与两个第一显示区101a相接。
参考图1，该显示面板10还可以包括：位于第三显示区101c的多个第三发光单元119，以及与多个第三发光单元119一一对应连接的多个第三像素电路组120。位于第一周边区101d的第一行驱动电路115和位于第二周边区101e的第二行驱动电路116均与该第三显示区101c的第三像素电路组120连接。也即是，第一行驱动电路115和第二行驱动电路116均可以为第三像素电路组120提供行驱动信号，该第三显示区101c的第三像素电路组120可以通过两个行驱动电路进行驱动。
示例的，该显示面板10可以包括多个第三扫描信号线121。每个第三扫描信号线121的一端与第一行驱动电路115连接，另一端与第二行驱动电路116连接，且第三扫描信号还与第三像素电路组120连接。
可选的，多个第三发光单元119的密度大于多个第一发光单元102的密度，且大于多个第二发光单元104的密度。屏下摄像区(第二显示区101b的中心区101b1)的第二发光单元104的密度(即像素密度)低于正常显示区(第三显示区101c)的第三发光单元119的密度，则摄像头可以设置在能够允许更多光透过的低像素密度区域的下方。上述“多个第三发光单元119的密度大于多个第 一发光单元102的密度，且大于多个第二发光单元104的密度”指相同面积下第三发光单元119的数量大于第二发光单元104的数量，且大于第一发光单元102的数量。
在本申请实施例中，第三显示区101c为主要的显示区域，具有较高的分辨率(pixel per inch，PPI)，即第三显示区101c内排布有密度较高的用于显示的第三发光单元119。每个第三发光单元119对应一个第三像素电路组120，且每个第三发光单元119通过对应的一个第三像素电路组120驱动发光。第二显示区101b可以允许从显示面板10显示侧射入的光透过显示面板10而到达显示面板10的背侧，从而使位于显示面板10背侧的传感器等部件的正常工作，本申请实施例不限于此。例如，第二显示区101b也可以允许从显示面板10的背侧发出的光通过显示面板10而到达显示面板10的显示侧。第一显示区101a和第二显示区101b也包括多个发光单元，以用于显示。但是，由于驱动发光单元发光的像素电路组通常不透光，因此为了提高第二显示区101b的中心区101b1的透过率，可以将第二显示区101b的发光单元与驱动该发光单元的像素电路组从物理位置上分离。例如，与第二显示区101b中的发光单元(例如图1中第二显示区101b内的第二发光单元104)连接的第二像素电路组105可以设置在第一显示区101a。也即是，第二像素电路组105会占据第一显示区101a的部分空间。并且，第一显示区101a的剩余空间用于设置第一显示区101a的第一发光单元102和第一像素电路组103。例如图1中第一显示区101a中的每一个点填充方框代表一个像素电路组。若某个填充方框表示的像素电路组为第一像素电路组103，则该填充方框还可以表示第一发光单元102。此种情况下，第一显示区101a中的第一像素电路组103(或者第一发光单元102)以及与第二显示区101b中的第二发光单元104连接的第二像素电路组105在第一显示区101a中阵列排布。由此，第一显示区101a和第二显示区101b的分辨率低于第三显示区101c的分辨率，即第三显示区101c的像素密度大于第一显示区101a的像素密度，且大于第二显示区101b的像素密度。
在本申请实施例中，参考图1和图30，显示面板10还可以包括：多个数据线122。在第二显示区101b的形状为矩形的情况下，每个数据线122位于第二显示区101b的部分在衬底基板101上的正投影可以呈直线或折线，且位于第二显示区101b靠近第一显示区101a的区域。也即是，每个数据线122位于第二显示区101b的部分可以沿第二显示区101b贴边设计。
可选的，结合图31和图32，每个数据线122位于第二显示区101b的部分在衬底基板101上的正投影可以包括依次相接的第一线段1221，第二线段1222以及第三线段1223。其中，第一线段1221的延伸方向和第三线段1223的延伸方向均为第二方向Y，第二线段1222的延伸方向为第一方向X。并且，该第一线段1221位于第二显示区101b靠近第三显示区101c的一侧，第二线段1222位于第二显示区101b靠近第一显示区101a的一侧，第三线段1223位于第二显示区101b靠近第三周边区101f的一侧。
参考图32，每个数据线122还可以位于第三周边区101f，且每个数据线122位于第三周边区101f的部分可以与该数据线122的第三线段1223相接。
图33是本申请实施例提供的一种第一连接走线和第二连接走线的局部示意图。参考图33可以看出，多个第一连接走线107的另一端的连线，以及多个第二连接走线108的另一端的连线均与第一显示区101a远离第二显示区101b的边缘平行，且多个第一连接走线107的另一端的连线，以及多个第二连接走线108的另一端的连线与第一显示区101a远离第二显示区101b的边缘之间的距离均小于距离阈值。
该第一连接走线107的另一端可以是该第一连接走线107的两端中远离第二显示区101b的一端。该第二连接走线108的另一端可以是该第二连接走线108的两端中远离第二显示区101b的一端。通过使得多个第一连接走线107的另一端的连线与第一显示区101a远离第二显示区101b的边缘的距离设计的较小，并使得多个第二连接走线108的另一端的连线与第一显示区101a远离第二显示区101b的边缘的距离设计的较小，可以使得第一显示区101a中各处均存在连接走线。由此可以使得第一显示区101a中各处的交叠电容一致，保证该第一显示区101a的显示效果的均一性。其中，图33中所示的多个第一连接走线107的另一端的连线以及多个第二连接走线108的另一端的连线共线，采用同一个标号e表示。
可选的，多个第一连接走线107的另一端的连线，多个第二连接走线108的另一端的连线与第一显示区101a远离第二显示区101b的边缘均可以大致平行于第一方向X。多个第一连接走线107的另一端的连线，多个第二连接走线108的另一端的连线以及第一显示区101a远离第二显示区101b的边缘共线。也即是，多个第一连接走线107的另一端，多个第二连接走线108的另一端均可以延伸至第一显示区101a远离第二显示区101b的边缘。
在本申请实施例中，“大致”指的是可以允许有15％以内的误差范围。例如，“大致平行”可以是指两者的夹角在0度至30度之间，如可以为0度至10度，0度至15度等。
在本申请实施例中，由于第一显示区101a中能够发光的第一发光单元102的数量较少，而第三显示区101c中能够发光的第三发光单元119的数量较多，因此可能会导致该第一显示区101a的显示亮度比第三显示区101c的显示亮度低。由此，为了提高该第一显示区101a的显示亮度，可以使得每个第一发光单元102通过至少两个像素电路进行驱动，进而提高该第一发光单元102的亮度，保证第一显示区101a的显示效果和第三显示区101c的显示效果的一致性。
可选的，参考图30，第一像素电路组103可以包括：第一像素电路1031。每个第一像素电路组103中的第一像素电路1031被配置为与至少一个第一发光单元102电连接。第二像素电路组105可以包括：第二像素电路1051。每个第二像素电路组105包括的第二像素电路1052被配置为与至少一个第二发光单元104电连接。
若该第一像素电路组103仅包括第一像素电路1031，不包括其他像素电路，且该第一像素电路被配置为与一个第一发光单元102电连接，则该第一发光单元102可以被一个像素电路驱动。相应的，若该第二像素电路组105仅包括第二像素电路1051，不包括其他像素电路，且该第二像素电路被配置为与一个第二发光单元104电连接，则该第二发光单元104可以被一个像素电路驱动。
若该第一像素电路组103仅包括第一像素电路1031，不包括其他像素电路，且该第一像素电路被配置为与多个第一发光单元102(例如两个第一发光单元102)电连接，则该多个第一发光单元102可以被同一个像素电路驱动。相应的，若该第二像素电路组105仅包括第二像素电路1051，不包括其他像素电路，且该第二像素电路被配置为与多个第二发光单元104(例如两个第二发光单元104)电连接，则该多个第二发光单元104可以被同一个像素电路驱动。
可选的，参考图34，每个第一像素电路组103还可以包括：至少一个第三像素电路1032。每个第一像素电路组103中的至少两个像素电路被配置为与同一个第一发光单元103电连接。每个第二像素电路组105还可以包括：至少一个第四像素电路1052。每个第二像素电路组105中的至少两个像素电路被配置为与同一个第二发光单元104电连接。
若该第一像素电路组103包括一个第一像素电路1031和一个第三像素电路 1032，且该第一像素电路1031和第三像素电路1032被配置为与同一个第一发光单元102电连接，则该第一发光单元102可以被两个像素电路驱动。相应的，若该第且该第二像素电路1051和第四像素电路1052被配置为与一个第二发光单元104电连接，则该第二发光单元104可以被两个像素电路驱动。
若该第一像素电路组103包括一个第一像素电路1031和多个第三像素电路1032，且该一个第一像素电路1031和多个第三像素电路1032被配置为与同一个第一发光单元102电连接，则该第一发光单元102可以被多个像素电路驱动。相应的，若该第二像素电路组105包括一个第二像素电路1051和多个第四像素电路1052，且该第二像素电路1051和第四像素电路1052被配置为与同一个第二发光单元104电连接，则该第二发光单元104可以被多个像素电路驱动。
在本申请实施例中，像素电路与发光单元电连接可以是指：像素电路与发光单元的第一电极电连接。例如，该第一像素电路组103中的至少两个像素电路被配置为与同一个第一发光单元102电连接可以是指：该第一像素电路组103中的至少两个像素电路被配置为与同一个第一发光单元102的第一电极a1电连接。
可选的，以第一像素电路组103包括一个第一像素电路1031和一个第三像素电路1032，第二像素电路组105包括一个第二像素电路1051和一个第四像素电路1052为例进行说明。
参考图35，该第一发光单元102的第一电极a1包括第一图案102-1和第二图案102-2。该第二图案102-2可以用于与第一像素电路组103中的至少两个像素电路电连接。其中，该第二图案102-2即为第一发光单元102的第一电极a1与第一像素电路组103的连接处。
该第一发光单元102的第一电极a1与第一像素电路组103的连接处(第二图案102-2)在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影不重叠，且与多个第二连接走线108在衬底基板101上的正投影不重叠。由此，可以使得第一电极a1与第一像素电路组103的连接处，不会受到第一连接走线107和第二连接走线108的影响，可以确保与该第一像素电路组103连接的第一发光单元102正常发光。
在本申请实施例中，为了保证第二显示区101b的透过率，通常该第二显示区101b设置的第二发光单元104的数量较少，因此可能会导致该第二显示区101b的显示亮度比第三显示区101c的显示亮度低。由此，为了提高该第二显示 区101b的显示亮度，可以使得每个第二发光单元104通过至少两个像素电路进行驱动，进而提高该第二发光单元104的亮度，保证第二显示区101b的显示效果和第三显示区101c的显示效果的一致性。
参考图35，该虚设电极图案106包括第三图案106-1和第四图案106-2。该第四图案106-2可以用于与第二像素电路组105中的至少两个像素电路电连接。其中，该第四图案106-2即为虚设电极图案106与第一像素电路组103的连接处。
该虚设电极图案106与第二像素电路组105的连接处(第四图案106-2)在衬底基板101上的正投影，与多个第一连接走线107在衬底基板101上的正投影不重叠，且与多个第二连接走线108在衬底基板101上的正投影不重叠。由此，可以使得虚设电极图案106与第一像素电路组103的连接处，不会受到第一连接走线107和第二连接走线108的影响，可以确保该第二像素电路组105通过该虚设电极图案106驱动第二发光单元104正常发光。
在本申请实施例中，第一像素电路组103和第二像素电路组105的结构可以相同，例如均包括两个像素电路，第一像素电路组103和第二像素电路组105均可以称为像素电路对f。为了后续方便描述，可以将第一像素电路组103和第二像素电路组105中的每个像素电路组包括的两个像素电路均称为第一像素电路和第二像素电路。也即是，为了方便描述，第一像素电路组103包括的第三像素电路1032可以称为第二像素电路，第二像素电路组105包括的第二像素电路1051可以称为第一像素电路，第二像素电路组105包括的第四像素电路1052可以称为第二像素电路。
图36是本申请实施例提供的一种第一像素电路组或第二像素电路组的等效电路图。参考图36，该第一像素电路组103中的至少两个像素电路被配置为与同一个第一发光单元102电连接。第二像素电路组105中的至少两个像素电路被配置为与同一个第二发光单元104电连接。
可选的，显示面板10还包括位于衬底基板101上的复位电源信号线，数据线，扫描信号线，电源信号线，复位控制信号线以及发光控制信号线。如图36所示，各像素电路(第一像素电路f1和第二像素电路f2)包括数据写入晶体管T4，驱动晶体管T3，阈值补偿晶体管T2以及第一复位控制晶体管T7，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极连接，第一复位控制晶体管T7的第一极与复位电源信号线连接以接收复位信号Vinit，第一复位控制晶体管T7的第二极与发光单 元连接，数据写入晶体管T4的第一极与驱动晶体管T3的第二极连接。例如，如图36所示，各像素单元的像素电路还包括存储电容C，第一发光控制晶体管T6，第二发光控制晶体管T5和第二复位晶体管T1。数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的栅极与扫描信号线电连接以接收补偿控制信号；第一复位晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset；第二复位晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset；第一发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM；第二发光控制晶体管T5的第一极与电源信号线电连接，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
可选的，扫描信号和补偿控制信号可以相同，即数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T3的栅极电连接到第一扫描信号线，阈值补偿晶体管T2的栅极电连接到第二扫描信号线，而第一扫描信号线和第二扫描信号线传输的信号可以相同，也可以不同，从而使得数据写入晶体管T3的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。
可选的，第一发光控制晶体管T6和第二发光控制晶体管T5被输入的发光控制信号可以相同，即第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的发光控制信号线，而不同的发光控制信号线传输的信号可以相同，也可以不同。
可选的，第一复位晶体管T7和第二复位晶体管T1被输入的复位控制信号可以相同，即第一复位晶体管T7的栅极和第二复位晶体管T1的栅极可以电连 接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极也可以分别电连接至不同的复位控制信号线，此时，不同复位控制信号线上的信号可以相同也可以不相同。
如图36所示，显示面板10工作时，画面显示的第一阶段，第二复位晶体管T1打开，使N1节点的电压初始化；第二阶段，同一个数据信号Data通过两个相连的数据写入晶体管T4，以及与两个相连的数据写入晶体管T4分别连接的两个驱动晶体管T3以及两个阈值补偿晶体管T2存储在两个像素电路的两个N1节点；在第三发光阶段，两个像素电路(即第一像素电路f1和或第二像素电路f2组成的像素电路对f)中的第二发光控制晶体管T5，驱动晶体管T3以及第一发光控制晶体管T6均打开，以将同样的数据信号传输到两个N4节点，此时，两个像素电路的N4节点相连，共同驱动同一个发光单元B发光，可以达到增加电流和亮度的目的。其中，该发光单元B可以为第一显示区101a中的第一发光单元102，也可以为第二显示区101b中的第二发光单元104。
需要说明的是，在本申请实施例中，像素电路组中包括的像素电路除了可以为图36所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构，6T1C结构，6T2C结构或者9T2C结构，本申请实施例对此不作限定。只要将两个像素电路的数据写入晶体管T4相连，并将两个像素电路的N4节点相连以实现共同驱动同一个发光单元发光即可。
图37是本申请实施例提供的第一显示区内的像素电路的有源半导体层的局示意图。如图37所示，有源半导体层123可采用半导体材料图案化形成。有源半导体层123可用于制作上述的第二复位晶体管T1，阈值补偿晶体管T2，驱动晶体管T3，数据写入晶体管T4，第二发光控制晶体管T5，第一发光控制晶体管T6和第一复位控制晶体管T7的有源层。有源半导体层123包括各像素单元的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层123为由p硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层123可采用非晶硅，多晶硅，氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
图38是本申请实施例提供的第一显示区内的第一导电层的局部示意图。显示面板包括位于有源半导体层123远离衬底基板一侧的栅极绝缘层，用于将上述的有源半导体层123与后续形成的第一导电层124(即栅极金属层)绝缘。图38示出了该显示面板包括的第一导电层124，第一导电层124设置在栅极绝缘层上，从而与有源半导体层123绝缘。第一导电层124可以包括电容C的第二极CC2，沿第二方向Y延伸的多条扫描信号线g1，多条复位控制信号线g2，多条发光控制信号线g3。当然，该第一导电层124还可以包括第二复位晶体管T1，阈值补偿晶体管T2，驱动晶体管T3，数据写入晶体管T4，第二发光控制晶体管T5，第一发光控制晶体管T6和第一复位控制晶体管T7的栅极。
其中，数据写入晶体管T3的栅极可以为扫描信号线g1与有源半导体层123交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线g3与有源半导体层123交叠的一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线g3与有源半导体层123交叠的另一部分。第二复位晶体管T1的栅极为复位控制信号线g2与有源半导体层123交叠的一部分，第一复位控制晶体管T7的栅极为复位控制信号线g2与有源半导体层123交叠的另一部分。阈值补偿晶体管T2可为双栅结构的薄膜晶体管，阈值补偿晶体管T2的第一个栅极可为扫描信号线g1与有源半导体层123交叠的部分，阈值补偿晶体管T2的第二个栅极可为从扫描信号线g1突出的突出结构P与有源半导体层123交叠的部分。驱动晶体管T1的栅极可为电容C的第二极CC2。
需要说明的是，作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层123通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极，漏极在结构上可以是对称的，所以其源极，漏极在物理结构上可以是没有区别的。在本申请实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本申请实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
参考图38，扫描信号线g1，复位控制信号线g2和发光控制信号线g3沿列方向Y排布。扫描信号线g1位于复位控制信号线g2和发光控制信号线g3之间。
在第一方向X上，电容C的第二极CC2(即驱动晶体管T1的栅极)位于 扫描信号线g1和发光控制信号线g3之间。从扫描信号线g1突出的突出结构P位于扫描信号线g1的远离发光控制信号线g3的一侧。
在上述的第一导电层124上形成有第一绝缘层，用于将上述的第一导电层124与后续形成的第二导电层125绝缘。
图39是本申请实施例提供的第一显示区内的第二导电层的局部示意图。参考图39，第二导电层125包括电容C的第一极CC1以及沿第二方向Y延伸的多条复位电源信号线g4。电容C的第一极CC1与电容C的第二极CC2至少部分重叠以形成电容C。
可选的，在上述的第二导电层125上形成有第二绝缘层，用于将上述的第二导电层125与后续形成的源漏金属层126绝缘。
图40是本申请实施例提供的第一显示区的源漏金属层的局部示意图。图28是本申请实施例提供的第一显示区内的有源半导体层，第一导电层，第二导电层以及源漏金属层的层叠示意图。参考图40和图41，源漏金属层126包括沿第一方向X延伸的数据线122以及电源信号线g5。数据线122通过贯穿栅极绝缘层，第一绝缘层和第二绝缘层的过孔与数据写入晶体管T2的第二极电连接。电源信号线g5通过贯穿栅极绝缘层，第一绝缘层和第二绝缘层的过孔与第二发光控制晶体管T5的第一极电连接。电源信号线g5和数据线122沿第二方向Y交替设置。电源信号线g5通过贯穿第二绝缘层的过孔与电容C的第一极CC1电连接。
在本申请实施例中，在上述的源漏金属层126远离衬底基板101的一侧可以设置钝化层以及平坦层用于保护上述的源漏金属层126。
参考图41，第一像素电路组103和第二像素电路组105可以包括沿第二方向Y排列为两个像素电路，即包括一个像素电路对f。而第三像素电路组120不包括上述像素电路对f(未示出)，仅包括一个像素电路。第三像素电路组120中沿第二方向Y排列的相邻的两个像素电路分别驱动一个第三发光单元119发光，且该相邻的两个像素电路中的两个数据写入晶体管彼此独立，且分别连接不同的数据线。
综上所述，本申请实施例提供了一种显示面板，该显示面板中的第一显示区设置有虚设电极图案，该虚设电极图案与第一连接走线位于不同层。由此可以便于使得第一显示区的各个像素电路组所在区域与第一连接走线之间的交叠电容一致，进而能够保证显示面板的显示效果。
图42是本申请实施例提供的一种显示装置的结构示意图。参考图42可以看出，该显示装置可以包括：供电组件20以及上述实施例提供的显示面板10。该供电组件20可以用于为显示面板10供电。其中，该显示装置可以为曲面显示装置。
可选的，该显示装置可以为有机发光二极管(organic light-emitting diode，OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (25)

  1. 一种显示面板，其特征在于，所述显示面板包括：
    衬底基板，所述衬底基板具有相邻的第一显示区和第二显示区；
    多个第一发光单元，所述多个第一发光单元位于所述第一显示区；
    多个第一像素电路组，所述多个第一像素电路组位于所述第一显示区，且每个所述第一像素电路组与至少一个所述第一发光单元电连接；
    多个第二发光单元，所述多个第二发光单元位于所述第二显示区；
    多个第二像素电路组，所述多个第二像素电路组位于所述第一显示区；
    多个虚设电极图案，位于所述第一显示区；
    以及，多个第一连接走线，所述多个第一连接走线中的至少一个所述第一连接走线的一端与至少一个所述第二发光单元电连接，另一端与所述虚设电极图案和所述第二像素电路组电连接；
    其中，所述多个第一连接走线和所述多个虚设电极图案位于不同层。
  2. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括：多个第二连接走线；
    所述多个第二连接走线中的至少一个所述第二连接走线的一端与至少一个所述第二发光单元电连接，另一端与所述虚设电极图案和所述第二像素电路组电连接；
    其中，所述多个第二连接走线和所述多个第一连接走线以及所述多个虚设电极图案均位于不同层。
  3. 根据权利要求2所述的显示面板，其特征在于，所述显示面板包括的多个第一连接走线和多个第二连接走线的个数之和，与所述虚设电极图案的个数相同，且一一对应，所述多个第一连接走线和所述多个第二连接走线中的每个与对应的一个所述虚设电极图案电连接。
  4. 根据权利要求2所述的显示面板，其特征在于，至少一个所述虚设电极图案包括主体部和第一连接部，所述第一连接部沿第一方向延伸，所述第一连接走线和所述第二连接走线均沿第二方向延伸，所述第一方向和所述第二方向相 交；
    所述第一连接部与所述多个第一连接走线和所述多个第二连接走线中的至少一个在相交处通过过孔电连接。
  5. 根据权利要求4所述的显示面板，其特征在于，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述源漏金属层包括间隔设置的源极和漏极；所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；
    所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层，所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠。
  6. 根据权利要求5所述的显示面板，其特征在于，所述多个虚设电极图案至少包括：第一虚设电极图案以及第二虚设电极图案；所述第二绝缘层具有多个第一过孔和多个第二过孔，所述第三绝缘层具有与所述多个第一过孔一一对应的多个第三过孔，以及与所述多个第二过孔一一对应的多个第四过孔；
    每个所述第一过孔在所述衬底基板上的正投影，与对应的所述第三过孔在所述衬底基板上的正投影至少部分重叠，每个所述第一过孔用于露出一个所述第一连接走线，所述第一虚设电极图案中的第一连接部的至少部分通过所述第三过孔和所述第一过孔与所述第一连接走线电连接；
    每个所述第二连接走线的至少部分位于所述第二过孔内，每个所述第四过孔用于露出一个所述第二连接走线，所述第二虚设电极图案中的第一连接部的至少部分通过所述第四过孔与所述第二连接走线电连接。
  7. 根据权利要求4至6任一所述的显示面板，其特征在于，所述相交处在所述衬底基板上的正投影，与所述第一连接部在所述衬底基板上的正投影重叠。
  8. 根据权利要求2所述的显示面板，其特征在于，所述显示面板还包括：多个第二连接部，所述第二连接部沿第一方向延伸，所述第一连接走线和所述第二连接走线均沿第二方向延伸，所述第一方向和所述第二方向相交；
    所述第二连接部与所述虚设电极图案位于不同层，且所述第二连接部与一 个所述虚设电极图案通过过孔电连接，所述第二连接部还和所述多个第一连接走线以及所述多个第二连接走线中的至少一个在相交处通过过孔电连接。
  9. 根据权利要求8所述的显示面板，其特征在于，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述第二连接部与所述源漏金属层位于同层。
  10. 根据权利要求9所述的显示面板，其特征在于，所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；
    所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层，所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠。
  11. 根据权利要求10所述的显示面板，其特征在于，所述第一绝缘层具有多个第五过孔，每个所述第五过孔用于露出一个所述第二连接部，一个所述第一连接走线的至少部分通过一个所述第五过孔与所述第二连接部电连接；
    所述第一绝缘层和所述第二绝缘层具有多个第六过孔，每个所述第六过孔用于露出一个所述第二连接部，一个所述第二连接走线的至少部分通过一个所述第六过孔与所述第二连接部电连接。
  12. 根据权利要求8至11任一所述的显示面板，其特征在于，所述相交处在所述衬底基板上的正投影，与任一所述虚设电极图案在所述衬底基板上的正投影不重叠；
    或者，所述相交处在所述衬底基板上的正投影，位于一个所述虚设电极图案在所述衬底基板上的正投影内。
  13. 根据权利要求2所述的显示面板，其特征在于，每个所述第二像素电路组包括：位于所述衬底基板上的源漏金属层，所述源漏金属层包括间隔设置的源极和漏极；所述显示面板还包括：第一绝缘层，第二绝缘层以及第三绝缘层；所述源漏金属层，所述第一绝缘层，所述多个第一连接走线，所述第二绝缘层， 所述多个第二连接走线，所述第三绝缘层以及所述虚设电极图案沿远离所述衬底基板的方向依次层叠；
    所述第二绝缘层具有多个第七过孔和多个第八过孔，所述第三绝缘层具有与所述多个第七过孔一一对应的多个第九过孔，以及与所述多个第八过孔一一对应的多个第十过孔；
    每个所述第七过孔在所述衬底基板上的正投影，与对应的所述第九过孔在所述衬底基板上的正投影至少部分重叠，每个所述第七过孔用于露出一个所述第一连接走线，至少一个所述第二发光单元的第一电极通过所述第七过孔和所述第九过孔与所述第一连接走线电连接；
    每个所述第二连接走线的至少部分位于所述第八过孔内，每个所述第十过孔用于露出一个所述第二连接走线，至少一个所述第二发光单元的第一电极通过所述第十过孔与所述第二连接走线电连接。
  14. 根据权利要求13所述的显示面板，其特征在于，所述第一绝缘层具有多个第十一过孔，所述第二绝缘层具有与所述多个第十一过孔一一对应的多个第十二过孔，所述第三绝缘层具有与所述多个第十二过孔一一对应的多个第十三过孔；每个所述第十一过孔在所述衬底基板上的正投影，与对应的所述第十二过孔在所述衬底基板上的正投影至少部分重叠，每个所述第十二过孔在所述衬底基板上的正投影，与对应的所述第十三过孔在所述衬底基板上的正投影至少部分重叠；所述显示面板还包括：多个第一连接图案以及与所述多个第一连接图案一一对应的多个第二连接图案；
    每个所述第十一过孔用于露出一个所述第二像素电路组中一个晶体管的漏极，一个所述第一连接图案的至少部分通过所述第十一过孔与所述漏极电连接；每个所述第十二过孔用于露出一个所述第一连接图案，与一个所述第一连接图案对应的一个所述第二连接图案的至少部分通过所述第十二过孔与所述第一连接图案电连接；每个所述第十三过孔用于露出一个所述第二连接图案，一个虚设电极图案的至少部分通过所述第十三过孔与所述第二连接图案连接；
    其中，所述多个第一连接图案与所述多个第一连接走线位于同层，所述多个第二连接图案与所述多个第二连接走线位于同层。
  15. 根据权利要求2至14任一所述的显示面板，其特征在于，所述多个第一连接走线在所述衬底基板上的正投影与所述多个第二连接走线在所述衬底基板上的正投影不重叠。
  16. 根据权利要求15所述的显示面板，其特征在于，所述多个第一连接走线在所述衬底基板上的正投影与所述多个第二连接走线在所述衬底基板上的正投影在所述显示面板的第二方向上交错排布。
  17. 根据权利要求1至16任一所述的显示面板，其特征在于，所述衬底基板包括：两个所述第一显示区，两个所述第一显示区位于所述第二显示区沿第一方向的两侧；所述衬底基板还包括：第一周边区和第二周边区，所述第一周边区和所述第二周边区分别位于两个所述第一显示区的两侧；所述显示面板还包括：位于所述第一周边区的第一行驱动电路和位于所述第二周边区的第二行驱动电路；
    所述第一行驱动电路与一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接，所述第二行驱动电路与另一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接。
  18. 根据权利要求17所述的显示面板，其特征在于，所述显示面板还包括：位于一个所述第一显示区的多个第一扫描信号线，以及位于另一个所述第一显示区的多个第二扫描信号线；
    所述第一行驱动电路通过所述多个第一扫描信号线与一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接，所述第二行驱动电路通过所述多个第二扫描信号线与另一个所述第一显示区中的所述第一像素电路组和所述第二像素电路组电连接；
    其中，所述多个第一扫描信号线与所述多个第二扫描信号线位于同层，且所述多个第一扫描信号线在所述衬底基板上的正投影以及所述多个第二扫描信号线在所述衬底基板上的正投影均位于所述第二显示区之外。
  19. 根据权利要求17或18所述的显示面板，其特征在于，所述衬底基板还 包括：位于所述第一显示区和所述第二显示区同一侧的第三显示区；所述第一周边区和所述第二周边区位于所述第三显示区沿所述第一方向的两侧；所述显示面板还包括：位于所述第三显示区的多个第三发光单元，以及与所述多个第三发光单元一一对应连接的多个第三像素电路组；
    所述第一行驱动电路和所述第二行驱动电路均与所述第三显示区中的所述第三像素电路组连接。
  20. 根据权利要求19所述的显示面板，其特征在于，所述多个第三发光单元的密度大于所述多个第一发光单元的密度，且大于所述多个第二发光单元的密度。
  21. 根据权利要求1至20任一所述的显示面板，其特征在于，所述第二显示区的形状为矩形；所述显示面板还包括：多个数据线；
    每个所述数据线位于所述第二显示区的部分在所述衬底基板上的正投影呈直线或折线，且位于所述第二显示区靠近所述第一显示区的区域。
  22. 根据权利要求1至21任一所述的显示面板，其特征在于，每个所述第二发光单元包括：沿远离所述衬底基板的依次层叠的第一电极，发光层以及第二电极；
    其中，所述多个虚设电极图案与所述第一电极位于同层。
  23. 根据权利要求1至22任一所述的显示面板，其特征在于，每个所述虚设电极图案在所述衬底基板上的正投影，与至少一个所述第二像素电路组在所述衬底基板上的正投影至少部分重叠，且每个所述虚设电极图案在所述衬底基板上的正投影与任一所述第一发光单元在所述衬底基板上的正投影不重叠。
  24. 根据权利要求1至23任一所述的显示面板，其特征在于，每个所述虚设电极图案与所述第二像素电路组的连接处在所述衬底基板上的正投影，与所述多个第一连接走线在所述衬底基板上的正投影不重叠，且与所述多个第二连接走线在所述衬底基板上的正投影不重叠。
  25. 一种显示装置，其特征在于，所述显示装置包括：供电组件以及如权利要求1至24任一所述的显示面板；
    所述供电组件用于为所述显示面板供电。
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CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
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