WO2023150902A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2023150902A1
WO2023150902A1 PCT/CN2022/075443 CN2022075443W WO2023150902A1 WO 2023150902 A1 WO2023150902 A1 WO 2023150902A1 CN 2022075443 W CN2022075443 W CN 2022075443W WO 2023150902 A1 WO2023150902 A1 WO 2023150902A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel circuit
display area
display panel
pixel
light
Prior art date
Application number
PCT/CN2022/075443
Other languages
English (en)
French (fr)
Inventor
蔡建畅
邓治国
刘彪
尚庭华
陈家兴
龙祎璇
牛佐吉
汪明文
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000134.6A priority Critical patent/CN117158125A/zh
Priority to PCT/CN2022/075443 priority patent/WO2023150902A1/zh
Publication of WO2023150902A1 publication Critical patent/WO2023150902A1/zh

Links

Images

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • OLED display panels have been widely used due to their advantages of self-illumination, low driving voltage, and fast response speed.
  • An OLED display panel generally includes a plurality of pixel units, and each pixel unit includes a light emitting element and a pixel circuit connected to the light emitting element.
  • the present application provides a display panel and a display device, and the technical solution is as follows:
  • a display panel is provided, and the display panel includes:
  • a base substrate having a first display area and a second display area, the second display area at least partially surrounding the first display area;
  • a plurality of first pixel circuit groups are arranged in an array in the second display area, each of the first pixel circuit groups includes one first pixel circuit and at most six second pixels circuits, the first pixel circuits and the at most six second pixel circuits are arranged along the row direction of the display panel;
  • a plurality of first light emitting elements are located in the first display area;
  • a plurality of second light-emitting elements are located in the second display area, and the plurality of second light-emitting elements correspond to the second pixel circuits in the plurality of first pixel circuit groups one-to-one , each of the second light-emitting elements is connected to a corresponding one of the second pixel circuits;
  • a plurality of connecting wires extend along the row direction, one end of each of the connecting wires is located in the first display area, and is connected to one of the first light emitting elements, The other end of each connecting wire is located in the second display area and is connected to a first pixel circuit in one of the first pixel circuit groups.
  • the number of the second pixel circuits included in each of the first pixel circuit groups is an even number.
  • the second pixel circuits in each of the first pixel circuit groups include: a plurality of second pixel circuits of the first type and a plurality of second pixel circuits of the second type;
  • the number of the second pixel circuits of the first type is the same as the number of the second pixel circuits of the second type, and for each of the first pixel circuit groups, the first pixel in the first pixel circuit group A circuit is located between the plurality of second pixel circuits of the first type and the plurality of second pixel circuits of the second type.
  • the base substrate further has a third display area, and the third display area is located on a side of the second display area away from the first display area;
  • the display panel further includes:
  • a plurality of second pixel circuit groups are located in the third display area, and the second pixel circuit groups include third pixel circuits;
  • a plurality of third light emitting elements are located in the third display area, the plurality of third light emitting elements are the same as the third pixel circuits in the plurality of second pixel circuit groups One-to-one correspondence, each of the third light-emitting elements is connected to a corresponding one of the third pixel circuits;
  • the number of third pixel circuits included in each second pixel circuit group is the same as the number of first-type second pixel circuits included in one first pixel circuit group.
  • the color of light emitted by the third light-emitting element connected to the third pixel circuit included in the second pixel circuit group is connected to a second pixel circuit of the first type included in the first pixel circuit group.
  • the colors of the light emitted by the second light-emitting elements are correspondingly the same;
  • the color of the light emitted by the third light-emitting element connected to the third pixel circuit included in the second pixel circuit group, and the color of the light emitted by all the second pixel circuits of the second type connected to a second pixel circuit included in the first pixel circuit group are correspondingly the same.
  • the third display area is strip-shaped, and the third display area extends along a column direction of the display panel.
  • each of the first pixel circuit groups includes four of the second pixel circuits.
  • the first display area is located in the middle of the base substrate along the row direction;
  • the second display area includes a first sub-area and a second sub-area; the first sub-area and the The second sub-regions are respectively located on both sides of the first display area along the row direction;
  • the number of one row of first pixel circuit groups located in the first sub-area is the same as the number of one row of first pixel circuit groups located in the second sub-area.
  • the multiple connecting wires include: multiple first-type connecting wires and multiple second-type connecting wires;
  • One end of each of the first-type connecting wires connected to the first pixel circuit is located in the first sub-region, and one end of each of the second-type connecting wires connected to the first pixel circuit is located in the first sub-region. the second sub-region;
  • the multiple first-type connecting traces correspond to the multiple second-type connecting traces one-to-one, and the length of each of the first-type connecting traces along the row direction is the same as that of the corresponding The lengths of the second type of connecting traces along the row direction are equal.
  • the first pixel circuit of the target first pixel circuit group in the plurality of first pixel circuit groups is used to connect to a power supply terminal, and the power supply terminal is used to provide a fixed voltage power supply for the first pixel circuit Signal;
  • the first pixel circuit of the target first pixel circuit group is not connected to the first light emitting element.
  • the first light-emitting element includes a first electrode, a light-emitting pattern, and a second electrode sequentially stacked along a direction away from the base substrate;
  • each connecting wire located in the first display area is connected to the first electrode in one of the first light-emitting elements.
  • the display panel further includes: a plurality of first connection structures and a plurality of second connection structures, the plurality of first connection structures are located in the first display area, and the plurality of second connection structures are located in the second display area;
  • the plurality of first connection structures and the plurality of second connection structures are located on the same layer as the plurality of connection lines, and each connection line is located at one end of the first display area and one of the The first electrode in the first light-emitting element is connected through one of the first connection structures, and each connection line is located at the other end of the second display area and passes through the first pixel circuit in one of the first pixel circuit groups.
  • One of the second connection structures is connected.
  • connection trace for each of the connection traces, a first connection structure connected by the connection trace, a second connection structure connected by the connection trace, and the connection trace are of an integral structure.
  • the display panel further includes a plurality of third connection structures, the plurality of third connection structures are located in the second display area;
  • the second light-emitting element includes stacked first electrodes, light emitting patterns and second electrodes;
  • the multiple third connection structures are located on the same layer as the multiple connection wires, and the first electrode in each of the second light-emitting elements is connected to one second pixel circuit through one third connection structure. .
  • the material of the connecting wiring is a transparent conductive material.
  • the transparent conductive material is indium tin oxide.
  • the multiple connecting wires include multiple first-layer connecting wires and multiple second-layer connecting wires;
  • the display panel further includes: an insulating layer between the plurality of second layer connection traces;
  • a part of the first light emitting elements is connected to the first layer connecting wires, and another part of the first light emitting elements is connected to the second layer connecting wires.
  • the orthographic projections of the plurality of first-layer connection traces on the substrate are alternately arranged with the orthographic projections of the plurality of second-layer connection traces on the substrate.
  • a display device in another aspect, includes: a photosensitive element, and the display panel as described in the above aspect;
  • the photosensitive element is located in the first display area of the display panel.
  • the photosensitive element is a camera.
  • FIG. 1 is a schematic diagram of the arrangement of pixel circuits in a display panel provided by an embodiment of the present application
  • Fig. 2 is a schematic diagram of the arrangement of light-emitting elements in a display panel provided by an embodiment of the present application;
  • Fig. 3 is a top view of a base substrate provided by an embodiment of the present application.
  • Fig. 4 is a schematic diagram of arrangement of pixel circuits in another display panel provided by an embodiment of the present application.
  • Fig. 5 is a schematic diagram of the arrangement of light-emitting elements in another display panel provided by the embodiment of the present application.
  • Fig. 6 is a partial schematic diagram of a display panel provided by an embodiment of the present application.
  • Fig. 7 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • Fig. 8 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of another display panel provided by an embodiment of the present application.
  • Fig. 10 is a schematic structural diagram of a light-emitting element provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the camera of the display device in order to increase the screen-to-body ratio of the display panel, can be arranged in the display area of the display panel.
  • the pixel circuits of each pixel unit in the area where the camera is located are generally arranged in a non-camera area.
  • the pixel circuit located in the non-camera area is connected to the light-emitting element located in the camera area through connecting wires, so as to provide a driving signal for the light-emitting element located in the camera area.
  • FIG. 1 is a schematic diagram of arrangement of pixel circuits in a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the arrangement of light emitting elements in a display panel provided by an embodiment of the present application. 1 and 2, it can be seen that the display panel 10 may include: a base substrate 101, a plurality of first pixel circuit groups 102, a plurality of first light emitting elements 103, a plurality of second light emitting elements 104 and a plurality of connections Route 105.
  • Fig. 3 is a top view of a base substrate provided by an embodiment of the present application.
  • the base substrate 101 may have a first display area 101 a and a second display area 101 b, and the second display area 101 b may at least partially surround the first display area 101 a.
  • the display panel 10 includes a plurality of first pixel circuit groups 102 arranged in an array in the second display area 101b, and each first pixel circuit group 102 may include one first pixel circuit 1021 and at most six a second pixel circuit 1022. Wherein, the first pixel circuits 1021 and at most six second pixel circuits 1022 are arranged along the row direction X of the display panel 10 .
  • each first pixel circuit group 102 in FIG. 1 includes four second pixel circuits 1022 .
  • the number of second pixel circuits 1022 included in each first pixel circuit group 102 may be related to the arrangement of sub-pixels of different colors in the display panel 10 .
  • the display panel 10 generally includes red (red, R) sub-pixels, green (green, G) sub-pixels and blue (blue, B) sub-pixels.
  • Each sub-pixel is composed of a pixel circuit and a light-emitting element.
  • a plurality of second light emitting elements 104 may be located in the second display area 101b.
  • the plurality of second light-emitting elements 104 may correspond to the second pixel circuits 1022 in the plurality of first pixel circuit groups 102 one-to-one, and each second light-emitting element 104 is connected to a corresponding second pixel circuit 1022 .
  • the second pixel circuit 1022 provides a driving signal for the corresponding second light-emitting element 104 .
  • the number of the second light-emitting elements 104 included in the display panel 10 may be equal to the number of the second pixel circuits 1022 included in the display panel 10 , and there is a one-to-one correspondence.
  • Each sub-pixel located in the second display area 101b may be composed of a second pixel circuit 1022 and a corresponding second light emitting element 104 .
  • the plurality of first light emitting elements 103 in the display panel 10 may be located in the first display area 101a.
  • a plurality of connection wires 105 may extend along the row direction X of the display panel 10 .
  • One end of each connecting wire 105 may be located in the first display area 101a, and be connected to a first light-emitting element 103, and the other end of each connecting wire 105 may be located in the second display area 101b, and be connected to a first pixel circuit.
  • the first pixel circuits 1021 in the group 102 are connected.
  • the first pixel circuit 1021 located in the second display area 101b is connected to the first light-emitting element 103 located in the first display area 101a through the connecting wire 105, so that the first pixel circuit 1021 provides driving for the first light-emitting element 103 Signal.
  • the number of connecting wires 105 included in the display panel 10 may be equal to the number of first light emitting elements 103 included in the display panel 10 . That is, there is a one-to-one correspondence between the plurality of connecting wires 105 and the plurality of first light emitting elements 103 .
  • the number of first pixel circuits 1021 included in the display panel 10 may be greater than the number of first light emitting elements 103 included in the display panel 10 .
  • each first pixel circuit group 102 includes at most six second pixel circuits 1022, every area of at most six second pixel circuits 1022 in the second display area 101b can be compressed into one
  • the first pixel circuit 1021 is used to provide a driving signal for the first light emitting element 103 of the first display area 101a. Therefore, the length of the connection wire 105 connecting the first pixel circuit 1021 and the first light-emitting element 103 can be shortened, the reliability of signal transmission by the connection wire 105 can be improved, and the display effect of the display panel 10 can be ensured.
  • each first pixel circuit group includes at most six second pixel circuits that provide driving signals for the second light-emitting elements in the second display area, Therefore, every area of at most six second pixel circuits in the second display area can compress one first pixel circuit for providing driving signals to the first light-emitting elements in the first display area. Therefore, the length of the connection wire connecting the first pixel circuit and the first light-emitting element can be shortened, the reliability of signal transmission by the connection wire can be improved, and the display effect of the display panel can be ensured.
  • the material of the connecting wire 105 can be a transparent conductive material, which can avoid the influence of the connecting wire 105 on the transmittance of the first display area 101a, and enable the first pixel circuit 1021 to be the first pixel circuit 1021 through the connecting wire 105.
  • a light emitting element 103 provides a driving signal.
  • the transparent conductive material may be indium tin oxide (ITO).
  • the number of the second pixel circuits 1022 included in each first pixel circuit group 102 may be an even number.
  • each first pixel circuit group 102 includes two second pixel circuits 1022 , or includes four second pixel circuits 1022 , or includes six second pixel circuits 1022 .
  • the number of the second pixel circuits 1022 included in each first pixel circuit group 102 may also be an odd number, which is not limited in this embodiment of the present application.
  • the second pixel circuits 1022 in each first pixel circuit group 102 include: a plurality of first-type second pixel circuits 1022a and a plurality of second-type second pixel circuits 1022b.
  • the number of the first-type second pixel circuits 1022a is the same as the number of the second-type second pixel circuits 1022b.
  • the first pixel circuits 1021 in the first pixel circuit group 102 are located between the plurality of first-type second pixel circuits 1022a and the plurality of second-type second pixel circuits 1022b. That is, in each first pixel circuit group 102 , the first pixel circuit 1021 may be arranged in the middle of all the pixel circuits included in the first pixel circuit group 102 .
  • the first pixel circuit 1021 that provides the driving signal for the first light-emitting element 103 is arranged in the middle position, it is convenient to connect the first pixel in the first sub-region 101b1 located on the left side of the first display region 101a in the second display region 101b.
  • the length of the connecting wiring 105 of the circuit 1021 is the same as the length of the connecting wiring 105 of the first pixel circuit 1021 in the second sub-region 101b2 located on the right side of the first display region 101a in the second display region 101b. In this way, the symmetry of the plurality of connecting wires 105 included in the display panel 10 can be improved, and the problem of poor display on the display panel 10 can be avoided.
  • the first pixel circuit group 102 in FIG. 4 includes four second pixel circuits 1022 .
  • the four second pixel circuits 1022 include two first-type second pixel circuits 1022a and two second-type second pixel circuits 1022b.
  • the six second pixel circuits 1022 include three first-type second pixel circuits 1022a and three second-type second pixel circuits 1022b.
  • the two second pixel circuits 1022 include a first-type second pixel circuit 1022a and a second-type second pixel circuit 1022b.
  • the base substrate 101 further has a third display area 101c, and the third display area 101c may be located on a side of the second display area 101b away from the first display area 101a.
  • the display panel 10 may further include: a plurality of second pixel circuit groups 106 and a plurality of third light emitting elements 107 located in the third display area 101c.
  • the second pixel circuit group 106 includes a third pixel circuit 1061 .
  • a plurality of third light-emitting elements 107 correspond to the third pixel circuits 1061 in the plurality of second pixel circuit groups 106, and each third light-emitting element 107 is connected to a corresponding third pixel circuit 1061, so that the third pixel The circuit 1061 provides a driving signal for the corresponding third light emitting element 107 .
  • the number of third pixel circuits 1061 included in each second pixel circuit group 106 may be the same as the number of first-type second pixel circuits 1022a included in one first pixel circuit group 102 .
  • the arrangement of the pixel circuits in each area of the display panel 10 where the pixel circuits are arranged is the same. If the size of the third display area 101c (display area near the border) of the display panel 10 along the row direction X is small, and it is difficult to set the first pixel circuit group 102 as the minimum repeating unit, then the second pixel circuit group can be used 106 is set for the minimum repeating unit.
  • the arrangement of the third pixel circuits 1061 included in the second pixel circuit group 106 may correspond to the arrangement of the first-type second pixel circuits 1022a included in the first pixel circuit group 102, and may also correspond to the arrangement of the second pixel circuits 1022a included in the first pixel circuit group 102.
  • the arrangement of the second type of second pixel circuits 1022b is corresponding. It depends on whether the second pixel circuit group 106 is located in the third display area 101c on the left side of the second display area 101b or in the third display area 101c on the right side.
  • the arrangement of the third pixel circuits 1061 included in the second pixel circuit group 106 can be the same as that of the first pixel circuit group.
  • the arrangement of the second type of second pixel circuits 1022b included in 102 is corresponding.
  • the arrangement of the third pixel circuits 1061 included in the second pixel circuit group 106 can be compared with that of the first pixel circuit group 102.
  • the arrangement of the first-type second pixel circuits 1022a is corresponding.
  • the arrangement of the third pixel circuits 1061 included in the second pixel circuit group 106 corresponds to the arrangement of the second-type second pixel circuits 1022b included in the first pixel circuit group 102, which can be used to represent: the second pixel circuit group
  • the color of the light emitted by the third light emitting element 107 connected to the third pixel circuit 1061 included in 106, the color of the light emitted by the second light emitting element 104 connected to the second type of second pixel circuit 1022b included in the first pixel circuit group 102 The color of the light corresponds to the same.
  • the color of the sub-pixel formed by the third pixel circuit 1061 and the third light-emitting element 107 connected thereto corresponds to the color of the sub-pixel formed by the second-type second pixel circuit 1022b and the second light-emitting element 104 connected thereto. same.
  • the arrangement of the third pixel circuits 1061 included in the second pixel circuit group 106 corresponds to the arrangement of the first-type second pixel circuits 1022a included in the first pixel circuit group 102, which can be used to indicate that: the second pixel circuit group 106 includes The color of the light emitted by the third light-emitting element 107 connected to the third pixel circuit 1061, the color of the light emitted by the second light-emitting element 104 connected with the first-type second pixel circuit 1022a included in the first pixel circuit group 102 The color corresponds to the same.
  • the color of the sub-pixel formed by the third pixel circuit 1061 and the third light-emitting element 107 connected thereto corresponds to the color of the sub-pixel formed by the second pixel circuit 1022a of the first type and the second light-emitting element 104 connected thereto. same.
  • the first pixel circuit group 102 includes two first-type second pixel circuits 1022a and two second-type second pixel circuits 1022b.
  • each minimum repeating unit m includes two second light-emitting elements 104 connected to two first-type second pixel circuits 1022a from left to right, and two second-type second pixel circuits 1022a connected to them, and two second-type second pixel circuits 1022a Two second light-emitting elements 104 connected to the two-pixel circuit 1022b.
  • the four second light emitting elements 104 are blue light emitting element, green light emitting element, red light emitting element and green light emitting element respectively from left to right.
  • the second pixel circuit group 106 includes two third pixel circuits 1061 corresponding to the two second-type second pixel circuits 1022b, and the two third light-emitting elements 107 connected to the two third pixel circuits 1061 are respectively red Light emitting element and green light emitting element.
  • the pixel circuit connected to the blue light-emitting element constitutes a blue sub-pixel
  • the pixel circuit connected to the green light-emitting element constitutes a green sub-pixel
  • the pixel circuit connected to the red light-emitting element constitutes a red sub-pixel.
  • FIG. 6 only shows the anode of each light-emitting element, and does not show the light-emitting pattern and cathode of each light-emitting element.
  • the first pixel circuit 1021 in the first pixel circuit group 102 is arranged in the middle of all the pixel circuits included in the first pixel circuit group 102, if the third display area 101c of the display panel 10 can be placed next to the first pixel circuit If there are third pixel circuits 1061 with the same number of second pixel circuits 1022a of the first type (or second pixel circuits 1022b of the second type) in the group 102, the second pixel circuit group 106 may not include dummy circuits corresponding to the first pixel circuits 1021 pixel circuit.
  • the dummy pixel circuit refers to a pixel circuit not connected to any light emitting element.
  • the size of the third display area 101c of the display panel 10 along the row direction X is relatively small, and only the third pixel circuit 1061 may be reserved (the third pixel circuit 1061 may correspond to the second pixel circuit 1022a of the first type, or Corresponding to the second type of second pixel circuit 1022b), there is no need to keep a dummy pixel circuit (corresponding to the first pixel circuit 1021). In this way, more space can be reserved for the peripheral area of the base substrate 101 , which is convenient for arranging other devices in the peripheral area of the display panel 10 .
  • connection structure corresponding to the dummy pixel circuit is not shown to indicate that the second pixel circuit group 106 does not include a dummy pixel circuit, and the second connection structure 109 corresponding to the first pixel circuit 1061 is used to indicate the first pixel circuit.
  • the circuit group 106 includes a first pixel circuit 1061 .
  • the third display area 101c may be in a strip shape, and the third display area 101c may extend along the column direction Y of the display panel 10 .
  • the third display area 101c may also be arc-shaped.
  • the embodiment of the present application does not limit the shape of the third display area 101c.
  • the first display region 101a may be located in the middle of the base substrate 101 along the row direction X.
  • the second display area 101b includes a first sub-area 101b1 and a second sub-area 101b2, and the first sub-area 101b1 and the second sub-area 101b2 are located on two sides of the first display area 101a along the row direction X respectively.
  • the first sub-area 101b1 of the second display area 101b is located on the left side of the first display area 101a
  • the second sub-area 101b2 of the second display area 101b is located on the right side of the first display area 101a.
  • the number of first pixel circuit groups 102 that can be arranged in the row direction X in the first sub-region 101b1 can be equal to the number of first pixel circuit groups 102 that can be arranged in the row direction X in the second sub-pixel. That is, among the plurality of first pixel circuit groups 102 , the number of one row of first pixel circuit groups 102 located in the first sub-region 101b1 is the same as the number of one row of first pixel circuit groups 102 located in the second sub-region 101b2 .
  • the multiple connecting wires 105 may include: multiple first-type connecting wires 105a and multiple second-type connecting wires 105b.
  • One end of each first-type connecting wire 105a connected to the first pixel circuit 1021 is located in the first sub-region 101b1, and one end of each second-type connecting wire 105b connected to the first pixel circuit 1021 is located in the second sub-region 101b2.
  • the plurality of first-type connection traces 105a correspond to the plurality of second-type connection traces 105b one-to-one
  • the length of each first-type connection trace 105a along the row direction X corresponds to the corresponding second-type connection trace.
  • the lengths of the lines 105b along the row direction X are equal.
  • Fig. 8 is a partial schematic diagram of a first sub-region and a first display area provided by an embodiment of the present application
  • Fig. 9 is a partial schematic diagram of a second sub-region and a first display area provided by an embodiment of the present application
  • the length of the first-type connecting traces 105a along the row direction X is equal to the length of the corresponding second-type connecting traces 105b along the row direction X.
  • each first-type connecting wire 105a along the row direction X is equal to the length of the corresponding second-type connecting wire 105b along the row direction X, the symmetry of the multiple connecting wires 105 included in the display panel 10 can be ensured. performance, to ensure the display effect of the display panel 10.
  • the first pixel circuits 1021 of the target first pixel circuit group in the plurality of first pixel circuit groups 102 are used to connect to the power supply terminal, and the power supply terminal can be used to provide The first pixel circuit 1021 provides a fixed voltage power signal.
  • the first pixel circuit 1021 of the target first pixel circuit group is not connected to the first light emitting element 103 .
  • the power supply end may be a power supply end of a positive power supply signal
  • the power supply terminal may be used to provide a positive power supply signal for the first pixel circuit 1021 in the target first pixel circuit group.
  • the positive power supply signal may also be referred to as a VDD signal.
  • the first pixel circuit 1021 of the target first pixel circuit group is not connected to the first light emitting element 103, and the first pixel circuit 1021 of the target first pixel circuit group may be called a dummy pixel circuit. If the dummy pixel circuit is not provided with a fixed-voltage power supply signal through the power supply terminal, the change of the signal in the dummy pixel circuit may interfere with the normal operation of other pixel circuits. Therefore, in the embodiment of the present application, by making the power supply end provide these dummy pixel circuits with a power signal of a fixed voltage, the signal changes in the dummy pixel circuits can be avoided, the normal operation of other pixel circuits in the display panel 10 can be ensured, and the display panel 10 display effects.
  • the first light emitting element 103 may include a first electrode b1 , a light emitting pattern b2 and a second electrode b3 sequentially stacked along a direction away from the base substrate 101 .
  • One end of each connecting wire 105 located in the first display area 101 a is connected to the first electrode b1 in one first light emitting element 103 .
  • the first light-emitting element 103 may further include a pixel defining layer b4, and the pixel defining layer b4 may have a hollow area, and the hollow area may be used to expose at least part of the first electrode b1, so that the first electrode b1 can emit light together with Pattern b2 contacts.
  • the first electrode b1 may be an anode
  • the second electrode b3 may be a cathode.
  • the display panel 10 may further include: a plurality of first connection structures 108 and a plurality of second connection structures 109 .
  • a plurality of first connection structures 108 are located in the first display area 101a, and a plurality of second connection structures 109 are located in the second display area 101b.
  • the plurality of first connection structures 108 and the plurality of second connection structures 109 are located on the same layer as the plurality of connection traces 105 . That is, the multiple first connection structures 108 , the multiple second connection structures 109 and the multiple connection traces 105 can be prepared using the same material and by the same patterning process.
  • the first pixel circuit 1021 , the plurality of connecting wires 105 and the first light emitting element 103 are stacked along a direction away from the base substrate 101 .
  • the plurality of first connection structures 108 and the plurality of second connection structures 109 are located between the first pixel circuit 1021 and the first light emitting element 103 .
  • multiple connecting wires 105 can also be located on the same layer as the conductive film layer in the first pixel circuit 1021, for example, multiple connecting wires 105 can be located on one side of the source-drain layer close to the base substrate 101.
  • the conductive film layer, or the plurality of connection wires 105 are located at the source and drain layers, or at the gate layer.
  • the material of the source and drain layers may be a transparent conductive material (such as ITO).
  • the material of the gate layer may be a transparent conductive material (such as ITO).
  • Each connecting wire 105 is located at one end of the first display area 101a and is connected to the first electrode b1 in a first light-emitting element 103 through a first connecting structure 108, and each connecting wire 105 is located at the other end of the second display area 101b.
  • One end is connected to a first pixel circuit 1021 in a first pixel circuit group 102 through a second connection structure 109 . That is, one end of each connection wire 105 located in the first display region 101 a is connected to a first connection structure 108 , and the first connection structure 108 may be connected to a first electrode b1 in a first light emitting element 103 .
  • Each connection wire 105 is located at the other end of the second display area 101 b and is connected to a second connection structure 109 , and the second connection structure 109 is connected to a first pixel circuit 1021 in a first pixel circuit group 102 .
  • first insulating layer between the first pixel circuit 1021 and the connecting wire 105
  • second insulating layer between the connecting wire 105 and the first electrode b1 in the first light emitting element 103
  • first via hole there may be a first via hole in the first insulating layer, and the orthographic projection of the first via hole on the base substrate 101 at least partially overlaps with the orthographic projection of the second connection structure 109 on the base substrate 101 . That is, the second connection structure 109 is connected to the first pixel circuit 1021 through the first via hole.
  • the orthographic projection of the second via hole on the base substrate 101 at least partially overlaps with the orthographic projection of the first connection structure 108 on the base substrate 101 . That is, the first connection structure 108 is connected to the first electrode b1 in the first light emitting element 103 through the second via hole.
  • connection line 105 since the plurality of first connection structures 108 and the plurality of second connection structures 109 are located on the same layer as the plurality of connection lines 105, for each connection line 105, a first connection connected by the connection line 105
  • the structure 108 , a second connection structure 109 connected by the connecting wire 105 , and the connecting wire 105 may be an integral structure.
  • the display panel 10 may further include a plurality of third connection structures 110 .
  • the plurality of third connection structures 110 may be located in the second display area 101b.
  • the second light-emitting element 104 has the same structure as the first light-emitting element 103 , and also includes a first electrode b1 , a light-emitting pattern b2 and a second electrode b3 sequentially stacked along a direction away from the base substrate 101 .
  • the plurality of third connection structures 110 are located on the same layer as the plurality of connection traces 105 . That is, multiple third connecting structures 110 and multiple connecting wires 105 can be prepared using the same material and by the same patterning process.
  • the second pixel circuit 1022 , the plurality of third connection structures 110 and the second light emitting element 104 can be stacked along a direction away from the base substrate 101 . That is, the plurality of third connection structures 110 are located between the second pixel circuit 1022 and the second light emitting element 104 .
  • the plurality of third connection structures 110 may also be located on the same layer as the conductive film layer in the second pixel circuit 1022, for example, the plurality of third connection structures 110 may be located on the side of the source-drain layer close to the base substrate 101.
  • a certain conductive film layer, or a plurality of third connection structures 110 are located at the source and drain layers, or at the gate layer.
  • the material of the source and drain layers may be a transparent conductive material (such as ITO).
  • the material of the gate layer may be a transparent conductive material (such as ITO).
  • the first electrode b1 in each second light emitting element 104 is connected to a second pixel circuit 1022 through a third connection structure 110 . That is, the first electrode b1 in each second light emitting element 104 is connected to a third connection structure 110 , and the third connection structure 110 is connected to a second pixel circuit 1022 .
  • the second pixel circuit 1022 and the first pixel circuit 1021 can be prepared together. Therefore, there is also a first insulating layer between the second pixel circuit 1022 and the connecting wire 105 , and there is also a second insulating layer between the connecting wire 105 and the first electrode b1 in the second light emitting element 104 . There may be a third via hole in the first insulating layer, and the orthographic projection of the third via hole on the base substrate 101 at least partially overlaps with the orthographic projection of the third connection structure 110 on the base substrate 101 . That is, the third connection structure 110 is connected to the second pixel circuit 1022 through the third via hole.
  • the orthographic projection of the fourth via hole on the base substrate 101 at least partially overlaps with the orthographic projection of the third connection structure 110 on the base substrate 101 . That is, the third connection structure 110 is connected to the first electrode b1 in the second light emitting element 104 through the fourth via hole.
  • the multiple connecting wires 105 may include multiple first-layer connecting wires and multiple second-layer connecting wires.
  • the display panel 10 further includes an insulating layer (for example, referred to as a third insulating layer) between the plurality of first-layer connecting traces and the plurality of second-layer connecting traces.
  • a third insulating layer between the plurality of first-layer connecting traces and the plurality of second-layer connecting traces.
  • connecting wires 105 In the case of a large number of connecting wires 105, multiple connecting wires 105 can be arranged through two layers of wires, so as to avoid the gap between adjacent connecting wires 105 due to the large number of connecting wires 105. The distance between them is relatively small, which ensures the reliability of signal transmission by the connecting traces 105.
  • the orthographic projections of the plurality of first-layer connection traces on the substrate 101 may be alternately arranged with the orthographic projections of the plurality of second-layer connection traces on the substrate 101 . Since the connecting traces of the first layer and the connecting traces of the second layer are arranged alternately, the distance between two adjacent connecting traces 105 on the same layer can be made large enough to ensure the reliability of signal transmission.
  • the plurality of connecting wires 105 may also include more layers of connecting wires 105, and an insulating layer is provided between two adjacent layers of connecting wires 105.
  • the number is not limited.
  • each first pixel circuit group includes at most six second pixel circuits that provide driving signals for the second light-emitting elements in the second display area, Therefore, every area of at most six second pixel circuits in the second display area can compress one first pixel circuit for providing driving signals to the first light-emitting elements in the first display area. Therefore, the length of the connection wire connecting the first pixel circuit and the first light-emitting element can be shortened, the reliability of signal transmission by the connection wire can be improved, and the display effect of the display panel can be ensured.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: a photosensitive element 20 , and the display panel 10 provided in the above-mentioned embodiments.
  • the photosensitive element 20 may be located in the first display area 101a of the display panel.
  • the first display area 101a may be a rectangle as shown in FIG. 11 , and the area of the orthographic projection of the photosensitive element 20 on the base substrate 00 may be smaller than or equal to the area of the inscribed circle of the first display area 101a. That is, the size of the area where the photosensitive element 20 is located may be smaller than or equal to the size of the inscribed circle of the first display area 101a.
  • the size of the area where the photosensitive element 20 is located is equal to the size of the inscribed circle N of the first display area 101a, that is, the shape of the area where the photosensitive element 20 is located can be a circle.
  • the area where the photosensitive element 20 is located may also be referred to as a light transmission hole.
  • the first display area 101a may also be in other shapes than rectangle, such as circle.
  • the photosensitive element 20 may be a camera.
  • the display device may be an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (PMOLED) ) display device, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) display device, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator, etc. any product or component with display function .
  • AMOLED active-matrix organic light-emitting diode
  • PMOLED passive-matrix organic light-emitting diode
  • QLED quantum dot light emitting diodes
  • Words such as “comprises” or “comprising” and similar terms mean that the elements or items listed before “comprising” or “comprising” include the elements or items listed after “comprising” or “comprising” and their equivalents, and do not exclude other component or object.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right” and so on are only used to indicate relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Landscapes

  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

公开了一种显示面板及显示装置，涉及显示技术领域。显示面板(10)中每个第一像素电路组(102)包括为第二显示区(101b)的第二发光元件(104)提供驱动信号的至多六个第二像素电路(1022)，因此第二显示区(101b)中每至多六个第二像素电路(1022)的区域就可以压缩出一个用于为第一显示区(101a)的第一发光元件(103)提供驱动信号的第一像素电路(1021)。由此可以使得连接第一像素电路(1021)和第一发光元件(103)的连接走线的长度可以较短，能够提高连接走线传输信号的可靠性，确保显示面板(10)的显示效果。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度块等优点而得到了广泛的应用。OLED显示面板一般包括多个像素单元，每个像素单元包括发光元件以及与该发光元件连接的像素电路。
发明内容
本申请提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有第一显示区和第二显示区，所述第二显示区至少部分包围所述第一显示区；
多个第一像素电路组，所述多个第一像素电路组阵列排布于所述第二显示区，每个所述第一像素电路组包括一个第一像素电路和至多六个第二像素电路，所述第一像素电路和所述至多六个第二像素电路沿所述显示面板的行方向排布；
多个第一发光元件，所述多个第一发光元件位于所述第一显示区；
多个第二发光元件，所述多个第二发光元件位于所述第二显示区，所述多个第二发光元件与所述多个第一像素电路组中的第二像素电路一一对应，每个所述第二发光元件与对应的一个所述第二像素电路连接；
以及，多个连接走线，所述多个连接走线沿所述行方向延伸，每个所述连接走线的一端位于所述第一显示区，且与一个所述第一发光元件连接，每个所述连接走线的另一端位于所述第二显示区，且与一个所述第一像素电路组中的第一像素电路连接。
可选的，每个所述第一像素电路组包括的所述第二像素电路的数量为偶数。
可选的，每个所述第一像素电路组中的所述第二像素电路包括：多个第一类第二像素电路和多个第二类第二像素电路；
其中，所述第一类第二像素电路的数量和所述第二类第二像素电路的数量相同，对于每个所述第一像素电路组，所述第一像素电路组中的第一像素电路位于所述多个第一类第二像素电路和所述多个第二类第二像素电路之间。
可选的，所述衬底基板还具有第三显示区，所述第三显示区位于所述第二显示区远离所述第一显示区的一侧；所述显示面板还包括：
多个第二像素电路组，所述多个第二像素电路组位于所述第三显示区，所述第二像素电路组包括第三像素电路；
以及，多个第三发光元件，所述多个第三发光元件位于所述第三显示区，所述多个第三发光元件与所述多个第二像素电路组中的第三像素电路一一对应，每个所述第三发光元件与对应的一个所述第三像素电路连接；
其中，每个所述第二像素电路组包括的第三像素电路的数量与一个所述第一像素电路组包括的第一类第二像素电路的数量相同。
可选的，所述第二像素电路组包括的第三像素电路连接的所述第三发光元件发出的光线的颜色，与一个所述第一像素电路组包括的第一类第二像素电路连接的所述第二发光元件发出的光线的颜色对应相同；
或者，所述第二像素电路组包括的第三像素电路连接的所述第三发光元件发出的光线的颜色，与一个所述第一像素电路组包括的第二类第二像素电路连接的所述第二发光元件发出的光线的颜色对应相同。
可选的，所述第三显示区呈条状，且所述第三显示区沿所述显示面板的列方向延伸。
可选的，每个所述第一像素电路组包括四个所述第二像素电路。
可选的，所述第一显示区位于所述衬底基板沿所述行方向的中部；所述第二显示区包括第一子区域和第二子区域；所述第一子区域和所述第二子区域分别位于所述第一显示区沿所述行方向的两侧；
其中，所述多个第一像素电路组中，位于所述第一子区域的一行第一像素电路组的数量，与位于所述第二子区域的一行第一像素电路组的数量相同。
可选的，所述多个连接走线包括：多个第一类连接走线和多个第二类连接 走线；
每个所述第一类连接走线与所述第一像素电路连接的一端位于所述第一子区域，每个所述第二类连接走线与所述第一像素电路连接的一端位于所述第二子区域；
其中，所述多个第一类连接走线与所述多个第二类连接走线一一对应，且每个所述第一类连接走线沿所述行方向的长度，与对应的所述第二类连接走线沿所述行方向的长度相等。
可选的，所述多个第一像素电路组中目标第一像素电路组的第一像素电路用于与电源端连接，所述电源端用于为所述第一像素电路提供固定电压的电源信号；
其中，所述目标第一像素电路组的第一像素电路不与所述第一发光元件连接。
可选的，所述第一发光元件包括沿远离所述衬底基板的方向依次层叠的第一电极，发光图案以及第二电极；
每个所述连接走线位于所述第一显示区的一端与一个所述第一发光元件中的第一电极连接。
可选的，所述显示面板还包括：多个第一连接结构和多个第二连接结构，所述多个第一连接结构位于所述第一显示区，所述多个第二连接结构位于所述第二显示区；
其中，所述多个第一连接结构和所述多个第二连接结构均与所述多个连接走线位于同层，每个连接走线位于所述第一显示区的一端和一个所述第一发光元件中的第一电极通过一个所述第一连接结构连接，每个连接走线位于所述第二显示区的另一端和一个所述第一像素电路组中的第一像素电路通过一个所述第二连接结构连接。
可选的，对于每个所述连接走线，所述连接走线连接的一个第一连接结构，所述连接走线连接的一个第二连接结构以及所述连接走线为一体结构。
可选的，所述显示面板还包括多个第三连接结构，所述多个第三连接结构位于所述第二显示区；所述第二发光元件包括沿远离所述衬底基板的方向依次层叠的第一电极，发光图案以及第二电极；
所述多个第三连接结构与所述多个连接走线位于同层，每个所述第二发光 元件中的第一电极和一个所述第二像素电路通过一个所述第三连接结构连接。
可选的，所述连接走线的材料为透明导电材料。
可选的，所述透明导电材料为氧化铟锡。
可选的，所述多个连接走线包括多个第一层连接走线和多个第二层连接走线；所述显示面板还包括：位于所述多个第一层连接走线和所述多个第二层连接走线之间的绝缘层；
其中，所述多个第一发光元件中，一部分第一发光元件和所述第一层连接走线连接，另一部分第一发光元件和所述第二层连接走线连接。
可选的，所述多个第一层连接走线在所述衬底基板上的正投影，与所述多个第二层连接走线在所述衬底基板上的正投影交替排布。
另一方面，提供了一种显示装置，所述显示装置包括：感光元件，以及如上述方面所述的显示面板；
其中，所述感光元件位于所述显示面板的第一显示区内。
可选的，所述感光元件为摄像头。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板中像素电路的排布示意图；
图2是本申请实施例提供的一种显示面板中发光元件的排布示意图；
图3是本申请实施例提供的一种衬底基板的俯视图；
图4是本申请实施例提供的另一种显示面板中像素电路的排布示意图；
图5是本申请实施例提供的另一种显示面板中发光元件的排布示意图；
图6是本申请实施例提供的一种显示面板的局部示意图；
图7是本申请实施例提供的另一种显示面板的局部示意图；
图8是本申请实施例提供的又一种显示面板的局部示意图；
图9是本申请实施例提供的再一种显示面板的局部示意图；
图10是本申请实施例提供的一种发光元件的结构示意图；
图11是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
相关技术中，为了提高显示面板的屏占比，可以将显示装置的摄像头设置在显示面板的显示区域。并且，为了增大摄像头所在区域的透过率，通常将该摄像头所在区域中各像素单元的像素电路设置在非摄像头区域。位于非摄像头区域的像素电路通过连接走线与位于摄像头区域的发光元件连接，从而为位于摄像头区域的发光元件提供驱动信号。
但是，由于非摄像头区域各个像素电路与摄像头区域的发光元件之间的连接走线的长度可能较长，因此信号传输的可靠性较低，会导致显示面板的显示效果较差。
图1是本申请实施例提供的一种显示面板中像素电路的排布示意图。图2是本申请实施例提供的一种显示面板中发光元件的排布示意图。结合图1和图2可以看出，该显示面板10可以包括：衬底基板101，多个第一像素电路组102，多个第一发光元件103，多个第二发光元件104以及多个连接走线105。
图3是本申请实施例提供的一种衬底基板的俯视图。参考图3，该衬底基板101可以具有第一显示区101a和第二显示区101b，第二显示区101b可以至少部分包围第一显示区101a。
结合图1和图3，显示面板10包括的多个第一像素电路组102可以阵列排布于第二显示区101b，每个第一像素电路组102可以包括一个第一像素电路1021和至多六个第二像素电路1022。其中，第一像素电路1021和至多六个第二像素电路1022沿显示面板10的行方向X排布。
例如，图1中每个第一像素电路组102包括四个第二像素电路1022。可选的，每个第一像素电路组102中包括的第二像素电路1022的数量可以与显示面板10中不同颜色的子像素的排布方式有关。其中，显示面板10通常包括红色(red，R)子像素，绿色(green，G)子像素以及蓝色(blue，B)子像素。每个子像素由一个像素电路和一个发光元件构成。
结合图1至图3，多个第二发光元件104可以位于第二显示区101b。其中，多个第二发光元件104可以与多个第一像素电路组102中的第二像素电路1022一一对应，每个第二发光元件104与对应的一个第二像素电路1022连接。由此使得第二像素电路1022为对应的第二发光元件104提供驱动信号。也即是，显示面板10包括的第二发光元件104的数量可以与显示面板10包括的第二像素电路1022的数量相等，且一一对应。位于第二显示区101b的每个子像素可以由一个第二像素电路1022和对应的一个第二发光元件104构成。
另外，显示面板10中的多个第一发光元件103可以位于第一显示区101a。多个连接走线105可以沿显示面板10的行方向X延伸。每个连接走线105的一端可以位于第一显示区101a，且与一个第一发光元件103连接，每个连接走线105的另一端可以位于第二显示区101b，且与一个第一像素电路组102中的第一像素电路1021连接。也即是，位于第二显示区101b的第一像素电路1021通过连接走线105与位于第一显示区101a的第一发光元件103连接，使得第一像素电路1021为第一发光元件103提供驱动信号。
其中，显示面板10包括的连接走线105的数量可以与显示面板10包括的第一发光元件103的数量相等。也即是，多个连接走线105和多个第一发光元件103一一对应。另外，显示面板10包括的第一像素电路1021的数量可以大于显示面板10包括的第一发光元件103的数量。
在本申请实施例中，由于每个第一像素电路组102包括至多六个第二像素电路1022，因此第二显示区101b中每至多六个第二像素电路1022的区域就可以压缩出一个用于为第一显示区101a的第一发光元件103提供驱动信号的第一像素电路1021。由此可以使得连接第一像素电路1021和第一发光元件103的连接走线105的长度可以较短，能够提高连接走线105传输信号的可靠性，确保显示面板10的显示效果。
综上所述，本申请实施例提供了一种显示面板，该显示面板中每个第一像素电路组包括为第二显示区的第二发光元件提供驱动信号的至多六个第二像素电路，因此第二显示区中每至多六个第二像素电路的区域就可以压缩出一个用于为第一显示区的第一发光元件提供驱动信号的第一像素电路。由此可以使得连接第一像素电路和第一发光元件的连接走线的长度可以较短，能够提高连接走线传输信号的可靠性，确保显示面板的显示效果。
可选的，连接走线105的材料可以为透明导电材料，可以避免连接走线105对第一显示区101a的透过率造成影响，并且能够使得第一像素电路1021通过连接走线105为第一发光元件103提供驱动信号。例如，该透明导电材料可以为氧化铟锡(indium tin oxide，ITO)。
在本申请实施例中，每个第一像素电路组102包括的第二像素电路1022的数量可以为偶数。例如，每个第一像素电路组102包括两个第二像素电路1022，或者包括四个第二像素电路1022，又或者包括六个第二像素电路1022。当然，每个第一像素电路组102包括的第二像素电路1022的数量也可以为奇数，本申请实施例对此不做限定。
参考图4可以看出，每个第一像素电路组102中的第二像素电路1022包括：多个第一类第二像素电路1022a和多个第二类第二像素电路1022b。第一类第二像素电路1022a的数量和第二类第二像素电路1022b的数量相同。对于每个第一像素电路组102，第一像素电路组102中的第一像素电路1021位于多个第一类第二像素电路1022a和多个第二类第二像素电路1022b之间。也即是，每个第一像素电路组102中，第一像素电路1021可以设置在该第一像素电路组102包括的所有像素电路的中间位置。
由于为第一发光元件103提供驱动信号的第一像素电路1021设置在中间位置，因此便于使得连接第二显示区101b中位于第一显示区101a的左侧的第一子区域101b1的第一像素电路1021的连接走线105的长度，以及第二显示区101b中位于第一显示区101a的右侧的第二子区域101b2的第一像素电路1021的连接走线105的长度对应相同。由此可以使得显示面板10包括的多个连接走线105的对称性较好，避免显示面板10出现显示不良的问题。
示例的，图4的第一像素电路组102包括四个第二像素电路1022。该四个第二像素电路1022包括两个第一类第二像素电路1022a和两个第二类第二像素电路1022b。当然，在第一像素电路组102包括六个第二像素电路1022的情况下，该六个第二像素电路1022包括三个第一类第二像素电路1022a和三个第二类第二像素电路1022b。在第一像素电路组102包括两个第二像素电路1022的情况下，该两个第二像素电路1022包括一个第一类第二像素电路1022a和一个第二类第二像素电路1022b。
在本申请实施例中，参考图3，衬底基板101还具有第三显示区101c，该 第三显示区101c可以位于第二显示区101b远离第一显示区101a的一侧。显示面板10还可以包括：位于第三显示区101c的多个第二像素电路组106以及多个第三发光元件107。该第二像素电路组106包括第三像素电路1061。多个第三发光元件107与多个第二像素电路组106中的第三像素电路1061一一对应，每个第三发光元件107与对应的一个第三像素电路1061连接，以使得第三像素电路1061为对应的第三发光元件107提供驱动信号。
其中，每个第二像素电路组106包括的第三像素电路1061的数量可以与一个第一像素电路组102包括的第一类第二像素电路1022a的数量相同。
显示面板10中设置有像素电路的各个区域中的像素电路的排布相同。若显示面板10的第三显示区101c(靠近边界的显示区)沿行方向X的尺寸较小，难以以第一像素电路组102为最小重复单元进行设置时，则可以以第二像素电路组106为最小重复单元进行设置。
第二像素电路组106包括的第三像素电路1061的排布可以与第一像素电路组102包括的第一类第二像素电路1022a的排布对应，也可以与第一像素电路组102包括的第二类第二像素电路1022b的排布对应。这取决于第二像素电路组106位于第二显示区101b的左侧的第三显示区101c还是右侧的第三显示区101c。
示例的，若第二像素电路组106位于第二显示区101b的左侧的第三显示区101c，则第二像素电路组106包括的第三像素电路1061的排布可以与第一像素电路组102包括的第二类第二像素电路1022b的排布对应。若第二像素电路组106位于第二显示区101b的右侧的第三显示区101c，则第二像素电路组106包括的第三像素电路1061的排布可以与第一像素电路组102包括的第一类第二像素电路1022a的排布对应。
其中，第二像素电路组106包括的第三像素电路1061的排布与第一像素电路组102包括的第二类第二像素电路1022b的排布对应，可以用于表示：第二像素电路组106包括的第三像素电路1061连接的第三发光元件107发出的光线的颜色，与一个所述第一像素电路组102包括的第二类第二像素电路1022b连接的第二发光元件104发出的光线的颜色对应相同。也即是，第三像素电路1061及其连接的第三发光元件107构成的子像素的颜色，与第二类第二像素电路1022b及其连接的第二发光元件104构成的子像素的颜色对应相同。
第二像素电路组106包括的第三像素电路1061的排布与第一像素电路组102包括的第一类第二像素电路1022a的排布对应，可以用于表示：第二像素电路组106包括的第三像素电路1061连接的第三发光元件107发出的光线的颜色，与一个所述第一像素电路组102包括的第一类第二像素电路1022a连接的第二发光元件104发出的光线的颜色对应相同。也即是，第三像素电路1061及其连接的第三发光元件107构成的子像素的颜色，与第一类第二像素电路1022a及其连接的第二发光元件104构成的子像素的颜色对应相同。
示例的，第一像素电路组102包括两个第一类第二像素电路1022a和两个第二类第二像素电路1022b。相应的，参考图6和图7，每个最小重复单元m从左至右包括与两个第一类第二像素电路1022a连接的两个第二发光元件104，以及与两个第二类第二像素电路1022b连接的两个第二发光元件104。参考图6，这四个第二发光元件104从左至右分别为蓝色发光元件，绿色发光元件，红色发光元件以及绿色发光元件。第二像素电路组106包括与两个第二类第二像素电路1022b对应的两个第三像素电路1061，且这两个第三像素电路1061所连接的两个第三发光元件107分别为红色发光元件和绿色发光元件。其中，蓝色发光元件与其连接的像素电路构成蓝色子像素，绿色发光元件与其连接的像素电路构成绿色子像素，红色发光元件与其连接的像素电路构成红色子像素。图6仅示出了各个发光元件的阳极，并未示出各个发光元件的发光图案以及阴极。
由于第一像素电路组102中的第一像素电路1021设置在第一像素电路组102包括的所有像素电路的中间位置，因此若显示面板10的第三显示区101c可以放置下与第一像素电路组102中第一类第二像素电路1022a(或者第二类第二像素电路1022b)数量相同的第三像素电路1061，则第二像素电路组106可以不包括与第一像素电路1021对应的虚设像素电路。该虚设像素电路是指不与任何发光元件连接的像素电路。
也即是，显示面板10的第三显示区101c沿行方向X的尺寸较小，可以只保留第三像素电路1061(第三像素电路1061可以对应于第一类第二像素电路1022a，也可以对应于第二类第二像素电路1022b)，无需保留虚设像素电路(对应于与第一像素电路1021)。由此可以为衬底基板101的周边区预留出较多的空间，便于设置显示面板10中位于周边区的其他器件。其中，图6中以未示意与虚设像素电路对应的连接结构来表示第二像素电路组106不包括虚设像素电 路，以示意与第一像素电路1061对应的第二连接结构109来表示第一像素电路组106包括第一像素电路1061。
在本申请实施例中，第三显示区101c可以呈条状，且第三显示区101c可以沿显示面板10的列方向Y延伸。当然，在第二显示区101b的四个角呈弧形的情况下，第三显示区101c也可以呈弧形。本申请实施例对第三显示区101c的形状不做限定。
在本申请实施例中，第一显示区101a可以位于衬底基板101沿行方向X的中部。第二显示区101b包括第一子区域101b1和第二子区域101b2，该第一子区域101b1和第二子区域101b2分别位于第一显示区101a沿行方向X的两侧。例如第二显示区101b的第一子区域101b1位于第一显示区101a的左侧，第二显示区101b的第二子区域101b2位于第一显示区101a的右侧。
由于第一显示区101a位于衬底基板101沿行方向X的中部，因此第一子区域101b1的面积和第二子区域101b2的面积可以相同。由此，第一子区域101b1在行方向X上能够设置的第一像素电路组102的数量，可以与第二子像素在行方向X上能够设置的第一像素电路组102的数量。也即是，多个第一像素电路组102中，位于第一子区域101b1的一行第一像素电路组102的数量，与位于第二子区域101b2的一行第一像素电路组102的数量相同。
在本申请实施例中，多个连接走线105可以包括：多个第一类连接走线105a和多个第二类连接走线105b。每个第一类连接走线105a与第一像素电路1021连接的一端位于第一子区域101b1，每个第二类连接走线105b与第一像素电路1021连接的一端位于第二子区域101b2。其中，多个第一类连接走线105a与多个第二类连接走线105b一一对应，且每个第一类连接走线105a沿行方向X的长度，与对应的第二类连接走线105b沿行方向X的长度相等。
示例的，图8是本申请实施例提供的一种第一子区域和第一显示区的局部示意图，图9是本申请实施例提供的一种第二子区域和第一显示区的局部示意图。参考图8和图9，第一类连接走线105a沿行方向X的长度与对应的第二类连接走线105b沿行方向X的长度相等。
由于每个第一类连接走线105a沿行方向X的长度与对应的第二类连接走线105b沿行方向X的长度相等，因此可以确保显示面板10包括的多个连接走线105的对称性，确保显示面板10的显示效果。
在本申请实施例中，多个第一像素电路组102中目标第一像素电路组的第一像素电路1021用于与电源端连接，该电源端可以用于为目标第一像素电路组中的第一像素电路1021提供固定电压的电源信号。其中，目标第一像素电路组的第一像素电路1021不与第一发光元件103连接。
示例的，电源端可以为正极电源信号的电源端，电源端可以用于为目标第一像素电路组中的第一像素电路1021提供正极电源信号。该正极电源信号还可以称为VDD信号。
目标第一像素电路组的第一像素电路1021不与第一发光元件103连接，目标第一像素电路组的第一像素电路1021可以称为虚设像素电路。如果不通过电源端为虚设像素电路提供固定电压的电源信号，则虚设像素电路中信号的变化可能会对其他像素电路的正常工作造成干扰。由此，本申请实施例通过使得电源端为这些虚设像素电路提供一固定电压的电源信号，可以避免虚设像素电路中信号发生变化，可以确保显示面板10中其他像素电路的正常工作，保证显示面板10的显示效果。
在本申请实施例中，参考图10，第一发光元件103可以包括沿远离衬底基板101的方向依次层叠的第一电极b1，发光图案b2以及第二电极b3。每个连接走线105位于第一显示区101a的一端与一个第一发光元件103中的第一电极b1连接。并且，第一发光元件103还可以包括像素界定层b4，该像素界定层b4中可以具有镂空区域，该镂空区域可以用于露出第一电极b1的至少部分，以使得第一电极b1能够和发光图案b2接触。其中，第一电极b1可以为阳极，第二电极b3可以为阴极。
可选的，参考图8和图9，显示面板10还可以包括：多个第一连接结构108和多个第二连接结构109。多个第一连接结构108位于第一显示区101a，多个第二连接结构109位于第二显示区101b。多个第一连接结构108和多个第二连接结构109均与多个连接走线105位于同层。也即是，多个第一连接结构108，多个第二连接结构109以及多个连接走线105可以采用相同材料并由同一次构图工艺制备得到。
其中，第一像素电路1021，多个连接走线105以及第一发光元件103沿远离衬底基板101的方向层叠。由此，多个第一连接结构108以及多个第二连接结构109位于第一像素电路1021和第一发光元件103之间。当然，多个连接走 线105也可以与第一像素电路1021中的导电膜层位于同层，例如，多个连接走线105可以位于源漏极层靠近衬底基板101的一侧的某一导电膜层，或者多个连接走线105位于源漏极层，又或者位于栅极层。其中，在多个连接走线105位于源漏极层的情况下，源漏极层的材料可以为透明导电材料(例如ITO)。在多个连接走线105位于栅极层的情况下，栅极层的材料可以为透明导电材料(例如ITO)。
每个连接走线105位于第一显示区101a的一端和一个第一发光元件103中的第一电极b1通过一个第一连接结构108连接，每个连接走线105位于第二显示区101b的另一端和一个第一像素电路组102中的第一像素电路1021通过一个第二连接结构109连接。也即是，每个连接走线105位于第一显示区101a的一端和一个第一连接结构108连接，且该第一连接结构108可以与一个第一发光元件103中的第一电极b1连接。每个连接走线105位于第二显示区101b的另一端和一个第二连接结构109连接，且该第二连接结构109与一个第一像素电路组102中的第一像素电路1021连接。
在本申请实施例中，第一像素电路1021和连接走线105之间具有第一绝缘层，连接走线105和第一发光元件103中的第一电极b1之间具有的第二绝缘层。该第一绝缘层中可以具有第一过孔，该第一过孔在衬底基板101上的正投影与第二连接结构109在衬底基板101上的正投影至少部分重叠。也即是，该第二连接结构109通过第一过孔与第一像素电路1021连接。并且，第二绝缘层中可以具有第二过孔，该第二过孔在衬底基板101上的正投影与第一连接结构108在衬底基板101上的正投影至少部分重叠。也即是，该第一连接结构108通过第二过孔与第一发光元件103中的第一电极b1连接。
其中，由于多个第一连接结构108和多个第二连接结构109均与多个连接走线105位于同层，因此对于每个连接走线105，该连接走线105连接的一个第一连接结构108，该连接走线105连接的一个第二连接结构109，以及该连接走线105可以为一体结构。
另外，显示面板10还可以包括多个第三连接结构110。该多个第三连接结构110可以位于第二显示区101b。第二发光元件104和第一发光元件103结构相同，也包括沿远离衬底基板101的方向依次层叠的第一电极b1，发光图案b2以及第二电极b3。多个第三连接结构110与多个连接走线105位于同层。也即 是，多个第三连接结构110和多个连接走线105可以采用相同材料并由同一次构图工艺制备得到。
第二像素电路1022，多个第三连接结构110以及第二发光元件104可以沿远离衬底基板101的方向层叠。也即是，多个第三连接结构110位于第二像素电路1022和第二发光元件104之间。当然，多个第三连接结构110也可以与第二像素电路1022中的导电膜层位于同层，例如，多个第三连接结构110可以位于源漏极层靠近衬底基板101的一侧的某一导电膜层，或者多个第三连接结构110位于源漏极层，又或者位于栅极层。其中，在多个第三连接结构110位于源漏极层的情况下，源漏极层的材料可以为透明导电材料(例如ITO)。在多个第三连接结构110位于栅极层的情况下，栅极层的材料可以为透明导电材料(例如ITO)。
每个第二发光元件104中的第一电极b1和一个第二像素电路1022通过一个第三连接结构110连接。也即是，每个第二发光元件104中的第一电极b1和一个第三连接结构110连接，该第三连接结构110和一个第二像素电路1022连接。
在本申请实施例中，第二像素电路1022和第一像素电路1021可以一同制备得到。由此第二像素电路1022和连接走线105之间也具有第一绝缘层，连接走线105和第二发光元件104中的第一电极b1之间也具有的第二绝缘层。该第一绝缘层中可以具有第三过孔，该第三过孔在衬底基板101上的正投影与第三连接结构110在衬底基板101上的正投影至少部分重叠。也即是，该第三连接结构110通过第三过孔与第二像素电路1022连接。并且，第二绝缘层中可以具有第四过孔，该第四过孔在衬底基板101上的正投影与第三连接结构110在衬底基板101上的正投影至少部分重叠。也即是，该第三连接结构110通过第四过孔与第二发光元件104中的第一电极b1连接。
在本申请实施例中，多个连接走线105可以包括多个第一层连接走线和多个第二层连接走线。显示面板10还包括位于多个第一层连接走线和多个第二层连接走线之间的绝缘层(例如称为第三绝缘层)。其中，多个第一发光元件103中，一部分第一发光元件103和第一层连接走线连接，另一部分第一发光元件103和第二层连接走线连接。
在连接走线105的数量较多的情况下，多个连接走线105可以通过两层走 线层来排布，避免由于连接走线105的数量较多而导致相邻的连接走线105之间的距离较小，保证连接走线105传输信号的可靠性。
可选的，多个第一层连接走线在衬底基板101上的正投影，可以与多个第二层连接走线在衬底基板101上的正投影交替排布。由于第一层连接走线和第二层连接走线交替设置，因此可以使得位于同层且相邻的两个连接走线105之间的距离足够大，保证信号传输的可靠性。
当然，多个连接走线105还可以包括更多层的连接走线105，且相邻的两层连接走线105之间均设置有绝缘层，本申请实施例对连接走线105的设置层数不做限定。
综上所述，本申请实施例提供了一种显示面板，该显示面板中每个第一像素电路组包括为第二显示区的第二发光元件提供驱动信号的至多六个第二像素电路，因此第二显示区中每至多六个第二像素电路的区域就可以压缩出一个用于为第一显示区的第一发光元件提供驱动信号的第一像素电路。由此可以使得连接第一像素电路和第一发光元件的连接走线的长度可以较短，能够提高连接走线传输信号的可靠性，确保显示面板的显示效果。
图11是本申请实施例提供的一种显示装置的结构示意图。参考图11，该显示装置可以包括：感光元件20，以及如上述实施例所提供的显示面板10。其中，该感光元件20可以位于显示面板的第一显示区101a内。
该第一显示区101a可以为图11所示的矩形，感光元件20在衬底基板00上的正投影的面积可以小于等于第一显示区101a的内切圆的面积。即，感光元件20所处区域的尺寸可以小于或等于该第一显示区101a的内切圆的尺寸。例如，结合图11，其示出的显示面板10中，感光元件20所处区域的尺寸等于第一显示区101a的内切圆N的尺寸，即该感光元件20所在区域的形状可以为圆形，相应的，该感光元件20所在区域也可以称为透光孔。当然，在一些实施例中，第一显示区101a也可以为除矩形之外的其他形状，如圆形。
可选的，该感光元件20可以为摄像头。
在本申请实施例中，该显示装置可以为有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、无源矩阵有机发光二极管(passive-matrix organic light-emitting diode，PMOLED)显示装置、 量子点发光二极管(quantum dot light emitting diodes，QLED)显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示面板，其特征在于，所述显示面板(10)包括：
    衬底基板(101)，所述衬底基板(101)具有第一显示区(101a)和第二显示区(101b)，所述第二显示区(101b)至少部分包围所述第一显示区(101a)；
    多个第一像素电路组(102)，所述多个第一像素电路组(102)阵列排布于所述第二显示区(101b)，每个所述第一像素电路组(102)包括一个第一像素电路(1021)和至多六个第二像素电路(1022)，所述第一像素电路(1021)和所述至多六个第二像素电路(1022)沿所述显示面板(10)的行方向(X)排布；
    多个第一发光元件(103)，所述多个第一发光元件(103)位于所述第一显示区(101a)；
    多个第二发光元件(104)，所述多个第二发光元件(104)位于所述第二显示区(101b)，所述多个第二发光元件(104)与所述多个第一像素电路组(102)中的第二像素电路(1022)一一对应，每个所述第二发光元件(104)与对应的一个所述第二像素电路(1022)连接；
    以及，多个连接走线(105)，所述多个连接走线(105)沿所述行方向(X)延伸，每个所述连接走线(105)的一端位于所述第一显示区(101a)，且与一个所述第一发光元件(103)连接，每个所述连接走线(105)的另一端位于所述第二显示区(101b)，且与一个所述第一像素电路组(102)中的第一像素电路(1021)连接。
  2. 根据权利要求1所述的显示面板，其特征在于，每个所述第一像素电路组(102)包括的所述第二像素电路(1022)的数量为偶数。
  3. 根据权利要求2所述的显示面板，其特征在于，每个所述第一像素电路组(102)中的所述第二像素电路(1022)包括：多个第一类第二像素电路(1022a)和多个第二类第二像素电路(1022b)；
    其中，所述第一类第二像素电路(1022a)的数量和所述第二类第二像素电路(1022b)的数量相同，对于每个所述第一像素电路组(102)，所述第一像 素电路组(102)中的第一像素电路(1021)位于所述多个第一类第二像素电路(1022a)和所述多个第二类第二像素电路(1022b)之间。
  4. 根据权利要求3所述的显示面板，其特征在于，所述衬底基板(101)还具有第三显示区(101c)，所述第三显示区(101c)位于所述第二显示区(101b)远离所述第一显示区(101a)的一侧；所述显示面板(10)还包括：
    多个第二像素电路组(106)，所述多个第二像素电路组(106)位于所述第三显示区(101c)，所述第二像素电路组(106)包括第三像素电路(1061)；
    以及，多个第三发光元件(107)，所述多个第三发光元件(107)位于所述第三显示区(101c)，所述多个第三发光元件(107)与所述多个第二像素电路组(106)中的第三像素电路(1061)一一对应，每个所述第三发光元件(107)与对应的一个所述第三像素电路(1061)连接；
    其中，每个所述第二像素电路组(106)包括的第三像素电路(1061)的数量与一个所述第一像素电路组(102)包括的第一类第二像素电路(1022a)的数量相同。
  5. 根据权利要求4所述的显示面板，其特征在于，所述第二像素电路组(106)包括的第三像素电路(1061)连接的所述第三发光元件(107)发出的光线的颜色，与一个所述第一像素电路组(102)包括的第一类第二像素电路(1022a)连接的所述第二发光元件(104)发出的光线的颜色对应相同；
    或者，所述第二像素电路组(106)包括的第三像素电路(1061)连接的所述第三发光元件(107)发出的光线的颜色，与一个所述第一像素电路组(102)包括的第二类第二像素电路(1022b)连接的所述第二发光元件(104)发出的光线的颜色对应相同。
  6. 根据权利要求4所述的显示面板，其特征在于，所述第三显示区(101c)呈条状，且所述第三显示区(101c)沿所述显示面板(10)的列方向(Y)延伸。
  7. 根据权利要求2至6任一所述的显示面板，其特征在于，每个所述第一像素电路组(102)包括四个所述第二像素电路(1022)。
  8. 根据权利要求1至7任一所述的显示面板，其特征在于，所述第一显示区(101a)位于所述衬底基板(101)沿所述行方向(X)的中部；所述第二显示区(101b)包括第一子区域(101b1)和第二子区域(101b2)；所述第一子区域(101b1)和所述第二子区域(101b2)分别位于所述第一显示区(101a)沿所述行方向(X)的两侧；
    其中，所述多个第一像素电路组(102)中，位于所述第一子区域(101b1)的一行第一像素电路组(102)的数量，与位于所述第二子区域(101b2)的一行第一像素电路组(102)的数量相同。
  9. 根据权利要求8所述的显示面板，其特征在于，所述多个连接走线(105)包括：多个第一类连接走线(105a)和多个第二类连接走线(105b)；
    每个所述第一类连接走线(105a)与所述第一像素电路(1021)连接的一端位于所述第一子区域(101b1)，每个所述第二类连接走线(105b)与所述第一像素电路(1021)连接的一端位于所述第二子区域(101b2)；
    其中，所述多个第一类连接走线(105a)与所述多个第二类连接走线(105b)一一对应，且每个所述第一类连接走线(105a)沿所述行方向(X)的长度，与对应的所述第二类连接走线(105b)沿所述行方向(X)的长度相等。
  10. 根据权利要求1至9任一所述的显示面板，其特征在于，所述多个第一像素电路组(102)中目标第一像素电路组的第一像素电路(1021)用于与电源端连接，所述电源端用于为所述第一像素电路(1021)提供固定电压的电源信号；
    其中，所述目标第一像素电路组的第一像素电路(1021)不与所述第一发光元件(103)连接。
  11. 根据权利要求1至10任一所述的显示面板，其特征在于，所述第一发光元件(103)包括沿远离所述衬底基板(101)的方向依次层叠的第一电极(b1)，发光图案(b2)以及第二电极(b3)；
    每个所述连接走线(105)位于所述第一显示区(101a)的一端与一个所述 第一发光元件(103)中的第一电极(b1)连接。
  12. 根据权利要求11所述的显示面板，其特征在于，所述显示面板(10)还包括：多个第一连接结构(108)和多个第二连接结构(109)，所述多个第一连接结构(108)位于所述第一显示区(101a)，所述多个第二连接结构(109)位于所述第二显示区(101b)；
    其中，所述多个第一连接结构(108)和所述多个第二连接结构(109)均与所述多个连接走线(105)位于同层，每个连接走线(105)位于所述第一显示区(101a)的一端和一个所述第一发光元件(103)中的第一电极(b1)通过一个所述第一连接结构(108)连接，每个连接走线(105)位于所述第二显示区(101b)的另一端和一个所述第一像素电路组(102)中的第一像素电路(1021)通过一个所述第二连接结构(109)连接。
  13. 根据权利要求12所述的显示面板，其特征在于，对于每个所述连接走线(105)，所述连接走线(105)连接的一个第一连接结构(108)，所述连接走线(105)连接的一个第二连接结构(109)以及所述连接走线(105)为一体结构。
  14. 根据权利要求1至13任一所述的显示面板，其特征在于，所述显示面板(10)还包括多个第三连接结构(110)，所述多个第三连接结构(110)位于所述第二显示区(101b)；所述第二发光元件(104)包括沿远离所述衬底基板(101)的方向依次层叠的第一电极(b1)，发光图案(b2)以及第二电极(b3)；
    所述多个第三连接结构(110)与所述多个连接走线(105)位于同层，每个所述第二发光元件(104)中的第一电极(b1)和一个所述第二像素电路(1022)通过一个所述第三连接结构(110)连接。
  15. 根据权利要求1至14任一所述的显示面板，其特征在于，所述连接走线(105)的材料为透明导电材料。
  16. 根据权利要求15所述的显示面板，其特征在于，所述透明导电材料为氧 化铟锡。
  17. 根据权利要求1至16任一所述的显示面板，其特征在于，所述多个连接走线(105)包括多个第一层连接走线和多个第二层连接走线；所述显示面板(10)还包括：位于所述多个第一层连接走线和所述多个第二层连接走线之间的绝缘层；
    其中，所述多个第一发光元件(103)中，一部分第一发光元件(103)和所述第一层连接走线连接，另一部分第一发光元件(103)和所述第二层连接走线连接。
  18. 根据权利要求17所述的显示面板，其特征在于，所述多个第一层连接走线在所述衬底基板(101)上的正投影，与所述多个第二层连接走线在所述衬底基板(101)上的正投影交替排布。
  19. 一种显示装置，其特征在于，所述显示装置包括：感光元件(20)，以及如权利要求1至18任一所述的显示面板(10)；
    其中，所述感光元件(20)位于所述显示面板(10)的第一显示区(101a)内。
  20. 根据权利要求19所述的显示装置，其特征在于，所述感光元件(20)为摄像头。
PCT/CN2022/075443 2022-02-08 2022-02-08 显示面板及显示装置 WO2023150902A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280000134.6A CN117158125A (zh) 2022-02-08 2022-02-08 显示面板及显示装置
PCT/CN2022/075443 WO2023150902A1 (zh) 2022-02-08 2022-02-08 显示面板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/075443 WO2023150902A1 (zh) 2022-02-08 2022-02-08 显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2023150902A1 true WO2023150902A1 (zh) 2023-08-17

Family

ID=87563315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/075443 WO2023150902A1 (zh) 2022-02-08 2022-02-08 显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN117158125A (zh)
WO (1) WO2023150902A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265455A (zh) * 2019-06-25 2019-09-20 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
US20200052048A1 (en) * 2018-08-10 2020-02-13 Au Optronics Corporation Display apparatus
CN113517324A (zh) * 2021-05-25 2021-10-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
EP3944225A1 (en) * 2020-07-21 2022-01-26 Samsung Display Co., Ltd. Display device
CN113990909A (zh) * 2021-10-28 2022-01-28 京东方科技集团股份有限公司 显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200052048A1 (en) * 2018-08-10 2020-02-13 Au Optronics Corporation Display apparatus
CN110265455A (zh) * 2019-06-25 2019-09-20 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
EP3944225A1 (en) * 2020-07-21 2022-01-26 Samsung Display Co., Ltd. Display device
CN113517324A (zh) * 2021-05-25 2021-10-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN113990909A (zh) * 2021-10-28 2022-01-28 京东方科技集团股份有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN117158125A (zh) 2023-12-01

Similar Documents

Publication Publication Date Title
US11322567B2 (en) Display panel, manufacture method thereof and display apparatus
CN110890026B (zh) 显示面板及显示装置
JP7329685B2 (ja) 表示パネル
US10756147B2 (en) Organic light-emitting display panel with improved resolution and electronic device
US20240062717A1 (en) Display panel and display device
KR20210002102A (ko) 디스플레이 패널 및 그 제조 방법 및 디스플레이 디바이스
CN114830220A (zh) 显示面板及显示装置
US20240021146A1 (en) Display substrate, display panel, and display device
US20230337494A1 (en) Display panel and display apparatus
US20230329062A1 (en) Display panel and display apparatus
KR20230158123A (ko) 표시 패널 및 표시 장치
CN216623636U (zh) 显示面板及显示装置
KR20230144108A (ko) 표시 패널 및 표시 장치
US20230132313A1 (en) Display panel and manufacturing method thereof, and display device
CN215266306U (zh) 显示面板及显示装置
WO2021227025A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021248489A1 (zh) 显示基板及显示装置
US11387310B2 (en) Array substrate with connection portion connecting power bus and power line and display panel
CN218851230U (zh) 显示面板及显示装置
WO2023150902A1 (zh) 显示面板及显示装置
WO2022262047A1 (zh) 触控显示面板
WO2023010944A1 (zh) 显示面板及终端设备
WO2023206138A1 (zh) 显示基板和显示装置
WO2022222407A1 (zh) 显示面板及显示装置
WO2023137663A1 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 18020645

Country of ref document: US