WO2021237725A9 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021237725A9
WO2021237725A9 PCT/CN2020/093492 CN2020093492W WO2021237725A9 WO 2021237725 A9 WO2021237725 A9 WO 2021237725A9 CN 2020093492 W CN2020093492 W CN 2020093492W WO 2021237725 A9 WO2021237725 A9 WO 2021237725A9
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WO
WIPO (PCT)
Prior art keywords
line
electrically connected
data
signal line
power
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Application number
PCT/CN2020/093492
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English (en)
French (fr)
Other versions
WO2021237725A1 (zh
Inventor
徐攀
林奕呈
王玲
王国英
张星
韩影
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/273,290 priority Critical patent/US11758780B2/en
Priority to EP20904248.0A priority patent/EP3992705A4/en
Priority to CN202080000853.9A priority patent/CN114072724B/zh
Priority to PCT/CN2020/093492 priority patent/WO2021237725A1/zh
Publication of WO2021237725A1 publication Critical patent/WO2021237725A1/zh
Publication of WO2021237725A9 publication Critical patent/WO2021237725A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to, but is not limited to, the field of display, and in particular, to a display substrate and a display device.
  • the first power supply wiring is electrically connected to the first power supply wiring
  • the data wiring is electrically connected to the data signal wiring
  • the reference wiring is electrically connected to the reference signal wiring
  • the first power line is located on the first side of the display area
  • the data line is located on the second side of the display area, and the second side is different from the first side
  • the data line and the reference trace is located on the same side of the display area
  • the resistance of the first power line is greater than the resistance of the data signal line and greater than the resistance of the reference signal line.
  • the line width of the first power supply line is larger than the line width of the data signal line and larger than the line width of the reference signal line.
  • the display substrate further includes: a second power line and a second power line located in the non-display area;
  • the second power line and the reference line are disposed in different layers, and the orthographic projection of the second power line on the substrate is the same as the reference line on the substrate. There is an overlapping area in the orthographic projection;
  • the second power line is electrically connected to the reference line.
  • the display substrate further includes: a flexible circuit board, a source driver chip located in the non-display area, and at least one pad; the pad and the first power trace are located in the On the same side of the display area, the source driver chip and the data wiring are located on the same side of the display area; the source driver chip is located on the side of the second power line away from the display area;
  • the source driver chip is electrically connected to the data wiring, and is configured to provide a data signal to the data signal line through the data wiring;
  • the flexible circuit board is electrically connected to the pad and the second power supply line respectively, and is configured to supply power to the first power supply line and to the second power supply line through the solder pad.
  • the display substrate further includes: a peripheral circuit board, a flexible signal line, a source driver chip and at least one pad located in the non-display area; the pad and the first power supply
  • the traces are located on the same side of the display area, the source driver chips and the data traces are located on the same side of the display area; the source driver chips are located on the second power lines away from the display area side;
  • the source driver chip is electrically connected to the data wiring, and is configured to provide a data signal to the data signal line through the data wiring;
  • the peripheral circuit board is electrically connected to the pad, the second power supply wiring and the source driver chip respectively through the flexible signal line, and is configured to supply power to the first power supply wiring through the pad , supply power to the second power supply wiring, and provide signals to the source driver chip.
  • the driving structure layer further includes: a plurality of first power supply connection lines located in the display area and extending along the second direction; the first power supply connection lines are connected to the first power supply connection line. 1. Different layers of power lines are set;
  • the orthographic projection of the at least one first power supply connection line on the substrate and the orthographic projection of the first power supply line on the substrate have an overlapping area; each of the at least one first power supply connection line is electrically connected to the first power supply line. connect.
  • the driving structure layer further includes: a plurality of scan signal lines and a plurality of reset signal lines extending along the second direction and a plurality of driving structures arranged in a matrix, the first power supply The wire is arranged between two adjacent drive structures;
  • each driving structure includes: a first driving circuit, a second driving circuit and a third driving circuit arranged along the second direction.
  • the display substrate further includes: a gate driving circuit located in the non-display area; the gate driving circuit is located on a third side of the display area, and the third side is connected to the display area. a different side of the first side and the second side;
  • the gate driving circuit which is electrically connected to the scan signal line and the reset signal line, respectively, and is configured to provide signals to the scan signal line and the reset signal line;
  • the gate drive circuit includes: a plurality of shift registers, each shift register includes: a first shift register and a second shift register; the first shift register is electrically connected to the scanning signal line and is set to A signal is provided to the scanning signal line, a second shift register is electrically connected to the reset signal line, and is configured to provide a signal to the reset signal line; a plurality of first shift registers are cascaded, and a plurality of second shift registers are cascaded .
  • the display substrate further includes: a scan line and a reset line; the scan line is electrically connected to the scan signal line and the gate driving circuit, respectively, and the reset line, respectively electrically connected to the reset signal line and the gate driving circuit;
  • the gate driving circuit includes: a plurality of shift register groups, each shift register group includes: at least one shift register; all the shift registers in each shift register group are arranged along the first direction;
  • a plurality of shift registers are arranged in a staircase shape, and the distance between adjacent shift registers along the second direction is greater than the sum of the length of the scan line and the length of the reset line.
  • the data signal line includes: a first data line, a second data line and a third data line; the first data line and the first driving circuit electrically connected, the second data line is electrically connected to the second drive circuit, the third data line is electrically connected to the third drive circuit; the reference signal line is respectively connected to the first drive circuit, the second drive circuit and the third drive circuit are electrically connected;
  • the first data line and the second data line are located between the first driving circuit and the second driving circuit, and the second data line is located between the first data line and the second driving circuit
  • the third data line and the reference signal line are located between the second driving circuit and the third driving circuit, and the third data line is located near the reference signal line and the third one side of the drive circuit;
  • the first data line and the reference signal line are located between the first driving circuit and the second driving circuit, and the first data line is located between the reference signal line and the second driving circuit one side; the second data line and the third data line are located between the second driving circuit and the third driving circuit, and the third data line is located near the second data line one side of the third drive circuit.
  • the first driving circuit and the third driving circuit are mirror-symmetrical with respect to a center line of the first data line and the third data line.
  • the third driving circuit in the first driving structure and the first driving circuit in the second driving structure are mirror-symmetrical with respect to the first power supply line located between the first driving structure and the second driving structure ;
  • the third driving circuit in the second driving structure and the first driving circuit in the third driving structure are mirror-symmetrical with respect to the first power supply line located between the second driving structure and the third driving structure .
  • the driving structure layer further includes: a first reference connection line and a second reference connection line extending along the second direction;
  • the first reference connection line and the second reference connection line are disposed in different layers; the second reference connection line is electrically connected to the reference signal line and the first reference connection line, respectively.
  • each driving structure includes two first reference connection lines arranged along the second direction and three second reference connection lines arranged along the second direction;
  • the first first reference connection line is electrically connected to the first second reference connection line and the second second reference connection line respectively;
  • the second first reference connection line is electrically connected to the second second reference connection line and the third second reference connection line respectively;
  • One of the second reference connection lines is electrically connected to the reference signal line and is a continuous integral structure.
  • the display substrate further includes: a light-emitting structure layer located on a side of the driving structure layer away from the substrate, the light-emitting structure layer including: a plurality of light-emitting elements;
  • Each driving structure in the driving structure layer includes: a pixel driving circuit configured to drive the light-emitting element to emit light;
  • the pixel drive circuit includes: a first transistor, a second transistor, a third transistor and a storage capacitor; the second transistor is a drive transistor; the storage capacitor includes: a first electrode plate and a second electrode plate;
  • the control electrode of the first transistor is electrically connected to the scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrodes of the two transistors are electrically connected to the first node, the first electrodes of the second transistors are electrically connected to the first power line, and the second electrodes of the second transistors are electrically connected to the second node;
  • the third transistor The control electrode of the third transistor is electrically connected to the reset signal line, the first electrode of the third transistor is electrically connected to the reference signal line, the second electrode of the third transistor is electrically connected to the second node, and the first electrode of the storage capacitor is electrically connected the plate is electrically connected to the second node, and the second plate of the storage capacitor is electrically connected to the first node;
  • the first pole of the light-emitting element is electrically connected to the second node, and the second pole of the light-emitting element is electrically connected to the second power line.
  • the driving structure layer includes: a first insulating layer, an active layer, a second insulating layer, a first metal layer, a third insulating layer, and a first insulating layer, which are sequentially arranged along a direction perpendicular to the substrate. two metal layers;
  • the active layer includes: active layers of all transistors;
  • the first metal layer includes: a first reference connection line, control electrodes of all transistors, a first electrode plate, a reset signal line, a scan signal line and a first power supply a connecting line;
  • the second metal layer includes: a second reference connecting line, a reference signal line, a data line, a second electrode plate, and the first and second electrodes of all transistors.
  • the third insulating layer is provided with a first via hole exposing the first power supply electrical connection line and a second via hole exposing the first reference electrical connection line;
  • the first power line is electrically connected to the first power supply electrical connection line through the first via hole
  • the second reference connection line is electrically connected to the first reference connection line through the second via hole
  • the second power supply line and the scanning signal line are arranged in the same layer;
  • the third insulating layer is provided with a connection via hole exposing the second power line
  • the reference trace is electrically connected to the second power line through the connection via hole.
  • the light-emitting structure layer includes: a first electrode, an organic light-emitting layer, and a second electrode; the first electrode is located on a side of the organic light-emitting layer close to the substrate, and the second electrode is located on a side of the organic light-emitting layer close to the substrate. an electrode is located on a side of the organic light-emitting layer away from the substrate;
  • the orthographic projection of the second electrode on the substrate and the orthographic projection of the second power line on the substrate have an overlapping area, and the second electrode is electrically connected to the second power line.
  • the data trace length is negatively correlated with the data signal wire length.
  • the shape of the display area is a circle, an ellipse, a fan, a heart, a triangle or an N-gon, and N is greater than 4.
  • the present disclosure also provides a display device, comprising: the above-mentioned display substrate.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Fig. 3 is the enlarged schematic diagram of the dotted line part of Fig. 1 and Fig. 2;
  • FIG. 4 is a schematic diagram of a partial display area of a display substrate provided by an exemplary embodiment
  • FIG. 5 is a top view of a first power supply line and a first power supply connection line in an exemplary embodiment
  • FIG. 6 is a schematic diagram of a gate driving circuit provided by an exemplary embodiment
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment
  • FIG. 8 is a working timing diagram of a pixel driving circuit provided by an exemplary embodiment
  • FIG. 9 is a schematic layout diagram of a driving structure provided by an exemplary embodiment
  • FIG. 10 to FIG. 12 are schematic diagrams of a manufacturing process of a display substrate provided by an exemplary embodiment.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • the special-shaped display is a special-shaped display transformed on the basis of the traditional display, so that the characteristics of the display can better adapt to the overall structure and environment of the building.
  • the common special-shaped screens mainly include fan-shaped, arc-shaped, circular, cylindrical, triangular and other structural forms.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is an enlarged schematic diagram of the dotted line portion of FIGS. 1 and 2 .
  • the display substrate provided by the embodiments of the present disclosure includes: a display area AA and a non-display area BB.
  • the display substrate includes: a base, a driving structure layer and a wiring layer located in the display area and arranged on the base; the driving structure layer is located in the display area AA, and the wiring layer is located in the non-display area BB; the driving structure layer includes: along the first The first power supply line VDD, the data signal line Data and the reference signal line Vref extending in the direction; the wiring layer includes: the first power supply wiring 301 , the data wiring 201 and the reference wiring 202 .
  • the special-shaped boundary of the display substrate in FIG. 1 and FIG. 2 is different, the special-shaped boundary in FIG. 1 is a heart shape, and the special-shaped boundary in FIG. 2 is an ellipse.
  • the first power line 301 is electrically connected to the first power line VDD
  • the data line 201 is electrically connected to the data signal line Data
  • the reference line 202 is connected to the reference signal line Vref.
  • the first power trace 301 is located on the first side of the display area
  • the data trace 201 is located on the second side of the display area AA.
  • the first side is different from the second side
  • the data trace 201 and the reference trace 202 are located on the same side of the display area. side.
  • first side and the second side may be opposite sides, and the second side is a side away from the first side.
  • a and B are positioned opposite each other when B is on the side away from A.
  • the first power supply line VDD includes a first end A1 and a second end A2 which are oppositely disposed.
  • the first side refers to the side of the display area located close to the first end A1 of the first power line VDD, and the second side refers to the side close to the second end A2 of the first power line VDD.
  • the resistance of the first power line VDD is greater than that of the data signal line Data and greater than that of the reference signal line Vref.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal foil; the flexible substrate may be, but not limited to, polyparaphenylene ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , one or more of textile fibers.
  • the first power line VDD is configured to continuously provide a high-level power signal.
  • the display area AA has a contoured boundary.
  • the non-display area BB surrounds the display area AA.
  • the boundary of the non-display area BB may be a special-shaped boundary, and FIGS. 1 and 2 are described by taking an example that the boundary of the non-display area BB is a special-shaped boundary.
  • the number of the first power supply lines 301 is multiple, and the number of the first power supply lines VDD is multiple.
  • the plurality of first power lines 301 are in one-to-one correspondence with the plurality of first power lines VDD.
  • Each of the first power supply lines 301 is connected to the corresponding first power supply line VDD.
  • the first power supply line 301 and the first power supply line VDD may be disposed in the same layer, or may be disposed in different layers.
  • the number of data traces 201 is multiple, and the number of data signal lines Data is multiple.
  • the plurality of data traces 201 are in one-to-one correspondence with the plurality of data signal lines Data.
  • Each data trace 201 is connected to the corresponding data signal line Data.
  • the data wiring 201 and the data signal line Data may be arranged at the same layer, or may be arranged at different layers.
  • the number of reference traces 202 is multiple, and the number of reference signal lines Vref is multiple.
  • the plurality of reference traces 202 are in one-to-one correspondence with the plurality of reference signal lines Vref.
  • Each reference trace 202 is connected to the corresponding reference signal line Vref.
  • the reference trace 202 and the reference signal line Vref may be disposed in the same layer, or may be disposed in different layers.
  • the length of the data line and the The length of the data signal line connected to it is negatively correlated, and the longer the data signal line is, the shorter the length of the data line connected to it. That is, the difference in the length of the data trace is used to compensate the load difference of the data signal line.
  • the display substrate provided by the embodiment of the present disclosure includes: a display area and a non-display area, and the display substrate includes: a substrate, a driving structure layer and a wiring layer disposed on the substrate; the driving structure layer is located in the display area, and the wiring layer is located in the non-display area ;
  • the driving structure layer includes: a first power supply line, a data signal line and a reference signal line extending along a first direction;
  • the line layer includes: a first power supply line, a data line and a reference line; the first power supply line and the The first power line is electrically connected, the data line is electrically connected with the data signal line, and the reference line is electrically connected with the reference signal line;
  • the first power line is located on the first side of the display area, and the data line is located on the second side of the display area , the second side is different from the first side;
  • the data wiring and the reference wiring are located on the same side of the display area; for the first power supply line, the data signal line and
  • the line width of the first power supply line VDD is larger than the line width of the data signal line Data, and is larger than the line width of the reference signal line Vref, which can reduce the resistance of the first power supply line VDD.
  • the larger the size of the display substrate the larger the line width of the first power supply line VDD.
  • the line width of the first power supply line VDD in a 55-inch display substrate can reach ten microns.
  • the display substrate further includes: a second power supply line VSS and a second power supply wiring 401 located in the non-display area BB.
  • the second power line VSS is electrically connected to the second power line 401 , and the second power line VSS extends along the second direction.
  • the second power line VSS and the second power line 401 are located on the same side of the display area AA, and the second power line 401 and the data line 201 are located on the same side of the display area AA.
  • the second direction intersects the first direction, and a plane where the first direction and the second direction are located is a plane where the display substrate is located.
  • the first direction is perpendicular to the second direction.
  • the second power line VSS and the reference line 202 are disposed in different layers, and the orthographic projection of the second power line VSS on the substrate and the orthographic projection of the reference line 202 on the substrate have an overlapping area; the second power line VSS and the reference line 202 electrical connection.
  • the second power supply line VSS is electrically connected to the reference signal line Vref through the reference trace 202, which not only ensures that when the pixel driving circuit initializes the first pole of the light-emitting element, the first The signals of the pole and the second pole are equal, and at the same time, the normal display of the display substrate is ensured, the display effect of the display substrate is improved, and the signal wiring is saved.
  • the second power supply line VSS is configured to continuously provide a low-level power supply signal.
  • a display substrate provided by an exemplary embodiment may further include: a flexible circuit board (not shown in the figure), a source driver chip 20 and at least one bonding pad 30 located in the non-display area BB .
  • the pads 30 and the first power traces 301 are located on the same side of the display area AA, the source driver chip 20 and the data traces 201 are located on the same side of the display area AA; the source driver chip 20 is located on the second power trace VSS away from the display area AA side.
  • the source driver chip is electrically connected to the data wiring 201 , and is configured to provide data signals to the data signal line Data through the data wiring 201 .
  • the flexible circuit board is electrically connected to the pads 30 and the second power traces 401 respectively, and is configured to supply power to the first power traces 301 and to the second power traces 401 through the pads 30 .
  • the flexible circuit board may be disposed at any position of the display substrate.
  • the flexible circuit board starts supplying power to the first power supply trace along the side of the first power cord away from the source driver chip, and starts supplying power to the second power trace along the side of the first power cord close to the source driver chip, so that the The sum of the voltage drop of the first power line and the second power line is greatly reduced, which can improve the display effect of the display substrate.
  • the pads 30 and the first power traces 301 are located on the same side of the display area AA, the source driver chip 20 and the data traces 201 are located on the same side of the display area AA; the source driver chip 20 is located on the second power trace VSS away from the display area AA side.
  • the source driver chip is electrically connected to the data wiring 201 , and is configured to provide data signals to the data signal line Data through the data wiring 201 .
  • one end of the flexible signal line is bound to the substrate, and the other end is bound to a peripheral circuit board, and the peripheral circuit board is routed to the first power supply line, the first power supply line, the second Two power traces and source driver chips supply power.
  • the peripheral circuit board and the flexible signal line may be disposed at any position of the display substrate.
  • the peripheral circuit board and the flexible signal line start supplying power to the first power line along the side of the first power line that is far away from the source driver chip, and start supplying power to the second power line along the side of the first power line close to the source driver chip. , the sum of the voltage drop of the first power line and the second power line can be greatly reduced, and the display effect of the display substrate can be improved.
  • the number of source driver chips may be determined according to the size of the display substrate, and the larger the size of the display substrate, the greater the number of source driver chips.
  • FIG. 1 and FIG. 2 take a source driver chip as an example for description.
  • the first power supply line VL and the first power supply line VDD are disposed in different layers.
  • the orthographic projection of the at least one first power supply line VL on the substrate and the orthographic projection of the first power supply line VDD on the substrate have an overlapping area.
  • Each of the at least one first power supply connection lines VL is electrically connected to the first power supply line VDD.
  • Each of the at least one first power supply connection line is electrically connected to the first power supply line, which can reduce display unevenness of the display substrate caused by different voltage drops of different first power supply lines in the display substrate, and improve the display effect of the display substrate.
  • the fabrication material of the first power supply line VDD may be the same as the fabrication material of the first power supply connection line VL, or may be different from the fabrication material of the first power supply connection line VL.
  • the driving structure layer may include M rows and N columns of driving structures, and M and N may be positive integers greater than 1.
  • FIG. 4 is an example of a driving structure with three rows and three columns in the driving structure layer.
  • the reset signal line Reset and the first power supply connection line VL are arranged to define a row of driving structures, and the adjacent first power supply lines are arranged to define a column of driving structures.
  • FIG. 6 is a schematic diagram of a gate driving circuit provided by an exemplary embodiment.
  • a display substrate provided by an exemplary embodiment further includes: a gate driving circuit located in a non-display area.
  • the gate driving circuit is located on a third side of the display area, and the third side is a side different from the first side and the second side.
  • the gate driving circuit is electrically connected to the scan signal line Scan and the reset signal line Reset respectively, and is configured to provide signals to the scan signal line and the reset signal line.
  • the gate driving circuit includes a plurality of shift registers 50 .
  • a plurality of shift registers are arranged along the edges of the display area.
  • Each shift register 50 includes a first shift register GOA1 and a second shift register GOA2.
  • the first shift register GOA1 electrically connected to the scan signal line Scan, is configured to supply signals to the scan signal line Scan
  • the second shift register GAO2, electrically connected to the reset signal line Reset is configured to supply signals to the reset signal line Reset.
  • a plurality of first shift registers GOA1 are cascaded, and a plurality of second shift registers GOA2 are cascaded.
  • the first shift register and the second shift register in each shift register are arranged along the first direction.
  • the display substrate further includes: a scan line SL and a reset line RL; the scan line SL is electrically connected to the scan signal line and the gate driving circuit, respectively, and the reset line The line RL is electrically connected to the reset signal line and the gate driving circuit, respectively.
  • a plurality of shift registers are arranged in a stair-like arrangement, and the distance L along the second direction between adjacent shift registers is greater than the sum of the length of the scan line and the length of the reset line. The smaller the distance between adjacent shift registers along the second direction, the easier it is for the display substrate to realize a narrow frame.
  • a plurality of shift register groups are disposed around the edges of the display area, at least partially surrounding the display area.
  • the arrangement of the shift registers is determined according to the contoured boundary.
  • the gate driving circuit is located on the third side of the display area.
  • the scan signal line Scan includes a first end B1 and a second end B2 that are oppositely arranged.
  • the third side may be a side close to the first end B1 of the scan signal line Scan, or a side close to the second end B2 of the scan signal line Scan.
  • the display substrate may include: two gate driving circuits, the two gate driving circuits are located on the third side and the fourth side of the display area, respectively.
  • the structures of the two gate driving circuits are the same, and the plurality of shift registers in the two gate driving circuits are in one-to-one correspondence.
  • Corresponding shift registers in the two gate driving circuits are connected to the same scanning signal line and the same reset signal line, and are set to provide signals to the scanning signal line and the reset signal line at different stages, which can prolong the service life of the display substrate.
  • the peripheral circuit board is electrically connected to the gate driving circuit through a flexible signal line, and is configured to provide a signal to the gate driving circuit, wherein the signal includes a clock signal.
  • the display substrate further includes: gate signal traces 501 .
  • the gate signal wiring 501 is electrically connected to the flexible signal line and the gate driving circuit respectively.
  • the display substrate further includes: a flexible binding board.
  • the flexible binding board may be a chip-on-film.
  • the source driver chip may be located on the flexible bonding board.
  • the flexible binding board can provide signals to the multi-channel control wiring, the first power wiring, the second power wiring and the gate signal wiring, wherein the multi-channel control wiring is connected to the source driver chip Control traces for the multiplexer.
  • part of the peripheral wirings may be arranged on the flexible circuit board, and part of the peripheral wirings may be arranged on the flexible binding board.
  • the flexible circuit board can be connected with the first power trace and the second power trace, and the flexible binding board can provide signals to the multiple control traces and gate signal traces, or the flexible circuit board can be connected with the second power trace.
  • the power trace and the gate signal trace provide signals, and the flexible binding board can provide signals to the first power trace and the multiple control traces.
  • the source driver chip may be located on a glass substrate, and the flexible circuit board may be electrically connected with the multiple control traces, the first power traces, the second power traces and the gate signal traces.
  • the data signal lines include: a first data line Data1, a second data line Data2 and a third data line Data3; the first data line Data1 It is electrically connected to the first drive circuit 100A, the second data line Data2 is electrically connected to the second drive circuit 100B, and the third data line Data3 is electrically connected to the third drive circuit 100B; the reference signal line Vref is connected to the first drive circuit 100A, The second driving circuit 100B and the third driving circuit 100C are electrically connected.
  • the first data line Data1 and the second data line Data2 are located between the first driving circuit 100A and the second driving circuit 100B, and the second data line Data2 is located on the side of the first data line Data1 close to the second driving circuit 100B; the third data line The line Data3 and the reference signal line Vref are located between the second driving circuit 100B and the third driving circuit 100C, and the third data line Data3 is located on the side of the reference signal line Vref close to the third driving circuit 100C; or, the first data line Data1 and the reference The signal line Vref is located between the first driving circuit 100A and the second driving circuit 100B, the first data line Data1 is located on the side of the reference signal line Vref close to the second driving circuit 100B; the second data line Data2 and the third data line Data3 are located in Between the second driving circuit 100B and the third driving circuit 100C, the third data line Data3 is located on the side 100C of the second data line Data2 close to the third driving circuit.
  • FIG. 4 illustrates an example where the first data line
  • the data line and the first power line may be located on both sides of the driving circuit, or the data line and the first power line may be located between the two driving circuits.
  • FIG. 4 is an example in which the data line and the first power line may be located on both sides of the driving circuit.
  • the first driving circuit 100A and the third driving circuit 100C are mirror-symmetrical with respect to the center line C of the first and third data lines.
  • the first driving circuit and the second driving circuit when the first data line Data1 and the second data line Data2 are located between the first driving circuit 100A and the second driving circuit 100B, the first driving circuit and the second driving circuit The centerlines of the data line and the second data line are mirror-symmetrical.
  • the first driving circuit and the second driving circuit are mirror-symmetrical with respect to the center line of the first data line and the reference signal line .
  • the display substrate includes: a first driving structure, a second driving structure and a third driving structure which are arranged along the second direction and are adjacently arranged.
  • the third driving circuit in the first driving structure and the first driving circuit in the second driving structure are mirror-symmetrical with respect to the first power supply line located between the first driving structure and the second driving structure;
  • the three driving circuits and the first driving circuit in the third driving structure are mirror-symmetrical with respect to the first power supply line located between the second driving structure and the third driving structure.
  • the display substrate further includes: a light emitting structure layer on a side of the driving structure layer away from the substrate.
  • the light-emitting structure layer includes: a plurality of light-emitting elements.
  • Each driving circuit in the driving structure layer includes: a pixel driving circuit configured to drive the light-emitting element to emit light, and the pixel driving circuit is electrically connected with the light-emitting element.
  • the light emitting element may be an organic light emitting diode.
  • the control electrode of the first transistor T1 is electrically connected to the scan signal line Scan, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the second transistor T1 is electrically connected to the first node N1; The control electrode of T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first power supply line VDD, the second electrode of the second transistor T2 is electrically connected to the second node N2; The control electrode is electrically connected to the reset signal line Reset, the first electrode of the third transistor T3 is electrically connected to the reference signal line Vref, the second electrode of the third transistor T3 is electrically connected to the second node N2, and the first electrode of the storage capacitor C ST is electrically connected
  • the plate 41 is electrically connected to the second node N2, the second pole plate 42 of the storage capacitor C ST is electrically connected to the first node N1; the first pole of
  • the line width of the second power supply line VSS is equal to the line width of the data signal line Data, which can simplify the manufacturing process.
  • the transistors T1 to T3 can all be N-type thin film transistors or P-type thin film transistors, which can unify the process flow, reduce the process process, and help improve the yield of the display substrate.
  • FIG. 8 is an operation timing diagram of the pixel driving circuit provided by an exemplary embodiment.
  • a working process of a pixel driving circuit provided by an exemplary embodiment includes:
  • the first power line VDD continues to provide a high-level signal
  • the second power line VSS and the reference signal line Vref continue to provide a low-level signal.
  • the first stage S1 that is, the reset stage, the input signal of the scan signal line Scan is a high-level signal
  • the input signal of the reset signal line Reset is a high-level signal
  • the input signal of the data signal line Data is a low-level signal
  • the first A transistor T1 is turned on, the low-level signal of the data signal line Data is written into the first node N1
  • the third transistor T3 is turned on, and the low-level signal of the reference signal line Vref is written into the second node N2, because the second node N2
  • the voltage is the same as the voltage of the second power supply line VSS, and the light-emitting element OLED does not emit light.
  • the second transistor T2 Since the difference between the voltage of the signal of the first node N1 and the voltage of the second node N2 is greater than the threshold voltage of the second transistor T2, the second transistor T2 is turned on, and the voltage of the second node N2 gradually rises until the voltage of the second node N2 It is equal to the difference between the voltage of the signal of the first node N1 and the threshold voltage of the second transistor T2. As the voltage of the second node N2 gradually rises, the greater the mobility of the second transistor T2, the more the voltage of the second node N2 rises, the lower the threshold voltage of the second transistor T2, the higher the voltage of the second node N2 rises. smaller. After the compensation stage, the current difference caused by the different mobility and threshold voltage of the second transistor T2 in different pixel driving circuits can be reduced, the display uniformity of the display substrate can be compensated, and the display effect of the display substrate can be improved.
  • the input signal of the scan signal line Scan is a low-level signal
  • the input signal of the reset signal line Reset is a low-level signal
  • the input signal of the data signal line Data is a low-level signal.
  • the transistor T1 is turned off, the second transistor T2 is turned on, and a driving circuit is provided to the light-emitting element OLED, and the light-emitting element OLED emits light.
  • the input signal of the data signal line Data changes from a low level to a high level within one frame, so that the frequency of the input signal of the data signal line Data is higher.
  • FIG. 9 is a schematic layout diagram of a driving structure provided by an exemplary embodiment.
  • the first transistor T1 includes: a first active layer 11 , a first gate electrode 12 , a first source electrode 13 and a first drain electrode 14
  • the second transistor T2 includes a second active layer 21, a second gate electrode 22, a second source electrode 23 and a second drain electrode 24, and the third transistor T3 includes a third active layer 31, a third gate electrode 32, a third Three source electrodes 33 and third drain electrodes 34 .
  • the storage capacitor includes a first electrode plate 41 and a second electrode plate 42 .
  • FIG. 9 illustrates the source electrode of the first pole and the drain electrode of the second pole as an example.
  • the driving structure layer further includes: a first reference connection line 51 and a second reference connection line 61 extending along the second direction.
  • the first reference connection line 51 and the second reference connection line 61 are disposed in different layers, and the second reference connection line 61 is electrically connected to the reference signal line Vref and the first reference connection line 51 respectively.
  • each driving structure includes two first reference connection lines arranged along the first direction and three second reference connection lines arranged along the first direction .
  • the orthographic projection of the first first reference connecting line on the substrate and the orthographic projection of the first data line and the second data line on the substrate have an overlapping area; the orthographic projection of the second first reference connecting line on the substrate and the The orthographic projections of the three data lines and the reference signal lines on the substrate have overlapping regions.
  • the first first reference connection line is electrically connected with the first second reference connection line and the second second reference connection line respectively; the second first reference connection line is respectively connected with the second second reference connection line and the second reference connection line
  • the three second reference connection lines are electrically connected; the second second reference connection line is connected with the reference signal line, and is a continuous integral structure.
  • the scan signal line Scan is electrically connected to the first gate electrode 12 of the first transistor T1 in each driving structure
  • the reset signal line Reset is electrically connected to the third gate electrode 12 of the third transistor T3 in each driving structure
  • the gate electrode 32 is electrically connected
  • the data signal line Data is electrically connected to the first source electrode 13 of the first transistor T1 in each driving structure
  • the first reference connection line 51 and the second reference connection line 61 are set to make the third transistor T3
  • the third source electrode 33 is electrically connected to the reference signal line Vref.
  • the first gate electrode 12 of the first transistor T1 is electrically connected to the scan signal line Scan
  • the first source electrode 13 of the first transistor T1 is electrically connected to the data signal line Data
  • the first gate electrode 12 of the first transistor T1 is electrically connected to the scan signal line Scan.
  • the first drain electrode 14 of a transistor T1 is electrically connected to the second gate electrode 22 of the second transistor T2.
  • the second gate electrode 22 of the second transistor T2 is electrically connected to the first drain electrode 14 of the first transistor T1
  • the second source electrode 23 of the second transistor T2 is electrically connected to the third drain electrode 34 of the third transistor T3 and the first drain electrode 34 of the light-emitting element One pole is electrically connected
  • the second drain electrode 24 of the second transistor T2 is electrically connected to the first power supply line VDD
  • the third gate electrode 32 of the third transistor T3 is electrically connected to the reset signal line Reset
  • the third source of the third transistor T3 The electrode 33 is electrically connected to the reference signal line Vref through the first reference connection line 51 and the second reference connection line 61.
  • the third drain electrode 34 of the third transistor T3 is connected to the second source electrode 23 of the second transistor T2 and the first electrode of the light-emitting element. One pole is electrically connected.
  • the first plate 41 is electrically connected to the second source electrode 23 of the second transistor T2 and the third drain electrode 34 of the third transistor T3, and the second plate 42 is electrically connected to the first drain electrode 14 of the first transistor T1 and the second transistor T1
  • the second gate electrode 22 of T2 is electrically connected.
  • the driving structure layer includes: a first insulating layer, an active layer, a second insulating layer, a first metal layer, a third insulating layer, and a second metal layer that are sequentially arranged along a direction perpendicular to the substrate .
  • the active layer includes: the active layers of all transistors.
  • the active layers of each transistor are arranged in the same layer and formed through the same patterning process.
  • the first metal layer includes: a first reference connection line, control electrodes of all transistors, a first electrode plate, a reset signal line, a scan signal line and a first power supply connection line.
  • the first reference connection line, the control electrodes of all transistors, the first electrode plate, the reset signal line, the scan signal line and the first power supply connection line are arranged in the same layer and formed by the same patterning process.
  • the second metal layer includes: a second reference connection line, a reference signal line, a data line, a second electrode plate, and the first and second electrodes of all transistors.
  • the second reference connection line, the reference signal line, the data line, the second electrode plate, and the first electrodes and the second electrodes of all transistors are arranged in the same layer and formed through the same patterning process.
  • the transistors in the pixel driving circuit shown in the figure are all explained by taking N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (turn-on level), and is turned off when it is connected to a low level. (cutoff level).
  • the first electrode of the transistor may be the source electrode
  • the second electrode of the transistor may be the drain electrode.
  • the pixel driving circuit includes, but is not limited to, the configuration in FIG. 7 .
  • each transistor in the pixel driving circuit can also use N-type transistors or a mixture of P-type transistors and N-type transistors.
  • the port polarity may be connected according to the port polarity of the corresponding transistor in the embodiment of the present disclosure.
  • the transistors used in the pixel driving circuit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the active layer (channel region) of the transistor is made of semiconductor materials.
  • polysilicon such as low temperature polysilicon or high temperature polysilicon
  • amorphous silicon indium gallium tin oxide (IGZO), etc.
  • the gate, source, and drain are made of metal materials, such as metal aluminum or aluminum alloy.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • the electrodes of the capacitor may be metal electrodes or one of the electrodes may be semiconductor materials (eg, doped polysilicon).
  • the first transistor T1 in all the driving circuits in each driving structure is located on the side of the second electrode plate 42 close to the first power supply connection line VL, and the third transistor T3 is located on the second electrode plate 42 is away from the side of the first power connection line VL.
  • the first transistor in the first driving circuit and the first transistor in the third driving circuit are relative to the center line of the two first power supply lines on both sides of the driving structure Mirror symmetry, the second transistor in the first drive circuit and the second transistor in the third drive circuit are mirror-symmetrical with respect to the center line of the two first power lines on both sides of the drive structure, and the third transistor in the first drive circuit and The third transistor in the third driving circuit is mirror-symmetrical with respect to the center line of the two first power lines on both sides of the driving structure.
  • the first transistor in the first driving circuit and the transistor in the second driving circuit when the first data line and the second data line are disposed between the first driving circuit and the second driving circuit, the first transistor in the first driving circuit and the transistor in the second driving circuit
  • the first transistor is mirror-symmetrical with respect to the center line of the first data line and the second data line
  • the second transistor in the first driving circuit and the second transistor in the second driving circuit are relative to the first data line and the second data line.
  • the center line is mirror-symmetrical
  • the third transistor in the first driving circuit and the third transistor in the second driving circuit are mirror-symmetrical with respect to the center line of the first data line and the second data line.
  • the first transistor in the first driving circuit and the first transistor in the second driving circuit are relative to the first data line and the The center line of the reference signal line is mirror-symmetrical
  • the second transistor in the first drive circuit and the second transistor in the second drive circuit are mirror-symmetrical with respect to the center line of the first data line and the reference signal line
  • the third transistor in the first drive circuit is mirror-symmetrical.
  • the transistor and the third transistor in the second driving circuit are mirror-symmetrical with respect to the center line of the first data line and the reference signal line.
  • the driving structure layer further includes: a flat layer on a side of the second metal layer away from the substrate, a via hole is provided on the flat layer, and the via hole in the flat layer exposes the second source electrode of the second transistor T2 .
  • the light emitting structure layer includes: a first electrode, an organic light emitting layer, and a second electrode.
  • the first electrode is located on the side of the organic light-emitting layer close to the substrate, and the second electrode is located on the side of the organic light-emitting layer away from the substrate.
  • the first electrode is electrically connected to the second source electrode of the second transistor T2 through the flat layer via hole.
  • the third insulating layer is provided with a first via hole exposing the first power supply connection line VL and a second via hole exposing the first reference connection line 51 .
  • the first power supply line VDD is electrically connected to the first power supply connection line VL through the first via hole; the second reference connection line 61 is electrically connected to the first reference connection line 51 through the second via hole.
  • the second power supply line VSS and the scan signal line Scan are disposed on the same layer.
  • a connection via hole exposing the second power line is provided on the third insulating layer, and the reference trace is electrically connected to the second power line through the connection via hole.
  • the orthographic projection of the second electrode on the substrate and the orthographic projection of the second power line on the substrate have an overlapping area, and the second electrode is electrically connected to the second power line.
  • the shape of the display area may be an axisymmetric shape, or may be a non-axisymmetric shape.
  • the axis of symmetry may extend in the first direction or in the second direction.
  • the shape of the display area may be a circle, an ellipse, a fan, a heart, a triangle or an N-gon, and N is greater than 4.
  • the structure of the display substrate provided by an exemplary embodiment is described below through the preparation process of the display substrate.
  • the "patterning process” includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping processes.
  • Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can use any one or more of spray coating and spin coating
  • etching can use any one or more of dry etching and wet etching. one or more.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process. If the "film” does not require a patterning process during the entire fabrication process, the "film” may also be referred to as a "layer".
  • the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • each driving structure 10 to 12 are schematic diagrams of a manufacturing process of a display substrate provided by an exemplary embodiment, and illustrate a layout structure of one driving structure of the display substrate, and each driving structure includes: three driving circuits.
  • the pixel driving circuit in each driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor.
  • (1) forming an active layer on a substrate comprising: depositing a first insulating film on the substrate, patterning the first insulating film through a patterning process to form a first insulating layer, depositing a semiconductor film on the first insulating layer, and patterning the first insulating film The process patterns the semiconductor thin film to form an active layer in the display area.
  • the active layer includes a first active layer 11 , a second active layer 21 and a third active layer 31 , as shown in FIG. 10 .
  • the first active layer 11 serves as the active layer of the first transistor
  • the second active layer 21 serves as the active layer of the second transistor
  • the third active layer 31 serves as the active layer of the third transistor.
  • the orthographic projections of the first active layer 11, the second active layer 21 and the third active layer 31 on the substrate are spaced apart from the orthographic projections of the first electrode plate 41 on the substrate, That is, there is no overlapping area between the first active layer 11 and the first electrode plate 41 , between the second active layer 21 and the first electrode plate 41 , and between the third active layer 31 and the first electrode plate 41 , It is beneficial to design the channel width to length ratio of the first transistor, the second transistor and the third transistor according to relevant requirements.
  • the orthographic projections of the first active layer 11, the second active layer 21 and the third active layer 31 on the substrate are spaced apart from the orthographic projections of the second electrode plate 42 on the substrate, That is, there is no overlapping area between the first active layer 11 and the second electrode plate 42 , between the second active layer 21 and the second electrode plate 42 , and between the third active layer 31 and the second electrode plate 42 , It is beneficial to design the channel width to length ratio of the first transistor, the second transistor and the third transistor according to relevant requirements.
  • Forming the second metal layer includes: depositing a second insulating film on the substrate on which the active layer is formed, and patterning the second insulating film through a patterning process to form a second insulating layer in the display area.
  • a first metal film is deposited on the second insulating layer, and the first metal film is patterned through a patterning process to form a first metal layer.
  • the first metal layer includes: a reset signal line Reset, a scan signal line Scan, a first power supply connection line VL, a first reference connection line 51, and a first gate electrode 12, a second gate electrode 22, a first gate electrode 12, a second gate electrode 22, a The triple grid electrode 32 and the first electrode plate 41 are shown in FIG. 11 .
  • the reset signal line Reset, the scan signal line Scan, the first power supply connection line VL and the first reference connection line 51 are arranged in parallel and all extend in the first direction.
  • the reset signal line Reset and the scan signal line Scan are located on both sides of the first pole plate 41 respectively, the first power supply connection line VL is located on the side of the scan signal line Scan away from the first pole plate 41, and the first reference connection line 51 is located on the reset signal line 51.
  • the line Reset is away from the side of the first electrode plate 41 .
  • the first gate electrode 12 is an integral structure connected to the scan signal line Scan, and is disposed across the first active layer 11 .
  • the second gate electrode 22 is disposed across the second active layer 21 .
  • the third gate electrode 32 is an integral structure connected to the reset signal line Reset, and is provided across the third active layer 31 .
  • this process further includes a conductorization process.
  • the conductorization treatment is that after the first metal layer is formed, the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 are used as shielding to perform plasma treatment on the active layer, and the first gate electrode 12, the second gate electrode 12, the second gate electrode
  • the active layer in the shielding region of the gate electrode 22 and the third gate electrode 32 (ie, the region where the active layer overlaps with the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32) serves as the channel region of the transistor, and is not
  • the active layer in the region shielded by the first metal layer is processed into a conductive layer to form conductive source and drain regions.
  • a third insulating layer is formed.
  • the forming of the third insulating layer includes: depositing a third insulating film on the substrate on which the first metal layer is formed, and patterning the third insulating film through a patterning process to form the third insulating layer.
  • a plurality of via holes are opened on the third insulating layer, and the plurality of via holes include: a first via hole H1 located at the position of the first power supply connection line VL, and a second via hole H2 located at the position of the first reference connection line, located at the position of the first reference connection line.
  • the third via hole H3 and the fourth via hole H4 on both sides of the first gate electrode 12 , the fifth via hole H5 and the fifth via hole H6 on both sides of the second gate electrode 22 , and the The seventh via hole H7 and the eighth via hole H8 located on the side of the third gate electrode 32 are located in the ninth via hole H9 where the first electrode plate 41 is located, as shown in FIG. 12 .
  • the first via hole H1 exposes the surface of the first power connection line VL
  • the second via hole H2 exposes the surface of the first reference connection line 51
  • the third via hole H3 and the fourth via hole H2 expose the surface of the first reference connection line 51
  • the holes H4 expose the surfaces of both ends of the first active layer 11
  • the fifth via hole H5 and the sixth via hole H6 expose the surfaces of both ends of the second active layer 21
  • the seventh via hole H7 exposes the surface of the second gate electrode 22
  • the eighth via hole H8 exposes the third active layer 31
  • the ninth via hole H9 exposes the surface of the first electrode plate 41 .
  • the second metal layer includes: a first power supply line VDD, three data lines Data, a reference signal line Vref, a second reference connection line 61, and a first source electrode 13, a first drain electrode 14, a first source electrode 13, a first drain electrode 14, a second reference connection line 61 formed in each driving structure Two source electrodes 23 , second drain electrodes 24 , third source electrodes 33 , third drain electrodes 34 and second electrode plates 42 . As shown in Figure 4.
  • the first power supply line VDD, the data line Data and the reference signal line Vref are arranged in parallel and extend in the second direction. Two data lines are arranged between the first driving structure and the second driving structure, and another data line and a reference signal line are arranged between the second driving structure and the third driving structure.
  • the first power supply line VDD is electrically connected to the first power supply connection line VL through the first via hole H1.
  • the second reference connection line 61 is electrically connected to the first reference connection line 51 through the second via hole H2.
  • the first source electrode 13 is an integral structure connected to the data signal line Data, so that each data signal line Data is electrically connected to the first source electrode 13 of the driving structure where it is located, and the first source electrode 13 is electrically connected to one end of the first active layer 11 through the third via hole H3, the first drain electrode 14 is electrically connected to the other end of the first active layer 11 through the fourth via hole H4, and the first drain electrode 14 is also electrically connected to the first active layer 11 through the fourth via hole H4.
  • the seventh via hole H7 is electrically connected to the second gate electrode 22 and the second electrode plate 42 at the same time, so that the first drain electrode 14 , the second gate electrode 22 and the second electrode plate 42 have the same potential.
  • the second source electrode 23 is electrically connected to one end of the second active layer 21 and the first electrode plate 41 through the fifth via hole H5 and the ninth via hole H9 at the same time, thereby realizing the second source
  • the electrode 23, the third drain electrode 34 and the first electrode plate 41 have the same potential.
  • the second drain electrode 24 is electrically connected to the other end of the second active layer 21 through the sixth via hole H6.
  • the third source electrode 33 is electrically connected to one end of the third active layer 31 through the eighth via hole H8, and is also electrically connected to the reference signal line Vref through the second via hole H2, thereby realizing the first Three source electrodes 33 are electrically connected to the reference signal line Vref.
  • the second source electrode 23 , the third drain electrode 34 and the first electrode plate 41 are an integral structure connected to each other.
  • forming the fourth insulating layer and the flattening layer comprising: on the substrate formed with the second metal layer, firstly depositing a fourth insulating film, then coating the flattening film, masking the flattening film, exposing and developing, to The fourth insulating film is etched to form a fourth insulating layer, and a flat layer disposed on the fourth insulating layer and located in the display area and the transparent area, the fourth insulating layer and the flat layer are provided with a plurality of via holes, a plurality of The via hole includes: a via hole in each driving structure where the source electrode of the second transistor T2 is located. The via hole exposes the surface of the source electrode of the second transistor T2.
  • (6) forming a transparent conductive layer comprising: depositing a transparent conductive film on a substrate formed with a flat layer, patterning the transparent conductive film through a patterning process, and forming a transparent conductive layer on the flat layer, the transparent conductive layer comprising a first electrode , a first electrode is formed in each light-emitting element in the display area, and the first electrode is electrically connected to the source electrode of the second transistor T2 through a flat layer via hole.
  • a pixel definition layer including: coating a pixel definition film on a substrate forming a transparent conductive layer, forming a pixel definition layer (Pixel Define Layer) through a mask, exposure and development process, and the pixel definition layer is formed in the display area.
  • the pixel definition layer in each light emitting element is formed with an opening region exposing the anode.
  • Forming the organic light-emitting layer includes: forming an organic light-emitting layer in the opening area of the formed pixel definition layer and on the pixel definition layer, and the organic light-emitting layer is electrically connected to the first electrode.
  • Forming the second electrode includes: coating a cathode film on the substrate on which the organic light-emitting layer is formed, and patterning the conductive film through a patterning process to form the second electrode.
  • the cathode is formed in the display area and covers the organic light-emitting layer in each light-emitting element. In the display area, the second electrode is electrically connected to the organic light emitting layer.
  • the encapsulation layer (10) forming an encapsulation layer, forming an encapsulation layer on the substrate forming the second electrode, the encapsulation layer comprising a first encapsulation layer of an inorganic material, a second encapsulation layer of an organic material and a third encapsulation layer of an inorganic material, the first encapsulation layer It is arranged on the second electrode, the second encapsulation layer is arranged on the first encapsulation layer, and the third encapsulation layer is arranged on the second encapsulation layer to form a stacked structure of inorganic material/organic material/inorganic material.
  • the first metal layer and the second metal layer may use a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • Various, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). , which can be single layer, multi-layer or composite layer.
  • the first insulating layer is called a buffer layer, which is set to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called a gate insulating layer
  • the third insulating layer is called an interlayer insulating layer
  • the fourth insulating layer is called a passivation layer.
  • the thickness of the second insulating layer may be smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer may be smaller than the sum of the thicknesses of the second insulating layer and the third insulating layer, so as to ensure the insulating effect.
  • the capacity of the storage capacitor can be increased.
  • the flat layer may be an organic material
  • the transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel definition layer may employ polyimide, acrylic, or polyethylene terephthalate.
  • the second electrode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or may Alloys made with any one or more of the above metals.
  • the first insulating layer has a thickness of 3000 angstroms to 5000 angstroms
  • the second insulating layer has a thickness of 1000 angstroms to 2000 angstroms
  • the third insulating layer has a thickness of 4500 angstroms to 7000 angstroms
  • the fourth insulating layer has a thickness of 4500 angstroms to 7000 angstroms.
  • the thickness of the insulating layer is 3000 angstroms to 5000 angstroms.
  • the thickness of the first metal layer is 80 angstroms to 1200 angstroms
  • the thickness of the second metal layer is 3000 angstroms to 5000 angstroms
  • the thickness of the third metal layer is 3000 angstroms to 9000 angstroms.
  • the active layer may be a metal oxide layer.
  • the metal oxide layer may employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin, Oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium or gallium and zinc, and the like.
  • the metal oxide layer may be a single layer, or it may be a double layer, or it may be multiple layers.
  • the pixel driving circuit may be 5T1C or 7T1C.
  • other electrodes or leads may also be arranged in the film layer structure.
  • Embodiments of the present disclosure also provide a display device, including: a display substrate.
  • the display device may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or may be any product or component with a display function.
  • the display substrate provided in this embodiment is the display substrate provided by any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and details are not described herein again.

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Abstract

一种显示基板和显示装置，显示基板包括：显示区域(AA)和非显示区域(BB)，显示基板包括：基底以及设置在基底上的驱动结构层和走线层；驱动结构层位于显示区域(AA)，走线层位于非显示区域(BB)；驱动结构层包括：沿第一方向延伸的第一电源线(VDD)、数据信号线(Data)和参考信号线(Vref)；走线层包括：第一电源走线(301)、数据走线(201)和参考走线(202)；第一电源走线(301)与第一电源线(VDD)电连接，第一电源走线(301)位于显示区域(AA)的第一侧，数据走线(201)位于显示区域(AA)的第二侧，第二侧与第一侧不同；数据走线(201)和参考走线(202)位于显示区域(AA)的同一侧；对于同一长度的第一电源线(VDD)，数据信号线(Data)和参考信号线(Vref)，第一电源线(VDD)的电阻大于数据信号线(Data)的电阻，且大于参考信号线(Vref)的电阻。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示领域，特别涉及一种显示基板和显示装置。
背景技术
随着显示器技术的飞速发展，显示器除了传统的信息展示等作用外，为了更好的适应环境的整体结构和使用要求，在外形上的要求也在逐步提升，随之产生了异形显示器。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：显示区域和非显示区域，所述显示基板包括：基底以及设置在所述基底上的驱动结构层和走线层；所述驱动结构层位于所述显示区域，所述走线层位于所述非显示区域；所述驱动结构层包括：沿第一方向延伸的第一电源线、数据信号线和参考信号线；所述走线层包括：第一电源走线、数据走线和参考走线；
所述第一电源走线与所述第一电源线电连接，所述数据走线与所述数据信号线电连接，所述参考走线与所述参考信号线电连接；
所述第一电源走线位于所述显示区域的第一侧，所述数据走线位于所述显示区域的第二侧，所述第二侧与所述第一侧不同；所述数据走线和所述参考走线位于所述显示区域的同一侧；
对于同一长度的所述第一电源线，所述数据信号线和所述参考信号线，所述第一电源线的电阻大于所述数据信号线的电阻，且大于所述参考信号线的电阻。
在一些可能的实现方式中，所述第一电源线线宽大于所述数据信号线线宽，且大于所述参考信号线线宽。
在一些可能的实现方式中，所述显示基板还包括：位于所述非显示区域的第二电源线和第二电源走线；
所述第二电源线与所述第二电源走线电连接，所述第二电源线沿第二方向延伸，所述第二方向和所述第一方向相交；所述第二电源线与所述第二电源走线位于所述显示区域的同一侧，所述第二电源走线与所述数据走线位于所述显示区域的同一侧。
在一些可能的实现方式中，所述第二电源线与所述参考走线异层设置，所述第二电源线在所述基底上的正投影与所述参考走线在所述基底上的正投影存在重叠区域；
所述第二电源线与所述参考走线电连接。
在一些可能的实现方式中，所述显示基板还包括：柔性电路板以及位于所述非显示区域的源极驱动芯片和至少一个焊盘；所述焊盘与所述第一电源走线位于所述显示区域的同一侧，所述源极驱动芯片与所述数据走线位于所述显示区域的同一侧；所述源极驱动芯片位于所述第二电源线远离所述显示区域的一侧；
所述源极驱动芯片与所述数据走线电连接，设置为通过数据走线向所述数据信号线提供数据信号；
所述柔性电路板，分别与焊盘和第二电源走线电连接，设置为通过所述焊盘向所述第一电源走线供电，并向所述第二电源走线供电。
在一些可能的实现方式中，所述显示基板还包括：外围电路板、柔性信号线以及位于所述非显示区域的源极驱动芯片和至少一个焊盘；所述焊盘与所述第一电源走线位于所述显示区域的同一侧，所述源极驱动芯片与所述数据走线位于所述显示区域的同一侧；所述源极驱动芯片位于所述第二电源线远离所述显示区域的一侧；
所述源极驱动芯片与所述数据走线电连接，设置为通过所述数据走线向所述数据信号线提供数据信号；
所述外围电路板，通过所述柔性信号线分别与所述焊盘、所述第二电源走线和所述源极驱动芯片电连接，设置为通过焊盘向所述第一电源走线供电， 向所述第二电源走线供电，并向所述源极驱动芯片提供信号。
在一些可能的实现方式中，所述驱动结构层还包括：位于所述显示区域，且沿所述第二方向延伸的多个第一电源连接线；所述第一电源连接线与所述第一电源线异层设置；
至少一个第一电源连接线在基底上的正投影与所述第一电源线在基底上的正投影存在重叠区域；所述至少一个第一电源连接线的每一个与所述第一电源线电连接。
在一些可能的实现方式中，所述驱动结构层还包括：沿所述第二方向延伸的多个扫描信号线和多个复位信号线以及矩阵排布的多个驱动结构，所述第一电源线设置在两个相邻的驱动结构之间；
其中，每个驱动结构包括：沿所述第二方向排布的第一驱动电路、第二驱动电路和第三驱动电路。
在一些可能的实现方式中，所述显示基板还包括：位于所述非显示区域的栅极驱动电路；所述栅极驱动电路位于所述显示区域的第三侧，所述第三侧为与所述第一侧和所述第二侧不同的一侧；
所述栅极驱动电路，分别与所述扫描信号线和所述复位信号线电连接，设置为向所述扫描信号线和所述复位信号线提供信号；
所述栅极驱动电路包括：多个移位寄存器，每个移位寄存器包括：第一移位寄存器和第二移位寄存器；第一移位寄存器，与所述扫描信号线电连接，设置为向扫描信号线提供信号，第二移位寄存器，与所述复位信号线电连接，设置为向复位信号线提供信号；多个第一移位寄存器级联，多个第二移位寄存器级联。
在一些可能的实现方式中，所述显示基板还包括：扫描走线和复位走线；所述扫描走线，分别与所述扫描信号线和栅极驱动电路电连接，所述复位走线，分别与所述复位信号线和所述栅极驱动电路电连接；
所述栅极驱动电路包括：多个移位寄存器组，每个移位寄存器组包括：至少一个移位寄存器；每个移位寄存器组中的所有移位寄存器沿第一方向排布；
多个移位寄存器组成阶梯状排布，相邻移位寄存器之间沿第二方向的间距大于所述扫描走线线长和所述复位走线线长之和。
在一些可能的实现方式中，在每个驱动结构中，所述数据信号线包括：第一数据线、第二数据线和第三数据线；所述第一数据线与所述第一驱动电路电连接，所述第二数据线与所述第二驱动电路电连接，所述第三数据线与所述第三驱动电路电连接；所述参考信号线，分别与所述第一驱动电路、所述第二驱动电路和所述第三驱动电路电连接；
所述第一数据线和所述第二数据线位于所述第一驱动电路和所述第二驱动电路之间，所述第二数据线位于所述第一数据线靠近所述第二驱动电路的一侧；所述第三数据线和所述参考信号线位于所述第二驱动电路和所述第三驱动电路之间，所述第三数据线位于所述参考信号线靠近所述第三驱动电路一侧；
或者，所述第一数据线和所述参考信号线位于所述第一驱动电路和所述第二驱动电路之间，所述第一数据线位于所述参考信号线靠近所述第二驱动电路的一侧；所述第二数据线和所述第三数据线位于所述第二驱动电路和所述第三驱动电路之间，所述第三数据线位于所述第二数据线靠近所述第三驱动电路一侧。
在一些可能的实现方式中，在每个驱动结构中，所述第一驱动电路与所述第三驱动电路相对于所述第一数据线和所述第三数据线的中线镜像对称。
所述显示基板包括：沿第二方向排布的、且相邻设置的第一驱动结构、第二驱动结构和第三驱动结构；
所述第一驱动结构中的第三驱动电路与所述第二驱动结构中的第一驱动电路相对于位于所述第一驱动结构和所述第二驱动结构之间的第一电源线镜像对称；
所述第二驱动结构中的第三驱动电路与所述第三驱动结构中的第一驱动电路相对于位于所述第二驱动结构和所述第三驱动结构之间的第一电源线镜像对称。
在一些可能的实现方式中，所述驱动结构层还包括：沿所述第二方向延 伸的第一参考连接线和第二参考连接线；
所述第一参考连接线和所述第二参考连接线异层设置；所述第二参考连接线分别与所述参考信号线和所述第一参考连接线电连接。
在一些可能的实现方式中，每个驱动结构中包括两个沿第二方向排布的第一参考连接线和三个沿第二方向排布的第二参考连接线；
第一个第一参考连接线分别与第一个第二参考连接线和第二个第二参考连接线电连接；
第二个第一参考连接线分别与第二个第二参考连接线和第三个第二参考连接线电连接；
其中一个第二参考连接线与所述参考信号线电连接，且为连续的一体结构。
在一些可能的实现方式中，所述显示基板还包括：位于所述驱动结构层远离所述基底一侧的发光结构层，所述发光结构层包括：多个发光元件；
所述驱动结构层中的每个驱动结构包括：设置为驱动所述发光元件发光的像素驱动电路；
所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；所述第二晶体管为驱动晶体管；所述存储电容包括：第一极板和第二极板；
所述第一晶体管的控制极与扫描信号线电连接，所述第一晶体管的第一极与数据信号线电连接，所述第一晶体管的第二极与第一节点电连接；所述第二晶体管的控制极与第一节点电连接，所述第二晶体管的第一极与第一电源线电连接，所述第二晶体管的第二极与第二节点电连接；所述第三晶体管的控制极与复位信号线电连接，所述第三晶体管的第一极与参考信号线电连接，所述第三晶体管的第二极与第二节点电连接，所述存储电容的第一极板与所述第二节点电连接，所述存储电容的第二极板与所述第一节点电连接；
所述发光元件的第一极与第二节点电连接，所述发光元件的第二极与第二电源线电连接。
在一些可能的实现方式中，所述驱动结构层包括：沿垂直于所述基底方 向依次设置的第一绝缘层、有源层、第二绝缘层、第一金属层、第三绝缘层和第二金属层；
所述有源层包括：所有晶体管的有源层；所述第一金属层包括：第一参考连接线、所有晶体管的控制极、第一极板、复位信号线、扫描信号线和第一电源连接线；所述第二金属层包括：第二参考连接线、参考信号线、数据线、第二极板以及所有晶体管的第一极和第二极。
在一些可能的实现方式中，所述第三绝缘层设置有暴露出所述第一电源电连接线的第一过孔和暴露出所述第一参考电连接线的第二过孔；
所述第一电源线通过所述第一过孔与所述第一电源电连接线电连接，所述第二参考连接线通过所述第二过孔与所述第一参考连接线电连接。
在一些可能的实现方式中，所述第二电源线与扫描信号线同层设置；
所述第三绝缘层上设置有暴露出所述第二电源线的连接过孔；
所述参考走线通过所述连接过孔与所述第二电源线电连接。
在一些可能的实现方式中，所述发光结构层包括：第一电极、有机发光层和第二电极；所述第一电极位于所述有机发光层靠近所述基底的一侧，所述第二电极位于所述有机发光层远离所述基底的一侧；
所述第二电极在所述基底上的正投影与所述第二电源线在所述基底上的正投影存在重叠区域，所述第二电极与所述第二电源线电连接。
在一些可能的实现方式中，数据走线线长与数据信号线线长呈负相关。
在一些可能的实现方式中，所述显示区域的形状为圆形、椭圆形、扇形、心形、三角形或N边形，N大于4。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方 案的限制。
图1为本公开实施例提供的显示基板的一个结构示意图；
图2为本公开实施例提供的显示基板的另一结构示意图；
图3为图1和图2的虚线部分的放大示意图；
图4为一种示例性实施例提供的显示基板的局部显示区域的示意图；
图5为一种示例性实施例中第一电源线和第一电源连接线的俯视图；
图6为一种示例性实施例提供的栅极驱动电路的示意图；
图7为一种示例性实施例提供的像素驱动电路的等效电路图；
图8为一种示例性实施例提供的像素驱动电路的工作时序图；
图9为一种示例性实施例提供的一个驱动结构的版图示意图；
图10至图12为一种示例性实施例提供的显示基板制备过程的示意图。
详述
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或 以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
异形显示器是在传统显示器的基础上改造成的特殊形状的显示器，以使显示器的特点能更好的适应建筑物的整体结构和环境。目前常见的异形屏主要有扇形、弧形、圆形、圆柱形、三角形等结构形式。
在异型屏中，由于每列电源线所供给的像素的数量有所不同，使得每列电源线的压降不同，导致了异形屏显示不均。
图1为本公开实施例提供的显示基板的一个结构示意图，图2为本公开实施例提供的显示基板的另一结构示意图，图3为图1和图2的虚线部分的放大示意图。如图1至3所示，本公开实施例提供的显示基板，包括：显示区域AA和非显示区域BB。显示基板包括：基底以及位于显示区域的，且设置在基底上的驱动结构层和走线层；驱动结构层位于显示区域AA，走线层位于非显示区域BB；驱动结构层包括：沿第一方向延伸的第一电源线VDD、数据信号线Data和参考信号线Vref；走线层包括：第一电源走线301、数据走线201和参考走线202。图1和图2中的显示基板的异形边界不同，图1的异形边界是心形，图2的异形边界为椭圆形。
在一种示例性实施例中，第一电源走线301与第一电源线VDD电连接，数据走线201与数据信号线Data电连接，参考走线202与参考信号线Vref连接。第一电源走线301位于显示区域的第一侧，数据走线201位于显示区域AA的第二侧，第一侧与第二侧不同，数据走线201和参考走线202位于显示区域的同一侧。
在一种示例性实施例中，第一侧和第二侧可以为相对设置的两侧，第二侧为远离第一侧的一侧。A和B相对设置指的是B位于远离A的一侧。
如图1和2所示，第一电源线VDD包括：相对设置的第一端A1和第二端A2。第一侧指的位于靠近第一电源线VDD的第一端A1的显示区域的一侧，第二侧指的是靠近第一电源线VDD的第二端A2的一侧。
对于同一长度的第一电源线VDD，数据信号线Data和参考信号线Vref，第一电源线VDD的电阻大于数据信号线Data的电阻，且大于参考信号线Vref的电阻。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，第一电源线VDD设置为持续提供高电平电源信号。
在一种示例性实施例中，显示区域AA具有异形边界。非显示区域BB包围显示区域AA。非显示区域BB的边界可以为异形边界，图1和2是以非显示区域BB的边界为异形边界为例进行说明。
在一种示例性实施例中，第一电源走线301的数量为多个，第一电源线VDD的数量为多个。多个第一电源走线301与多个第一电源线VDD一一对应。每个第一电源走线301与对应的第一电源线VDD连接。
在一种示例性实施例中，第一电源走线301与第一电源线VDD可以同层设置，或者可以异层设置。
在一种示例性实施例中，数据走线201的数量为多个，数据信号线Data的数量为多个。多个数据走线201与多个数据信号线Data一一对应。每个数据走线201与对应的数据信号线Data连接。
在一种示例性实施例中，数据走线201与数据信号线Data可以同层设置，或者可以异层设置。
在一种示例性实施例中，参考走线202的数量为多个，参考信号线Vref的数量为多个。多个参考走线202与多个参考信号线Vref一一对应。每个参考走线202与对应的参考信号线Vref连接。
在一种示例性实施例中，参考走线202与参考信号线Vref可以同层设置，或者可以异层设置。
在一种示例性实施例中，异形显示基板由于数据信号线连接的像素的数量不相等，从而使得数据信号线的负载存在差异，而负载差异会影响显示效果，因此，数据走线线长和与其连接的数据信号线线长呈负相关，数据信号 线线长越长，与其连接的数据走线线长越短。即利用数据走线线长差异来补偿数据信号线的负载差异。
本公开实施例提供的显示基板包括：显示区域和非显示区域，显示基板包括：基底以及设置在基底上的驱动结构层和走线层；驱动结构层位于显示区域，走线层位于非显示区域；驱动结构层包括：沿第一方向延伸的第一电源线、数据信号线和参考信号线；走线层包括：第一电源走线、数据走线和参考走线；第一电源走线与第一电源线电连接，数据走线与数据信号线电连接，参考走线与参考信号线电连接；第一电源走线位于显示区域的第一侧，数据走线位于显示区域的第二侧，第二侧与第一侧不同；数据走线和参考走线位于显示区域的同一侧；对于同一长度的第一电源线，数据信号线和参考信号线，第一电源线的电阻大于数据信号线的电阻，且大于参考信号线的电阻。本公开实施例提供的技术方案通过将第一电源走线和数据走线布局在显示区域烦人两侧，可以实现异型显示基板的窄边框。
在一种示例性实施例中，第一电源线VDD线宽大于数据信号线Data线宽，且大于参考信号线Vref线宽，可以降低第一电源线VDD的电阻。
在一种示例性实施例中，显示基板的尺寸越大，第一电源线VDD线宽就越大，例如55寸的显示基板中的第一电源线VDD线宽可以达到十几微米。
如图1至3所示，一种示例性实施例中，显示基板还包括：位于非显示区域BB的第二电源线VSS和第二电源走线401。
第二电源线VSS与第二电源走线401电连接，第二电源线VSS沿第二方向延伸。第二电源线VSS与第二电源走线401位于显示区域AA的同一侧，第二电源走线401与数据走线201位于显示区域AA的同一侧。
在一种示例性实施例中，第二方向与第一方向相交，第一方向与第二方向所在的平面为显示基板所在的平面。
在一种示例性实施例中，第一方向垂直于第二方向。
第二电源线VSS与参考走线202异层设置，第二电源线VSS在基底上的正投影与参考走线202在基底上的正投影存在重叠区域；第二电源线VSS与参考走线202电连接。
在一种示例性实施例中，第二电源线VSS通过参考走线202与参考信号线Vref电连接，不仅可以保证像素驱动电路在对发光元件的第一极进行初始化时，发光元件的第一极和第二极的信号相等，同时保证了显示基板的正常显示，提升了显示基板的显示效果，节省了信号走线。
在一种示例性实施例中，第二电源线VSS与第二电源走线401可以同层设置，或者可以异层设置。
在一种示例性实施例中，第二电源线VSS设置为持续提供低电平电源信号。
在一种示例性实施例中，第一电源线VDD的电源信号的电压值可以大于第二电源线VSS的电源信号的电压值。
如图1至3所示，一种示例性实施例提供的显示基板还可以包括：柔性电路板(图中未示出)以及位于非显示区域BB的源极驱动芯片20和至少一个焊盘30。
焊盘30与第一电源走线301位于显示区域AA的同一侧，源极驱动芯片20与数据走线201位于显示区域AA的同一侧；源极驱动芯片20位于第二电源线VSS远离显示区域AA的一侧。源极驱动芯片与数据走线201电连接，设置为通过数据走线201向数据信号线Data提供数据信号。
柔性电路板，分别与焊盘30和第二电源走线401电连接，设置为通过焊盘30向第一电源走线301供电，并向第二电源走线401供电。
在一种示例性实施例中，柔性电路板可以设置在显示基板的任意位置。
柔性电路板沿第一电源线远离源极驱动芯片的一侧向第一电源走线开始供电，沿第一电源线靠近源极驱动芯片的一侧向第二电源走线开始供电，可以使得第一电源线和第二电源线的压降之和大大减少，可以提高显示基板的显示效果。
如图1至3所示，在一种示例性实施例中，显示基板还可以包括：外围电路板、柔性信号线以及位于非显示区域的源极驱动芯片20和至少一个焊盘30。
焊盘30与第一电源走线301位于显示区域AA的同一侧，源极驱动芯片 20与数据走线201位于显示区域AA的同一侧；源极驱动芯片20位于第二电源线VSS远离显示区域AA的一侧。源极驱动芯片与数据走线201电连接，设置为通过数据走线201向数据信号线Data提供数据信号。
外围电路板，通过柔性信号线分别与焊盘、第二电源走线和源极驱动芯片电连接，设置为通过焊盘向第一电源走线供电，向第二电源走线供电，并向源极驱动芯片提供信号。
在一种示例性实施例中，柔性信号线的一端绑定在基底上，另一端绑定在外围电路板上，外围电路板通过柔性信号线向设置在基底上的第一电源走线、第二电源走线和源极驱动芯片供电。
在一种示例性实施例中，外围电路板和柔性信号线可以设置在显示基板的任意位置处。
外围电路板和柔性信号线沿第一电源线远离源极驱动芯片的一侧向第一电源走线开始供电，沿第一电源线靠近源极驱动芯片的一侧向第二电源走线开始供电，可以使得第一电源线和第二电源线的压降之和大大减少，可以提高显示基板的显示效果。
在一种示例性实施例中，焊盘30的尺寸根据工艺精度和膨胀量考虑，焊盘的宽度为100纳米至200纳米。
在一种示例性实施例中，焊盘的数量根据显示需求确定。图1是以两个焊盘为例进行说明，图2是以一个焊盘为例进行说明。
在一种示例性实施例中，源极驱动芯片的数量可以根据显示基板的尺寸来确定，显示基板的尺寸越大，源极驱动芯片的数量越多。图1和图2是以一个源极驱动芯片为例进行说明。
图4为一种示例性实施例提供的显示基板的局部显示区域的示意图，图5为一种示例性实施例中第一电源线和第一电源连接线的俯视图。如图4和5所示，一种示例性实施例提供的显示基板的驱动结构层还包括：位于显示区域AA，且沿第二方向延伸的多个第一电源连接线VL。
第一电源连接线VL与第一电源线VDD异层设置。至少一个第一电源连接线VL在基底上的正投影与第一电源线VDD在基底上的正投影存在重叠区 域。至少一个第一电源连接线VL的每一个与第一电源线VDD电连接。
至少一个第一电源连接线的每一个与第一电源线电连接，可以减弱显示基板中不同第一电源线的不同压降造成的显示基板的显示不均，提升显示基板的显示效果。
在一种示例性实施例中，第一电源线VDD的制作材料可以与第一电源连接线VL的制作材料相同，或者可以与第一电源连接线VL的制作材料不同。
在一种示例性实施例中，第一电源连接线VL可以设置在第一电源线VDD靠近基底的一侧。
如图4所示，一种示例性实施例提供的显示基板中的驱动结构层还包括：沿第二方向延伸的多个扫描信号线Scan和多个复位信号线Reset以及矩阵排布的多个驱动结构，第一电源线VDD设置在两个相邻的驱动结构之间。每个驱动结构包括：沿第二方向排布的第一驱动电路100A、第二驱动电路100B和第三驱动电路100C。
在一种示例性实施例中，驱动结构层可以包括M行N列驱动结构，M和N可以为大于1的正整数。图4是以驱动结构层三行三列驱动结构为例进行说明。
在一种示例性实施例中，复位信号线Reset和第一电源连接线VL设置为限定出一行驱动结构，相邻第一电源线设置为限定出一列驱动结构。
图6为一种示例性实施例提供的栅极驱动电路的示意图。如图1、图2和图6所示，一种示例性实施例提供的显示基板还包括：位于非显示区域的栅极驱动电路。栅极驱动电路位于显示区域的第三侧，第三侧为与第一侧和第二侧不同的一侧。
栅极驱动电路，分别与扫描信号线Scan和复位信号线Reset电连接，设置为向扫描信号线和复位信号线提供信号。
栅极驱动电路包括：多个移位寄存器50。多个移位寄存器沿着显示区域的边缘设置。每个移位寄存器50包括：第一移位寄存器GOA1和第二移位寄存器GOA2。第一移位寄存器GOA1，与扫描信号线Scan电连接，设置为 向扫描信号线Scan提供信号，第二移位寄存器GAO2，与复位信号线Reset电连接，设置为向复位信号线Reset提供信号。多个第一移位寄存器GOA1级联，多个第二移位寄存器GOA2级联。每个移位寄存器中的第一移位寄存器和第二移位寄存器沿第一方向排布。
如图6所示，在一种示例性实施例中，显示基板还包括：扫描走线SL和复位走线RL；扫描走线SL，分别与扫描信号线和栅极驱动电路电连接，复位走线RL，分别与复位信号线和栅极驱动电路电连接。
如图6所示，在一种示例性实施例中，栅极驱动电路包括：多个移位寄存器组。每个移位寄存器组包括：至少一个移位寄存器；每个移位寄存器组中的所有移位寄存器沿第一方向排布。图6是以一个移位寄存器组包括：四个移位寄存器为例进行说明。每个移位寄存器组包括的移位寄存器的数量与显示区域的边界相关。
如图6所示，多个移位寄存器组成阶梯状排布，相邻移位寄存器之间沿第二方向的间距L大于扫描走线线长和复位走线线长之和。相邻移位寄存器之间沿第二方向的间距越小，显示基板越容易实现窄边框。
在一种示例性实施例中，多个移位寄存器组环绕着显示区域的边缘设置，至少部分包围显示区域。
在一种示例性实施例中，移位寄存器的排布方式是根据异形边界来确定的。
在一种示例性实施例中，栅极驱动电路位于所述显示区域的第三侧。扫描信号线Scan包括：相对设置的第一端B1和第二端B2。第三侧可以为靠近扫描信号线Scan的第一端B1的一侧，或者靠近扫描信号线Scan的第二端B2的一侧。
在一种示例性实施例中，栅极驱动电路可以与焊盘位于显示基板的同一侧。图1和图2是以栅极驱动电路分别与焊盘和源极驱动芯片位于显示基板的不同侧。以图1提供的心形显示基板为例，栅极驱动电路可以设置在两个焊盘之间的非显示区域。
在一种示例性实施例中，显示基板可以包括：两个栅极驱动电路，两个 栅极驱动电路分别位于显示区域的第三侧和第四侧。两个栅极驱动电路的结构相同，两个栅极驱动电路中的多个移位寄存器一一对应。两个栅极驱动电路中对应的移位寄存器连接同一扫描信号线和同一复位信号线，设置为不同阶段向扫描信号线和复位信号线提供信号，可以延长显示基板的使用寿命。
在一种示例性实施例中，外围电路板通过柔性信号线与栅极驱动电路电连接，设置为向栅极驱动电路提供信号，其中，信号包括时钟信号。
如图1和2所示，在一种示例性实施例中，显示基板还包括：栅极信号走线501。栅极信号走线501，分别与柔性信号线和栅极驱动电路电连接。
在一种示例性实施例中，显示基板还包括：柔性绑定板。柔性绑定板可以为覆晶薄膜。
在一种示例性实施例中，源极驱动芯片可以位于柔性绑定板上。
在一种示例性实施例中，若显示基板的外围走线布局不复杂，所有外围布局可以设置在柔性绑定板上。此时，柔性绑定板可以向多路控制走线、第一电源走线、第二电源走线和栅极信号走线提供信号，其中，多路控制走线为与源极驱动芯片连接的多路选择器的控制走线。
在一种示例性实施例中，若显示基板的外围走线布局复杂时，可以将部分外围走线设置在柔性电路板上，将部分外围走线设置在柔性绑定板上。此时，柔性电路板可以与第一电源走线和第二电源走线连接，柔性绑定板可以向多路控制走线和栅极信号走线提供信号，或者，柔性电路板可以与第二电源走线和栅极信号走线提供信号，柔性绑定板可以向第一电源走线和多路控制走线提供信号。
在一种示例性实施例中，源极驱动芯片可以位于玻璃基板上，柔性电路板可以与多路控制走线、第一电源走线、第二电源走线和栅极信号走线电连接。
在一种示例性实施例中，如图4所示，在每个驱动结构中，数据信号线包括：第一数据线Data1、第二数据线Data2和第三数据线Data3；第一数据线Data1与第一驱动电路100A电连接，第二数据线Data2与第二驱动电路100B电连接，第三数据线Data3与第三驱动电路100B电连接；参考信号线 Vref，分别与第一驱动电路100A、第二驱动电路100B和第三驱动电路100C电连接。
第一数据线Data1和第二数据线Data2位于第一驱动电路100A和第二驱动电路100B之间，第二数据线Data2位于第一数据线Data1靠近第二驱动电路100B的一侧；第三数据线Data3和参考信号线Vref位于第二驱动电路100B和第三驱动电路100C之间，第三数据线Data3位于参考信号线Vref靠近第三驱动电路100C一侧；或者，第一数据线Data1和参考信号线Vref位于第一驱动电路100A和第二驱动电路100B之间，第一数据线Data1位于参考信号线Vref靠近第二驱动电路100B的一侧；第二数据线Data2和第三数据线Data3位于第二驱动电路100B和第三驱动电路100C之间，第三数据线Data3位于第二数据线Data2靠近第三驱动电路一侧100C。图4是以第一数据线Data1和第二数据线Data2位于第一驱动电路100A和第二驱动电路100B之间为例进行说明。
在一种示例性实施例中，数据线可以与第一电源线位于驱动电路的两侧，或者数据线可以与第一电源线位于两个驱动电路之间。图4是以数据线可以与第一电源线位于驱动电路的两侧为例进行说明。
在一种示例性实施例中，如图6所示，在每个驱动结构中，第一驱动电路100A与第三驱动电路100C相对于第一数据线和第三数据线的中线C镜像对称。
在一种示例性实施例中，当第一数据线Data1和第二数据线Data2位于第一驱动电路100A和第二驱动电路100B之间时，第一驱动电路与第二驱动电路相对于第一数据线和第二数据线的中线镜像对称设置。当第一数据线Data1和参考信号线Vref位于第一驱动电路100A和第二驱动电路100B之间时，第一驱动电路和第二驱动电路相对于第一数据线和参考信号线的中线镜像对称。
在一种示例性实施例中，如图6所示，显示基板包括：沿第二方向排布的、且相邻设置的第一驱动结构、第二驱动结构和第三驱动结构。
第一驱动结构中的第三驱动电路与第二驱动结构中的第一驱动电路相对于位于第一驱动结构和第二驱动结构之间的第一电源线镜像对称；第二驱动 结构中的第三驱动电路与第三驱动结构中的第一驱动电路相对于位于第二驱动结构和第三驱动结构之间的第一电源线镜像对称。
在一种示例性实施例中，显示基板还包括：位于驱动结构层远离基底一侧的发光结构层。发光结构层包括：多个发光元件。驱动结构层中的每个驱动电路包括：设置为驱动发光元件发光的像素驱动电路，像素驱动电路与发光元件电连接。
在一种示例性实施例中，发光元件可以为有机发光二极管。
图7为一种示例性实施例提供的像素驱动电路的等效电路图。如图7所示，像素驱动电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C ST。第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为复位晶体管；存储电容C ST包括：第一极板41和第二极板42。
第一晶体管T1的控制极与扫描信号线Scan电连接，第一晶体管T1的第一极与数据信号线Data电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一电源线VDD电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与复位信号线Reset电连接，第三晶体管T3的第一极与参考信号线Vref电连接，第三晶体管T3的第二极与第二节点N2电连接，存储电容C ST的第一极板41与第二节点N2电连接，存储电容C ST的第二极板42与第一节点N1电连接；发光元件OLED的第一极与第二节点N2电连接，发光元件的第二极与第二电源线VSS电连接。
在一种示例性实施例中，第二电源线VSS线宽等于数据信号线Data线宽，可以简化制作工艺。
在本实施例中，晶体管T1至T3均可以为N型薄膜晶体管或P型薄膜晶体管，可以统一工艺流程，减少工艺制程，有助于提高显示基板的良率。
以一种示例性实施例提供的像素驱动电路中的晶体管T1至T3均为N型薄膜晶体管为例，图8为一种示例性实施例提供的像素驱动电路的工作时序图。如图7和8所示，一种示例性实施例提供的像素驱动电路的工作过程包括：
第一电源线VDD持续提供高电平信号，第二电源线VSS和参考信号线Vref持续提供低电平信号。
第一阶段S1、即重置阶段，扫描信号线Scan的输入信号为高电平信号，复位信号线Reset的输入信号为高电平信号，数据信号线Data的输入信号为低电平信号，第一晶体管T1导通，数据信号线Data的低电平信号写入第一节点N1，第三晶体管T3导通，参考信号线Vref的低电平信号写入第二节点N2，由于第二节点N2的电压与第二电源线VSS的电压相同，发光元件OLED不发光。
第二阶段S2、即补偿阶段，扫描信号线Scan的输入信号为高电平信号，复位信号线Reset的输入信号为低电平信号，数据信号线Data的输入信号为低电平信号，第一晶体管T1导通，数据信号线Data的低电平信号写入第一节点N1，第三晶体管T3截止。由于第一节点N1的信号的电压与第二节点N2的电压差值大于第二晶体管T2的阈值电压，第二晶体管T2导通，第二节点N2的电压逐渐抬升，直至第二节点N2的电压等于第一节点N1的信号的电压与第二晶体管T2的阈值电压的差值。随着第二节点N2的电压逐渐抬升，第二晶体管T2的迁移率越大，第二节点N2的电压抬升的越多，第二晶体管T2的阈值电压越小，第二节点N2的电压抬升的越小。经过补偿阶段，能把不同像素驱动电路中由于第二晶体管T2的迁移率和阈值电压不同所造成的电流差异缩小，可以实现显示基板的显示均匀性的补偿，提高了显示基板的显示效果。
第三阶段S3、即写入阶段，扫描信号线Scan的输入信号为高电平信号，复位信号线Reset的输入信号为低电平信号，数据信号线Data的输入信号为高电平信号，第一晶体管T1导通，数据信号线Data的高电平信号写入第一节点N1，由于存储电容C ST的作用，第二节点N2的信号的电压值会发生相应变化。该步骤虽然时间很短，但也会像补偿阶段那样改变第二节点N2的电压值，起到再次补偿的效果。
第四阶段S4、即发光阶段，扫描信号线Scan的输入信号为低电平信号，复位信号线Reset的输入信号为低电平信号，数据信号线Data的输入信号为低电平信号，第一晶体管T1截止，第二晶体管T2导通，向发光元件OLED 提供驱动电路，发光元件OLED发光。
在一种示例性实施例中，数据信号线Data的输入信号在一帧内由低电平变为高电平，使得数据信号线Data的输入信号的频率较高。
图9为一种示例性实施例提供的一个驱动结构的版图示意图。如图9所示，在一种示例性实施例中提供的显示基板中，第一晶体管T1包括：第一有源层11、第一栅电极12、第一源电极13和第一漏电极14，第二晶体管T2包括第二有源层21、第二栅电极22、第二源电极23和第二漏电极24，第三晶体管T3包括第三有源层31、第三栅电极32、第三源电极33和第三漏电极34。存储电容包括第一极板41和第二极板42。图9是以第一极为源电极，第二极为漏电极为例进行说明。
如图9所示，在一种示例性实施例中，驱动结构层还包括：沿第二方向延伸的第一参考连接线51和第二参考连接线61。
第一参考连接线51与第二参考连接线61异层设置，第二参考连接线61分别与参考信号线Vref和第一参考连接线51电连接。
如图9所示，在一种示例性实施例中，每个驱动结构中包括两个沿第一方向排布的第一参考连接线和三个沿第一方向排布的第二参考连接线。
第一个第一参考连接线在基底上的正投影与第一数据线和第二数据线在基底上的正投影存在重叠区域；第二个第一参考连接线在基底上的正投影与第三数据线和参考信号线在基底上的正投影存在重叠区域。第一个第一参考连接线分别与第一个第二参考连接线和第二个第二参考连接线电连接；第二个第一参考连接线分别与第二个第二参考连接线和第三个第二参考连接线电连接；第二个第二参考连接线与参考信号线连接，且为连续的一体结构。
在一种示例性实施例中，扫描信号线Scan与每个驱动结构中的第一晶体管T1的第一栅电极12电连接，复位信号线Reset与每个驱动结构中第三晶体管T3的第三栅电极32电连接，数据信号线Data与每个驱动结构中第一晶体管T1的第一源电极13电连接，第一参考连接线51和第二参考连接线61设置为使第三晶体管T3的第三源电极33与参考信号线Vref电连接。以第一驱动结构100A的像素驱动电路为例，第一晶体管T1的第一栅电极12与扫描信号线Scan电连接，第一晶体管T1的第一源电极13与数据信号线Data 电连接，第一晶体管T1的第一漏电极14与第二晶体管T2的第二栅电极22电连接。第二晶体管T2的第二栅电极22与第一晶体管T1的第一漏电极14电连接，第二晶体管T2的第二源电极23与第三晶体管T3的第三漏电极34和发光元件的第一极电连接，第二晶体管T2的第二漏电极24与第一电源线VDD电连接，第三晶体管T3的第三栅电极32与复位信号线Reset电连接，第三晶体管T3的第三源电极33通过第一参考连接线51和第二参考连接线61与参考信号线Vref电连接，第三晶体管T3的第三漏电极34与第二晶体管T2的第二源电极23和发光元件的第一极电连接。第一极板41与第二晶体管T2的第二源电极23和第三晶体管T3的第三漏电极34电连接，第二极板42与第一晶体管T1的第一漏电极14和第二晶体管T2的第二栅电极22电连接。
在一种示例性实施例中，驱动结构层包括：沿垂直于基底方向依次设置的第一绝缘层、有源层、第二绝缘层、第一金属层、第三绝缘层和第二金属层。
有源层包括：所有晶体管的有源层。每个晶体管的有源层同层设置且通过同一次构图工艺形成。第一金属层包括：第一参考连接线、所有晶体管的控制极、第一极板、复位信号线、扫描信号线和第一电源连接线。第一参考连接线、所有晶体管的控制极、第一极板、复位信号线、扫描信号线和第一电源连接线同层设置，且通过同一次构图工艺形成。第二金属层包括：第二参考连接线、参考信号线、数据线、第二极板以及所有晶体管的第一极和第二极。第二参考连接线、参考信号线、数据线、第二极板以及所有晶体管的第一极和第二极同层设置，且通过同一次构图工艺形成。
图中所示的像素驱动电路中的晶体管均是以N型晶体管为例进行说明，即各个晶体管在栅极接入高电平时导通(导通电平)，而在接入低电平时截止(截止电平)。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。
该像素驱动电路包括但不限于图7的配置方式，例如，像素驱动电路中的各个晶体管也可以采用N型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体 管的端口极性进行连接即可。
该像素驱动电路中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，在本公开的实施例中，电容的电极可以采用金属电极或其中一个电极采用半导体材料(例如掺杂的多晶硅)。
在一种示例性实施例中，每个驱动结构中的所有驱动电路中的第一晶体管T1位于第二极板42靠近第一电源连接线VL的一侧，第三晶体管T3位于第二极板42远离第一电源连接线VL的一侧。
在一种示例性实施例中，在每个驱动结构中，第一驱动电路中的第一晶体管与第三驱动电路中的第一晶体管相对于驱动结构两侧的两个第一电源线的中线镜像对称，第一驱动电路中的第二晶体管与第三驱动电路中的第二晶体管相对于驱动结构两侧的两个第一电源线的中线镜像对称，第一驱动电路中的第三晶体管与第三驱动电路中的第三晶体管相对于驱动结构两侧的两个第一电源线的中线镜像对称。
在一种示例性实施例中，当第一驱动电路和第二驱动电路之间设置有第一数据线和第二数据线时，第一驱动电路中的第一晶体管与第二驱动电路中的第一晶体管相对于第一数据线和第二数据线的中线镜像对称，第一驱动电路中的第二晶体管与第二驱动电路中的第二晶体管相对于第一数据线和第二数据线的中线镜像对称，第一驱动电路中的第三晶体管与第二驱动电路中的第三晶体管相对于第一数据线和第二数据线的中线镜像对称。当第一驱动电路和第二驱动电路之间设置有第一数据线和参考信号线时，第一驱动电路中的第一晶体管与第二驱动电路中的第一晶体管相对于第一数据线和参考信号线的中线镜像对称，第一驱动电路中的第二晶体管与第二驱动电路中的第二晶体管相对于第一数据线和参考信号线的中线镜像对称，第一驱动电路中的 第三晶体管与第二驱动电路中的第三晶体管相对于第一数据线和参考信号线的中线镜像对称。
在一种示例性实施例中，驱动结构层还包括：位于第二金属层远离基底一侧的平坦层，平坦层上设置有过孔，平坦层过孔暴露第二晶体管T2的第二源电极。
在一种示例性实施例中，发光结构层包括：第一电极、有机发光层和第二电极。第一电极位于有机发光层靠近基底的一侧，第二电极位于有机发光层远离基底的一侧。第一电极通过平坦层过孔与第二晶体管T2的第二源电极电连接。
一种示例性实施例中，如图9所示，第三绝缘层设置有暴露出第一电源连接线VL的第一过孔和暴露出第一参考连接线51的第二过孔。第一电源线VDD通过第一过孔与第一电源连接线VL电连接；第二参考连接线61通过第二过孔与第一参考连接线51电连接。
在一种示例性实施例中，如图1至3所示，第二电源线VSS与扫描信号线Scan同层设置。第三绝缘层上设置有暴露出第二电源线的连接过孔，参考走线通过连接过孔与第二电源线电连接。
在一种示例性实施例中，第二电极在基底上的正投影与第二电源线在基底上的正投影存在重叠区域，第二电极与第二电源线电连接。
在一种示例性实施例中，显示区域的形状可以为轴对称形状，或者可以为非轴对称形状。当显示区域的形状为轴对称形状时，对称轴可以沿第一方向延伸或者沿第二方向延伸。
在一种示例性实施例中，显示区域的形状可以为圆形、椭圆形、扇形、心形、三角形或N边形，N大于4。
下面通过显示基板的制备过程说明一种示例性实施例提供的显示基板的结构。“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆 工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
图10至图12为一种示例性实施例提供的显示基板制备过程的示意图，示意了显示基板一个驱动结构的版图结构，每个驱动结构包括：三个驱动电路。每个驱动电路中的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。
(1)在基底形成有源层，包括：在基底上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成第一绝缘层，在第一绝缘层上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成位于显示区域的有源层。有源层包括第一有源层11、第二有源层21和第三有源层31，如图10所示。
第一有源层11作为第一晶体管的有源层，第二有源层21作为第二晶体管的有源层，第三有源层31作为第三晶体管的有源层。
在一种示例性实施例中，第一有源层11、第二有源层21和第三有源层31在基底上的正投影与第一极板41在基底上的正投影间隔设置，即第一有源层11与第一极板41之间、第二有源层21与第一极板41之间以及第三有源层31与第一极板41之间没有交叠区域，有利于根据相关需求设计第一晶体管、第二晶体管和第三晶体管的沟道宽长比。
在一种示例性实施例中，第一有源层11、第二有源层21和第三有源层31在基底上的正投影与第二极板42在基底上的正投影间隔设置，即第一有源层11与第二极板42之间、第二有源层21与第二极板42之间以及第三有源层31与第二极板42之间没有交叠区域，有利于根据相关需求设计第一晶体管、第二晶体管和第三晶体管的沟道宽长比。
(2)形成第二金属层，包括：在形成有有源层的基底上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成位于显示区域的第二绝缘层。在第二绝缘层上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成第一金属层。第一金属层包括：复位信号线Reset、扫描信号线 Scan、第一电源连接线VL、第一参考连接线51以及形成在每个驱动结构中第一栅电极12、第二栅电极22、第三栅电极32和第一极板41，如图11所示。
在一种示例性实施例中，复位信号线Reset、扫描信号线Scan、第一电源连接线VL和第一参考连接线51平行设置，且均沿第一方向延伸。复位信号线Reset和扫描信号线Scan分别位于第一极板41的两侧，第一电源连接线VL位于扫描信号线Scan远离第一极板41的一侧，第一参考连接线51位于复位信号线Reset远离第一极板41的一侧。
在一种示例性实施例中，第一栅电极12是与扫描信号线Scan连接的一体结构，且跨设在第一有源层11上。第二栅电极22跨设在第二有源层21上。第三栅电极32是与复位信号线Reset连接的一体结构，且跨设在第三有源层31上。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一金属层后，利用第一栅电极12、第二栅电极22和第三栅电极32作为遮挡对有源层进行等离子体处理，被第一栅电极12、第二栅电极22和第三栅电极32遮挡区域的有源层(即有源层与第一栅电极12、第二栅电极22和第三栅电极32重叠的区域)作为晶体管的沟道区域，未被第一金属层遮挡区域的有源层被处理成导体化层，形成导体化的源漏区域。
(3)形成第三绝缘层。形成第三绝缘层包括：在形成有第一金属层的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层。第三绝缘层上开设有多个过孔，多个过孔包括：位于第一电源连接线VL所在位置的第一过孔H1、位于第一参考连接线所在位置的第二过孔H2，位于第一栅电极12两侧的第三过孔H3和第四过孔H4，位于第二栅电极22两侧的第五过孔H5和第五过孔H6、位于第二栅电极22所在位置的第七过孔H7，位于第三栅电极32一侧的第八过孔H8位于第一极板41所在位置的第九过孔H9，如图12所示。
在一种示例性实施例中，第一过孔H1暴露出第一电源连接线VL的表面，第二过孔H2暴露出第一参考连接线51的表面，第三过孔H3和第四过孔H4暴露出第一有源层11两端的表面。第五过孔H5和第六过孔H6暴露 出第二有源层21两端的表面，第七过孔H7暴露出第二栅电极22的表面，第八过孔H8暴露出第三有源层31的表面，第九过孔H9暴露出第一极板41的表面。
(4)形成第二金属层，包括：在形成有第三绝缘层的基底上，沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，在第三绝缘层上形成位于显示区域的第二金属层。第二金属层包括：第一电源线VDD、三条数据线Data、参考信号线Vref、第二参考连接线61以及形成在每个驱动结构中的第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第二极板42。如图4所示。
在一种示例性实施例中，第一电源线VDD、数据线Data和参考信号线Vref平行设置，且沿第二方向延伸。两条数据线设置第一驱动结构和第二驱动结构之间，另外一条数据线和参考信号线设置在第二驱动结构和第三驱动结构之间。
在一种示例性实施例中，第一电源线VDD通过第一过孔H1与第一电源连接线VL电连接。第二参考连接线61通过第二过孔H2与第一参考连接线51电连接。
在一种示例性实施例中，第一源电极13是与数据信号线Data连接的一体结构，使得每条数据信号线Data分别与所在驱动结构的第一源电极13电连接，第一源电极13通过第三过孔H3与第一有源层11的一端电连接，第一漏电极14通过第四过孔H4与第一有源层11的另一端电连接，第一漏电极14还通过第七过孔H7同时与第二栅电极22和第二极板42电连接，实现了第一漏电极14、第二栅电极22和第二极板42具有相同的电位。
在一种示例性实施例中，第二源电极23通过第五过孔H5和第九过孔H9同时与第二有源层21的一端和第一极板41电连接，实现了第二源电极23、第三漏电极34和第一极板41具有相同的电位。第二漏电极24通过第六过孔H6与第二有源层21的另一端电连接。
在一种示例性实施例中，第三源电极33通过第八过孔H8与第三有源层31的一端电连接，同时通过第二过孔H2与参考信号线Vref电连接，实现了 第三源电极33与参考信号线Vref的电连接。
在一种示例性实施例中，第二源电极23、第三漏电极34和第一极板41为相互连接的一体结构。
(5)形成第四绝缘层和平坦层，包括：在形成有第二金属层的基底上，先沉积第四绝缘薄膜，后涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，对第四绝缘薄膜进行刻蚀形成第四绝缘层，以及设置在第四绝缘层上的，位于显示区域和透明区域的平坦层，第四绝缘层和平坦层上开设有多个过孔，多个过孔包括：每个驱动结构中第二晶体管T2的源电极所在位置的过孔。过孔暴露出第二晶体管T2的源电极的表面。
(6)形成透明导电层，包括：在形成有平坦层的基底上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在平坦层上形成透明导电层，透明导电层包括第一电极，第一电极形成在显示区域的每个发光元件中，第一电极通过平坦层过孔与第二晶体管T2的源电极电连接。
(7)形成像素定义层，包括：在形成透明导电层的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)，像素定义层形成在在显示区域的每个发光元件中，每个发光元件中的像素定义层形成有暴露出阳极的开口区域。
(8)形成有机发光层，包括：在形成的像素定义层的开口区域内和像素定义层上形成有机发光层，有机发光层与第一电极电连接。
(9)形成第二电极，包括：在形成有机发光层的基底上涂覆阴极薄膜，通过构图工艺对导电薄膜进行构图，形成第二电极。阴极形成在显示区域中，并覆盖每个发光元件中的有机发光层。在显示区域中，第二电极与有机发光层电连接。
(10)形成封装层，在形成第二电极的基底上形成封装层，封装层包括无机材料的第一封装层、有机材料的第二封装层和无机材料的第三封装层，第一封装层设置在第二电极上，第二封装层设置在第一封装层上，第三封装层设置在第二封装层上，形成无机材料/有机材料/无机材料的叠层结构。
在一种示例性实施例中，第一金属层和第二金属层可以采用金属材料， 如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为缓冲层，设置为提高基底的抗水氧能力，第二绝缘层称为栅绝缘层，第三绝缘层称为层间绝缘层，第四绝缘层称为钝化层。
在一种示例性实施例中，第二绝缘层的厚度可以小于第三绝缘层的厚度，第一绝缘层的厚度可以小于第二绝缘层和第三绝缘层的厚度之和，在保证绝缘效果的前提下，可以提高存储电容的容量。
在一种示例性实施例中，平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在一种示例性实施例中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在一种示例性实施例中，第二电极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或可以采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，第一绝缘层的厚度为3000埃到5000埃，第二绝缘层的厚度为1000埃到2000埃，第三绝缘层的厚度为4500埃到7000埃，第四绝缘层的厚度为3000埃到5000埃。
在一种示例性实施例中，第一金属层的厚度为80埃到1200埃，第二金属层的厚度为3000埃到5000埃，第三金属层的厚度为3000埃到9000埃。
在一种示例性实施例中，有源层可以为金属氧化物层。金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟或镓和锌的氧化物等。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方 式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，像素驱动电路可以是5T1C或7T1C。再如，膜层结构中还可以设置其它电极或引线。
本公开实施例还提供一种显示装置，包括：显示基板。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪，或者可以为任何具有显示功能的产品或部件。
本实施例提供的显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示基板，包括：显示区域和非显示区域，所述显示基板包括：基底以及设置在所述基底上的驱动结构层和走线层；所述驱动结构层位于所述显示区域，所述走线层位于所述非显示区域；所述驱动结构层包括：沿第一方向延伸的第一电源线、数据信号线和参考信号线；所述走线层包括：第一电源走线、数据走线和参考走线；
    所述第一电源走线与所述第一电源线电连接，所述数据走线与所述数据信号线电连接，所述参考走线与所述参考信号线电连接；
    所述第一电源走线位于所述显示区域的第一侧，所述数据走线位于所述显示区域的第二侧，所述第二侧与所述第一侧不同；所述数据走线和所述参考走线位于所述显示区域的同一侧；
    对于同一长度的所述第一电源线，所述数据信号线和所述参考信号线，所述第一电源线的电阻大于所述数据信号线的电阻，且大于所述参考信号线的电阻。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源线线宽大于所述数据信号线线宽，且大于所述参考信号线线宽。
  3. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于所述非显示区域的第二电源线和第二电源走线；
    所述第二电源线与所述第二电源走线电连接，所述第二电源线沿第二方向延伸，所述第二方向和所述第一方向相交；所述第二电源线与所述第二电源走线位于所述显示区域的同一侧，所述第二电源走线与所述数据走线位于所述显示区域的同一侧。
  4. 根据权利要求3所述的显示基板，其中，所述第二电源线与所述参考走线异层设置，所述第二电源线在所述基底上的正投影与所述参考走线在所述基底上的正投影存在重叠区域；
    所述第二电源线与所述参考走线电连接。
  5. 根据权利要求3或4所述的显示基板，其中，所述显示基板还包括：柔性电路板以及位于所述非显示区域的源极驱动芯片和至少一个焊盘；所述 焊盘与所述第一电源走线位于所述显示区域的同一侧，所述源极驱动芯片与所述数据走线位于所述显示区域的同一侧；所述源极驱动芯片位于所述第二电源线远离所述显示区域的一侧；
    所述源极驱动芯片与所述数据走线电连接，设置为通过数据走线向所述数据信号线提供数据信号；
    所述柔性电路板，分别与焊盘和第二电源走线电连接，设置为通过所述焊盘向所述第一电源走线供电，并向所述第二电源走线供电。
  6. 根据权利要求3或4所述的显示基板，其中，所述显示基板还包括：外围电路板、柔性信号线以及位于所述非显示区域的源极驱动芯片和至少一个焊盘；所述焊盘与所述第一电源走线位于所述显示区域的同一侧，所述源极驱动芯片与所述数据走线位于所述显示区域的同一侧；所述源极驱动芯片位于所述第二电源线远离所述显示区域的一侧；
    所述源极驱动芯片与所述数据走线电连接，设置为通过所述数据走线向所述数据信号线提供数据信号；
    所述外围电路板，通过所述柔性信号线分别与所述焊盘、所述第二电源走线和所述源极驱动芯片电连接，设置为通过焊盘向所述第一电源走线供电，向所述第二电源走线供电，并向所述源极驱动芯片提供信号。
  7. 根据权利要求2至6任一项所述的显示基板，其中，所述驱动结构层还包括：位于所述显示区域，且沿所述第二方向延伸的多个第一电源连接线；所述第一电源连接线与所述第一电源线异层设置；
    至少一个第一电源连接线在基底上的正投影与所述第一电源线在基底上的正投影存在重叠区域；所述至少一个第一电源连接线的每一个与所述第一电源线电连接。
  8. 根据权利要求2至7任一项所述的显示基板，其中，所述驱动结构层还包括：沿所述第二方向延伸的多个扫描信号线和多个复位信号线以及矩阵排布的多个驱动结构，所述第一电源线设置在两个相邻的驱动结构之间；
    其中，每个驱动结构包括：沿所述第二方向排布的第一驱动电路、第二驱动电路和第三驱动电路。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：位于所述非显示区域的栅极驱动电路；所述栅极驱动电路位于所述显示区域的第三侧，所述第三侧为与所述第一侧和所述第二侧不同的一侧；
    所述栅极驱动电路，分别与所述扫描信号线和所述复位信号线电连接，设置为向所述扫描信号线和所述复位信号线提供信号；
    所述栅极驱动电路包括：多个移位寄存器，每个移位寄存器包括：第一移位寄存器和第二移位寄存器；第一移位寄存器，与所述扫描信号线电连接，设置为向扫描信号线提供信号，第二移位寄存器，与所述复位信号线电连接，设置为向复位信号线提供信号；多个第一移位寄存器级联，多个第二移位寄存器级联。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括：扫描走线和复位走线；所述扫描走线，分别与所述扫描信号线和栅极驱动电路电连接，所述复位走线，分别与所述复位信号线和所述栅极驱动电路电连接；
    所述栅极驱动电路包括：多个移位寄存器组，每个移位寄存器组包括：至少一个移位寄存器；每个移位寄存器组中的所有移位寄存器沿第一方向排布；
    多个移位寄存器组成阶梯状排布，相邻移位寄存器之间沿第二方向的间距大于所述扫描走线线长和所述复位走线线长之和。
  11. 根据权利要求8所述的显示基板，其中，在每个驱动结构中，所述数据信号线包括：第一数据线、第二数据线和第三数据线；所述第一数据线与所述第一驱动电路电连接，所述第二数据线与所述第二驱动电路电连接，所述第三数据线与所述第三驱动电路电连接；所述参考信号线，分别与所述第一驱动电路、所述第二驱动电路和所述第三驱动电路电连接；
    所述第一数据线和所述第二数据线位于所述第一驱动电路和所述第二驱动电路之间，所述第二数据线位于所述第一数据线靠近所述第二驱动电路的一侧；所述第三数据线和所述参考信号线位于所述第二驱动电路和所述第三驱动电路之间，所述第三数据线位于所述参考信号线靠近所述第三驱动电路一侧；
    或者，所述第一数据线和所述参考信号线位于所述第一驱动电路和所述第二驱动电路之间，所述第一数据线位于所述参考信号线靠近所述第二驱动电路的一侧；所述第二数据线和所述第三数据线位于所述第二驱动电路和所述第三驱动电路之间，所述第三数据线位于所述第二数据线靠近所述第三驱动电路一侧。
  12. 根据权利要求11所述的显示基板，其中，在每个驱动电路中，所述第一驱动电路与所述第三驱动电路相对于所述第一数据线和所述第三数据线的中线镜像对称。
  13. 根据权利要求8所述的显示基板，其中，所述显示基板包括：沿第二方向排布的、且相邻设置的第一驱动结构、第二驱动结构和第三驱动结构；
    所述第一驱动结构中的第三驱动电路与所述第二驱动结构中的第一驱动电路相对于位于所述第一驱动结构和所述第二驱动结构之间的第一电源线镜像对称；
    所述第二驱动结构中的第三驱动电路与所述第三驱动结构中的第一驱动电路相对于位于所述第二驱动结构和所述第三驱动结构之间的第一电源线镜像对称。
  14. 根据权利要求8所述的显示基板，其中，所述驱动结构层还包括：沿所述第二方向延伸的第一参考连接线和第二参考连接线；
    所述第一参考连接线和所述第二参考连接线异层设置；所述第二参考连接线分别与所述参考信号线和所述第一参考连接线电连接。
  15. 根据权利要求14所述的显示基板，其中，每个驱动结构中包括两个沿第二方向排布的第一参考连接线和三个沿第二方向排布的第二参考连接线；
    第一个第一参考连接线分别与第一个第二参考连接线和第二个第二参考连接线电连接；
    第二个第一参考连接线分别与第二个第二参考连接线和第三个第二参考连接线电连接；
    其中一个第二参考连接线与所述参考信号线电连接，且为连续的一体结构。
  16. 根据权利要求1至15任一项述的显示基板，其中，所述显示基板还包括：位于所述驱动结构层远离所述基底一侧的发光结构层，所述发光结构层包括：多个发光元件；
    所述驱动结构层中的每个驱动电路包括：设置为驱动所述发光元件发光的像素驱动电路；
    所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；所述第二晶体管为驱动晶体管；所述存储电容包括：第一极板和第二极板；
    所述第一晶体管的控制极与扫描信号线电连接，所述第一晶体管的第一极与数据信号线电连接，所述第一晶体管的第二极与第一节点电连接；所述第二晶体管的控制极与第一节点电连接，所述第二晶体管的第一极与第一电源线电连接，所述第二晶体管的第二极与第二节点电连接；所述第三晶体管的控制极与复位信号线电连接，所述第三晶体管的第一极与参考信号线电连接，所述第三晶体管的第二极与第二节点电连接，所述存储电容的第一极板与所述第二节点电连接，所述存储电容的第二极板与所述第一节点电连接；
    所述发光元件的第一极与第二节点电连接，所述发光元件的第二极与第二电源线电连接。
  17. 根据权利要求16所述的显示基板，其中，所述驱动结构层包括：沿垂直于所述基底方向依次设置的第一绝缘层、有源层、第二绝缘层、第一金属层、第三绝缘层和第二金属层；
    所述有源层包括：所有晶体管的有源层；所述第一金属层包括：第一参考连接线、所有晶体管的控制极、第一极板、复位信号线、扫描信号线和第一电源连接线；所述第二金属层包括：第二参考连接线、参考信号线、数据线、第二极板以及所有晶体管的第一极和第二极。
  18. 根据权利要求17所述的显示基板，其中，所述第三绝缘层设置有暴露出所述第一电源连接线的第一过孔和暴露出所述第一参考连接线的第二过孔；
    所述第一电源线通过所述第一过孔与所述第一电源连接线电连接，所述 第二参考连接线通过所述第二过孔与所述第一参考连接线电连接。
  19. 根据权利要求17所述的显示基板，其中，所述第二电源线与扫描信号线同层设置；
    所述第三绝缘层上设置有暴露出所述第二电源线的连接过孔；
    所述参考走线通过所述连接过孔与所述第二电源线电连接。
  20. 根据权利要求17所述的显示基板，其中，所述发光结构层包括：第一电极、有机发光层和第二电极；所述第一电极位于所述有机发光层靠近所述基底的一侧，所述第二电极位于所述有机发光层远离所述基底的一侧；
    所述第二电极在所述基底上的正投影与所述第二电源线在所述基底上的正投影存在重叠区域，所述第二电极与所述第二电源线电连接。
  21. 根据权利要求1所述的显示基板，其中，数据走线线长与数据信号线线长呈负相关。
  22. 根据权利要求1所述的显示基板，其中，所述显示区域的形状为圆形、椭圆形、扇形、心形、三角形或N边形，N大于4。
  23. 一种显示装置，包括：如权利要求1至22任一项所述的显示基板。
PCT/CN2020/093492 2020-05-29 2020-05-29 显示基板和显示装置 WO2021237725A1 (zh)

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