WO2023184163A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023184163A1
WO2023184163A1 PCT/CN2022/083768 CN2022083768W WO2023184163A1 WO 2023184163 A1 WO2023184163 A1 WO 2023184163A1 CN 2022083768 W CN2022083768 W CN 2022083768W WO 2023184163 A1 WO2023184163 A1 WO 2023184163A1
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WIPO (PCT)
Prior art keywords
layer
transparent conductive
auxiliary
display
display substrate
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PCT/CN2022/083768
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English (en)
French (fr)
Inventor
唐庆
顾青松
熊林
马宁
王丹凤
Original Assignee
京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 绵阳京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/083768 priority Critical patent/WO2023184163A1/zh
Priority to CN202280000602.XA priority patent/CN117256209A/zh
Publication of WO2023184163A1 publication Critical patent/WO2023184163A1/zh

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  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • embodiments of the present disclosure provide a display substrate, including: a base substrate, a pixel circuit layer, a first flat layer, at least one transparent conductive layer, and a plurality of first light-emitting elements.
  • the base substrate includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area.
  • a pixel circuit layer is located in the first display area, the pixel circuit layer includes a plurality of pixel circuits, and the plurality of pixel circuits includes a plurality of first pixel circuits.
  • a plurality of first light-emitting elements are located in the second display area.
  • the first flat layer is located on the side of the pixel circuit layer away from the base substrate, and is located in the first display area and the second display area.
  • At least one transparent conductive layer is located on a side of the first flat layer away from the base substrate.
  • the transparent conductive layer includes: a plurality of first transparent conductive lines and at least one auxiliary structure, and the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines. catch.
  • An orthographic projection of the auxiliary structure on the base substrate overlaps with an orthographic projection of at least one of the plurality of pixel circuits on the base substrate.
  • the display substrate further includes: a first conductive layer located between the pixel circuit layer and the first flat layer, the first conductive layer includes: at least one shielding electrode, the shielding electrode The electrode is electrically connected to at least one pixel circuit among the plurality of pixel circuits, and an orthographic projection of the auxiliary structure on the base substrate overlaps with an orthographic projection of the shielding electrode on the base substrate.
  • the pixel circuit layer includes: a second conductive layer, the second conductive layer includes a first power supply line, and the shielding electrode is electrically connected to the first power supply line.
  • the auxiliary structure is electrically connected to the shielding electrode.
  • the pixel circuit at least includes: a driving transistor, a threshold compensation transistor and a first reset transistor, the driving transistor, the threshold compensation transistor and the first reset transistor are all electrically connected to the first node;
  • the orthographic projection of the shielding electrode on the base substrate is configured to cover the orthographic projection of the first node of the pixel circuit on the base substrate.
  • the orthographic projection of the shielding electrode on the base substrate has an irregular shape.
  • a second planar layer is provided between the first conductive layer and the second conductive layer, and the first conductive layer is connected to the first conductive layer through a first via hole penetrating the second planar layer.
  • the second conductive layer is electrically connected; an orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate and the first via hole on the base substrate There is overlap in orthographic projections.
  • the first transparent conductive line includes an edge transparent conductive line adjacent the auxiliary structure.
  • the auxiliary structure is located between two of the edge transparent conductive lines.
  • the distance between the auxiliary structure and the adjacent edge transparent conductive line is greater than or equal to 2 microns and less than or equal to 3 microns.
  • the at least one auxiliary structure includes: a plurality of auxiliary blocks regularly arranged.
  • a plurality of auxiliary blocks of the auxiliary structure are arranged in an array, and the shapes and sizes of the plurality of auxiliary blocks are substantially the same.
  • the orthographic projection of the plurality of auxiliary blocks on the base substrate is a rectangle.
  • the plurality of auxiliary blocks of the auxiliary structure are arranged in a ring.
  • At least one auxiliary block of the auxiliary structure is electrically connected to the first power line.
  • At least two adjacent auxiliary blocks of the auxiliary structure are connected by connecting lines.
  • the plurality of auxiliary blocks of the auxiliary structure are divided into multiple groups, each group includes at least two auxiliary blocks, and the auxiliary blocks within a group are connected by connecting lines.
  • the at least one auxiliary structure is annular or mesh-shaped in an orthographic projection of the base substrate.
  • the plurality of pixel circuits further include: a plurality of second pixel circuits located in the first display area; the display substrate further includes: a plurality of third pixel circuits located in the first display area. Two light-emitting elements; at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to The at least one second light-emitting element is driven.
  • embodiments of the present disclosure provide a display device including the display substrate as described above.
  • Figure 1 is a schematic diagram of the preparation of a display substrate
  • Figure 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • Figure 3 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure
  • Figure 5 is a partial cross-sectional schematic diagram along the P-P’ direction in Figure 4;
  • Figure 6 is a partial top view of the display substrate after forming the second conductive layer in Figure 4.
  • Figure 7 is a partial top view of the display substrate after forming the transparent conductive layer in Figure 4.
  • FIG. 8 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 9 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 12 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 13 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 14 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 15 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 16 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 17 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 18 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 19 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 20 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • 21 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 22 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 23 is a partial cross-sectional schematic diagram along the P-P’ direction in Figure 22;
  • Figure 24 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 25 is an operating timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 26 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 27 is a partial cross-sectional view along the R-R’ direction in Figure 26;
  • Figure 28A is a schematic top view of the display substrate after forming the semiconductor layer in Figure 26;
  • Figure 28B is a schematic top view of the display substrate after forming the first gate metal layer in Figure 26;
  • Figure 28C is a schematic top view of the display substrate after forming the second gate metal layer in Figure 26;
  • Figure 28D is a schematic top view of the display substrate after forming the third insulating layer in Figure 26;
  • Figure 28E is a schematic top view of the display substrate after forming the second conductive layer in Figure 26;
  • FIG. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection and “coupling” include the case where constituent elements are connected together through an element having a certain electrical effect.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • Light transmittance in this disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • line length refers to the length along the extension direction of the trace
  • line width refers to the length in the plane where the trace is located, in the direction that crosses the direction of the trace extension (for example, the direction perpendicular to the extension direction).
  • the display substrate may include: an under-screen camera area and a normal display area located around the under-screen camera area.
  • the under-screen camera area can only retain light-emitting elements, and the pixel circuit that drives the light-emitting elements in the under-screen camera area is set in the normal display area, and is electrically connected to the light-emitting elements in the under-screen camera area through transparent conductive wires set on the transparent conductive layer.
  • Pixel circuit in normal display area since the surrounding environment of the transparent conductive line at the edge of the transparent conductive line layer is relatively open, it is easily exposed to a larger amount of exposure during the exposure process, which easily causes the line width of the edge transparent conductive line to become thinner.
  • the edge transparent conductive line may refer to a transparent conductive line having an open area on at least one side in the line width direction.
  • the length of the open area along the line width direction of the transparent conductive line may be greater than or equal to 8 microns. That is, the distance between at least one side of the edge transparent conductive line in the line width direction and the adjacent trace may be greater than or equal to 8 microns.
  • one side of the edge transparent conductive line can be provided with an adjacent transparent conductive line, and the distance between the adjacent transparent conductive line can be about 2 microns to 3 microns, such as 2.5 microns; the other side of the edge transparent conductive line can Sides can have open areas.
  • the edge transparent conductive line has open areas on opposite sides in the line width direction.
  • the line width of the transparent conductive line may become thinner or the line may be broken due to the reflection focusing effect of the conductive layer during the exposure process.
  • Figure 1 is a schematic diagram of the preparation of a display substrate.
  • the display substrate may include: a base substrate 1, and a second conductive layer 2, a second flat layer 3, a first conductive layer 4, a first flat layer 5 and a transparent layer disposed on the base substrate 1.
  • conductive layer Figure 1 shows a schematic diagram of the principle of the exposure process during the preparation of the transparent conductive layer.
  • the preparation process of the transparent conductive layer includes: forming a transparent conductive film 6 on the first flat layer 5, forming a photoresist film 7 on the transparent conductive film 6, and performing photolithography using a mask as a mask.
  • the photoresist film 7 is exposed, so that the photoresist film forms a photoresist retained part and a photoresist to-be-removed part.
  • a development process is performed. In the development process, the photoresist to-be-removed part is removed to form a photolithography process. Glue graphics.
  • the transparent conductive film 6 is etched using the photoresist pattern as a mask to form a transparent conductive layer. However, as shown in FIG.
  • the first conductive layer 4 can overlap with the second conductive layer 2 through the via hole, and the overlapping structure of the first conductive layer 4 in the via hole can form a bowl-like inner recess.
  • the opening direction of the inner recess is away from the base substrate 1 .
  • the inner recess can form a focusing effect similar to a concave mirror.
  • the first conductive layer 4 of metal material will reflect light and focus it on the photoresist retaining portion located above the inner concave portion of the first conductive layer 4, so that this part of the photoresist is exposed or partially exposed, and developed Then it is washed away, so the transparent conductive lines formed after etching the transparent conductive film using the photoresist pattern as a mask are prone to breakage or thinning. Therefore, at the via hole position of the second flat layer 3, due to the reflection focusing effect of the first conductive layer 4 during the exposure process, the photoresist film at the via hole position will become thinner, resulting in the appearance of the finally formed transparent conductive line. The lines are broken or thinned, causing dark spots on the display.
  • This embodiment provides a display substrate, including: a base substrate, a pixel circuit layer, a first flat layer, at least one transparent conductive layer, and a plurality of first light-emitting elements.
  • the base substrate includes a first display area and a second display area, the first display area at least partially surrounding the second display area.
  • the pixel circuit layer is located in the first display area and includes a plurality of pixel circuits.
  • the plurality of pixel circuits include a plurality of first pixel circuits.
  • a plurality of first light-emitting elements are located in the second display area.
  • the first flat layer is located on a side of the pixel circuit layer away from the base substrate, and is located in the first display area and the second display area.
  • At least one transparent conductive layer is located on a side of the first flat layer away from the base substrate.
  • the transparent conductive layer includes: a plurality of first transparent conductive lines and at least one auxiliary structure.
  • the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through a plurality of first transparent conductive lines.
  • the orthographic projection of the auxiliary structure on the base substrate overlaps with the orthographic projection of the at least one pixel circuit on the base substrate.
  • the display substrate provided in this embodiment can improve the exposure environment of the exposure process of the transparent conductive layer by arranging auxiliary structures on the transparent conductive layer, thereby improving the situation where the first transparent conductive line of the transparent conductive layer is broken or the line width becomes thin. .
  • the display substrate may further include: a first conductive layer located between the pixel circuit layer and the first planar layer.
  • the first conductive layer may include: at least one shielding electrode, and the shielding electrode may be electrically connected to at least one pixel circuit.
  • the orthographic projection of the auxiliary structure on the base substrate and the orthographic projection of the shielding electrode on the base substrate may overlap. This example can use the auxiliary structure to improve the breakage or thinning of the line width of the transparent conductive lines caused by the reflection focusing effect of the shielding electrode during the exposure process, thereby improving the yield of the display substrate.
  • the pixel circuit layer may include a second conductive layer, and the second conductive layer may include a first power line.
  • the shielding electrode may be electrically connected to the first power line.
  • the auxiliary structure can be electrically connected to the shielding electrode. Wherein, the auxiliary structure can be electrically connected to the first power line through the shielding electrode.
  • this embodiment is not limited to this.
  • the auxiliary structure may be directly connected to the first power line, or the auxiliary structure may be connected to other signal lines that transmit direct current signals, or the auxiliary structure may have no electrical connection.
  • the pixel circuit may include at least a driving transistor, a threshold compensation transistor, and a first reset transistor.
  • the drive transistor, the threshold compensation transistor and the first reset transistor are all electrically connected to the first node.
  • the orthographic projection of the shielding electrode on the base substrate may be configured to cover the orthographic projection of the first node of the pixel circuit of the display substrate on the base substrate.
  • the orthographic projection of the shielding electrode on the base substrate may have an irregular shape. However, this embodiment is not limited to this.
  • a second flat layer may be disposed between the first conductive layer and the second conductive layer, and the first conductive layer may be electrically connected to the second conductive layer through a first via hole penetrating the second flat layer.
  • An orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate may overlap with an orthographic projection of the first via hole on the base substrate.
  • the first transparent conductive line may include an edge transparent conductive line, and the edge transparent conductive line may be adjacent the auxiliary structure.
  • the edge transparent conductive line may be adjacent the auxiliary structure.
  • the auxiliary structure may be located between two edge transparent conductive lines.
  • the auxiliary structure can be located between two edge transparent conductive lines, thereby improving the problem of breakage or thinning of the edge transparent conductive lines and improving the yield rate.
  • the spacing between the auxiliary structure and adjacent edge transparent conductive lines may be greater than or equal to 2 microns and less than or equal to 3 microns.
  • the spacing between the auxiliary structure and adjacent edge transparent conductive lines may be approximately 2.5 microns.
  • At least one auxiliary structure may include: a plurality of auxiliary blocks regularly arranged.
  • multiple auxiliary blocks of the auxiliary structure may be arranged in an array, and the shapes and sizes of the multiple auxiliary blocks may be approximately the same.
  • orthographic projections of the plurality of auxiliary blocks on the base substrate may be rectangular.
  • the plurality of auxiliary blocks of the auxiliary structure may be arranged in a ring, for example, in a rectangular ring.
  • the orthographic projection of the plurality of auxiliary blocks on the base substrate may be rectangular or L-shaped.
  • the orthographic projection of the auxiliary block on the substrate may be a circle, an ellipse, a quadrilateral, a pentagon, a hexagon or other shapes.
  • At least one auxiliary block of the auxiliary structure may be electrically connected to the first power line.
  • at least one auxiliary block may be electrically connected to the first power line through the shielding electrode.
  • auxiliary blocks of the auxiliary structure may be connected by connecting lines.
  • multiple auxiliary blocks of the auxiliary structure may be divided into multiple groups, each group may include at least two auxiliary blocks, and the auxiliary blocks within a group may be connected by connecting lines.
  • the plurality of auxiliary blocks connected through the connection lines may be electrically connected to the first power line, or the plurality of auxiliary blocks connected through the connection lines may not be electrically connected to other signal lines.
  • the orthographic projection of the at least one auxiliary structure on the base substrate may be annular or mesh-shaped.
  • an auxiliary structure can be a one-piece structure.
  • the auxiliary structure may be electrically connected to the first power line, or may have no electrical connection relationship.
  • this embodiment is not limited to this.
  • the solution of this embodiment is illustrated below through some examples.
  • the following description takes the display substrate as a display substrate suitable for full-screen and under-screen imaging technology as an example.
  • this embodiment is not limited to this.
  • FIG. 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 3 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB.
  • the surrounding area BB is a non-display area.
  • the display area AA may include: a first display area A1 and a second display area A2.
  • hardware such as a photosensitive sensor (eg, camera) is disposed on one side of the display substrate, and the orthographic projection of the photosensitive sensor on the display substrate overlaps the second display area A2.
  • the second display area A2 can be a light-transmitting display area, and can also be called an under-display camera (UDC, Under Display Camera) area; the first display area A1 can be a normal display area.
  • the first display area A1 is opaque and is only used for display.
  • the display substrate of this embodiment can lay a solid foundation for the realization of a true full screen.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the second display area A2 may be a rectangle, such as a rounded rectangle.
  • this embodiment is not limited to this.
  • the second display area A2 may be in the shape of a circle, other quadrilateral, or pentagon.
  • the display substrate may include: a base substrate and a plurality of sub-pixels located on the base substrate.
  • the plurality of sub-pixels include: a plurality of first sub-pixels and a plurality of second sub-pixels.
  • At least one first sub-pixel includes a first pixel circuit 11 and a first light-emitting element 13, and at least one second sub-pixel includes a second pixel circuit 12 and a second light-emitting element 14.
  • the second pixel circuit 12 and the second light-emitting element 14 are both located in the first display area A1, the first pixel circuit 11 is located in the first display area A1, and the first light-emitting element 13 is located in the second display area A2.
  • the plurality of first pixel circuits 11 may be spaced apart between the plurality of second pixel circuits 12 .
  • the second pixel circuit 12 may be called an in-situ pixel circuit
  • the first pixel circuit 11 may be called an ex-situ pixel circuit.
  • the second display area A2 between adjacent first light-emitting elements 13 is a light-transmitting sub-area, and the area where the first light-emitting element 13 is located is a display sub-area.
  • No pixel circuit is provided in the second display area A2, only light-emitting elements are provided in the second display area A2, and the pixel circuit that drives the light-emitting elements of the second display area A2 is provided in the first display area A1, that is, through the light-emitting elements and the pixel circuit
  • the separate arrangement can improve the light transmittance of the second display area A2.
  • the shape of the light-emitting element of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically or vertically.
  • the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically or horizontally. Arranged in straight rows or squares. However, this embodiment is not limited to this.
  • At least one second pixel circuit 12 of the plurality of second pixel circuits 12 may be electrically connected to at least one second light-emitting element 14 of the plurality of second light-emitting elements 14 , and the orthographic projection of the at least one second pixel circuit 12 on the base substrate at least partially overlaps the orthographic projection of the at least one second light-emitting element 14 on the base substrate.
  • At least one second pixel circuit 12 may be configured to provide a driving signal to the electrically connected second light-emitting element 14 to drive the second light-emitting element 14 to emit light.
  • FIG. 2 takes the first pixel circuit 11 that drives the first light-emitting element 13 to emit light as an example in the first display area A1.
  • the display substrate can adopt a pixel circuit compression scheme.
  • the pixel circuit is reduced in size.
  • the size in the first direction X allows the first pixel circuit 11 and the second pixel circuit 12 to be placed in the first direction
  • the first direction is not limited to this.
  • the first pixel circuit 11 may be located in the peripheral area, thereby forming an external pixel circuit solution.
  • the first display area A1 may be located at at least one side of the second display area A2.
  • the first display area A1 may surround the second display area A2. That is, the second display area A2 may be surrounded by the first display area A1.
  • the second display area A2 may be disposed at other positions, for example, at the top middle position of the base substrate, or at the upper left corner or upper right corner of the base substrate.
  • this embodiment is not limited to this.
  • At least one first pixel circuit 11 among the plurality of first pixel circuits 11 and at least one first light-emitting element 13 among the plurality of first light-emitting elements 13 The electrical connection can be made through the transparent conductive wire L.
  • One end of the transparent conductive line L is electrically connected to the first pixel circuit 11 , and the other end is electrically connected to the first light-emitting element 13 .
  • the transparent conductive line L may extend from the first display area A1 to the second display area A2.
  • the transparent conductive line L may extend along the first direction X from the first display area A1 to the second display area A2; or, the transparent conductive line L may first extend along the second direction Y in the first display area A1 and then along the One direction X extends to the second display area A2.
  • this embodiment is not limited to this.
  • the transparent conductive line L may be made of a transparent conductive material, for example, a conductive oxide material, such as indium tin oxide (ITO), may be used.
  • ITO indium tin oxide
  • the transparent conductive lines L may be arranged in one transparent conductive layer, or a plurality of transparent conductive lines L may be arranged in two or three transparent conductive layers.
  • Each transparent conductive line L can connect a first pixel circuit 11 and a first light-emitting element 13 .
  • a first pixel circuit 11 and a first light-emitting element 13 may be connected in sequence through a plurality of transparent conductive lines L located on different transparent conductive layers to achieve electrical connection.
  • At least one first pixel circuit 11 may be configured to provide a driving signal to at least one electrically connected first light-emitting element 13 to drive the first light-emitting element 13 to emit light.
  • the first pixel circuit 11 and the first light-emitting element 13 are located in different areas, and the orthographic projection of the first pixel circuit 11 on the base substrate and the orthographic projection of the at least one first light-emitting element 13 on the base substrate may not overlap.
  • the first light-emitting element 13 and the first pixel circuit 11 electrically connected thereto may be located in the same row. That is, the driving signal of the first light-emitting element 13 comes from the first pixel circuit 11 in the same row.
  • pixel circuits of sub-pixels in the same row are electrically connected to the same gate line.
  • this embodiment is not limited to this.
  • the first light-emitting element and the first pixel circuit electrically connected thereto may not be located in the same row.
  • FIG. 4 is a schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 can be a partially enlarged schematic diagram of area S in FIG. 3 .
  • Figure 5 is a partial cross-sectional view along the P-P' direction in Figure 4.
  • a transparent conductive layer is used as an example.
  • the display substrate may include multiple transparent conductive layers. 4 and 5 omit to illustrate the multiple film layer structures on the side of the second conductive layer close to the display substrate and the multiple film layers on the side of the transparent conductive layer away from the base substrate.
  • the display substrate of the first display area A1 may include: a base substrate 10 , a base plate disposed on the base substrate 10
  • the pixel circuit layer (for example, includes the second conductive layer 22 ), the second flattening layer 32 , the first conductive layer 21 , the first flattening layer 31 and the transparent conductive layer 23 .
  • a third flat layer, an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer may also be provided on the side of the transparent conductive layer 23 away from the base substrate 10 .
  • the pixel circuit layer may include: a semiconductor layer, a first insulation layer, a first gate metal layer, a second insulation layer, a second gate metal layer, a third insulation layer, and second conductive layer.
  • the second conductive layer 22 may also be called a first source-drain metal layer
  • the first conductive layer 21 may also be called a second source-drain metal layer.
  • the first flat layer 31 and the second flat layer 32 may be organic material layers. However, this embodiment is not limited to this.
  • FIG. 6 is a partial top view of the display substrate after forming the first conductive layer in FIG. 4 .
  • the first conductive layer 21 and the second conductive layer 22 are illustrated in FIG. 6 .
  • FIG. 7 is a partial top view of the display substrate after forming the transparent conductive layer in FIG. 4 .
  • the first conductive layer 21 and the transparent conductive layer 23 are illustrated in FIG. 7 .
  • the second conductive layer 22 may at least include: a plurality of data lines (eg, data lines DL), a plurality of first power supply lines (eg, a first power supply line).
  • Line PL1 a plurality of connection electrodes (including, for example, the first anode connection electrode 220).
  • the data line DL and the first power line PL1 may extend along the second direction Y, and the data line DL and the first power line PL1 are adjacent in the first direction X.
  • the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.
  • the first conductive layer 21 may at least include: a plurality of shielding electrodes 211 and a plurality of connection electrodes (for example, including the second anode connection electrode 210 ).
  • the second anode connection electrode 210 may be electrically connected to the first anode connection electrode 220 through the first via hole K1b opened on the second flat layer 32 .
  • the shielding electrode 211 may be electrically connected to the first power line PL1 through the first via hole K1a opened on the second flat layer 32 .
  • the transparent conductive layer 23 may at least include: a plurality of first transparent conductive lines (for example, edge transparent conductive lines 231a and 231b, non-edge transparent conductive lines 232), and auxiliary Structure 233.
  • first transparent conductive lines for example, edge transparent conductive lines 231a and 231b, non-edge transparent conductive lines 232
  • auxiliary Structure 233 e.g., a plurality of first transparent conductive lines (for example, edge transparent conductive lines 231a and 231b, non-edge transparent conductive lines 232), and auxiliary Structure 233.
  • the edge transparent conductive lines 231a and 231b have an open area on one side in the trace width direction, and the orthographic projection of the edge transparent conductive line 231a on the substrate may intersect with the orthographic projection of the first via K1a on the substrate.
  • the non-edge transparent conductive lines 232 have adjacent traces on both sides in the trace width direction.
  • non-edge transparent conductive line 232 may be located between edge transparent conductive lines 2
  • edge transparent conductive line 231a may be adjacent to the non-edge transparent conductive line 232, and an auxiliary structure 233 may be provided in an open area on the other side.
  • Auxiliary structure 233 may be located between edge transparent conductors 231a and 231b.
  • the auxiliary structure 233 in this example may have no electrical connection and is a dummy structure.
  • edge transparent conductive lines 231 a and 231 b and non-edge transparent conductive lines 232 may both extend along the second direction Y.
  • the line widths of the edge transparent conductive lines and the non-edge transparent conductive lines may be approximately the same, for example, may be approximately 2.0 microns to 2.5 microns, such as may be approximately 2.3 microns. However, this embodiment is not limited to this.
  • the line width of the edge transparent conductive lines may be greater than the line width of the non-edge transparent conductive lines.
  • the length H1 of the open area between the edge transparent conductive lines 231a and 231b in the first direction X may be greater than or equal to 8 microns, for example, may be about 8 microns or 9 microns.
  • the auxiliary structure 233 may be located in the open area between the edge transparent conductive lines 231a and 231b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in a ring shape (eg, a rectangular ring).
  • the plurality of auxiliary blocks 2330 may be sequentially arranged along the second direction Y and close to the edge transparent conductive lines 231a and 231b.
  • the orthographic projection of a part of the auxiliary blocks 2330 on the base substrate of the auxiliary structure 233 may overlap with the orthographic projection of the shielding electrode 211 on the base substrate.
  • the orthographic projection of another part of the auxiliary blocks 2330 on the base substrate overlaps with the orthographic projection of the shielding electrode 211 on the substrate.
  • the orthographic projection of the substrate can have no overlap.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be arranged in a circular ring shape, an elliptical ring shape, or other shapes.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be substantially the same shape and size.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be a rectangle.
  • the length of the auxiliary block 2330 along the first direction X may be greater than or equal to 1 micron and less than or equal to 2 microns, and the length along the second direction Y may be greater than or equal to 1 micron and less than or equal to 2 microns.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be a square with a size of 1 micron ⁇ 1 micron, or a square with a size of 1 micron ⁇ 1 micron.
  • this embodiment is not limited to the shape of the auxiliary block.
  • the orthographic projection of the auxiliary block on the substrate may be a circle, an ellipse, a pentagon, a hexagon, or other shapes.
  • the auxiliary structure in this example may include multiple auxiliary blocks that are not electrically connected, and the size of the auxiliary blocks is not large, which can avoid affecting the signal transmission of the first transparent conductive line.
  • the distance H2 between adjacent auxiliary blocks 2330 in the first direction X and the distance H3 between adjacent auxiliary blocks 2330 in the second direction Y may be substantially the same.
  • H2 and H3 can be greater than or equal to 1 micron and less than or equal to 2 microns, such as about 1 micron or 1.5 microns.
  • the spacing between the auxiliary structure 233 and the adjacent edge transparent conductive line 231a may be substantially the same as the spacing between the auxiliary structure 233 and the adjacent edge transparent conductive line 231b.
  • the distance between the auxiliary structure 233 and the adjacent edge transparent conductive line 231 a is the distance H4 between the auxiliary block 2330 of the auxiliary structure 233 closest to the edge transparent conductive line 231 a and the edge transparent conductive line 231 a.
  • H4 can be greater than or equal to 2 microns and less than or equal to 3 microns, such as about 2 microns, or 2.5 microns, or 3 microns. However, this embodiment is not limited to this.
  • the exposure environment of the exposure process for preparing the transparent conductive layer can be improved (for example, reducing the amount of light in the first via hole). reflection, reducing the amount of exposure received by the first transparent conductive line), thus affecting the line width of the first transparent conductive line.
  • it can also improve the first transparent conductive layer due to the reflection focusing effect of the first conductive layer in the exposure process. Conductive wires are broken or thinned.
  • FIG. 8 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • the open area between the edge transparent conductive lines 231a and 231b is provided with an auxiliary structure 233.
  • the auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. Adjacent auxiliary blocks 2330 of the auxiliary structure 233 may be connected by connecting lines 2331. In this example, the connection lines 2331 may connect multiple auxiliary blocks 2330 in sequence along the rectangular ring.
  • FIG. 9 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. Adjacent auxiliary blocks 2330 of the auxiliary structure 233 may be connected by connecting lines 2331. In this example, the connection lines 2331 may connect multiple auxiliary blocks 2330 in sequence along the rectangular ring.
  • At least one auxiliary block 2330 that overlaps the front projection of the shielding electrode 211 of the first conductive layer on the base substrate can pass through the second via K2 opened in the first planar layer and the shielding electrode 211 Electrical connection.
  • the shielding electrode 211 may be electrically connected to the first power line located on the second conductive layer.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 can be electrically connected to the first power line through the connecting wires 2331 and the shielding electrodes 211 .
  • the impact of the floating connection of the auxiliary structure 233 on other signal lines can be improved.
  • FIG. 10 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. Multiple auxiliary blocks 2330 arranged along the width direction of the transparent conductive line may be connected through connecting lines 2331, and there is no connection between adjacent auxiliary blocks 2330 arranged along the length direction of the transparent conductive line.
  • auxiliary blocks 2330 of the auxiliary structure 233 can be divided into multiple groups according to the column direction.
  • Each group includes one row of auxiliary blocks 2330 (for example, includes two or three auxiliary blocks).
  • the auxiliary blocks 2330 in a group can be passed through The connection line 2331 is connected. There are no electrical connections between auxiliary blocks 2330 between adjacent groups.
  • the auxiliary blocks 2330 of each group may be electrically connected to the first power line, or may not be electrically connected.
  • this embodiment is not limited to this.
  • FIG. 11 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in a rectangular ring.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into two groups, wherein the first group may include a first row and a first column of auxiliary blocks 2330, and the second group may include a last row and a second column of auxiliary blocks 2330.
  • the auxiliary blocks 2330 in each group can be electrically connected through connection lines 2331. There can be no connection between the first group and the second group.
  • the auxiliary blocks 2330 of each group may be electrically connected to the first power line, or may not be electrically connected.
  • this embodiment is not limited to this.
  • FIG. 12 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring.
  • the orthographic projection of the shielding electrode 211 of the first conductive layer on the base substrate overlaps with the orthographic projection of the base substrate.
  • Multiple (for example, six) auxiliary blocks 2330 can pass through the second via hole opened in the first flat layer.
  • the shielding electrode 211 may be electrically connected to the first power line located on the second conductive layer.
  • a part of the auxiliary blocks 2330 of the auxiliary structure 233 may be electrically connected to the first power line through the shielding electrode 211, and the other part of the auxiliary blocks 2330 may not be electrically connected.
  • FIG. 13 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array.
  • the auxiliary block 2330 of this example may be a dead structure with no electrical connections.
  • the plurality of auxiliary blocks 2330 may be arranged in an array along the second direction Y and the first direction X.
  • the orthographic projection of a part of the auxiliary blocks 2330 of the auxiliary structure 233 on the base substrate may overlap with the orthographic projection of the shielding electrode 211 located on the first conductive layer on the base substrate, and the orthographic projection of another part of the auxiliary blocks 2330 on the base substrate overlaps
  • the orthographic projection of the shielding electrode 211 on the base substrate may not overlap.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be substantially the same shape and size.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be approximately rectangular. However, this embodiment is not limited to this. Regarding the rest of the structure of the display substrate of this embodiment, reference can be made to the description of the previous embodiment, so the details will not be described again.
  • FIG. 14 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. Adjacent auxiliary blocks 2330 may be connected through connection lines 2331. Multiple auxiliary blocks 2330 of the auxiliary structure 233 are connected to form a network structure.
  • At least one auxiliary block 2330 that overlaps the front projection of the base substrate and the front projection of the shielding electrode 211 on the base substrate can be electrically connected to the shielding electrode 211 through the second via hole K2 opened in the first planar layer.
  • the shielding electrode 211 is electrically connected to the first power line.
  • FIG. 15 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into multiple groups in the column direction, and each group may include one row of auxiliary blocks 2330.
  • the auxiliary blocks 2330 of each group can be connected through connection lines 2331.
  • Neighboring groups of auxiliary blocks 2330 may not be connected. At least one group of auxiliary blocks 2330 may be electrically connected to the first power line, or none of the plurality of groups of auxiliary blocks may be electrically connected to the first power line. This embodiment is not limited to this. Regarding the rest of the structure of the display substrate of this embodiment, reference can be made to the description of the previous embodiment, so the details will not be described again.
  • FIG. 16 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 16 only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array.
  • the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into three groups; the first group may include the plurality of auxiliary blocks 2330 of the first column and exclude the auxiliary blocks of the first and second rows from the bottom; the second group may include The plurality of auxiliary blocks 2330 in the second column and part of the auxiliary blocks in the second to last row do not include the auxiliary blocks in the third column and the first to last row; the third group may include the plurality of auxiliary blocks 2330 in the third column and the second to last row.
  • the auxiliary blocks of the first group can be connected to form a strip shape, and the auxiliary blocks of the second and third groups can be connected to form an L shape.
  • the auxiliary blocks in each group may be connected through connecting lines 2331, and the auxiliary blocks in adjacent groups may not be connected. At least one group of auxiliary blocks may be electrically connected to the first power line, or none of the plurality of groups of auxiliary blocks may be connected to the first power line.
  • FIG. 17 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • the open area between the edge transparent conductive lines 231a and 231b is provided with an auxiliary structure 233.
  • the auxiliary structure 233 may include two auxiliary blocks 2330 arranged in an annular shape.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be L-shaped.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may overlap with the orthographic projection of the shielding electrode 211 located on the first conductive layer on the base substrate.
  • the auxiliary block 2330 can be electrically connected to the shielding electrode 211 through at least one second via hole K2 opened in the first planar layer, thereby achieving electrical connection with the first power line. In other examples, the auxiliary block 2330 may not be electrically connected to the first power line.
  • FIG. 18 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231 a and 231 b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be strip-shaped.
  • the auxiliary block 2330 may have no electrical connection and may be an invalid structure; or, at least one auxiliary block 2330 may be electrically connected to the first power line.
  • FIG. 19 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b.
  • the auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged regularly.
  • the orthographic projection of the auxiliary block 2330 on the base substrate may be strip-shaped or L-shaped.
  • the auxiliary block 2330 may have no electrical connection and may be an inactive structure; or, at least one auxiliary block 2330 may be electrically connected to the first power line.
  • FIG. 20 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b.
  • the orthographic projection of the auxiliary structure 233 on the base substrate may be annular, such as a rectangular annular shape.
  • the auxiliary structure 233 may have no electrical connection and may be an inactive structure; or may be electrically connected to the first power line.
  • this embodiment is not limited to this.
  • the orthographic projection of the auxiliary structure 233 on the substrate may be a circular ring, an elliptical ring, or other shapes.
  • FIG. 21 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b.
  • the orthographic projection of the auxiliary structure 233 on the base substrate may be mesh-shaped.
  • the auxiliary structure 233 may have no electrical connection and may be an inactive structure; or may be electrically connected to the first power line.
  • this embodiment is not limited to this.
  • FIG. 22 is another schematic top view of a partial film layer of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 23 is a partial cross-sectional view along the P-P' direction in Figure 22.
  • a transparent conductive layer is used as an example.
  • the multiple film layer structures on the side of the second conductive layer close to the display substrate and the multiple film layers on the side of the transparent conductive layer away from the base substrate are omitted in FIGS. 22 and 23 .
  • the display substrate of the first display area A1 may include: a base substrate 10 , a base plate disposed on the base substrate 10
  • the pixel circuit layer (for example, including the second conductive layer 22 ), the first flat layer 31 and the transparent conductive layer 23 .
  • the transparent conductive layer 23 may include an auxiliary structure 233 located in an open area between the edge transparent conductive lines 231a and 231b. The orthographic projection of the auxiliary structure 233 on the base substrate may overlap with the orthographic projection of the pixel circuit of the pixel circuit layer on the base substrate.
  • the display substrate of this example may have a single source-drain metal layer structure, and the display substrate of the previous embodiment may have a double-source-drain metal layer structure.
  • the rest of the structure of the display substrate of this embodiment reference can be made to the description of the previous embodiment, so the details will not be described again.
  • the display substrate provided in this embodiment can improve the exposure environment of the exposure process for preparing the transparent conductive layer by arranging auxiliary structures in the open area outside the first transparent conductive line (for example, reducing the reflection of light in the first via hole, Reduce the amount of exposure received by the first transparent conductive line), thus affecting the line width of the edge transparent conductive line.
  • it can also improve the appearance of the first transparent conductive line due to the reflection focusing effect of the first conductive layer during the exposure process. Broken or thinned wires.
  • the auxiliary structure provided in the open area outside the first transparent conductive line may include multiple auxiliary blocks, and the multiple auxiliary blocks may be arranged in B-type, D-type, S-type, H-type, L-type, N type or M type and other graphics.
  • An orthographic projection of at least a part of the plurality of auxiliary blocks on the base substrate may overlap with an orthographic projection of the shielding electrode on the base substrate.
  • a transparent conductive layer may include multiple auxiliary structures as shown in FIG. 4 , or may include the auxiliary structures as shown in FIG. 4 and the auxiliary structures as shown in FIG. 13 .
  • this embodiment is not limited to this.
  • the following is an example of the film structure of the pixel circuit layer of the display substrate.
  • FIG. 24 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 25 is an operating timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this exemplary embodiment has a 7T1C structure. However, this embodiment is not limited to this.
  • the pixel circuit may be a 3T1C, 5T1C, 8T1C or 8T2C structure.
  • the pixel circuit of this example includes six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7.
  • the light-emitting element EL includes an anode, a cathode, and an organic light-emitting layer provided between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the drive transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switching transistors may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Polysilicon
  • oxide thin film transistors uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO).
  • LTPO low-temperature polycrystalline Oxide
  • the display substrate includes a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, a first two initial signal lines INIT2, a first reset control line RST1 and a second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide the scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide the data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide the light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide the light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit.
  • the first reset control line RST1 may be electrically connected to the scan line GL of the n-1-th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first The reset control signal RESET1(n) is the same as the scan signal SCAN(n-1).
  • the second reset control line RST2 may be electrically connected to the scan line GL of the n-th row pixel circuit to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n).
  • the second reset control line RST2 electrically connected to the nth row of pixel circuits and the first reset control line RST1 electrically connected to the n+1th row of pixel circuits have an integrated structure. In this way, the signal lines of the display substrate can be reduced and the narrow frame of the display substrate can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 is configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 is configured to provide a second initial signal to the pixel circuit.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the driving transistor T3 is electrically connected to the light-emitting element EL, and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS, etc.
  • a driving current is output to drive the light-emitting element EL to emit light.
  • the gate electrode of the data writing transistor T4 is electrically connected to the scan line GL
  • the first electrode of the data writing transistor T4 is electrically connected to the data line DL
  • the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan line GL
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3.
  • the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML.
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power line PL1.
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3.
  • the second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the anode of element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3.
  • the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the gate of the light-emitting element EL.
  • the anode is reset.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the gate is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the light-emitting element EL. anode electrical connection.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the drive transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, and the second node N2 is the connection point of the first light emission control transistor T5, the data writing transistor T4 and the threshold compensation transistor T2.
  • the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6.
  • the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting transistor T7. Connection point of component EL.
  • the working process of the pixel circuit illustrated in FIG. 24 will be described below with reference to FIG. 25 .
  • the pixel circuit shown in FIG. 24 includes a plurality of transistors that are all P-type transistors as an example for explanation.
  • the working process of the pixel circuit of the first structure includes: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first phase S1 is called the reset phase.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized and the original data voltage in the storage capacitor Cst is cleared.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, causing data to be written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, and the third light-emitting control transistor T5.
  • the two light-emitting control transistors T6 and the second reset transistor T7 are turned off. At this stage, the light-emitting element EL does not emit light.
  • the second stage S2 is called the data writing stage or threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light-emitting control signal EM provided by the light-emitting control line EML are both high-level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 is turned on.
  • the scan signal SCAN is a low-level signal, turning on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the third node N2 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst.
  • the voltage of the first electrode of the storage capacitor Cst (ie, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. , ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, causing the first reset transistor T1 to turn off.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the third stage S3 is called the luminous stage.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned-on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3
  • Vth is the driving transistor T3
  • the threshold voltage of , Vdata is the data voltage output by the data line DL
  • VDD is the first voltage signal output by the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 26 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 27 is a partial cross-sectional view along the R-R' direction in Figure 26.
  • the pixel circuit layer of the display substrate of the first display area may include: a semiconductor layer 110 , a first insulating layer 101 , which are sequentially disposed on the base substrate 10 .
  • a second flat layer 32 and a first conductive layer 21 are sequentially provided on the side of the second conductive layer 22 away from the base substrate 10 .
  • the first insulation layer 101, the second insulation layer 102, and the third insulation layer 103 may be inorganic insulation layers. However, this embodiment is not limited to this.
  • FIG. 28A is a schematic top view of the display substrate after forming the semiconductor layer in FIG. 26 .
  • FIG. 28B is a schematic top view of the display substrate after forming the first gate metal layer in FIG. 26 .
  • FIG. 28C is a schematic top view of the display substrate after forming the second gate metal layer in FIG. 26 .
  • FIG. 28D is a schematic top view of the display substrate after forming the third insulating layer in FIG. 26 .
  • FIG. 28E is a schematic top view of the display substrate after forming the second conductive layer in FIG. 26 .
  • the structure of the display substrate is explained below through an example of the preparation process of the display substrate.
  • the "patterning process" mentioned in the embodiments of this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials including processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the preparation process of the display substrate may include the following operations.
  • the substrate substrate 10 may be a rigid substrate, such as a glass substrate.
  • the base substrate 10 may be a flexible substrate.
  • a semiconductor film is deposited on the base substrate 10 of the first display area, and the semiconductor film is patterned through a patterning process to form the semiconductor layer 110 .
  • the semiconductor layer 110 may include: active layers of a plurality of transistors of the pixel circuit (for example, including: the active layer T10 of the first reset transistor T1 , the active layer T20 of the threshold compensation transistor T2 , The active layer T30 of the driving transistor T3, the active layer T40 of the data writing transistor T4, the active layer T50 of the first light emission control transistor T5, the active layer T60 of the second light emission control transistor T6, and the second reset transistor T7. Active layer T70).
  • the active layer of seven transistors of a pixel circuit may be an integral structure connected to each other.
  • the material of the semiconductor layer 110 may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the plurality of doped regions may be on both sides of the channel region and be doped with impurities and thus be conductive. Impurities can vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as the source or drain electrode of the transistor. Portions of the active layer between transistors can be interpreted as wiring doped with impurities that can be used to electrically connect the transistors.
  • the first gate metal layer 111 may include: gates of a plurality of transistors of the pixel circuit, a first plate Cst-1 of the storage capacitor Cst, a first reset control line RST1, a second Reset control line RST2, scanning line GL and light emission control line EML.
  • the first reset control line RST1 and the gate T11 of the first reset transistor T1 may have an integrated structure.
  • the scan line GL, the gate electrode T41 of the data writing transistor T4 and the gate electrode T21 of the threshold compensation transistor T2 may have an integrated structure.
  • the gate T31 of the driving transistor T3 and the first plate Cst-1 of the storage capacitor Cst may have an integrated structure.
  • the light emission control line EML, the gate electrode T51 of the first light emission control transistor T5 and the gate electrode T61 of the second light emission control transistor T61 may have an integrated structure.
  • the second reset control line RST2 and the gate T71 of the second reset transistor T7 may have an integrated structure.
  • a second insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a layer covering the first gate metal.
  • the second gate metal layer 112 may include: the second plate Cst-2 of the storage capacitor Cst of the pixel circuit, the shield electrode BK, the first initial signal line INIT1 and the second initial signal line INIT2 .
  • the shielding electrode BK is configured to shield the impact of the data voltage jump on the key nodes, prevent the data voltage jump from affecting the potential of the key nodes of the pixel circuit, and improve the display effect.
  • a third insulating film is deposited on the base substrate 10 forming the foregoing structure, and the third insulating layer 103 is formed through a patterning process.
  • the third insulating layer 103 has a plurality of pixel via holes.
  • a third metal film is deposited, and the third metal film is patterned through a patterning process to form the second conductive layer 22 disposed on the third insulating layer 103 of the first display area.
  • the third insulating layer 103 is provided with a plurality of pixel via holes, including, for example, the first pixel via hole V1 to the fifteenth pixel via hole V15.
  • the third insulating layer 103 , the second insulating layer 102 and the first insulating layer 101 in the first to eighth pixel vias V1 to V8 are removed, exposing the surface of the semiconductor layer 110 .
  • the third insulating layer 103 and the second insulating layer 102 in the ninth pixel via V9 are removed, exposing the surface of the first gate metal layer 111 .
  • the third insulating layer 103 in the tenth to fifteenth pixel via holes V10 to V15 is removed, exposing the surface of the second gate metal layer 112 .
  • the second conductive layer 22 may include: a data line DL, a first power line PL1 , and a plurality of connection electrodes (for example, a first anode connection electrode 220 , a first connection electrode 221 to a fifth connection electrode 220 ). Connect electrode 225).
  • the first anode connection electrode 220 may be electrically connected to the second doped region of the active layer T60 of the second light emission control transistor T6 through the fifth pixel via V5.
  • the first connection electrode 221 may be electrically connected to the first doping region of the active layer T10 of the first reset transistor T1 through the first pixel via V1, and may also be electrically connected to the first initial signal line INIT1 through the tenth pixel via V10.
  • the second connection electrode 222 can be electrically connected to the first doping region of the active layer of the second reset transistor of the pixel circuit in the previous row through the eighth pixel via V18, and can also be electrically connected to the second initial doping region through the eleventh pixel via V11.
  • the signal line INIT2 is electrically connected.
  • the third connection electrode 223 can be electrically connected to the gate T31 of the driving transistor T3 through the ninth pixel via V9, and can also be electrically connected to the first doped region of the active layer T20 of the threshold compensation transistor T2 through the second pixel via V2. connect.
  • the fourth connection electrode 224 can be electrically connected to the first doped region of the active layer of the first reset transistor of the next row of pixel circuits through the seventh pixel via V7, and can also be electrically connected to another first doped region through the fourteenth via V14.
  • the initial signal line INIT1 is electrically connected.
  • the fifth connection electrode 225 can be electrically connected to the first doped region of the active layer T70 of the second reset transistor T7 through the sixth pixel via V6, and can also be connected to another second initial signal through the fifteenth pixel via V15.
  • Line INIT2 is electrically connected.
  • the data line DL may be electrically connected to the first doped region of the active layer T40 of the data writing transistor T4 through the third pixel via V3.
  • the first power line PL1 may be electrically connected to the shield electrode BK through the twelfth pixel via V12, and may also be electrically connected to the first doped region of the active layer T50 of the first light emission control transistor T5 through the fourth pixel via V4. , and can also be electrically connected to the second plate Cst-2 of the storage capacitor Cst through the two thirteenth pixel vias V13 arranged vertically.
  • the second display area A2 may include a base substrate 10 and a first insulating layer 101 , a second insulating layer 102 and a third insulating layer 103 stacked on the base substrate 10 .
  • a first flat film is coated on the base substrate 10 forming the foregoing structure, and the second flat layer 32 is formed through a patterning process. Subsequently, a fourth metal film is deposited, and the fourth metal film is patterned through a patterning process to form the first conductive layer 21 disposed on the second flat layer 32 of the first display area. As shown in FIGS. 26 and 27 , the second flat layer 32 may be provided with a plurality of via holes, such as first via holes K1a and K1b. The second flat layer 32 in the first via holes K1a and K1b is removed, exposing the surface of the second conductive layer 22.
  • the first conductive layer 21 may include: a shielding electrode 211 and a second anode connection electrode 210 .
  • the shielding electrode 211 may be electrically connected to the first power line PL1 through the first via hole K1a.
  • the second anode connection electrode 210 may be electrically connected to the first anode connection electrode 220 through the first via hole K1a.
  • the shielding electrode 211 may have an irregular shape to be configured to cover the first node N1 and reduce the crosstalk of the transparent conductive layer to the first node N1.
  • this embodiment is not limited to this.
  • the shielding electrode 211 may be a circle or a regular shape such as a pentagon or a hexagon.
  • a second flat film is coated on the base substrate 10 forming the foregoing structure, and the first flat layer 31 is formed through a patterning process. Subsequently, a transparent conductive film is deposited, and the transparent conductive film is patterned through a patterning process to form a transparent conductive layer disposed on the first flat layer 31 , as shown in FIGS. 4 and 5 .
  • a third flat film is coated on the base substrate forming the foregoing structure, and a third flat layer is formed through a patterning process.
  • an anode conductive film is deposited, and the anode conductive film is patterned through a patterning process to form an anode layer disposed on the third flat layer.
  • a pixel definition film is coated on the substrate with the aforementioned pattern formed, and a pixel definition layer (PDL, Pixel Define Layer) is formed through masking, exposure and development processes.
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer.
  • An organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern.
  • the cathode is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first gate metal layer, the second gate metal layer, the first conductive layer, and the second conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and Any one or more of molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo /Cu/Mo etc.
  • the transparent conductive layer may be made of transparent conductive material, such as indium tin oxide (ITO).
  • the first insulating layer, the second insulating layer and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer. , multi-layer or composite layer.
  • the first to fifth flat layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode can be made of transparent conductive materials. However, this embodiment is not limited to this.
  • the structure of the display substrate and its preparation process in this embodiment are only illustrative. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, multiple transparent conductive layers may be provided, such as forming another transparent conductive layer on a side of the first flat layer away from the base substrate, and then forming a third flat layer and an anode layer. However, this embodiment is not limited to this.
  • each transparent conductive layer may be provided with an auxiliary structure adjacent to the edge transparent conductive line to improve the exposure environment of the exposure process for preparing each transparent conductive layer ( For example, reducing the reflection of light in the first via hole reduces the amount of exposure received by the first transparent conductive line), thereby affecting the line width of the transparent conductive line, and can also improve the effect of the first conductive layer during the exposure process.
  • the transparent conductive wire is broken or thinned due to the reflection focusing effect.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • This embodiment also provides a method for preparing a display substrate, including: forming a pixel circuit layer on a base substrate, the pixel circuit layer including a plurality of pixel circuits, the plurality of pixel circuits including a plurality of first pixel circuits; A first flat layer is formed on the side of the circuit layer away from the base substrate; at least one transparent conductive layer is formed on the side of the first flat layer away from the base substrate; and a plurality of transparent conductive layers are formed on the side of the transparent conductive layer away from the base substrate. a first light-emitting element.
  • the base substrate includes a first display area and a second display area, the first display area at least partially surrounding the second display area.
  • a plurality of first light-emitting elements are located in the second display area.
  • the first flat layer is located in the first display area and the second display area.
  • the transparent conductive layer includes: a plurality of first transparent conductive lines and at least one auxiliary structure.
  • the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines.
  • An orthographic projection of the auxiliary structure on the base substrate overlaps with an orthographic projection of at least one of the plurality of pixel circuits on the base substrate.
  • At least one embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • FIG. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 29 , this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light-emitting side of the display structure layer away from the display substrate 91 . The orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the second display area A2.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板（91），包括：衬底基板（10）、像素电路层、第一平坦层（31）、至少一个透明导电层（23）和多个第一发光元件（13）。衬底基板（10）包括第一显示区（A1）和第二显示区（A2），第一显示区（A1）至少部分围绕第二显示区（A2）。像素电路层位于第一显示区（A1），包括多个像素电路，多个像素电路包括多个第一像素电路（11）。多个第一发光元件（13）位于第二显示区（A2）。第一平坦层（31）位于像素电路层远离衬底基板（10）的一侧，且位于第一显示区（A1）和第二显示区（A2）。透明导电层（23）位于第一平坦层（31）远离衬底基板（10）的一侧，且包括多条第一透明导电线和至少一个辅助结构（233）。多个第一发光元件（13）和多个第一像素电路（11）通过多条第一透明导电线耦接。辅助结构（233）在衬底基板（10）的正投影与至少一个像素电路在衬底基板（10）的正投影存在交叠。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、像素电路层、第一平坦层、至少一个透明导电层以及多个第一发光元件。衬底基板包括第一显示区和第二显示区，其中，所述第一显示区至少部分围绕所述第二显示区。像素电路层位于所述第一显示区，所述像素电路层包括多个像素电路，所述多个像素电路包括多个第一像素电路。多个第一发光元件位于所述第二显示区。第一平坦层位于所述像素电路层远离所述衬底基板一侧，且位于所述第一显示区和所述第二显示区。至少一个透明导电层位于所述第一平坦层远离所述衬底基板的一侧。其中，所述透明导电层包括：多条第一透明导电线和至少一个辅助结构，所述多个第一发光元件和所述多个第一像素电路通过所述多条第一透明导电线耦接。所述辅助结构在所述衬底基板的正投影与所述多个像素电路中的至少一个像素电路在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，显示基板还包括：位于所述像素电路层和所 述第一平坦层之间的第一导电层，所述第一导电层包括：至少一个遮挡电极，所述遮挡电极与所述多个像素电路中的至少一个像素电路电连接，所述辅助结构在所述衬底基板的正投影与所述遮挡电极在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述像素电路层包括：第二导电层，所述第二导电层包括第一电源线，所述遮挡电极与所述第一电源线电连接。
在一些示例性实施方式中，所述辅助结构与所述遮挡电极电连接。
在一些示例性实施方式中，所述像素电路至少包括：驱动晶体管、阈值补偿晶体管和第一复位晶体管，所述驱动晶体管、所述阈值补偿晶体管和第一复位晶体管均与第一节点电连接；所述遮挡电极在所述衬底基板的正投影被配置为覆盖所述像素电路的第一节点在所述衬底基板的正投影。
在一些示例性实施方式中，所述遮挡电极在所述衬底基板的正投影为非规则形状。
在一些示例性实施方式中，所述第一导电层与所述第二导电层之间设置有第二平坦层，所述第一导电层通过贯穿所述第二平坦层的第一过孔与所述第二导电层电连接；所述多条第一透明导电线中的至少一条第一透明导电线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述第一透明导电线包括边缘透明导电线，所述边缘透明导电线与所述辅助结构相邻。
在一些示例性实施方式中，所述辅助结构位于两条所述边缘透明导电线之间。
在一些示例性实施方式中，所述辅助结构与相邻的所述边缘透明导电线之间的间距大于或等于2微米且小于或等于3微米。
在一些示例性实施方式中，所述至少一个辅助结构包括：规则排布的多个辅助块。
在一些示例性实施方式中，所述辅助结构的多个辅助块阵列排布，且所述多个辅助块的形状和尺寸大致相同。
在一些示例性实施方式中，所述多个辅助块在所述衬底基板的正投影为 矩形。
在一些示例性实施方式中，所述辅助结构的多个辅助块呈环形排布。
在一些示例性实施方式中，所述辅助结构的至少一个辅助块与第一电源线电连接。
在一些示例性实施方式中，所述辅助结构的至少两个相邻的辅助块通过连接线连接。
在一些示例性实施方式中，所述辅助结构的多个辅助块被划分为多组，每组包括至少两个辅助块，一组内的辅助块通过连接线连接。
在一些示例性实施方式中，所述至少一个辅助结构在所述衬底基板的正投影为环状或网状。
在一些示例性实施方式中，所述多个像素电路还包括：位于所述第一显示区的多个第二像素电路；所述显示基板还包括：位于所述第一显示区的多个第二发光元件；所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，所述至少一个第二像素电路配置为驱动所述至少一个第二发光元件。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的制备示意图；
图2为本公开至少一实施例的显示基板的示意图；
图3为本公开至少一实施例的显示基板的局部示意图；
图4为本公开至少一实施例的显示基板的局部膜层的俯视示意图；
图5为图4中沿P-P’方向的局部剖面示意图；
图6为图4中形成第二导电层后的显示基板的局部俯视示意图；
图7为图4中形成透明导电层后的显示基板的局部俯视示意图；
图8为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图9为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图10为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图11为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图12为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图13为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图14为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图15为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图16为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图17为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图18为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图19为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图20为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图21为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图22为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图；
图23为图22中沿P-P’方向的局部剖面示意图；
图24为本公开至少一实施例的像素电路的等效电路图；
图25为本公开至少一实施例的像素电路的工作时序图；
图26为本公开至少一实施例的像素电路的俯视示意图；
图27为图26中沿R-R’方向的局部剖面示意图；
图28A为图26中形成半导体层后的显示基板的俯视示意图；
图28B为图26中形成第一栅金属层后的显示基板的俯视示意图；
图28C为图26中形成第二栅金属层后的显示基板的俯视示意图；
图28D为图26中形成第三绝缘层后的显示基板的俯视示意图；
图28E为图26中形成第二导电层后的显示基板的俯视示意图；
图29为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地 连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”、“耦接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
本公开中，“线长”表示沿走线延伸方向的长度，“线宽”表示在走线所在平面内，在与走线延伸方向交叉的方向(例如，延伸方向的垂直方向) 上的长度。
在一些实现方式中，显示基板可以包括：屏下摄像头区域和位于屏下摄像头区域周边的正常显示区域。屏下摄像头区域可以仅保留发光元件，而将驱动屏下摄像头区域的发光元件的像素电路设置在正常显示区域，并通过设置在透明导电层的透明导电线电连接屏下摄像头区域的发光元件和正常显示区域的像素电路。然而，由于透明导电线层的边缘透明导电线的周边环境较为空旷，在曝光工艺中，容易受到较多的曝光量，从而容易造成边缘透明导电线的线宽变细。其中，边缘透明导电线可以指在线宽方向的至少一侧具有空旷区域的透明导电线。空旷区域沿着透明导电线的线宽方向的长度可以大于或等于8微米。即，边缘透明导电线在线宽方向上的至少一侧与相邻走线之间的间距可以大于或等于8微米。例如，边缘透明导电线的一侧可以设置有相邻的透明导电线，且与相邻透明导电线之间的间距可以约为2微米至3微米，比如2.5微米；边缘透明导电线的另一侧可以具有空旷区域。又如，边缘透明导电线在线宽方向上的相对两侧均具有空旷区域。
另外，在一些实现方式中，还存在由于导电层在曝光工艺中的反射聚焦作用导致透明导电线的线宽变细或者断线的情况。图1为一种显示基板的制备示意图。在一些实现方式中，显示基板可以包括：衬底基板1、以及设置在衬底基板1上的第二导电层2、第二平坦层3、第一导电层4、第一平坦层5和透明导电层。图1所示为透明导电层的制备过程中曝光工艺的原理示意图。在一些实现方式中，透明导电层的制备过程包括：在第一平坦层5上形成透明导电薄膜6，在透明导电薄膜6上形成光刻胶薄膜7，以掩膜版为掩膜对光刻胶薄膜7进行曝光，从而使得光刻胶薄膜形成光刻胶保留部和光刻胶待去除部，曝光工艺后进行显影工艺，在显影工艺中，将光刻胶待去除部去除，形成光刻胶图形。以光刻胶图形为掩膜对透明导电薄膜6进行刻蚀，形成透明导电层。然而，如图1所示，第一导电层4可以通过过孔与第二导电层2搭接，第一导电层4在过孔中的搭接结构可以形成类似于碗状的内凹部。该内凹部的开口方向背离衬底基板1。在光线照射下，该内凹部可以形成类似于凹面镜的聚焦效果。在曝光工艺中，金属材料的第一导电层4会反射光线并聚光至位于第一导电层4的内凹部上方的光刻胶保留部，使得这部分光 刻胶被曝光或者部分曝光，显影后被洗去，从而以光刻胶图形为掩膜刻蚀透明导电薄膜后形成的透明导电线容易出现断线或变细。因此，在第二平坦层3的过孔位置，由于第一导电层4在曝光工艺中的反射聚焦作用，会造成过孔位置的光刻胶薄膜变薄，从而导致最终形成的透明导电线出现断线或变细，造成显示暗点。
本实施例提供一种显示基板，包括：衬底基板、像素电路层、第一平坦层、至少一个透明导电层以及多个第一发光元件。衬底基板包括第一显示区和第二显示区，第一显示区至少部分围绕第二显示区。像素电路层位于第一显示区，包括多个像素电路，多个像素电路包括多个第一像素电路。多个第一发光元件位于第二显示区。第一平坦层位于像素电路层远离衬底基板的一侧，且位于第一显示区和第二显示区。至少一个透明导电层位于第一平坦层远离衬底基板的一侧。透明导电层包括：多条第一透明导电线和至少一个辅助结构。多个第一发光元件和多个第一像素电路通过多条第一透明导电线耦接。辅助结构在衬底基板的正投影与至少一个像素电路在衬底基板的正投影存在交叠。
本实施例提供的显示基板，通过在透明导电层设置辅助结构，可以改善透明导电层的曝光工艺的曝光环境，从而改善透明导电层的第一透明导电线出现断线或线宽变细的情况。
在一些示例性实施方式中，显示基板还可以包括：位于像素电路层和第一平坦层之间的第一导电层。第一导电层可以包括：至少一个遮挡电极，遮挡电极可以与至少一个像素电路电连接。辅助结构在衬底基板的正投影与遮挡电极在衬底基板的正投影可以存在交叠。本示例可以通过辅助结构，改善由于遮挡电极在曝光工艺中的反射聚焦作用导致的透明导电线出现断线或线宽变细的情况，从而提升显示基板的良率。
在一些示例性实施方式中，像素电路层可以包括：第二导电层，第二导电层可以包括第一电源线。遮挡电极可以与第一电源线电连接。在一些示例中，辅助结构可以与遮挡电极电连接。其中，辅助结构可以通过遮挡电极与第一电源线电连接。然而，本实施例对此并不限定。例如，辅助结构可以直 接连接第一电源线，或者，辅助结构可以连接其他传输直流电信号的信号线，或者，辅助结构可以没有电性连接。
在一些示例性实施方式中，像素电路可以至少包括驱动晶体管、阈值补偿晶体管和第一复位晶体管。驱动晶体管、阈值补偿晶体管和第一复位晶体管均与第一节点电连接。遮挡电极在衬底基板的正投影可以被配置为覆盖显示基板的像素电路的第一节点在衬底基板的正投影。在一些示例中，遮挡电极在衬底基板的正投影可以为非规则形状。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一导电层与第二导电层之间可以设置有第二平坦层，第一导电层可以通过贯穿第二平坦层的第一过孔与第二导电层电连接。多条第一透明导电线中的至少一条第一透明导电线在衬底基板的正投影可以与第一过孔在衬底基板的正投影存在交叠。
在一些示例性实施方式中，第一透明导电线可以包括边缘透明导电线，边缘透明导电线可以与辅助结构相邻。在本示例中，通过设置与边缘透明导电线相邻的辅助结构，可以减少边缘透明导电线在制备过程中接受过多的曝光量，改善边缘透明导电线出现断线或线宽变细的情况，从而提升显示基板的良率。
在一些示例性实施方式中，辅助结构可以位于两条边缘透明导电线之间。例如，辅助结构可以位于两条边缘透明导电线之间，从而改善边缘透明导电线出现断线或线宽变细的情况，并提升良率。
在一些示例性实施方式中，辅助结构与相邻的边缘透明导电线之间的间距可以大于或等于2微米且小于或等于3微米。比如，辅助结构与相邻的边缘透明导电线之间的间距可以约为2.5微米。
在一些示例性实施方式中，至少一个辅助结构可以包括：规则排布的多个辅助块。在一些示例中，辅助结构的多个辅助块可以阵列排布，且多个辅助块的形状和尺寸可以大致相同。例如，多个辅助块在衬底基板的正投影可以为矩形。在另一些示例中，辅助结构的多个辅助块可以呈环形排布，例如可以呈矩形环排布。例如，多个辅助块在衬底基板的正投影可以为矩形或L型。然而，本实施例对此并不限定。例如，辅助块在衬底基板的正投影可以为圆形、椭圆形、四边形、五边形或六边形等其他形状。
在一些示例性实施方式中，辅助结构的至少一个辅助块可以与第一电源线电连接。例如，至少一个辅助块可以通过遮挡电极与第一电源线电连接。
在一些示例性实施方式中，辅助结构的至少两个相邻的辅助块可以通过连接线连接。在一些示例中，辅助结构的多个辅助块可以被划分为多组，每组可以包括至少两个辅助块，一组内的辅助块可以通过连接线连接。其中，通过连接线连接的多个辅助块可以与第一电源线电连接，或者，通过连接线连接的多个辅助块可以不与其他信号线电连接。
在一些示例性实施方式中，至少一个辅助结构在衬底基板的正投影可以为环状或网状。在本示例中，一个辅助结构可以为一体结构。辅助结构可以与第一电源线电连接，或者可以没有电性连接关系。然而，本实施例对此并不限定。
下面通过一些示例对本实施例的方案进行举例说明。下面以显示基板为适用于全面屏和屏下摄像技术的显示基板为例进行说明。然而，本实施例对此并不限定。
图2为本公开至少一实施例的显示基板的示意图。图3为本公开至少一实施例的显示基板的局部示意图。在一些示例性实施方式中，如图2和图3所示，显示基板可以包括：显示区域AA和周边区域BB。周边区域BB为非显示区域。显示区域AA可以包括：第一显示区A1和第二显示区A2。例如，感光传感器(例如，摄像头)等硬件设置在显示基板的一侧，且感光传感器在显示基板的正投影与第二显示区A2交叠。第二显示区A2可以为透光显示区，还可以称为屏下摄像头(UDC，Under Display Camera)区域；第一显示区A1可以为正常显示区。例如，第一显示区A1不透光仅用于显示。本实施例的显示基板可以给真全面屏的实现奠定坚实的基础。
在一些示例性实施方式中，如图2所示，显示区域AA可以为矩形，例如圆角矩形。第二显示区A2可以为矩形，例如圆角矩形。然而，本实施例对此并不限定。例如，第二显示区A2可以为圆形、其他四边形或五边形等形状。
在一些示例性实施方式中，如图2所示，显示基板可以包括：衬底基板以及位于衬底基板上的多个子像素。多个子像素包括：多个第一子像素和多 个第二子像素。至少一个第一子像素包括第一像素电路11和第一发光元件13，至少一个第二子像素包括第二像素电路12和第二发光元件14。第二像素电路12和第二发光元件14均位于第一显示区A1，第一像素电路11位于第一显示区A1，第一发光元件13位于第二显示区A2。多个第一像素电路11可以间隔分布在多个第二像素电路12之间。例如，第二像素电路12可以称为原位像素电路，第一像素电路11可以称为非原位像素电路。在第二显示区A2内，相邻第一发光元件13之间为透光子区，第一发光元件13所在区域为显示子区。在第二显示区A2不设置像素电路，第二显示区A2仅设置发光元件，而将驱动第二显示区A2的发光元件的像素电路设置在第一显示区A1，即通过发光元件和像素电路分离设置的方式可以提高第二显示区A2的光透过率。
在一些示例性实施方式中，子像素的发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，多个第二像素电路12中的至少一个第二像素电路12可以与多个第二发光元件14中的至少一个第二发光元件14电连接，且至少一个第二像素电路12在衬底基板的正投影与至少一个第二发光元件14在衬底基板的正投影至少部分重叠。至少一个第二像素电路12可以配置为给所电连接的第二发光元件14提供驱动信号，以驱动第二发光元件14发光。
图2以驱动第一发光元件13发光的第一像素电路11位于第一显示区A1为例，该情况下的显示基板可以采用像素电路压缩方案，在像素电路压缩方案中，减小像素电路在第一方向X上的尺寸，从而可以在第一方向X上放置第一像素电路11和第二像素电路12，可以将第一像素电路11分散布置在第二像素电路12中。例如，第一方向X为行方向，在同一行像素电路中，第一像素电路11可以间隔布置在第二像素电路12中。然而，本实施例对此并不限定。例如，第一像素电路11可以位于周边区域，从而形成像素电路外置 方案。
在一些示例性实施方式中，如图2所示，第一显示区A1可以位于第二显示区A2的至少一侧。例如，第一显示区A1可以围绕第二显示区A2。即，第二显示区A2可以被第一显示区A1包围。在另一些示例中，第二显示区A2可以设置在其他位置，例如，可以位于衬底基板的顶部中间位置，或者，位于衬底基板的左上角位置或右上角位置处。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2和图3所示，多个第一像素电路11中的至少一个第一像素电路11与多个第一发光元件13中的至少一个第一发光元件13可以通过透明导电线L电连接。透明导电线L的一端与第一像素电路11电连接，另一端与第一发光元件13电连接。透明导电线L可以从第一显示区A1延伸至第二显示区A2。例如，透明导电线L可以沿第一方向X从第一显示区A1延伸至第二显示区A2；或者，透明导电线L可以先在第一显示区A1沿第二方向Y延伸，再沿第一方向X延伸至第二显示区A2。然而，本实施例对此并不限定。
在一些示例性实施方式中，透明导电线L可以采用透明导电材料，例如，可以采用导电氧化物材料，比如，氧化铟锡(ITO)。然而，本实施例对此并不限定。在一些示例中，透明导电线L可以排布在一个透明导电层中，或者，多个透明导电线L可以排布在两个或三个透明导电层中。每一条透明导电线L可以连接一个第一像素电路11和一个第一发光元件13。或者，一个第一像素电路11和一个第一发光元件13可以通过位于不同透明导电层的多条透明导电线L依次连接来实现电连接。
在一些示例性实施方式中，至少一个第一像素电路11可以配置为给所电连接的至少一个第一发光元件13提供驱动信号，以驱动第一发光元件13发光。第一像素电路11和第一发光元件13位于不同区域，第一像素电路11在衬底基板的正投影与至少一个第一发光元件13在衬底基板的正投影可以不存在交叠。如图2所示，第一发光元件13和与其电连接的第一像素电路11可以位于同一行。即，第一发光元件13的驱动信号来自于同一行的第一像素电路11。例如，同一行子像素的像素电路与同一条栅线电连接。然而，本实施例对此并不限定。例如，第一发光元件和与其电连接的第一像素电路 可以不位于同一行。
图4为本公开至少一实施例的显示基板的局部膜层的俯视示意图。图4可以为图3中区域S的局部放大示意图。图5为图4中沿P-P’方向的局部剖面示意图。在本示例中，以一个透明导电层为例进行示意。然而，本实施例对此并不限定。例如，显示基板可以包括多个透明导电层。图4和图5中省略示意了第二导电层靠近显示基板一侧的多个膜层结构以及透明导电层远离衬底基板一侧的多个膜层。
在一些示例性实施方式中，如图4和图5所示，在垂直于显示基板的方向上，第一显示区A1的显示基板可以包括：衬底基板10、设置在衬底基板10上的像素电路层(例如包括第二导电层22)、第二平坦层32、第一导电层21、第一平坦层31以及透明导电层23。在透明导电层23远离衬底基板10一侧还可以设置有第三平坦层、阳极层、像素定义层、有机发光层和阴极层。在一些示例中，像素电路层可以包括：依次设置在衬底基板10上的半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层和第二导电层。在一些示例中，第二导电层22还可以称为第一源漏金属层，第一导电层21还可以称为第二源漏金属层。第一平坦层31和第二平坦层32可以为有机材料层。然而，本实施例对此并不限定。
图6为图4中形成第一导电层后的显示基板的局部俯视示意图。在图6中示意了第一导电层21和第二导电层22。图7为图4中形成透明导电层后的显示基板的局部俯视示意图。图7中示意了第一导电层21和透明导电层23。
在一些示例性实施方式中，如图4至图7所示，第二导电层22至少可以包括：多条数据线(例如，数据线DL)、多条第一电源线(例如，第一电源线PL1)以及多个连接电极(例如包括第一阳极连接电极220)。数据线DL和第一电源线PL1可以沿第二方向Y延伸，且数据线DL和第一电源线PL1在第一方向X上相邻。第一方向X与第二方向Y交叉，例如第一方向X与第二方向Y相互垂直。
在一些示例性实施方式中，如图4至图7所示，第一导电层21至少可以包括：多个遮挡电极211、多个连接电极(例如包括第二阳极连接电极210)。 第二阳极连接电极210可以通过第二平坦层32上开设的第一过孔K1b与第一阳极连接电极220电连接。遮挡电极211可以通过第二平坦层32上开设的第一过孔K1a与第一电源线PL1电连接。
在一些示例中，如图4至图7所示，透明导电层23至少可以包括：多条第一透明导电线(例如，边缘透明导电线231a和231b、非边缘透明导电线232)、以及辅助结构233。其中，边缘透明导电线231a和231b在走线宽度方向上的一侧具有空旷区域，边缘透明导电线231a在衬底基板的正投影与第一过孔K1a在衬底基板的正投影可以存在交叠。非边缘透明导电线232在走线宽度方向上的两侧均具有相邻的走线。例如，非边缘透明导电线232可以位于边缘透明导电线231a和231b之间。边缘透明导电线231a的一侧可以与非边缘透明导电线232相邻，另一侧的空旷区域内可以设置辅助结构233。辅助结构233可以位于边缘透明导线231a和231b之间。本示例的辅助结构233可以没有电性连接，为无效(Dummy)结构。
在一些示例中，如图7所示，边缘透明导电线231a和231b以及非边缘透明导电线232可以均沿第二方向Y延伸。边缘透明导电线和非边缘透明导电线的线宽可以大致相同，例如可以约为2.0微米至2.5微米，比如可以约为2.3微米。然而，本实施例对此并不限定。例如，边缘透明导电线的线宽可以大于非边缘透明导电线的线宽。
在一些示例中，如图7所示，非边缘透明导电线232和相邻的透明导电线在第一方向X上的间距可以大致相同，例如可以约为2.0微米至2.5微米，比如可以约为2.2微米。边缘透明导电线231a和231b之间的空旷区域在第一方向X上的长度H1可以大于或等于8微米，例如可以约为8微米或9微米。
在一些示例中，如图7所示，辅助结构233可以位于边缘透明导电线231a和231b之间的空旷区域内。辅助结构233可以包括呈环形(例如矩形环)排布的多个辅助块2330。多个辅助块2330可以沿第二方向Y并靠近边缘透明导电线231a和231b依次排布。辅助结构233的一部分辅助块2330在衬底基板的正投影与遮挡电极211在衬底基板的正投影可以存在交叠，另一部分辅助块2330在衬底基板的正投影与遮挡电极211在衬底基板的正投影可以没有 交叠。在另一些示例中，辅助结构233的多个辅助块2330可以呈圆环形，椭圆环形等其他形状排布。
在一些示例中，如图7所示，辅助结构233的多个辅助块2330的形状和尺寸可以大致相同。辅助块2330在衬底基板的正投影可以为矩形。辅助块2330沿第一方向X的长度可以为大于或等于1微米且小于或等于2微米，沿第二方向Y的长度可以大于或等于1微米且小于或等于2微米。例如，辅助块2330在衬底基板的正投影可以为1微米×1微米尺寸的正方形，或者1微米×1微米尺寸的正方形。然而，本实施例对于辅助块的形状并不限定。例如，辅助块在衬底基板的正投影可以为圆形、椭圆形、五边形、六边形等其他形状。本示例的辅助结构可以包括多个没有电性连接的辅助块，且辅助块的尺寸不大，可以避免对第一透明导电线的信号传输产生影响。
在一些示例中，如图7所示，相邻辅助块2330在第一方向X上的间距H2与相邻辅助块2330在第二方向Y上的间距H3可以大致相同。例如，H2和H3可以大于或等于1微米且小于或等于2微米，例如可以约为1微米或1.5微米。辅助结构233和相邻的边缘透明导电线231a之间的间距可以与辅助结构233和相邻的边缘透明导电线231b之间的间距大致相同。在图7中，辅助结构233与相邻的边缘透明导电线231a之间的间距即为辅助结构233的最靠近边缘透明导电线231a的辅助块2330与边缘透明导电线231a之间的距离H4。在一些示例中，H4可以大于或等于2微米且小于或等于3微米，比如可以约为2微米，或者2.5微米，或者3微米。然而，本实施例对此并不限定。
在本示例中，通过在第一透明导电线外侧的空旷区域内设置环形排布的多个辅助块，可以改善制备透明导电层的曝光工艺的曝光环境(比如，减少光在第一过孔内进行反射，减少第一透明导电线接受的曝光量)，从而对第一透明导电线的线宽产生影响，另外还可以改善由于第一导电层在曝光工艺中的反射聚焦作用而导致第一透明导电线出现断线或变细的情况。
图8为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图8中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图8所示，边缘透明导电线231a和231b之间的空旷区域设置有辅 助结构233。辅助结构233包括呈矩形环排布的多个辅助块2330。辅助结构233的相邻辅助块2330可以通过连接线2331连接。在本示例中，连接线2331可以沿着矩形环依次连接多个辅助块2330。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图9为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图9中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图9所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233包括呈矩形环排布的多个辅助块2330。辅助结构233的相邻辅助块2330可以通过连接线2331连接。在本示例中，连接线2331可以沿着矩形环依次连接多个辅助块2330。在衬底基板上的正投影与第一导电层的遮挡电极211在衬底基板的正投影存在交叠的至少一个辅助块2330可以通过第一平坦层开设的第二过孔K2与遮挡电极211电连接。遮挡电极211可以与位于第二导电层的第一电源线电连接。辅助结构233的多个辅助块2330可以通过连接线2331和遮挡电极211实现与第一电源线电连接。本示例，通过将辅助结构233与第一电源线电连接，可以改善由于辅助结构233浮接对其他信号走线产生的影响。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图10为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图10中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图10所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233包括呈矩形环排布的多个辅助块2330。沿透明导电线的宽度方向上排布的多个辅助块2330可以通过连接线2331连接，沿透明导电线的长度方向上排布的相邻辅助块2330之间没有连接。例如，辅助结构233的多个辅助块2330按照列方向可以被划分为多个组，每组包括一行辅助块2330(例如包括两个或三个辅助块)，一组内的辅助块2330可以通过连接线2331连接。相邻组之间的辅助块2330没有电连接。在本示例中，每组的辅助块2330可以与第一电源线电连接，或者可以没有电性连接。然而，本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图11为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图11中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图11所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括呈矩形环排布的多个辅助块2330。例如，辅助结构233的多个辅助块2330可以被划分为两组，其中，第一组可以包括第一行和第一列辅助块2330，第二组可以包括最后一行和第二列辅助块2330，每组内的辅助块2330可以通过连接线2331电连接。第一组和第二组之间可以没有连接。在本示例中，每组的辅助块2330可以与第一电源线电连接，或者可以没有电性连接。然而，本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图12为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图12中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图12所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233包括呈矩形环排布的多个辅助块2330。在衬底基板上的正投影与第一导电层的遮挡电极211在衬底基板的正投影存在交叠的多个(例如六个)辅助块2330可以通过第一平坦层开设的第二过孔K2与遮挡电极211电连接。遮挡电极211可以与位于第二导电层的第一电源线电连接。辅助结构233的一部分辅助块2330可以通过遮挡电极211实现与第一电源线电连接，另一部分辅助块2330可以没有电性连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图13为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图13中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图13所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括呈阵列排布的多个辅助块2330。本示例的辅助块2330可以为没有电连接的无效结构。多个辅助块2330可以沿第二方向Y和第一方向X阵列排布。辅助结构233的一部分辅助块2330在衬底基板的正投影与位于第一导电层的遮挡电极211在衬底基板的正投影可以存在交叠，另一部分辅助块2330在衬底基板的正投影与遮挡电极211在衬底基板的正投影可以没有交叠。辅助结构233的多个辅助块2330的形状和尺寸可 以大致相同。辅助块2330在衬底基板的正投影可以大致为矩形。然而，本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图14为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图14中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图14所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括阵列排布的多个辅助块2330。相邻辅助块2330之间可以通过连接线2331连接。辅助结构233的多个辅助块2330连接形成网状结构。在衬底基板的正投影与遮挡电极211在衬底基板的正投影存在交叠的至少一个辅助块2330可以通过第一平坦层开设的第二过孔K2与遮挡电极211电连接，由此通过遮挡电极211实现与第一电源线电连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图15为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图15中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图15所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括阵列排布的多个辅助块2330。辅助结构233的多个辅助块2330可以按照列方向被划分为多组，每组可以包括一行辅助块2330。每组的辅助块2330可以通过连接线2331连接。相邻组的辅助块2330可以没有连接。至少一组的辅助块2330可以与第一电源线电连接，或者，多组辅助块可以均不与第一电源线电连接。本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图16为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图16中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图16所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括阵列排布的多个辅助块2330。辅助结构233的多个辅助块2330可以被划分为三组；第一组可以包括第一列的多个辅助块2330且不包括倒数第一行和第二行的辅助块；第二组可以包括第二列的 多个辅助块2330以及倒数第二行的部分辅助块，并不包括第三列和倒数第一行的辅助块；第三组可以包括第三列的多个辅助块2330以及倒数第一行的辅助块。第一组的辅助块可以连接形成条状，第二组和第三组的辅助块可以连接形成L型。每组内的辅助块可以通过连接线2331连接，相邻组的辅助块可以没有连接。至少一组辅助块可以与第一电源线电连接，或者，多组辅助块可以均不与第一电源线连接。本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图17为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图17中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图17所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括呈环形排布的两个辅助块2330。辅助块2330在衬底基板的正投影可以为L型。辅助块2330在衬底基板的正投影与位于第一导电层的遮挡电极211在衬底基板的正投影可以存在交叠。辅助块2330可以通过第一平坦层开设的至少一个第二过孔K2与遮挡电极211电连接，从而实现与第一电源线电连接。在另一些示例中，辅助块2330可以与第一电源线没有电性连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图18为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。在图18中仅示意第一导电层和透明导电层，省略示意了其他膜层。在一些示例中，如图18所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括呈阵列排布的多个辅助块2330。辅助块2330在衬底基板的正投影可以为条状。辅助块2330可以没有电性连接，可以为无效结构；或者，至少一个辅助块2330可以与第一电源线电连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图19为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。如图19所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233可以包括规则排布的多个辅助块2330。辅助块2330在衬底基板的正投影可以为条状或者可以为L型。辅助块2330可以没有电性连 接，可以为无效结构；或者，至少一个辅助块2330可以与第一电源线电连接。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图20为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。如图20所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233在衬底基板的正投影可以为环状，例如矩形环状。辅助结构233可以没有电性连接，可以为无效结构；或者，可以与第一电源线电连接。然而，本实施例对此并不限定。例如，辅助结构233在衬底基板的正投影可以为圆环形、椭圆环形等其他形状。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图21为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。如图21所示，边缘透明导电线231a和231b之间的空旷区域设置有辅助结构233。辅助结构233在衬底基板的正投影可以为网状。辅助结构233可以没有电性连接，可以为无效结构；或者，可以与第一电源线电连接。然而，本实施例对此并不限定。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图22为本公开至少一实施例的显示基板的局部膜层的另一俯视示意图。图23为图22中沿P-P’方向的局部剖面示意图。在本示例中，以一个透明导电层为例进行示意。图22和图23中省略示意了第二导电层靠近显示基板一侧的多个膜层结构以及透明导电层远离衬底基板一侧的多个膜层。
在一些示例性实施方式中，如图22和图23所示，在垂直于显示基板的方向上，第一显示区A1的显示基板可以包括：衬底基板10、设置在衬底基板10上的像素电路层(例如包括第二导电层22)、第一平坦层31以及透明导电层23。透明导电层23可以包括位于边缘透明导电线231a和231b之间的空旷区域的辅助结构233。辅助结构233在衬底基板的正投影可以与像素电路层的像素电路在衬底基板的正投影存在交叠。本示例的显示基板可以为单源漏金属层的结构，前述实施例的显示基板可以为双源漏金属层的结构。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本实施例提供的显示基板，通过在第一透明导电线外侧的空旷区域内设置辅助结构，可以改善制备透明导电层的曝光工艺的曝光环境(比如，减少光在第一过孔内进行反射，减少第一透明导电线接受的曝光量)，从而对边缘透明导电线的线宽产生影响，另外，还可以改善由于第一导电层在曝光工艺中的反射聚焦作用而导致第一透明导电线出现断线或变细的情况。
在另一些示例中，第一透明导电线外侧的空旷区域设置的辅助结构可以包括多个辅助块，且多个辅助块可以排布为B型、D型、S型、H型、L型、N型或者M型等图形。多个辅助块中的至少一部分在衬底基板的正投影可以与遮挡电极在衬底基板的正投影存在交叠。
在另一些示例中，在一个透明导电层内设置的多个辅助结构的形状可以大致相同，或者可以部分相同。例如，一个透明导电层包括的多个辅助结构可以均如图4所示的辅助结构，或者可以包括如图4所示的辅助结构和如图13所示的辅助结构。然而，本实施例对此并不限定。
下面对显示基板的像素电路层的膜层结构进行举例说明。
图24为本公开至少一实施例的像素电路的等效电路图。图25为本公开至少一实施例的像素电路的工作时序图。本示例性实施例的像素电路为7T1C结构。然而，本实施例对此并不限定。例如，像素电路可以为3T1C、5T1C、8T1C或8T2C等结构。
在一些示例性实施方式中，如图24所示，本示例的像素电路包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图24所示，显示基板包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。第二复位控制线RST2可以与第n行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)相同。在一些示例中，第n行像素电路所电连接的第二复位控制线RST2与第n+1行像素电路所电连接的第一复位控制线RST1为一体结构。如此，可以减少显示基板的信号线，实现显示基板的窄边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1配置为向像素电路提 供第一初始信号，第二初始信号线INIT2配置为向像素电路提供第二初始信号。例如，第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。
在一些示例性实施方式中，如图24所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电极与驱动晶体管T3的栅极电连接，存储电容Cst的第二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第 四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图25对图24示意的像素电路的工作过程进行说明。以图24所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图25所示，在一帧显示时间段，第一结构的像素电路的工作过程包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制 信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图26为本公开至少一实施例的像素电路的俯视示意图。图27为图26中沿R-R’方向的局部剖面示意图。在一些示例性实施方式中，如图26和图27所示，第一显示区的显示基板的像素电路层可以包括：依次设置在衬底基板10上的半导体层110、第一绝缘层101、第一栅金属层111、第二绝缘层102、第二栅金属层112、第三绝缘层103以及第二导电层22。第二导电层22远离衬底基板10一侧依次设置有第二平坦层32以及第一导电层21。在一些示例中，第一绝缘层101、第二绝缘层102和第三绝缘层103可以为无机绝缘层。然而，本实施例对此并不限定。
图28A为图26中形成半导体层后的显示基板的俯视示意图。图28B为图26中形成第一栅金属层后的显示基板的俯视示意图。图28C为图26中形成第二栅金属层后的显示基板的俯视示意图。图28D为图26中形成第三绝缘层后的显示基板的俯视示意图。图28E为图26中形成第二导电层后的显示基板的俯视示意图。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底基板。
在一些示例性实施方式中，衬底基板10可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如，衬底基板10可以为柔性基板。
(2)、形成半导体层。
在一些示例性实施方式中，在第一显示区的衬底基板10上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层110。如图27和图28A所示，半导体层110可以包括：像素电路的多个晶体管的有源层(例如包括：第一复位晶体管T1的有源层T10、阈值补偿晶体管T2的有源层T20、驱动晶体管T3的有源层T30、数据写入晶体管T4的有源层T40、第一发光控制晶体管T5的有源层T50、第二发光控制晶体管T6的有源层T60以及第二复位晶体管T7的有源层T70)。一个像素电路的七个晶体管的有源层可以为相互连接的一体结构。
在一些示例性实施方式中，半导体层110的材料例如可以包括多晶硅。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。多个掺杂区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。在一些示例中，有源层的掺杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
(3)、形成第一栅金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，依次沉积第一绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层110的第一绝缘层101，以及设置在第一显示区的第一绝缘层101上的第一栅金属层111。如图27和图28B所示，第一栅金属层111可以包括：像素电路的多个晶体管的栅极、以及存储电容Cst的第一极板Cst-1、第一复位控制线RST1、第二复位控制线RST2、扫描线GL以及发光控制线EML。第一复位控制线RST1与第一复位晶体管T1的栅极T11可以为一体结构。扫描线GL与数据写入晶体管T4的栅极T41和阈值补偿晶体管T2的栅极T21可以为一体结构。驱动晶体管T3的栅极T31和存储电容Cst的第一极板Cst-1可以为一体结构。发光控制线EML、第一发光控制晶体管T5的栅极T51以及第二发光控制晶体管T61的栅极T61可以为一体结构。第二复位控制线RST2与第二复位晶体管T7的栅极T71可以为一体结构。
(4)、形成第二栅金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，依次沉积第二绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一栅金属层111的第二绝缘层102，以及设置在第一显示区的第二绝缘层102上的第二栅金属层112。如图27和图28C所示，第二栅金属层112可以包括：像素电路的存储电容Cst的第二极板Cst-2、屏蔽电极BK、第一初始信号线INIT1以及第二初始信号线INIT2。屏蔽电极BK配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素电路的关键节点的电位，提高显示效果。
(5)、形成第三绝缘层和第二导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，沉积第三绝缘薄膜，通过图案化工艺形成第三绝缘层103。第三绝缘层103开设有多个像素过孔。随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，形成设置在第一显示区的第三绝缘层103上的第二导电层22。
如图7和图28D所示，第三绝缘层103开设有多个像素过孔，例如包括第一像素过孔V1至第十五像素过孔V15。第一像素过孔V1至第八像素过孔V8内的第三绝缘层103、第二绝缘层102和第一绝缘层101被去掉，暴露出半导体层110的表面。第九像素过孔V9内的第三绝缘层103和第二绝缘层102被去掉，暴露出第一栅金属层111的表面。第十像素过孔V10至第十五像素过孔V15内的第三绝缘层103被去掉，暴露出第二栅金属层112的表面。
如图27和图28E所示，第二导电层22可以包括：数据线DL、第一电源线PL1、以及多个连接电极(例如，第一阳极连接电极220、第一连接电极221至第五连接电极225)。第一阳极连接电极220可以通过第五像素过孔V5与第二发光控制晶体管T6的有源层T60的第二掺杂区电连接。第一连接电极221可以通过第一像素过孔V1与第一复位晶体管T1的有源层T10的第一掺杂区电连接，还可以通过第十像素过孔V10与第一初始信号线INIT1电连接。第二连接电极222可以通过第八像素过孔V18与上一行像素电路的第二复位晶体管的有源层的第一掺杂区电连接，还可以通过第十一像素过孔V11与第二初始信号线INIT2电连接。第三连接电极223可以通过第九像素过孔V9与驱动晶体管T3的栅极T31电连接，还可以通过第二像素过孔V2与阈值补偿晶体管T2的有源层T20的第一掺杂区电连接。第四连接电极224可以通过第七像素过孔V7与下一行像素电路的第一复位晶体管的有源层的第一掺杂区电连接，还可以通过第十四过孔V14与另一条第一初始信号线INIT1电连接。第五连接电极225可以通过第六像素过孔V6与第二复位晶体管T7的有源层T70的第一掺杂区电连接，还可以通过第十五像素过孔V15与另一条第二初始信号线INIT2电连接。数据线DL可以通过第三像素过孔V3与数据写入晶体管T4的有源层T40的第一掺杂区电连接。第一电源线PL1可以通过第十二像素过孔V12与屏蔽电极BK电连接，还可以通过第四像素过孔V4与第一发光控制晶体管T5的有源层T50的第一掺杂区电连 接，还可以通过竖排设置的两个第十三像素过孔V13与存储电容Cst的第二极板Cst-2电连接。
至此，制备完成第一显示区A1的像素电路层。第二显示区A2可以包括衬底基板10以及叠设在衬底基板10的第一绝缘层101、第二绝缘层102和第三绝缘层103。
(6)、形成第二平坦层和第一导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，涂覆第一平坦薄膜，通过图案化工艺形成第二平坦层32。随后，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化，形成设置在第一显示区的第二平坦层32上的第一导电层21。如图26和图27所示，第二平坦层32可以开设有多个过孔，例如第一过孔K1a和K1b。第一过孔K1a和K1b内的第二平坦层32被去掉，暴露出第二导电层22的表面。第一导电层21可以包括：遮挡电极211和第二阳极连接电极210。遮挡电极211可以通过第一过孔K1a与第一电源线PL1电连接。第二阳极连接电极210可以通过第一过孔K1a与第一阳极连接电极220电连接。在本示例中，遮挡电极211可以为不规则形状，以配置为覆盖第一节点N1，减小透明导电层对第一节点N1的串扰。然而，本实施例对此并不限定。在另一些示例中，遮挡电极211可以为圆形或五边形或六边形等规则形状。
(7)、形成第一平坦层和透明导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，涂覆第二平坦薄膜，通过图案化工艺形成第一平坦层31。随后，沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成设置在第一平坦层31上的透明导电层，如图4和图5所示。
在一些示例中，在形成前述结构的衬底基板上，涂覆第三平坦薄膜，通过图案化工艺形成第三平坦层。随后，沉积阳极导电薄膜，通过图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极层。随后，在形成前述图案的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)。像素定义层形成有暴露出阳极层的多个像素开口。在前述形成的像素开口内形成有机发光层，有机发光层 与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极图案，阴极分别与有机发光层和第二电源线电连接。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例性实施方式中，第一栅金属层、第二栅金属层、第一导电层、第二导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。透明导电层可以采用透明导电材料，例如氧化铟锡(ITO)。第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一平坦层至第五平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，可以设置多个透明导电层，比如在第一平坦层远离衬底基板一侧形成另一个透明导电层，随后形成第三平坦层和阳极层。然而，本实施例对此并不限定。
在一些示例中，当显示基板包括多个透明导电层时，每个透明导电层均可以设置与边缘透明导电线相邻的辅助结构，以改善制备每个透明导电层的曝光工艺的曝光环境(比如，减少光在第一过孔内进行反射，减少第一透明导电线接受的曝光量)，从而对透明导电线的线宽产生影响，并且还可以改善由于第一导电层在曝光工艺中的反射聚焦作用而导致透明导电线出现断线或变细的情况。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本实施例还提供一种显示基板的制备方法，包括：在衬底基板上形成像 素电路层，像素电路层包括多个像素电路，多个像素电路包括多个第一像素电路；在所述像素电路层远离所述衬底基板一侧形成第一平坦层；在所述第一平坦层远离所述衬底基板一侧形成至少一个透明导电层；在透明导电层远离衬底基板一侧形成多个第一发光元件。衬底基板包括第一显示区和第二显示区，第一显示区至少部分围绕第二显示区。多个第一发光元件位于第二显示区。第一平坦层位于第一显示区和第二显示区。透明导电层包括：多条第一透明导电线和至少一个辅助结构，多个第一发光元件和多个第一像素电路通过多条第一透明导电线耦接。辅助结构在衬底基板的正投影与多个像素电路中的至少一个像素电路在衬底基板的正投影存在交叠。
关于本实施例的显示基板的制备方法可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图29为本公开至少一实施例的显示装置的示意图。如图29所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的显示结构层的出光侧的感光传感器92。感光传感器92在显示基板91上的正投影与第二显示区A2存在交叠。
在一些示例性实施方式中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，其中，所述第一显示区至少部分围绕所述第二显示区；
    像素电路层，位于所述第一显示区，所述像素电路层包括多个像素电路，所述多个像素电路包括多个第一像素电路；
    多个第一发光元件，位于所述第二显示区；
    第一平坦层，位于所述像素电路层远离所述衬底基板一侧，且位于所述第一显示区和所述第二显示区；
    至少一个透明导电层，位于所述第一平坦层远离所述衬底基板的一侧；
    其中，所述透明导电层包括：多条第一透明导电线和至少一个辅助结构，所述多个第一发光元件和所述多个第一像素电路通过所述多条第一透明导电线耦接；
    所述辅助结构在所述衬底基板的正投影与所述多个像素电路中的至少一个像素电路在所述衬底基板的正投影存在交叠。
  2. 根据权利要求1所述的显示基板，还包括：位于所述像素电路层和所述第一平坦层之间的第一导电层，所述第一导电层包括：至少一个遮挡电极，所述遮挡电极与所述多个像素电路中的至少一个像素电路电连接，所述辅助结构在所述衬底基板的正投影与所述遮挡电极在所述衬底基板的正投影存在交叠。
  3. 根据权利要求2所述的显示基板，其中，所述像素电路层包括：第二导电层，所述第二导电层包括第一电源线，所述遮挡电极与所述第一电源线电连接。
  4. 根据权利要求3所述的显示基板，其中，所述辅助结构与所述遮挡电极电连接。
  5. 根据权利要求2至4中任一项所述的显示基板，其中，所述像素电路至少包括：驱动晶体管、阈值补偿晶体管和第一复位晶体管，所述驱动晶体 管、所述阈值补偿晶体管和第一复位晶体管均与第一节点电连接；所述遮挡电极在所述衬底基板的正投影被配置为覆盖所述像素电路的第一节点在所述衬底基板的正投影。
  6. 根据权利要求5所述的显示基板，其中，所述遮挡电极在所述衬底基板的正投影为非规则形状。
  7. 根据权利要求3所述的显示基板，其中，所述第一导电层与所述第二导电层之间设置有第二平坦层，所述第一导电层通过贯穿所述第二平坦层的第一过孔与所述第二导电层电连接；所述多条第一透明导电线中的至少一条第一透明导电线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影存在交叠。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述第一透明导电线包括边缘透明导电线，所述边缘透明导电线与所述辅助结构相邻。
  9. 根据权利要求8所述的显示基板，其中，所述辅助结构位于两条所述边缘透明导电线之间。
  10. 根据权利要求8或9所述的显示基板，其中，所述辅助结构与相邻的所述边缘透明导电线之间的间距大于或等于2微米且小于或等于3微米。
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述至少一个辅助结构包括：规则排布的多个辅助块。
  12. 根据权利要求11所述的显示基板，其中，所述辅助结构的多个辅助块阵列排布，且所述多个辅助块的形状和尺寸大致相同。
  13. 根据权利要求12所述的显示基板，其中，所述多个辅助块在所述衬底基板的正投影为矩形。
  14. 根据权利要求11所述的显示基板，其中，所述辅助结构的多个辅助块呈环形排布。
  15. 根据权利要求11至14中任一项所述的显示基板，其中，所述辅助结构的至少一个辅助块与第一电源线电连接。
  16. 根据权利要求11至15中任一项所述的显示基板，其中，所述辅助结构的至少两个相邻的辅助块通过连接线连接。
  17. 根据权利要求16所述的显示基板，其中，所述辅助结构的多个辅助块被划分为多组，每组包括至少两个辅助块，一组内的辅助块通过连接线连接。
  18. 根据权利要求1至10中任一项所述的显示基板，其中，所述至少一个辅助结构在所述衬底基板的正投影为环状或网状。
  19. 根据权利要求1至18中任一项所述的显示基板，其中，所述多个像素电路还包括：位于所述第一显示区的多个第二像素电路；所述显示基板还包括：位于所述第一显示区的多个第二发光元件；所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，所述至少一个第二像素电路配置为驱动所述至少一个第二发光元件。
  20. 一种显示装置，包括如权利要求1至19中任一项所述的显示基板。
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