WO2024016165A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024016165A1
WO2024016165A1 PCT/CN2022/106514 CN2022106514W WO2024016165A1 WO 2024016165 A1 WO2024016165 A1 WO 2024016165A1 CN 2022106514 W CN2022106514 W CN 2022106514W WO 2024016165 A1 WO2024016165 A1 WO 2024016165A1
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WIPO (PCT)
Prior art keywords
light
display area
emitting devices
pixel driving
transparent conductive
Prior art date
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PCT/CN2022/106514
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English (en)
French (fr)
Inventor
卢彦伟
王彬艳
李诗琪
蔡建畅
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002268.1A priority Critical patent/CN117837295A/zh
Priority to PCT/CN2022/106514 priority patent/WO2024016165A1/zh
Publication of WO2024016165A1 publication Critical patent/WO2024016165A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • embodiments of the present disclosure provide a display panel, including: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a circuit structure layer disposed between the circuit structure layer and the light-emitting structure layer. multiple conductive layers; wherein,
  • the substrate includes: a first display area and a second display area.
  • the second display area is located on at least one side of the first display area.
  • the light transmittance of the first display area is greater than that of the second display area.
  • the circuit structure layer includes: a first gate signal line, a constant voltage line, a plurality of shield electrodes and a plurality of pixel circuits located in the second display area.
  • the pixel circuit includes a driving transistor, and the driving transistor includes a gate
  • the plurality of pixel circuits include a plurality of first pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide the plurality of pixel circuits with A first constant voltage; the shielding electrode is connected to the constant voltage line, and the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate;
  • the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines include: a plurality of first type conductive lines and a plurality of second type conductive lines, the first type of conductive lines extend along a first direction
  • the orthographic projection of the portion on the substrate overlaps with the orthographic projection of at least one of the plurality of shield electrodes on the substrate, and the portion of the second type conductive line extending along the first direction is on the There is no overlap between the orthographic projection of the substrate and the orthographic projection of the plurality of shielding electrodes on the substrate;
  • the light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area.
  • the plurality of first light-emitting devices include: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices.
  • a light-emitting device, at least one first-type first light-emitting device among the plurality of first-type first light-emitting devices communicates with the plurality of first-type first light-emitting devices through at least one first-type conductive line among the plurality of first-type conductive lines.
  • At least one first pixel driving circuit in a pixel driving circuit is connected, and at least one second-type first light-emitting device among the plurality of second-type first light-emitting devices is connected through at least one of the plurality of second-type conductive lines.
  • a second type conductive line is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits.
  • the first pixel driving circuit is configured to drive the first light-emitting device to emit light.
  • the first-type light-emitting device is configured to emit light of a first color
  • the second-type first light-emitting device is configured to emit light of a second color, and the second color light is different from the first color light.
  • embodiments of the present disclosure also provide a display device, including: the display panel as described in the above embodiments.
  • Figure 1 is a schematic structural diagram of a display panel in an embodiment of the present disclosure
  • Figure 2 is a schematic plan view of a display panel in an embodiment of the present disclosure
  • Figure 3 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure
  • Figure 4 is a first partial schematic diagram of a display panel in an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the conductive wire passing through the shielding electrode in the first display area in some technologies
  • Figure 6A is a second partial schematic diagram of a display panel in an embodiment of the present disclosure.
  • Figure 6B is a third partial schematic diagram of a display panel in an embodiment of the present disclosure.
  • Figure 6C is a fourth partial schematic diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 7 is a first connection schematic diagram of the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure
  • Figure 8 is a schematic diagram of the connection of the first transparent conductive lines of the first transparent conductive layer in Figure 7;
  • Figure 9 is a schematic diagram of the connection of the second transparent conductive lines of the second transparent conductive layer in Figure 7;
  • Figure 10 is a schematic diagram of the connection of the third transparent conductive line of the third transparent conductive layer in Figure 7;
  • Figure 11 is a schematic diagram of the connection of the metal conductive lines of the metal conductive layer in Figure 7;
  • Figure 12 is a second connection schematic diagram of the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure
  • Figure 13 is a third connection schematic diagram of the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure
  • Figure 14 is a schematic diagram after forming a semiconductor layer according to an embodiment of the present disclosure.
  • Figure 15A is a schematic diagram after forming the first conductive layer according to an embodiment of the present disclosure.
  • Figure 15B is a schematic plan view of the first conductive layer in Figure 15A;
  • Figure 16A is a schematic diagram after forming the second conductive layer according to an embodiment of the present disclosure.
  • Figure 16B is a schematic plan view of the second conductive layer in Figure 16A;
  • Figure 17 is a schematic diagram after the fourth insulating layer is formed according to an embodiment of the present disclosure.
  • Figure 18A is a schematic diagram after the third conductive layer is formed according to an embodiment of the present disclosure.
  • Figure 18B is a schematic plan view of the third conductive layer in Figure 18A;
  • Figure 19 is a schematic diagram after the fifth insulating layer is formed according to an embodiment of the present disclosure.
  • Figure 20A is a schematic diagram after forming the fourth conductive layer according to an embodiment of the present disclosure.
  • Figure 20B is a schematic plan view of the fourth conductive layer in Figure 20A;
  • Figure 21A is a schematic diagram after forming the first transparent conductive layer according to an embodiment of the present disclosure.
  • Figure 21B is a schematic plan view of the first transparent conductive layer in Figure 21A;
  • Figure 22A is a schematic diagram after forming the second transparent conductive layer according to an embodiment of the present disclosure.
  • Figure 22B is a schematic plan view of the second transparent conductive layer in Figure 22A;
  • Figure 23A is a schematic diagram after the third transparent conductive layer is formed according to an embodiment of the present disclosure.
  • Figure 23B is a schematic plan view of the third transparent conductive layer in Figure 23A;
  • Figure 24A is a first schematic diagram after forming an anode layer according to an embodiment of the present disclosure.
  • Figure 24B is a schematic plan view of the anode layer in Figure 23A;
  • Figure 24C is a second schematic diagram after the anode layer is formed according to the embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram after forming a pixel definition layer according to an embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor includes at least three gate electrodes (gate electrode or control electrode), drain electrodes (drain electrode terminals, drain regions, or drain electrodes), and source electrodes (source electrode terminals, source regions, or source electrodes). Terminal components.
  • the transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.
  • one pole is directly described as the first pole and the other pole is the second pole, where the first pole can be the drain electrode and
  • the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the transistors in the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT) or field effect transistors (Field Effect Transistor, FET) or other devices with the same characteristics.
  • the thin film transistors used in embodiments of the present disclosure may include, but are not limited to, oxide transistors (Oxide TFT) or low temperature polysilicon thin film transistors (Low Temperature Poly-silicon TFT, LTPS TFT), etc.
  • oxide transistors Oxide TFT
  • Low Temperature Poly-silicon TFT Low Temperature Poly-silicon TFT, LTPS TFT
  • the embodiment of the present disclosure does not limit this.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • the first direction X may refer to the extension direction or the horizontal direction of the gate lines in the display area
  • the second direction Y may refer to the extension direction or the vertical direction of the data lines in the display area
  • the third direction Z It may refer to the direction perpendicular to the plane of the display panel or the thickness direction of the display panel, etc.
  • the first direction X and the second direction Y may be perpendicular to each other
  • the first direction X and the third direction Z may be perpendicular to each other.
  • full-screen or narrow-frame products have gradually become the development trend of display products due to their larger screen-to-body ratio and ultra-narrow frames.
  • sensors such as camera sensors or fingerprint sensors are usually installed.
  • full-screen or narrow-frame products usually use under-screen camera technology (Full display with camera, FDC) or under-screen fingerprint technology, placing cameras and other sensors in the under-display camera area of the display panel (Under Display Camera, UDC), the camera area under the screen not only has a certain transmittance, but also has a display function to achieve Full Display in Camera (FDC).
  • FDC Full Display with camera
  • UDC Under Display Camera
  • Figure 1 is a schematic structural diagram of a display panel.
  • the display area AA of the display panel may include: a first display area AA1 and a second display area AA2.
  • the second display area AA2 may be located at least one side.
  • the second display area AA2 may at least partially surround the first display area AA1.
  • the second display area AA2 may include a transition display area AAG adjacent to the first display area AA1.
  • the position of the first display area AA1 can correspond to the position of the sensor, and is configured to display a picture and transmit light. The transmitted light is received by the sensor.
  • the first display area AA1 can also be called a sensor corresponding area or an under-screen area.
  • the second display area AA2 is configured as a display screen, and the second display area AA2 can also be called a normal resolution display area, a normal sub-pixel area, a low-transmission display area, or the like.
  • the transitional display area AAG is configured to display a picture and configure signal wiring. The signal wiring is connected to the signal lines in the light-transmitting display area to lead out these signal lines.
  • the transitional display area AAG can also be called virtual (Dummy). sub-pixel area.
  • the light transmittance of the first display area AA1 is higher than the light transmittance of the second display area AA2.
  • the light transmittance of the first display area AA1 is higher than the light transmittance of the transition display area AAG.
  • light transmittance refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to the incident light flux.
  • “there is an overlapping area between the front projection of the sensor on the display panel and the first display area AA1” may mean that part of the front projection of the sensor on the display panel is located within the first display area AA1, or that the front projection of the sensor on the display panel is within the first display area AA1. All of them are located within the first display area AA1, or the orthographic projection of the photosensitive window of the sensor on the display panel is located within the first display area AA1, etc.
  • the embodiment of the present disclosure does not limit this.
  • the resolution of the first display area AA1 and the second display area AA2 may be the same, or the resolution of the first display area AA1 may be lower than the resolution of the second display area AA2.
  • resolution Pixels Per Inch, PPI refers to the number of pixels per unit area, which can be called pixel density. The higher the PPI value, the higher the density the display panel can display the picture, and the richer the details of the picture. .
  • the first display area AA1 may be located at an upper part, a lower part, or an edge position of the display area of the display panel.
  • the first display area AA1 may be located at the top middle position of the display area of the display panel, and the second display area AA2 may surround the first display area AA1.
  • the first display area AA1 may be located at other locations such as the upper left corner or the upper right corner of the display area of the display panel, and the second display area AA2 may surround at least one side (for example, one side, upper and lower sides) of the first display area AA1 Or left and right sides, etc.).
  • the embodiment of the present disclosure does not limit this.
  • the shape of the first display area AA1 may be any one or more of the following: square, rectangle, polygon, circle, elliptical semicircle, or Pentagon etc.
  • the shape of the display area of the display panel may be a rectangle, such as a rounded rectangle, and the first display area AA1 may be a circle.
  • the embodiment of the present disclosure does not limit this.
  • the shape of the outer contour of the transition display area AAG may be any one or more of the following: rectangle, polygon, circle, ellipse, etc.
  • the embodiment of the present disclosure does not limit this.
  • sensors may include but are not limited to: camera sensors, fingerprint sensors, light sensors, infrared sensors, ultrasonic sensors, LiDAR (Light Detection and Ranging) sensors or radar (Radar) sensors, etc.
  • camera sensors fingerprint sensors
  • light sensors infrared sensors
  • ultrasonic sensors ultrasonic sensors
  • radar radar
  • the first display area AA1 may include: a first circuit structure layer disposed on the substrate and a third circuit structure layer disposed on a side of the first circuit structure layer away from the substrate.
  • the second display area AA2 may include a second circuit structure layer disposed on the substrate and a second light-emitting structure layer disposed on a side of the second circuit structure layer away from the substrate.
  • the first circuit structure layer of the first display area AA1 includes a plurality of stacked insulating layers, and the first circuit structure layer may be called a composite insulating layer.
  • the first light-emitting structure layer of the first display area AA1 may include a plurality of functional sub-pixels.
  • the functional sub-pixels may include a first light-emitting device sp1.
  • the first light-emitting device sp1 may include at least a first anode.
  • the anode is connected to at least one first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2 through a conductive line (for example, a transparent conductive line), and the first pixel driving circuit QD1 is configured to be connected through the conductive line.
  • the first light-emitting device sp1 outputs a corresponding current, and the first light-emitting device sp1 is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the second circuit structure layer of the second display area AA2 may include: a plurality of first pixel driving circuits QD1 and a plurality of second pixel driving circuits QD2.
  • the second circuit structure layer may be called a driving circuit. structural layer.
  • the area in the second display area AA2 where the first pixel driving circuit QD1 is provided may be called a transition display area AAG.
  • the second light-emitting structure layer of the second display area AA2 may include a plurality of normal sub-pixels, the normal sub-pixels may include a second light-emitting device sp2, the second light-emitting device sp2 may include at least a second anode, and at least one normal sub-pixel has a second light-emitting structure layer.
  • the anode is connected to at least one second pixel driving circuit QD2.
  • the second pixel driving circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2.
  • the second light-emitting device sp2 is configured to respond to the connected pixel drive. The current output by the circuit emits light with corresponding brightness.
  • the first light-emitting device sp1 and the first pixel driving circuit QD1 that drives it are located in different display areas. Therefore, the first light-emitting device sp1 can be called a non-in-situ driven light-emitting device, and the first pixel driving circuit QD1 can be called a non-in-situ driven light-emitting device. In-situ pixel driving circuit.
  • the second light-emitting device sp2 and the second pixel driving circuit QD2 that drives it are both located in the second display area AA2. Therefore, the second light-emitting device sp2 can be called an in-situ driven light-emitting device, and the second pixel driving circuit QD2 can be called In-situ pixel driving circuit.
  • the display area of the display panel may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P may include a plurality of sub-pixels.
  • a subpixel can be the smallest part of a pixel whose brightness is controllable.
  • At least one sub-pixel may include: a light-emitting device and a pixel driving circuit connected to the light-emitting device, and the pixel driving circuit is configured to drive the connected light-emitting device to emit light.
  • the light emitting device may be a light emitting diode (Light Emitting Diode, LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED), a micro Any of LED (including: mini-LED or micro-LED), etc.
  • the light-emitting device may be an OLED, and the light-emitting device emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel driving circuit.
  • the light-emitting device may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting device may be electrically connected to the corresponding pixel driving circuit.
  • the color of light emitted by the light-emitting device can be determined by those skilled in the art according to actual application scenarios.
  • at least one of the plurality of pixel units P may include three sub-pixels, and the three sub-pixels may include: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel.
  • at least one of the plurality of pixel units P may include: four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • the embodiment of the present disclosure does not limit this.
  • the shape of the light emitting device may be a rectangle, a rhombus, a pentagon, a hexagon, etc.
  • multiple sub-pixels in a pixel unit may be arranged in horizontal parallel, vertical parallel, X-shape, cross-shape or Z-shape arrangement.
  • a pixel unit includes three sub-pixels
  • the three sub-pixels can be arranged horizontally, vertically, or in a zigzag pattern.
  • the four sub-pixels can be arranged horizontally, vertically, squarely or diamond-shaped.
  • the four sub-pixels can be arranged in a diamond shape to form an RGGB pixel array. cloth.
  • the embodiment of the present disclosure does not limit this.
  • the arrangement of pixel units in the first display area AA1 and the arrangement of the pixel units in the second display area AA2 may be the same, or may be different.
  • the number of sub-pixels included in the pixel unit in the first display area AA1 and the number of sub-pixels included in the pixel unit in the second display area AA2 may be the same, or may be different.
  • the arrangement of the sub-pixels included in the pixel unit in the first display area AA1 may be the same as the arrangement of the sub-pixels included in the pixel unit in the second display area AA2, or may be different.
  • the embodiment of the present disclosure does not limit this.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit of this exemplary embodiment adopts a 7T1C structure is used as an example for explanation.
  • Figure 3 is an equivalent circuit diagram of the pixel driving circuit in the embodiment of the present disclosure, as shown in Figure 3.
  • the pixel driving circuit may include: 7 transistors (first transistor T1 to seventh transistor T7) and a storage capacitor Cst.
  • the pixel driving circuit can communicate with 8 signal lines (scan signal line GL, data signal line DL, first power line PL1, second power line PL2, light emission control line EML, first initial signal line INIT1, second initial signal line INIT2 , the first reset control line RST1 and the second reset control line RST2) are connected.
  • the third transistor T3 can also be called a driving transistor
  • the fourth transistor T4 can also be called a data writing transistor
  • the second transistor T2 can also be called a threshold compensation transistor
  • the fifth transistor T5 can also be called the first light emitting control transistor.
  • Transistors, the sixth transistor T6 can also be called the second light emitting control transistor, the first transistor T1 can also be called the first reset transistor, and the seventh transistor T7 can also be called the second reset transistor.
  • transistors can be divided into N-type transistors and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) ).
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) ).
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display panel to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO) display panel can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the display panel may include: a scanning signal line GL, a data signal line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, second initial signal line INIT2, first reset control line RST1 and second reset control line RST2.
  • the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel driving circuit
  • the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel driving circuit.
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the scanning signal line GL may be configured to provide the scanning signal SCAN to the pixel driving circuit
  • the data signal line DL may be configured to provide the data signal DATA to the pixel driving circuit
  • the emission control line EML may be configured to provide the emission control signal EM to the pixel driving circuit.
  • a reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel driving circuit
  • a second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel driving circuit.
  • the first reset control line RST1 may be electrically connected to the scanning signal line GL of the n-1th row of pixel driving circuits to be input with the scanning signal SCAN(n -1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1).
  • the second reset control line RST2 may be electrically connected to the scan signal line GL of the n-th row pixel driving circuit to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). .
  • the second reset control line RST2 electrically connected to the pixel driving circuit of the nth row and the first reset control line RST1 electrically connected to the pixel driving circuit of the n+1th row may have an integrated structure.
  • n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced and the narrow frame design of the display panel can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel driving circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel driving circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the first power line PL1 may be used as a constant voltage line.
  • the first initial signal line INIT1 may also be used as a constant voltage line.
  • the constant voltage line are not limited to the first power supply line PL1 and the first initial signal line INIT1. Any signal line that provides a constant voltage in the pixel circuit can be used as a constant voltage line.
  • the scanning signal line GL, the light emitting control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the first reset control line RST1 and the second reset control line RST2 may be arranged along the horizontal direction. Extending, the first power line PL1, the second power line PL2 and the data signal line DL may extend in a vertical direction.
  • the third transistor T3 is electrically connected to the light-emitting device EL, and operates when the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals are connected.
  • the driving current is output under control to drive the light emitting device EL to emit light.
  • the gate electrode of the fourth transistor T4 is electrically connected to the scanning signal line GL
  • the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL
  • the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3 .
  • the gate electrode of the second transistor T2 is electrically connected to the scanning signal line GL.
  • the first electrode of the second transistor T2 is electrically connected to the gate electrode of the third transistor T3.
  • the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. Electrical connection.
  • the gate of the fifth transistor T5 is electrically connected to the light emitting control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. connect.
  • the gate electrode of the sixth transistor T6 is electrically connected to the light-emitting control line EML
  • the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3
  • the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device EL. connect.
  • the first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3.
  • the seventh transistor T7 is electrically connected to the anode of the light-emitting device EL and is configured to reset the gate of the light-emitting device EL.
  • the anode is reset.
  • the gate of the first transistor T1 is electrically connected to the first reset control line RST1.
  • the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1.
  • the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. Electrical connection.
  • the gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device EL. connect.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the pixel driving circuit may include: a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is the connection point of the storage capacitor Cst
  • the first transistor T1, the third transistor T3 and the second transistor T2 and the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3.
  • the third node N3 is a connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting device EL.
  • the fourth node N4 is the anode connection node.
  • the light emitting device EL may be an organic electroluminescent diode (OLED) including an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • OLED organic electroluminescent diode
  • the working process of the pixel driving circuit shown in FIG. 3 will be described below, taking the plurality of transistors included in the pixel driving circuit shown in FIG. 3 as P-type transistors as an example.
  • the working process of the pixel driving circuit may include: a first stage S1, a second stage S2, and a third stage S3.
  • the first phase S1 is called the reset phase.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low level signal, turning on the first transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, to the first node N1.
  • One node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning signal line GL is a high-level signal
  • the lighting control signal EM provided by the lighting control line EML is a high-level signal, so that the fourth transistor T4, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the light-emitting device EL does not emit light.
  • the second stage S2 is called the data writing stage or threshold compensation stage.
  • the scanning signal SCAN provided by the scanning signal line GL is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the luminescence control signal EM provided by the luminescence control line EML are both high-level signals
  • the data signal line DL outputs data signal DATA.
  • the third transistor T3 is turned on.
  • the scan signal SCAN is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line DL is provided to the first node N1, and charges the difference between the data voltage Vdata output by the data signal line DL and the threshold voltage of the third transistor T3 into the storage capacitor Cst, and the voltage of the first capacitor plate (ie, the first node N1) of the storage capacitor Cst is Vdata-
  • the seventh transistor T7 is turned on, causing the second initial signal provided by the second initial signal line INIT2 to be provided to the anode of the light-emitting device EL, initializing (resetting) the anode of the light-emitting device EL, clearing its internal pre-stored voltage, and completing the initialization. Make sure that the light-emitting device EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first transistor T1 to turn off.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.
  • the third stage S3 is called the luminous stage.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning signal line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6.
  • the first voltage signal VDD output by the first power line PL1 passes through the turned-on fifth transistor T5.
  • the third transistor T3 and the sixth transistor T6 provide a driving voltage to the anode of the light-emitting device EL to drive the light-emitting device EL to emit light.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the light-emitting device EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line DL
  • VDD is the first voltage signal output by the first power supply line PL1.
  • the pixel driving circuit of this embodiment can better compensate the threshold voltage of the third transistor T3.
  • Figure 4 is a first partial schematic diagram of a display panel in an embodiment of the present disclosure. It is an enlarged view of the Q area in Figure 1. It illustrates the planar structure of the area adjacent to the transition display area AAG in the first display area AA1, and illustrates The planar structure of the transition display area AAG and its surrounding areas in the second display area AA2.
  • the first display area AA1 may only provide the first light-emitting device sp1 without providing the first pixel driving circuit QD1 that drives the first light-emitting device sp1, so that the first display area AA1 Area AA1 can be displayed and can transmit light at the same time.
  • the first light-emitting device sp1 may include at least a first anode, and at least one first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2 is connected to at least one first pixel driving circuit QD1 through a conductive line L (eg, a transparent conductive line).
  • the first anode of the light emitting device sp1 is connected.
  • the conductive line L may extend from the first display area AA1 to the transition display area AAG in the second display area AA2. In this way, by arranging the first pixel driving circuit QD1 that drives the first light-emitting device sp1 in the transition display area AAG in the second display area AA2, the light blocking by the pixel driving circuit can be reduced, thereby increasing the brightness of the first display area AA1. transmittance. For example, taking the first pixel driving circuit QD1 as a 7T1C pixel driving circuit shown in FIG. 3, one end of the conductive line L (for example, a transparent conductive line) may be connected to the fourth node N4 (ie, the fourth node N4) of the first pixel driving circuit QD1. The anode connection node) is electrically connected, and the other end of the conductive line L can be electrically connected to the first anode of the first light-emitting device sp1.
  • the second display area AA2 may include: a plurality of first pixel driving circuits QD1, a plurality of second pixel driving circuits QD2, and a plurality of second light-emitting devices sp2. At least one of the second pixel driving circuits QD2 is configured to be connected to at least one second light emitting device sp2 in the second display area AA2, and the second pixel driving circuit QD2 is configured to directly connect to the The second light-emitting device sp2 outputs a corresponding current, so that the second light-emitting device sp2 emits light with a corresponding brightness.
  • the second light-emitting device sp2 electrically connected to the second pixel driving circuit QD2 may be located in the second display area AA2 together with the second pixel driving circuit QD2, and all or part of the second light-emitting device sp2 may be located in the second display area AA2.
  • the front projection of the at least one second pixel driving circuit QD2 on the substrate and the front projection of the at least one second light emitting device sp2 on the substrate may at least partially overlap.
  • the transition display area AAG in the second display area AA2 may include: a plurality of first pixel driving circuits QD1, at least one of the plurality of first pixel driving circuits QD1.
  • a pixel driving circuit QD1 may be connected to at least one first light-emitting device sp1 in the first display area AA1 through the conductive line L, and the at least one first pixel driving circuit QD1 is configured to provide power to the connected first light-emitting device through the conductive line L.
  • sp1 outputs a corresponding current, causing the first light-emitting device sp1 to emit light with corresponding brightness.
  • the first light-emitting device sp1 electrically connected to the first pixel driving circuit QD1 may be located in a different display area from the first pixel driving circuit QD1.
  • the orthographic projection of the at least one first pixel driving circuit QD1 on the substrate and the orthographic projection of the at least one first light-emitting device sp1 on the substrate may not overlap.
  • FIG. 1 As shown in FIG. 1
  • the transition display area AAG may also include: a plurality of second pixel driving circuits QD2 and a plurality of second light-emitting devices sp2, and the plurality of second pixel driving circuits QD2 are At least one second pixel driving circuit QD2 may be connected to at least one second light-emitting device sp2 in the transition display area AAG, and the second pixel driving circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2, so that The second light-emitting device sp2 emits light with corresponding brightness.
  • one or more second pixel driving circuits QD2 may be provided between adjacent first pixel driving circuits QD1.
  • two second pixel driving circuits QD2 may be provided between adjacent first pixel driving circuits QD1.
  • Pixel driving circuit QD2, or, as shown in FIG. 4, four second pixel driving circuits QD2, etc. may be provided between adjacent first pixel driving circuits QD1.
  • the embodiment of the present disclosure does not limit this.
  • the transition display area AAG may also include: an inactive pixel drive circuit QD0.
  • Setting the inactive pixel drive circuit can help improve the uniformity of components of multiple film layers in the etching process. properties to ensure the uniformity of the display panel.
  • the structure of the inactive pixel driving circuit and the first and second pixel driving circuits QD1 and QD2 of the row or column in which it is located may be substantially the same, except that it is not electrically connected to any light-emitting device.
  • the conductive line L may be made of transparent conductive material.
  • the transparent conductive material can be a conductive oxide material, such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel driving circuit mentioned in the exemplary embodiment of the present disclosure is an area divided according to the base structure layer
  • the light-emitting device mentioned in the present disclosure is an area divided according to the light-emitting structure layer.
  • the positions of the light-emitting device and the pixel driving circuit that drives the light-emitting device may be corresponding, or the positions of the light-emitting device and the pixel driving circuit that drives the light-emitting device may not correspond.
  • the plurality of second light-emitting devices sp2 in the transition display area AAG can be arranged normally in a regular pitch arrangement, while some of the second pixel driving circuits QD2 in the transition display area AAG can be compactly arranged in a small pitch arrangement, as Arrangement space is reserved for the first pixel driving circuit QD1 that drives the first light-emitting device sp1.
  • the positions of the second light-emitting device sp2 and the second pixel driving circuit QD2 in the transition display area AAG do not correspond.
  • a plurality of first light-emitting devices sp1 are disposed in the first display area AA1, and the first pixel driving circuit QD1 is disposed in the transition display area AAG.
  • the first light-emitting device sp1 in the first display area AA1 and the first pixel driving circuit QD1 are disposed in the transition display area AAG.
  • the positions of the first pixel driving circuit QD1 of the light-emitting device sp1 do not correspond to each other.
  • the area where the first pixel driving circuit QD1 is provided may be obtained by reducing the size of the second pixel driving circuit QD2.
  • the area where the first pixel driving circuit QD1 is provided can be obtained by reducing the size of the second pixel driving circuit QD2 in the first direction
  • the area where the first pixel driving circuit QD1 is provided can be obtained by reducing the size of the second pixel driving circuit QD2 in the first direction X and the second direction Y.
  • the embodiment of the present disclosure does not limit this.
  • a can be an integer greater than 1, for example, a can be equal to 2, 3 or 4, etc.
  • the second pixel driving circuit QD2 and the first pixel driving circuit QD1 can usually be arranged in a manner of 2 pressing 1, 3 pressing 1, or 4 pressing 1 in the first direction X, and the two pixel driving circuits QD1 in the first direction , 3 or 4 second pixel driving circuits QD2 are compressed, leaving 1 position for setting the first pixel driving circuit QD1.
  • the embodiment of the present disclosure does not limit this.
  • the size of the second pixel driving circuit QD2 in the first direction X may be smaller than the size of the second light emitting device sp2 in the first direction X.
  • the original b-row pixel driving circuit can be passed along the second direction Y. Compression, thereby adding a new row of arrangement space for the pixel driving circuit, and the space occupied by the b row pixel driving circuit before compression and the b+1 row pixel driving circuit after compression are the same.
  • b can be an integer greater than 1.
  • b can be equal to 2, 3, or 4, etc.
  • the size of the second pixel driving circuit QD2 in the second direction Y may be smaller than the size of the second light emitting device sp2 in the second direction Y.
  • the transition display area AAG is not only provided with a first pixel driving circuit QD1 electrically connected to the first light-emitting device sp1, but also provided with a second pixel driving circuit electrically connected to the second light-emitting device sp2. QD2, therefore, the number of pixel driving circuits in the transition display area AAG may be greater than the number of the first light-emitting devices sp1 in the first display area AA1.
  • a shield electrode 60 is provided in the display panel.
  • Figure 5 is a schematic diagram of a conductive line passing through a shield electrode in the first display area AA1 in some technologies.
  • the shield electrode 60 under the conductive line has an irregular shape and the shield electrode 60 is reflective, resulting in
  • the line widths of the plurality of conductive lines L (1 to 7) are not uniform. Among them, the line width of the conductive lines passing through the wider position of the shield electrode 60 is thinner, while the line width of the conductive lines passing through the narrower position of the shield electrode 60 is smaller. wider. In this way, the capacitance difference between the conductive lines of the same row and adjacent pixels will be large, resulting in a display unevenness (mura) problem.
  • Table 1 shows the line width of the conductive line passing through the wider part of the shield electrode 60 and the line width of the conductive line passing through the narrow part of the shield electrode 60 .
  • CD(7) refers to the line width of the conductive lines 7 of different display panels passing through the shielding electrode 60, indicating the line width of the conductive lines passing through the widest part of the shielding electrode 60;
  • CD(3) refers to the line width of the conductive lines 7 of different display panels.
  • the line width of the conductive line 3 of the panel passing through the shield electrode 60 represents the line width of the conductive line passing through the narrowest part of the shield electrode 60 .
  • the line width (critical dimension, CD) of the conductive line differs by about 0.2um (micron), which will cause
  • the capacitance difference between conductive lines (such as ITO traces) in a pixel unit is about 0.1fF.
  • one end of the conductive line L can be electrically connected to the fourth node N4 (ie, the anode connection node) of the first pixel drive circuit QD1, and the conductive line L The other end of can be electrically connected with the anode of the first light-emitting device sp1.
  • the conductive line L extends from the first display area AA1 to the transition display area AAG to realize the electrical connection between the first pixel driving circuit QD1 and the first light-emitting device sp1, the length of the conductive line L is longer, and ultimately one pixel unit is conductive
  • the capacitance between lines can vary by about a few hundred fF. In this way, at low gray levels, due to the long turn-on time, the node capacitance of the fourth node N4 (i.e., the anode connection node) is larger, and the capacitance difference between conductive lines (such as ITO traces) in the same row and adjacent pixels If it is larger, the turn-on time will be greatly affected, leading to mura problems.
  • the capacitances of conductive lines vary widely.
  • the lengths of the conductive lines of the plurality of light-emitting devices located in the first display area AA1 are different, which will lead to different changes in the capacitance of the light-emitting devices that emit light of different colors.
  • the capacitance difference of the conductive wire connected to the light-emitting device that emits red light is larger. .
  • the capacitance of the conductive wires connected to the green-emitting light-emitting device is greatly different, the light-emitting time of the green-emitting light-emitting device will be reduced, resulting in brightness differences in the display panel, resulting in poor display.
  • the defective degree of a green-emitting light-emitting device is greater than that of a red-emitting light-emitting device, and the defective degree of a red-emitting light-emitting device is greater than that of a blue-emitting light-emitting device.
  • the driving current for driving a light-emitting device that emits blue light may be greater than the driving current for driving a light-emitting device that emits red light, and the driving current for driving a light-emitting device that emits red light may be greater than that for driving a light-emitting device that emits green light. of driving current.
  • the driving current for driving a green-emitting light-emitting device is the smallest among the three primary color light-emitting devices. Therefore, when the capacitance of the fourth node N4 (i.e., the anode connection node) of the light-emitting devices emitting different lights is the same, the green-emitting light-emitting device has the same capacitance.
  • the light-emitting device turns on later than the light-emitting device that emits red light and the light-emitting device that emits blue light. At low gray levels, using the near-to-far connection method will cause some of the green-emitting light-emitting devices to not light up, affecting the display effect.
  • Embodiments of the present disclosure provide a display panel, which may include: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit structure layer and the light-emitting structure layer;
  • the substrate includes: a first display area and a second display area, the second display area is located on at least one side of the first display area, the light transmittance of the first display area is greater than the light transmittance of the second display area;
  • the circuit structure layer including: a first gate signal line, a constant voltage line, a plurality of shield electrodes and a plurality of pixel circuits located in the second display area.
  • the pixel circuit includes a driving transistor, the driving transistor includes a gate electrode, and the plurality of pixel circuits includes a plurality of third A pixel driving circuit;
  • the first gate signal line is connected to the gate of the driving transistor;
  • the constant voltage line is configured to provide a first constant voltage to a plurality of pixel circuits;
  • the shielding electrode is connected to the constant voltage line, and the first gate signal line is on the substrate
  • the orthographic projection on the substrate falls into the orthographic projection of the shielding electrode on the substrate;
  • the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines include: a plurality of first-type conductive lines and a plurality of second-type conductive lines,
  • the orthographic projection of the portion of the first type of conductive line extending along the first direction on the substrate overlaps with the orthographic projection of at least one of the plurality of shielding electrodes on the substrate, and the portion of the second type of conductive line extending along the first direction is on
  • a first-type light-emitting device and a plurality of second-type first light-emitting devices at least one first-type first light-emitting device among the plurality of first-type first light-emitting devices passes through at least one of the plurality of first-type conductive lines.
  • the conductive line is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits, and at least one second-type first light-emitting device among the plurality of second-type first light-emitting devices passes through the plurality of second-type conductive lines.
  • At least one of the second type conductive lines is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits.
  • the first pixel driving circuit is configured to drive the first light-emitting device to emit light, and the first type of first light-emitting device
  • the first light-emitting device of the second type is configured to emit light of a first color and is configured to emit light of a second color, and the second color light is different from the first color light.
  • the display panel provided by the exemplary embodiments of the present disclosure, on the one hand, by arranging the orthographic projection of the first type conductive line connected to the first type first light-emitting device and the shielding electrode on the substrate to overlap, it is possible to Maintaining the uniformity of the line width of the first type of conductive lines can make the difference in capacitance of the first type of conductive lines smaller.
  • the orthographic projection of the second type conductive line connected to the second type first light-emitting device and the shielding electrode on the substrate to not overlap, the uniformity of the line width of the second type conductive line can be maintained, so that The second type of conductive wire has a smaller difference in capacitance. In this way, by optimizing the wiring settings, the brightness difference can be improved and the display effect improved.
  • the shape of the shielding electrode may be a regular shape, for example, the shape of the shielding electrode may be a rectangle. In this way, by setting the shape of the shielding electrode to be rectangular, the routing environment of the first type of conductive wires can be ensured to be consistent, the uniformity of the line width of the first type of conductive wires can be improved, and the capacitance difference of the first type of conductive wires can be smaller. .
  • the plurality of first light-emitting devices in the first display area may include: multiple groups of first light-emitting devices.
  • the first light-emitting devices in each group of the plurality of groups of first light-emitting devices may be arranged along the first direction X, and the plurality of groups of first light-emitting devices may be arranged along the second direction Y.
  • the second direction Y intersects the first direction X.
  • the second direction Y and the first direction are perpendicular to each other.
  • more first pixel driving circuits QD1 are electrically connected to a plurality of first-type first light-emitting devices than to a plurality of second-type first light-emitting devices.
  • Each of the first pixel driving circuits QD1 is closer to the first display area. In this way, the length difference of the conductive lines connected to the first type of first light-emitting devices can be reduced, thereby reducing or avoiding display defects.
  • the display panel may include three transparent conductive layers, and the three transparent conductive layers may include: a first transparent conductive layer arranged sequentially along the side away from the substrate. layer, a second transparent conductive layer and a third transparent conductive layer.
  • the first transparent conductive layer may include a plurality of first transparent conductive lines
  • the second transparent conductive layer may include a plurality of second transparent conductive lines
  • the third transparent conductive layer may include a plurality of third transparent conductive lines.
  • the orthographic projections of the portion of the first transparent conductive line extending along the first direction, the portion of the second transparent conductive line extending along the first direction, and the portion of the third transparent conductive line extending along the first direction on the substrate may not overlap, That is, there are no overlapping traces.
  • the orthographic projection of the portion of the third transparent conductive line extending along the first direction and the portion of the second transparent conductive line extending along the first direction on the substrate may not overlap, that is, there may be no overlapping wiring.
  • the portion extending in the first direction X may have substantially the same size in the second direction Y.
  • a plurality of first-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through first transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through third transparent conductive lines.
  • a plurality of first-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through first transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through second transparent conductive lines.
  • a plurality of first-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through second transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through first transparent conductive lines.
  • a plurality of first-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through third transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through first transparent conductive lines.
  • a plurality of second-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through first transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through third transparent conductive lines.
  • a transparent conductive line electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area is connected to a transparent conductive line near the center of the first display area.
  • the types of transparent conductive lines electrically connected to the plurality of first-type first light-emitting devices in the center of the display area are the same, or the plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to the same type of transparent conductive lines.
  • the types of transparent conductive lines electrically connected to the plurality of first-type first light-emitting devices near the edge of the first display area are the same.
  • a transparent conductive line electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area is connected to a transparent conductive line near the center of the first display area.
  • the plurality of first-type first light-emitting devices in the center of the display area are electrically connected in different types, or the transparent conductive lines that are electrically connected to the plurality of second-type first light-emitting devices near the edge of the first display area are different from those near the first display area.
  • the types of transparent conductive lines electrically connected to the plurality of first-type first light-emitting devices at the edge of the display area are different.
  • a plurality of second-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through first transparent conductive lines.
  • a pixel driving circuit is electrically connected, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through third transparent conductive lines.
  • a plurality of first-type first light-emitting devices near the center of the first display area are connected to a plurality of first light-emitting devices through first transparent conductive lines.
  • a pixel driving circuit is electrically connected.
  • a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through third transparent conductive lines.
  • a plurality of first pixel driving circuits located near the center of the first display area are electrically connected.
  • the plurality of first-type first light-emitting devices between the first-type first light-emitting devices and the plurality of first-type first light-emitting devices near the edge of the first display area are connected through second transparent conductive lines and a plurality of first pixel driving circuits.
  • a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through first transparent conductive lines
  • a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through third transparent conductive lines
  • a plurality of second-type first light-emitting devices located near the center of the first display area The plurality of second-type first light-emitting devices between the device and the plurality of second-type first light-emitting devices close to the edge of the first display area are electrically connected to the plurality of first pixel driving circuits through second transparent conductive lines.
  • the transparent conductive lines electrically connected to the plurality of first-type first light-emitting devices are located in the group of first light-emitting devices in the second direction.
  • the transfer electrode side of the device is located in the group of first light-emitting devices in the second direction.
  • the transparent conductive lines electrically connected to the plurality of second-type first light-emitting devices are located in the group of first light-emitting devices in the second direction. The other side of the device's transfer electrode.
  • the first display area includes: a first sub-area and a second sub-area, the second sub-area is located on at least one side of the first sub-area and is adjacent to the second display area; a plurality of At least one first light-emitting device located in the first sub-region among the first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through conductive lines of a plurality of conductive layers; the plurality of first pixel driving circuits At least one first light-emitting device located in the second sub-region among the light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through conductive lines of the metal conductive layer in the circuit structure layer.
  • the metal conductive layer and the shielding electrode are located on the same film layer.
  • the shield electrode may be rectangular in shape.
  • the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the plurality of pixel circuits may further include: a plurality of second pixel driving circuits, and a plurality of second pixel driving circuits. At least one second pixel driving circuit in the circuit is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.
  • the second display area may include: a transition display area and a normal display area, and the transition display area is located on at least one side of the normal display area and adjacent to the first display area;
  • the transition display area may include : a plurality of first pixel driving circuits;
  • the normal display area includes: at least part of the plurality of second light-emitting devices and at least part of the plurality of second pixel driving circuits, at least part of the plurality of second light-emitting devices and the plurality of second pixel driving circuits; At least part of the second pixel driving circuit is connected.
  • the transition display area may include: a plurality of sub-transition areas; the light-emitting structure layer may further include: a plurality of second light-emitting sub-areas located close to at least one sub-transition area of the multiple sub-transition areas. device; the circuit structure layer may further include: a plurality of second pixel driving circuits located in at least one sub-transition region of the plurality of sub-transition regions close to the first display region; at least one second pixel driving circuit in the plurality of second pixel driving circuits.
  • the circuit is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.
  • the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the circuit structure layer may further include: a plurality of second pixel driving circuits located in the second display area, At least one second pixel driving circuit among the plurality of second pixel driving circuits is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device.
  • the device emits light.
  • the first color light may be green light
  • the second color light may include at least one of red light and blue light.
  • the first type of first light-emitting device may include: a green first light-emitting device sp1_g, which is configured to emit green light
  • the second type of first light-emitting device may include: a blue first light-emitting device sp1_b and The red first light-emitting device sp1_r and the blue first light-emitting device sp1_b are configured to emit blue light
  • the red first light-emitting device sp1_r is configured to emit red light.
  • the display panel includes three transparent conductive layers
  • the first type of first light-emitting device includes: green first light-emitting device sp1_g
  • the second type of first light-emitting device includes: blue first light-emitting device sp1_b and red first light-emitting device sp1_r
  • the display panel in the embodiment of the present disclosure will be described with reference to the accompanying drawings.
  • the length of the conductive line connected to the anode connection node of the green first light-emitting device sp1_g can be reduced to reduce the capacitance of the anode connection node, thereby ensuring that the green first light-emitting device sp1_g can start normally.
  • Bright take the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g as being closest to the first display area AA1, that is, the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is preferentially close to The first display area AA1 is arranged.
  • element A is close to element B may mean that there are no other elements A and other elements B between element A and element B, but there may be other elements besides element A and element B. other components.
  • the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is close to the first display area AA1
  • the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g described in the exemplary embodiment of the present disclosure may refer to the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g.
  • first pixel driving circuit QD1 electrically connected to the red first light-emitting device sp1_r and a first pixel driving circuit QD1 electrically connected to the blue first light-emitting device sp1_b, but there may be a third Other pixel driving circuits such as two-pixel driving circuit QD2 or inactive pixel driving circuit QD0.
  • the plurality of first light-emitting devices sp1 in the first display area AA1 may include: a plurality of green first light-emitting devices sp1_g, a plurality of blue first light-emitting devices sp1_b and a plurality of red first light-emitting devices sp1_g.
  • Device sp1_r The green first light-emitting device sp1_g is configured to emit green light, the blue first light-emitting device sp1_b is configured to emit blue light, and the red first light-emitting device sp1_r is configured to emit red light.
  • the plurality of second pixel driving circuits QD2 electrically connected to the green first light-emitting devices sp1_g are more electrically connected to the blue first light-emitting devices sp1_b and the red first light-emitting devices sp1_r.
  • Each of the plurality of second pixel driving circuits QD2 is closer to the first display area AA1. In this way, the length difference of the conductive lines electrically connected to the green first light-emitting device sp1_g can be reduced, so that display defects can be reduced or avoided.
  • FIG. 6A is a second partial schematic diagram of the display panel in an embodiment of the present disclosure.
  • FIG. 6B is a third partial schematic diagram of the display panel in an embodiment of the present disclosure.
  • FIG. 6C is a fourth partial schematic diagram of the display panel in an embodiment of the present disclosure. , showing part of the display area.
  • the first display area AA1 may have a center line CL extending along the second direction Y, and the first display area AA1 may be divided into a left half area and a right half area along the center line CL.
  • the conductive lines connected to the first light-emitting devices in the area and the right area may be substantially symmetrical about the center line CL.
  • 6A to 6C illustrate not only some of the light-emitting devices in the first display area AA1, but also some of the light-emitting devices in the sub-transition area close to the first display area AA1 in the transition display area AAG.
  • the first display area AA1 may include: a first sub-area AA1a and a second sub-area AA1b.
  • the second sub-area AA1b may surround the first sub-area AA1a and be adjacent to the transition display area AAG. That is, the second sub-area AA1b may be located between the first sub-area AA1a and the transition display area AAG.
  • the second sub-area AA1b may be an edge area of the first display area AA1, and the first sub-area AA1a may be a central area of the first display area AA1.
  • the shape of the first display area AA1 may be approximately circular
  • the shape of the first sub-area AA1a may be a circle with a smaller diameter than the first display area AA1
  • the first The sub-area AA1a may be a ring surrounding the first sub-area AA1a.
  • the first display area AA1 may be approximately circular in shape
  • the first sub-area AA1a may be approximately circular in diameter smaller than the first display area AA1
  • the first sub-area AA1a may be in a shape surrounding the first sub-area AA1 . Approximate ring of area AA1a.
  • the embodiment of the present disclosure does not limit this.
  • the film layer where the conductive line connected to at least one first light-emitting device located in the first sub-region AA1a among the plurality of first light-emitting devices is located is connected to the plurality of first light-emitting devices.
  • the conductive lines connected to at least one first light-emitting device located in the first sub-region AA1a are located in different film layers.
  • At least one first light-emitting device located in the first sub-region AA1a among the plurality of first light-emitting devices is electrically connected to at least one first light-emitting device among the plurality of first light-emitting devices through a conductive line of the transparent conductive layer; and more At least one first light-emitting device located in the first sub-region AA1a among the first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through the conductive lines of the metal conductive layer in the circuit structure layer.
  • the conductive lines of the metal conductive layer may be the conductive lines of the first source-drain metal layer (SD1) or the conductive lines of the second source-drain metal layer (SD2).
  • SD1 first source-drain metal layer
  • SD2 the conductive lines of the second source-drain metal layer
  • the conductive lines of the metal conductive layer and the shielding electrode are located on the same film layer.
  • the shielding electrode and the conductive lines of the metal conductive layer may both be located on the second source and drain metal layer.
  • the number of green first light-emitting devices sp1_g in the first sub-region AA1a may be greater than or equal to the second sub-region The number of green first light-emitting devices sp1_g in AA1b.
  • the transition display area AAG in the second display area AA2 may include: a plurality of sub-transition areas; the light-emitting structure layer may further include: at least one sub-transition area located close to the first display area among the plurality of sub-transition areas.
  • a plurality of second light-emitting devices in the transition area; the circuit structure layer may also include: a plurality of second pixel driving circuits located in at least one sub-transition area of the plurality of sub-transition areas close to the first display area; a plurality of second pixel driving circuits At least one second pixel driving circuit is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.
  • FIG. 6A and FIG. 6B illustrate 48 columns of light-emitting devices on both sides of the center line CL, where, for the left side of the center line CL, the 1st to 39th columns of light-emitting devices can be located in the first sub-region AA1a, the 40th The light-emitting devices in the 44th to 44th columns may be located in the second sub-region AA1b.
  • the light-emitting devices in the 1st to 39th columns and the 40th to 44th columns are the first light-emitting devices sp1, which may be arranged laterally from the first display through the conductive lines L.
  • the area AA1 extends to the transition display area AAG in the second display area AA2 and is connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • the film layers of the conductive lines used in the light-emitting devices in the 1st to 39th columns may be different from the film layers of the conductive lines used in the light-emitting devices in the 40th to 44th columns.
  • the light-emitting devices in the first display area AA1 as shown in Figures 6A to 13, the light-emitting devices in the 1st to 39th columns in the first sub-area AA1a can be driven by a lateral arrangement of conductive lines in the transparent conductive layer.
  • the 40th to 44th columns of light-emitting devices in the second sub-region AA1b can be arranged laterally using conductive lines of the metal conductive layer (such as the second source-drain metal layer SD2) Drive mode.
  • the light-emitting devices in the 45th to 48th columns may be located in the sub-transition area AAGn closest to the first display area AA1 in the transition display area AAG, and the 45th to 48th columns
  • the light-emitting device in the 48th column can be the second light-emitting device sp2, using an in-situ driving method, that is, the light-emitting devices in the 45th to 48th columns are directly connected to the second pixel driving circuit QD2 located in the transition display area AAG. In this way, neither It affects the transmittance and also ensures a good transition from the transition display area AAG to the first display area AA1.
  • the first display area AA1 may include: a first pull line area AA1-1, a second pull line area AA1-2, which are sequentially arranged away from the center of the first display area AA1.
  • the first cord area AA1-1 may be an area of the first display area AA1 relatively close to the geometric center of the first display area AA1
  • the fourth cord area AA1-4 may be an area of the first display area AA1 relatively close to the first display area.
  • the shapes of the first pull cord area AA1-1, the second pull cord area AA1-2, the third pull cord area AA1-3, and the fourth pull cord area AA1-4 Can be approximately part of a semicircle.
  • the size of the first cord area AA1-1 in the second direction Y may be larger than the size of the second cord area AA1-2 in the second direction Y.
  • the size of the second cord area AA1-2 in the second direction Y may be greater than
  • the size of the third wire pulling area AA1-3 in the second direction Y and the size of the second wire pulling area AA1-2 in the second direction Y may be larger than the size of the fourth wire pulling area AA1-4 in the second direction Y.
  • the embodiment of the present disclosure does not limit this.
  • the first light-emitting device sp1 in the first wire-drawing area AA1-1 can be electrically connected using the first conductive line L1 of the first transparent conductive layer
  • the second wire-drawing area AA1-2 can be electrically connected by using the second conductive line L2 of the second transparent conductive layer
  • the third wire pulling area AA1-3 can be electrically connected by using the third conductive wire L3 of the third transparent conductive layer
  • the fourth wire pulling area AA1-3 can be electrically connected by using the third conductive wire L3 of the third transparent conductive layer.
  • the conductive lines of the metal conductive layer (such as the second source and drain metal layer) can be used for electrical connection.
  • FIG. 6C illustrates 48 columns of light-emitting devices on both sides of the center line CL.
  • the light-emitting devices of the 1st to 13th columns can be located in the first pull line area AA1-1
  • the 14th to 13th columns of light-emitting devices can be located on the left side of the center line CL.
  • the light-emitting devices in the 26th column can be located in the second wire pulling area AA1-2
  • the light-emitting devices in the 27th to 39th columns can be located in the third wire pulling area AA1-3
  • the light-emitting devices in the 40th to 44th columns can be located in the fourth wire pulling area AA1-4.
  • the light-emitting devices in the 1st to 39th columns and the light-emitting devices in the 40th to 44th columns are the first light-emitting devices sp1, which can be arranged laterally through the conductive lines L to extend from the first display area AA1 to the transition display in the second display area AA2. In the area AAG, it is connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • the light-emitting devices in the 1st to 13th columns located in the first wire area AA1-1 can use the first transparent conductive line in the first transparent conductive layer.
  • the 14th to 26th columns of light-emitting devices located in the second wire pulling area AA1-2 can use the second transparent conductive layer in the second transparent conductive layer.
  • the light-emitting devices in the 27th to 39th columns located in the third wire pulling area AA1-3 can use the third transparent conductive layer in the third transparent conductive layer.
  • the 40th to 44th column light-emitting devices located in the fourth wire-wiring area AA1-4 can use a metal conductive layer (such as the second source and drain metal layer SD2) horizontally arranged driving mode of conductive lines.
  • a metal conductive layer such as the second source and drain metal layer SD2
  • the light-emitting devices in the 45th to 48th columns may be located in the sub-transition area AAGn closest to the first display area AA1 in the transition display area AAG, and the 45th to 48th columns
  • the light-emitting device in the 48th column can be the second light-emitting device sp2, using an in-situ driving method, that is, the light-emitting devices in the 45th to 48th columns are directly connected to the second pixel driving circuit QD2 located in the transition display area AAG. In this way, neither It affects the transmittance and also ensures a good transition from the transition display area AAG to the first display area AA1.
  • the first light-emitting device sp1 near the center of the first display area AA1 can be electrically connected using conductive lines of the transparent conductive layer.
  • the first display area The first light-emitting device sp1 near the edge of AA1 can be electrically connected using conductive lines of a metal conductive layer (such as a second source-drain metal layer).
  • a metal conductive layer such as a second source-drain metal layer
  • connection method of the light-emitting devices in the first display area AA1 will be described below with reference to the layout shown in FIGS. 6A to 6C and in conjunction with the accompanying drawings.
  • the connection relationship between a group of first light-emitting devices in the left half area of the first display area AA1 and a row of first pixel driving circuits QD1 in the transition display area AAG in the second display area AA2 is taken as an example.
  • other structures are omitted.
  • the transparent conductive lines of different layers are represented by different line types.
  • the first transparent conductive line L1 is represented by a solid line
  • the second transparent conductive line L2 is represented by a dotted line
  • the third transparent conductive line L3 is represented by a dotted line. .
  • FIG. 7 is a first connection schematic diagram of the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic connection diagram of the first transparent conductive line L1 of the first transparent conductive layer in FIG. 7 .
  • FIG. 9 is a schematic connection diagram of the second transparent conductive line L2 of the second transparent conductive layer in FIG. 7 .
  • FIG. 10 is a schematic connection diagram of the third transparent conductive line L3 of the third transparent conductive layer in FIG. 7 .
  • FIG. 11 is a schematic diagram of the connection of the metal conductive lines L4 of the metal conductive layer in FIG. 7 .
  • FIG. 8 is a schematic connection diagram of the first transparent conductive line L1 of the first transparent conductive layer in FIG. 7 .
  • FIG. 9 is a schematic connection diagram of the second transparent conductive line L2 of the second transparent conductive layer in FIG. 7 .
  • FIG. 10 is a schematic connection diagram of the third transparent conductive
  • FIG. 12 is a second connection schematic diagram of the first light emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure.
  • FIG. 13 is a third connection schematic diagram of the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure. The connection method of the light-emitting device will be described below with reference to Figures 6A to 13.
  • the green first light-emitting device sp1_g in the first sub-region AA1a of the first display area AA1 can pass through the first transparent conductive layer located on the first transparent conductive layer.
  • the line L1 is electrically connected to the first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2.
  • the green first light-emitting device sp1_g in the first sub-region AA1a can pass through the second transparent conductive line L2 located in the second transparent conductive layer and the first pixel driving circuit QD1 in the transition display area AAG. Electrical connection. As shown in FIGS.
  • the green first light-emitting device sp1_g in the first sub-region AA1a can be electrically connected through the third transparent conductive line L3 located in the third transparent conductive layer and the first pixel driving circuit QD1 in the transition display area AAG. connect.
  • a plurality of green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1, and are close to the second
  • the plurality of green first light-emitting devices sp1_g at the edge of the display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the third transparent conductive line L3, that is, along the first direction X away from the transition display area AAG.
  • the plurality of green first light-emitting devices sp1_g are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1.
  • the plurality of green first light-emitting devices sp1_g close to the transition display area AAG pass through the third
  • the transparent conductive line L3 is electrically connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g are located at the anode of the group of first light-emitting devices in the second direction Y.
  • the orthographic projection of the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g on the display panel plane and the shielding electrode 60 on the display panel plane The orthographic projections of can overlap.
  • the shielding electrode 60 is configured to shield the crosstalk of the first node N1 from the capacitance between the conductive lines.
  • the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can pass through the first light-emitting device sp1_b located on the first transparent conductive layer.
  • the transparent conductive line L1 is electrically connected to the first pixel driving circuit QD1 of the transition display area AAG.
  • the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can communicate with the transition display area AAG through the second transparent conductive line L2 located on the second transparent conductive layer.
  • the first pixel driving circuit QD1 is electrically connected. As shown in FIGS. 7 and 10 , the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can communicate with the transition display area AAG through the third transparent conductive line L3 located on the third transparent conductive layer.
  • the first pixel driving circuit QD1 is electrically connected. As shown in FIGS. 7 to 10 , the plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b located in the first sub-region AA1a and close to the transition display area AAG can pass through the third transparent conductive layer located on the third transparent conductive layer.
  • the conductive line L3 is electrically connected to the first pixel driving circuit QD1 of the transition display area AAG.
  • the plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b in the first sub-area AA1a away from the transition display area AAG can pass through
  • the first transparent conductive line L1 of the first transparent conductive layer is electrically connected to the first pixel driving circuit QD1 of the transition display area AAG.
  • the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r are located at the rotation point of the group of first light-emitting devices in the second direction Y.
  • the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3 electrically connected to the blue first light-emitting device sp1_b are located in the second direction Y of the group of first light-emitting devices.
  • the same side for example, the lower side.
  • the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L32 are electrically connected to the red first light-emitting device sp1_r, and the first transparent conductive line L32 is electrically connected to the blue first light-emitting device sp1_b.
  • the line L1, the second transparent conductive line L2 and the third transparent conductive line L3 are located on the same side, for example, the lower side, of the transfer electrode of the group of first light-emitting devices in the second direction Y.
  • the front projection of the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b on the display panel plane There may be no overlap with the orthographic projection of the shield electrode 60 on the display panel plane.
  • the second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the blue first light-emitting device sp1_b are in the second In the direction Y, they are located on both sides of the transfer electrodes of the group of first light-emitting devices.
  • the second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the red first light-emitting device sp1_r are located on both sides of the transfer electrodes of the group of first light-emitting devices in the second direction Y. side.
  • the green first light-emitting device sp1_g in the second sub-region AA1b can pass through the metal conductive line L4 located in the metal conductive layer and the first part of the transition display area AAG.
  • the pixel driving circuit QD1 is electrically connected.
  • the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the second sub-region AA1b can pass through the metal conductive line L4 located in the metal conductive layer and the first pixel of the transition display area AAG
  • the driving circuit QD1 is electrically connected.
  • the metal conductive line L4 electrically connected to the green first light-emitting device sp1_g, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b is located in the second direction Y in the group of first light-emitting devices.
  • the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane and the orthographic projection of the shield electrode 60 on the display panel plane may not overlap.
  • the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane is electrically connected to the first transparent conductive line L4 of the red first light-emitting device sp1_r and the first blue light-emitting device sp1_b.
  • Orthographic projections of the line L1, the second transparent conductive line L2, and the third transparent conductive line L3 on the display panel plane may overlap.
  • the metal conductive line L4 electrically connected to the first light-emitting device sp1 is in the orthographic projection of the display panel plane and the first transparent conductive line L1 and the second transparent conductive line electrically connected to the green first light-emitting device sp1_g.
  • Orthographic projections of L2 and the third transparent conductive line L3 on the display panel plane may not overlap.
  • the wiring arrangement space of the first transparent conductive layer can arrange about 10 to 15 first transparent conductive lines L1.
  • the first transparent conductive lines L1 The wiring arrangement space of the layer can arrange 13 first transparent conductive lines L1.
  • the wiring arrangement space of the second transparent conductive layer can arrange about 10 to 15 second transparent conductive lines L2.
  • the wiring arrangement space of the second transparent conductive layer can arrange Cloth 13 second transparent conductive threads L2.
  • the wiring arrangement space of the third transparent conductive layer can arrange about 10 to 15 third transparent conductive lines L3.
  • the wiring arrangement space of the third transparent conductive layer can arrange Cloth 13 third transparent conductive threads L3.
  • approximately five metal conductive lines L4 can be arranged in the wiring arrangement space of the metal conductive layer.
  • the embodiment of the present disclosure does not limit this.
  • the metal conductive layer may be a first source-drain metal layer (SD1) or a second source-drain metal layer (SD2).
  • the first source-drain metal (SD1) layer may include: first poles and second poles of a plurality of transistors in the pixel driving circuit, data signal lines, first power lines, and the like.
  • the second source-drain metal layer (SD2) may include: the shield electrode 60.
  • the second light-emitting device sp2 relatively close to the first display area AA1 in the second display area AA2 adopts an in-situ driving mode, that is, a transition display
  • the second light-emitting device sp2 relatively close to the first display area AA1 and the second pixel driving circuit QD2 driving the second light-emitting device sp2 are both located in the transition display area AAG.
  • the light-emitting devices in the 45th to 48th columns adopt an in-situ driving method.
  • the first pixel driving circuit QD1 in the transition display area AAG is electrically connected.
  • a plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1, close to the first A plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b at the edge of the display area AA1 (ie, the first display area AA1 relatively close to the second display area AA2) pass through the second transparent conductive line L2 of the second transparent conductive layer It is electrically connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • a plurality of green first light-emitting devices sp1_g near the center of the first display area AA1 passes through the second transparent conductive line L2 of the second transparent conductive layer and the transition display area AAG.
  • the first pixel driving circuit QD1 is electrically connected, and the plurality of green first light-emitting devices sp1_g close to the edge of the first display area AA1 (that is, the first display area AA1 is relatively close to the second display area AA2) pass through the first transparent conductive layer.
  • a transparent conductive line L1 is electrically connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • a plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b close to the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1, close to The plurality of red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b at the edge of the first display area AA1 (that is, the first display area AA1 relatively close to the second display area AA2) passes through the third transparent conductive layer located on the third transparent conductive layer.
  • the conductive line L3 is electrically connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • the first light-emitting device sp1 of the first display area AA1 can be electrically connected using the first transparent conductive line L1 of the first transparent conductive layer.
  • the second transparent conductive line L2 of the second transparent conductive layer can be used for electrical connection, after utilizing the wiring arrangement space of the second transparent conductive layer , the first light-emitting device sp1 relatively close to the transition display area AAG in the first sub-region AA1a can be electrically connected using the third transparent conductive line L3 of the third transparent conductive layer.
  • the metal conductive line L4 of the metal conductive layer can be used for electrical connection in the second sub-area AA1b.
  • other arrangements can also be adopted.
  • the first light-emitting device sp1 close to the transition display area AAG can be electrically connected using the second transparent conductive line L2 of the second transparent conductive layer.
  • the embodiment of the present disclosure does not limit this.
  • the structure of the display panel is explained below through an example of the preparation process of the display panel.
  • the "patterning process" mentioned in the embodiments of this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials including processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the display panels of the second display area AA2 and the first display area AA1 may include: a substrate, a circuit structure layer provided on the substrate, a first transparent conductive layer , a second transparent conductive layer, a third transparent conductive layer and a light-emitting structure layer.
  • the circuit structure layer of the first display area AA1 may include: a plurality of insulation layers.
  • the circuit structure layer of the second display area AA2 may include: a plurality of first pixel driving circuits and a plurality of second pixel driving circuits.
  • a first flat layer may be disposed between the first transparent conductive layer and the second transparent conductive layer, and a second flat layer may be disposed between the second transparent conductive layer and the third transparent conductive layer.
  • a third flat layer may be disposed between the third transparent conductive layer and the light-emitting structure layer.
  • the first to third planar layers may be organic material layers.
  • the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer.
  • the anode layer may include: an anode of the first light-emitting device located in the first display area AA1 and an anode of the second light-emitting device located in the second display area AA2.
  • the anode area of the first light-emitting device may be smaller than the anode area of the second light-emitting device that emits light of the same color, so as to increase the light transmittance of the first display area AA1.
  • the display panel may include two or more transparent conductive layers.
  • the embodiment of the present disclosure does not limit this.
  • the preparation process of the display panel may include the following operations.
  • the following description takes a first pixel driving circuit QD1 and a second pixel driving circuit QD2 in the second display area AA2 as an example.
  • the first pixel driving circuit QD1 of the transition display area AAG can use the pixel driving circuit shown in FIG. 3 .
  • the structures of the second pixel driving circuit QD2 and the first pixel driving circuit QD1 may be substantially the same, and the structures of the inactive pixel driving circuit and the first pixel driving circuit QD1 may be substantially similar, but the inactive pixel driving circuit has no via connection, Those skilled in the art can refer to the relevant descriptions to understand that the signal is not received, and the embodiments of the present disclosure will not be described in detail here.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz.
  • the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate , polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be Materials such as polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft films are used.
  • the first inorganic material layer and the second inorganic material layer can be made of silicon nitride. (SiNx) or silicon oxide (SiOx), etc., are configured to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • forming a semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, and forming a first insulating film covering the substrate. layer, and a semiconductor layer disposed on the first insulating layer, as shown in Figure 14.
  • the first insulating layer may be called a buffer layer and is configured to improve the water and oxygen resistance of the substrate.
  • the semiconductor layer may be called an active (ACT) layer.
  • the semiconductor layer of the second display area AA2 may at least include: an active layer of a plurality of transistors of the pixel driving circuit, for example, a first active layer of the first transistor T1 Layer 11, second active layer 12 of the second transistor T2, third active layer 13 of the third transistor T3, fourth active layer 14 of the fourth transistor T4, fifth active layer 15 of the fifth transistor T5 , the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7.
  • an active layer of a plurality of transistors of the pixel driving circuit for example, a first active layer of the first transistor T1 Layer 11, second active layer 12 of the second transistor T2, third active layer 13 of the third transistor T3, fourth active layer 14 of the fourth transistor T4, fifth active layer 15 of the fifth transistor T5 , the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7.
  • the active layers (for example, the first active layer 11 to the seventh active layer 17 ) of multiple transistors of a pixel driving circuit may be interconnected and integrated. structure.
  • the second active layer 12 and the sixth active layer 16 may be located on one side of the third active layer 13 in the first direction X, and the fourth active layer 14 and the fifth active layer 15 may be located on a side opposite to the first direction X of the third active layer 13 .
  • the fifth active layer 15 , the sixth active layer 16 and the seventh active layer 17 are located on one side of the third active layer 13 in the second direction Y.
  • the first active layer 11 , the second active layer 12 and The fourth active layer 14 may be located on a side opposite to the second direction Y of the third active layer 13 .
  • the shape of the first active layer 11 may be an “n” shape.
  • the shape of the second active layer 12 may be an inverted “L” shape.
  • the shape of the third active layer 13 may be an “ ⁇ ” shape.
  • the shapes of the fourth active layer 14 , the fifth active layer 15 , the sixth active layer 16 and the seventh active layer 17 may all be in an "I" shape.
  • the active layer of each transistor may include: at least one channel region, and first and second regions located on both sides of the channel region.
  • the channel region may be undoped with impurities and have semiconductor characteristics.
  • the first region and the second region may be on both sides of the channel region and be doped with impurities and thus be conductive. Impurities can vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as the source or drain electrode of the transistor. Portions of the active layer between the transistors may be interpreted as wiring doped with impurities and may be configured to electrically connect the transistors.
  • the first region 11 - 1 of the first active layer 11 , the first region 14 - 1 of the fourth active layer 14 , and the fifth active layer 15 The first area 15-1 and the first area 17-1 of the seventh active layer 17 may be provided separately.
  • the second region 11-2 of the first active layer 11 can simultaneously serve as the first region 12-1 of the second active layer 12 and the second gate signal portion SL2, and the first region 13-1 of the third active layer 13
  • the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 can be simultaneously used.
  • the second region 13-2 of the third active layer 13 can be simultaneously used as the second active layer 14-2.
  • the second region 12-2 of the source layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 can simultaneously serve as the second region of the seventh active layer 17. District 17-2.
  • the semiconductor layer may be made of metal oxide material.
  • metal oxide materials may include, but are not limited to: oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin oxides, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the semiconductor layer can use amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • the semiconductor layer may be a single layer, a double layer, or multiple layers.
  • the embodiment of the present disclosure does not limit this.
  • the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer layer or composite layer.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, and patterning the first conductive film through a patterning process. , forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 15A and 15B.
  • Figure 15B is a schematic plan view of the first conductive layer in Figure 15A.
  • the second insulating layer may be called a gate insulation (GI) layer
  • the first conductive layer may be called a first gate metal (Gate1) layer.
  • the first conductive layer of the second display area AA2 may include at least: a scanning signal line 21, a first reset control line 22, a light emitting control line 23, The first plate 24 and the second reset control line 25 of the storage capacitor Cst.
  • the shape of the first plate 24 of the storage capacitor may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 24 on the substrate is consistent with the third active
  • the orthographic projections of the layers 13 on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a first plate of the storage capacitor and the gate electrode of the third transistor T3.
  • the transistor used in the embodiments of the present disclosure may include a variety of structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
  • the second transistor T2 and the first transistor T1 connected to the gate electrode of the third transistor T3 may be double-gate thin film transistors, which may help reduce leakage of the gate electrode of the third transistor T3. current.
  • the shape of the scanning signal line 21 , the first reset control line 22 , the second reset control line 25 and the light emitting control line 23 may be a line shape in which the main body part extends along the first direction X.
  • the scanning signal lines 21 and the light emission control lines 23 may be located on both sides of the first plate 24 in the second direction Y.
  • the first reset control line 22 may be located on a side of the scanning signal line 21 away from the first plate 24 .
  • the second reset control line 25 may be located on a side of the scanning signal line 21 away from the first plate 24 .
  • the area where the scanning signal line 21 overlaps with the second active layer 12 can serve as a gate electrode of the second transistor T2, and the orthographic projection of the scanning signal line 21 on the substrate is consistent with the second active layer 12.
  • the scanning signal line 21 is provided with a gate block 21-1 that protrudes toward the first reset control line 22, and the area where the gate block 21-1 overlaps the second active layer 12 can serve as the second transistor T2.
  • the second transistor T2 of the double-gate structure can be formed.
  • the scanning signal line 21 and the gate electrode of the second transistor T2 of the pixel driving circuit in the same row may be an integral structure connected to each other.
  • the area where the scanning signal line 21 overlaps with the fourth active layer 14 may serve as the gate electrode of the fourth transistor T4, and the orthographic projection of the scanning signal line 21 on the substrate is in contact with the fourth active layer 14. 14 There are overlapping regions in orthographic projections on the substrate.
  • the scanning signal line 21 and the gate electrode of the fourth transistor T4 of the pixel driving circuit in the same row may be an integral structure connected to each other.
  • the area where the first reset control line 22 overlaps the first active layer 11 can be used as a gate electrode of the first transistor T1 in a double-gate structure.
  • the first reset control line 22 is on the substrate. There is an overlapping area between the orthographic projection and the orthographic projection of the first active layer 11 on the substrate.
  • the first reset control line 22 and the gate electrode of the first transistor T1 of the pixel driving circuit in the same row may be an integral structure connected to each other.
  • the area where the second reset control line 25 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7, and the orthographic projection of the second reset control line 25 on the substrate is consistent with the second There is an overlapping area in the orthographic projection of the active layer 12 on the substrate.
  • the second reset control line 25 and the gate electrode of the seventh transistor T7 of the pixel driving circuit in the same row may be an integral structure connected to each other.
  • the area of the light-emitting control line 23 overlapping the fifth active layer 15 serves as the gate electrode of the fifth transistor T5
  • the area of the light-emitting control line 23 overlapping the sixth active layer 16 serves as the gate electrode of the fifth transistor T5.
  • the orthographic projection of the luminescence control line 23 on the substrate and the orthographic projection of the sixth active layer 16 on the substrate There are overlapping areas of projections.
  • the light emission control line 23 and the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 of the pixel driving circuit in the same row may be an integral structure connected to each other.
  • the first conductive layer after forming the first conductive layer pattern, can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first transistors T1 to In the channel region of the seventh transistor T7, the semiconductor layer in the region not blocked by the first conductive layer is conductive, that is, the first and second regions of the first active layer to the seventh active layer are all conductive.
  • the second conductive layer may be formed of a metal material.
  • the metal material may include but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above-listed metals, such as aluminum Neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc.
  • the second conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer layer or composite layer.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process. , forming a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 16A and 16B.
  • Figure 16B is a schematic plan view of the second conductive layer in Figure 16A .
  • the third insulating layer may be called a gate insulation (GI) layer
  • the second conductive layer may be called a second gate metal (Gate2) layer.
  • the second conductive layer of the second display area AA2 may at least include: a first initial signal line 31 , a second initial signal line 32 , and a storage capacitor Cst.
  • the second plate 33 of the storage capacitor may be located between the scanning signal line 21 and the light emission control line 23 of the pixel driving circuit, adjacent in the first direction X or the opposite direction of the first direction X.
  • the second plates 33 of the pixel driving circuit can be connected through a plate connecting line 35.
  • the first end of the plate connecting line 35 is connected to the second plate 33 of the pixel driving circuit.
  • the second end of the plate connecting line 35 is connected to the second plate 33 of the pixel driving circuit. After the end extends along the first direction X or the opposite direction of the first direction
  • the second plates 33 of the circuit are connected to each other.
  • the second plates of multiple pixel driving circuits in a unit row can form an integrated structure connected to each other through plate connection lines, and the second plates of the integrated structure can be multiplexed as power connections. lines to ensure that multiple second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.
  • the outline of the second electrode plate 33 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 33 on the base is consistent with the position of the first electrode plate 24 on the base.
  • the orthographic projections on the pixels at least partially overlap, and the first plate 24 and the second plate 33 constitute the storage capacitor of the pixel driving circuit.
  • the second plate 33 is provided with an opening 36 , and the opening 36 may be located in the middle of the second plate 33 .
  • the opening 36 may be rectangular, so that the second electrode plate 33 forms a ring-shaped structure.
  • the opening 36 exposes the third insulating layer covering the first electrode plate 24
  • the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 36 on the substrate.
  • the opening 36 may be configured to accommodate a subsequently formed first via hole.
  • the first via hole is located in the opening 36 and exposes the first plate 24 so that the second pole of the subsequently formed first transistor T1 can pass through the first via hole.
  • the via hole is connected to the first plate 24 .
  • the shape of the first initial signal line 31 and the second initial signal line 32 may be a line shape in which the main body portion extends along the first direction X.
  • the stopper 34 may be located between the scanning signal line 21 and the first initial signal line 31.
  • the shape of the stopper 34 may be a polygonal shape.
  • the stopper 34 may include a first electrode segment extending along the first direction X and a second electrode segment extending along the second direction Y.
  • the orthographic projection of the stopper 34 on the substrate at least partially overlaps with the orthographic projection of the subsequently formed data signal line 45 on the substrate. Therefore, the stopper 34 can shield the impact of the data voltage jump on the key node and avoid the data voltage. The jump affects the potential of key nodes of the pixel drive circuit and improves the display effect.
  • the orthographic projection of the stopper 34 on the substrate and the second region 11-2 of the first active layer 11 are on the substrate.
  • the orthographic projection on at least partially overlaps, so that the blocker 34 can block the second gate signal portion SL2 and play a shielding role. In this way, the impact of the voltage jump on the key nodes can be shielded and the impact of the voltage jump on the pixel driving can be avoided.
  • the potential of the key nodes of the circuit improves the display effect.
  • the second electrode segment of the left stopper 34 can extend to the left pixel driving circuit (not shown in the figure) to block the conductive connection portion of its second transistor T2, and the right stopper 34 can The first electrode segment extends to the pixel drive circuit on the left side of the figure, blocking the conductive connection portion of its second transistor T2.
  • the stopper 34 may not be provided, or the orthographic projection of the stopper 34 on the substrate does not overlap with the orthographic projection of the second gate signal line SL2 on the substrate.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a layer covering the second conductive layer.
  • the fourth insulation layer is provided with multiple via holes, as shown in Figure 17.
  • the fourth insulating layer may be referred to as an interlayer dielectric (ILD) layer.
  • ILD interlayer dielectric
  • the plurality of via holes may include: a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , and a fifth via hole.
  • V5 the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10 and the eleventh via V11.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 36 of the second plate 33 on the substrate, and the fourth insulation in the first via hole V1 layer and the third insulating layer are etched away to expose the surface of the first plate 24, and the first via hole V1 is configured so that the second electrode of the subsequently formed first transistor T1 can communicate with the first electrode through the via hole. Board 24 connection.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second electrode plate 33 on the substrate, and the fourth insulating layer in the second via hole V2 is engraved It is etched away to expose the surface of the second electrode plate 33 , and the second via hole V2 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the second electrode plate 33 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthogonal projection of the first area of the fifth active layer 55 on the substrate, and the third via hole V3 in the third via hole V3
  • the four insulating layers, the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer 55, and the third via V3 is configured to enable the subsequently formed fifth transistor T5.
  • the first pole is connected to the first region of the fifth active layer 55 through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer 66 on the substrate, and the orthogonal projection of the fourth via hole V4 on the substrate is
  • the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second area of the sixth active layer 16 (also the second area of the seventh active layer), and the fourth via V4 It is configured such that the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) is connected to the second region of the sixth active layer 16 through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer 14 on the substrate, and the orthogonal projection of the fifth via hole V5 on the substrate is
  • the four insulating layers, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fourth active layer 14, and the fifth via V5 is configured to enable the subsequently formed fourth transistor T4.
  • the first pole is connected to the first region of the fourth active layer 14 through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second area of the first active layer 11 on the substrate, and the orthogonal projection of the sixth via hole V6 on the substrate is
  • the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second area of the first active layer 11 (also the first area of the second active layer 12), and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed first transistor T1 (the first electrode of the second transistor T2) to the second region of the first active layer 11 through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the first region of the seventh active layer 17 on the substrate, and the third via hole V7 in the seventh via hole V7
  • the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer 17 .
  • the seventh via hole V7 is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first area of the first active layer 11 on the substrate, and the orthogonal projection of the eighth via hole V8 on the substrate is
  • the four insulating layers, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the first active layer 11, and the eighth via V8 is configured to enable the subsequently formed first transistor T1.
  • the first pole is connected to the first region of the first active layer 11 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the ninth via hole V9 is It is etched away to expose the surface of the first initial signal line 31, and the ninth via hole V9 is configured so that the first pole of the subsequently formed first transistor T1 is connected to the first initial signal line 31 through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second initial signal line 32 on the substrate, and the fourth insulating layer in the tenth via hole V10 is The surface of the second initial signal line 32 is etched away, and the tenth via hole V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the second initial signal line 32 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the stopper 34 on the substrate, and the fourth insulating layer in the eleventh via hole V11 is engraved It is etched away to expose the surface of the stopper 34 , and the eleventh via hole V11 is configured so that the first power line formed later is connected to the stopper 34 through the via hole.
  • the via hole pattern of the second pixel driving circuit QD2 or the inactive pixel driving circuit and the via hole pattern of the first pixel driving circuit QD1 may be substantially the same.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a fourth insulating layer.
  • the third conductive layer on the layer is as shown in Figures 18A and 18B.
  • Figure 18B is a schematic plan view of the third conductive layer in Figure 18A.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the third conductive layer of the second display area AA2 may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, and a data signal line 45. and first power cord 46.
  • the shape of the first connection electrode 41 may be a strip shape with a main body portion extending along the second direction Y.
  • the first connection electrode 41 may serve as the first gate signal line SL1, which is connected to the gate electrode of the third transistor T3.
  • the first connection electrode 41 may simultaneously serve as the first gate signal line SL1, the second electrode of the first transistor T1, and the first electrode of the second transistor T2.
  • the first end of the first connection electrode 41 is connected to the first plate 24 (also the gate electrode of the third transistor T3) through the first via V1 and the opening 36, so that the first gate signal line SL1 and the gate electrode of the third transistor T3 Electrode connections.
  • the second end of the first connection electrode 41 is connected to the second area of the first active layer (also the first area of the second active layer) through the sixth via hole V6, so that the first plate 24 (also the third transistor The gate electrode of T3)
  • the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the gate electrode of the transistor T3 is connected such that the second gate signal line SL2 is connected to the first gate signal line SL1.
  • the first gate signal line SL1 and the second gate signal line SL2 are made of different materials.
  • the material of the first gate signal line SL1 may include metal
  • the material of the second gate signal line SL2 may include a conductive material formed by conducting semiconductor material.
  • the first gate signal line SL1, the second gate signal line SL2 and the gate electrode of the third transistor T3 are connected to form a first node N1 (also referred to as a gate signal portion).
  • the potential on the first node N1 is the same.
  • the second gate signal line SL2 may not be provided.
  • the gate electrode of the third transistor T3 and the first gate signal line SL1 constitute the first node N1.
  • the second gate signal line SL2 may be the second electrode of the first transistor T1, or may be the first electrode of the second transistor T2.
  • the shape of the second connection electrode 42 may be a strip shape with a main body portion extending along the second direction Y.
  • the first end of the second connection electrode 42 is connected to the first area of the first active layer 11 through the eighth via hole V8, and the second end of the second connection electrode 42 is connected to the first initial signal line 31 through the ninth via hole V9. connect.
  • the second connection electrode 42 may serve as the first pole of the first transistor T1, enabling the first initial signal line 31 to write the first initial signal into the first transistor T1.
  • the shape of the third connection electrode 43 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the third connection electrode 43 is connected to the seventh through hole V7.
  • the first area of the source layer 17 is connected, and the second end of the third connection electrode 43 is connected to the second initial signal line 32 through the tenth via hole V10.
  • the third connection electrode 43 may serve as the first pole of the seventh transistor T7, enabling the second initial signal line 32 to write the second initial signal into the seventh transistor T7.
  • the shape of the fourth connection electrode 44 may be a rectangular shape, and the fourth connection electrode 44 communicates with the second region of the sixth active layer 16 (also the seventh active layer) through the fourth via hole V4. 17) are connected, so that the second area of the sixth active layer 16 and the second area of the seventh active layer 17 have the same potential.
  • the fourth connection electrode 44 may serve as the second electrode of the sixth transistor T6 (or the second electrode of the seventh transistor T7), and the fourth connection electrode 44 is configured to be connected to a subsequently formed anode electrode.
  • the shape of the data signal line 45 may be a line shape in which the main body portion extends along the second direction Y.
  • the data signal line 45 is connected to the first area of the fourth active layer 14 through the fifth via V5. Therefore, the data signal line 45 can serve as the first pole of the fourth transistor T4, enabling the data signal line 45 to write the data signal.
  • the first pole of the fourth transistor T4. For example, the orthographic projection of the data signal line 45 on the substrate overlaps with the orthographic projection of the stopper 34 on the substrate.
  • the shape of the first power line 46 may be a line shape with the main body portion extending along the second direction Y.
  • the first power line 46 is connected to the first area of the fifth active layer 15 through the third via hole V3, and the first power line 46 is connected to the second plate 33 through the second via hole V2.
  • the first power line 46 may serve as the first pole of the fifth transistor T5.
  • the orthographic projection of the first power line 46 on the substrate overlaps with the orthographic projection of the stopper 34 on the substrate.
  • the first power line 46 is connected to the stopper 34 through the eleventh via hole V11. In this way, due to the first power line 46 is configured to provide a constant voltage to the pixel driving circuit, which can stabilize the voltage on the stopper 34 and play a shielding role.
  • the first power lines 46 may be designed with unequal widths.
  • the first power lines 46 with unequal widths can not only facilitate the layout of the pixel structure, but also reduce parasitics generated by the first power lines. capacitance.
  • the third conductive layer may be formed of metal material.
  • the metal material may include but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above-listed metals, such as aluminum Neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc.
  • the third conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • forming the fourth conductive layer pattern may include: depositing a fifth insulating film and a fourth conductive film on the substrate on which the foregoing pattern is formed, and patterning the fourth conductive film using a patterning process, Form a fifth insulating layer covering the third conductive layer, as shown in Figure 19, and form a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 20A and 20B.
  • Figure 20B shows the fourth conductive layer in Figure 20A. Layer plan view.
  • the fifth insulation layer may include a plurality of via holes, and the plurality of via holes may include: a second first via hole V21 and a second second via hole V22.
  • the orthographic projection of the second via hole V21 on the substrate overlaps with the orthographic projection of the first power line 46 on the substrate, and is configured to expose the surface of the first power line 46 .
  • the orthographic projection of the second via hole V22 on the substrate overlaps with the orthographic projection of the fourth connection electrode 44 on the substrate, and is configured to expose the surface of the fourth connection electrode 44 .
  • the fourth conductive layer may be called a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer of the second display area AA2 may at least include: a shield electrode 60 and a fifth connection electrode 50 .
  • the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the first gate signal line SL1 on the substrate, and a shielding block 60 is provided on one side of the shielding electrode 60 in the first direction X. -1.
  • the orthographic projection of the shielding block 60-1 on the substrate at least partially overlaps the orthographic projection of the first power line 46 on the substrate.
  • the shielding block 60-1 is connected to the first power line 46 through the second via hole V21.
  • the shield block 60-1 is configured to connect the shield electrode 60 to the first power line 46 through the second via hole V21
  • the first power line 46 is configured to provide a constant voltage to the pixel driving circuit, so that the shield electrode 60 The voltage is stable and can play a shielding role.
  • the shielding electrode 60 Since the luminescent signal of the anode is extracted through the conductive line L in the first display area AA1, the influence of the conductive line L on key nodes (such as the first node N1) can be avoided by providing the shielding electrode 60, thereby improving the display effect.
  • the orthographic projection of the first gate signal line SL1 on the substrate completely falls within the boundary range of the orthographic projection of the shield electrode 60 on the substrate.
  • the shield electrode 60 can have a better shielding effect.
  • the distance between the boundary of the orthographic projection of the first gate signal line SL1 on the substrate and the orthographic projection of the shield electrode 60 on the substrate is greater than or equal to 1.75 ⁇ m (micron).
  • the distance of the shield electrode 60 beyond the first gate signal line SL1 can be limited.
  • the distance between the boundary of the orthographic projection of the first gate signal line SL1 on the substrate and the orthographic projection of the shielding electrode SE on the substrate is greater than or equal to 2.33 ⁇ m.
  • the second gate signal line SL2 is connected to the first gate signal line SL1 to form the first node N1. Therefore, the shield electrode 60 The orthographic projection on the substrate overlaps with the orthographic projection of the second gate signal line SL2 on the substrate.
  • the orthographic projection of the shield electrode 60 on the substrate is the same as the orthographic projection of the first plate 24 (also the gate electrode of the third transistor T3) on the substrate and the first gate signal line SL1 (also the gate electrode of the third transistor T3).
  • the orthographic projections of the first region) on the substrate at least partially overlap.
  • the orthographic projection of the shield electrode 60 on the substrate partially overlaps the orthographic projection of the second gate signal line SL2 on the substrate, and the orthographic projection of the stopper 34 on the substrate partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate.
  • the orthographic projections of SL2 on the substrate partially overlap. Therefore, in the display panel shown in FIG. 20A , the shield electrode 60 and the stopper 34 form a double-layer shield on the second gate signal line SL2.
  • the orthographic projection of the shield electrode 60 on the substrate partially overlaps the orthographic projection of the stopper 34 on the substrate.
  • the orthographic projection of the shield electrode 60 on the substrate partially overlaps the orthographic projection of the first gate signal line SL1 on the substrate, and the orthographic projection of the stopper 34 on the substrate partially overlaps with the orthographic projection of the second gate signal line SL1 on the substrate.
  • the orthographic projections of SL2 on the substrate partially overlap, so that the shielding electrode 60 and the shielding electrode SE and the stopper 34 jointly serve to shield the first node N1.
  • the stopper 34 may not be provided, or the orthographic projection of the stopper 34 on the substrate and the orthographic projection of the second gate signal line SL2 on the substrate may not overlap.
  • the shape of the shielding electrode 60 may be a regular shape, for example, the shape of the shielding electrode 60 may be a rectangular shape.
  • the width of the shield electrode 60 at different positions can be made uniform, thereby making the line width of the transparent conductor passing above the shield electrode 60 consistent, and reducing the impact on the line width of the transparent conductor. Influence. Furthermore, it is helpful to improve the problem of uneven brightness.
  • the shape of the fifth connection electrode 50 may be a rectangular shape.
  • the orthographic projection of the fifth connection electrode on the substrate at least partially overlaps the orthographic projection of the fourth connection electrode 44 on the substrate.
  • the fifth connection electrode 50 may serve as an anode connection electrode.
  • the fifth connection electrode 50 is connected to the fourth connection electrode 44 through the second via hole V22 and is configured to be connected to the anode electrode formed subsequently.
  • the circuit structure layer of the second display area AA2 may include: a substrate and a first insulating layer, a semiconductor layer, and a second insulating layer sequentially stacked on the substrate. layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer.
  • the semiconductor layer may include: an active layer of a plurality of transistors in the first pixel driving circuit QD1 and the second pixel driving circuit QD2; the first conductive layer may include: a gate electrode of the plurality of transistors, a first plate of a storage capacitor, a scanning signal line, first reset control line, light emitting control line and second reset control line.
  • the second conductive layer may include: the second plate of the storage capacitor, the plate connecting line, the block, the first initial signal line and the second The initial signal line, the third conductive layer may include: first and second electrodes of a plurality of transistors, a data signal line, and a first power supply line, and the fourth conductive layer may include: an anode connection electrode and a shielding electrode. That is, the circuit structure layer of the second display area AA2 may include: a first pixel driving circuit QD1 and a second pixel driving circuit QD2.
  • the light-transmitting area of the first display area AA1 may include: a substrate and a first insulating layer, a second insulating layer, and a third insulating layer sequentially stacked on the substrate. Three insulation layers, a fourth insulation layer and a fifth insulation layer.
  • the non-light-transmitting area of the first display area AA1 may include: a substrate and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer sequentially stacked on the substrate. That is, the circuit structure layer of the first display area AA1 is not provided with a pixel driving circuit.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum. Any one or more of (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu /Mo et al.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum.
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and nitrogen. Any one or more types of silicon oxide (SiON) can be a single layer, multiple layers or composite layers.
  • the circuit structure layer is prepared on the substrate.
  • a sixth insulating film and a first transparent conductive film are deposited on the substrate on which the foregoing pattern is formed, and the first transparent conductive film is patterned through a patterning process to form a layer covering the fourth conductive layer.
  • the sixth insulating layer, and the first transparent conductive layer disposed on the sixth insulating layer, are shown in Figures 21A and 21B.
  • the first transparent conductive layer may include: a sixth connection electrode 61 .
  • the shape of the sixth connection electrode 61 may be a rectangular shape.
  • the orthographic projection of the sixth connection electrode 61 on the substrate at least partially overlaps the orthographic projection of the fifth connection electrode 50 on the substrate.
  • the sixth connection electrode 61 can serve as a transfer electrode of the first light-emitting device.
  • the sixth connection electrode 61 is connected to the fifth connection electrode 50 through the via hole of the sixth insulating layer, and is configured to be connected to the anode electrode formed subsequently.
  • the first transparent conductive layer may further include: a first transparent conductive line L1.
  • a first transparent conductive line L1 may be connected to a sixth connection electrode 61 located in the first display area AA1, and the other end of the first transparent conductive line L1 may be connected to the transition display area AAG located in the second display area AA2.
  • a sixth connection electrode 61 in the first pixel driving circuit QD1 is connected, so that the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • a first flat film is coated on the substrate on which the foregoing pattern is formed, and a first flat layer is formed through a patterning process.
  • a second transparent conductive film is deposited, and the second transparent conductive film is patterned through a patterning process to form a second transparent conductive layer disposed on the first flat layer, as shown in FIGS. 22A and 22B .
  • the second transparent conductive layer may include: a seventh connection electrode 71 .
  • the shape of the seventh connection electrode 71 may be a rectangular shape.
  • the orthographic projection of the seventh connection electrode 71 on the substrate at least partially overlaps the orthographic projection of the sixth connection electrode 61 on the substrate.
  • the seventh connection electrode 71 can serve as a transfer electrode of the first light-emitting device.
  • the seventh connection electrode 71 is connected to the sixth connection electrode 61 through the via hole of the first planar layer, and is configured to be connected to the anode electrode formed subsequently.
  • the second transparent conductive layer may further include: a second transparent conductive line L2.
  • a second transparent conductive line L2 may be connected to a seventh connection electrode 71 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to the transition display area AAG located in the second display area AA2.
  • a seventh connection electrode 71 in the first pixel driving circuit QD1 is connected, so that the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • a second flat film is coated on the substrate on which the foregoing pattern is formed, and a second flat layer is formed through a patterning process. Subsequently, a third transparent conductive film is deposited, and the third transparent conductive film is patterned through a patterning process to form a third transparent conductive layer disposed on the second flat layer, as shown in FIGS. 23A and 23B .
  • the third transparent conductive layer may include: an eighth connection electrode 81 .
  • the shape of the eighth connection electrode 81 may be a rectangular shape.
  • the orthographic projection of the eighth connection electrode 81 on the substrate at least partially overlaps the orthographic projection of the seventh connection electrode 71 on the substrate.
  • the eighth connection electrode 81 may serve as a third A transfer electrode of a light-emitting device.
  • the eighth connection electrode 81 is connected to the seventh connection electrode 71 through the via hole of the second flat layer, and is configured to be connected to the anode electrode formed subsequently.
  • the third transparent conductive layer may further include: a third transparent conductive line L3.
  • a third transparent conductive line L3 may be connected to an eighth connection electrode 81 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to an eighth connection electrode 81 located in the transition display area AAG in the second display area AA2.
  • An eighth connection electrode 81 in the first pixel driving circuit QD1 is connected, so that the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.
  • the conductive line L may include one or more of a first transparent conductive line L1, a second transparent conductive line L2, and a third transparent conductive line L3.
  • the orthographic projection of the conductive line L1 on the substrate partially overlaps the orthographic projection of the first pixel driving circuit QD1 on the substrate.
  • the orthographic projection of the conductive line L1 on the substrate partially overlaps the orthographic projection of the first gate signal line SL1 in the first pixel driving circuit QD1 on the substrate.
  • the shield electrode 60 is located between the conductive line L1 and the first gate signal line SL1.
  • the shield electrode 60 is formed, and then the conductive lines L1 (such as the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3) are formed, and then the The light-emitting device, therefore, the film layer where the shielding electrode 60 is located is between the film layer where the conductive line L1 is located and the film layer where the first gate signal line SL1 is located, and the film layer where the shielding electrode 60 is located is between the film layer where the conductive line L1 is located and the third transistor T3 Between the film layers where the gate electrode is located.
  • the conductive lines L1 such as the first transparent conductive line L1, the second transparent conductive line L2 and the third transparent conductive line L3
  • a third flat film is coated on the substrate on which the foregoing pattern is formed, and a third flat layer is formed through a patterning process.
  • an anode conductive film is deposited, and the anode conductive film is patterned through a patterning process to form an anode layer disposed on the third flat layer, as shown in Figures 24A and 24B.
  • a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) is formed through masking, exposure and development processes.
  • PDL Pixel Define Layer
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer, and the pixel openings are configured to define the light extraction area of the pixel unit, as shown in FIG. 25 .
  • An organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern.
  • the cathode is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • 24A, 24B and 25 take eight light-emitting devices in the second display area AA2 and omit part of the structure of the second pixel driving circuit QD2 as an example for schematic explanation.
  • FIG. 24C is a schematic illustration using an example of connecting the second anode of a second light-emitting device in the second display area AA2 to the second pixel driving circuit QD2.
  • the structure of the light-emitting device in the first display area AA1 may be basically similar.
  • the anode layer may include: a first anode electrode 91 , a second anode electrode 92 and a third anode electrode 93 .
  • the first anode electrode 91 may serve as an anode of the green light emitting device.
  • the orthographic projection of the first anode electrode 91 on the substrate may partially overlap with the orthographic projections of the eighth, seventh, seventh, sixth and fifth connection electrodes 81 , 71 , 61 and 50 on the substrate.
  • the second anode electrode 92 may serve as an anode of the red light emitting device.
  • the orthographic projection of the second anode electrode 92 on the substrate may partially overlap with the orthographic projections of the eighth, seventh, seventh, sixth and fifth connection electrodes 81 , 71 , 61 and 50 on the substrate.
  • the third anode electrode 93 may serve as an anode of the blue light emitting device.
  • the orthographic projection of the third anode electrode 93 on the substrate may partially overlap with the orthographic projections of the eighth, seventh, seventh, sixth and fifth connection electrodes 81 , 71 , 61 and 50 on the substrate.
  • the plurality of pixel openings may include: a first pixel opening 94 , a second pixel opening 95 , and a third pixel opening 96 .
  • the shape of the first pixel opening 94 may be a pentagon.
  • the orthographic projection of the first pixel opening 94 on the substrate falls within the boundary of the orthographic projection of the first anode electrode 91 on the substrate.
  • the shape of the second pixel opening 95 may be a hexagon.
  • the orthographic projection of the second pixel opening 95 on the substrate falls within the boundary of the orthographic projection of the second anode electrode 92 on the substrate.
  • the shape of the third pixel opening 96 may be a hexagon.
  • the orthographic projection of the third pixel opening 96 on the substrate falls within the boundary of the orthographic projection of the third anode electrode 93 on the substrate.
  • the first to third transparent conductive layers may use transparent conductive materials, such as indium tin oxide (ITO).
  • the sixth insulating layer and the first to third flat layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode can be made of transparent conductive materials.
  • the embodiments of the present disclosure do not limit this.
  • the structure of the display panel and its preparation process in the embodiments of the present disclosure are only illustrative.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to the actual application scenario.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, and is well compatible with the preparation processes in some technologies.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate. .
  • the display panel may include four or more transparent conductive layers.
  • the transparent conductive lines electrically connected to the first type of first light-emitting devices and the second type of first light-emitting devices in the first sub-region of the first display area may be located on two different transparent conductive layers, and the two different transparent conductive lines At least one transparent conductive layer may be spaced between the layers.
  • the display panel provided by the embodiment of the present disclosure, by adjusting the wiring method of the transparent conductive lines electrically connected to the first type of first light-emitting devices and the second type of first light-emitting devices in the first display area, it can be ensured that the conductive lines Uniformity, thereby improving the display uniformity of the first display area and improving the display effect of the first display area.
  • An embodiment of the present disclosure also provides a display device.
  • the display device may include: the display panel in one or more of the above exemplary embodiments.
  • the display device may further include: a sensor located on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel overlaps with the first display area of the display panel.
  • the display device may be a product with a function of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • the display device may include, but is not limited to, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a billboard, a laser printer with a display function, a picture screen, a personal digital assistant (PDA) , Personal Digital Assistant), digital cameras, camcorders, viewfinders, navigators, vehicles, large-area walls, information inquiry equipment (such as business inquiry equipment in e-government, banks, hospitals, electric power and other departments), or monitors Any product or component with display function.
  • PDA personal digital assistant
  • the embodiment of the present disclosure does not limit this.
  • the senor may include, but is not limited to: a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor or an ultrasonic sensor, etc.
  • a camera sensor a fingerprint sensor
  • a light sensor a light sensor
  • an infrared sensor a light sensor
  • ultrasonic sensor a sensor that uses a laser beam to measure the senor's temperature
  • the embodiment of the present disclosure does not limit this.
  • the above description of the display device embodiment is similar to the above description of the display panel embodiment, and has similar beneficial effects as the display panel embodiment.
  • those skilled in the art should refer to the description of the embodiments of the display panel of the present disclosure for understanding, and will not be described again here.

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Abstract

一种显示面板及显示装置，显示面板包括：基底、电路结构层、发光结构层以及多个透明导电层。透明导电层位于电路结构层和发光结构层之间，包括多条第一类导电线和多条第二类导电线，第一类导电线沿第一方向延伸的部分与屏蔽电极（60）在基底的正投影存在交叠，第二类导电线沿第一方向延伸的部分与屏蔽电极（60）在基底的正投影不存在交叠，至少一个第一类第一发光器件通过至少一条第一类导电线与至少一个第一像素驱动电路（QD1）连接，至少一个第二类第一发光器件通过至少一条第二类导电线与至少一个第一像素驱动电路（QD1）连接，第一类第一发光器件被配置为出射第一颜色光线，第二类第一发光器件被配置为出射第二颜色光线，第二颜色光线与第一颜色光线不同。

Description

显示面板及显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)和量子点发光二极管(Quantum-dot Light Emitting Diode，QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。屏下摄像技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供一种显示面板，包括：基底、叠设于所述基底上的电路结构层和发光结构层、以及设置于所述电路结构层和所述发光结构层之间的多个导电层；其中，
所述基底，包括：第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区的透光率大于所述第二显示区的透光率；
所述电路结构层，包括：位于所述第二显示区的第一栅信号线、恒压线、多个屏蔽电极和多个像素电路，所述像素电路包括驱动晶体管，所述驱动晶体管包括栅极，所述多个像素电路包括多个第一像素驱动电路；所述第一栅信号线与所述驱动晶体管的栅极相连；所述恒压线被配置为向所述多个像素电路提供第一恒定电压；所述屏蔽电极与所述恒压线相连，所述第一栅信号线在所述基底上的正投影落入所述屏蔽电极在所述基底上的正投影内；
所述多个导电层，包括：多条导电线，所述多条导电线包括：多条第一类导电线和多条第二类导电线，所述第一类导电线沿第一方向延伸的部分在所述基底的正投影与所述多个屏蔽电极中的至少一个屏蔽电极在所述基底的正投影存在交叠，所述第二类导电线沿第一方向延伸的部分在所述基底的正投影与所述多个屏蔽电极在所述基底的正投影不存在交叠；
所述发光结构层，包括：位于所述第一显示区的多个第一发光器件，所述多个第一发光器件包括：多个第一类第一发光器件和多个第二类第一发光器件，所述多个第一类第一发光器件中的至少一个第一类第一发光器件通过所述多条第一类导电线中的至少一条第一类导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接，所述多个第二类第一发光器件中的至少一个第二类第一发光器件通过所述多条第二类导电线中的至少一条第二类导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接，所述第一像素驱动电路被配置为驱动所述第一发光器件发光，所述第一类第一发光器件被配置为出射第一颜色光线，所述第二类第一发光器件被配置为出射第二颜色光线，所述第二颜色光线与所述第一颜色光线不同。
另一方面，本公开实施例还提供一种显示装置，包括：如上述实施例中所述的显示面板。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的其它优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例中的显示面板的结构示意图；
图2为本公开实施例中的显示面板的平面示意图；
图3为本公开实施例中的像素驱动电路的等效电路图；
图4为本公开实施例中的显示面板的第一种局部示意图；
图5为一些技术中第一显示区中导电线经过屏蔽电极的示意图；
图6A为本公开实施例中显示面板的第二种局部示意图；
图6B为本公开实施例中显示面板的第三种局部示意图；
图6C为本公开实施例中显示面板的第四种局部示意图；
图7为本公开示例性实施例中的第一发光器件与第一像素驱动电路的第一种连接示意图；
图8为图7中第一透明导电层的第一透明导电线的连接示意图；
图9为图7中第二透明导电层的第二透明导电线的连接示意图；
图10为图7中第三透明导电层的第三透明导电线的连接示意图；
图11为图7中金属导电层的金属导电线的连接示意图；
图12为本公开示例性实施例中的第一发光器件与第一像素驱动电路的第二种连接示意图；
图13为本公开示例性实施例中的第一发光器件与第一像素驱动电路的第三种连接示意图；
图14为本公开实施例形成半导体层后的示意图；
图15A为本公开实施例形成第一导电层后的示意图；
图15B为图15A中第一导电层的平面示意图；
图16A为本公开实施例形成第二导电层后的示意图；
图16B为图16A中第二导电层的平面示意图；
图17为本公开实施例形成第四绝缘层后的示意图；
图18A为本公开实施例形成第三导电层后的示意图；
图18B为图18A中第三导电层的平面示意图；
图19为本公开实施例形成第五绝缘层后的示意图；
图20A为本公开实施例形成第四导电层后的示意图；
图20B为图20A中第四导电层的平面示意图；
图21A为本公开实施例形成第一透明导电层后的示意图；
图21B为图21A中第一透明导电层的平面示意图；
图22A为本公开实施例形成第二透明导电层后的示意图；
图22B为图22A中第二透明导电层的平面示意图；
图23A为本公开实施例形成第三透明导电层后的示意图；
图23B为图23A中第三透明导电层的平面示意图；
图24A为本公开实施例形成阳极层后的第一种示意图；
图24B为图23A中阳极层的平面示意图；
图24C为本公开实施例形成阳极层后的第二种示意图；
图25为本公开实施例形成像素定义层后的示意图。
具体实施方式
本文描述了多个实施例，但是该描述是示例性的，而不是限制性的，在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在示例性实施方式中进行了讨论，但是所公开的特征的许多其它组合方式是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其它特征或元件结合使用，或可以替代任何其它实施例中的任何其它特征或元件。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅电极(栅极或控制极)、漏电极(漏电极端子、漏区域或漏极)以及源电极(源电极端子、源区域或源极)这三个端子的元件。晶体管在漏电极与源电极之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为了区分晶体管除栅电极(栅极或控制极)之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极且第二极可以为源电极，或者，第一极可以为源电极且第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
本公开实施例中的晶体管均可以为薄膜晶体管(Thin Film Transistor， TFT)或场效应管(Field Effect Transistor，FET)或其它特性相同的器件。例如，本公开实施例中使用的薄膜晶体管可以包括但不限于氧化物晶体管(Oxide TFT)或者低温多晶硅薄膜晶体管(Low Temperature Poly-silicon TFT，LTPS TFT)等。这里，本公开实施例对此不做限定。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”、“近似”，是指不严格限定界限，允许工艺和测量误差范围内的情况。例如，在本公开中，“大致相同”是指数值相差10％以内的情况。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本公开实施例中，第一方向X可以是指显示区域中栅线的延伸方向或者水平方向，第二方向Y可以是指显示区域中数据线的延伸方向或者竖直方向，第三方向Z可以是指垂直于显示面板平面的方向或者显示面板的厚度方向等。其中，第一方向X和第二方向Y可以相互垂直，第一方向X和第三方向Z可以相互垂直。
随着显示技术的发展，全面屏或窄边框等产品以其较大的屏占比和超窄边框，已逐步成为显示产品的发展趋势。对于智能终端等产品，通常会设置摄像头传感器、或者指纹传感器等传感器。为提高屏占比，全面屏或窄边框产品通常采用屏下摄像头技术(Full display with camera，FDC)或者屏下指纹技术，将摄像头等传感器放置于显示面板的屏下摄像区域(Under Display Camera，UDC)，屏下摄像区域不仅具有一定的透过率，而且具有显示功能，实现摄像头区全显示(Full Display in Camera，FDC)。
图1为一种显示面板的结构示意图。如图1所示，在平行于显示面板的平面上，显示面板的显示区域AA可以包括：第一显示区AA1和第二显示区AA2，第二显示区AA2可以位于第一显示区AA1的至少一侧。例如，第二 显示区AA2可以至少部分围绕第一显示区AA1。例如，第二显示区AA2可以包括：过渡显示区AAG，过渡显示区AAG与第一显示区AA1相邻。例如，第一显示区AA1的位置可以与传感器的位置相对应，被配置为显示画面和透过光线，透过的光线被传感器接收，第一显示区AA1又可称为传感器对应区、屏下摄像显示区或者透光显示区等。例如，第二显示区AA2被配置为显示画面，第二显示区AA2又可称为正常分辨率显示区、正常子像素区、或者低透过显示区等。例如，过渡显示区AAG被配置为显示画面和配置信号走线，信号走线与透光显示区中的信号线连接，以将这些信号线引出，过渡显示区AAG又可称为虚拟(Dummy)子像素区。
在一种示例性实施例中，第一显示区AA1的光线透过率高于第二显示区AA2的光线透过率。第一显示区AA1的光线透过率高于过渡显示区AAG的光线透过率。其中，光线透过率是指光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。如此，由于第一显示区AA1的位置可以与传感器的位置相对应，传感器在显示面板的正投影与第一显示区AA1存在交叠区域，可以使得较多的光线能够穿过显示面板而被传感器接收。例如，“传感器在显示面板的正投影与第一显示区AA1存在交叠区域”可以是指传感器在显示面板的正投影的一部分位于第一显示区AA1以内，或者，传感器在显示面板的正投影的全部位于第一显示区AA1以内，或者，传感器的感光窗口在显示面板的正投影位于第一显示区AA1以内等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第一显示区AA1和第二显示区AA2的分辨率可以相同，或者，第一显示区AA1的分辨率低于第二显示区AA2的分辨率。其中，分辨率(Pixels Per Inch，PPI)是指单位面积所拥有像素的数量，可以称为像素密度，PPI数值越高，代表显示面板能够以越高的密度显示画面，画面的细节就越丰富。
在一种示例性实施例中，第一显示区AA1可以位于显示面板的显示区域的上部、下部、或者边缘位置等。例如，第一显示区AA1在可以位于显示面板的显示区域的顶部正中间位置，第二显示区AA2可以围绕在第一显示区AA1的四周。或者，第一显示区AA1可以位于显示面板的显示区域的左上 角或者右上角等其它位置，第二显示区AA2可以围绕在第一显示区AA1的至少一侧(例如，一侧、上下两侧或者左右两侧等)。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在平行于显示面板的平面内，第一显示区AA1的形状可以是如下任意一种或多种：正方形、矩形、多边形、圆形、椭圆形半圆形或者五边形等。举例来说，显示面板的显示区域的形状可以为矩形，例如圆角矩形，第一显示区AA1可以为圆形。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在平行于显示面板的平面内，过渡显示区AAG的外轮廓的形状可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，传感器可以包括但不限于：摄像头传感器、指纹传感器、光线传感器、红外线传感器、超声波传感器、激光雷达(LIDAR，Light Detection and Ranging)传感器或者雷达(Radar)传感器等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在垂直于显示面板的平面上，第一显示区AA1可以包括：设置在基底上的第一电路结构层和设置在第一电路结构层远离基底一侧的第一发光结构层。第二显示区AA2可以包括设置在基底上的第二电路结构层和设置在第二电路结构层远离基底一侧的第二发光结构层。
在一种示例性实施例中，第一显示区AA1的第一电路结构层包括叠设的多个绝缘层，第一电路结构层可以称为复合绝缘层。第一显示区AA1的第一发光结构层可以包括多个功能子像素，功能子像素可以包括第一发光器件sp1，第一发光器件sp1可以至少包括第一阳极，至少一个功能子像素的第一阳极通过导电线(例如，透明导电线)与第二显示区AA2中的过渡显示区AAG中至少一个第一像素驱动电路QD1连接，第一像素驱动电路QD1被配置为通过导电线向所连接的第一发光器件sp1输出相应的电流，第一发光器件sp1被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在一种示例性实施例中，第二显示区AA2的第二电路结构层可以包括：多个第一像素驱动电路QD1和多个第二像素驱动电路QD2，第二电路结构 层可以称为驱动结构层。第二显示区AA2中设置有第一像素驱动电路QD1的区域可以称为过渡显示区AAG。第二显示区AA2的第二发光结构层可以包括多个正常子像素，正常子像素可以包括第二发光器件sp2，第二发光器件sp2可以至少包括第二阳极，至少一个正常子像素的第二阳极与至少一个第二像素驱动电路QD2连接，第二像素驱动电路QD2被配置为直接向所连接的第二发光器件sp2输出相应的电流，第二发光器件sp2被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
例如，第一发光器件sp1与驱动其的第一像素驱动电路QD1位于不同的显示区，因此，第一发光器件sp1可称作非原位驱动发光器件，第一像素驱动电路QD1可称为非原位像素驱动电路。例如，第二发光器件sp2与驱动其的第二像素驱动电路QD2均位于第二显示区AA2，因此，第二发光器件sp2可称作原位驱动发光器件，第二像素驱动电路QD2可称为原位像素驱动电路。
在一种示例性实施例中，显示面板的显示区域可以包括：以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个可以包括：多个子像素。一个子像素可以为亮度可控的最小部分。至少一个子像素可以包括：发光器件和与发光器件连接的像驱动素电路，像素驱动电路被配置为驱动所连接的发光器件发光。
在一种示例性实施例中，发光器件可以是发光二极管(Light Emitting Diode，LED)、有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光器件可以为OLED，发光器件在其对应的像素驱动电路的驱动下发出红光、绿光、蓝光、或者白光等。
在一种示例性实施例中，以发光器件为OLED为例，发光器件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光器件的阳极可以与对应的像素驱动电路电连接。
在一种示例性实施例中，发光器件发光的颜色可由本领域技术人员根据实际应用场景而定。例如，多个像素单元P的至少一个可以包括三个子像素，三个子像素可以包括：红色(R)子像素、绿色(G)子像素和蓝色(B)子 像素。又例如，多个像素单元P的至少一个可以包括：四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。这里，本公开实施例对此不做限定。
在一种示例性实施例中，发光器件的形状可以是矩形、菱形、五边形或六边形等。
在一种示例性实施例中，像素单元中的多个子像素可以采用水平并列、竖直并列、X形、十字形或品字形等排布方式。例如，以像素单元包括三个子像素为例，三个子像素可以采用水平并列、竖直并列或品字形方式排列等。例如，以像素单元包括四个子像素为例，四个子像素可以采用水平并列、竖直并列、正方形(Square)或钻石形(Diamond)方式排列等。例如，如图2所示，以四个子像素包括：一个红色子像素、一个蓝色子像素和两个绿色子像素为例，四个子像素可以采用钻石形(Diamond)方式排列，形成RGGB像素排布。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第一显示区AA1中像素单元的排布方式与第二显示区AA2中像素单元的排布方式可以相同，或者可以不同。第一显示区AA1中像素单元的中包括的子像素的个数与第二显示区AA2中像素单元中包括的子像素的个数可以相同，或者可以不同。第一显示区AA1中像素单元的中包括的子像素的排布方式与第二显示区AA2中像素单元中包括的子像素的排布方式可以相同，或者可以不同。这里，本公开实施例对此不做限定。
在一种示例性实施例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
在一种示例性实施例中，以本示例性实施例的像素驱动电路采用7T1C结构为例进行说明，图3为本公开实施例中的像素驱动电路的等效电路图，如图3所示，像素驱动电路可以包括：7个晶体管(第一晶体管T1到第七晶体管T7)和一个存储电容Cst。像素驱动电路可以与8个信号线(扫描信号线GL、数据信号线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2)连接。其中，第三晶体管T3又可以称为驱动晶体管，第四晶体管T4又可称为数据写入晶体管，第二晶体管T2又可称为阈值补偿 晶体管，第五晶体管T5又可称为第一发光控制晶体管，第六晶体管T6又可称为第二发光控制晶体管，第一晶体管T1又可称为第一复位晶体管，第七晶体管T7又可称为第二复位晶体管。
在一种示例性实施例中，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在一种示例性实施例中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一种示例性实施例中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一种示例性实施例中，如图3所示，显示面板可以包括：扫描信号线GL、数据信号线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一种示例性实施例中，第一电源线PL1可以配置为向像素驱动电路提供恒定的第一电压信号VDD，第二电源线PL2可以配置为向像素驱动电路提供恒定的第二电压信号VSS，并且第一电压信号VDD 大于第二电压信号VSS。扫描信号线GL可以配置为向像素驱动电路提供扫描信号SCAN，数据信号线DL可以配置为向像素驱动电路提供数据信号DATA，发光控制线EML可以配置为向像素驱动电路提供发光控制信号EM，第一复位控制线RST1可以配置为向像素驱动电路提供第一复位控制信号RESET1，第二复位控制线RST2可以配置为向像素驱动电路提供第二复位控制信号RESET2。在一种示例性实施例中，在第n行像素驱动电路中，第一复位控制线RST1可以与第n-1行像素驱动电路的扫描信号线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。第二复位控制线RST2可以与第n行像素驱动电路的扫描信号线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)相同。在一种示例性实施例中，第n行像素驱动电路所电连接的第二复位控制线RST2与第n+1行像素驱动电路所电连接的第一复位控制线RST1可以为一体结构。其中，n为大于0的整数。如此，可以减少显示面板的信号线，实现显示面板的窄边框设计。然而，本实施例对此并不限定。
在一种示例性实施例中，第一初始信号线INIT1可以配置为向像素驱动电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素驱动电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一种示例性实施例中，为了节省布线，第一电源线PL1可以作为恒压线。例如，在其它示例中，为了节省布线，也可以第一初始信号线INIT1作为恒压线。恒压线的示例不限于第一电源线PL1和第一初始信号线INIT1，只要是像素电路中提供恒定电压的信号线均可以作为恒压线。
在一种示例性实施例中，扫描信号线GL、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2可以沿水平方向延伸，第一电源线PL1、第二电源线PL2和数据 信号线DL可以沿竖直方向延伸。
在一种示例性实施例中，如图3所示，第三晶体管T3与发光器件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光器件EL发光。第四晶体管T4的栅极与扫描信号线GL电连接，第四晶体管T4的第一极与数据信号线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第二晶体管T2的栅极与扫描信号线GL电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第一电源线PL1电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光器件EL的阳极电连接。第一晶体管T1与第三晶体管T3的栅极电连接，并配置为对第三晶体管T3的栅极进行复位，第七晶体管T7与发光器件EL的阳极电连接，并配置为对发光器件EL的阳极进行复位。第一晶体管T1的栅极与第一复位控制线RST1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连接。第七晶体管T7的栅极与第二复位控制线RST2电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与发光器件EL的阳极电连接。存储电容Cst的第一电容极板与第三晶体管T3的栅极电连接，存储电容Cst的第二电容极板与第一电源线PL1电连接。
在一种示例性实施例中，如图3所示，像素驱动电路可以包括：第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1为存储电容Cst、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光器件EL的连接点。第四节点N4为阳极连接节点。
在一种示例性实施例中，发光器件EL可以是有机电致发光二极管(OLED)，包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
下面以图3所示的像素驱动电路包括的多个晶体管均为P型晶体管为例，对图3所示的像素驱动电路的工作过程进行说明。
在一种示例性实施例中，在一帧显示时间段，像素驱动电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描信号线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7断开。此阶段发光器件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描信号线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据信号线DL输出数据信号DATA。此阶段由于存储电容Cst的第一电容极板为低电平，因此，第三晶体管T3导通。扫描信号SCAN为低电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通，使得数据信号线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线DL输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电容极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据信号线DL输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光器件EL的阳极，对发光器件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光器件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一晶体管T1断开。发光控制信号线 EML提供的发光控制信号EM为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描信号线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL的阳极提供驱动电压，驱动发光器件EL发光。
在像素电路驱动过程中，流过第三晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光器件EL的电流与第三晶体管T3的阈值电压无关。因此，本实施例的像素驱动电路可以较好地补偿第三晶体管T3的阈值电压。
图4为本公开实施例中的显示面板的第一种局部示意图，为图1中Q区域的放大图，示意了第一显示区AA1中邻近过渡显示区AAG附近区域的平面结构，并且示意了第二显示区AA2中过渡显示区AAG及其附近区域的平面结构。
在一种示例性实施例中，如图4所示，第一显示区AA1可以只设置第一发光器件sp1，而不设置驱动第一发光器件sp1的第一像素驱动电路QD1，使得第一显示区AA1既可以进行显示，同时可以透过光线。例如，第一发光器件sp1可以至少包括第一阳极，第二显示区AA2中的过渡显示区AAG中至少一个第一像素驱动电路QD1通过导电线L(例如，透明导电线)与至少 一个第一发光器件sp1的第一阳极连接。导电线L可以从第一显示区AA1延伸至第二显示区AA2中的过渡显示区AAG。如此，通过将驱动第一发光器件sp1的第一像素驱动电路QD1设置在第二显示区AA2中的过渡显示区AAG，可以减少像素驱动电路对光线的遮挡，从而可以增加第一显示区AA1的透过率。例如，以第一像素驱动电路QD1为图3所示的7T1C的像素驱动电路为例，导电线L(例如，透明导电线)的一端可以与第一像素驱动电路QD1的第四节点N4(即阳极连接节点)电连接，导电线L的另一端可以与第一发光器件sp1的第一阳极电连接。
在一种示例性实施例中，如图4所示，第二显示区AA2可以包括：多个第一像素驱动电路QD1、多个第二像素驱动电路QD2和多个第二发光器件sp2，多个第二像素驱动电路QD2中的至少一个第二像素驱动电路QD2被配置为与第二显示区AA2中的至少一个第二发光器件sp2连接，第二像素驱动电路QD2被配置为直接向所连接的第二发光器件sp2输出相应的电流，使该第二发光器件sp2发出相应亮度的光。即，与第二像素驱动电路QD2电连接的第二发光器件sp2可以和该第二像素驱动电路QD2均位于第二显示区AA2内，第二发光器件sp2的全部或部分可以位于该第二显示区AA2内。例如，至少一个第二像素驱动电路QD2在基底的正投影与至少一个第二发光器件sp2在基底的正投影可以至少部分交叠。
在一种示例性实施例中，如图4所示，第二显示区AA2中过渡显示区AAG可以包括：多个第一像素驱动电路QD1，多个第一像素驱动电路QD1中的至少一个第一像素驱动电路QD1可以通过导电线L与第一显示区AA1中的至少一个第一发光器件sp1连接，至少一个第一像素驱动电路QD1被配置为通过导电线L向所连接的第一发光器件sp1输出相应的电流，使该第一发光器件sp1发出相应亮度的光。即，与第一像素驱动电路QD1电连接的第一发光器件sp1可以和该第一像素驱动电路QD1位于不同显示区内。例如，至少一个第一像素驱动电路QD1在基底的正投影与至少一个第一发光器件sp1在基底的正投影可以没有交叠。在一种示例性实施例中，如图4所示，过渡显示区AAG还可以包括：多个第二像素驱动电路QD2和多个第二发光器件sp2，多个第二像素驱动电路QD2中的至少一个第二像素驱动电路QD2 可以与过渡显示区AAG中的至少一个第二发光器件sp2连接，第二像素驱动电路QD2被配置为直接向所连接的第二发光器件sp2输出相应的电流，使该第二发光器件sp2发出相应亮度的光。在一种示例性实施例中，相邻第一像素驱动电路QD1之间可以设置一个或多个第二像素驱动电路QD2，例如，相邻第一像素驱动电路QD1之间可以设置两个第二像素驱动电路QD2，或者，如图4所示，相邻第一像素驱动电路QD1之间可以设置四个第二像素驱动电路QD2等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图4所示，过渡显示区AAG还可以包括：无效像素驱动电路QD0，设置无效像素驱动电路可以利于提高多个膜层的部件在刻蚀工艺中的均一性，保证显示面板均一性。例如，无效像素驱动电路与其所在行或所在列的第一像素驱动电路QD1和第二像素驱动电路QD2的结构可以大致相同，只是其不与任何发光器件电连接。
在一种示例性实施例中，导电线L可以采用透明导电材料。例如，透明导电材料可以采用导电氧化物材料，比如，氧化铟锡(ITO)等。这里，本公开实施例对此不做限定。
其中，本公开示例性实施例中所说的像素驱动电路是按照基底结构层划分的区域，本公开中所说的发光器件是按照发光结构层划分的区域。例如，发光器件与驱动该发光器件的像素驱动电路两者的位置可以是对应的，或者，发光器件与驱动该发光器件的像素驱动电路两者的位置可以是不对应的。例如，过渡显示区AAG的多个第二发光器件sp2可以按照常规间距的排列方式正常排布，而过渡显示区AAG的部分第二像素驱动电路QD2可以按照小间距的排列方式紧凑排布，为驱动第一发光器件sp1的第一像素驱动电路QD1留出排布空间。此时，过渡显示区AAG的第二发光器件sp2与第二像素驱动电路QD2两者的位置是不对应的。又例如，多个第一发光器件sp1设置在第一显示区AA1，而第一像素驱动电路QD1设置在过渡显示区AAG，此时，第一显示区AA1的第一发光器件sp1与驱动第一发光器件sp1的第一像素驱动电路QD1两者的位置是不对应的。
在一种示例性实施例中，在过渡显示区AAG中，可以通过减小第二像素驱动电路QD2的尺寸来获得设置第一像素驱动电路QD1的区域。例如， 可以通过减小第二像素驱动电路QD2在第一方向X上的尺寸来获得设置第一像素驱动电路QD1的区域；或者，可以通过减小第二像素驱动电路QD2在第二方向Y上的尺寸来获得设置第一像素驱动电路QD1的区域；或者，可以通过减小第二像素驱动电路QD2在第一方向X和第二方向Y上的尺寸来获得设置第一像素驱动电路QD1的区域。这里，本公开实施例对此不做限定。
例如，以通过减小第二像素驱动电路QD2在第一方向X上的尺寸来获得设置第一像素驱动电路QD1的区域为例，例如，如图4所示，可以将原来的每a列像素驱动电路通过沿第一方向X压缩，从而新增一列像素驱动电路的排布空间，且压缩前的a列像素驱动电路和压缩后的a+1列像素驱动电路所占用的空间可以是相同。其中，a可以为大于1的整数，例如，a可以等于2、3或者4等。例如，通常可以采用在第一方向X上2压1、3压1或者4压1的方式排布第二像素驱动电路QD2和第一像素驱动电路QD1，将在第一方向X上的2个、3个或4个第二像素驱动电路QD2压缩，留出1个设置第一像素驱动电路QD1的位置。这里，本公开实施例对此不做限定。此时，第二像素驱动电路QD2在第一方向X上的尺寸可以小于第二发光器件sp2在第一方向X上的尺寸。
又例如，以通过减小第二像素驱动电路QD2在第二方向Y上的尺寸来获得设置第一像素驱动电路QD1的区域为例，可以将原来的b行像素驱动电路通过沿第二方向Y压缩，从而新增一行像素驱动电路的排布空间，且压缩前的b行像素驱动电路和压缩后的b+1行像素驱动电路所占用的空间是相同。其中，b可以为大于1的整数。例如，如b可以等于2、3或者4等。此时，第二像素驱动电路QD2在第二方向Y上的尺寸可以小于第二发光器件sp2在第二方向Y上的尺寸。
在一种示例性实施例中，由于过渡显示区AAG不仅设置有与第一发光器件sp1电连接的第一像素驱动电路QD1，还设置有与第二发光器件sp2电连接的第二像素驱动电路QD2，因此，过渡显示区AAG的像素驱动电路的数量可以大于第一显示区AA1的第一发光器件sp1的数量。
在一种示例性实施例中，为了减小导电线(如ITO走线)之间的电容对 第一节点N1的串扰，在显示面板中设置了屏蔽电极60。图5为一些技术中第一显示区AA1中导电线经过屏蔽电极的示意图，如图5所示，导电线下方的屏蔽电极60为不规则形状并且屏蔽电极60有反光，导致经过屏蔽电极60的多个导电线L(1到7)的线宽不均一，其中，经过屏蔽电极60较宽的位置的导电线的线宽较细，而经过屏蔽电极60较窄的位置的导电线的线宽较宽。这样，就会导致相同行、相邻像素的导电线之间的电容差异较大，导致显示不均匀(mura)问题。
如图5所示，以经过屏蔽电极60较宽的位置的导电线为导电线7，且经过屏蔽电极60较窄的位置的导电线为导电线3为例，本公开发明人通过实现测得表1所示经过屏蔽电极60的较宽处的导电线的线宽和经过屏蔽电极60的较窄处的导电线的线宽。在表1中，CD(7)是指不同显示面板的导电线7经过屏蔽电极60的线宽，表示经过屏蔽电极60的最宽处的导电线的线宽；CD(3)是指不同显示面板的导电线3经过屏蔽电极60的线宽，表示经过屏蔽电极60的最窄处的导电线的线宽。
表1实测导电线L经过屏蔽电极的线宽
显示面板 CD(7) CD(3)
Panel1 1.85 1.90
Panel2 1.76 2.03
Panel3 1.67 1.89
Panel4 1.71 1.94
Panel5 1.82 1.98
Panel6 1.85 1.98
Panel7 1.80 1.98
平均线宽 1.78 1.96
通过对表1所示数据进行分析可知，由于屏蔽电极60形状不规则，即屏蔽电极60的宽度不一致，使得导电线的线宽(critical dimension，CD)相差0.2um(微米)左右，从而会导致在一个像素单元中导电线(如ITO走线) 之间的电容相差0.1fF左右。而且，以像素驱动电路采用图3所示的7T1C的像素驱动电路为例，导电线L的一端可以与第一像素驱动电路QD1的第四节点N4(即阳极连接节点)电连接，导电线L的另一端可以与第一发光器件sp1的阳极电连接。由于导电线L从第一显示区AA1延伸至过渡显示区AAG来实现第一像素驱动电路QD1与第一发光器件sp1的电连接，因此，导电线L的长度较长，最终一个像素单元中导电线(如ITO走线)之间的电容可能会相差约几百fF。这样，在低灰阶下，由于启亮时间较长，第四节点N4(即阳极连接节点)节点电容较大，相同行、相邻像素的导电线(如ITO走线)之间的电容差异较大，会导致启亮时间受影响非常大，导致mura问题。
在一些示例中，在显示面板中，导电线的电容量差异较大。位于第一显示区AA1的多个发光器件的导电线的长度不同，会导致发不同颜色光的发光器件的电容量差异变化不同。与发红光的发光器件相连的导电线的电容量差异和与发蓝光的发光器件相连的导电线的电容量差异相比，与发绿光的发光器件相连的导电线的电容量差异较大。由于与发绿光的发光器件相连的导电线的电容量差异较大，会造成发绿光的发光器件的发光时间减少，从而显示面板出现亮度差异，造成显示不良。在低灰阶下，发绿光的发光器件的不良程度大于发红光的发光器件的不良程度，且发红光的发光器件的不良程度大于发蓝光的发光器件的不良程度。例如，在相同灰阶下，驱动发蓝光的发光器件的驱动电流可以大于驱动发红光的发光器件的驱动电流，且驱动发红光的发光器件的驱动电流可以大于驱动发绿光的发光器件的驱动电流。驱动发绿光的发光器件的驱动电流是三基色发光器件中最小的，因此，在出射不同光的发光器件的第四节点N4(即阳极连接节点)的电容相同的情况下，发绿光的发光器件相比发红光的发光器件和发蓝光的发光器件的启亮晚。在低灰阶下，采用由近及远连接方式会导致部分发绿光的发光器件未启亮，影响显示效果。
本公开实施例提供一种显示面板，该显示面板可以包括：基底、叠设于基底上的电路结构层和发光结构层、以及设置于电路结构层和发光结构层之间的多个导电层；其中，基底，包括：第一显示区和第二显示区，第二显示 区位于第一显示区的至少一侧，第一显示区的透光率大于第二显示区的透光率；电路结构层，包括：位于第二显示区的第一栅信号线、恒压线、多个屏蔽电极和多个像素电路，像素电路包括驱动晶体管，驱动晶体管包括栅极，多个像素电路包括多个第一像素驱动电路；第一栅信号线与驱动晶体管的栅极相连；恒压线被配置为向多个像素电路提供第一恒定电压；屏蔽电极与恒压线相连，第一栅信号线在基底上的正投影落入屏蔽电极在基底上的正投影内；多个导电层，包括：多条导电线，多条导电线包括：多条第一类导电线和多条第二类导电线，第一类导电线沿第一方向延伸的部分在基底的正投影与多个屏蔽电极中的至少一个屏蔽电极在基底的正投影存在交叠，第二类导电线沿第一方向延伸的部分在基底的正投影与多个屏蔽电极在基底的正投影不存在交叠；发光结构层，包括：位于第一显示区的多个第一发光器件，多个第一发光器件包括：多个第一类第一发光器件和多个第二类第一发光器件，多个第一类第一发光器件中的至少一个第一类第一发光器件通过多条第一类导电线中的至少一条第一类导电线与多个第一像素驱动电路中的至少一个第一像素驱动电路连接，多个第二类第一发光器件中的至少一个第二类第一发光器件通过多条第二类导电线中的至少一条第二类导电线与多个第一像素驱动电路中的至少一个第一像素驱动电路连接，第一像素驱动电路被配置为驱动第一发光器件发光，第一类第一发光器件被配置为出射第一颜色光线，第二类第一发光器件被配置为出射第二颜色光线，第二颜色光线与第一颜色光线不同。
如此，在本公开示例性实施例所提供的显示面板中，一方面，通过设置与第一类第一发光器件所连接的第一类导电线与屏蔽电极在基底的正投影存在交叠，可以保持第一类导电线的线宽的均一性，可以使得第一类导电线的电容差异较小。另一方面，通过设置与第二类第一发光器件所连接的第二类导电线与屏蔽电极在基底的正投影没有交叠，可以保持第二类导电线的线宽的均一性，可以使得第二类导电线的电容差异较小。如此，通过优化布线设置，可以改善亮度差异，提高显示效果。
在一种示例性实施例中，屏蔽电极的形状可以为规则形状，例如，屏蔽电极的形状可以为矩形。如此，通过设置屏蔽电极的形状为矩形，可以保证 第一类导电线的走线环境一致，可以提升第一类导电线的线宽的均一性，可以使得第一类导电线的电容差异较小。
在一种示例性实施例中，第一显示区的多个第一发光器件可以包括：多组第一发光器件。多组第一发光器件的每一组中的第一发光器件可以沿第一方向X排布，多组第一发光器可以沿第二方向Y排布。第二方向Y与第一方向X交叉，例如，第二方向与第一方向相互垂直。其中，在至少一组第一发光器件sp1中，与多个第一类第一发光器件电连接的多个第一像素驱动电路QD1，比与多个第二类第一发光器件电连接的多个第一像素驱动电路QD1中的每一个都更靠近第一显示区。如此，可以使得第一类第一发光器件连接的导电线的长度差异减小，从而可以减轻或避免显示不良。
在一种示例性实施例中，以导电层为透明导电层为例，显示面板可以包括三个透明导电层，三个透明导电层可以包括：沿着远离基底一侧依次设置的第一透明导电层、第二透明导电层和第三透明导电层。第一透明导电层可以包括多条第一透明导电线，第二透明导电层可以包括多条第二透明导电线，第三透明导电层可以包括多条第三透明导电线。例如，第一透明导电线沿第一方向延伸的部分与第二透明导电线沿第一方向延伸的部分和第三透明导电线沿第一方向延伸的部分在基底的正投影可以没有交叠，即没有交叠走线。例如，第三透明导电线沿第一方向延伸的部分与第二透明导电线沿第一方向延伸的部分在基底的正投影可以没有交叠，即没有交叠走线。例如，第一透明导电线沿第一方向X延伸的部分在第二方向Y的尺寸、第二透明导电线沿第一方向X延伸的部分在第二方向Y的尺寸和第三透明导电线沿第一方向X延伸的部分在第二方向Y的尺寸可以大致相同。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第一类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第一类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第一类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第一类第一发光器件通 过第二透明导电线与多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第一类第一发光器件通过第二透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第一类第一发光器件通过第一透明导电线与第二显示区的多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第一类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第一类第一发光器件通过第一透明导电线与第二显示区的多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第二类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第二类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第二类第一发光器件电连接的透明导电线与靠近第一显示区中心的多个第一类第一发光器件电连接的透明导电线的类型是相同的，或者，靠近第一显示区边缘的多个第二类第一发光器件电连接的透明导电线与靠近第一显示区边缘的多个第一类第一发光器件电连接的透明导电线的类型是相同的。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第二类第一发光器件电连接的透明导电线与靠近第一显示区中心的多个第一类第一发光器件电连接的类型是不相同的，或者，靠近第一显示区边缘的多个第二类第一发光器件电连接的透明导电线与靠近第一显示区边缘的多个第一类第一发光器件电连接的透明导电线的类型是不相同的。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第二类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第二类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第一类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第一类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接，位于靠近第一显示区中心的多个第一类第一发光器件与靠近第一显示区边缘的多个第一类第一发光器件之间的多个第一类第一发光器件通过第二透明导电线与多个第一像素驱动电路电连接；在第一显示区的至少一组第一发光器件中，靠近第一显示区中心的多个第二类第一发光器件通过第一透明导电线与多个第一像素驱动电路电连接，靠近第一显示区边缘的多个第二类第一发光器件通过第三透明导电线与多个第一像素驱动电路电连接，位于靠近第一显示区中心的多个第二类第一发光器件与靠近第一显示区边缘的多个第二类第一发光器件之间的多个第二类第一发光器件通过第二透明导电线与多个第一像素驱动电路电连接。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，多个第一类第一发光器件电连接的透明导电线在第二方向上位于该组第一发光器件的转接电极的一侧。
在一种示例性实施例中，在第一显示区的至少一组第一发光器件中，多个第二类第一发光器件电连接的透明导电线在第二方向上位于该组第一发光器件的转接电极的另一侧。
在一种示例性实施例中，第一显示区包括：第一子区域和第二子区域，第二子区域位于第一子区域的至少一侧，并与第二显示区相邻；多个第一发光器件中的位于第一子区域的至少一个第一发光器件，通过多个导电层的导电线与多个第一像素驱动电路中的至少一个第一像素驱动电路连接；多个第一发光器件中的位于第二子区域的至少一个第一发光器件，通过电路结构层中的金属导电层的导电线与多个第一像素驱动电路中的至少一个第一像素驱动电路连接。
在一种示例性实施例中，金属导电层与屏蔽电极位于同一膜层。
在一种示例性实施例中，屏蔽电极的形状可以为矩形。
在一种示例性实施例中，发光结构层还可以包括：位于第二显示区的多个第二发光器件；多个像素电路还包括：多个第二像素驱动电路，多个第二 像素驱动电路中的至少一个第二像素驱动电路与多个第二发光器件中的至少一个第二发光器件电连接，至少一个第二像素驱动电路被配置为驱动至少一个第二发光器件发光。
在一种示例性实施例中，第二显示区可以包括：过渡显示区和正常显示区，过渡显示区位于正常显示区的至少一侧，并与第一显示区相邻；过渡显示区可以包括：多个第一像素驱动电路；正常显示区包括：多个第二发光器件中的至少部分和多个第二像素驱动电路中的至少部分，多个第二发光器件中的至少部分与多个第二像素驱动电路中的至少部分连接。
在一种示例性实施例中，过渡显示区可以包括：多个子过渡区；发光结构层还可以包括：位于多个子过渡区中靠近第一显示区的至少一个子过渡区的多个第二发光器件；电路结构层还可以包括：位于多个子过渡区中靠近第一显示区的至少一个子过渡区的多个第二像素驱动电路；多个第二像素驱动电路中的至少一个第二像素驱动电路与多个第二发光器件中的至少一个第二发光器件电连接，至少一个第二像素驱动电路被配置为驱动至少一个第二发光器件发光。
在一种示例性实施例中，发光结构层还可以包括：位于第二显示区的多个第二发光器件；电路结构层还可以包括：位于第二显示区的多个第二像素驱动电路，多个第二像素驱动电路中的至少一个第二像素驱动电路与多个第二发光器件中的至少一个第二发光器件电连接，至少一个第二像素驱动电路被配置为驱动至少一个第二发光器件发光。
在一种示例性实施例中，第一颜色光线可以为绿光，第二颜色光线可以包括：红光和蓝光中的至少一种。例如，第一类第一发光器件可以包括：绿色第一发光器件sp1_g，绿色第一发光器件sp1_g被配置为出射绿色光线；第二类第一发光器件可以包括：蓝色第一发光器件sp1_b和红色第一发光器件sp1_r，蓝色第一发光器件sp1_b被配置为出射蓝色光线，红色第一发光器件sp1_r被配置为出射红色光线。
下面以显示面板包括三个透明导电层、第一类第一发光器件包括：绿色第一发光器件sp1_g，第二类第一发光器件包括：蓝色第一发光器件sp1_b和红色第一发光器件sp1_r为例，结合附图对本公开实施例中的显示面板进 行说明。
在一种示例性实施例中，可以通过减小绿色第一发光器件sp1_g的阳极连接节点连接的导电线长度，使得阳极连接节点的电容减小，从而，保证绿色第一发光器件sp1_g能够正常启亮。在下述示例中，以绿色第一发光器件sp1_g电连接的第一像素驱动电路QD1最靠近第一显示区AA1为例，即与绿色第一发光器件sp1_g电连接的第一像素驱动电路QD1优先靠近第一显示区AA1排布。其中，在本公开示例性实施例中，“元件A靠近元件B”可以指元件A与元件B之间不具有其它的元件A和其它的元件B，但是可以具有除了元件A和元件B之外的其它元件。例如，本公开示例性实施例所描述的“绿色第一发光器件sp1_g电连接的第一像素驱动电路QD1靠近第一显示区AA1”，可以指绿色第一发光器件sp1_g电连接的第一像素驱动电路QD1和第一显示区AA1之间，不具有与红色第一发光器件sp1_r电连接的第一像素驱动电路QD1和蓝色第一发光器件sp1_b连接的第一像素驱动电路QD1，但是可以具有第二像素驱动电路QD2或者无效像素驱动电路QD0等其它像素驱动电路。
在一种示例性实施例中，第一显示区AA1的多个第一发光器件sp1可以包括：多个绿色第一发光器件sp1_g、多个蓝色第一发光器件sp1_b以及多个红色第一发光器件sp1_r。绿色第一发光器件sp1_g被配置为出射绿色光线，蓝色第一发光器件sp1_b被配置为出射蓝色光线，红色第一发光器件sp1_r被配置为出射红色光线。其中，在至少一组第一发光器件sp1中，与绿色第一发光器件sp1_g电连接的多个第二像素驱动电路QD2，比与蓝色第一发光器件sp1_b和红色第一发光器件sp1_r电连接的多个第二像素驱动电路QD2中的每一个都更靠近第一显示区AA1。如此，可以使得与绿色第一发光器件sp1_g电连接的导电线的长度差异减小，如此，可以减轻或避免显示不良。
图6A为本公开实施例中显示面板的第二种局部示意图，图6B为本公开实施例中显示面板的第三种局部示意图，图6C为本公开实施例中显示面板的第四种局部示意图，示意了部分显示区域。如图6A至图6C所示，第一显示区AA1可以具有沿第二方向Y延伸的中心线CL，第一显示区AA1可以沿中心线CL被划分为左半区域和右半区域，左半区域和右边区域内第一发 光器件连接的导电线可以关于该中心线CL大致对称。其中，在图6A至图6C中除了示意除了第一显示区域AA1中的部分发光器件之外，还示意出了过渡显示区AAG中靠近第一显示区AA1的子过渡区中的部分发光器件。
在一种示例性实施例中，如图6A和图6B所示，第一显示区AA1可以包括：第一子区域AA1a和第二子区域AA1b。第二子区域AA1b可以包围第一子区域AA1a，并与过渡显示区AAG相邻。即，第二子区域AA1b可以位于第一子区域AA1a和过渡显示区AAG之间。第二子区域AA1b可以为第一显示区AA1的边缘区域，第一子区域AA1a可以为第一显示区AA1的中心区域。
在一种示例性实施例中，如图6A所示，第一显示区AA1的形状可以约为圆形，第一子区域AA1a的形状可以为直径小于第一显示区AA1的圆形，第一子区域AA1a可以为围绕第一子区域AA1a的圆环。如图6B所示，第一显示区AA1的形状可以约为近似圆形，第一子区域AA1a可以为直径小于第一显示区AA1的近似圆形，第一子区域AA1a可以为围绕第一子区域AA1a的近似圆环。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图6A和图6B所示，多个第一发光器件中的位于第一子区域AA1a的至少一个第一发光器件连接的导电线所在膜层与多个第一发光器件中的位于第一子区域AA1a的至少一个第一发光器件连接的导电线所在膜层不同。例如，多个第一发光器件中的位于第一子区域AA1a的至少一个第一发光器件，通过透明导电层的导电线与多个第一发光器件中的至少一个第一发光器件电连接；多个第一发光器件中的位于第一子区域AA1a的至少一个第一发光器件通过电路结构层中的金属导电层的导电线与多个第一像素驱动电路中的至少一个第一像素驱动电路连接。例如，金属导电层的导电线可以为第一源漏金属层(SD1)的导电线或者第二源漏金属层(SD2)的导电线。这里，本公开实施例对此不做限定。
在一种示例性实施例中，金属导电层的导电线与屏蔽电极位于同一膜层。例如，屏蔽电极与金属导电层的导电线可以均位于第二源漏金属层。
在一种示例性实施例中，如图6A和图6B所示，在一组第一发光器件中，第一子区域AA1a内的绿色第一发光器件sp1_g的数目可以大于或等于第二 子区域AA1b内的绿色第一发光器件sp1_g的数目。
在一种示例性实施例中，第二显示区AA2中的过渡显示区AAG可以包括：多个子过渡区；发光结构层还可以包括：位于多个子过渡区中靠近第一显示区的至少一个子过渡区的多个第二发光器件；电路结构层还可以包括：位于多个子过渡区中靠近第一显示区的至少一个子过渡区的多个第二像素驱动电路；多个第二像素驱动电路中的至少一个第二像素驱动电路与多个第二发光器件中的至少一个第二发光器件电连接，至少一个第二像素驱动电路被配置为驱动至少一个第二发光器件发光。
例如，图6A和图6B中示意出中心线CL两侧的48列发光器件，其中，针对在中心线CL左侧中，第1至第39列发光器件可以位于第一子区域AA1a，第40至第44列发光器件可以位于第二子区域AA1b，第1至第39列发光器件以及第40至第44列发光器件为第一发光器件sp1，可以通过导电线L横向排布从第一显示区AA1延伸至第二显示区AA2中的过渡显示区AAG中，与过渡显示区AAG中的第一像素驱动电路QD1连接。例如，第1至第39列发光器件所采用的导电线所在膜层与第40至第44列发光器件所采用的导电线所在膜层可以不相同。例如，针对第一显示区AA1中的发光器件，如图6A至图13所示，第一子区域AA1a内的第1至第39列发光器件可以采用透明导电层中的导电线横向排布驱动方式，在透明导电层的排布空间利用完成之后，第二子区域AA1b内的第40至第44列发光器件可以采用金属导电层(如第二源漏金属层SD2)的导电线横向排布驱动方式。例如，针对过渡显示区AAG中靠近第一显示区AA1的发光器件，第45至第48列发光器件可以位于过渡显示区AAG中的最靠近第一显示区AA1的子过渡区AAGn，第45至第48列发光器件可以为第二发光器件sp2，采用原位驱动方式，即第45至第48列发光器件直接与位于过渡显示区AAG中的第二像素驱动电路QD2连接，如此，既不会影响透过率，也保证了过渡显示区AAG到第一显示区AA1的良好过渡。
在一种示例性实施例中，如图6C所示，第一显示区AA1可以包括：沿远离第一显示区AA1中心依次设置的第一拉线区AA1-1、第二拉线区AA1-2、第三拉线区AA1-3和第四拉线区AA1-4。第一拉线区AA1-1可以为第一显 示区AA1的中相对靠近第一显示区AA1的几何中心的区域，第四拉线区AA1-4为第一显示区AA1的中相对靠近第一显示区AA1的边缘的区域。例如，以第一显示区AA1的形状为近似圆形为例，第一拉线区AA1-1、第二拉线区AA1-2、第三拉线区AA1-3和第四拉线区AA1-4的形状可以为近似半圆形的一部分。第一拉线区AA1-1在第二方向Y上的尺寸可以大于第二拉线区AA1-2在第二方向Y上的尺寸，第二拉线区AA1-2在第二方向Y上的尺寸可以大于第三拉线区AA1-3在第二方向Y上的尺寸，第二拉线区AA1-2在第二方向Y上的尺寸可以大于第四拉线区AA1-4在第二方向Y上的尺寸。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图6C所示，第一拉线区AA1-1中的第一发光器件sp1可以采用第一透明导电层的第一导电线L1进行电连接，第二拉线区AA1-2可以采用第二透明导电层的第二导电线L2进行电连接，第三拉线区AA1-3可以采用第三透明导电层的第三导电线L3进行电连接，第四拉线区AA1-4可以采用金属导电层(如第二源漏金属层)的导电线进行电连接。
例如，图6C中示意出中心线CL两侧的48列发光器件，其中，针对在中心线CL左侧中，第1至第13列发光器件可以位于第一拉线区AA1-1，第14至第26列发光器件可以位于第二拉线区AA1-2，第27至第39列发光器件可以位于第三拉线区AA1-3，第40至第44列发光器件可以位于第四拉线区AA1-4，第1至第39列发光器件以及第40至第44列发光器件为第一发光器件sp1，可以通过导电线L横向排布从第一显示区AA1延伸至第二显示区AA2中的过渡显示区AAG中，与过渡显示区AAG中的第一像素驱动电路QD1连接。例如，针对第一显示区AA1中的发光器件，如图6C所示，位于第一拉线区AA1-1的第1至第13列发光器件可以采用第一透明导电层中的第一透明导电线横向排布驱动方式，在第一透明导电层的排布空间利用完成之后，位于第二拉线区AA1-2的第14至第26列发光器件可以采用第二透明导电层中的第二透明导电线横向排布驱动方式，在第二透明导电层的排布空间利用完成之后，位于第三拉线区AA1-3的第27至第39列发光器件可以采用第三透明导电层中的第三透明导电线横向排布驱动方式，在透明导电层的排布空间利用完成之后，位于第四拉线区AA1-4的第40至第44列发光 器件可以采用金属导电层(如第二源漏金属层SD2)的导电线横向排布驱动方式。例如，针对过渡显示区AAG中靠近第一显示区AA1的发光器件，第45至第48列发光器件可以位于过渡显示区AAG中的最靠近第一显示区AA1的子过渡区AAGn，第45至第48列发光器件可以为第二发光器件sp2，采用原位驱动方式，即第45至第48列发光器件直接与位于过渡显示区AAG中的第二像素驱动电路QD2连接，如此，既不会影响透过率，也保证了过渡显示区AAG到第一显示区AA1的良好过渡。
在本示例中，第一显示区AA1中靠近中心的第一发光器件sp1，可以采用透明导电层的导电线进行电连接，在利用完透明导电层的走线排布空间之后，第一显示区AA1中靠近边缘的第一发光器件sp1，可以采用金属导电层(如第二源漏金属层)的导电线进行电连接。如此，可以保证孔径不变，走线环境均匀，不会增加mask(掩膜版)。而且，由于金属导电层(如第二源漏金属层)的负载较小，对周边走线环境影响较小。此外，由于对处于边界位置的发光器件采用金属导电层(如第二源漏金属层)的导电线进行电连接，对第一显示区AA1的透过率影响较小。
下面参考图6A至图6C所示布局，结合附图对第一显示区AA1中发光器件的连接方式进行说明。在下述示例中，是以第一显示区AA1的一组第一发光器件在左半区域内的部分与第二显示区AA2中过渡显示区AAG中一行第一像素驱动电路QD1的连接关系为例进行示意的，省略了其它结构。以不同线型示意不同层的透明导电线，第一透明导电线L1是以实线示意的，第二透明导电线L2是以虚线示意的，第三透明导电线L3是以点划线示意的。
图7为本公开示例性实施例中的第一发光器件与第一像素驱动电路QD1的第一种连接示意图。图8为图7中第一透明导电层的第一透明导电线L1的连接示意图。图9为图7中第二透明导电层的第二透明导电线L2的连接示意图。图10为图7中第三透明导电层的第三透明导电线L3的连接示意图。图11为图7中金属导电层的金属导电线L4的连接示意图。图12为本公开示例性实施例中的第一发光器件与第一像素驱动电路QD1的第二种连接示意图。图13为本公开示例性实施例中的第一发光器件与第一像素驱动电路QD1的第三种连接示意图。下面结合图6A至图13对发光器件的连接方式进 行说明。
在一种示例性实施例中，如图7和图8所示，第一显示区AA1的第一子区域AA1a内的绿色第一发光器件sp1_g可以通过位于第一透明导电层的第一透明导电线L1与第二显示区AA2中的过渡显示区AAG中的第一像素驱动电路QD1电连接。如图7和图9所示，第一子区域AA1a内的绿色第一发光器件sp1_g可以通过位于第二透明导电层的第二透明导电线L2与过渡显示区AAG中的第一像素驱动电路QD1电连接。如图7和图10所示，第一子区域AA1a内的绿色第一发光器件sp1_g可以通过位于第三透明导电层的第三透明导电线L3与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7所示，靠近第一显示区AA1中心的多个绿色第一发光器件sp1_g通过第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接电连接，靠近第二显示区AA1边缘的多个绿色第一发光器件sp1_g通过第三透明导电线L3与过渡显示区AAG中的第一像素驱动电路QD1电连接电连接，即沿第一方向X远离过渡显示区AAG的多个绿色第一发光器件sp1_g通过第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接电连接，靠近过渡显示区AAG的多个绿色第一发光器件sp1_g通过第三透明导电线L3与过渡显示区AAG中的第一像素驱动电路QD1电连接电连接。如图7所示，绿色第一发光器件sp1_g电连接的第一透明导电线L1、第二透明导电线L2和第三透明导电线L3在第二方向Y上位于该组第一发光器件的阳极连接电极的同一侧，例如上侧。如图7所示，绿色第一发光器件sp1_g电连接的第一透明导电线L1、第二透明导电线L2和第三透明导电线L3在显示面板平面的正投影与屏蔽电极60在显示面板平面的正投影可以存在交叠。其中，屏蔽电极60被配置为屏蔽导电线之间的电容对第一节点N1的串扰。
在一种示例性实施例中，如图7和图8所示，第一子区域AA1a内的红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于第一透明导电层的第一透明导电线L1与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7和图9所示，第一子区域AA1a内的红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于第二透明导电层的第二透明导电线 L2与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7和图10所示，第一子区域AA1a内的红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于第三透明导电层的第三透明导电线L3与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7至图10所示，第一子区域AA1a内的靠近过渡显示区AAG的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于第三透明导电层的第三透明导电线L3与过渡显示区AAG的第一像素驱动电路QD1电连接，第一子区域AA1a内的远离过渡显示区AAG的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于第一透明导电层的第一透明导电线L1与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7所示，红色第一发光器件sp1_r电连接的第一透明导电线L1、第二透明导电线L2与第三透明导电线L3在第二方向Y上位于该组第一发光器件的转接电极的同一侧，例如，下侧。如图7所示，蓝色第一发光器件sp1_b电连接的第一透明导电线L1、第二透明导电线L2与第三透明导电线L3在第二方向Y上位于该组第一发光器件的同一侧，例如，下侧。如图7所示，红色第一发光器件sp1_r电连接的第一透明导电线L1、第二透明导电线L2与第三透明导电线L32以及蓝色第一发光器件sp1_b电连接的第一透明导电线L1、第二透明导电线L2与第三透明导电线L3在第二方向Y上位于该组第一发光器件的转接电极的同一侧，例如，下侧。如图7所示，红色第一发光器件sp1_r和蓝色第一发光器件sp1_b电连接的第一透明导电线L1、第二透明导电线L2与第三透明导电线L3在显示面板平面的正投影与屏蔽电极60在显示面板平面的正投影可以没有交叠。
在一种示例性实施例中，如图7所示，绿色第一发光器件sp1_g电连接的第二透明导电线L2与蓝色第一发光器件sp1_b电连接的第二透明导电线L2在第二方向Y上位于该组第一发光器件的转接电极的两侧。绿色第一发光器件sp1_g电连接的第二透明导电线L2与红色第一发光器件sp1_r电连接的第二透明导电线L2在第二方向Y上位于该组第一发光器件的转接电极的两侧。
在一种示例性实施例中，如图7和图11所示，第二子区域AA1b内的绿色第一发光器件sp1_g可以通过位于金属导电层的金属导电线L4与过渡显示 区AAG的第一像素驱动电路QD1电连接。如图7和图11所示，第二子区域AA1b内的红色第一发光器件sp1_r和蓝色第一发光器件sp1_b可以通过位于金属导电层的金属导电线L4与过渡显示区AAG的第一像素驱动电路QD1电连接。如图7和图11所示，绿色第一发光器件sp1_g、红色第一发光器件sp1_r和蓝色第一发光器件sp1_b电连接的金属导电线L4位于在第二方向Y上位于该组第一发光器件的转接电极的同一侧，例如下侧。如图7和图11所示，第一发光器件sp1电连接的金属导电线L4在显示面板平面的正投影与屏蔽电极60在显示面板平面的正投影可以不存在交叠。如图7和图11所示，第一发光器件sp1电连接的金属导电线L4在显示面板平面的正投影与红色第一发光器件sp1_r和蓝色第一发光器件sp1_b电连接的第一透明导电线L1、第二透明导电线L2和第三透明导电线L3在显示面板平面的正投影可以存在交叠。如图7和图11所示，第一发光器件sp1电连接的金属导电线L4在显示面板平面的正投影与绿色第一发光器件sp1_g电连接的第一透明导电线L1、第二透明导电线L2和第三透明导电线L3在显示面板平面的正投影可以不存在交叠。
在一种示例性实施例中，第一透明导电层的走线排布空间可以排布约10至15条第一透明导电线L1，例如，如图7和图8所示，第一透明导电层的走线排布空间可以排布13条第一透明导电线L1。第二透明导电层的走线排布空间可以排布约10至15条第二透明导电线L2，例如，如图7和图9所示，第二透明导电层的走线排布空间可以排布13条第二透明导电线L2。第三透明导电层的走线排布空间可以排布约10至15条第三透明导电线L3，例如，如图7和图10所示，第三透明导电层的走线排布空间可以排布13条第三透明导电线L3。例如，如图7和图11所示，金属导电层的的走线排布空间可以排布约5条金属导电线L4。这里，本公开实施例对此不做限定。
例如，金属导电层可以为第一源漏金属(SD1)层或者第二源漏金属层(SD2)。例如，第一源漏金属(SD1)层可以包括：像素驱动电路中多个晶体管的第一极和第二极、数据信号线以及第一电源线等。例如，第二源漏金属层(SD2)可以包括：屏蔽电极60。
在一种示例性实施例中，如图7、图12和图13所示，在第二显示区AA2 中相对靠近第一显示区AA1的第二发光器件sp2采用原位驱动方式，即过渡显示区中相对靠近第一显示区AA1的第二发光器件sp2与驱动该第二发光器件sp2的第二像素驱动电路QD2均位于过渡显示区AAG中。例如，如图7所示，第45列至第48发光器件采用原位驱动方式。
在一种示例性实施例中，如图12所示，靠近第一显示区AA1中心的多个绿色第一发光器件sp1_g通过第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接，靠近第一显示区AA1边缘(即第一显示区AA1的相对靠近第二显示区AA2)的多个绿色第一发光器件sp1_g通过第二透明导电层的第二透明导电线L2与过渡显示区AAG中的第一像素驱动电路QD1电连接。靠近第一显示区AA1中心的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b通过第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接，靠近第一显示区AA1边缘(即第一显示区AA1的相对靠近第二显示区AA2)的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b通过第二透明导电层的第二透明导电线L2与过渡显示区AAG中的第一像素驱动电路QD1电连接。
在一种示例性实施例中，如图13所示，靠近第一显示区AA1中心的多个绿色第一发光器件sp1_g通过第二透明导电层的第二透明导电线L2与过渡显示区AAG中的第一像素驱动电路QD1电连接，靠近第一显示区AA1边缘(即第一显示区AA1的相对靠近第二显示区AA2)的多个绿色第一发光器件sp1_g通过第一透明导电层的第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接。靠近第一显示区AA1中心的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b通过第一透明导电线L1与过渡显示区AAG中的第一像素驱动电路QD1电连接电连接，靠近第一显示区AA1边缘(即第一显示区AA1的相对靠近第二显示区AA2)的多个红色第一发光器件sp1_r和蓝色第一发光器件sp1_b通过位于第三透明导电层的第三透明导电线L3与过渡显示区AAG中的第一像素驱动电路QD1电连接。
在本示例中，针对第一显示区AA1的第一发光器件sp1，第一子区域AA1a内的靠近中心的第一发光器件sp1可以采用第一透明导电层的第一透明导电线L1进行电连接，在利用完第一透明导电层的走线排布空间之后， 可以采用第二透明导电层的第二透明导电线L2进行电连接，在利用完第二透明导电层的走线排布空间之后，第一子区域AA1a内相对靠近过渡显示区AAG的第一发光器件sp1可以采用第三透明导电层的第三透明导电线L3进行电连接，在利用完第三透明导电层的走线排布空间之后，第二子区域AA1b内可以采用金属导电层的金属导电线L4进行电连接。当然，还可以采用其它排布方式，例如，靠近过渡显示区AAG的第一发光器件sp1可以采用第二透明导电层的第二透明导电线L2进行电连接。这里，本公开实施例对此不做限定。
下面通过显示面板的制备过程的示例说明显示面板的结构。本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一种示例性实施例中，在垂直于显示面板的方向上，第二显示区AA2和第一显示区AA1的显示面板可以包括：基底、设置在基底的电路结构层、第一透明导电层、第二透明导电层、第三透明导电层和发光结构层。第一显示区AA1的电路结构层可以包括：多个绝缘层。第二显示区AA2的电路结构层可以包括：多个第一像素驱动电路和多个第二像素驱动电路。第一透明导电层和第二透明导电层之间可以设置第一平坦层，第二透明导电层和第三透明导电层之间可以设置第二平坦层。第三透明导电层和发光结构层之间可以设置第三平坦层。例如，第一平坦层至第三平坦层可以为有机材料层。发光结构层可以包括：阳极层、像素定义层、有机发光层和阴极层。阳极层可以包括：位于第一显示区AA1的第一发光器件的阳极、位于第二显示区AA2 的第二发光器件的阳极。例如，第一发光器件的阳极面积可以小于出射相同颜色光的第二发光器件的阳极面积，以提高第一显示区域AA1的光透过率。在另一些示例中，显示面板可以包括两个或更多个透明导电层。这里，本公开实施例对此不做限定。
在一种示例性实施例中，显示面板的制备过程可以包括如下操作。下面以第二显示区AA2的一个第一像素驱动电路QD1和一个第二像素驱动电路QD2为例进行说明。其中，过渡显示区AAG的第一像素驱动电路QD1可以采用如图3所示的像素驱动电路。此外，第二像素驱动电路QD2与第一像素驱动电路QD1的结构可以基本上相同，无效像素驱动电路与第一像素驱动电路QD1的结构可以基本上类似，但无效像素驱动电路无过孔连接，不接信号，本领域技术人员可参见相关描述而理解，本公开实施例在此不做过多赘述。
(1)提供基底。
在一种示例性实施例中，基底可以是柔性基底，或者可以是刚性基底。例如，刚性基底可以包括但不限于玻璃、石英中的一种或多种。例如，柔性基底可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。例如，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，被配置为提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
(2)在基底上形成半导体层图案。
在一种示例性实施例中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图14所示。
在一种示例性实施例中，第一绝缘层可以称为缓冲(Buffer)层，被配置为提高基底的抗水氧能力。半导体层可以称为有源(Active，ACT)层。
在一种示例性实施例中，如图14所示，第二显示区AA2的半导体层可以至少包括：像素驱动电路的多个晶体管的有源层，例如，第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第三晶体管T3的第三有源层13、第四晶体管T4的第四有源层14、第五晶体管T5的第五有源层15、第六晶体管T6的第六有源层16、以及第七晶体管T7的第七有源层17。
在一种示例性实施例中，如图14所示，一个像素驱动电路的多个晶体管的有源层(例如，第一有源层11至第七有源层17)可以为相互连接的一体结构。
在一种示例性实施例中，如图14所示，第二有源层12和第六有源层16可以位于第三有源层13的第一方向X的一侧，第四有源层14和第五有源层15可以位于第三有源层13的第一方向X的反方向的一侧。第五有源层15、第六有源层16和第七有源层17位于第三有源层13的第二方向Y的一侧，第一有源层11、第二有源层12和第四有源层14可以位于第三有源层13的第二方向Y的反方向的一侧。
在一种示例性实施例中，如图14所示，第一有源层11的形状可以呈“n”字形。第二有源层12的形状可以呈倒“L”字形。第三有源层13的形状可以呈“Ω”字形。第四有源层14、第五有源层15、第六有源层16和第七有源层17的形状均可以呈“I”字形。
在一种示例性实施例中，每个晶体管的有源层可以包括：至少一个沟道区、以及位于沟道区两侧的第一区和第二区。例如，沟道区可以不掺杂杂质，并具有半导体特性。第一区和第二区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。在一些示例中，有源层的掺杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以被配置为电连接晶体管。
在一种示例性实施例中，如图14所示，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第五有源层15的第一区15-1和第七有源层17的第一区17-1可以单独设置。第一有源层11的第二区11-2可以同时作为第二有源层12的第一区12-1和第二栅信号部SL2，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区 15-2，第三有源层13的第二区13-2可以同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2可以同时作为第七有源层17的第二区17-2。
在一种示例性实施例中，半导体层可以采用金属氧化物材料制成。例如，金属氧化物材料可以包括但不限于：包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。例如，半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料制成，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。例如，半导体层可以是单层、双层或者多层等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第一绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
(3)形成第一导电层图案。
在一种示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图15A和图15B所示，图15B为图15A中第一导电层的平面示意图。
在一种示例性实施例中，第二绝缘层可以称为栅极绝缘(GI)层，第一导电层可以称为第一栅金属(Gate1)层。
在一种示例性实施例中，如图15A和图15B所示，第二显示区AA2的的第一导电层可以至少包括：扫描信号线21、第一复位控制线22、发光控制线23、存储电容Cst的第一极板24和第二复位控制线25。
在一种示例性实施例中，存储电容的第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三有源层13在基底上的正投影至少部分交叠。在一种示例性实施例中，第一极板24 可以同时作为存储电容的一个第一极板和第三晶体管T3的栅电极。例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一种示例性实施例中，与第三晶体管T3的栅电极连接的第二晶体管T2和第一晶体管T1可以为双栅型薄膜晶体管，可以有助于降低第三晶体管T3的栅电极的漏电流。
在一种示例性实施例中，扫描信号线21、第一复位控制线22、第二复位控制线25和发光控制线23的形状可以是主体部分沿着第一方向X延伸的线形状。扫描信号线21和发光控制线23可以位于第一极板24的第二方向Y两侧。第一复位控制线22可以位于扫描信号线21的远离第一极板24的一侧。第二复位控制线25可以位于扫描信号线21的远离第一极板24的一侧。
在一种示例性实施例中，扫描信号线21与第二有源层12相重叠的区域可以作为第二晶体管T2的一个栅电极，扫描信号线21在基底上的正投影与第二有源层12在基底上的正投影存在第一交叠区域。例如，扫描信号线21设置有朝向第一复位控制线22一侧凸起的栅极块21-1，栅极块21-1与第二有源层12相重叠的区域可以作为第二晶体管T2的另一个栅电极，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在第二交叠区域，如此，可以形成双栅结构的第二晶体管T2。例如，扫描信号线21与同一行的像素驱动电路的第二晶体管T2的栅电极可以为相互连接的一体结构。
在一种示例性实施例中，扫描信号线21与第四有源层14相重叠的区域可以作为第四晶体管T4的栅电极，扫描信号线21在基底上的正投影与第四有源层14在基底上的正投影存在交叠区域。例如，扫描信号线21与同一行的像素驱动电路的第四晶体管T4的栅电极可以为相互连接的一体结构。
在一种示例性实施例中，第一复位控制线22与第一有源层11相重叠的区域可以作为双栅结构的第一晶体管T1的栅电极，第一复位控制线22在基底上的正投影与第一有源层11在基底上的正投影存在交叠区域。例如，第一复位控制线22与同一行的像素驱动电路的第一晶体管T1的栅电极可以为相互连接的一体结构。
在一种示例性实施例中，第二复位控制线25与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，第二复位控制线25在基底上的正投影与 第二有源层12在基底上的正投影存在交叠区域。例如，第二复位控制线25与同一行的像素驱动电路的第七晶体管T7的栅电极可以为相互连接的一体结构。
在一种示例性实施例中，发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23中与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。发光控制线23在基底上的正投影与第五有源层15在基底上的正投影存在交叠区域，发光控制线23在基底上的正投影与第六有源层16在基底上的正投影存在交叠区域。例如，如此，发光控制线23与同一行的像素驱动电路的第五晶体管T5的栅电极和第六晶体管T6的栅电极可以为相互连接的一体结构。
在一种示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
在一种示例性实施例中，第二导电层可以采用金属材料形成。例如，金属材料可以包括但不限于：银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或者上述列出的金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等。例如，第二导电层可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
(4)形成第二导电层图案。
在一种示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图16A和图16B所示，图16B为图16A中第二导电层的平面示意图。
在一种示例性实施例中，第三绝缘层可以称为栅极绝缘(GI)层，第二导电层可以称为第二栅金属(Gate2)层。
在一种示例性实施例中，如图16A和图16B所示，第二显示区AA2的的第二导电层至少可以包括：第一初始信号线31、第二初始信号线32、存储电容Cst的第二极板33、挡块34和极板连接线35。
在一种示例性实施例中，存储电容的第二极板33可以位于本像素驱动电路的扫描信号线21和发光控制线23之间，第一方向X或第一方向X的反方向上相邻像素驱动电路的第二极板33之间可以通过极板连接线35连接，极板连接线35的第一端与本像素驱动电路的第二极板33连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻像素驱动电路的第二极板33连接，即极板连接线35被配置为使一单元行上相邻像素驱动电路的第二极板33相互连接。
在一种示例性实施例中，通过极板连接线可以使一单元行中多个像素驱动电路的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源连接线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示面板的显示不良，保证显示面板的显示效果。
在一种示例性实施例中，第二极板33的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板33在基底上的正投影与第一极板24在基底上的正投影至少部分交叠，第一极板24和第二极板33构成像素驱动电路的存储电容。
在一种示例性实施例中，第二极板33上设置有开口36，开口36可以位于第二极板33的中部。例如，开口36可以为矩形，使第二极板33形成环形结构。例如，开口36暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口36在基底上的正投影。例如，开口36可以被配置为容置后续形成的第一过孔，第一过孔位于开口36内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极通过第一过孔与第一极板24连接。
在一种示例性实施例中，第一初始信号线31和第二初始信号线32的形状可以是主体部分沿着第一方向X延伸的线形状。
在一种示例性实施例中，挡块34可以位于扫描信号线21与第一初始信 号线31之间。例如，挡块34的形状可以为折线状。例如，挡块34可以包括：沿第一方向X延伸的第一电极段和沿第二方向Y延伸的第二电极段。例如，挡块34在基底上的正投影与后续形成的数据信号线45在基底上的正投影至少部分交叠，从而，挡块34可以屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。例如，挡块34在基底上的正投影与第一有源层11的第二区11-2(也是第二有源层12的第一区12-1和第二栅信号部SL2)在基底上的正投影至少部分交叠，从而，挡块34可以对第二栅信号部SL2进行遮挡，起到屏蔽作用，如此，可以屏蔽电压跳变对关键节点的影响，避免电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。例如，左侧的挡块34的第二电极段可以延伸至左侧的像素驱动电路(图中未示出)，对其第二晶体管T2的导电连接部进行遮挡，右侧的挡块34的第一电极段延伸至图中左侧像素驱动电路，对其第二晶体管T2的导电连接部进行遮挡。当然，在另外一些实施例中，也可以不设置挡块34，或者，挡块34在基底上的正投影与第二栅信号线SL2在基底上的正投影不交叠。
(5)形成第四绝缘层图案。
在一种示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图17所示。
在一种示例性实施例中，第四绝缘层可以称为层间介质(ILD)层。
在一种示例性实施例中，如图17所示，多个过孔可以包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在一种示例性实施例中，第一过孔V1在基底上的正投影位于第二极板33的开口36在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在一种示例性实施例中，第二过孔V2在基底上的正投影位于第二极板33在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板33的表面，第二过孔V2被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第二极板33连接。
在一种示例性实施例中，第三过孔V3在基底上的正投影位于第五有源层55的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层55的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层55的第一区连接。
在一种示例性实施例中，第四过孔V4在基底上的正投影位于第六有源层66的第二区在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层16的第二区(也是第七有源层的第二区)的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六有源层16的第二区连接。
在一种示例性实施例中，第五过孔V5在基底上的正投影位于第四有源层14的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层14的第一区的表面，第五过孔V5被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有源层14的第一区连接。
在一种示例性实施例中，第六过孔V6在基底上的正投影位于第一有源层11的第二区在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层11的第二区(也是第二有源层12的第一区)的表面，第六过孔V6被配置为使后续形成的第一晶体管T1的第二极(第二晶体管T2的第一极)通过该过孔与第一有源层11的第二区连接。
在一种示例性实施例中，第七过孔V7在基底上的正投影位于第七有源层17的第一区在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层17的第一区的表面。 第七过孔V7被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层的第一区连接。
在一种示例性实施例中，第八过孔V8在基底上的正投影位于第一有源层11的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层11的第一区的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层11的第一区连接。
在一种示例性实施例中，第九过孔V9在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面，第九过孔V9被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线31连接。
在一种示例性实施例中，第十过孔V10在基底上的正投影位于第二初始信号线32在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层被刻蚀掉，暴露出第二初始信号线32的表面，第十过孔V10被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第二初始信号线32连接。
在一种示例性实施例中，第十一过孔V11在基底上的正投影位于挡块34在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出挡块34的表面，第十一过孔V11被配置为使后续形成的第一电源线通过该过孔与挡块34连接。
在一种示例性实施例中，第二像素驱动电路QD2或者无效像素驱动电路的过孔图案与第一像素驱动电路QD1的过孔图案可以基本上相同。
(6)形成第三导电层图案。
在一种示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图18A和图18B所示，图18B为图18A中第三导电层的平面示意图。
在一种示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
在一种示例性实施例中，第二显示区AA2的第三导电层可以包括：第一 连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、数据信号线45和第一电源线46。
在一种示例性实施例中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状。在一种示例性实施例中，第一连接电极41可以作为第一栅信号线SL1，第一栅信号线SL1和第三晶体管T3的栅电极连接。在一种示例性实施例中，第一连接电极41可以同时作为第一栅信号线SL1、第一晶体管T1的第二极和第二晶体管T2的第一极。第一连接电极41的第一端通过第一过孔V1和开口36与第一极板24(也是第三晶体管T3的栅电极)连接，使得第一栅信号线SL1和第三晶体管T3的栅电极连接。第一连接电极41的第二端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，使第一极板24(也是第三晶体管T3的栅电极)第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位，如此，使得第一晶体管T1的第二极、第二晶体管T2的第一极和第三晶体管T3的栅电极连接，并使得第二栅信号线SL2与第一栅信号线SL1相连。
例如，第一栅信号线SL1和第二栅信号线SL2的材料不同。例如，第一栅信号线SL1的材料可以包括金属，第二栅信号线SL2的材料可以包括半导体材料经导体化形成的导电材料。
例如，第一栅信号线SL1、第二栅信号线SL2和第三晶体管T3的栅电极相连，构成第一节点N1(也称为栅信号部)。第一节点N1上的电位相同。当然，在其它的实施例中，可以不设置第二栅信号线SL2，此情况下，第三晶体管T3的栅电极以及第一栅信号线SL1构成第一节点N1。例如，第二栅信号线SL2可以为第一晶体管T1的第二极，或者，可以为第二晶体管T2的第一极。
在一种示例性实施例中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的条形状。第二连接电极42的第一端通过第八过孔V8与第一有源层11的第一区连接，第二连接电极42的第二端通过第九过孔V9与第一初始信号线31连接。在一种示例性实施例中，第二连接电极42可以作为第一晶体管T1的第一极，实现了第一初始信号线31将第一初始信号写入第一晶体管T1。
在一种示例性实施例中，第三连接电极43的形状可以为主体部分沿着第二方向Y延伸的条形状，第三连接电极43的第一端通过第七过孔V7与第七有源层17的第一区连接，第三连接电极43的第二端通过第十过孔V10与第二初始信号线32连接。在一种示例性实施例中，第三连接电极43可以作为第七晶体管T7的第一极，实现了第二初始信号线32将第二初始信号写入第七晶体管T7。
在一种示例性实施例中，第四连接电极44的形状可以为矩形状，第四连接电极44通过第四过孔V4与第六有源层16的第二区(也是第七有源层17的第二区)连接，使第六有源层16的第二区和第七有源层17的第二区具有相同的电位。例如，第四连接电极44可以作为第六晶体管T6的第二极(或者第七晶体管T7的第二极)，第四连接电极44被配置为与后续形成的阳极电极连接。
在一种示例性实施例中，数据信号线45的形状可以是主体部分沿着第二方向Y延伸的线形状。数据信号线45通过第五过孔V5与第四有源层14的第一区连接，因此，数据信号线45可以作为第四晶体管T4的第一极，实现数据信号线45将数据信号写入第四晶体管T4的第一极。例如，数据信号线45在基底上的正投影与挡块34在基底上的正投影存在交叠。
在一种示例性实施例中，第一电源线46的形状可以为主体部分沿着第二方向Y延伸的线形状。第一电源线46通过第三过孔V3与第五有源层15的第一区连接，第一电源线46通过第二过孔V2与第二极板33连接，如此，由于第一电源线46同时与第二极板33和第五有源层15的第一区连接，因而实现了第一电源线46将第一电源信号写入第五晶体管T5的第一极，并使第二极板33和第五有源层的第一区具有相同的电位。例如，第一电源线46可以作为第五晶体管T5的第一极。第一电源线46在基底上的正投影与挡块34在基底上的正投影存在交叠，第一电源线46通过第十一过孔V11与挡块34连接，如此，由于第一电源线46被配置为向像素驱动电路提供恒定电压，可以使得挡块34上的电压稳定，可起到屏蔽作用。
在一种示例性实施例中，第一电源线46可以为非等宽度设计，采用非等宽度设计的第一电源线46不仅可以便于像素结构的布局，而且可以降低第一 电源线产生的寄生电容。
在一种示例性实施例中，第三导电层可以采用金属材料形成。例如，金属材料可以包括但不限于：银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或者上述列出的金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等。第三导电层可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
(7)形成第四导电层图案。
在一种示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜和第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，如图19所示，形成设置在第五绝缘层上的第四导电层，如图20A和图20B所示，图20B为图20A中第四导电层的平面示意图。
在一种示例性实施例中，第五绝缘层可以包括多个过孔，多个过孔可以包括：第二一过孔V21和第二二过孔V22。例如，第二一过孔V21在基底上的正投影与第一电源线46在基底上的正投影存在交叠，被配置为暴露出第一电源线46的表面。例如，第二二过孔V22在基底上的正投影与第四连接电极44在基底上的正投影存在交叠，被配置为暴露出第四连接电极44的表面。
在一种示例性实施例中，第四导电层可以称为第二源漏金属(SD2)层。
在一种示例性实施例中，第二显示区AA2的第四导电层至少可以包括：屏蔽电极60和第五连接电极50。
在一种示例性实施例中，屏蔽电极60在基底上的正投影与第一栅信号线SL1在基底上的正投影存在重叠，屏蔽电极60的第一方向X的一侧设置有屏蔽块60-1，屏蔽块60-1在基底上的正投影与第一电源线46在基底上的正投影至少部分交叠，屏蔽块60-1通过第二一过孔V21与第一电源线46连接，屏蔽块60-1被配置为使屏蔽电极60通过第二一过孔V21与第一电源线46连接，第一电源线46被配置为向像素驱动电路提供恒定电压，如此，屏蔽电极60上的电压稳定，可起到屏蔽作用。由于在第一显示区AA1中通过导电线L引出阳极的发光信号，如此，通过设置屏蔽电极60可以避免导电线L对关键节点(如第一节点N1)的影响，提高显示效果。例如，第一栅信号线 SL1在基底上的正投影完全落入屏蔽电极60在基底上的正投影的边界范围内，如此，可以使得屏蔽电极60起到更好的屏蔽作用。例如，为了减轻显示不良(mura)和提高显示效果，第一栅信号线SL1在基底上的正投影与屏蔽电极60在基底上的正投影的边界之间的距离大于或等于1.75μm(微米)。因为像素单元所占用的区域的面积有限，可以对屏蔽电极60超出第一栅信号线SL1的距离进行限定。例如，一些实施例中，为了获得较好的屏蔽效果，第一栅信号线SL1在基底上的正投影与屏蔽电极SE在基底上的正投影的边界之间的距离大于或等于2.33μm。
在一种示例性实施例中，在显示面板包括第二栅信号线SL2的情况下，第二栅信号线SL2与第一栅信号线SL1相连，以形成第一节点N1，因此，屏蔽电极60在基底上的正投影与第二栅信号线SL2在基底上的正投影存在重叠。
在一种示例性实施例中，屏蔽电极60在基底上的正投影与第一极板24(也是第三晶体管T3的栅电极)在基底上的正投影、第一栅信号线SL1(也是第一晶体管T1的第二极、第二晶体管T2的第一极)在基底上的正投影、以及第二栅信号线SL2(也是第一有源层11的第二区、第二有源层12的第一区)在基底上的正投影至少部分交叠。
在一种示例性实施例中，屏蔽电极60在基底上的正投影与第二栅信号线SL2在基底上的正投影部分交叠，挡块34在基底上的正投影与第二栅信号线SL2在基底上的正投影部分交叠。从而，在图20A所示的显示面板中，屏蔽电极60和挡块34对第二栅信号线SL2形成了双层屏蔽。
在一种示例性实施例中，屏蔽电极60在基底上的正投影与挡块34在基底上的正投影部分交叠。
在一种示例性实施例中，屏蔽电极60在基底上的正投影与第一栅信号线SL1在基底上的正投影部分交叠，挡块34在基底上的正投影与第二栅信号线SL2在基底上的正投影部分交叠，从而，屏蔽电极60和屏蔽电极SE和挡块34共同起到对第一节点N1的屏蔽作用。
当然，在其它的实施例中，也可以不设置挡块34，或者挡块34在基底上的正投影与第二栅信号线SL2在基底上的正投影可以不交叠。
在一种示例性实施例中，屏蔽电极60的形状可以为规则形状，例如，屏蔽电极60的形状可以为矩形状。如此，通过设置屏蔽电极60为规则形状，可以使得屏蔽电极60不同位置的宽度均匀，从而，可以使得从屏蔽电极60上方经过的透明导线的线宽会一致，可以减少对透明导线的线宽的影响。进而，有利于改善亮度不均问题。
在一种示例性实施例中，第五连接电极50的形状可以为矩形状。第五连接电极在基底上的正投影与第四连接电极44在基底上的正投影至少部分交叠。第五连接电极50可以作为阳极连接电极。第五连接电极50通过第二二过孔V22与第四连接电极44连接，被配置为与后续形成的阳极电极连接。
在一种示例性实施例中，在垂直于显示面板的平面内，第二显示区AA2的电路结构层可以包括：基底以及在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层和第四导电层。半导体层可以包括：第一像素驱动电路QD1和第二像素驱动电路QD2中多个晶体管的有源层，第一导电层可以包括：多个晶体管的栅电极、存储电容的第一极板、扫描信号线、第一复位控制线、发光控制线和第二复位控制线，第二导电层可以包括：存储电容的第二极板、极板连接线、挡块、第一初始信号线和第二初始信号线，第三导电层可以包括：多个晶体管的第一极和第二极、数据信号线、以及第一电源线，第四导电层可以包括：阳极连接电极和屏蔽电极。即第二显示区AA2的电路结构层可以包括：第一像素驱动电路QD1和第二像素驱动电路QD2。
在一种示例性实施例中，在垂直于显示面板的平面内，第一显示区AA1的透光区域可以包括：基底以及在基底上依次叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层。第一显示区AA1的非透光区域可以包括：基底以及在基底上依次叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层。即第一显示区AA1的电路结构层没有设置像素驱动电路。
在一种示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌 合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
至此，在基底上制备完成电路结构层。
(8)形成第一透明导电层。
在一种示例性实施例中，在形成前述图案的基底上，沉积第六绝缘薄膜和第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成覆盖第四导电层的第六绝缘层，以及设置在第六绝缘层的第一透明导电层，如图21A和图21B所示。
在一种示例性实施例中，第一透明导电层可以包括：第六连接电极61。
在一种示例性实施例中，第六连接电极61的形状可以为矩形状。第六连接电极61在基底上的正投影与第五连接电极50在基底上的正投影至少部分交叠。当第一发光器件通过位于第一透明导电层的第一透明导电线L1与过渡显示区AAG的第一像素驱动电路QD1电连接时，第六连接电极61可以作为第一发光器件的转接电极。第六连接电极61通过第六绝缘层的过孔与第五连接电极50连接，被配置为与后续形成的阳极电极连接。
在一种示例性实施例中，第一透明导电层还可以包括：第一透明导电线L1。例如，第一透明导电线L1的一端可以与位于第一显示区AA1中的一个第六连接电极61连接，第一透明导电线L1的另一端可以与位于第二显示区AA2中过渡显示区AAG的第一像素驱动电路QD1中的一个第六连接电极61连接，如此，可以使得后续形成的阳极电极与过渡显示区AAG中的第一像素驱动电路QD1连接。
(9)形成第二透明导电层。
在一种示例性实施例中，在形成前述图案的基底上，涂覆第一平坦薄膜，通过图案化工艺形成第一平坦层。随后，沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行图案化，形成设置在第一平坦层上的第二透明导电层，如图22A和图22B所示。
在一种示例性实施例中，第二透明导电层可以包括：第七连接电极71。
在一种示例性实施例中，第七连接电极71的形状可以为矩形状。第七连接电极71在基底上的正投影与第六连接电极61在基底上的正投影至少部分交叠。当第一发光器件通过位于第二透明导电层的第二透明导电线L2与过渡显示区AAG的第一像素驱动电路QD1电连接时，第七连接电极71可以作为第一发光器件的转接电极。第七连接电极71通过第一平坦层的过孔与第六连接电极61连接，被配置为与后续形成的阳极电极连接。
在一种示例性实施例中，第二透明导电层还可以包括：第二透明导电线L2。例如，第二透明导电线L2的一端可以与位于第一显示区AA1中的一个第七连接电极71连接，第二透明导电线L2的另一端可以与位于第二显示区AA2中过渡显示区AAG的第一像素驱动电路QD1中的一个第七连接电极71连接，如此，可以使得后续形成的阳极电极与过渡显示区AAG中的第一像素驱动电路QD1连接。
(10)形成第三透明导电层。
在一种示例性实施例中，在形成前述图案的基底上，涂覆第二平坦薄膜，通过图案化工艺形成第二平坦层。随后，沉积第三透明导电薄膜，通过图案化工艺对第三透明导电薄膜进行图案化，形成设置在第二平坦层上的第三透明导电层，如图23A和图23B所示。
在一种示例性实施例中，第三透明导电层可以包括：第八连接电极81。
在一种示例性实施例中，第八连接电极81的形状可以为矩形状。第八连接电极81在基底上的正投影与第七连接电极71在基底上的正投影至少部分交叠。当第一发光器件通过位于第三透明导电层的第三透明导电线L3与位于第二显示区AA2中过渡显示区AAG的第一像素驱动电路QD1电连接时，第八连接电极81可以作为第一发光器件的转接电极。第八连接电极81通过第二平坦层的过孔与第七连接电极71连接，被配置为与后续形成的阳极电极连接。
在一种示例性实施例中，第三透明导电层还可以包括：第三透明导电线L3。例如，第三透明导电线L3的一端可以与位于第一显示区AA1的一个第八连接电极81连接，第二透明导电线L2的另一端可以与位于第二显示区 AA2中过渡显示区AAG的第一像素驱动电路QD1中的一个第八连接电极81连接，如此，可以使得后续形成的阳极电极与过渡显示区AAG中的第一像素驱动电路QD1连接。
在一种示例性实施例中，导电线L可以包括：第一透明导电线L1、第二透明导电线L2和第三透明导电线L3中的一种或多种。例如，导电线L1在基底上的正投影与第一像素驱动电路QD1在基底上的正投影部分交叠。例如，导电线L1在基底上的正投影与第一像素驱动电路QD1中的第一栅信号线SL1在基底上的正投影部分交叠。屏蔽电极60位于导电线L1和第一栅信号线SL1之间。在本公开的实施例中，形成像素驱动电路之后，形成屏蔽电极60，再形成导电线L1(如第一透明导电线L1、第二透明导电线L2和第三透明导电线L3)，然后形成发光器件，从而，屏蔽电极60所在膜层位于导电线L1所在膜层和第一栅信号线SL1所在膜层之间，屏蔽电极60所在膜层位于导电线L1所在膜层和第三晶体管T3的栅电极所在膜层之间。
(11)形成发光结构层。
在一种示例性实施例中，在形成前述图案的基底上，涂覆第三平坦薄膜，通过图案化工艺形成第三平坦层。随后，沉积阳极导电薄膜，通过图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极层，如图24A和图24B所示。随后，在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)。像素定义层形成有暴露出阳极层的多个像素开口，像素开口被配置为限定像素单元的出光区域，如图25所示。在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极图案，阴极分别与有机发光层和第二电源线电连接。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。其中，图24A、图24B和图25中是以第二显示区AA2中的8个发光器件并省略了第二像素驱动电路QD2部分结构为例进行示意说明。图24C中是以第二显示区AA2中的1个第二发光器件的第二阳极与第二像素驱动电路QD2连接为例进行示意说明。第一显示区AA1中的发光器件的结构可以基本上类似，本领域技术人员可参见相关描述而理解，本公开实施例在此不 做过多赘述。
在一种示例性实施例中，阳极层可以包括：第一阳极电极91、第二阳极电极92和第三阳极电极93。
在一种示例性实施例中，第一阳极电极91可以作为绿色发光器件的阳极。第一阳极电极91在基底上的正投影可以与第八连接电极81、第七连接电极71、第六连接电极61和第五连接电极50在基底上的正投影部分交叠。
在一种示例性实施例中，第二阳极电极92可以作为红色发光器件的阳极。第二阳极电极92在基底上的正投影可以与第八连接电极81、第七连接电极71、第六连接电极61和第五连接电极50在基底上的正投影部分交叠。
在一种示例性实施例中，第三阳极电极93可以作为蓝色发光器件的阳极。第三阳极电极93在基底上的正投影可以与第八连接电极81、第七连接电极71、第六连接电极61和第五连接电极50在基底上的正投影部分交叠。
在一种示例性实施例中，多个像素开口可以包括：第一像素开口94、第二像素开口95和第三像素开口96。
在一种示例性实施例中，第一像素开口94的形状可以为五边形。第一像素开口94的基底上的正投影落入第一阳极电极91在基底上的正投影的边界内。
在一种示例性实施例中，第二像素开口95的形状可以为六边形。第二像素开口95的基底上的正投影落入第二阳极电极92在基底上的正投影的边界内。
在一种示例性实施例中，第三像素开口96的形状可以为六边形。第三像素开口96的基底上的正投影落入第三阳极电极93在基底上的正投影的边界内。
在一种示例性实施例中，第一透明导电层至第三透明导电层可以采用透明导电材料，例如氧化铟锡(ITO)。第六绝缘层、第一平坦层至第三平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极可以采用透明导电材料。这里，本公开实 施例对此不做限定。
本公开实施例的显示面板的结构及其制备过程仅仅是一种示例性说明。在一种示例性实施例中，可以根据实际应用场景变更相应结构以及增加或减少构图工艺。本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与一些技术中的制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在一种示例性实施例中，显示面板可以包括四个或更多透明导电层。第一显示区的第一子区域内的第一类第一发光器件和第二类第一发光器件所电连接的透明导电线可以位于两个不同的透明导电层，且两个不同的透明导电层之间可以间隔至少一个透明导电层。
在本公开实施例提供的显示面板中，通过对第一显示区的第一类第一发光器件和第二类第一发光器件所电连接的透明导电线的布线方式进行调整，可以保证导电线均一性，从而改善第一显示区的显示均一性，提高第一显示区的显示效果。
本公开实施例还提供了一种显示装置。该显示装置可以包括：上述一个或多个示例性实施例中的显示面板。
在一种示例性实施例中，该显示装置还可以包括：传感器，传感器位于显示面板的非显示侧一侧，且传感器在显示面板的正投影与显示面板的第一显示区存在交叠。
这里，显示装置可以为具有图像(包括静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。
在一种示例性实施例中，显示装置可以包括但不限于为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、广告牌、具有显示功能的激光打印机、画屏、个人数字助理(PDA，Personal Digital Assistant)、数码相机、便携式摄录机、取景器、导航仪、车辆、大面积墙壁、信息查询设备(比如电子政务、银行、医院、电力等部门的业务查询设备)、或者监视器等任何具有显示功能的产品或部件。这里，本公开实施例对此不不做限定。
在一种示例性实施例中，传感器可以包括但不限于：摄像头传感器、指纹传感器、光线传感器、红外线传感器或者超声波传感器等。这里，本公开实施例对此不做限定。
以上显示装置实施例的描述，与上述显示面板实施例的描述是类似的，具有同显示面板实施例相似的有益效果。对于本公开显示装置实施例中未披露的技术细节，本领域的技术人员请参照本公开显示面板实施例中的描述而理解，这里不再赘述。
虽然本公开所揭露的实施方式如上，但上述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示面板，包括：基底、叠设于所述基底上的电路结构层和发光结构层、以及设置于所述电路结构层和所述发光结构层之间的多个导电层；其中，
    所述基底，包括：第一显示区和第二显示区，所述第二显示区位于所述第一显示区的至少一侧，所述第一显示区的透光率大于所述第二显示区的透光率；
    所述电路结构层，包括：位于所述第二显示区的第一栅信号线、恒压线、多个屏蔽电极和多个像素电路，所述像素电路包括驱动晶体管，所述驱动晶体管包括栅极，所述多个像素电路包括多个第一像素驱动电路；所述第一栅信号线与所述驱动晶体管的栅极相连；所述恒压线被配置为向所述多个像素电路提供第一恒定电压；所述屏蔽电极与所述恒压线相连，所述第一栅信号线在所述基底上的正投影落入所述屏蔽电极在所述基底上的正投影内；
    所述多个导电层，包括：多条导电线，所述多条导电线包括：多条第一类导电线和多条第二类导电线，所述第一类导电线沿第一方向延伸的部分在所述基底的正投影与所述多个屏蔽电极中的至少一个屏蔽电极在所述基底的正投影存在交叠，所述第二类导电线沿第一方向延伸的部分在所述基底的正投影与所述多个屏蔽电极在所述基底的正投影不存在交叠；
    所述发光结构层，包括：位于所述第一显示区的多个第一发光器件，所述多个第一发光器件包括：多个第一类第一发光器件和多个第二类第一发光器件，所述多个第一类第一发光器件中的至少一个第一类第一发光器件通过所述多条第一类导电线中的至少一条第一类导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接，所述多个第二类第一发光器件中的至少一个第二类第一发光器件通过所述多条第二类导电线中的至少一条第二类导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接，所述第一像素驱动电路被配置为驱动所述第一发光器件发光，所述第一类第一发光器件被配置为出射第一颜色光线，所述第二类第一发光器件被配置为出射第二颜色光线，所述第二颜色光线与所述第一颜色光线不同。
  2. 根据权利要求1所述的显示面板，其中，
    所述第一显示区的多个第一发光器件包括：多组第一发光器件，所述多组第一发光器件的每一组中的第一发光器件沿所述第一方向排布，所述多组第一发光器件沿第二方向排布，所述第二方向与所述第一方向交叉；
    在所述至少一组第一发光器件中，与所述多个第一类第一发光器件电连接的多个第一像素驱动电路，比与所述多个第二类第一发光器件电连接的多个第一像素驱动电路中的每一个都更靠近所述第一显示区。
  3. 根据权利要求2所述的显示面板，其中，
    所述多个导电层包括：沿着远离所述基底一侧依次设置的第一透明导电层、第二透明导电层和第三透明导电层；所述第一透明导电层包括多条第一透明导电线，所述第二透明导电层包括多条第二透明导电线，所述第三透明导电层包括多条第三透明导电线。
  4. 根据权利要求3所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第一类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第一类第一发光器件通过所述第三透明导电线与多个所述第一像素驱动电路电连接。
  5. 根据权利要求3所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第一类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第一类第一发光器件通过所述第二透明导电线与多个所述第一像素驱动电路电连接。
  6. 根据权利要求3所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第一类第一发光器件通过所述第二透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第一类第一发光器件通过所述第一透明导电线与所述第二显示区的多个所述第一像素驱动电路电连接。
  7. 根据权利要求3所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中 心的多个第一类第一发光器件通过所述第三透明导电线与多个第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第一类第一发光器件通过所述第一透明导电线与所述第二显示区的多个所述第一像素驱动电路电连接。
  8. 根据权利要求4至7中任一项所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第二类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第二类第一发光器件通过所述第三透明导电线与多个所述第一像素驱动电路电连接。
  9. 根据权利要求4至7中任一项所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第二类第一发光器件电连接的透明导电线与靠近所述第一显示区中心的多个第一类第一发光器件电连接的透明导电线的类型是相同的，或者，靠近所述第一显示区边缘的多个第二类第一发光器件电连接的透明导电线与靠近所述第一显示区边缘的多个第一类第一发光器件电连接的透明导电线的类型是相同的。
  10. 根据权利要求4至7中任一项所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第二类第一发光器件电连接的透明导电线与靠近所述第一显示区中心的多个第一类第一发光器件电连接的类型是不相同的，或者，靠近所述第一显示区边缘的多个第二类第一发光器件电连接的透明导电线与靠近所述第一显示区边缘的多个第一类第一发光器件电连接的透明导电线的类型是不相同的。
  11. 根据权利要求4至7中任一项所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第二类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第二类第一发光器件通过所述第三透明导电线与多个所述第一像素驱动电路电连接。
  12. 根据权利要求4至7中任一项所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，所述多个第一类第一发光器件电连接的导电线在第二方向上位于该组第一发光器件的转接电极的一侧。
  13. 根据权利要求12所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，所述多个第二类第一发光器件电连接的导电线在第二方向上位于该组第一发光器件的转接电极的另一侧。
  14. 根据权利要求3所述的显示面板，其中，
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第一类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第一类第一发光器件通过所述第三透明导电线与多个所述第一像素驱动电路电连接，位于所述靠近所述第一显示区中心的多个第一类第一发光器件与所述靠近所述第一显示区边缘的多个第一类第一发光器件之间的多个第一类第一发光器件通过所述第二透明导电线与多个所述第一像素驱动电路电连接；
    在所述第一显示区的至少一组第一发光器件中，靠近所述第一显示区中心的多个第二类第一发光器件通过所述第一透明导电线与多个所述第一像素驱动电路电连接，靠近所述第一显示区边缘的多个第二类第一发光器件通过所述第三透明导电线与多个所述第一像素驱动电路电连接，位于所述靠近所述第一显示区中心的多个第二类第一发光器件与所述靠近所述第一显示区边缘的多个第二类第一发光器件之间的多个第二类第一发光器件通过所述第二透明导电线与多个所述第一像素驱动电路电连接。
  15. 根据权利要求1至7中任一项所述的显示面板，其中，
    所述第一显示区包括：第一子区域和第二子区域，所述第二子区域位于所述第一子区域和所述第二显示区之间；
    所述多个第一发光器件中的位于所述第一子区域的至少一个第一发光器件，通过所述多个导电层的导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接；
    所述多个第一发光器件中的位于所述第二子区域的至少一个第一发光器件，通过所述电路结构层中的金属导电层的导电线与所述多个第一像素驱动电路中的至少一个第一像素驱动电路连接。
  16. 根据权利要求15所述的显示面板，其中，所述金属导电层与所述屏蔽电极位于同一膜层。
  17. 根据权利要求1至7中任一项所述的显示面板，其中，
    所述发光结构层还包括：位于所述第二显示区的多个第二发光器件；
    所述多个像素电路还包括：多个第二像素驱动电路，所述多个第二像素驱动电路中的至少一个第二像素驱动电路与所述多个第二发光器件中的至少一个第二发光器件电连接，所述至少一个第二像素驱动电路被配置为驱动所述至少一个第二发光器件发光。
  18. 根据权利要求17所述的显示面板，其中，
    所述第二显示区包括：过渡显示区和正常显示区，所述过渡显示区位于所述第一显示区和所述正常显示区之间；
    所述过渡显示区包括：所述多个第一像素驱动电路；
    所述正常显示区包括：所述多个第二发光器件中的至少部分和所述多个第二像素驱动电路中的至少部分，所述多个第二发光器件中的至少部分与所述多个第二像素驱动电路中的至少部分连接。
  19. 根据权利要求1至7中任一项所述的显示面板，其中，
    所述第一颜色光线为绿光，所述第二颜色光线包括：蓝光和红光中至少一种。
  20. 一种显示装置，包括：如权利要求1至19中任一项所述的显示面板。
  21. 根据权利要求20所述的显示装置，还包括：传感器，所述传感器位于所述显示面板的非显示侧一侧，且所述传感器在所述显示面板的正投影与所述显示面板的第一显示区存在交叠。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160321991A1 (en) * 2015-04-28 2016-11-03 Samsung Display Co., Ltd. Organic light-emitting diode display
CN107316873A (zh) * 2017-07-19 2017-11-03 武汉天马微电子有限公司 一种阵列基板及显示装置
CN108597374A (zh) * 2018-04-20 2018-09-28 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN113497109A (zh) * 2020-04-06 2021-10-12 三星显示有限公司 显示面板和包括该显示面板的显示设备
CN113763874A (zh) * 2021-09-16 2021-12-07 京东方科技集团股份有限公司 显示基板及显示装置
CN114255703A (zh) * 2020-09-21 2022-03-29 京东方科技集团股份有限公司 显示基板及显示装置
WO2022068152A1 (zh) * 2020-09-30 2022-04-07 京东方科技集团股份有限公司 显示面板和显示装置
CN114373774A (zh) * 2022-01-11 2022-04-19 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160321991A1 (en) * 2015-04-28 2016-11-03 Samsung Display Co., Ltd. Organic light-emitting diode display
CN107316873A (zh) * 2017-07-19 2017-11-03 武汉天马微电子有限公司 一种阵列基板及显示装置
CN108597374A (zh) * 2018-04-20 2018-09-28 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN113497109A (zh) * 2020-04-06 2021-10-12 三星显示有限公司 显示面板和包括该显示面板的显示设备
CN114255703A (zh) * 2020-09-21 2022-03-29 京东方科技集团股份有限公司 显示基板及显示装置
WO2022068152A1 (zh) * 2020-09-30 2022-04-07 京东方科技集团股份有限公司 显示面板和显示装置
CN113763874A (zh) * 2021-09-16 2021-12-07 京东方科技集团股份有限公司 显示基板及显示装置
CN114373774A (zh) * 2022-01-11 2022-04-19 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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