WO2023122888A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023122888A1
WO2023122888A1 PCT/CN2021/141666 CN2021141666W WO2023122888A1 WO 2023122888 A1 WO2023122888 A1 WO 2023122888A1 CN 2021141666 W CN2021141666 W CN 2021141666W WO 2023122888 A1 WO2023122888 A1 WO 2023122888A1
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WO
WIPO (PCT)
Prior art keywords
transparent conductive
conductive layer
base substrate
line
orthographic projection
Prior art date
Application number
PCT/CN2021/141666
Other languages
English (en)
French (fr)
Inventor
蔡建畅
唐庆
赵彧
卢彦伟
范建民
王彬艳
龙跃
黄炜赟
闫卓然
王一飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21969275.3A priority Critical patent/EP4336987A1/en
Priority to PCT/CN2021/141666 priority patent/WO2023122888A1/zh
Priority to CN202180004215.9A priority patent/CN116686418A/zh
Publication of WO2023122888A1 publication Critical patent/WO2023122888A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • This article relates to but is not limited to the field of display technology, especially a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, a first conductive layer on the base substrate, a first flat surface located on a side of the first conductive layer away from the base substrate. layer, the second conductive layer on the side of the first flat layer away from the base substrate, the second flat layer on the side of the second conductive layer away from the base substrate, and the second flat layer on the side of the
  • the second planar layer is at least one transparent conductive layer on a side away from the base substrate.
  • the second conductive layer is electrically connected to the first conductive layer through at least one first via hole penetrating through the first planar layer.
  • the transparent conductive layer includes: at least one first transparent conductive line and at least one auxiliary wiring.
  • An orthographic projection of the first transparent conductive line on the base substrate overlaps with an orthographic projection of the at least one first via hole on the base substrate.
  • At least part of the auxiliary wiring is in the same extension direction as the first transparent conductive line, and the orthographic projection of the auxiliary wiring on the base substrate is the same as that of the first via hole on the base substrate. Orthographic projections are adjacent.
  • the length of the auxiliary trace along the extending direction is greater than the diameter of the first via hole along the extending direction.
  • the distance between the auxiliary trace and the edge on the same side of the first via hole is less than 5 microns.
  • the absolute value of the difference between the line width of the auxiliary trace along the crossing direction of the extending direction and the line width of the first transparent conductive line along the crossing direction of the extending direction is less than Or equal to 0.3 microns.
  • An absolute value of a difference in line width of the lines in a crossing direction of the extending directions is less than or equal to 0.35 ⁇ m.
  • the length of the auxiliary routing along the extending direction is 13.5 microns to 16.5 microns; the line width of the auxiliary routing along the crossing direction of the extending direction is 1.9 microns to 2.4 microns;
  • a first distance between the auxiliary wiring and the first transparent conductive line is 2.1 microns to 2.6 microns.
  • the orthographic projection of the end of the auxiliary wiring in the extending direction on the base substrate is in the shape of an arc.
  • the at least one transparent conductive layer includes a first transparent conductive layer.
  • the first transparent conductive layer further includes: at least one third anode connection electrode, and the auxiliary wiring includes a first auxiliary wiring.
  • the first auxiliary wiring is integrated with the third anode connection electrode, and the third anode connection electrode is configured to be electrically connected to the second anode connection electrode of the second conductive layer.
  • the at least one transparent conductive layer further includes: a second transparent conductive layer located on a side of the first transparent conductive layer away from the base substrate.
  • the second transparent conductive layer includes a second auxiliary wiring and at least one fourth anode connection electrode.
  • the second auxiliary wiring is integrated with the fourth anode connection electrode.
  • the at least one transparent conductive layer further includes: a third transparent conductive layer located on a side of the second transparent conductive layer away from the base substrate.
  • the third transparent conductive layer includes a third auxiliary wiring and at least one fifth anode connection electrode.
  • the third auxiliary wiring is integrated with the fifth anode connection electrode.
  • the transparent conductive layer further includes: a plurality of second transparent conductive lines arranged adjacently.
  • the plurality of second transparent conductive lines include: two edge transparent conductive lines and at least one non-edge transparent conductive line; the at least one non-edge transparent conductive line is located in the middle of the two edge transparent conductive lines.
  • the line width of the edge transparent conductive line along the crossing direction of the extending direction is greater than the line width of the non-edge transparent conductive line along the crossing direction of the extending direction.
  • the absolute value of the difference between the line width of the edge transparent conductive line along the crossing direction of the extending direction and the line width of the non-edge transparent conductive line along the crossing direction of the extending direction is 0.3 microns to 0.5 microns.
  • the line width of the edge transparent conductive line along the crossing direction of the extending direction is 2.0 microns to 2.5 microns, and the line width of the non-edge transparent conductive line along the crossing direction of the extending direction 1.8 microns to 2.2 microns.
  • the transparent conductive layer further includes: at least one third transparent conductive line, the orthographic projection of the third transparent conductive line on the base substrate is the same as that of the second conductive layer on the The orthographic projection of the base substrate overlaps, and the distance between the third transparent conductive line and the remaining transparent conductive lines is greater than 4 microns.
  • a line width of the third transparent conductive lines along a crossing direction of the extending directions is greater than a line width of the edge transparent conductive lines along a crossing direction of the extending directions.
  • the transparent conductive layer further includes: at least one fourth transparent conductive line and at least one fifth transparent conductive line.
  • the line length of the fourth transparent conductive line along the extending direction is greater than the line length of the fifth transparent conductive line along the extending direction, and the line width of the fourth transparent conductive line along the crossing direction of the extending direction less than the line width of the fifth transparent conductive line in a crossing direction along the extending direction.
  • the orthographic projection of the fourth transparent conductive line on the base substrate overlaps with the orthographic projection of the first number of first via holes on the base substrate
  • the fifth The orthographic projection of the transparent conductive line on the base substrate overlaps with the orthographic projection of a second number of first via holes on the base substrate, wherein the first number is greater than the second number.
  • the orthographic projection of any one of the fourth transparent conductive line and the fifth transparent conductive line on the base substrate is the same as that of the first via hole on the base substrate.
  • the ratio of the length of the overlapping region of the orthographic projection in a direction intersecting with the extending direction of the transparent conductive line to the line width of the transparent conductive line is greater than or equal to 0.5.
  • the overlapping area of the orthographic projection of the fourth transparent conductive line on the base substrate and the orthographic projection of the second conductive layer on the base substrate is greater than that of the fifth transparent conductive line.
  • the overlapping area of the orthographic projection of the transparent conductive line on the base substrate and the orthographic projection of the second conductive layer on the base substrate is greater than that of the fifth transparent conductive line.
  • the material of the second conductive layer is a transparent conductive material.
  • the second conductive layer includes: a shielding electrode, the shielding electrode is electrically connected to the first power line, and the orthographic projection of the shielding electrode on the base substrate is configured to cover the An orthographic projection of the first node of the pixel circuit of the display substrate on the base substrate.
  • the orthographic projection of the shielding electrode on the base substrate has a regular shape.
  • the orthographic projection of the shielding electrode on the base substrate is a rectangle or a rectangle with rounded corners.
  • the shielding electrodes adjacent to the pixel circuits are integrally structured.
  • the display substrate includes a first display area and a second display area, and the first display area at least partially surrounds the second display area.
  • the display substrate further includes a plurality of sub-pixels, at least one sub-pixel includes the pixel circuit and a light emitting element, and the pixel circuit is configured to drive the light emitting element.
  • the multiple sub-pixels include at least one first sub-pixel and at least one second sub-pixel, the pixel circuit and light emitting element of the first sub-pixel are located in the first display area, and the pixel circuit of the second sub-pixel is located in In the first display area, the light-emitting element of the second sub-pixel is located in the second display area, and the pixel circuit of the second sub-pixel passes through the at least one transparent conductive layer and the light emitting element of the second sub-pixel
  • the components are electrically connected.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a method for preparing a display substrate, including: forming a first conductive layer on a base substrate; forming a first flat layer on a side of the first conductive layer away from the base substrate ; forming a second conductive layer on the side of the first planar layer away from the base substrate, the second conductive layer passes through at least one first via hole penetrating through the first planar layer and the first conductive layer electrical connection; forming a second planar layer on the side of the second conductive layer away from the base substrate; forming at least one transparent conductive layer on the side of the second planar layer away from the base substrate.
  • the transparent conductive layer includes: at least one first transparent conductive line and at least one auxiliary wiring; the orthographic projection of the first transparent conductive line on the base substrate and the at least one first via hole on the substrate
  • the orthographic projection of the base substrate overlaps.
  • At least part of the auxiliary wiring is in the same extension direction as the first transparent conductive line, and the orthographic projection of the auxiliary wiring on the base substrate is the same as that of the first via hole on the base substrate. Orthographic projections are adjacent.
  • FIG. 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 1B is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 2 is a schematic partial top view of a display substrate according to at least one embodiment of the present disclosure
  • Fig. 3 is a partial cross-sectional schematic diagram along the P-P ' direction in Fig. 2;
  • FIG. 4 is a schematic partial top view of the display substrate after the first transparent conductive layer is formed in FIG. 2;
  • FIG. 5 is a schematic partial top view of the display substrate after forming the second conductive layer in FIG. 2;
  • FIG. 6 is a schematic diagram of the principle of the exposure process during the preparation of the first transparent conductive layer in FIG. 2;
  • FIG. 7 is a partially enlarged schematic diagram of a first transparent conductive line and a first auxiliary wiring of a first transparent conductive layer of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 8 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • Fig. 9 is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 8.
  • FIG. 10 is a schematic partial top view of the display substrate after the third transparent conductive layer is formed in FIG. 8;
  • FIG. 11 is a schematic partial top view of the display substrate after forming the second transparent conductive layer in FIG. 8;
  • Fig. 12 is another schematic top view of the display substrate of at least one embodiment of the present disclosure after forming the second transparent conductive layer;
  • FIG. 13 is a schematic partial top view of a display substrate
  • FIG. 14 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a capacitor showing a transparent conductive layer of a substrate
  • 16 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • 17 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 18 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 19 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 20 is another schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • the gate may also be referred to as a control electrode.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • Light transmittance in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.
  • line length means the length along the extending direction of the line
  • line width means the length in the direction intersecting with the extending direction of the line (for example, the perpendicular direction to the extending direction) in the plane where the line is located .
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate, a first conductive layer located on the base substrate, a first flat layer, a second conductive layer, a second flat layer, and at least one transparent conductive layer.
  • the second conductive layer is electrically connected to the first conductive layer through at least one first via hole penetrating through the first planar layer.
  • the transparent conductive layer includes: at least one first transparent conductive line and at least one auxiliary wiring.
  • the orthographic projection of the first transparent conductive line on the base substrate overlaps with the orthographic projection of the at least one first via hole on the base substrate.
  • At least part of the auxiliary wiring is in the same extension direction as the first transparent conductive line, and the orthographic projection of the auxiliary wiring on the base substrate is adjacent to the orthographic projection of the first via hole on the base substrate.
  • the display substrate may include one transparent conductive layer, or may include a plurality of transparent conductive layers (eg, three transparent conductive layers).
  • each of the multiple transparent conductive layers may include a first transparent conductive line and an auxiliary wiring, or at least one of the multiple transparent conductive layers may include a first transparent conductive line and an auxiliary wiring. Wire.
  • this embodiment does not limit it.
  • the display substrate provided in this embodiment can improve the exposure environment of the exposure process of the transparent conductive layer by arranging auxiliary wiring around the first transparent conductive line, thereby improving the reflection focusing effect of the second conductive layer in the exposure process. This leads to disconnection or thinning of the line width in the transparent conductive layer.
  • the length of the auxiliary trace along the extending direction may be greater than the diameter of the first via hole along the extending direction.
  • the distance between the auxiliary trace and the same-side edge of the first via hole may be less than 5 micrometers (um).
  • the amount of light entering during the exposure process of the transparent conductive layer and the amount of etching during etching can be improved, thereby improving the situation of disconnection or narrowing of the line width of the transparent conductive layer.
  • the absolute value of the difference between the line width of the auxiliary trace along the crossing direction of the extending direction and the line width of the first transparent conductive line along the crossing direction of the extending direction may be less than or equal to 0.3 microns.
  • the absolute value of the difference between the first distance and the line width of the first transparent conductive line in the crossing direction of the extending direction may be less than Or equal to 0.35 microns.
  • the length of the auxiliary traces along the extension direction may be about 13.5 microns to 16.5 microns, for example, it may be about 15 microns; the line width of the auxiliary traces along the crossing direction of the extension direction may be about 1.9 microns to 2.4 microns, For example, it may be about 2.2 microns; along the crossing direction of the extension direction, the first distance between the auxiliary wiring and the first transparent conductive line may be about 2.1 microns to 2.6 microns, for example, it may be about 2.35 microns.
  • this embodiment does not limit it.
  • the orthographic projection of the ends of the auxiliary traces in the extension direction on the base substrate may be in the shape of an arc.
  • the ends of the auxiliary traces may be arc-shaped, the problem of mask discharge during the preparation of the transparent conductive layer can be improved, thereby improving the situation of disconnection or narrowing of the line width of the transparent conductive layer.
  • the at least one transparent conductive layer may include: a first transparent conductive layer.
  • the first transparent conductive layer may include: at least one third anode connection electrode.
  • the auxiliary routing may include: a first auxiliary routing.
  • the first auxiliary wiring and the third anode connection electrode may have an integral structure.
  • the third anode connection electrode is configured to be electrically connected to the second anode connection electrode of the second conductive layer.
  • this embodiment does not limit it.
  • the first auxiliary wiring of the first transparent conductive layer and the third anode connection electrode may be arranged independently of each other.
  • the first auxiliary wiring of the first transparent conductive layer may be electrically connected to the first power line or the second power line.
  • At least one transparent conductive layer may further include: a second transparent conductive layer located on a side of the first transparent conductive layer away from the base substrate.
  • the second transparent conductive layer may include a second auxiliary wiring and at least one fourth anode connection electrode, and the second auxiliary wiring and the fourth anode connection electrode may have an integral structure.
  • the fourth anode connection electrode may be configured to be electrically connected to the third anode connection electrode of the first transparent conductive layer.
  • this embodiment does not limit it.
  • the fourth anode connection electrode may be configured to be electrically connected to the second anode connection electrode of the second conductive layer.
  • the second auxiliary wiring of the second transparent conductive layer and the fourth anode connection electrode may be arranged independently of each other.
  • the second auxiliary wiring of the second transparent conductive layer may be electrically connected to the first power line or the second power line.
  • At least one transparent conductive layer may further include: a third transparent conductive layer located on a side of the second transparent conductive layer away from the base substrate.
  • the third transparent conductive layer may include a third auxiliary wiring and at least one fifth anode connection electrode, and the third auxiliary wiring and the fifth anode connection electrode may have an integrated structure.
  • the fifth anode connection electrode may be configured to be electrically connected to the fourth anode connection electrode of the second transparent conductive layer.
  • this embodiment does not limit it.
  • the fifth anode connection electrode may be configured to be electrically connected to the second anode connection electrode of the second conductive layer.
  • the third auxiliary wiring of the third transparent conductive layer and the fifth anode connection electrode may be arranged independently of each other.
  • the third auxiliary wiring of the third transparent conductive layer may be electrically connected to the first power line or the second power line.
  • the transparent conductive layer may further include: a plurality of adjacently arranged second transparent conductive lines.
  • the plurality of second transparent conductive lines may include: two edge transparent conductive lines and at least one non-edge transparent conductive line. At least one non-edge transparent conductive line is located in the middle of two edge transparent conductive lines.
  • the line width of the edge transparent conductive lines along the crossing direction of the extending direction is greater than the line width of the non-edge transparent conductive lines along the crossing direction of the extending direction.
  • At least one transparent conductive layer of the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer may include a plurality of second transparent conductive lines.
  • the line width of the edge transparent conductive lines by increasing the line width of the edge transparent conductive lines, the amount of light entering and the amount of etching during the exposure process of the transparent conductive layer can be improved, Therefore, the line width consistency of the transparent conductive layer is improved.
  • the absolute value of the difference between the line width of the edge transparent conductive lines in the crossing direction of the extending direction and the line width of the non-edge transparent conductive lines in the crossing direction of the extending direction may be 0.3 ⁇ m to 0.5 ⁇ m.
  • the line width of the edge transparent conductive lines in the crossing direction along the extension direction may be about 2.0 microns to 2.5 microns, such as about 2.3 microns
  • the line width of the non-edge transparent conductive lines in the crossing direction along the extending direction may be about 1.8 microns to 2.2 microns, such as about 2.0 microns.
  • this embodiment does not limit it.
  • the transparent conductive layer may further include: at least one third transparent conductive line.
  • the orthographic projection of the third transparent conductive line on the base substrate overlaps with the orthographic projection of the second conductive layer on the base substrate, and the distance between the third transparent conductive line and the remaining transparent conductive lines is greater than 4 microns.
  • the line width of the third transparent conductive lines along the crossing direction of the extending direction is greater than the line width of the edge transparent conductive lines along the crossing direction of the extending direction.
  • at least one transparent conductive layer of the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer may include a plurality of second transparent conductive lines.
  • the third transparent conductive wire is provided independently, and there may be no other adjacent transparent conductive wires around, that is, the third transparent conductive wire may be an independent single wire.
  • the third transparent conductive lines arranged separately by increasing the line width of the third transparent conductive lines, the amount of light entering in the exposure process of the transparent conductive layer and the etching amount during etching can be improved, thereby improving the line width of the transparent conductive layer. wide consistency.
  • the transparent conductive line in the plane where the transparent conductive line is located, if there is no other transparent conductive line within 4 microns around any transparent conductive line, it is considered that the transparent conductive line has no adjacent transparent conductive line, that is, the transparent conductive line
  • the wires are individually provided conductive wires. If the distance between any transparent conductive line and other transparent conductive lines is less than or equal to 4 micrometers, it is considered that the transparent conductive line has adjacent transparent conductive lines.
  • the transparent conductive layer may further include: at least one fourth transparent conductive line and at least one fifth transparent conductive line.
  • the line length of the fourth transparent conductive line along the extending direction is greater than the line length of the fifth transparent conductive line along the extending direction, and the line width of the fourth transparent conductive line in the crossing direction along the extending direction is smaller than the crossing direction of the fifth transparent conductive line along the extending direction line width.
  • at least one transparent conductive layer of the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer may include fourth transparent conductive lines and fifth transparent conductive lines. In this example, by adjusting the length and width of different transparent conductive lines, the difference in capacitance between different transparent conductive lines can be reduced, thereby improving the display effect.
  • the orthographic projection of the fourth transparent conductive line on the base substrate overlaps with the orthographic projection of the first number of first via holes on the base substrate, and the fifth transparent conductive line on the base substrate
  • the orthographic projection overlaps with the orthographic projection of the second number of first via holes on the base substrate, wherein the first number is greater than the second number.
  • the number of first via holes overlapping with the fourth transparent conductive line is greater than the number of first via holes overlapping with the fifth transparent conductive line.
  • the reflective focusing function of the layer can make the line width of the fourth conductive line smaller than the line width of the fifth conductive line.
  • the line width of the transparent conductive line can be improved, so as to reduce the capacitance difference between different transparent conductive lines.
  • the overlapping area of the orthographic projection of the fourth transparent conductive line on the base substrate and the orthographic projection of the second conductive layer on the base substrate is larger than the orthographic projection of the fifth transparent conductive line on the base substrate
  • the overlapping area with the orthographic projection of the second conductive layer on the base substrate may be smaller than the line width of the fifth conductive line.
  • the line width of the transparent conductive line can be improved, so as to reduce the capacitance difference between different transparent conductive lines.
  • the material of the second conductive layer may be a transparent conductive material, such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the second conductive layer includes: a blocking electrode.
  • the shielding electrode is electrically connected to the first power line, and the orthographic projection of the shielding electrode on the base substrate is configured to cover the orthographic projection of the first node of the pixel circuit of the display substrate on the base substrate.
  • the orthographic projection of the shielding electrode on the base substrate is a regular shape.
  • the orthographic projection of the shielding electrode on the substrate may be a rectangle or a rectangle with rounded corners.
  • this embodiment does not limit it.
  • the influence on the line width of the transparent conductive layer can be reduced, and the difference in capacitance between different transparent conductive lines can be reduced, thereby improving the display effect.
  • FIG. 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 1B is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes: a display area AA and a peripheral area BB.
  • the peripheral area BB is a non-display area.
  • the display area AA may include: a first display area A1 and a second display area A2.
  • hardware such as a photosensitive sensor (eg, a camera) is disposed on one side of the display substrate, and the orthographic projection of the photosensitive sensor on the display substrate overlaps the second display area A2.
  • the second display area A2 may be a light-transmitting display area, and may also be called an under-display camera (UDC, Under Display Camera) area; the first display area A1 may be a normal display area.
  • the first display area A1 is opaque and only used for display.
  • the display substrate of this embodiment can lay a solid foundation for the realization of a true full screen.
  • the display area AA may be a rectangle, such as a rectangle with rounded corners.
  • the second display area A2 may be a rectangle, such as a rectangle with rounded corners.
  • this embodiment does not limit it.
  • the second display area A2 may be in the shape of a circle, other quadrilaterals, or pentagons.
  • the display substrate may include: a base substrate and a plurality of sub-pixels located on the base substrate.
  • the plurality of sub-pixels includes: a plurality of first sub-pixels and a plurality of second sub-pixels.
  • At least one first sub-pixel includes a first pixel circuit 11 and a first light-emitting element 13
  • at least one second sub-pixel includes a second pixel circuit 12 and a second light-emitting element 14 .
  • Both the first pixel circuit 11 and the first light emitting element 13 are located in the first display area A1
  • the second pixel circuit 12 is located in the first display area A1
  • the second light emitting element 14 is located in the second display area A2.
  • a plurality of second pixel circuits 12 may be distributed among the plurality of first pixel circuits 11 at intervals.
  • the first pixel circuit 11 may be referred to as an in-situ pixel circuit
  • the second pixel circuit 12 may be referred to as an ex-situ pixel circuit.
  • the light-transmitting sub-area is between adjacent second light-emitting elements 14, and the area where the second light-emitting elements 14 are located is the display sub-area.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • the second display area A2 In order to improve the light transmittance of the second display area A2, only light emitting elements may be provided in the second display area A2, and pixel circuits for driving the light emitting elements of the second display area A2 may be provided in the first display area A1. That is, the light transmittance of the second display area A2 is improved by separately setting the light emitting element and the pixel circuit.
  • the second display area A2 is not provided with pixel circuits.
  • At least one first pixel circuit 11 of the plurality of first pixel circuits 11 may be electrically connected to at least one first light emitting element 13 of the plurality of first light emitting elements 13 , and the orthographic projection of the at least one first pixel circuit 11 on the substrate is at least partially overlapped with the orthographic projection of the at least one first light-emitting element 13 on the substrate.
  • At least one first pixel circuit 11 can be configured to provide a driving signal to the electrically connected first light emitting element 13 to drive the first light emitting element 13 to emit light.
  • the display substrate can adopt a pixel circuit compression scheme.
  • the pixel circuit is reduced.
  • the size in the first direction X so that the first pixel circuit 11 and the second pixel circuit 12 can be placed in the first direction X, and the second pixel circuits 12 can be distributed in the first pixel circuit 11 .
  • the first direction X is a row direction, and in the same row of pixel circuits, the second pixel circuits 12 are arranged at intervals in the first pixel circuits 11 .
  • this embodiment does not limit it.
  • the second pixel circuit 12 may be located in the peripheral area, so as to form an external pixel circuit solution.
  • the first display area A1 may be located on at least one side of the second display area A2.
  • the first display area A1 may surround the second display area A2. That is, the second display area A2 may be surrounded by the first display area A1.
  • the second display area A2 may be set at other positions, for example, it may be located at the middle of the top of the base substrate, or at the upper left corner or the upper right corner of the base substrate.
  • this embodiment does not limit it.
  • At least one second pixel circuit 12 among the plurality of second pixel circuits 12 can be connected with at least one second light-emitting element among the plurality of second light-emitting elements 14 14 are electrically connected through transparent conductive lines L.
  • One end of the transparent conductive line L is electrically connected to the second pixel circuit 12 , and the other end is electrically connected to the second light emitting element 14 .
  • the transparent conductive line L extends from the first display area A1 to the second display area A2.
  • the transparent conductive line L may extend from the first display area A1 to the second display area A2 along the first direction X; or, the transparent conductive line L may first extend in the first display area A1 along the second direction Y, and then extend along the second A direction X extends to the second display area A2.
  • this embodiment does not limit it.
  • the transparent conductive line L may be made of a transparent conductive material, for example, a conductive oxide material such as indium tin oxide (ITO). However, this embodiment does not limit it.
  • the transparent conductive lines L may be arranged in one transparent conductive layer, or a plurality of transparent conductive lines L may be arranged in two or three transparent conductive layers. Each transparent conductive line L can connect a second pixel circuit 12 and a second light emitting element 14 .
  • At least one second pixel circuit 12 is configured to provide a driving signal to at least one second light emitting element 14 electrically connected to drive the second light emitting element 14 to emit light.
  • the second pixel circuit 12 and the second light-emitting element 14 are located in different regions, and the orthographic projection of the second pixel circuit 12 on the substrate does not overlap with the orthographic projection of at least one second light-emitting element 14 on the substrate.
  • the second light emitting element 14 and the second pixel circuit 12 electrically connected thereto may be located in the same row. That is, the driving signal of the second light emitting element 14 comes from the second pixel circuits 12 in the same row.
  • the pixel circuits of the sub-pixels in the same row are electrically connected to the same gate line.
  • this embodiment does not limit it.
  • the second light emitting element and the second pixel circuit electrically connected thereto may not be located in the same row.
  • FIG. 2 is a schematic partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 2 may be a partially enlarged schematic diagram of area S in FIG. 1B .
  • Fig. 3 is a schematic partial cross-sectional view along the P-P' direction in Fig. 2 .
  • FIG. 4 is a schematic partial top view of the display substrate after forming the first transparent conductive layer in FIG. 2 .
  • FIG. 5 is a schematic partial top view of the display substrate after forming the second conductive layer in FIG. 2 .
  • multiple film layer structures on the side of the first conductive layer close to the display substrate are omitted.
  • the display substrate in the first display area A1 may include: a base substrate 10 , which are sequentially arranged on the base substrate 10
  • the first conductive layer 21 may also be called a first source-drain metal layer
  • the second conductive layer 22 may also be called a second source-drain metal layer.
  • the first flat layer 31 , the second flat layer 32 and the third flat layer 33 may be organic material layers. However, this embodiment does not limit it.
  • the first conductive layer 21 may at least include: a plurality of data lines (for example, data lines DL), a plurality of first power supply lines (for example, first power supply lines line PL1) and a plurality of connection electrodes (for example, the first anode connection electrode 211).
  • the data line DL and the first power line PL1 may extend in the second direction Y, and the data line DL and the first power line PL1 are adjacent in the first direction X.
  • the second conductive layer 22 may at least include: a plurality of connecting electrodes (for example, a shielding electrode 222 and a second anode connecting electrode 221 ).
  • the second anode connection electrode 221 may be electrically connected to the first anode connection electrode 211 through the first via hole K11 opened on the first planar layer 31 .
  • the shielding electrode 222 can be electrically connected to the first power line PL1 through the first via hole K12 opened on the first planar layer 31 .
  • the first transparent conductive layer 23 at least includes a plurality of transparent conductive lines (for example, the first transparent conductive lines 231), at least one auxiliary wiring (for example, the first auxiliary wiring 232), and a plurality of connecting electrodes (for example, the third The anode is connected to the electrode 233).
  • the third anode connection electrode 233 may be electrically connected to the second anode connection electrode 221 through the second via hole K2 opened on the second planar layer 32 .
  • the third anode connection electrode 233 and the first auxiliary wiring 232 may be integrally structured.
  • Anode layer 26 may include a plurality of anodes (eg, anode 261 ).
  • the anode 261 may be electrically connected to the third anode connection electrode 233 through the third via hole K3 opened in the third planar layer 33 .
  • FIG. 6 is a schematic diagram of the principle of the exposure process during the preparation of the first transparent conductive layer in FIG. 2 .
  • the preparation process of the first transparent conductive layer includes: forming a first transparent conductive film 41 on the second planar layer 32, forming a photoresist film 42 on the first transparent conductive film 41, and using a mask Expose the photoresist film 42 as a mask, so that the photoresist film forms a photoresist reserved part and a photoresist to-be-removed part.
  • a development process is performed. In the development process, the photoresist to-be-removed part is formed. The part is removed to form a photoresist pattern.
  • the first transparent conductive film 41 is etched using the photoresist pattern as a mask to form the first transparent conductive layer.
  • the second conductive layer 22 of metal material will reflect light and condense light to the photoresist remaining portion above the bowl-shaped portion of the second conductive layer 22 , so that this Part of the photoresist is exposed or partly exposed and washed away after development, so that the transparent conductive lines formed after etching the first transparent conductive film with the photoresist pattern as a mask are prone to disconnection or thinning.
  • the photoresist film at the via hole position will become thinner, resulting in disconnection of the finally formed transparent conductive line or thinner.
  • the photoresist film above the second conductive layer 22 will also be thinned, and then As a result, the transparent conductive lines formed in the first transparent conductive layer become thinner.
  • the amount of light entering in the exposure process and the amount of etching during etching are improved, thereby affecting the line width of the transparent conductive line. Improve the situation that the transparent conductive line is broken or thinned due to the reflective focusing effect of the second conductive layer in the exposure process.
  • the first auxiliary wiring 232 and the first transparent conductive line 231 of the first transparent conductive layer both extend along the second direction Y.
  • the first auxiliary wiring 232 is located on one side of the first transparent conductive line 231 in the first direction X, and the other side of the first transparent conductive line 231 is adjacent to the other transparent conductive lines.
  • the orthographic projection of the first transparent conductive line 231 on the base substrate 10 overlaps with the orthographic projection of the first via hole K11 on the base substrate 10 .
  • the orthographic projection of the first auxiliary wiring 232 on the base substrate 10 is adjacent to the orthographic projection of the first via hole K11 on the base substrate 10 in the first direction X.
  • this embodiment does not limit it.
  • the orthographic projection of the first auxiliary wiring 232 on the substrate may be L-shaped, a part of which may extend along the second direction Y, and another part may extend along the first direction X.
  • FIG. 7 is a partially enlarged schematic diagram of a first transparent conductive line and a first auxiliary wiring of a first transparent conductive layer of a display substrate according to at least one embodiment of the present disclosure.
  • the first auxiliary wiring 232 of the first transparent conductive layer is located on one side of the first transparent conductive line 231 along the first direction X.
  • the first auxiliary wiring 232 and the third anode connection electrode 233 may be integrally structured.
  • this embodiment does not limit it.
  • the first auxiliary wiring 232 and the third anode connection electrode 233 may be independent from each other, and the first auxiliary wiring 232 may be electrically connected to other wirings (eg, the first power line or the second power line).
  • the third anode connection electrode 233 may be in the shape of a rectangle, such as a rectangle with rounded corners.
  • the first auxiliary wiring 232 is, for example, a strip structure extending along the second direction Y. In the second direction Y, one end of the first auxiliary wiring 232 is connected to the third anode connection electrode 233 , and the orthographic projection of the other end of the first auxiliary wiring 232 on the base substrate may have a circular arc structure.
  • the end of the first auxiliary wiring 232 in the shape of an arc in the orthographic projection of the base substrate, the problem of mask discharge in the manufacturing process can be improved, thereby improving the situation where the line width becomes thinner or even broken. .
  • the length H1 of the first auxiliary trace 232 along the extension direction may be greater than that of the first via hole K12 along the second direction Y. aperture.
  • the distance H2 between the first auxiliary trace 232 and the same-side edge of the first via hole K12 may be less than 5 microns, and the first auxiliary trace 232 and the other same-side edge of the first via hole K12 The interval H3 between them may be less than 5 microns.
  • the absolute value of the difference of H6 may be less than or equal to 0.3 microns.
  • the absolute value can be less than or equal to 0.35 microns.
  • this embodiment does not limit it.
  • FIG. 8 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 8 may be another partially enlarged schematic diagram of area S in FIG. 2 .
  • Fig. 9 is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 8 .
  • FIG. 10 is a schematic partial top view of the display substrate after the third transparent conductive layer is formed in FIG. 8 .
  • FIG. 11 is a schematic partial top view of the display substrate after the second transparent conductive layer is formed in FIG. 8 .
  • 12 is another schematic top view of the display substrate after forming the second transparent conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 8 to FIG. 12 omit and illustrate multiple film layer structures on the side of the first conductive layer close to the base substrate.
  • the display substrate in the first display area A1 may include: a base substrate 10 , which are sequentially arranged on the base substrate 10
  • the first planarization layer 31 , the second planarization layer 32 , the third planarization layer 33 , the fourth planarization layer 34 and the fifth planarization layer 35 may be organic material layers. However, this embodiment does not limit it.
  • the first conductive layer 21 may at least include: a data line DL, a first power line PL1 and a plurality of connection electrodes (for example, a first anode connection electrode 211 ).
  • the second conductive layer 22 may at least include: a shielding electrode 222 and a second anode connection electrode 221 .
  • the second anode connection electrode 221 is electrically connected to the first anode connection electrode 211 through the first via hole opened in the first flat layer 31, and the shielding electrode 222 is electrically connected to the first power line PL1 through the first via hole opened in the first flat layer 31. connect.
  • the first transparent conductive layer 23 at least includes a plurality of transparent conductive lines (for example, a plurality of transparent conductive lines 230 extending along the first direction X shown in FIG. 12 ), a first auxiliary wiring and a third anode connection electrode 233 .
  • the third anode connection electrode 233 is electrically connected to the second anode connection electrode 221 through the second via hole opened in the second planar layer 32 .
  • the second transparent conductive layer 24 at least includes: a plurality of transparent conductive lines (eg, first transparent conductive lines 241 ), second auxiliary wiring lines 242 and fourth anode connection electrodes 243 .
  • the fourth anode connection electrode 243 is electrically connected to the third anode connection electrode 233 through the third via hole opened in the third planar layer 33 .
  • the third transparent conductive layer 25 at least includes: a plurality of transparent conductive lines (for example, a plurality of transparent conductive lines 250 extending along the second direction Y) and a fifth anode connection electrode 251 .
  • the fifth anode connection electrode 251 is electrically connected to the fourth anode connection electrode 243 through the fourth via hole opened in the fourth planar layer 34 .
  • Anode layer 26 may include a plurality of anodes (eg, anode 261 ).
  • the anode 261 can be electrically connected to the fifth anode connection electrode 251 through the fifth via hole opened in the fifth planar layer 35 .
  • the second anode connection electrode of the second conductive layer 22 may be an anode connection electrode arranged in sequence through three transparent conductive layers (that is, the third anode connection electrode comprising the first transparent conductive layer, the third anode connection electrode of the second transparent conductive layer The fourth anode is connected to the electrode and the fifth anode of the third transparent conductive layer is connected to the electrode) to realize the electrical connection with the anode.
  • this embodiment does not limit it.
  • the second anode connection electrode of the second conductive layer 22 can pass through the third anode connection electrode of the first transparent conductive layer, the fourth anode connection electrode of the second transparent conductive layer or the fifth anode connection electrode of the third transparent conductive layer , to achieve electrical connection with the anode.
  • the orthographic projection of the first transparent conductive line 241 of the second transparent conductive layer on the base substrate 10 and the orthographic projection of the first via hole on the base substrate 10 There is an overlap.
  • One side of the first transparent conductive line 241 is provided with a second auxiliary wiring 242 , and the second auxiliary wiring 242 and the first transparent conductive line 241 extend in the same direction, for example, both extend along the second direction Y.
  • the orthographic projection of the second auxiliary trace 242 on the base substrate 10 is adjacent to the orthographic projection of the first via hole on the base substrate 10 in the first direction X.
  • the orthographic projection of the end of the second auxiliary wiring 242 in the second direction Y on the base substrate 10 is in the shape of an arc.
  • the structure of the first transparent conductive line and the second auxiliary wiring of the second transparent conductive layer can be illustrated with reference to the structure of the first transparent conductive line and the first auxiliary wiring of the first transparent conductive layer in the above embodiment, so here No longer.
  • the first auxiliary wiring can also be arranged around the first transparent conductive line that overlaps with the first via hole;
  • a third auxiliary wiring is arranged around the first transparent conductive line that overlaps in the hole.
  • the third transparent conductive layer can also be provided with a third auxiliary wiring, and the third auxiliary wiring can be integrated with the fifth anode connection electrode.
  • the first transparent conductive layer can also be provided with a first auxiliary wiring, and the first auxiliary wiring can be integrated with the third anode connection electrode.
  • this embodiment does not limit it.
  • the second auxiliary wiring of the second transparent conductive layer and the fourth anode connection electrode may be independent of each other, the first auxiliary wiring of the first transparent conductive layer may be independent of the third anode connection electrode, and the third transparent conductive layer may be independent of each other.
  • the third auxiliary wiring of the conductive layer and the fifth anode connection electrode may be independent of each other.
  • FIG. 13 is a schematic partial top view of a display substrate.
  • a transparent conductive layer (for example, the first transparent conductive layer, the second transparent conductive layer or the third transparent conductive layer) may include: a single transparent conductive line 300a and a plurality of adjacent transparent conductive lines 300b .
  • a plurality of transparent conductive lines 300b are arranged adjacently in sequence, and the orthographic projections on the base substrate overlap with the orthographic projections of the second conductive layer on the base substrate.
  • the line width of the transparent conductive line 300b becomes thinner, as shown in the areas 3 and 4 marked in Figure 13, the line width of the transparent conductive line 300b in the areas 3 and 4 is smaller than that of the transparent conductive line 300b not connected to the second area.
  • the line width of the conductive layer overlap.
  • the line width of a single transparent conductive line 300a is thinner, as shown in areas 1 and 2 marked in FIG. 13 , the line width of the transparent conductive line 300a in area 2 is greater than that in area 1. Due to the reflective focusing effect of the second conductive layer during the exposure process, the photoresist film above the second conductive layer will become thinner, which in turn will result in thinner transparent conductive lines formed.
  • FIG. 14 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • the second conductive layer and the first transparent conductive layer are taken as examples for illustration.
  • the first transparent conductive layer may include: a plurality of second transparent conductive lines (eg, edge transparent conductive lines 234 and 236 , non-edge transparent conductive lines 235 ).
  • a plurality of second transparent conductive lines are arranged adjacent to each other, and the orthographic projection on the base substrate overlaps with the orthographic projection of the shielding electrode 222 of the second conductive layer on the base substrate.
  • edge transparent conductive line 2334 There is no adjacent transparent conductive line on the left side of the edge transparent conductive line 234, and there is no adjacent transparent conductive line on the right side of at least part of the edge transparent conductive line 236.
  • Two non-edge transparent conductive lines 235 are located between the edge transparent conductive line 234 and the 236 in the middle.
  • the line widths of the edge transparent conductive lines 234 and 236 along the crossing directions of the extending directions may be approximately the same, and may be greater than the line width of the non-edge transparent conductive lines 235 along the crossing directions of the extending directions.
  • the absolute value of the difference between the line width of the edge transparent conductive line (eg, the edge transparent conductive line 234 or 236 ) and the line width of the non-edge transparent conductive line 235 may be 0.3 ⁇ m to 0.5 ⁇ m.
  • the line width H7 of the edge transparent conductive line 234 in the crossing direction along the extension direction may be about 2.0 microns to 2.5 microns, such as about 2.3 microns
  • the line width H8 of the edge transparent conductive line 236 in the crossing direction along the extending direction may be about 2.0 microns to 2.5 microns.
  • the line width H9 of the non-edge transparent conductive lines 235 along the crossing direction of the extending direction may be about 1.8 microns to 2.2 microns, such as about 2.0 microns. There are no other transparent conductive lines in the range greater than or equal to 5 microns on the right side of the edge transparent conductive line 236 . After the edge transparent conductive lines 236 extend along the first direction X, there will be adjacent transparent conductive lines in the second direction Y, and the line width of the edge transparent conductive lines 236 with adjacent transparent conductive lines can be compared with that of non-edge transparent conductive lines. Lines 235 have approximately the same line width.
  • the edge transparent conductive lines 236 may include a first part and a second part, the first part has no adjacent transparent conductive lines within the range of 5 microns, the second part has adjacent transparent conductive lines within the range of 5 microns, and the lines of the first part
  • the width can be larger than the line width of the second part.
  • the second transparent conductive layer and the third transparent conductive layer may also include a plurality of second transparent conductive lines, and the line width of the edge transparent conductive lines in the plurality of second transparent conductive lines may be greater than that of the non-edge transparent conductive lines.
  • the line width of the conductive line may be greater than that of the non-edge transparent conductive lines.
  • the first transparent conductive layer may further include: a single third transparent conductive line (for example, the transparent conductive line 300a in FIG. 13 ).
  • the orthographic projection of the third transparent conductive line 300 a on the base substrate overlaps with the orthographic projection of the second conductive layer on the base substrate.
  • no other transparent conductive lines are arranged within 4 microns around the third transparent conductive line 300a.
  • the line width of the third transparent conductive lines 300a along the crossing direction of the extending direction may be larger than that of the edge transparent conductive lines (eg, the edge transparent conductive lines 234 and 236 in FIG. 14 ) along the crossing direction of the extending directions.
  • the line width of the third transparent conductive line 300a may be about 2.3 microns to 2.8 microns, such as about 2.6 microns.
  • the exposure environment of the first transparent conductive layer can be improved, thereby improving the thinning of the line width of the transparent conductive line.
  • this embodiment does not limit it.
  • the second transparent conductive layer and the third transparent conductive layer may also include third transparent conductive lines, and the line width of the third transparent conductive lines may be greater than that of the edge transparent conductive lines among the plurality of second transparent conductive lines line width.
  • FIG. 15 is a schematic diagram showing the capacitance of the transparent conductive layer of the substrate.
  • the abscissa represents the position of the second display area A2 of the display substrate in the first direction
  • the ordinate represents the ratio of the capacitance of the transparent conductive line connected to the light emitting element at the position to the total capacitance.
  • the second light-emitting element in the second display area A2 is electrically connected to the second pixel circuit in the first display area A1 through a transparent conductive line, and the capacitance of the transparent conductive line affects the display effect of the second light-emitting element.
  • the large capacitance of the transparent conductive wire leads to a decrease in the luminous duration and dim brightness; at low gray scales, the large capacitance causes the second light-emitting element to fail to light up and the brightness is low. It can be seen that the capacitance of the transparent conductive line has a great influence on the display failure of the display substrate, and the greater the difference in capacitance, the more obvious the display failure phenomenon.
  • the capacitance difference between different transparent conductive lines is reduced by setting the line length and line width of the transparent conductive lines, so as to improve the display effect.
  • the transparent conductive layer of the display substrate of this embodiment may include: at least one fourth transparent conductive line and at least one fifth transparent conductive line.
  • at least one of the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer may include fourth transparent conductive lines and fifth transparent conductive lines.
  • the line length of the fourth transparent conductive line along the extending direction is greater than the line length of the fifth transparent conductive line along the extending direction, and the line width of the fourth transparent conductive line in the crossing direction along the extending direction is smaller than the crossing direction of the fifth transparent conductive line along the extending direction line width.
  • the line width of the long transparent conductive line is set smaller, and the line width of the small transparent conductive line is set larger, so as to minimize the difference in capacitance between different transparent conductive lines.
  • the orthographic projection of the fourth transparent conductive line on the base substrate overlaps with the orthographic projection of the first number of first via holes on the base substrate, and the fifth transparent conductive line on the base substrate The orthographic projection overlaps with the orthographic projection of the second number of first via holes on the base substrate, wherein the first number is greater than the second number.
  • the influence of the reflective focusing effect of the second conductive layer in the exposure process on the line width of the fourth transparent conductive line is increased to reduce the The line width of the small fourth transparent conductive line.
  • the overlapping area of the orthographic projection of the fourth transparent conductive line on the base substrate and the orthographic projection of the second conductive layer on the base substrate is larger than the orthographic projection of the fifth transparent conductive line on the base substrate
  • the overlapping area with the orthographic projection of the second conductive layer on the base substrate is larger than the overlapping area of the fifth transparent conductive line and the second conductive layer.
  • FIG. 16 is another partial top view of a display substrate according to at least one embodiment of the present disclosure.
  • the second conductive layer and the first transparent conductive layer are taken as examples for illustration.
  • the second conductive layer is electrically connected to the first conductive layer through the first via hole opened in the first planar layer.
  • the shielding electrode 222 of the second conductive layer may be electrically connected to the first conductive layer through the first via hole K11 opened in the first planar layer.
  • the first transparent conductive layer includes at least a plurality of transparent conductive lines (for example, fourth transparent conductive lines 230a and fifth transparent conductive lines 230b).
  • the fourth transparent conductive line 230a overlaps the orthographic projection of the first number of first via holes on the base substrate
  • the fifth transparent conductive line 230b overlaps the orthographic projection of the second number of first via holes on the base substrate. stack.
  • the first number is greater than the second number. That is, the number of first via holes overlapped by the fourth transparent conductive line 230 a is greater than the number of first via holes overlapped by the fifth transparent conductive line 230 b.
  • this embodiment does not limit it.
  • the second transparent conductive layer and the third transparent conductive layer may also include fourth transparent conductive lines and fifth transparent conductive lines.
  • the overlapping area of the orthographic projection of any one of the fourth transparent conductive line and the fifth transparent conductive line on the base substrate and the orthographic projection of the first via hole on the base substrate is at A ratio of the length in a direction intersecting the extending direction of the transparent conductive line (for example, the first direction X) to the line width of the transparent conductive line may be greater than or equal to 0.5.
  • the orthographic projection of a transparent conductive line of the first transparent conductive layer (for example, the first transparent conductive line 231 ) on the base substrate is the same as the orthographic projection of the first via hole K12 on the base substrate.
  • the ratio of the length H10 of the overlapping area in the first direction X to the line width H6 of the transparent conductive line may be greater than or equal to 0.5, such as approximately 0.6 or 0.7.
  • the ratio of the length of the overlapping area of the transparent conductive line and the first via hole along the first direction X to the line width of the transparent conductive line may be greater than or equal to 0.5
  • the second The reflective focusing effect of the conductive layer affects the line width of the transparent conductive line overlapping the first via hole, for example, reduces the line width of the transparent conductive line overlapping the first via hole. In this way, the difference in capacitance between different transparent conductive lines can be reduced without other adverse conditions, so as to improve the display effect.
  • FIG. 17 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 18 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this exemplary embodiment has a 7T1C structure. However, this embodiment does not limit it.
  • the pixel circuit may have a structure such as 3T1C, 5T1C, 8T1C or 8T2C.
  • the pixel circuit of this example includes six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the display substrate includes scan lines GL, data lines DL, first power lines PL1, second power lines PL2, light emission control lines EML, first initial signal lines INIT1, second Two initial signal lines INIT2, a first reset control line RST1 and a second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit.
  • the first reset control line RST1 may be electrically connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first The reset control signal RESET1(n) is the same as the scan signal SCAN(n-1).
  • the second reset control line RST2 may be electrically connected to the scan line GL of the nth row of pixel circuits to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n).
  • the second reset control line RST2 electrically connected to the pixel circuit in the nth row and the first reset control line RST1 electrically connected to the pixel circuit in the n+1th row have an integral structure. In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • this embodiment does not limit it.
  • the first initial signal line INIT1 is configured to provide the first initial signal to the pixel circuit
  • the second initial signal line INIT2 is configured to provide the second initial signal to the pixel circuit.
  • the first initial signal and the second initial signal may be constant voltage signals whose magnitude may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the driving transistor T3 is electrically connected to the light emitting element EL, and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS. Output driving current to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is electrically connected to the scanning line GL
  • the first pole of the data writing transistor T4 is electrically connected to the data line DL
  • the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3 .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL
  • the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3
  • the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3 .
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML
  • the first pole of the first light emission control transistor T5 is electrically connected to the first power line PL1
  • the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML
  • the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3
  • the second pole of the second light emission control transistor T6 is connected to the light emission control line EML.
  • the anode of the element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL, and is configured to reset the gate of the light emitting element EL. Anode resets.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the grid is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the second reset transistor T7 is connected to the light emitting element EL. anode electrical connection.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T
  • the working process of the pixel circuit shown in FIG. 17 will be described below with reference to FIG. 18 .
  • the pixel circuit shown in FIG. 17 includes a plurality of transistors that are all P-type transistors as an example for description.
  • the working process of the pixel circuit with the first structure includes: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal to turn on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off. At this stage, the light emitting element EL does not emit light.
  • the second stage S2 is called a data writing stage or a threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the drive transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is supplied to the anode of the light-emitting element EL, and the anode of the light-emitting element EL is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization. , to ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage S3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 19 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • the display substrate in the first display area may include: a base substrate, and a semiconductor layer, a first insulating layer, and a first gate metal layer sequentially disposed on the base substrate.
  • the first insulating layer, the second insulating layer and the third insulating layer may be inorganic insulating layers
  • the fourth insulating layer may be an organic insulating layer.
  • the first source-drain metal layer is the first conductive layer in the foregoing embodiments
  • the second source-drain metal layer is the second conductive layer in the foregoing embodiments.
  • the film layer structure of the first conductive layer of the first display area near the base substrate in the foregoing embodiments can be referred to as shown in FIG. 19 .
  • the semiconductor layer may include: active layers of a plurality of transistors of the pixel circuit (for example, the active layer of the first transistor T1 to the active layer of the seventh transistor T7) .
  • the first gate metal layer may include: gates of multiple transistors of the pixel circuit, a first plate of a storage capacitor, a first reset control line RST1 , a second reset control line RST2 , a scan line GL and an emission control line EML.
  • the second gate metal layer may include: a second plate of the storage capacitor of the pixel circuit, a first initial signal line INIT1 , and a second initial signal line INIT2 .
  • the first source-drain metal layer may include: a data line DL, a first power line PL1, and a plurality of connection electrodes (eg, first anode connection electrodes).
  • the first anode connection electrode may be electrically connected to the second light emission control transistor T6 and the second reset transistor T7.
  • the second source-drain metal layer may include: a shielding electrode 222 and a second anode connection electrode 221 .
  • the blocking electrode 222 may be electrically connected to the first power line PL1.
  • the second anode connection electrode 221 may be electrically connected to the first anode connection electrode.
  • the shielding electrode 222 may have an irregular shape, so as to be configured to cover the first node N1, so as to reduce the crosstalk of the transparent conductive layer to the first node N1.
  • FIG. 20 is another schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • the shielding electrode 222a of the second conductive layer may be in a regular shape, such as a rectangle or a rectangle with rounded corners.
  • the shielding electrodes 222a of adjacent pixel circuits may be of an integral structure.
  • the shielding electrode 222a may be electrically connected to the first power line PL1 in a peripheral area.
  • this embodiment does not limit it.
  • the shielding electrode may be in a regular shape such as a circle or a pentagon or a hexagon.
  • the capacitance of the fourth node N4 will be larger, resulting in a longer turn-on time of the second light emitting element. , and the overlapping areas of different transparent conductive lines and the second conductive layer are different, which will affect the line width of the transparent conductive lines, resulting in differences in the capacitance of different transparent conductive lines, resulting in poor display.
  • the line width of the transparent conductive lines of the transparent conductive layer can be kept consistent, thereby reducing the capacitance difference between the transparent conductive lines of adjacent pixel circuits, thereby improving the low gray area. step display effect.
  • the structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate.
  • the "patterning process" mentioned in the embodiments of the present disclosure refers to metal materials, inorganic materials or transparent conductive materials, including coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments, and for organic materials , including coating organic materials, mask exposure and development and other treatments.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • Thin film refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • the manufacturing process of the display substrate may include the following operations.
  • the base substrate may be a rigid substrate, such as a glass substrate.
  • this embodiment does not limit it.
  • the base substrate may be a flexible substrate.
  • a semiconductor thin film is deposited on the base substrate in the first display region, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer.
  • the material of the semiconductor thin film may be polysilicon.
  • a first insulating film and a first metal film are sequentially deposited on the base substrate forming the aforementioned structure, and the first metal film is patterned by a patterning process to form a first insulating film covering the semiconductor layer. an insulating layer, and a first gate metal layer disposed on the first insulating layer in the first display area.
  • the semiconductor layer after forming the first gate metal layer pattern, the semiconductor layer may be subjected to conductorization treatment by using the first gate metal layer as a shield, and a plurality of transistors may be formed in the semiconductor layer in the area shielded by the first gate metal layer.
  • the channel region of the channel region, the semiconductor layer in the region not blocked by the first gate metal layer is conductorized, that is, the first doped region and the second doped region of the active layer of the first transistor T1 to the active layer of the seventh transistor T7 All regions are conductorized.
  • a second insulating film and a second metal film are sequentially deposited on the base substrate forming the aforementioned structure, and the second metal film is patterned by a patterning process to form a metal layer covering the first gate. the second insulating layer, and the second gate metal layer disposed on the second insulating layer of the first display area.
  • a third insulating film is deposited on the base substrate forming the aforementioned structure, and a third insulating layer is formed by a patterning process.
  • the third insulating layer is provided with a plurality of via holes.
  • a third metal film is deposited, and the third metal film is patterned through a patterning process to form a first source-drain metal layer disposed on the third insulating layer of the first display region.
  • the first source-drain metal layer is the aforementioned first conductive layer.
  • a fourth insulating film is coated on the base substrate forming the foregoing structure, and a fourth insulating layer is formed by a patterning process. Subsequently, a fourth metal thin film is deposited, and the fourth metal thin film is patterned through a patterning process to form a second source-drain metal layer disposed on the fourth insulating layer of the first display region.
  • the fourth insulating layer may also be referred to as a first planar layer.
  • the second source-drain metal layer is the aforementioned second conductive layer.
  • a second planar thin film is coated on the base substrate forming the foregoing structure, and a second planar layer is formed through a patterning process. Subsequently, the first transparent conductive film is deposited, and the first transparent conductive film is patterned through a patterning process to form the first transparent conductive layer disposed on the second planar layer.
  • a third planar thin film is coated on the base substrate forming the foregoing structure, and a third planar layer is formed by a patterning process. Subsequently, a second transparent conductive film is deposited, and the second transparent conductive film is patterned through a patterning process to form a second transparent conductive layer disposed on the third planar layer.
  • a fourth planar thin film is coated on the base substrate forming the foregoing structure, and a fourth planar layer is formed by a patterning process. Subsequently, a third transparent conductive film is deposited, and the third transparent conductive film is patterned through a patterning process to form a third transparent conductive layer disposed on the fourth planar layer.
  • a fifth planar thin film is coated on the base substrate forming the foregoing structure, and a fifth planar layer is formed through a patterning process. Subsequently, an anode conductive film is deposited, and the anode conductive film is patterned through a patterning process to form an anode layer disposed on the fifth flat layer.
  • a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) is formed through masking, exposure and development processes.
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer.
  • An organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode.
  • a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode pattern, and the cathode is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer can use metal materials, such as silver (Ag), copper (Cu), aluminum Any one or more of (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be single-layer structure, or multi-layer composite Structure, such as Mo/Cu/Mo etc.
  • the first transparent conductive layer to the third transparent conductive layer may use transparent conductive materials, such as ITO.
  • the first insulating layer, the second insulating layer and the third insulating layer can use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer , multi-layer or composite layer.
  • Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the first to fifth flat layers.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can use reflective materials such as metal, and the cathode can use transparent conductive materials. However, this embodiment does not limit it.
  • the structure of the display substrate and the manufacturing process thereof in this embodiment are merely illustrative.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • one or two transparent conductive layers may be provided.
  • the second conductive layer may be made of a transparent conductive material, so as to avoid reflection focusing effect during the preparation process of the transparent conductive layer.
  • this embodiment does not limit it.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and is well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • At least one embodiment of the present disclosure also provides a method for preparing a display substrate, including: forming a first conductive layer on the base substrate; forming a first flat layer on the side of the first conductive layer away from the base substrate; A second conductive layer is formed on the side away from the base substrate, and the second conductive layer is electrically connected to the first conductive layer through at least one first via hole penetrating the first planar layer; on the side of the second conductive layer away from the base substrate Forming a second flat layer; forming at least one transparent conductive layer on the side of the second flat layer away from the base substrate.
  • the transparent conductive layer includes: at least one first transparent conductive line and at least one auxiliary wiring.
  • the orthographic projection of the first transparent conductive line on the base substrate overlaps with the orthographic projection of the at least one first via hole on the base substrate. At least part of the auxiliary wiring is in the same extension direction as the first transparent conductive line, and the orthographic projection of the auxiliary wiring on the base substrate is adjacent to the orthographic projection of the first via hole on the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, including the above-mentioned display substrate.
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 21 , this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light emitting side of the display structure layer away from the display substrate 91 . The orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the second display area A2.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device can be any product or component with a display function such as an OLED display, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present disclosure are not limited thereto.

Abstract

一种显示基板，包括：衬底基板（10）、位于衬底基板（10）上的第一导电层（21）、第一平坦层（31）、第二导电层（22）、第二平坦层（32）以及至少一个透明导电层。第二导电层（22）通过贯穿第一平坦层（31）的至少一个第一过孔与第一导电层（21）电连接。透明导电层包括：至少一条第一透明导电线（231）和至少一条辅助走线（232）。第一透明导电线（231）在衬底基板（10）的正投影与至少一个第一过孔在衬底基板（10）的正投影存在交叠。辅助走线（232）的至少部分与第一透明导电线（231）的延伸方向相同，且辅助走线（232）在衬底基板（10）的正投影与第一过孔在衬底基板（10）的正投影相邻。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、位于衬底基板上的第一导电层、位于所述第一导电层远离所述衬底基板的一侧的第一平坦层、位于所述第一平坦层远离所述衬底基板的一侧的第二导电层、位于所述第二导电层远离所述衬底基板的一侧的第二平坦层、以及位于所述第二平坦层远离所述衬底基板的一侧的至少一个透明导电层。第二导电层通过贯穿所述第一平坦层的至少一个第一过孔与所述第一导电层电连接。所述透明导电层包括：至少一条第一透明导电线和至少一条辅助走线。所述第一透明导电线在所述衬底基板的正投影与所述至少一个第一过孔在所述衬底基板的正投影存在交叠。所述辅助走线的至少部分与所述第一透明导电线的延伸方向相同，且所述辅助走线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影相邻。
在一些示例性实施方式中，所述辅助走线沿所述延伸方向的长度大于所 述第一过孔沿所述延伸方向的孔径。
在一些示例性实施方式中，在所述延伸方向上，所述辅助走线和所述第一过孔的同侧边缘之间的间距小于5微米。
在一些示例性实施方式中，所述辅助走线沿所述延伸方向的交叉方向的线宽与所述第一透明导电线沿所述延伸方向的交叉方向的线宽的差值的绝对值小于或等于0.3微米。
在一些示例性实施方式中，在所述延伸方向的交叉方向上，所述辅助走线与所述第一透明导电线之间具有第一间距，所述第一间距与所述第一透明导电线沿所述延伸方向的交叉方向的线宽的差值的绝对值小于或等于0.35微米。
在一些示例性实施方式中，所述辅助走线沿所述延伸方向的长度为13.5微米至16.5微米；所述辅助走线沿所述延伸方向的交叉方向的线宽为1.9微米至2.4微米；沿所述延伸方向的交叉方向上，所述辅助走线与所述第一透明导电线之间的第一间距为2.1微米至2.6微米。
在一些示例性实施方式中，所述辅助走线在所述延伸方向的端部在所述衬底基板的正投影为圆弧形状。
在一些示例性实施方式中，所述至少一个透明导电层包括第一透明导电层。第一透明导电层还包括：至少一个第三阳极连接电极，所述辅助走线包括第一辅助走线。所述第一辅助走线与所述第三阳极连接电极为一体结构，所述第三阳极连接电极配置为与所述第二导电层的第二阳极连接电极电连接。
在一些示例性实施方式中，所述至少一个透明导电层还包括：位于所述第一透明导电层远离所述衬底基板一侧的第二透明导电层。所述第二透明导电层包括第二辅助走线和至少一个第四阳极连接电极。所述第二辅助走线与第四阳极连接电极为一体结构。
在一些示例性实施方式中，所述至少一个透明导电层还包括：位于所述第二透明导电层远离所述衬底基板一侧的第三透明导电层。所述第三透明导电层包括第三辅助走线和至少一个第五阳极连接电极。所述第三辅助走线与第五阳极连接电极为一体结构。
在一些示例性实施方式中，所述透明导电层还包括：多条相邻排布的第二透明导电线。所述多条第二透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影存在交叠。所述多条第二透明导电线包括：两条边缘透明导电线和至少一条非边缘透明导电线；所述至少一条非边缘透明导电线位于所述两条边缘透明导电线的中间。所述边缘透明导电线沿所述延伸方向的交叉方向的线宽大于所述非边缘透明导电线沿所述延伸方向的交叉方向的线宽。
在一些示例性实施方式中，所述边缘透明导电线沿所述延伸方向的交叉方向的线宽与所述非边缘透明导电线沿所述延伸方向的交叉方向的线宽之差的绝对值为0.3微米至0.5微米。
在一些示例性实施方式中，所述边缘透明导电线沿所述延伸方向的交叉方向的线宽为2.0微米至2.5微米，所述非边缘透明导电线沿所述延伸方向的交叉方向的线宽为1.8微米至2.2微米。
在一些示例性实施方式中，所述透明导电层还包括：至少一条第三透明导电线，所述第三透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影存在交叠，且所述第三透明导电线与其余透明导电线之间的间距大于4微米。所述第三透明导电线沿所述延伸方向的交叉方向的线宽大于所述边缘透明导电线沿所述延伸方向的交叉方向的线宽。
在一些示例性实施方式中，所述透明导电层还包括：至少一条第四透明导电线和至少一条第五透明导电线。所述第四透明导电线沿所述延伸方向的线长大于所述第五透明导电线沿所述延伸方向的线长，所述第四透明导电线沿所述延伸方向的交叉方向的线宽小于所述第五透明导电线沿所述延伸方向的交叉方向的线宽。
在一些示例性实施方式中，所述第四透明导电线在所述衬底基板的正投影与第一数目的第一过孔在所述衬底基板的正投影存在交叠，所述第五透明导电线在所述衬底基板的正投影与第二数目的第一过孔在所述衬底基板的正投影存在交叠，其中，所述第一数目大于所述第二数目。
在一些示例性实施方式中，所述第四透明导电线和第五透明导电线中任一透明导电线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正 投影的交叠区域，在与所述透明导电线的延伸方向交叉的方向上的长度，和所述透明导电线的线宽之比大于或等于0.5。
在一些示例性实施方式中，所述第四透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影的交叠面积，大于所述第五透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影的交叠面积。
在一些示例性实施方式中，所述第二导电层的材料为透明导电材料。
在一些示例性实施方式中，所述第二导电层包括：遮挡电极，所述遮挡电极与第一电源线电连接，所述遮挡电极在所述衬底基板的正投影被配置为覆盖所述显示基板的像素电路的第一节点在所述衬底基板的正投影。所述遮挡电极在所述衬底基板的正投影为规则形状。
在一些示例性实施方式中，所述遮挡电极在所述衬底基板的正投影为矩形或圆角矩形。
在一些示例性实施方式中，相邻所述像素电路的遮挡电极为一体结构。
在一些示例性实施方式中，所述显示基板包括第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区。所述显示基板还包括多个子像素，至少一个子像素包括所述像素电路和发光元件，所述像素电路配置为驱动所述发光元件。所述多个子像素包括至少一个第一子像素和至少一个第二子像素，所述第一子像素的像素电路和发光元件位于所述第一显示区，所述第二子像素的像素电路位于所述第一显示区，所述第二子像素的发光元件位于所述第二显示区，所述第二子像素的像素电路通过所述至少一个透明导电层与所述第二子像素的发光元件电连接。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法，包括：在衬底基板上形成第一导电层；在所述第一导电层远离所述衬底基板一侧形成第一平坦层；在所述第一平坦层远离所述衬底基板一侧形成第二导电层，所述第二导电层通过贯穿所述第一平坦层的至少一个第一过孔与所述第一导电层电连接；在所述第二导电层远离所述衬底基板的一侧形成第二平坦层；在所述 第二平坦层远离所述衬底基板的一侧形成至少一个透明导电层。所述透明导电层包括：至少一条第一透明导电线和至少一条辅助走线；所述第一透明导电线在所述衬底基板的正投影与所述至少一个第一过孔在所述衬底基板的正投影存在交叠。所述辅助走线的至少部分与所述第一透明导电线的延伸方向相同，且所述辅助走线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影相邻。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为本公开至少一实施例的显示基板的示意图；
图1B为本公开至少一实施例的显示基板的局部示意图；
图2为本公开至少一实施例的显示基板的局部俯视示意图；
图3为图2中沿P-P’方向的局部剖面示意图；
图4为图2中形成第一透明导电层后的显示基板的局部俯视示意图；
图5为图2中形成第二导电层后的显示基板的局部俯视示意图；
图6为图2中的第一透明导电层的制备过程中曝光工艺的原理示意图；
图7为本公开至少一实施例的显示基板的第一透明导电层的第一透明导电线和第一辅助走线的局部放大示意图；
图8为本公开至少一实施例的显示基板的另一局部俯视示意图；
图9为图8中沿Q-Q’方向的局部剖面示意图；
图10为图8中形成第三透明导电层后的显示基板的局部俯视示意图；
图11为图8中形成第二透明导电层后的显示基板的局部俯视示意图；
图12为本公开至少一实施例的显示基板的形成第二透明导电层后的另 一俯视示意图；
图13为一种显示基板的局部俯视示意图；
图14为本公开至少一实施例的显示基板的另一局部俯视示意图；
图15为一种显示基板的透明导电层的电容示意图；
图16为本公开至少一实施例的显示基板的另一局部俯视示意图；
图17为本公开至少一实施例的像素电路的等效电路图；
图18为本公开至少一实施例的像素电路的工作时序图；
图19为本公开至少一实施例的像素电路的俯视示意图；
图20为本公开至少一实施例的像素电路的另一俯视示意图；
图21为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方 位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半 透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
本公开中，“线长”表示沿走线延伸方向的长度，“线宽”表示在走线所在平面内，在与走线延伸方向交叉的方向(例如，延伸方向的垂直方向)上的长度。
本公开实施例提供一种显示基板，包括：衬底基板、位于衬底基板上的第一导电层、第一平坦层、第二导电层、第二平坦层以及至少一个透明导电层。第二导电层通过贯穿第一平坦层的至少一个第一过孔与第一导电层电连接。透明导电层包括：至少一条第一透明导电线和至少一条辅助走线。第一透明导电线在衬底基板的正投影与至少一个第一过孔在衬底基板的正投影存在交叠。辅助走线的至少部分与第一透明导电线的延伸方向相同，且辅助走线在衬底基板的正投影与第一过孔在衬底基板的正投影相邻。
在一些示例性实施方式中，显示基板可以包括一个透明导电层，或者可以包括多个透明导电层(例如，三个透明导电层)。例如，多个透明导电层中的每个透明导电层可以包括第一透明导电线和辅助走线，或者，多个透明导电层中的至少一个透明导电层可以包括第一透明导电线和辅助走线。然而，本实施例对此并不限定。
本实施例提供的显示基板，通过在第一透明导电线的周边设置辅助走线，可以改善透明导电层的曝光工艺的曝光环境，从而改善由于第二导电层在曝光工艺中的反射聚焦作用而导致透明导电层出现断线或线宽变细的情况。
在一些示例性实施方式中，辅助走线沿延伸方向的长度可以大于第一过孔沿延伸方向的孔径。在延伸方向上，辅助走线和第一过孔的同侧边缘之间的间距可以小于5微米(um)。本示例中，通过设置辅助走线，可以改善透明导电层的曝光工艺中的进光量和刻蚀时的刻蚀量，从而改善透明导电层的断线或线宽变细的情况。
在一些示例性实施方式中，辅助走线沿延伸方向的交叉方向的线宽与第 一透明导电线沿延伸方向的交叉方向的线宽的差值的绝对值可以小于或等于0.3微米。在延伸方向的交叉方向上，辅助走线与第一透明导电线之间具有第一间距，第一间距与第一透明导电线沿延伸方向的交叉方向的线宽的差值的绝对值可以小于或等于0.35微米。在一些示例中，辅助走线沿延伸方向的长度可以约为13.5微米至16.5微米，例如可以约为15微米；辅助走线沿延伸方向的交叉方向的线宽可以约为1.9微米至2.4微米，例如可以约为2.2微米；沿延伸方向的交叉方向上，辅助走线与第一透明导电线之间的第一间距可以约为2.1微米至2.6微米，例如可以约为2.35微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，辅助走线在延伸方向的端部在衬底基板的正投影可以为圆弧形状。本示例中，通过设计辅助走线的端部为圆弧形状，可以改善透明导电层制备过程中的掩膜放电问题，从而改善透明导电层的断线或线宽变细的情况。
在一些示例性实施方式中，至少一个透明导电层可以包括：第一透明导电层。第一透明导电层可以包括：至少一个第三阳极连接电极。辅助走线可以包括：第一辅助走线。第一辅助走线与第三阳极连接电极可以为一体结构。第三阳极连接电极配置为与第二导电层的第二阳极连接电极电连接。然而，本实施例对此并不限定。例如，第一透明导电层的第一辅助走线与第三阳极连接电极可以相互独立设置。比如，第一透明导电层的第一辅助走线可以与第一电源线或第二电源线电连接。
在一些示例性实施方式中，至少一个透明导电层还可以包括：位于第一透明导电层远离衬底基板一侧的第二透明导电层。第二透明导电层可以包括第二辅助走线和至少一个第四阳极连接电极，第二辅助走线与第四阳极连接电极可以为一体结构。在一些示例中，第四阳极连接电极可以配置为与第一透明导电层的第三阳极连接电极电连接。然而，本实施例对此并不限定。例如，第四阳极连接电极可以配置为与第二导电层的第二阳极连接电极电连接。在另一些示例中，第二透明导电层的第二辅助走线与第四阳极连接电极可以相互独立设置。比如，第二透明导电层的第二辅助走线可以与第一电源线或第二电源线电连接。
在一些示例性实施方式中，至少一个透明导电层还可以包括：位于第二透明导电层远离衬底基板一侧的第三透明导电层。第三透明导电层可以包括第三辅助走线和至少一个第五阳极连接电极，第三辅助走线与第五阳极连接电极可以为一体结构。在一些示例中，第五阳极连接电极可以配置为与第二透明导电层的第四阳极连接电极电连接。然而，本实施例对此并不限定。例如，第五阳极连接电极可以配置为与第二导电层的第二阳极连接电极电连接。在另一些示例中，第三透明导电层的第三辅助走线与第五阳极连接电极可以相互独立设置。比如，第三透明导电层的第三辅助走线可以与第一电源线或第二电源线电连接。
在一些示例性实施方式中，透明导电层还可以包括：多条相邻排布的第二透明导电线。多条第二透明导电线在衬底基板的正投影与第二导电层在衬底基板的正投影存在交叠。多条第二透明导电线可以包括：两条边缘透明导电线和至少一条非边缘透明导电线。至少一条非边缘透明导电线位于两条边缘透明导电线的中间。边缘透明导电线沿延伸方向的交叉方向的线宽大于非边缘透明导电线沿延伸方向的交叉方向的线宽。在一些示例中，第一透明导电层、第二透明导电层和第三透明导电层中的至少一个透明导电层可以包括多条第二透明导电线。在本示例中，针对多条相邻排布的第二透明导电线，通过增加边缘透明导电线的线宽，可以改善透明导电层的曝光工艺中的进光量和刻蚀时的刻蚀量，从而改善透明导电层的线宽一致性。
在一些示例性实施方式中，边缘透明导电线沿延伸方向的交叉方向的线宽与非边缘透明导电线沿延伸方向的交叉方向的线宽之差的绝对值可以为0.3微米至0.5微米。例如，边缘透明导电线沿延伸方向的交叉方向的线宽可以约为2.0微米至2.5微米，比如可以约为2.3微米，非边缘透明导电线沿延伸方向的交叉方向的线宽可以约为1.8微米至2.2微米，比如可以约为2.0微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，透明导电层还可以包括：至少一条第三透明导电线。第三透明导电线在衬底基板的正投影与第二导电层在衬底基板的正投影存在交叠，且第三透明导电线与其余透明导电线之间的间距大于4微米。第三透明导电线沿延伸方向的交叉方向的线宽大于边缘透明导电线沿延伸方 向的交叉方向的线宽。在一些示例中，第一透明导电层、第二透明导电层和第三透明导电层中的至少一个透明导电层可以包括多条第二透明导电线。在本示例中，第三透明导电线单独设置，周边可以没有相邻的其余透明导电线，即第三透明导电线可以为独立单根走线。针对单独排布的第三透明导电线，通过增加第三透明导电线的线宽，可以改善透明导电层的曝光工艺中的进光量和刻蚀时的刻蚀量，从而改善透明导电层的线宽一致性。
在本示例性实施方式中，在透明导电线所在平面内，任一透明导电线周边4微米范围内没有其余透明导电线，则认为该透明导电线没有相邻的透明导电线，即该透明导电线为单独设置的导电线。任一透明导电线与其余透明导电线之间的间距小于或等于4微米，则认为该透明导电线具有相邻的透明导电线。
在一些示例性实施方式中，透明导电层还可以包括：至少一条第四透明导电线和至少一条第五透明导电线。第四透明导电线沿延伸方向的线长大于第五透明导电线沿延伸方向的线长，第四透明导电线沿延伸方向的交叉方向的线宽小于第五透明导电线沿延伸方向的交叉方向的线宽。在一些示例中，第一透明导电层、第二透明导电层和第三透明导电层中的至少一个透明导电层可以包括第四透明导电线和第五透明导电线。本示例中，通过调整不同透明导电线的线长和线宽，可以减少不同透明导电线之间的电容差异，从而改善显示效果。
在一些示例性实施方式中，第四透明导电线在衬底基板的正投影与第一数目的第一过孔在衬底基板的正投影存在交叠，第五透明导电线在衬底基板的正投影与第二数目的第一过孔在衬底基板的正投影存在交叠，其中，第一数目大于第二数目。在本示例中，与第四透明导电线交叠的第一过孔的数目大于与第五透明导电线交叠的第一过孔的数目，在透明导电层的制备过程中，由于第二导电层的反射聚焦作用，可以使得第四导电线的线宽小于第五导电线的线宽。在本示例中，通过调整透明导电线与第一过孔的交叠面积，可以改善透明导电线的线宽，以减小不同透明导电线之间的电容差异。
在一些示例性实施方式中，第四透明导电线在衬底基板的正投影与第二导电层在衬底基板的正投影的交叠面积，大于第五透明导电线在衬底基板的 正投影与第二导电层在衬底基板的正投影的交叠面积。在本示例中，在透明导电层的制备过程中，由于第二导电层的反射聚焦作用，可以使得第四导电线的线宽小于第五导电线的线宽。在本示例中，通过调整透明导电线与第二导电层的交叠面积，可以改善透明导电线的线宽，以减小不同透明导电线之间的电容差异。
在一些示例性实施方式中，第二导电层的材料可以为透明导电材料，例如氧化铟锡(ITO)。本示例通过设置第二导电层的材料为透明导电材料，在透明导电层的制备过程中，第二导电层不会产生反射聚焦作用，可以改善透明导电层的断线和线宽变细的情况。
在一些示例性实施方式中，第二导电层包括：遮挡电极。遮挡电极与第一电源线电连接，遮挡电极在衬底基板的正投影被配置为覆盖显示基板的像素电路的第一节点在衬底基板的正投影。遮挡电极在衬底基板的正投影为规则形状。例如，遮挡电极在衬底基板的正投影可以为矩形或圆角矩形。然而，本实施例对此并不限定。本示例通过设置规则形状的遮挡电极，可以减小对透明导电层的线宽影响，并减小不同透明导电线的电容差异，从而改善显示效果。
下面通过一些示例对本实施例的方案进行举例说明。下面以显示基板为适用于全面屏和屏下摄像技术的显示基板为例进行说明。然而，本实施例对此并不限定。
图1A为本公开至少一实施例的显示基板的示意图。图1B为本公开至少一实施例的显示基板的局部示意图。在一些示例性实施方式中，如图1A和图1B所示，显示基板包括：显示区域AA和周边区域BB。周边区域BB为非显示区域。显示区域AA可以包括：第一显示区A1和第二显示区A2。例如，感光传感器(例如，摄像头)等硬件设置在显示基板的一侧，且感光传感器在显示基板的正投影与第二显示区A2交叠。第二显示区A2可以为透光显示区，还可以称为屏下摄像头(UDC，Under Display Camera)区域；第一显示区A1可以为正常显示区。例如，第一显示区A1不透光仅用于显示。本实施例的显示基板可以给真全面屏的实现奠定坚实的基础。
在一些示例性实施方式中，如图1A所示，显示区域AA可以为矩形， 例如圆角矩形。第二显示区A2可以为矩形，例如圆角矩形。然而，本实施例对此并不限定。例如，第二显示区A2可以为圆形、其他四边形或五边形等形状。
在一些示例性实施方式中，如图1A所示，显示基板可以包括：衬底基板以及位于衬底基板上的多个子像素。多个子像素包括：多个第一子像素和多个第二子像素。至少一个第一子像素包括第一像素电路11和第一发光元件13，至少一个第二子像素包括第二像素电路12和第二发光元件14。第一像素电路11和第一发光元件13均位于第一显示区A1，第二像素电路12位于第一显示区A1，第二发光元件14位于第二显示区A2。多个第二像素电路12可以间隔分布在多个第一像素电路11之间。例如，第一像素电路11可以称为原位像素电路，第二像素电路12可以称为非原位像素电路。在第二显示区A2内，相邻第二发光元件14之间为透光子区，第二发光元件14所在区域为显示子区。
在一些示例性实施方式中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
为了提高第二显示区A2的光透过率，可以在第二显示区A2仅设置发光元件，而将驱动第二显示区A2的发光元件的像素电路设置在第一显示区A1。即通过发光元件和像素电路分离设置的方式来提高第二显示区A2的光透过率。第二显示区A2不设置像素电路。
在一些示例性实施方式中，如图1A所示，多个第一像素电路11中的至少一个第一像素电路11可以与多个第一发光元件13中的至少一个第一发光元件13电连接，且至少一个第一像素电路11在衬底基板的正投影与至少一个第一发光元件13在衬底基板的正投影至少部分重叠。至少一个第一像素电路11可以配置为给所电连接的第一发光元件13提供驱动信号，以驱动第一发光元件13发光。
图1A以驱动第二发光元件14发光的第二像素电路12位于第一显示区 A1为例，该情况下的显示基板可以采用像素电路压缩方案，在像素电路压缩方案中，减小像素电路在第一方向X上的尺寸，从而可以在第一方向X上放置第一像素电路11和第二像素电路12，可以将第二像素电路12分散布置在第一像素电路11中。例如，第一方向X为行方向，在同一行像素电路中，第二像素电路12间隔布置在第一像素电路11中。然而，本实施例对此并不限定。例如，第二像素电路12可以位于周边区域，从而形成像素电路外置方案。
在一些示例性实施方式中，如图1A所示，第一显示区A1可以位于第二显示区A2的至少一侧。例如，第一显示区A1可以围绕第二显示区A2。即，第二显示区A2可以被第一显示区A1包围。在另一些示例中，第二显示区A2可以设置在其他位置，例如，可以位于衬底基板的顶部中间位置，或者，位于衬底基板的左上角位置或右上角位置处。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1A和图1B所示，多个第二像素电路12中的至少一个第二像素电路12可以与多个第二发光元件14中的至少一个第二发光元件14通过透明导电线L电连接。透明导电线L的一端与第二像素电路12电连接，另一端与第二发光元件14电连接。透明导电线L从第一显示区A1延伸至第二显示区A2。例如，透明导电线L可以沿第一方向X从第一显示区A1延伸至第二显示区A2；或者，透明导电线L可以先在第一显示区A1沿第二方向Y延伸，再沿第一方向X延伸至第二显示区A2。然而，本实施例对此并不限定。
在一些示例性实施方式中，透明导电线L可以采用透明导电材料，例如，可以采用导电氧化物材料，比如，氧化铟锡(ITO)。然而，本实施例对此并不限定。在一些示例中，透明导电线L可以排布在一个透明导电层中，或者，多个透明导电线L可以排布在两个或三个透明导电层中。每一条透明导电线L可以连接一个第二像素电路12和一个第二发光元件14。
在一些示例性实施方式中，至少一个第二像素电路12配置为给所电连接的至少一个第二发光元件14提供驱动信号，以驱动第二发光元件14发光。第二像素电路12和第二发光元件14位于不同区域，第二像素电路12在衬底基板的正投影与至少一个第二发光元件14在衬底基板的正投影不存在交叠。 如图1A所示，第二发光元件14和与其电连接的第二像素电路12可以位于同一行。即，第二发光元件14的驱动信号来自于同一行的第二像素电路12。例如，同一行子像素的像素电路与同一条栅线电连接。然而，本实施例对此并不限定。例如，第二发光元件和与其电连接的第二像素电路可以不位于同一行。
图2为本公开至少一实施例的显示基板的局部俯视示意图。图2可以为图1B中区域S的局部放大示意图。图3为图2中沿P-P’方向的局部剖面示意图。图4为图2中形成第一透明导电层后的显示基板的局部俯视示意图。图5为图2中形成第二导电层后的显示基板的局部俯视示意图。图2至图5中省略示意了第一导电层靠近显示基板一侧的多个膜层结构。
在一些示例性实施方式中，如图2和图3所示，在垂直于显示基板的方向上，第一显示区A1的显示基板可以包括：衬底基板10、依次设置在衬底基板10上的第一导电层21、第一平坦层31、第二导电层22、第二平坦层32、第一透明导电层23、第三平坦层33以及阳极层26。在一些示例中，第一导电层21还可以称为第一源漏金属层，第二导电层22还可以称为第二源漏金属层。第一平坦层31、第二平坦层32和第三平坦层33可以为有机材料层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2至图5所示，第一导电层21至少可以包括：多条数据线(例如，数据线DL)、多条第一电源线(例如，第一电源线PL1)以及多个连接电极(例如，第一阳极连接电极211)。数据线DL和第一电源线PL1可以沿第二方向Y延伸，且数据线DL和第一电源线PL1在第一方向X上相邻。第二导电层22至少可以包括：多个连接电极(例如，遮挡电极222和第二阳极连接电极221)。第二阳极连接电极221可以通过第一平坦层31上开设的第一过孔K11与第一阳极连接电极211电连接。遮挡电极222可以通过第一平坦层31上开设的第一过孔K12与第一电源线PL1电连接。第一透明导电层23至少包括多条透明导电线(例如，第一透明导电线231)、至少一条辅助走线(例如，第一辅助走线232)、以及多个连接电极(例如，第三阳极连接电极233)。第三阳极连接电极233可以通过第二平坦层32上开设的第二过孔K2与第二阳极连接电极221电连接。第三阳极 连接电极233与第一辅助走线232可以为一体结构。阳极层26可以包括多个阳极(例如，阳极261)。阳极261可以通过第三平坦层33开设的第三过孔K3与第三阳极连接电极233电连接。
图6为图2中的第一透明导电层的制备过程中曝光工艺的原理示意图。在一些实现方式中，第一透明导电层的制备过程包括：在第二平坦层32上形成第一透明导电薄膜41，在第一透明导电薄膜41上形成光刻胶薄膜42，以掩膜版为掩膜对光刻胶薄膜42进行曝光，从而使得光刻胶薄膜形成光刻胶保留部和光刻胶待去除部，曝光工艺后进行显影工艺，在显影工艺中，将光刻胶待去除部去除，形成光刻胶图形。以光刻胶图形为掩膜对第一透明导电薄膜41进行刻蚀，形成第一透明导电层。然而，如图6所示，在曝光工艺中，金属材料的第二导电层22会反射光线并聚光至位于第二导电层22的呈碗形的部分上方的光刻胶保留部，使得这部分光刻胶被曝光或者部分曝光，显影后被洗去，从而以光刻胶图形为掩膜刻蚀第一透明导电薄膜后形成的透明导电线容易出现断线或变细。在第一平坦层31的过孔位置，由于第二导电层22在曝光工艺中的反射聚焦作用，会造成过孔位置的光刻胶薄膜变薄，从而导致最终形成的透明导电线出现断线或变细。在第二导电层22和第一透明导电层的交叠位置，由于第二导电层22在曝光工艺中的反射聚焦作用，同样会造成第二导电层22上方的光刻胶薄膜变薄，进而导致第一透明导电层形成的透明导电线变细。
本实施例提供的显示基板，通过在透明导电线的一侧设置至少一条辅助走线，改善曝光工艺中的进光量和刻蚀时的刻蚀量，从而对透明导电线的线宽产生影响，改善由于第二导电层在曝光工艺中的反射聚焦作用而导致透明导电线出现断线或变细的情况。
在一些示例性实施方式中，如图2至图5所示，第一透明导电层的第一辅助走线232和第一透明导电线231均沿第二方向Y延伸。第一辅助走线232在第一方向X上位于第一透明导电线231的一侧，第一透明导电线231的另一侧与其余透明导电线相邻。第一透明导电线231在衬底基板10的正投影与第一过孔K11在衬底基板10的正投影存在交叠。第一辅助走线232在衬底基板10的正投影在第一方向X与第一过孔K11在衬底基板10的正投影相邻。 然而，本实施例对此并不限定。例如，第一辅助走线232在衬底基板的正投影可以为L型，其中一部分可以沿第二方向Y延伸，另一部分可以沿第一方向X延伸。
图7为本公开至少一实施例的显示基板的第一透明导电层的第一透明导电线和第一辅助走线的局部放大示意图。在一些示例性实施方式中，如图7所示，第一透明导电层的第一辅助走线232沿第一方向X位于第一透明导电线231的一侧。第一辅助走线232与第三阳极连接电极233可以为一体结构。然而，本实施例对此并不限定。例如，第一辅助走线232和第三阳极连接电极233可以相互独立，第一辅助走线232可以与其余走线(例如，第一电源线或第二电源线)电连接。
在一些示例性实施方式中，如图7所示，第三阳极连接电极233可以为矩形，例如圆角矩形。第一辅助走线232例如为沿第二方向Y延伸的条状结构。在第二方向Y上，第一辅助走线232的一端与第三阳极连接电极233连接，第一辅助走线232的另一端部在衬底基板的正投影可以为圆弧结构。在本示例中，通过设置第一辅助走线232的端部在衬底基板的正投影为圆弧形状，可以改善制备工艺中掩膜放电的问题，从而改善线宽变细甚至断线的情况。
在一些示例性实施方式中，如图7所示，第一辅助走线232沿延伸方向的线长(即沿第二方向Y的长度)H1可以大于第一过孔K12沿第二方向Y的孔径。在第二方向Y上，第一辅助走线232与第一过孔K12的同侧边缘之间的间距H2可以小于5微米，第一辅助走线232与第一过孔K12的另一同侧边缘之间的间距H3可以小于5微米。第一辅助走线232沿延伸方向的交叉方向(例如，沿第一方向X)的线宽H4与第一透明导电线231沿延伸方向的交叉方向(例如，沿第一方向X)的线宽H6的差值的绝对值可以小于或等于0.3微米。第一辅助走线232在第一方向X上与第一透明导电线231之间具有第一间距H5，第一间距H5与第一透明导电线231沿第一方向X的线宽H6的差值的绝对值可以小于或等于0.35微米。例如，第一辅助走线232沿第二方向Y的长度H1可以约为13.5微米至16.5微米，比如约为15微米；第一辅助走线232的线宽H4可以约为1.9微米至2.4微米，比如约为2.2微 米；第一辅助走线232在第一方向X上与第一透明导电线231之间的第一间距H5可以约为2.1微米至2.6微米，比如约为2.35微米。然而，本实施例对此并不限定。
图8为本公开至少一实施例的显示基板的另一局部俯视示意图。图8可以为图2中区域S的另一局部放大示意图。图9为图8中沿Q-Q’方向的局部剖面示意图。图10为图8中形成第三透明导电层后的显示基板的局部俯视示意图。图11为图8中形成第二透明导电层后的显示基板的局部俯视示意图。图12为本公开至少一实施例的显示基板形成第二透明导电层后的另一俯视示意图。图8至图12省略示意了第一导电层靠近衬底基板一侧的多个膜层结构。
在一些示例性实施方式中，如图8和图9所示，在垂直于显示基板的方向上，第一显示区A1的显示基板可以包括：衬底基板10、依次设置在衬底基板10上的第一导电层21、第一平坦层31、第二导电层22、第二平坦层32、第一透明导电层23、第三平坦层33、第二透明导电层24、第四平坦层34、第三透明导电层25、第五平坦层35以及阳极层26。在一些示例中，第一平坦层31、第二平坦层32、第三平坦层33、第四平坦层34和第五平坦层35可以为有机材料层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8至图12所示，第一导电层21至少可以包括：数据线DL、第一电源线PL1以及多个连接电极(例如，第一阳极连接电极211)。第二导电层22至少可以包括：遮挡电极222以及第二阳极连接电极221。第二阳极连接电极221通过第一平坦层31开设的第一过孔与第一阳极连接电极211电连接，遮挡电极222通过第一平坦层31开设的第一过孔与第一电源线PL1电连接。第一透明导电层23至少包括多条透明导电线(例如，图12所示的沿第一方向X延伸的多条透明导电线230)、第一辅助走线以及第三阳极连接电极233。第三阳极连接电极233通过第二平坦层32开设的第二过孔与第二阳极连接电极221电连接。第二透明导电层24至少包括：多条透明导电线(例如，第一透明导电线241)、第二辅助走线242以及第四阳极连接电极243。第四阳极连接电极243通过第三平坦层33开设的第三过孔与第三阳极连接电极233电连接。第三透明导电层25至少包括： 多条透明导电线(例如，沿第二方向Y延伸的多条透明导电线250)以及第五阳极连接电极251。第五阳极连接电极251通过第四平坦层34开设的第四过孔与第四阳极连接电极243电连接。阳极层26可以包括多个阳极(例如，阳极261)。阳极261可以通过第五平坦层35开设的第五过孔与第五阳极连接电极251电连接。在本示例中，第二导电层22的第二阳极连接电极可以通过三个透明导电层依次设置的阳极连接电极(即包括第一透明导电层的第三阳极连接电极、第二透明导电层的第四阳极连接电极以及第三透明导电层的第五阳极连接电极)，实现与阳极的电连接。然而，本实施例对此并不限定。例如，第二导电层22的第二阳极连接电极可以通过第一透明导电层的第三阳极连接电极、第二透明导电层的第四阳极连接电极或者第三透明导电层的第五阳极连接电极，实现与阳极的电连接。
在一些示例性实施方式中，如图11和图12所示，第二透明导电层的第一透明导电线241在衬底基板10的正投影与第一过孔在衬底基板10的正投影存在交叠。第一透明导电线241的一侧设置第二辅助走线242，第二辅助走线242和第一透明导电线241的延伸方向相同，例如均沿第二方向Y延伸。第二辅助走线242在衬底基板10的正投影在第一方向X上与第一过孔在衬底基板10的正投影相邻。第二辅助走线242在第二方向Y的端部在衬底基板10的正投影为圆弧形状。关于第二透明导电层的第一透明导电线和第二辅助走线的结构可以参照上述实施例的第一透明导电层的第一透明导电线和第一辅助走线的结构示意，故于此不再赘述。在本示例中，在第一透明导电层，同样可以在与第一过孔存在交叠的第一透明导电线的周边设置第一辅助走线；在第三透明导电层，可以在于第一过孔存在交叠的第一透明导电线的周边设置第三辅助走线。例如，第三透明导电层可以同样设置第三辅助走线，第三辅助走线可以与第五阳极连接电极为一体结构。第一透明导电层可以同样设置第一辅助走线，且第一辅助走线可以与第三阳极连接电极为一体结构。然而，本实施例对此并不限定。在一些示例中，第二透明导电层的第二辅助走线与第四阳极连接电极可以相互独立，第一透明导电层的第一辅助走线与第三阳极连接电极可以相互独立，第三透明导电层的第三辅助走线与第五阳极连接电极可以相互独立。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图13为一种显示基板的局部俯视示意图。如图13所示，一个透明导电层(例如，第一透明导电层、第二透明导电层或第三透明导电层)可以包括：单根透明导电线300a以及多条相邻的透明导电线300b。多条透明导电线300b依次相邻设置，且在衬底基板的正投影均与第二导电层在衬底基板的正投影存在交叠。透明导电线300b的线宽存在变细的情况，如图13中标示出的区域③和④所示，透明导电线300b在区域③和④处的线宽均小于透明导电线300b未与第二导电层交叠的线宽。单根透明导电线300a的线宽存在变细的情况，如图13中标示出的区域①和②所示，透明导电线300a在区域②处的线宽大于在区域①处的线宽。由于第二导电层在曝光工艺中的反射聚焦作用，会造成第二导电层上方的光刻胶薄膜变薄，进而导致形成的透明导电线变细。
图14为本公开至少一实施例的显示基板的另一局部俯视示意图。图14中以第二导电层和第一透明导电层为例进行示意。在一些示例性实施方式中，如图14所示，第一透明导电层可以包括：多条第二透明导电线(例如，边缘透明导电线234和236、非边缘透明导电线235)。多条第二透明导电线相邻排布，且在衬底基板的正投影与第二导电层的遮挡电极222在衬底基板的正投影存在交叠。边缘透明导电线234的左侧没有相邻的透明导电线，边缘透明导电线236的至少部分的右侧没有相邻的透明导电线，两条非边缘透明导电线235位于边缘透明导电线234和236的中间。在一些示例中，边缘透明导电线234和236沿延伸方向的交叉方向的线宽可以大致相同，且可以大于非边缘透明导电线235沿延伸方向的交叉方向的线宽。边缘透明导电线(例如，边缘透明导电线234或236)的线宽与非边缘透明导电线235的线宽之差的绝对值可以为0.3微米至0.5微米。例如，边缘透明导电线234沿延伸方向的交叉方向的线宽H7可以约为2.0微米至2.5微米，比如可以约为2.3微米，边缘透明导电线236沿延伸方向的交叉方向的线宽H8可以约为2.0微米至2.5微米，比如可以约为2.3微米，非边缘透明导电线235沿延伸方向的交叉方向的线宽H9可以约为1.8微米至2.2微米，比如可以约为2.0微米。边缘透明导电线236右侧大于或等于5微米范围内没有设置其余透明导电线。 边缘透明导电线236随着第一方向X延伸后，在第二方向Y上会存在相邻的透明导电线，存在相邻透明导电线的边缘透明导电线236的线宽可以与非边缘透明导电线235的线宽大致相同。换言之，边缘透明导电线236可以包括第一部分和第二部分，第一部分在周边5微米范围内没有相邻透明导电线，第二部分在5微米范围内存在相邻透明导电线，第一部分的线宽可以大于第二部分的线宽。在本示例中，通过对周边没有相邻透明导电线的单侧边缘的透明导电线进行线宽补偿，可以确保相邻透明导电线之间没有短路风险，并改善透明导电线线宽变细的情况。然而，本实施例对此并不限定。在另一些示例中，第二透明导电层和第三透明导电层可以同样包括多条第二透明导电线，且多条第二透明导电线中的边缘透明导电线的线宽可以大于非边缘透明导电线的线宽。
在一些示例性实施方式中，第一透明导电层还可以包括：单根的第三透明导电线(例如，图13中的透明导电线300a)。第三透明导电线300a在衬底基板的正投影与第二导电层在衬底基板的正投影存在交叠。在平行于显示基板所在平面内，第三透明导电线300a的周边4微米范围内没有排布其余透明导电线。第三透明导电线300a沿延伸方向的交叉方向的线宽可以大于边缘透明导电线(例如，图14中的边缘透明导电线234和236)沿延伸方向的交叉方向的线宽。例如，第三透明导电线300a的线宽可以约为2.3微米至2.8微米，比如可以约为2.6微米。在本示例中，通过对第三透明导电线的线宽进行补偿，可以改善第一透明导电层的曝光环境，从而改善透明导电线的线宽变细的情况。然而，本实施例对此并不限定。在另一些示例中，第二透明导电层和第三透明导电层可以同样包括第三透明导电线，且第三透明导电线的线宽可以大于多条第二透明导电线中的边缘透明导电线的线宽。
图15为一种显示基板的透明导电层的电容示意图。如图15所示，横坐标表示显示基板的第二显示区A2在第一方向上的位置，纵坐标表示与该位置处的发光元件相连的透明导电线的电容量占总电容量的比值。第二显示区A2的第二发光元件通过透明导电线与第一显示区A1的第二像素电路电连接，透明导电线的电容对于第二发光元件的显示效果产生影响。在高灰阶下，透明导电线的电容大会导致发光时长减小、亮度偏暗；低灰阶下，电容大会导 致第二发光元件无法启亮、亮度偏暗的情况。由此可见，透明导电线的电容对显示基板的显示不良影响较大，而且电容差异越大，显示不良现象越明显。本实施例提供的显示基板，通过设置透明导电线的线长和线宽，来降低不同透明导电线之间的电容差异，以改善显示效果。
在一些示例性实施方式中，本实施例的显示基板的透明导电层可以包括：至少一条第四透明导电线和至少一条第五透明导电线。例如，第一透明导电层、第二透明导电层和第三透明导电层中的至少一个可以包括第四透明导电线和第五透明导电线。第四透明导电线沿延伸方向的线长大于第五透明导电线沿延伸方向的线长，第四透明导电线沿延伸方向的交叉方向的线宽小于第五透明导电线沿延伸方向的交叉方向的线宽。本示例中，将线长大的透明导电线的线宽设置得较小，将线长小的透明导电线的线宽设置得较大，以尽量减小不同透明导电线之间的电容差异。
在一些示例性实施方式中，第四透明导电线在衬底基板的正投影与第一数目的第一过孔在衬底基板的正投影存在交叠，第五透明导电线在衬底基板的正投影与第二数目的第一过孔在衬底基板的正投影存在交叠，其中，第一数目大于第二数目。在本示例中，通过设置第四透明导电线与较多的第一过孔交叠，从而增加第二导电层在曝光工艺中的反射聚焦作用对第四透明导电线的线宽影响，以减小第四透明导电线的线宽。
在一些示例性实施方式中，第四透明导电线在衬底基板的正投影与第二导电层在衬底基板的正投影的交叠面积，大于第五透明导电线在衬底基板的正投影与第二导电层在衬底基板的正投影的交叠面积。在本示例中，通过设置第四透明导电线与第二导电层的交叠面积大于第五透明导电线与第二导电层的交叠面积，可以增加第二导电层在曝光工艺中的反射聚焦作用对第四透明导电线的线宽影响，以减小第四透明导电线的线宽。
图16为本公开至少一实施例的显示基板的另一局部俯视示意图。图16中仅以第二导电层和第一透明导电层为例进行示意。在一些示例性实施方式中，如图16所示，第二导电层通过第一平坦层开设的第一过孔与第一导电层电连接。例如，第二导电层的遮挡电极222可以通过第一平坦层开设的第一过孔K11与第一导电层电连接。第一透明导电层至少包括多条透明导电线(例 如，第四透明导电线230a和第五透明导电线230b)。第四透明导电线230a与第一数目的第一过孔在衬底基板的正投影存在交叠，第五透明导电线230b与第二数目的第一过孔在衬底基板的正投影存在交叠。例如，第一数目大于第二数目。即，第四透明导电线230a所交叠的第一过孔的数目大于第五透明导电线230b所交叠的第一过孔的数目。然而，本实施例对此并不限定。例如，第二透明导电层和第三透明导电层同样可以包括第四透明导电线和第五透明导电线。
在一些示例性实施方式中，第四透明导电线和第五透明导电线中任一透明导电线在衬底基板的正投影与第一过孔在衬底基板的正投影的交叠区域，在与透明导电线的延伸方向交叉的方向(例如，第一方向X)上的长度，和透明导电线的线宽之比可以大于或等于0.5。在一些示例中，如图7所示，第一透明导电层的一条透明导电线(例如第一透明导电线231)在衬底基板的正投影与第一过孔K12在衬底基板的正投影的交叠区域，在第一方向X上的长度H10，和透明导电线的线宽H6之比可以大于或等于0.5，比如可以约为0.6或0.7。在本示例中，透明导电线与第一过孔的交叠区域沿第一方向X的长度和透明导电线的线宽之比可以大于或等于0.5，可以利用透明导电层的制备过程中第二导电层的反射聚焦作用，对与第一过孔交叠的透明导电线的线宽产生影响，比如减小与第一过孔交叠的透明导电线的线宽。如此一来，可以在确保没有其他不良的情况保证不同透明导电线之间的电容差异减小，以改善显示效果。
图17为本公开至少一实施例的像素电路的等效电路图。图18为本公开至少一实施例的像素电路的工作时序图。本示例性实施例的像素电路为7T1C结构。然而，本实施例对此并不限定。例如，像素电路可以为3T1C、5T1C、8T1C或8T2C等结构。
在一些示例性实施方式中，如图17所示，本示例的像素电路包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括阳极、阴极和设置在阳极和阴极之间的有机 发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图17所示，显示基板包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。第二复位控制线RST2可以与第n行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)相 同。在一些示例中，第n行像素电路所电连接的第二复位控制线RST2与第n+1行像素电路所电连接的第一复位控制线RST1为一体结构。如此，可以减少显示基板的信号线，实现显示基板的窄边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1配置为向像素电路提供第一初始信号，第二初始信号线INIT2配置为向像素电路提供第二初始信号。例如，第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。
在一些示例性实施方式中，如图17所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电极与驱动晶体管T3的栅极电连接，存储电容Cst的第 二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图18对图17示意的像素电路的工作过程进行说明。以图17所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图18所示，在一帧显示时间段，第一结构的像素电路的工作过程包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即 第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图19为本公开至少一实施例的像素电路的俯视示意图。在一些示例性实施方式中，如图19所示，第一显示区的显示基板可以包括：衬底基板、以及依次设置在衬底基板上的半导体层、第一绝缘层、第一栅金属层、第二绝缘 层、第二栅金属层、第三绝缘层、第一源漏金属层、第四绝缘层以及第二源漏金属层。在一些示例中，第一绝缘层、第二绝缘层和第三绝缘层可以为无机绝缘层，第四绝缘层可以为有机绝缘层。然而，本实施例对此并不限定。在本示例中，第一源漏金属层即为前述实施例中的第一导电层，第二源漏金属层即为前述实施例中的第二导电层。前述实施例中第一显示区的第一导电层靠近衬底基板一侧的膜层结构可以参照图19所示。
在一些示例性实施方式中，如图19所示，半导体层可以包括：像素电路的多个晶体管的有源层(例如，第一晶体管T1的有源层至第七晶体管T7的有源层)。第一栅金属层可以包括：像素电路的多个晶体管的栅极、以及存储电容的第一极板、第一复位控制线RST1、第二复位控制线RST2、扫描线GL以及发光控制线EML。第二栅金属层可以包括：像素电路的存储电容的第二极板、第一初始信号线INIT1、第二初始信号线INIT2。第一源漏金属层可以包括：数据线DL、第一电源线PL1、以及多个连接电极(例如，第一阳极连接电极)。第一阳极连接电极可以与第二发光控制晶体管T6和第二复位晶体管T7电连接。第二源漏金属层可以包括：遮挡电极222和第二阳极连接电极221。遮挡电极222可以与第一电源线PL1电连接。第二阳极连接电极221可以与第一阳极连接电极电连接。在本示例中，遮挡电极222可以为不规则形状，以配置为覆盖第一节点N1，减小透明导电层对第一节点N1的串扰。
图20为本公开至少一实施例的像素电路的另一俯视示意图。在一些示例性实施方式中，如图20所示，第二导电层的遮挡电极222a可以为规则形状，例如可以为矩形或圆角矩形。相邻像素电路的遮挡电极222a可以为一体结构。遮挡电极222a可以在周边区域与第一电源线PL1电连接。然而，本实施例对此并不限定。例如，遮挡电极可以为圆形或五边形或六边形等规则形状。关于本实施例的像素电路的其余结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例性实施方式中，在低灰阶显示时，由于像素电路连接的透明导电线的长度较长，会导致第四节点N4的电容较大，导致第二发光元件的启亮时间较长，而不同透明导电线与第二导电层的交叠面积存在不同，会影 响透明导电线的线宽，导致不同透明导电线的电容差异，从而产生显示不良。在本示例性实施方式中，通过设置规则形状的遮挡电极，可以使得透明导电层的透明导电线的线宽保持一致，从而减小相邻像素电路的透明导电线的电容差异，从而改善低灰阶显示效果。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底基板。
在一些示例性实施方式中，衬底基板可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如衬底基板可以为柔性基板。
(2)、形成半导体层。
在一些示例性实施方式中，在第一显示区的衬底基板上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层。在一些示例中，半导体薄膜的材料可以为多晶硅。
(3)、形成第一栅金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，依次沉积第一绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层的第一绝缘层，以及设置在第一显示区的第一绝缘层上的第一栅金属层。
在一些示例性实施方式中，形成第一栅金属层图案后，可以利用第一栅金属层作为遮挡，对半导体层进行导体化处理，被第一栅金属层遮挡区域的半导体层形成多个晶体管的沟道区，未被第一栅金属层遮挡区域的半导体层被导体化，即第一晶体管T1的有源层至第七晶体管T7的有源层的第一掺杂区和第二掺杂区均被导体化。
(4)、形成第二栅金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，依次沉积第二绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一栅金属层的第二绝缘层，以及设置在第一显示区的第二绝缘层上的第二栅金属层。
(5)、形成第三绝缘层和第一源漏金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，沉积第三绝缘薄膜，通过图案化工艺形成第三绝缘层。第三绝缘层开设有多个过孔。随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，形成设置在第一显示区的第三绝缘层上的第一源漏金属层。在本示例中，第一源漏金属层即为前述的第一导电层。
(6)、形成第四绝缘层和第二源漏金属层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，涂覆第四绝缘薄膜，通过图案化工艺形成第四绝缘层。随后，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化，形成设置在第一显示区的第四绝缘层上的第二源漏金属层。在一些示例中，第四绝缘层还可以称为第一平坦层。在本示例中，第二源漏金属层即为前述的第二导电层。
(7)、形成第二平坦层和第一透明导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，涂覆第二平坦薄膜，通过图案化工艺形成第二平坦层。随后，沉积第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成设置在第二平坦层上的第一透明导电层。
(8)、形成第三平坦层和第二透明导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，涂覆第三平坦薄膜，通过图案化工艺形成第三平坦层。随后，沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行图案化，形成设置在第三平坦层上的第二透明导电层。
(9)、形成第四平坦层和第三透明导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，涂覆第四平坦薄膜，通过图案化工艺形成第四平坦层。随后，沉积第三透明导电薄膜，通过图案化工艺对第三透明导电薄膜进行图案化，形成设置在第四平坦层上的第三透明导电层。
(10)、形成第五平坦层和阳极层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，涂覆第五平坦薄膜，通过图案化工艺形成第五平坦层。随后，沉积阳极导电薄膜，通过图案化工艺对阳极导电薄膜进行图案化，形成设置在第五平坦层上的阳极层。
在一些示例性实施方式中，在形成前述图案的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)。像素定义层形成有暴露出阳极层的多个像素开口。在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极图案，阴极分别与有机发光层和第二电源线电连接。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例性实施方式中，第一栅金属层、第二栅金属层、第一源漏金属层、第二源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一透明导电层至第三透明导电层可以采用透明导电材料，例如ITO。第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一平坦层至第五平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚 对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，可以设置一个或两个透明导电层。又如，第二导电层可以采用透明导电材料，以避免透明导电层的制备过程中产生反光聚焦作用。然而，本实施例对此并不限定。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开至少一实施例还提供一种显示基板的制备方法，包括：在衬底基板上形成第一导电层；在第一导电层远离衬底基板一侧形成第一平坦层；在第一平坦层远离衬底基板一侧形成第二导电层，第二导电层通过贯穿第一平坦层的至少一个第一过孔与第一导电层电连接；在第二导电层远离衬底基板的一侧形成第二平坦层；在第二平坦层远离衬底基板的一侧形成至少一个透明导电层。透明导电层包括：至少一条第一透明导电线和至少一条辅助走线。第一透明导电线在衬底基板的正投影与至少一个第一过孔在衬底基板的正投影存在交叠。辅助走线的至少部分与第一透明导电线的延伸方向相同，且辅助走线在衬底基板的正投影与第一过孔在衬底基板的正投影相邻。
关于本实施例的显示基板的制备方法可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图21为本公开至少一实施例的显示装置的示意图。如图21所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的显示结构层的出光侧的感光传感器92。感光传感器92在显示基板91上的正投影与第二显示区A2存在交叠。
在一些示例性实施方式中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装 置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (25)

  1. 一种显示基板，包括：
    衬底基板；
    第一导电层，位于所述衬底基板上；
    第一平坦层，位于所述第一导电层远离所述衬底基板的一侧；
    第二导电层，位于所述第一平坦层远离所述衬底基板的一侧，并通过贯穿所述第一平坦层的至少一个第一过孔与所述第一导电层电连接；
    第二平坦层，位于所述第二导电层远离所述衬底基板的一侧；
    至少一个透明导电层，位于所述第二平坦层远离所述衬底基板的一侧；
    所述透明导电层包括：至少一条第一透明导电线和至少一条辅助走线，所述第一透明导电线在所述衬底基板的正投影与所述至少一个第一过孔在所述衬底基板的正投影存在交叠；所述辅助走线的至少部分与所述第一透明导电线的延伸方向相同，且所述辅助走线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影相邻。
  2. 根据权利要求1所述的显示基板，其中，所述辅助走线沿所述延伸方向的长度大于所述第一过孔沿所述延伸方向的孔径。
  3. 根据权利要求1所述的显示基板，其中，在所述延伸方向上，所述辅助走线和所述第一过孔的同侧边缘之间的间距小于5微米。
  4. 根据权利要求1所述的显示基板，其中，所述辅助走线沿所述延伸方向的交叉方向的线宽与所述第一透明导电线沿所述延伸方向的交叉方向的线宽的差值的绝对值小于或等于0.3微米。
  5. 根据权利要求1所述的显示基板，其中，在所述延伸方向的交叉方向上，所述辅助走线与所述第一透明导电线之间具有第一间距，所述第一间距与所述第一透明导电线沿所述延伸方向的交叉方向的线宽的差值的绝对值小于或等于0.35微米。
  6. 根据权利要求1所述的显示基板，其中，所述辅助走线沿所述延伸方向的长度为13.5微米至16.5微米；所述辅助走线沿所述延伸方向的交叉方向 的线宽为1.9微米至2.4微米；沿所述延伸方向的交叉方向上，所述辅助走线与所述第一透明导电线之间的第一间距为2.1微米至2.6微米。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，所述辅助走线在所述延伸方向的端部在所述衬底基板的正投影为圆弧形状。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述至少一个透明导电层包括：第一透明导电层，所述第一透明导电层还包括：至少一个第三阳极连接电极，所述辅助走线包括第一辅助走线，所述第一辅助走线与所述第三阳极连接电极为一体结构，所述第三阳极连接电极配置为与所述第二导电层的第二阳极连接电极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述至少一个透明导电层还包括：位于所述第一透明导电层远离所述衬底基板一侧的第二透明导电层；所述第二透明导电层包括第二辅助走线和至少一个第四阳极连接电极，所述第二辅助走线与所述第四阳极连接电极为一体结构。
  10. 根据权利要求9所述的显示基板，其中，所述至少一个透明导电层还包括：位于所述第二透明导电层远离所述衬底基板一侧的第三透明导电层；所述第三透明导电层包括第三辅助走线和至少一个第五阳极连接电极，所述第三辅助走线与所述第五阳极连接电极为一体结构。
  11. 根据权利要求1所述的显示基板，其中，所述透明导电层还包括：多条相邻排布的第二透明导电线；
    所述多条第二透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影存在交叠；
    所述多条第二透明导电线包括：两条边缘透明导电线和至少一条非边缘透明导电线；所述至少一条非边缘透明导电线位于所述两条边缘透明导电线的中间；
    所述边缘透明导电线沿延伸方向的交叉方向的线宽大于所述非边缘透明导电线沿所述延伸方向的交叉方向的线宽。
  12. 根据权利要求11所述的显示基板，其中，所述边缘透明导电线沿所述延伸方向的交叉方向的线宽与所述非边缘透明导电线沿所述延伸方向的交 叉方向的线宽之差的绝对值为0.3微米至0.5微米。
  13. 根据权利要求12所述的显示基板，其中，所述边缘透明导电线沿所述延伸方向的交叉方向的线宽为2.0微米至2.5微米，所述非边缘透明导电线沿所述延伸方向的交叉方向的线宽为1.8微米至2.2微米。
  14. 根据权利要求11至13中任一项所述的显示基板，其中，所述透明导电层还包括：至少一条第三透明导电线，所述第三透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影存在交叠，且所述第三透明导电线在所述衬底基板的正投影与其余透明导电线在所述衬底基板的正投影之间的间距大于4微米；
    所述第三透明导电线沿所述延伸方向的交叉方向的线宽大于所述边缘透明导电线沿所述延伸方向的交叉方向的线宽。
  15. 根据权利要求1至14中任一项所述的显示基板，其中，所述透明导电层还包括：至少一条第四透明导电线和至少一条第五透明导电线；
    所述第四透明导电线沿延伸方向的线长大于所述第五透明导电线沿所述延伸方向的线长，所述第四透明导电线沿所述延伸方向的交叉方向的线宽小于所述第五透明导电线沿所述延伸方向的交叉方向的线宽。
  16. 根据权利要求15所述的显示基板，其中，所述第四透明导电线在所述衬底基板的正投影与第一数目的第一过孔在所述衬底基板的正投影存在交叠，所述第五透明导电线在所述衬底基板的正投影与第二数目的第一过孔在所述衬底基板的正投影存在交叠，其中，所述第一数目大于所述第二数目。
  17. 根据权利要求16所述的显示基板，其中，所述第四透明导电线和第五透明导电线中任一透明导电线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影的交叠区域，在与所述透明导电线的延伸方向交叉的方向上的长度，和所述透明导电线沿延伸方向的交叉方向的线宽之比大于或等于0.5。
  18. 根据权利要求15所述的显示基板，其中，所述第四透明导电线在所述衬底基板的正投影与所述第二导电层在所述衬底基板的正投影的交叠面积，大于所述第五透明导电线在所述衬底基板的正投影与所述第二导电层在所述 衬底基板的正投影的交叠面积。
  19. 根据权利要求1所述的显示基板，其中，所述第二导电层的材料为透明导电材料。
  20. 根据权利要求1所述的显示基板，其中，所述第二导电层包括：遮挡电极，所述遮挡电极与第一电源线电连接，所述遮挡电极在所述衬底基板的正投影被配置为覆盖所述显示基板的像素电路的第一节点在所述衬底基板的正投影；所述遮挡电极在所述衬底基板的正投影为规则形状。
  21. 根据权利要求20所述的显示基板，其中，所述遮挡电极在所述衬底基板的正投影为矩形或圆角矩形。
  22. 根据权利要求20所述的显示基板，其中，相邻所述像素电路的遮挡电极为一体结构。
  23. 根据权利要求1至22中任一项所述的显示基板，所述显示基板包括第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
    所述显示基板还包括多个子像素，至少一个子像素包括所述像素电路和发光元件，所述像素电路配置为驱动所述发光元件，所述多个子像素包括至少一个第一子像素和至少一个第二子像素，所述第一子像素的像素电路和发光元件位于所述第一显示区，所述第二子像素的像素电路位于所述第一显示区，所述第二子像素的发光元件位于所述第二显示区，所述第二子像素的像素电路通过所述至少一个透明导电层与所述第二子像素的发光元件电连接。
  24. 一种显示装置，包括如权利要求1至23中任一项所述的显示基板。
  25. 一种显示基板的制备方法，包括：
    在衬底基板上形成第一导电层；
    在所述第一导电层远离所述衬底基板一侧形成第一平坦层；
    在所述第一平坦层远离所述衬底基板一侧形成第二导电层，所述第二导电层通过贯穿所述第一平坦层的至少一个第一过孔与所述第一导电层电连接；
    在所述第二导电层远离所述衬底基板的一侧形成第二平坦层；
    在所述第二平坦层远离所述衬底基板的一侧形成至少一个透明导电层；
    所述透明导电层包括：至少一条第一透明导电线和至少一条辅助走线，所述第一透明导电线在所述衬底基板的正投影与所述至少一个第一过孔在所述衬底基板的正投影存在交叠；所述辅助走线的至少部分与所述第一透明导电线的延伸方向相同，且所述辅助走线在所述衬底基板的正投影与所述第一过孔在所述衬底基板的正投影相邻。
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CN108122944A (zh) * 2016-10-31 2018-06-05 乐金显示有限公司 有机发光显示装置及其制造方法
CN110610980A (zh) * 2019-10-23 2019-12-24 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN112103326A (zh) * 2020-09-23 2020-12-18 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN113823671A (zh) * 2021-11-09 2021-12-21 昆山国显光电有限公司 显示面板和显示装置

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CN108122944A (zh) * 2016-10-31 2018-06-05 乐金显示有限公司 有机发光显示装置及其制造方法
CN110610980A (zh) * 2019-10-23 2019-12-24 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
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