WO2023066104A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023066104A1
WO2023066104A1 PCT/CN2022/124814 CN2022124814W WO2023066104A1 WO 2023066104 A1 WO2023066104 A1 WO 2023066104A1 CN 2022124814 W CN2022124814 W CN 2022124814W WO 2023066104 A1 WO2023066104 A1 WO 2023066104A1
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WIPO (PCT)
Prior art keywords
sub
signal line
display area
line
display
Prior art date
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PCT/CN2022/124814
Other languages
English (en)
French (fr)
Inventor
刘畅畅
方飞
卢红婷
李硕
胡耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22882714.3A priority Critical patent/EP4336480A1/en
Priority to US18/277,086 priority patent/US20240099084A1/en
Priority to CN202280003530.4A priority patent/CN116324950A/zh
Publication of WO2023066104A1 publication Critical patent/WO2023066104A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of first pixel circuits, a plurality of first light emitting elements, and at least one first signal line.
  • the base substrate includes a first display area and a second display area located on at least one side of the first display area.
  • a plurality of first pixel circuits and a plurality of first light emitting elements are located in the first display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light emitting element among the plurality of first light emitting elements, and is configured to drive the at least one first light emitting element to emit light.
  • At least one first signal line is configured to provide a first signal to a plurality of first pixel circuits in a first direction. At least one first signal line includes parallel and electrically connected first sub-signal lines and second sub-signal lines, the first sub-signal line is located in the first display area, and the second sub-signal line is located in the first sub-signal line Two display areas.
  • the first sub-signal line is made of a transparent conductive material
  • the second sub-signal line is made of a metal material
  • the second sub-signal line is located on a side of the first sub-signal line away from the base substrate.
  • the at least one first signal line further includes: a third sub-signal line and a fourth sub-signal line located in the second display area, the third sub-signal line and the first sub-signal line
  • the four sub-signal lines are located in the second display area on opposite sides of the first display area along the first direction. Both ends of the first sub-signal line are respectively electrically connected to the third sub-signal line and the fourth sub-signal line, and both ends of the second sub-signal line are respectively connected to the third sub-signal line and the fourth sub-signal line.
  • the fourth sub-signal lines are electrically connected.
  • At least one end of the first sub-signal line is electrically connected to the third sub-signal line or the fourth sub-signal line through the gate of at least one transistor of the first pixel circuit.
  • the display substrate includes a plurality of first signal lines, the plurality of first signal lines are divided into two groups, and the second sub-signal lines of the first group of first signal lines are located in the In the second display area on one side of the first display area along the second direction, the second sub-signal lines of the second group of first signal lines are located in the second display area on the other side of the first display area along the second direction. In the region, the second direction intersects the first direction.
  • the display substrate further includes: a plurality of second pixel circuits and a plurality of second light-emitting elements located in the second display area, at least one of the plurality of second pixel circuits
  • the two-pixel circuit is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and is configured to drive the at least one second light-emitting element to emit light.
  • the orthographic projection of the second sub-signal line of the at least one first signal line on the base substrate does not overlap with the orthographic projection of the anode of the second light-emitting element on the base substrate.
  • the second pixel circuit at least includes: a driving transistor, a threshold compensation transistor and a storage capacitor.
  • the gate of the driving transistor is electrically connected to the first plate of the storage capacitor and the first pole of the threshold compensation transistor.
  • the orthographic projection of the second sub-signal line of the at least one first signal line on the base substrate is related to the gate of the driving transistor of the second pixel circuit, the first electrode of the threshold compensation transistor and the memory The connection positions of the first plate of the capacitor do not overlap in the orthographic projection of the base substrate.
  • the second sub-signal line includes: a first connection section, a second connection section, a third connection section and a fourth connection section.
  • the second connecting segment is a straight segment extending along the first direction
  • the second connecting segment is electrically connected to the first connecting segment
  • the first connecting segment is configured to at least partially surround a second light emitting element the anode.
  • the third connecting segment is a broken line extending along the second direction
  • the fourth connecting segment is connected to the third connecting segment
  • the fourth connecting segment is a straight line extending along the first direction.
  • the second direction intersects the first direction.
  • the second display area is further provided with a plurality of auxiliary wirings arranged on the same layer as the second sub-signal lines, and the plurality of auxiliary wirings are arranged on the front side of the base substrate.
  • the connection position between the projection and the anode of the second light-emitting element, the gate of the drive transistor of the second pixel circuit, the first pole of the threshold compensation transistor, and the first plate of the storage capacitor is The orthographic projections of the substrate substrates do not overlap.
  • the auxiliary wiring is configured to be electrically connected to the first power line.
  • At least one of the plurality of auxiliary routings includes: a first auxiliary segment and a second auxiliary segment connected to each other, the first auxiliary segment is a straight line extending along the first direction segment, the second auxiliary segment is a broken line extending along a second direction, and the second direction intersects with the first direction.
  • the at least one first signal line includes at least one of the following: a scan line, a first reset control line, and a light emission control line.
  • the display substrate further includes: at least one second signal line configured to provide a second signal to the plurality of first pixel circuits in a second direction.
  • the at least one second signal line includes parallel and electrically connected fifth sub-signal lines and sixth sub-signal lines, the fifth sub-signal line is located in the first display area, and the sixth sub-signal line is located in the The second display area; the first direction intersects with the second direction.
  • the first direction is perpendicular to the second direction.
  • the at least one second signal line further includes: a seventh sub-signal line and an eighth sub-signal line located in the second display area, the seventh sub-signal line and the first sub-signal line
  • the eight sub-signal lines are located in the second display area on opposite sides of the first display area along the second direction. Both ends of the fifth sub-signal line are respectively electrically connected to the seventh sub-signal line and the eighth sub-signal line, and both ends of the sixth sub-signal line are respectively connected to the seventh sub-signal line and the eighth sub-signal line.
  • the eighth sub-signal line is electrically connected.
  • the fifth sub-signal line is disposed in the same layer as the first sub-signal line, and the sixth sub-signal line is located in a different layer from the second sub-signal line.
  • the pixel density of the first display area is less than or equal to the pixel density of the second display area.
  • the light transmittance of the first display area is greater than the light transmittance of the second display area.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit in at least one embodiment of the present disclosure
  • FIG. 3 is a working timing diagram of the pixel circuit provided in FIG. 2;
  • FIG. 4 is a partial schematic diagram of a first signal line of a display substrate according to at least one embodiment of the present disclosure
  • 5 and 6 are schematic diagrams of partial wiring of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 7 is a partial plan view of a display area of at least one embodiment of the present disclosure.
  • Fig. 8 is a partial plan view of area A11 in Fig. 7;
  • Fig. 9 is a partial cross-sectional schematic diagram along the Q-Q' direction in Fig. 8.
  • Fig. 10 is a partial plan view of area A12 in Fig. 7;
  • Fig. 11 is a partial plan view of area A13 in Fig. 7;
  • FIG. 12A is a partial schematic diagram of the first display area after the semiconductor layer is formed in FIG. 8;
  • FIG. 12B is a partial schematic diagram of the second display area after the semiconductor layer is formed in FIG. 10;
  • FIG. 12C is a partial schematic diagram of the display area after the semiconductor layer is formed in FIG. 11;
  • FIG. 13A is a partial schematic diagram of the first display area after the first conductive layer is formed in FIG. 8;
  • FIG. 13B is a partial schematic diagram of the second display area after the first conductive layer is formed in FIG. 10;
  • FIG. 13C is a partial schematic diagram of the display area after forming the first conductive layer in FIG. 11;
  • FIG. 14A is a partial schematic view of the first display area after forming the second conductive layer in FIG. 8;
  • FIG. 14B is a partial schematic diagram of the second display area after forming the second conductive layer in FIG. 10;
  • FIG. 14C is a partial schematic diagram of the display area after forming the second conductive layer in FIG. 11;
  • FIG. 15A is a partial schematic diagram of the first display area after forming the third insulating layer in FIG. 8;
  • FIG. 15B is a partial schematic diagram of the second display area after forming the third insulating layer in FIG. 10;
  • FIG. 15C is a partial schematic diagram of the display area after forming the third insulating layer in FIG. 11;
  • FIG. 16A is a partial schematic diagram of the first display area after forming the third conductive layer in FIG. 8;
  • FIG. 16B is a partial schematic diagram of the second display area after forming the third conductive layer in FIG. 10;
  • FIG. 16C is a partial schematic diagram of the display area after forming the third conductive layer in FIG. 11;
  • FIG. 17A is a partial schematic diagram of the first display area after forming the fourth insulating layer in FIG. 8;
  • FIG. 17B is a partial schematic diagram of the display area after forming the fourth insulating layer in FIG. 11;
  • FIG. 18A is a partial schematic diagram of the first display area after forming a transparent conductive layer in FIG. 8;
  • FIG. 18B is a partial schematic diagram of the display area after the transparent conductive layer is formed in FIG. 11;
  • FIG. 19A is a partial schematic diagram of the first display area after forming the fifth insulating layer in FIG. 8;
  • FIG. 19B is a partial schematic diagram of the second display area after forming the fifth insulating layer in FIG. 10;
  • FIG. 19C is a partial schematic diagram of the display area after forming the fifth insulating layer in FIG. 11;
  • FIG. 20A is a partial schematic diagram of the first display area after forming the fourth conductive layer in FIG. 8;
  • FIG. 20B is a partial schematic diagram of the second display area after forming the fourth conductive layer in FIG. 10;
  • Figure 21 is a schematic diagram of the anode layer and the fourth conductive layer in Figure 10;
  • Fig. 22 is a schematic diagram of wiring at the junction of the first display area and the second display area in at least one embodiment of the present disclosure
  • FIG. 23 is a partial schematic diagram of a second signal line of a display substrate according to at least one embodiment of the present disclosure.
  • 24 is a partial schematic diagram of a first signal line and a second signal line of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • the "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body and its incident light flux.
  • a extending along the B direction means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the main body The portion extends along the B direction for a greater length than the secondary portion extends along the other directions.
  • a extends along the direction of B all means "the main part of A extends along the direction of B".
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of first pixel circuits, a plurality of first light emitting elements, and at least one first signal line.
  • the base substrate includes a first display area and a second display area located on at least one side of the first display area.
  • a plurality of first pixel circuits and a plurality of first light emitting elements are located in the first display area.
  • the at least one first pixel circuit is electrically connected to the at least one first light emitting element and is configured to drive the at least one first light emitting element to emit light.
  • the at least one first signal line is configured to provide a first signal to the plurality of first pixel circuits in a first direction.
  • the at least one first signal line includes a first sub-signal line and a second sub-signal line that are parallel and electrically connected. At least part of the first sub-signal line is located in the first display area, and the second sub-signal line is located in the second display area.
  • parallel connection refers to a connection mode in which at least two elements of the same type or different types are connected in parallel between two points of the circuit.
  • the first sub-signal line may have a first end and a second end
  • the second sub-signal line may have a first end and a second end
  • the parallel connection of the first sub-signal line and the second sub-signal line means that the first sub-signal line
  • the first end of a sub-signal line is electrically connected to the first end of the second sub-signal line
  • the second end of the first sub-signal line is electrically connected to the second end of the second sub-signal line
  • the first sub-signal line and the second sub-signal line are electrically connected to each other.
  • the two sub-signal lines are connected in parallel to the transmission circuit of the first signal.
  • the display substrate provided in this embodiment can improve the influence of the impedance of the first signal line on the first display area by arranging the first signal line to transmit the first signal to the first display area in a parallel routing manner, thereby improving the display substrate. Refresh rate and uniform display effect.
  • the first sub-signal line may be made of a transparent conductive material, such as indium tin oxide (ITO), and the second sub-signal line may be made of a metal material.
  • the first sub-signal line is made of transparent conductive material, which can ensure the light transmittance of the first display area. Since the resistance of the transparent conductive material is greater than that of the metal material, in this example, the second sub-signal line of the metal material is connected in parallel with the first sub-signal line of the transparent conductive material, which can improve the resistance of the first sub-signal line. Excessive display defects in the second display area around the first display area can improve the refresh rate of the display substrate and uniform display effect.
  • ITO indium tin oxide
  • the second sub-signal line may be located on a side of the first sub-signal line away from the base substrate. However, this embodiment does not limit it. In some other examples, the second sub-signal line may be located on a side of the first sub-signal line close to the substrate.
  • the display substrate may further include: a plurality of second pixel circuits and a plurality of second light emitting elements located in the second display area. At least one second pixel circuit in the plurality of second pixel circuits is electrically connected to at least one second light emitting element in the plurality of second light emitting elements, and is configured to drive the at least one second light emitting element to emit light.
  • the orthographic projection of the second sub-signal line of the at least one first signal line on the base substrate does not overlap with the orthographic projection of the anode of the second light-emitting element on the base substrate.
  • the flatness of the second light-emitting element can be ensured, thereby ensuring the display effect of the second light-emitting element.
  • the second pixel circuit may at least include: a driving transistor, a threshold compensation transistor and a storage capacitor.
  • the gate of the drive transistor is electrically connected to the first plate of the storage capacitor and the first pole of the threshold compensation transistor.
  • the connection position of the second sub-signal line of the at least one first signal line on the base substrate and the gate of the driving transistor of the second pixel circuit, the first pole of the threshold compensation transistor and the first plate of the storage capacitor are at The orthographic projections of the substrate substrates do not overlap.
  • connection point of the gate of the drive transistor of the second pixel circuit, the first electrode of the threshold compensation transistor, and the first plate of the storage capacitor is the first node, and by setting the second sub-signal line of the first signal line Avoiding the first node can reduce the crosstalk of the first signal transmitted by the first signal line to the first node.
  • the second display area may further include: a plurality of auxiliary wirings arranged on the same layer as the second sub-signal lines.
  • the orthographic projections of the plurality of auxiliary wirings on the base substrate may not overlap with the orthographic projections of the anode of the second light-emitting element on the base substrate, and may also be connected to the gate of the driving transistor of the second pixel circuit and the first gate of the threshold compensation transistor.
  • the connection positions of one pole and the first pole plate of the storage capacitor do not overlap in the orthographic projection of the base substrate.
  • the auxiliary wiring can ensure the uniformity of wiring in the display area , and can ensure the display effect of the second light-emitting element, and reduce the crosstalk to the first node.
  • the auxiliary wiring may be configured to be electrically connected to the first power line. In this way, the display uniformity of the display substrate can be improved.
  • the display substrate may further include: at least one second signal line configured to provide a second signal to the plurality of first pixel circuits in a second direction.
  • the at least one second signal line may include parallel and electrically connected fifth and sixth sub-signal lines, the fifth sub-signal line may be located in the first display area, and the sixth sub-signal line may be located in the second display area.
  • the first direction intersects the second direction.
  • the first direction may be perpendicular to the second direction.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2 located on at least one side of the first display area A1.
  • the second display area A2 may surround the first display area A1.
  • the first display area A1 may be located in the middle of the top of the display area AA.
  • this embodiment does not limit it.
  • the first display area A1 may be located in other positions such as the upper left corner or the upper right corner of the display area AA.
  • the display area AA may be a rectangle, such as a rectangle with rounded corners.
  • the first display area A1 may be circular or elliptical. However, this embodiment does not limit it.
  • the first display area A1 may be in other shapes such as rectangle, pentagon, or hexagon.
  • the first display area A1 may be a light-transmitting display area, and may also be called an under-display camera (FDC, Full Display With Camera) area.
  • the second display area A2 may be a non-light-transmitting display area, and may also be called a normal display area.
  • the light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2.
  • the orthographic projection of hardware such as a photosensitive sensor (such as a camera, an infrared sensor) on the display substrate may be located in the first display area A1 of the display substrate.
  • the first display area A1 may be circular, and the size of the orthographic projection of the photosensor on the display substrate may be smaller than or equal to the size of the first display area A1.
  • this embodiment does not limit it.
  • the first display area may be rectangular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be smaller than or equal to the size of the inscribed circle of the first display area.
  • the display area AA may at least include a plurality of pixel units arranged regularly, a plurality of first signal lines extending along the first direction X (for example, including: scanning lines, reset control lines, light emission control lines), A plurality of second signal lines (for example including data lines and power lines) extending along the second direction Y.
  • first direction X and the second direction Y may be located in the same plane, and the first direction X and the second direction Y intersect, for example, the first direction X may be perpendicular to the second direction Y.
  • one pixel unit in the display area AA may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively. However, this embodiment does not limit it. In some examples, one pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • At least one sub-pixel may include a pixel circuit and a light emitting element.
  • the pixel circuitry can be configured to drive the connected light emitting elements.
  • the pixel circuit can be configured to provide a driving current to drive the light emitting element to emit light.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may have a 3T1C structure, an 8T1C structure, a 7T1C structure or a 5T1C structure.
  • T in the above circuit structure refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the light-emitting element can be a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diodes), a micro LED (including: any of mini-LED or micro-LED).
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of light emitted by the light emitting element can be determined according to needs.
  • the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the anode of the light emitting element can be electrically connected with the corresponding pixel circuit.
  • this embodiment does not limit it.
  • the shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, Arranged side by side or square.
  • this embodiment does not limit it.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit in this example is described by taking the 7T1C structure as an example.
  • FIG. 3 is a working timing diagram of the pixel circuit provided in FIG. 2 .
  • the pixel circuit of this example may include: six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the drive transistor and the six switch transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor oxide semiconductor
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPS) +Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPS low-temperature polycrystalline oxide
  • the pixel circuit can be connected to the scan line GL, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the initial signal line INIT, the first reset control line RST1 is electrically connected to the second reset control line RST2.
  • the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the scan line GL can be configured to provide the scan signal SCAN to the pixel circuit
  • the data line DL can be configured to provide the data signal DATA to the pixel circuit
  • the light emission control line EML can be configured to provide the light emission control signal EM to the pixel circuit
  • the first reset control line RST1 It may be configured to provide a first reset control signal RESET1 to the pixel circuit
  • the second reset control line RST2 may be configured to provide a second reset signal RESET2 to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row. Wherein, n is a positive integer. However, this embodiment does not limit it.
  • the second reset control signal line RST2 may be input with a second reset control signal RESET2 different from the scan signal SCAN.
  • the first reset control line RST1 may be connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first reset The control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the drive transistor T3 is electrically connected to the light-emitting element EL, and outputs a drive current under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.
  • signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.
  • the gate of the data writing transistor T4 is electrically connected to the scanning line GL
  • the first pole of the data writing transistor T4 is electrically connected to the data line DL
  • the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3 .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL
  • the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3
  • the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3 .
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML
  • the first pole of the first light emission control transistor T5 is electrically connected to the first power line PL1
  • the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML
  • the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3
  • the second pole of the second light emission control transistor T6 is connected to the light emission control line EML.
  • the anode of the element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL, and is configured to reset the gate of the light emitting element EL. Anode resets.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected to the initial signal line INIT, and the second pole of the first reset transistor T1 is connected to the gate of the driving transistor T3. electrical connection.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected to the initial signal line INIT, and the second pole of the second reset transistor T7 is connected to the anode of the light emitting element EL. electrical connection.
  • the first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T
  • the multiple transistors included in the pixel circuit shown in FIG. 2 are all P-type transistors as an example for description.
  • the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN.
  • the working process of the pixel circuit may include: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal to turn on the first reset transistor T1, and the initial signal Vinit provided by the initial signal line INIT is provided to the first node N1.
  • N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off.
  • the light emitting element EL does not emit light.
  • the second stage S2 is called a data writing stage or a threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N2 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the drive transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the initial signal Vinit provided by the initial signal line INIT is provided to the anode of the light-emitting element EL, and the anode of the light-emitting element EL is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure light emission.
  • the element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage S3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [(VDD-Vdata)] 2 ;
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • the first display area A1 of the display substrate may be provided with a plurality of first light emitting elements 12 and a plurality of first pixel circuits 11 .
  • At least one first pixel circuit 11 is electrically connected to at least one first light emitting element 12 and is configured to drive the at least one first light emitting element 12 to emit light.
  • Orthographic projections of the first pixel circuit 11 and the electrically connected first light-emitting element 12 on the base substrate may at least partially overlap.
  • the second display area A2 may be provided with a plurality of second light emitting elements 14 and a plurality of second pixel circuits 13 .
  • At least one second pixel circuit 13 is electrically connected to at least one second light emitting element 14 and configured to drive at least one second light emitting element 14 to emit light.
  • Orthographic projections of the second pixel circuit 13 and the electrically connected second light-emitting element 14 on the base substrate may at least partially overlap.
  • multiple first pixel circuits 11 and multiple first light emitting elements 12 may be electrically connected in one-to-one correspondence
  • multiple second pixel circuits 13 and multiple second light emitting elements 14 may be electrically connected in one-to-one correspondence.
  • this embodiment does not limit it.
  • the first pixel circuit 11 and the first light emitting element 12 may have a one-to-many relationship.
  • the second pixel circuit 13 and the second light emitting element 14 may have a one-to-many relationship.
  • FIG. 4 is a partial schematic diagram of a first signal line of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes a plurality of first signal lines L1.
  • the first signal line L1 can provide the first signal to the first pixel circuit in the first display area A1 in the first direction X.
  • the first signal line L1 may include at least one of the following: a scan line, a first reset control line, and a light emission control line.
  • the first signal line L1 may include: a first sub-signal line L11 , a second sub-signal line L12 , a third sub-signal line L13 and a fourth sub-signal line L14 .
  • Both the third sub-signal line L13 and the fourth sub-signal line L14 may extend along the first direction X, and are located in the second display area on opposite sides of the first display area A1 along the first direction X.
  • the first sub-signal line L11 may be located in the first display area A1 and extend along the first direction X.
  • Both ends of the first sub-signal line L11 may be electrically connected to the third sub-signal line L13 and the fourth sub-signal line L14, respectively.
  • the second sub-signal line L12 may be located in the second display area.
  • the second sub-signal line L12 may bypass the first display area A1, and both ends of the second sub-signal line L12 may be electrically connected to the third sub-signal line L13 and the fourth sub-signal line L14, respectively.
  • the second sub-signal line L12 may first extend along the second direction Y, then extend along the first direction X, and then extend along the second direction Y.
  • the first sub-signal line L11 and the second sub-signal line L12 of the first signal line L1 are electrically connected in parallel, and are connected in series with the third sub-signal line L13 and the fourth sub-signal line L14.
  • the plurality of first signal lines L1 may be divided into two groups.
  • the first group of first signal lines and the second group of first signal lines may be approximately symmetrical with respect to the first center line O1 of the first display area A1 along the second direction Y.
  • the number of first signal lines in the first group of first signal lines may be approximately the same as the number of first signal lines in the second group of first signal lines.
  • the second sub-signal line L12 of the first signal line L1 in the first group of first signal lines may be located in the second display area on the side of the first display area A1 along the second direction Y, and in the second group of first signal lines
  • the second sub-signal line L12 of the first signal line L1 may be located in the second display area on the other side of the first display area A1 along the second direction Y.
  • the second sub-signal line L12 of the first group of first signal lines can bypass the first display area A1 from the upper side of the first display area A1, and the second sub-signal line L12 of the second group of first signal lines can be routed from the upper side of the first display area A1.
  • the lower side of the first display area A1 bypasses the first display area A1. In this way, it is possible to avoid the accumulation of wires and affect the display effect.
  • the second sub-signal line L12 of the first signal line L1 close to the edge of the first display area A1 in the second direction Y may be located close to the first display area A1 along the second direction.
  • the second sub-signal line L12 of the first signal line L1 of the first central line O1 of Y is close to one side of the first display area A1.
  • the length of the second sub-signal line L12 of the first signal line L1 along the second direction Y close to the first middle line O1 of the first display area A1 along the second direction Y may be greater than the length of the second sub-signal line L12 of the first signal line L1 close to the edge of the first display area A1.
  • the length of the second sub-signal line L12 of the first signal line L1 along the second direction Y In this way, overlapping of wires can be reduced, which is beneficial to reasonably arrange the second sub-signal lines L12.
  • the first signal can be transmitted in the first display area A1 through the first sub-signal line L11 , and can also be transmitted in the second display area through the second sub-signal line L12 .
  • the transmission load of the first signal in the first display area A1 can be reduced by setting the first sub-signal line L11 and the second sub-signal line L12 that are electrically connected in parallel to transmit the first signal, thereby improving the first display area
  • the horizontal display defect exists in the second display area on the left and right sides of A1.
  • FIG. 5 and 6 are schematic diagrams of partial wiring of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 7 is a partial plan view of a display area according to at least one embodiment of the present disclosure.
  • FIG. 5 illustrates the second sub-signal line of one first signal line
  • FIG. 6 illustrates the second sub-signal lines of three first signal lines.
  • Figure 7 shows the anodes 120 of the plurality of first light emitting elements 12 in the first display area A1, the anodes 140 of the plurality of second light emitting elements 14 in the second display area A2, and part of the second sub-signals in the second display area A2 Line L12 and auxiliary line L3.
  • the pixel density (PPI) of the first display area A1 may be smaller than the pixel density of the second display area A2 .
  • this embodiment does not limit it.
  • the pixel density of the first display area may be equal to the pixel density of the second display area.
  • the orthographic projection of the second sub-signal line L12 of the first signal line on the base substrate and the orthographic projection of the anode 140 of the second light emitting element 14 on the base substrate may be different. overlap.
  • the second sub-signal line L12 bypasses the anode 140 of the second light emitting element 14 to ensure the flatness of the second light emitting element 14 , thereby ensuring the light emitting effect of the second light emitting element 14 .
  • the second sub-signal line L12 of the first signal line may include: a first connection segment L121, a second connection segment L122, a third connection segment L123 and a fourth connection segment L124.
  • the first connecting segment L121 may be an unsealed shape formed by connecting multiple straight segments, and the anode 140 of a second light emitting element 14 may be located in the area surrounded by the first connecting segment L121.
  • the first connecting section L121 can partially surround the anode 140 of a second light emitting element 14 .
  • the second connecting segment L122 may be a straight segment extending along the first direction X. Referring to FIG.
  • the second connection section L122 connects adjacent first connection sections L121. As shown in FIG.
  • the first connection section L121 and the second connection section L122 can be connected at intervals, so that the second sub-signal line L12 can bypass the anodes 140 of the plurality of second light emitting elements 14 along the first direction X.
  • the third connecting segment L123 may be a broken line extending along the second direction Y
  • the fourth connecting segment L124 may be a straight line extending along the first direction X.
  • a plurality of fourth connection sections L124 may be connected to one side of the third connection section L123. Only one end of the fourth connection section L124 is connected to the third connection section L123.
  • the fourth connection segment L124 may be located between the anodes 140 of adjacent second light emitting elements 14 arranged along the second direction Y.
  • the second sub-signal line L12 can bypass the anode 140 of the second light-emitting element 14 along the second direction Y through the third connection section L123, and the wiring environment around the anode 140 of the second light-emitting element 14 can be improved through the fourth connection section L124. unanimous. However, this embodiment does not limit it.
  • the first connecting segment L121 may be formed by connecting curved segments
  • the second connecting segment L122, the third connecting segment L123 and the fourth connecting segment L124 may be curved segments.
  • portions of the second sub-signal lines L12 of the plurality of first signal lines extending along the first direction X may be adjacently arranged in the second direction Y.
  • the portions of the second sub-signal lines L12 of the plurality of first signal lines extending along the second direction Y may be adjacent to or separated from the plurality of auxiliary traces L3.
  • the auxiliary routing L3 may include: a first auxiliary segment L31 and a second auxiliary segment L32 .
  • the first auxiliary segment L31 may be a straight segment extending along the first direction X.
  • the second auxiliary segment L32 may be a broken line extending along the second direction Y. Referring to FIG.
  • the first auxiliary section L31 and the second auxiliary section L32 are connected to each other.
  • a plurality of first auxiliary segments L31 may be connected at the same side of the second auxiliary segment L32.
  • the orthographic projection of the auxiliary wiring L3 on the substrate may not overlap with the orthographic projection of the anode 140 of the second light emitting element 14 on the substrate.
  • the shape of the auxiliary wiring L3 may be similar to that of the second sub-signal line L12. In this example, by setting the auxiliary wiring L3, the uniform arrangement of the wiring in the display area of the display substrate can be ensured.
  • the anode 140 of at least one second light emitting element 14 in the second display area A2 may be surrounded or partially surrounded by the second sub-signal line L12 and the auxiliary wiring L3 .
  • Both the second sub-signal line L12 and the auxiliary wiring L3 are routed around the anode 140 of the second light-emitting element 14, which can ensure the flatness of the second light-emitting element 14 and ensure the uniformity of the wiring environment around the second light-emitting element 14, Avoid affecting the light emitting effect of the second light emitting element 14 .
  • FIG. 8 is a partial plan view of the area A11 in FIG. 7 .
  • Fig. 9 is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 8 .
  • FIG. 10 is a partial plan view of the area A12 in FIG. 7 .
  • FIG. 11 is a partial plan view of the area A13 in FIG. 7 .
  • Figure 8 illustrates six first pixel circuits and six first light-emitting elements;
  • Figure 10 illustrates eight second pixel circuits and eight second light-emitting elements;
  • Figure 11 illustrates the first display area A1 and A first pixel circuit and a second pixel circuit are adjacent to the junction of the second display area A2.
  • the first display region in a plane parallel to the display substrate, may include a plurality of display island regions A1a spaced apart from each other and a light-transmitting region between adjacent display island regions A1a A1b.
  • Each display island area A1a can be configured to display images, and each light-transmitting area A1b can be configured to provide a space for light transmission.
  • the shapes of the multiple display islands A1a may be approximately the same, and the display islands A1a may have smooth edges, thereby reducing the light diffraction effect and improving the shooting effect.
  • the display islands A1a in the first display area may be independent of each other, the light-transmitting areas A1b in the first display area may communicate with each other, and the light-transmitting areas A1b may surround the display islands A1a.
  • Each display island area A1a may include one sub-pixel. The orthographic projection of the first light-emitting element and the electrically connected first pixel circuit on the base substrate overlaps.
  • a pixel unit in the second display area may include: a sub-pixel P1 that emits light of the first color, a sub-pixel that emits light of the second color P2, a sub-pixel P3 that emits light of the third color, and a sub-pixel P4 that emits light of the fourth color.
  • the orthographic projection of the second light-emitting element and the electrically connected second pixel circuit on the base substrate overlaps.
  • a plurality of second pixel circuits in the second display area may be arranged in an array, and a plurality of second light emitting elements may be arranged in a Pentile structure.
  • the second light-emitting elements that emit light of the first color and the second light-emitting elements that emit light of the second color may be alternately arranged along the first direction X and the second direction Y, and the second light-emitting elements that emit light of the third color and the second light that emit light
  • the second light-emitting elements of the fourth color light can be arranged alternately along the first direction X and the second direction Y;
  • the row where the second light-emitting element of the four-color light is located is dislocated, and the column where the second light-emitting element that emits the first color light and the second color light is located is the same as the column where the second light-emitting element that emits the third color light and the fourth color light is located.
  • the first color light may be red light
  • the second color light may be blue light
  • the third color light and fourth color light may be green light.
  • the display substrate may include: a base substrate 100 , a circuit structure layer disposed on the base substrate 100 , a light emitting structure layer, and a package structure layer 400 .
  • the circuit structure layer may include: a semiconductor layer 201, a first conductive layer (or called a first gate metal layer) 202, a second conductive layer (or called a second gate metal layer) 203 sequentially disposed on the substrate 100 , a third conductive layer (or called a first source-drain metal layer) 204 , a transparent conductive layer 205 , and a fourth conductive layer (or called a second source-drain metal layer) 206 .
  • a first insulating layer (or called a first gate insulating layer) 101 is arranged between the semiconductor layer 201 and the first conductive layer 202, and a second insulating layer (or called a gate insulating layer) 101 is arranged between the first conductive layer 202 and the second conductive layer 203.
  • the second gate insulating layer) 102 a third insulating layer (or interlayer insulating layer) 103 is arranged between the second conductive layer 203 and the third conductive layer 204, and a third insulating layer (or called an interlayer insulating layer) 103 is arranged between the third conductive layer 204 and the transparent conductive layer 205
  • the fifth insulating layer 105 is disposed between the fourth insulating layer 104 , the transparent conductive layer 205 and the fourth conductive layer 206 .
  • the sixth insulating layer 106 is provided on the side of the fourth conductive layer 206 away from the base substrate 100 .
  • the first insulating layer 101 to the third insulating layer 103 may be inorganic insulating layers, and the fourth insulating layer 104 to sixth insulating layer 106 may be organic insulating layers.
  • this embodiment does not limit it.
  • the light emitting structure layer may at least include: an anode layer 301 , a pixel definition layer 304 , an organic light emitting layer 302 and a cathode layer 303 sequentially disposed on the circuit structure layer.
  • the anode layer 301 can be electrically connected to the pixel circuit (such as the first pixel circuit or the second pixel circuit) of the circuit structure layer
  • the organic light emitting layer 302 can be connected to the anode layer 301
  • the cathode layer 303 can be connected to the organic light emitting layer 302
  • the organic light emitting layer 302 can be connected to the organic light emitting layer 302.
  • the layer 302 can emit light of a corresponding color under the drive of the anode layer 301 and the cathode layer 303 .
  • the encapsulation structure layer 400 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. material, the second encapsulation layer can be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.
  • the structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate.
  • the "patterning process" mentioned in the embodiments of the present disclosure refers to metal materials, inorganic materials or transparent conductive materials, including coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments, and for organic materials , including coating organic materials, mask exposure and development and other treatments.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • Thin film refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer in this specification means that A and B are formed simultaneously through the same patterning process, or the distances between the surfaces of A and B near the substrate and the substrate are basically the same, or A and B are formed at the same time.
  • the surface of B near the substrate is in direct contact with the same film layer.
  • the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the manufacturing process of the display substrate may include the following operations.
  • the substrate substrate can be a rigid substrate or a flexible substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz;
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be Using materials such as polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, the material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., are used to improve the water and oxygen resistance of the substrate.
  • PI polyimide
  • PET polyethylene terephthalate
  • SiNx silicon nitride
  • SiOx silicon oxide
  • a semiconductor thin film is deposited on the base substrate, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer disposed on the base substrate.
  • materials for the semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene.
  • FIG. 12A is a partial schematic diagram of the first display area after the semiconductor layer is formed in FIG. 8 .
  • FIG. 12B is a partial schematic diagram of the second display region after the semiconductor layer is formed in FIG. 10 .
  • FIG. 12C is a partial schematic diagram of the display area after the semiconductor layer is formed in FIG. 11 .
  • the semiconductor layer of the first display region may at least include: an active layer of a plurality of transistors of the first pixel circuit (for example, including: a first reset transistor of the first pixel circuit
  • an active layer of a plurality of transistors of the first pixel circuit
  • Each active layer may include: a channel region, and first and second regions located on opposite sides of the channel region.
  • the active layers of the seven transistors of each first pixel circuit may have an integrated structure. Active layers of transistors of different first pixel circuits are independent from each other.
  • the fourth active layer 240, the fifth active layer 250, the sixth active layer 260, and the seventh active layer 270 of the first pixel circuit may be roughly I-shaped, and the first active layer 210 and the third active layer
  • the active layer 230 may be approximately n-shaped, and the second active layer 220 may be approximately L-shaped.
  • the semiconductor layer of the second display region may at least include: an active layer of a plurality of transistors of the second pixel circuit (for example, including: a first reset transistor of the second pixel circuit
  • an active layer of a plurality of transistors of the second pixel circuit for example, including: a first reset transistor of the second pixel circuit
  • the active layers of the seven transistors of each second pixel circuit may have an integrated structure, and the active layers of the transistors of the adjacent second pixel circuits along the second direction Y may have an integrated structure.
  • the fourth active layer 340 of the second pixel circuit can be approximately I-shaped
  • the first active layer 310 and the third active layer 330 can be approximately N-shaped
  • the second active layer 320 the fifth active layer
  • the active layer 350, the sixth active layer 360, and the seventh active layer 370 may be substantially L-shaped.
  • a first insulating film and a first conductive film are sequentially deposited on the base substrate forming the foregoing structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and be disposed on the first The first conductive layer on the insulating layer.
  • FIG. 13A is a partial schematic diagram of the first display area after forming the first conductive layer in FIG. 8 .
  • FIG. 13B is a partial schematic diagram of the second display area after the formation of the first conductive layer in FIG. 10 .
  • FIG. 13C is a partial schematic diagram of the display area after the first conductive layer is formed in FIG. 11 .
  • the first conductive layer of the first display region may at least include: gates of a plurality of transistors of the first pixel circuit (for example, include: a first reset transistor of the first pixel circuit
  • a first reset transistor of the first pixel circuit The gate 211 of the transistor 21, the gate 221 of the threshold compensation transistor 22, the gate 231 of the drive transistor 23, the gate 241 of the data writing transistor 24, the gate 251 of the first light emission control transistor 25, the second light emission control transistor 26, the gate 271 of the second reset transistor 27), the first plate 281 of the storage capacitor 28 of the first pixel circuit, and the first metal connection line 283 and the second metal connection line 284.
  • the gate 221 of the threshold compensation transistor 22 , the gate 241 of the data writing transistor 24 and the gate 271 of the second reset transistor 27 may be of an integral structure.
  • the gate 231 of the driving transistor and the first plate 281 of the storage capacitor 28 may be in one body.
  • the gate 251 of the first light emission control transistor 25 and the gate 261 of the second light emission control transistor 26 may have an integrated structure.
  • the gate 211 of the first reset transistor 21 of the first pixel circuit and the first metal connection line 283 may be of an integral structure.
  • the gates 211 of the first reset transistors 21 of the adjacent first pixel circuits near the junction of the first display area and the second display area may be electrically connected through the first metal connection line 283 .
  • the gate 261 of the second light emission control transistor 26 of the first pixel circuit and the second metal connection line 284 may be integrally structured.
  • the gate 251 of the first light emission control transistor 25 and the gate 261 of the second light emission control transistor 26 of the adjacent first pixel circuit near the junction of the first display area and the second display area can pass through the second metal connection line 284 electrical connections.
  • the first conductive layer of the second display region may at least include: gates of a plurality of transistors of the second pixel circuit (for example, include: a first reset transistor of the second pixel circuit
  • the gate of the first reset transistor 31 of the second pixel circuit in this row, the gate of the second reset transistor 37 of the second pixel circuit in the previous row, and the first reset control line RST1(n) may have an integrated structure.
  • the gate of the threshold compensation transistor 32 , the gate of the data writing transistor 34 and the scan line GL(n) of the second pixel circuit in this row may be of an integrated structure.
  • the gate of the driving transistor 33 of the second pixel circuit and the first plate 381 of the storage capacitor 38 may be of an integral structure.
  • the gate of the first light emission control transistor 35 , the gate of the second light emission control transistor 36 and the light emission control line EML(n) of the second pixel circuit in this row may have an integral structure.
  • the first reset control line RST1(n) is electrically connected to the gate 211 of the first reset transistor 21 of the first pixel circuit.
  • the connection for example, may be of one-piece construction.
  • the light emission control line EML(n) is electrically connected to the gate 251 of the first light emission control transistor 25 of the first pixel circuit, for example, may have an integral structure.
  • the third sub-signal line L13 of the scan line GL(n) is electrically connected to the gate 241 of the data writing transistor 24 of the first pixel circuit, for example, may have an integrated structure.
  • the third sub-signal line L13 of the scanning line GL(n) may also have a first transfer terminal 501 so as to be electrically connected to the second sub-signal line L12 through the first transfer terminal 501 .
  • the first transfer terminal 501 may be located between the first plate 281 of the storage capacitor 28 of the first pixel circuit and the first plate 381 of the storage capacitor 38 of the second pixel circuit.
  • the semiconductor layer can be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel regions of multiple transistors, and the semiconductor layer not covered by the first conductive layer
  • the semiconductor layer in the shielding region of the first conductive layer is conductorized, that is, both the first region and the second region of the active layer of the transistor are conductorized.
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate forming the aforementioned structure, and the second conductive film is patterned through a patterning process to form a second insulating layer and be disposed on the second A second conductive layer on top of the insulating layer.
  • FIG. 14A is a partial schematic diagram of the first display area after forming the second conductive layer in FIG. 8 .
  • FIG. 14B is a partial schematic diagram of the second display area after forming the second conductive layer in FIG. 10 .
  • FIG. 14C is a partial schematic diagram of the display area after forming the second conductive layer in FIG. 11 .
  • the second conductive layer of the first display area may at least include: the second plate 282 of the storage capacitor 28 of the first pixel circuit, the third metal connection line 285, the second Four metal connecting wires 286 .
  • the third metal connection line 285 is configured to transmit an initial signal in the display island (the display island A1a shown in FIG. 8 ).
  • the fourth metal connection line 286 is configured to transmit initial signals between the display islands.
  • the third metal connection lines 285 in adjacent display island regions near the junction of the first display area and the second display area may be electrically connected through the fourth metal connection line 286 .
  • the third metal connection line 285 and the fourth metal connection line 286 may be of an integral structure.
  • the second conductive layer of the second display area may at least include: the second plate 382 of the storage capacitor 38 of the second pixel circuit, the shielding electrode 383, the initial signal line INIT .
  • Orthographic projections of the second plate 382 of the storage capacitor 38 of the second pixel circuit and the first plate 381 on the base substrate may overlap.
  • the orthographic projection of the shielding electrode 383 on the base substrate may overlap with the orthographic projection of the active layer of the threshold compensation transistor 32 of the second pixel circuit on the base substrate.
  • the shielding electrode 383 is configured to protect the threshold compensation transistor and shield the threshold compensation transistor from being interfered by other signals.
  • the initial signal line INIT may extend along the first direction X, and extend to the first display area adjacent to the fourth metal connection line 286 in the second direction Y.
  • a third insulating film is deposited on the base substrate with the aforementioned pattern, and the third insulating film is patterned through a patterning process to form a third insulating layer.
  • FIG. 15A is a partial schematic diagram of the first display area after forming the third insulating layer in FIG. 8 .
  • FIG. 15B is a partial schematic diagram of the second display region after forming the third insulating layer in FIG. 10 .
  • FIG. 15C is a partial schematic diagram of the display area after forming the third insulating layer in FIG. 11 .
  • the third insulating layer of the display region may be provided with a plurality of via holes, for example, may include: a first type via hole exposing the surface of the semiconductor layer, a first type via hole exposing the first conductive layer The second type via hole on the surface and the third type via hole exposing the surface of the second conductive layer.
  • the first type of vias in the first display area may include first vias V1 to sixth vias V6, and the second type of vias may include: seventh vias V7 to the thirteenth via hole V13, the third type of via hole may include: the fourteenth via hole V14 to the seventeenth via hole V17.
  • the first type of vias in the second display area may include: the twentieth via V20 to the twenty-fifth via V25, and the second type of vias may include: The twenty-sixth via hole V26 and the eighteenth via hole V18, the third type of via hole may include: the twenty-seventh via hole V27 to the twenty-ninth via hole V29.
  • a third conductive film is deposited on the aforementioned patterned base substrate, and the third conductive film is patterned by a patterning process to form a third conductive layer on the third insulating layer.
  • FIG. 16A is a partial schematic diagram of the first display area after forming the third conductive layer in FIG. 8 .
  • FIG. 16B is a partial schematic diagram of the second display area after the formation of the third conductive layer in FIG. 10 .
  • FIG. 16C is a partial schematic diagram of the display area after forming the third conductive layer in FIG. 11 .
  • the third conductive layer of the first display area may at least include: a plurality of pixel electrodes (for example, including the first pixel electrode 291 to the fifth pixel electrode 295 ), a plurality of transition electrodes connecting electrodes (for example, including the first via electrode 401 to the tenth via electrode 410 ), and the sixth metal connecting wire 288 .
  • the first pixel electrode 291 may be electrically connected to the first region of the first active layer 210 of the first reset transistor of the first pixel circuit through the first via hole V1, It may also be electrically connected to the third metal connection line 285 through the fifteenth via hole V15.
  • the second pixel electrode 292 may be electrically connected to the first region of the second active layer 220 of the threshold compensation transistor through the second via hole V2, and may also be electrically connected to the gate 231 of the driving transistor through the tenth via hole V10.
  • the third pixel electrode 293 can be electrically connected to the first region of the fifth active layer 250 of the first light emission control transistor through the fourth via hole V4, and can also be connected to the second plate of the storage capacitor 28 through the sixteenth via hole V16. 282 electrical connections.
  • the fourth pixel electrode 294 can be electrically connected to the second region of the sixth active layer 260 of the second light emission control transistor through the fifth via hole V5, and can also be connected to the seventh active layer of the second reset transistor through the sixth via hole V6.
  • the second region of layer 270 is electrically connected.
  • the fifth pixel electrode 295 may be electrically connected to the first region of the fourth active layer 240 of the data writing transistor through the third via hole V3.
  • the first transfer electrode 401 may be electrically connected to the third metal connection line 285 through the fourteenth via hole V14 .
  • the second transfer electrode 402 may be electrically connected to one end of the gate 211 of the first reset transistor through the eighth via hole V8.
  • the third transfer electrode 403 may be electrically connected to the other end of the gate 211 of the first reset transistor through the seventh via hole V7.
  • the fourth transfer electrode 404 may be electrically connected to the gate 241 of the data writing transistor through the ninth via hole V9.
  • the fifth transfer electrode 405 may be electrically connected to the gate 271 of the second reset transistor through the eleventh via hole V11.
  • the sixth transfer electrode 406 may be electrically connected to the gate 251 of the first light emission control transistor through the twelfth via hole V12.
  • the seventh transfer electrode 407 may be electrically connected to the gate 261 of the second light emission control transistor through the thirteenth via hole V13.
  • the ninth transfer electrode 409 may be electrically connected to the initial signal line INIT1 through the seventeenth via hole V17.
  • the tenth via electrode 410 may be electrically connected to one end of the third metal connection line 285 near the boundary of the first display area and the second display area through a fourteenth via hole V14 .
  • the sixth metal connection line 288 is configured to transmit scan signals between display islands.
  • One end of the sixth metal connection line 288 is electrically connected to the gate 271 of the second reset transistor 27 of the first pixel circuit.
  • the gate of the second reset transistor and the gate of the data writing transistor in the adjacent display island region near the junction of the first display region and the second display region may be electrically connected through the sixth metal connection line 288 .
  • the third conductive layer of the second display area may at least include: a data line DL, a first power line PL1, a plurality of pixel electrodes (such as including a sixth pixel electrode 296, the seventh pixel electrode 297 and the eighth pixel electrode 298 ), and the fifth metal connection line 287 .
  • the data line DL and the first power line PL1 may both extend in the second direction Y.
  • the data line DL and the first power line PL1 electrically connected to the second pixel circuit of the same column are adjacent in the first direction X.
  • the sixth pixel electrode 296 may be electrically connected to the first region of the first active layer 310 of the first reset transistor of the second pixel circuit through the twenty-first via hole V21. It may also be electrically connected to an initial signal line INIT through the twenty-seventh via hole V27.
  • the sixth pixel electrode 296 can also be electrically connected to the first region of the seventh active layer 370 of the second reset transistor through the twentieth via hole V20, and can also be electrically connected to another initial signal line INIT through the nineteenth via hole V19. connect.
  • the sixth pixel electrode 296 in this example may extend along the second direction Y, so as to realize the transmission of the initial signal along the second direction Y.
  • the sixth pixel electrode 296 and the initial signal line INIT can be connected to form a mesh structure for transmitting the initial signal, thereby ensuring the uniformity of the initial signal.
  • the seventh pixel electrode 297 may be electrically connected to the first region of the second active layer 320 of the threshold compensation transistor of the second pixel circuit through the twenty-second via hole V22 , may also be electrically connected to the gate of the driving transistor 33 through the twenty-sixth via V26.
  • the eighth pixel electrode 298 may be electrically connected to the second region of the sixth active layer 360 of the second light emission control transistor 36 through the twenty-fifth via hole V25.
  • the data line DL may be electrically connected to the first region of the fourth active layer 340 of the data writing transistor 34 through the twenty-third via hole V23 .
  • the first power line PL1 can be electrically connected to the shielding electrode 383 through the twenty-eighth via hole V28, and can also be electrically connected to the second plate 382 of the storage capacitor 38 through two twenty-ninth via holes V29 arranged vertically. It may also be electrically connected to the first region of the fifth active layer 350 of the first light emission control transistor 35 through the twenty-fourth via hole V24.
  • the fifth metal connection line 287 may be electrically connected to the first transfer terminal 501 of the third sub-signal line L13 of the scan line GL(n) through the eighteenth via hole V18 .
  • the fifth metal connection line 287 may extend along the second direction Y, and be electrically connected to the first reset control line RST1(n+1) electrically connected to the next row of pixel circuits.
  • a fourth insulating film is coated on the base substrate formed with the foregoing pattern, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer.
  • FIG. 17A is a partial schematic diagram of the first display area after forming the fourth insulating layer in FIG. 8 .
  • FIG. 17B is a partial schematic diagram of the display area after forming the fourth insulating layer in FIG. 11 .
  • the fourth insulating layer of the display region may have a plurality of via holes in the first display region, for example, may include fourth type via holes exposing the surface of the third conductive layer.
  • the fourth type of vias in the first display area may include: a thirty-first via V31 to a forty-second via V42 .
  • a transparent conductive film is deposited on the base substrate on which the foregoing pattern is formed, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer in the first display area.
  • FIG. 18A is a partial schematic diagram of the first display area after the transparent conductive layer is formed in FIG. 8 .
  • FIG. 18B is a partial schematic diagram of the display area after forming the transparent conductive layer in FIG. 11 .
  • the transparent conductive layer of the first display area may at least include: a data connection line 45, a first power transfer line 419, a second power transfer line 420, and a plurality of transfer lines (such as the first transition line 411 to the eighth transition line 418 ) and the first connection electrode 421 .
  • the data connection lines 45 may extend along the second direction Y.
  • the data connection line 45 can be electrically connected to the fifth pixel electrode 295 through the thirty-sixth via hole V36, so as to realize the electrical connection between the data connection line 45 and the first electrode of the data writing transistor 24 of the first pixel circuit.
  • the first power transfer line 419 can extend along the second direction Y, one end of the first power transfer line 419 can be electrically connected to the eighth transfer electrode 408 through the thirty-third via hole V33, and the other end can be connected to another first pixel
  • the third pixel electrode 293 of the circuit is electrically connected.
  • the second power transfer line 420 can extend along the second direction Y, one end of the second power transfer line 420 can be electrically connected to the third pixel electrode 293 through the forty-first via hole V41, and the other end can be connected to another first pixel circuit
  • the eighth via electrode 408 is electrically connected.
  • the first voltage signal can be transmitted along the second direction Y by using the first power transfer line 419 and the second power transfer line 420 .
  • one end of the first transfer wire 411 can be electrically connected to the first transfer electrode 401 in a display island area through the thirty-first via hole V31, and the other end can be extended to another display island.
  • One end of the second transfer line 412 may be electrically connected to the first pixel electrode 291 through the thirty-second via V32, and the other end may extend to another display island region.
  • initial signal transmission can be realized by using the first transfer line 411 , the first transfer electrode 401 , the third metal connection line 285 , the first pixel electrode 291 and the second transfer line 412 .
  • One end of the third transfer line 413 can be electrically connected to the third transfer electrode 403 in one display island area through the thirty-fourth via hole V34 , and the other end can extend to another display island area.
  • One end of the fourth transfer line 414 may be electrically connected to the second transfer electrode 402 through the thirty-fifth via hole V35 , and the other end may extend to another display island.
  • the third transfer electrode 403, the gate 211 of the first reset transistor, the second transfer electrode 402 and the fourth transfer line 414 can implement the first reset control signal. transmission.
  • One end of the fifth transfer wire 415 can be electrically connected to the fourth transfer electrode 404 in one display island area through the thirty-seventh via hole V37, and the other end can extend to another display island area.
  • One end of the sixth transfer line 416 can be electrically connected to the fifth transfer electrode 405 through the thirty-ninth via hole V39 , and the other end can extend to another display island.
  • the connecting electrode 405 and the sixth transfer wire 416 can realize the transmission of scanning signals.
  • One end of the seventh transfer line 417 can be electrically connected to the sixth transfer electrode 406 in one display island area through the thirty-eighth via hole V38 , and the other end can extend to another display island area.
  • One end of the eighth transfer line 418 may be electrically connected to the seventh transfer electrode 407 through the fortieth via V40 , and the other end may extend to another display island.
  • the transfer line 418 can realize the transmission of the lighting control signal.
  • the first connection electrode 421 can be electrically connected to the ninth transfer electrode 409 through the forty-second via hole V42, and can also be connected to the first pixel through a thirty-second via hole V32.
  • the first pixel electrode 291 of the circuit is electrically connected. Near the junction of the first display area and the second display area, the initial signal line INIT, the ninth transfer electrode 409 , the first connection electrode 421 , and the first pixel electrode 291 are used to transmit the initial signal.
  • a fifth insulating film is coated on the aforementioned patterned base substrate, and the fifth insulating film is patterned through a patterning process to form a fifth insulating layer.
  • FIG. 19A is a partial schematic diagram of the first display area after forming the fifth insulating layer in FIG. 8 .
  • FIG. 19B is a partial schematic diagram of the second display region after forming the fifth insulating layer in FIG. 10 .
  • FIG. 19C is a partial schematic diagram of the display area after forming the fifth insulating layer in FIG. 11 .
  • the fifth insulating layer of the display area may be provided with a plurality of via holes, for example, may include a fifth type via hole exposing the surface of the third conductive layer, and a transparent conductive layer exposing Type VI vias on the surface of the layer.
  • the sixth type of vias in the first display area may include: fifty-first vias V51 and fifty-second vias V52, and the fifth type of vias may include Fifty-third via hole V53.
  • the fifth-type vias in the second display area may include fifty-fourth vias V54 to fifty-sixth vias V56 .
  • a fourth conductive film is deposited on the base substrate on which the foregoing pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer in the first display area.
  • FIG. 20A is a partial schematic diagram of the first display area after forming the fourth conductive layer in FIG. 8 .
  • FIG. 20B is a partial schematic diagram of the second display area after forming the fourth conductive layer in FIG. 10 .
  • Fig. 11 is a partial schematic diagram of the display area after forming the fourth conductive layer.
  • the fourth conductive layer of the first display area may at least include: a power connection electrode 421 and a first anode connection electrode 422 .
  • One end of the power connection electrode 421 can be electrically connected to the first power transfer wire 419 through the fifty-first via hole V51 , and the other end can be electrically connected to the second power transfer wire 420 through the fifty-second via V52 .
  • the transmission of the first voltage signal along the second direction Y is realized by using the first power transfer line 419 , the power connection electrode 421 , and the second power transfer line 420 .
  • the first anode connection electrode 422 may be electrically connected to the fourth pixel electrode 294 through the fifty-third via hole V53, so as to be electrically connected to the second electrode of the sixth active layer 260 of the second light emission control transistor.
  • the fourth conductive layer of the second display area may at least include: a second anode connection electrode 423 , a second sub-signal line L12 , and an auxiliary wiring line L3 .
  • the second anode connection electrode 423 may be electrically connected to the eighth pixel electrode 298 through the fifty-fourth via hole V54.
  • the auxiliary routing L3 may include a first auxiliary segment L31 extending along the first direction X and a second auxiliary segment L32 extending along the second direction Y.
  • the second auxiliary segment L32 may be electrically connected to the first power line PL1 through the fifty-fifth via hole V55.
  • first auxiliary section L31 is connected to the second auxiliary section L32, and the other end is provided independently.
  • the auxiliary wiring L3 is electrically connected to the first power line PL1 and can transmit the first voltage signal, which is beneficial to improving the display uniformity of the display substrate.
  • the second sub-signal line L12 may include: a first connecting segment L121, a second connecting segment L121 extending along the first direction X, a third connecting segment L123 extending along the second direction Y, And a fourth connecting section L124 extending along the first direction X.
  • One end of the fourth connection section L124 is connected to the third connection section L123, and the other end is independently provided.
  • One end of a second connection segment L122 is connected to the first connection segment L121 , and the other end may be electrically connected to the fifth metal connection line 287 through the fifty-sixth via hole V56 .
  • the second sub-signal line L12 may be electrically connected to the third sub-signal line L13 through the fifth metal connection line 287 .
  • this embodiment does not limit it.
  • the second sub-signal line L12 may be directly electrically connected to the first connection end 501 of the third sub-signal line L13.
  • the orthographic projection of the second sub-signal line L12 and the auxiliary wiring L3 on the base substrate is compatible with the first node of the second pixel circuit (that is, the gate of the driving transistor, the first electrode of the threshold compensation transistor, the storage capacitor
  • the connection point of the first plate) on the orthographic projection of the base substrate may not overlap.
  • the third sub-signal line L13 of the scanning line GL(n) in this example may be electrically connected to the second sub-signal line L12 at the junction of the first display area and the second display area, and connected to the third sub-signal line L13 in the first display area.
  • the gate of the data writing transistor of a pixel circuit, the gate of the threshold compensation transistor and the gate of the second reset transistor are electrically connected.
  • the gate of the data writing transistor and the gate of the second reset transistor of the first pixel circuit in the adjacent display island area can be electrically connected through the sixth transfer line 416, adjacent to the boundary of the first display area
  • the gate of the data writing transistor and the gate of the second reset transistor in the adjacent display island region of the first pixel circuit can be electrically connected through the sixth metal connection line 288 on the third conductive layer.
  • the first sub-signal line of the scan line may include a plurality of sixth transition lines 416 to realize the transmission of the scan signal in the first display area.
  • the third sub-signal line of the scan line can be connected to the first sub-signal line through the sixth metal connection line 288, the gate of the data writing transistor of the first pixel circuit, the gate of the threshold compensation transistor, and the gate of the second reset transistor.
  • the third sub-signal line may be electrically connected to the second sub-signal line through the fifth metal connection line 287 .
  • FIG. 22 is a schematic diagram of wiring at the junction of the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the fourth sub-signal line L14 of the scan line GL(n) may be electrically connected to the second sub-signal line L12 at the junction of the first display area A1 and the second display area A2, It is also electrically connected to the gate 241 of the data writing transistor, the gate 221 of the threshold compensation transistor and the gate 271 of the second reset transistor of the first pixel circuit in the first display area A1.
  • the fourth sub-signal line L14 is connected to the gate 241 of the data writing transistor and the gate of the threshold compensation transistor of the first pixel circuit in the first display area A1 near the junction of the first display area A1 and the second display area A2.
  • the electrode 221 and the gate 271 of the second reset transistor may be of an integral structure.
  • the fourth sub-signal line L14 of the scanning line GL(n) can communicate with the first sub-signal through the gate 241 of the data writing transistor of the first pixel circuit, the gate 221 of the threshold compensation transistor and the gate 271 of the second reset transistor.
  • the fourth sub-signal line L14 may also be electrically connected to the second sub-signal line L12 through the fifth metal connection line 287 .
  • a sixth insulating film is coated on the base substrate formed with the foregoing pattern, and the sixth insulating film is patterned through a patterning process to form a sixth insulating layer.
  • the sixth insulating layer of the first display region may be provided with a plurality of via holes, such as a sixty-first via hole V61 .
  • the sixth insulating layer of the second display region may be provided with a plurality of via holes, such as a sixty-second via hole V62 .
  • an anode film is deposited on the aforementioned patterned base substrate, and the anode film is patterned by a patterning process to form an anode layer.
  • the anode layer of the first display area may include: the anode 120 of the first light emitting element 12, and the anode layer of the second display area may include: the anode of the second light emitting element 14 140.
  • the anode 120 of the first light emitting element 12 may be electrically connected to the first anode connection electrode 422 through the sixty-first via hole V61.
  • the anode 140 of the second light emitting element 14 may be electrically connected to the second anode connection electrode 423 through the sixty-second via hole V62.
  • FIG. 21 is a schematic diagram of the anode layer and the fourth conductive layer in FIG. 10 .
  • the orthographic projection of the auxiliary wiring L3 and the second sub-signal line L12 on the base substrate and the orthographic projection of the anode 140 of the second light emitting element 14 on the base substrate may be different. overlap.
  • the second sub-signal line L12 and the auxiliary wiring L3 may extend along the gap between the anodes 140 of adjacent second light emitting elements.
  • a pixel definition film is coated, and a pixel definition layer is formed through masking, exposure and development processes.
  • the pixel definition layer may be formed with a plurality of pixel openings exposing the anode layer.
  • the pixel definition layer of the first display region may form a first pixel opening OP1 exposing a part of the surface of the anode 120 of the first light emitting element 12 .
  • the pixel definition layer of the second display area may form a second pixel opening OP2 exposing a part of the surface of the anode 140 of the second light emitting element 14 .
  • an organic light emitting layer is formed in the aforementioned pixel opening, and the organic light emitting layer is connected to the anode layer.
  • a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first conductive layer 202, the second conductive layer 203, the third conductive layer 204, and the fourth conductive layer 206 can use metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum Any one or more of (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/ Cu/Mo etc.
  • the transparent conductive layer 205 can be made of a transparent conductive material, such as indium tin oxide (ITO).
  • the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can Is single layer, multilayer or composite layer.
  • Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the fourth insulating layer 104 , the fifth insulating layer 105 and the sixth insulating layer 106 .
  • the pixel definition layer 304 can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer 301 can be made of reflective materials such as metal, and the cathode layer 303 can be made of transparent conductive materials. However, this embodiment does not limit it.
  • the structure of the display substrate and the manufacturing process thereof in this embodiment are merely illustrative.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and is well compatible with the existing preparation process. The process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • the first signal line may further include: a light emission control line and a first reset control line.
  • the winding manner of the light emitting control line and the first reset control line, and the connection manner between the sub-signal lines are similar to the winding manner and connection manner of the scanning line, so details will not be repeated here.
  • the display substrate provided in this example can reduce the load of the scanning signal of the first display area by setting the scanning line to include the first sub-signal line and the second sub-signal line connected in parallel and electrically, which is beneficial to improve the left and right sides of the first display area.
  • Lateral display defects (Mura) on the side can improve the display uniformity of the display substrate.
  • FIG. 23 is a partial schematic diagram of a second signal line of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include a plurality of second signal lines L2.
  • the second signal line L2 may provide the second signal to the second pixel circuit in the first display area A1 in the second direction Y.
  • the second signal line L2 may include at least one of the following: a data line and a first power line.
  • the second signal line L2 may include: a fifth sub-signal line L21 , a sixth sub-signal line L22 , a seventh sub-signal line L23 and an eighth sub-signal line L24 .
  • Both the seventh sub-signal line L23 and the eighth sub-signal line L24 may extend along the second direction Y, and are located in the second display area on opposite sides of the first display area A1 along the second direction Y.
  • the fifth sub-signal line L21 may be located in the first display area A1 and extend along the second direction Y. Both ends of the fifth sub-signal line L21 may be electrically connected to the seventh sub-signal line L23 and the eighth sub-signal line L24, respectively.
  • the sixth sub-signal line L22 may be located in the second display area.
  • the sixth sub-signal line L22 may bypass the first display area A1, and both ends of the sixth sub-signal line L22 may be electrically connected to the seventh sub-signal line L23 and the eighth sub-signal line L24, respectively.
  • the sixth sub-signal line L22 may extend along the first direction X, then extend along the second direction Y, and then extend along the first direction X.
  • the fifth sub-signal line L21 and the sixth sub-signal line L22 of the second signal line L2 are electrically connected in parallel, and are connected in series with the seventh sub-signal line L23 and the eighth sub-signal line L24.
  • the data connection line 45 in the foregoing embodiment can be the fifth sub-signal line L21 located in the first display area, and the second display area can also include a data connection line 45 parallel and electrically connected sixth sub-signal line L22.
  • the fifth sub-signal line L21 may be located in the transparent conductive layer, and the sixth sub-signal line L22 may be in the fourth conductive layer.
  • this embodiment does not limit it.
  • the plurality of second signal lines L2 may be divided into two groups.
  • the first group of second signal lines and the second group of second signal lines may be approximately symmetrical with respect to the second central line O2 along the first direction X of the first display area A1 .
  • the number of second signal lines in the first group of second signal lines may be approximately the same as the number of second signal lines in the second group of second signal lines.
  • the sixth sub-signal line L22 of the second signal line L2 in the first group of second signal lines may be located in the second display area on the side of the first display area A1 along the first direction X, and in the second group of second signal lines
  • the sixth sub-signal line L22 of the second signal line L2 may be located in the second display area on the other side of the first display area A1 along the first direction X.
  • the sixth sub-signal line L22 of the first group of second signal lines can bypass the first display area A1 from the left side of the first display area A1
  • the sixth sub-signal line L22 of the second group of second signal lines can bypass the first display area A1 from the left side of the first display area A1.
  • the right side of the first display area A1 bypasses the first display area A1. In this way, it is possible to avoid the accumulation of wires and affect the display effect.
  • the sixth sub-signal line L22 of the second signal line L2 close to the edge of the first display area A1 in the first direction X may be located close to the first display area A1 along the first direction.
  • the sixth sub-signal line L22 of the second signal line L2 of the second middle line O2 of X is close to one side of the first display area A1.
  • the length of the sixth sub-signal line L22 of the second signal line L2 along the first direction X close to the second central line O2 of the first display area A1 along the first direction X may be longer than the length of the sixth sub-signal line L2 of the second signal line L2 close to the edge of the first display area A1.
  • the length of the sixth sub-signal line L22 of the second signal line L2 along the first direction X may be longer than the length of the sixth sub-signal line L22 of the second signal line L2 close to the edge of the first display area A1.
  • the second signal can be transmitted in the first display area A1 through the fifth sub-signal line L21 , and can also be transmitted in the second display area through the sixth sub-signal line L22 .
  • the transmission load of the second signal in the first display area A1 can be reduced, thereby improving the first display area
  • the vertical display in the second display area on the upper and lower sides of A1 is defective.
  • FIG. 24 is a partial schematic diagram of a first signal line and a second signal line of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include a plurality of first signal lines L1 and a plurality of second signal lines L2 .
  • the first signal line L1 may include a parallel and electrically connected first sub-signal line L11 and a second sub-signal line L12
  • the second signal line L2 may include a parallel and electrically connected fifth sub-signal line L21 and a sixth sub-signal line. L22.
  • the first sub-signal line L11 and the fifth sub-signal line L21 may be located in the first display area A1
  • the second sub-signal line L12 and the sixth sub-signal line L22 may be located in the second display area A2.
  • the first sub-signal line L11 and the fifth sub-signal line L21 may be located on the transparent conductive layer.
  • the second sub-signal line L12 and the sixth sub-signal line L22 may be located in the same film layer, for example, may be located in the fourth conductive layer, so as to save manufacturing process.
  • the second sub-signal line L12 and the sixth sub-signal line L22 may be located in different film layers, for example, the second sub-signal line L12 may be located in the fourth conductive layer, and the sixth sub-signal line L22 may be located in the fourth conductive layer.
  • the conductive layer is far away from the fifth conductive layer on one side of the base substrate, so as to avoid wire crossing.
  • the display substrate may further include a first auxiliary wiring provided on the same layer as the second sub-signal line, and a second auxiliary wiring provided on the same layer as the sixth sub-signal line.
  • the shape of the first auxiliary wiring can be similar to that of the second sub-signal line
  • the shape of the second auxiliary wiring can be similar to that of the sixth sub-signal line, so as to achieve wiring and display uniformity in the display area.
  • At least one embodiment of the present disclosure further provides a display device, including the above-mentioned display substrate.
  • FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 25 , this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light emitting side of the display structure layer away from the display substrate 91 . The orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the first display area A1.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device can be any product or component with a display function such as an OLED display, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板，包括：衬底基板(100)、多个第一像素电路(11)、多个第一发光元件(12)以及至少一条第一信号线(L1)。多个第一像素电路(11)和多个第一发光元件(12)位于第一显示区(A1)。至少一个第一像素电路(11)与至少一个第一发光元件(12)电连接，配置为驱动所述至少一个第一发光元件(12)发光。至少一条第一信号线(L1)配置为在第一方向(X)上给多个第一像素电路(11)提供第一信号。至少一条第一信号线(L1)包括并联且电连接的第一子信号线(L11)和第二子信号线(L12)，第一子信号线(L11)位于第一显示区(A1)，第二子信号线(L12)位于第二显示区(A2)。

Description

显示基板及显示装置
本申请要求于2021年10月20日提交中国专利局、申请号为202111221399.2、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，显示设备上通常会安装摄像头来满足拍摄需求。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、多个第一像素电路、多个第一发光元件、以及至少一条第一信号线。衬底基板，包括第一显示区和位于所述第一显示区至少一侧的第二显示区。多个第一像素电路和多个第一发光元件位于所述第一显示区。所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件电连接，配置为驱动所述至少一个第一发光元件发光。至少一条第一信号线，配置为在第一方向上给多个第一像素电路提供第一信号。至少一条第一信号线包括并联且电连接的第一子信号线和第二子信号线，所述第一子信号线位 于所述第一显示区，所述第二子信号线位于所述第二显示区。
在一些示例性实施方式中，所述第一子信号线采用透明导电材料，所述第二子信号线采用金属材料。
在一些示例性实施方式中，所述第二子信号线位于所述第一子信号线远离所述衬底基板的一侧。
在一些示例性实施方式中，所述至少一条第一信号线还包括：位于所述第二显示区的第三子信号线和第四子信号线，所述第三子信号线和所述第四子信号线位于所述第一显示区沿所述第一方向的相对两侧的第二显示区内。所述第一子信号线的两端分别与所述第三子信号线和所述第四子信号线电连接，所述第二子信号线的两端分别与所述第三子信号线和所述第四子信号线电连接。
在一些示例性实施方式中，所述第一子信号线的至少一端通过至少一个第一像素电路的晶体管的栅极与第三子信号线或第四子信号线电连接。
在一些示例性实施方式中，所述显示基板包括多条第一信号线，所述多条第一信号线被分为两组，第一组第一信号线的第二子信号线位于所述第一显示区沿第二方向一侧的第二显示区内，第二组第一信号线的第二子信号线位于所述第一显示区沿所述第二方向另一侧的第二显示区内，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述显示基板还包括：位于所述第二显示区的多个第二像素电路和多个第二发光元件，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，配置为驱动所述至少一个第二发光元件发光。所述至少一条第一信号线的第二子信号线在所述衬底基板的正投影与所述第二发光元件的阳极在所述衬底基板的正投影没有交叠。
在一些示例性实施方式中，所述第二像素电路至少包括：驱动晶体管、阈值补偿晶体管和存储电容。所述驱动晶体管的栅极与所述存储电容的第一极板和所述阈值补偿晶体管的第一极电连接。所述至少一条第一信号线的第二子信号线在所述衬底基板的正投影与所述第二像素电路的驱动晶体管的栅极、所述阈值补偿晶体管的第一极和所述存储电容的第一极板的连接位置在 所述衬底基板的正投影没有交叠。
在一些示例性实施方式中，所述第二子信号线包括：第一连接段、第二连接段、第三连接段和第四连接段。所述第二连接段为沿所述第一方向延伸的直线段，所述第二连接段与所述第一连接段电连接，所述第一连接段配置为至少部分包围一个第二发光元件的阳极。所述第三连接段为沿第二方向延伸的折线，所述第四连接段与所述第三连接段连接，所述第四连接段为沿所述第一方向延伸的直线段。所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述第二显示区还设置有与所述第二子信号线同层设置的多条辅助走线，所述多条辅助走线在所述衬底基板的正投影与所述第二发光元件的阳极、以及所述第二像素电路的所述驱动晶体管的栅极、所述阈值补偿晶体管的第一极和所述存储电容的第一极板的连接位置在所述衬底基板的正投影没有交叠。
在一些示例性实施方式中，所述辅助走线被配置为与第一电源线电连接。
在一些示例性实施方式中，所述多条辅助走线中的至少一条包括：相互连接的第一辅助段和第二辅助段，所述第一辅助段为沿所述第一方向延伸的直线段，所述第二辅助段为沿第二方向延伸的折线，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述至少一条第一信号线包括以下至少之一：扫描线、第一复位控制线、发光控制线。
在一些示例性实施方式中，所述显示基板还包括：至少一条第二信号线，配置为在第二方向上给多个第一像素电路提供第二信号。所述至少一条第二信号线包括并联且电连接的第五子信号线和第六子信号线，所述第五子信号线位于所述第一显示区，所述第六子信号线位于所述第二显示区；所述第一方向与第二方向交叉。
在一些示例性实施方式中，所述第一方向垂直于所述第二方向。
在一些示例性实施方式中，所述至少一条第二信号线还包括：位于所述第二显示区的第七子信号线和第八子信号线，所述第七子信号线和所述第八子信号线位于所述第一显示区沿所述第二方向的相对两侧的第二显示区内。 所述第五子信号线的两端分别与所述第七子信号线和所述第八子信号线电连接，所述第六子信号线的两端分别与所述第七子信号线和所述第八子信号线电连接。
在一些示例性实施方式中，所述第五子信号线与所述第一子信号线同层设置，所述第六子信号线与所述第二子信号线位于不同膜层。
在一些示例性实施方式中，所述第一显示区的像素密度小于或等于所述第二显示区的像素密度。
在一些示例性实施方式中，所述第一显示区的光透过率大于所述第二显示区的光透过率。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为图2提供的像素电路的工作时序图；
图4为本公开至少一实施例的显示基板的第一信号线的局部示意图；
图5和图6为本公开至少一实施例的显示基板的局部走线示意图；
图7为本公开至少一实施例的显示区域的局部平面示意图；
图8为图7中区域A11的局部平面示意图；
图9为图8中沿Q-Q’方向的局部剖面示意图；
图10为图7中区域A12的局部平面示意图；
图11为图7中区域A13的局部平面示意图；
图12A为图8中形成半导体层后的第一显示区的局部示意图；
图12B为图10中形成半导体层后的第二显示区的局部示意图；
图12C为图11中形成半导体层后的显示区域的局部示意图；
图13A为图8中形成第一导电层后的第一显示区的局部示意图；
图13B为图10中形成第一导电层后的第二显示区的局部示意图；
图13C为图11中形成第一导电层后的显示区域的局部示意图；
图14A为图8中形成第二导电层后的第一显示区的局部示意图；
图14B为图10中形成第二导电层后的第二显示区的局部示意图；
图14C为图11中形成第二导电层后的显示区域的局部示意图；
图15A为图8中形成第三绝缘层后的第一显示区的局部示意图；
图15B为图10中形成第三绝缘层后的第二显示区的局部示意图；
图15C为图11中形成第三绝缘层后的显示区域的局部示意图；
图16A为图8中形成第三导电层后的第一显示区的局部示意图；
图16B为图10中形成第三导电层后的第二显示区的局部示意图；
图16C为图11中形成第三导电层后的显示区域的局部示意图；
图17A为图8中形成第四绝缘层后的第一显示区的局部示意图；
图17B为图11中形成第四绝缘层后的显示区域的局部示意图；
图18A为图8中形成透明导电层后的第一显示区的局部示意图；
图18B为图11中形成透明导电层后的显示区域的局部示意图；
图19A为图8中形成第五绝缘层后的第一显示区的局部示意图；
图19B为图10中形成第五绝缘层后的第二显示区的局部示意图；
图19C为图11中形成第五绝缘层后的显示区域的局部示意图；
图20A为图8中形成第四导电层后的第一显示区的局部示意图；
图20B为图10中形成第四导电层后的第二显示区的局部示意图；
图21为图10中阳极层和第四导电层的示意图；
图22为本公开至少一实施例的第一显示区和第二显示区的交界处的走线示意图；
图23为本公开至少一实施例的显示基板的第二信号线的局部示意图；
图24为本公开至少一实施例的显示基板的第一信号线和第二信号线的局部示意图；
图25为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展 的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本公开实施例提供一种显示基板，包括：衬底基板、多个第一像素电路、多个第一发光元件以及至少一条第一信号线。衬底基板包括第一显示区和位于第一显示区至少一侧的第二显示区。多个第一像素电路和多个第一发光元件位于第一显示区。至少一个第一像素电路与至少一个第一发光元件电连接，配置为驱动至少一个第一发光元件发光。至少一条第一信号线配置为在第一方向上给多个第一像素电路提供第一信号。至少一条第一信号线包括并联且电连接的第一子信号线和第二子信号线。第一子信号线的至少部分位于第一显示区，第二子信号线位于第二显示区。
在本实施例中，并联是指将至少两个同类或不同类的元件并列连接在电路的两点之间的一种连接方式。在本示例中，第一子信号线可以具有第一端和第二端，第二子信号线可以具有第一端和第二端，第一子信号线和第二子信号线并联是指第一子信号线的第一端和第二子信号线的第一端电连接，第一子信号线的第二端和第二子信号线的第二端电连接，第一子信号线和第二子信号线并列接入第一信号的传输电路中。
本实施例提供的显示基板，通过设置第一信号线采用并联走线方式向第一显示区传输第一信号，可以改善第一信号线的阻抗对第一显示区的影响，从而可以提升显示基板的刷新率和均一化显示效果。
在一些示例性实施方式中，第一子信号线可以采用透明导电材料，例如氧化铟锡(ITO)等，第二子信号线可以采用金属材料。第一子信号线采用透明导电材料，可以确保第一显示区的光透过率。由于透明导电材料的电阻大于金属材料的电阻，本示例采用金属材料的第二子信号线与采用透明导电材料的第一子信号线进行并联且电连接，可以改善由于第一子信号线的电阻过大在第一显示区周边的第二显示区产生的显示不良，从而可以提升显示基板的刷新率和均一化显示效果。
在一些示例性实施方式中，第二子信号线可以位于第一子信号线远离衬底基板的一侧。然而，本实施例对此并不限定。在另一些示例中，第二子信号线可以位于第一子信号线靠近衬底基板的一侧。
在一些示例性实施方式中，显示基板还可以包括：位于第二显示区的多个第二像素电路和多个第二发光元件。多个第二像素电路中的至少一个第二像素电路与多个第二发光元件中的至少一个第二发光元件电连接，配置为驱动所述至少一个第二发光元件发光。至少一条第一信号线的第二子信号线在衬底基板的正投影与第二发光元件的阳极在衬底基板的正投影没有交叠。本示例通过设置第一信号线的第二子信号线绕过第二发光元件的阳极排布，可以保证第二发光元件的平坦性，从而保证第二发光元件的显示效果。
在一些示例性实施方式中，第二像素电路可以至少包括：驱动晶体管、阈值补偿晶体管和存储电容。驱动晶体管的栅极与存储电容的第一极板和阈值补偿晶体管的第一极电连接。至少一条第一信号线的第二子信号线在衬底基板的正投影与第二像素电路的驱动晶体管的栅极、阈值补偿晶体管的第一极和存储电容的第一极板的连接位置在衬底基板的正投影没有交叠。本示例中，第二像素电路的驱动晶体管的栅极、阈值补偿晶体管的第一极和存储电容的第一极板的连接点为第一节点，通过设置第一信号线的第二子信号线避开第一节点，可以降低第一信号线传输的第一信号对第一节点的串扰。
在一些示例性实施方式中，第二显示区还可以包括：与第二子信号线同层设置的多条辅助走线。多条辅助走线在衬底基板的正投影与第二发光元件的阳极在衬底基板的正投影可以没有交叠，还可以与第二像素电路的驱动晶体管的栅极、阈值补偿晶体管的第一极和存储电容的第一极板的连接位置在衬底基板的正投影没有交叠。本示例通过设置与第二子信号线的排布类似的辅助走线，且辅助走线绕过第二发光元件的阳极和第二像素电路的第一节点，可以保证显示区域的走线均一性，而且可以保证第二发光元件的显示效果，并降低对第一节点的串扰。
在一些示例性实施方式中，辅助走线可以被配置为与第一电源线电连接。如此一来，可以改善显示基板的显示均一性。
在一些示例性实施方式中，显示基板还可以包括：至少一条第二信号线，配置为在第二方向上给多个第一像素电路提供第二信号。至少一条第二信号线可以包括并联且电连接的第五子信号线和第六子信号线，第五子信号线可以位于第一显示区，第六子信号线可以位于第二显示区。第一方向与第二方 向交叉。例如，第一方向可以垂直于第二方向。本示例通过设置第二信号线采用并联走线方式向第一显示区传输第二信号，可以改善第二信号线的阻抗对第一显示区的影响，从而可以提升显示基板的刷新率和均一化显示效果。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA外围的周边区域BB。显示基板的显示区域AA可以包括：第一显示区A1和位于第一显示区A1至少一侧的第二显示区A2。例如，第二显示区A2可以围绕在第一显示区A1的四周。第一显示区A1可以位于显示区域AA的顶部正中间位置。然而，本实施例对此并不限定。例如，第一显示区A1可以位于显示区域AA的左上角或者右上角等其他位置。
在一些示例中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。第一显示区A1可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第一显示区A1可以为矩形、五边形、或六边形等其他形状。
在一些示例中，如图1所示，第一显示区A1可以为透光显示区，还可以称为屏下摄像头(FDC，Full Display With Camera)区域。第二显示区A2可以为非透光显示区，还可以称为正常显示区。第一显示区A1的光透过率可以大于第二显示区A2的光透过率。例如，感光传感器(比如，摄像头、红外传感器)等硬件在显示基板上的正投影可以位于显示基板的第一显示区A1内。在一些示例中，第一显示区A1可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的尺寸。然而，本实施例对此并不限定。在另一些示例中，第一显示区可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区的内切圆的尺寸。
在一些示例中，显示区域AA至少可以包括规则排布的多个像素单元、沿着第一方向X延伸的多条第一信号线(例如包括：扫描线、复位控制线、发光控制线)、沿着第二方向Y延伸的多条第二信号线(例如包括数据线和电源线)。其中，第一方向X和第二方向Y可以位于同一平面内，且第一方向X与第二方向Y交叉，例如，第一方向X可以垂直于第二方向Y。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三 个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，至少一个子像素可以包括像素电路和发光元件。像素电路可以配置为驱动所连接的发光元件。例如，像素电路可以配置为提供驱动电流以驱动发光元件发光。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以为3T1C结构、8T1C结构、7T1C结构或者5T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可以根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例中，发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。本示例的像素电路以7T1C结构为例进行说明。图3为图2提供的像素电路的工作时序图。
在一些示例中，如图2所示，本示例的像素电路可以包括：六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括阳极、阴极以及位于阳极和阴极之间的有机发光 层。
在一些示例中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPS+Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，如图2所示，像素电路可以与扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、初始信号线INIT、第一复位控制线RST1和第二复位控制线RST2电连接。在一些示例中，第一电源线PL1可以配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2可以配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL可以配置为向像素电路提供扫描信号SCAN，数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM，第一复位控制线RST1可以配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2可以配置为向像素电路提供第二复位信号RESET2。
在一些示例中，在一行像素电路中，第二复位控制线RST2可以与扫描线GL相连，以被输入扫描信号SCAN。即，第n行像素电路接收的第二复位信号RESET2(n)为第n行像素电路接收的扫描信号SCAN(n)。其中，n为正整数。然而，本实施例对此并不限定。例如，第二复位控制信号线RST2可以被输入不同于扫描信号SCAN的第二复位控制信号RESET2。在一些示 例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例中，如图2所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与初始信号线INIT电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与初始信号线INIT电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一极板与驱动晶体管T3的栅极电连接，存储电容Cst的第二极板与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱 动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图3对图2所示的像素电路的工作过程进行说明。其中，以图2所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。在本示例中，第二复位控制线RST2可以与扫描线GL相连，以被输入扫描信号SCAN。
在一些示例中，如图2和图3所示，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，初始信号线INIT提供的初始信号Vinit被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N2，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得初始信号线INIT提供的初始信号Vinit提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化， 确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[(VDD-Vdata)] 2；
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
在一些示例中，如图1所示，显示基板的第一显示区A1可以设置有多个第一发光元件12和多个第一像素电路11。至少一个第一像素电路11与至少一个第一发光元件12电连接，配置为驱动至少一个第一发光元件12发光。第一像素电路11与所电连接的第一发光元件12在衬底基板的正投影可以至少部分交叠。第二显示区A2可以设置有多个第二发光元件14和多个第二像素电路13。至少一个第二像素电路13与至少一个第二发光元件14电连接，配置为驱动至少一个第二发光元件14发光。第二像素电路13与所电连接的 第二发光元件14在衬底基板的正投影可以至少部分交叠。例如，多个第一像素电路11和多个第一发光元件12可以一一对应电连接，多个第二像素电路13和多个第二发光元件14可以一一对应电连接。然而，本实施例对此并不限定。例如，第一像素电路11和第一发光元件12可以为一对多的关系。又如，第二像素电路13和第二发光元件14可以为一对多的关系。
图4为本公开至少一实施例的显示基板的第一信号线的局部示意图。在一些示例中，如图4所示，显示基板包括多条第一信号线L1。第一信号线L1可以在第一方向X上给第一显示区A1内的第一像素电路提供第一信号。例如，第一信号线L1可以包括以下至少之一：扫描线、第一复位控制线、发光控制线。
在一些示例中，如图4所示，第一信号线L1可以包括：第一子信号线L11、第二子信号线L12、第三子信号线L13和第四子信号线L14。第三子信号线L13和第四子信号线L14可以均沿第一方向X延伸，并位于第一显示区A1沿第一方向X相对两侧的第二显示区内。第一子信号线L11可以位于第一显示区A1内，并沿第一方向X延伸。第一子信号线L11的两端可以分别与第三子信号线L13和第四子信号线L14电连接。第二子信号线L12可以位于第二显示区。第二子信号线L12可以绕过第一显示区A1，且第二子信号线L12的两端可以分别与第三子信号线L13和第四子信号线L14电连接。例如，第二子信号线L12可以先沿第二方向Y延伸，再沿第一方向X延伸，再沿第二方向Y延伸。第一信号线L1的第一子信号线L11和第二子信号线L12并联且电连接，并与第三子信号线L13和第四子信号线L14串联连接。
在一些示例中，如图4所示，多条第一信号线L1可以被分为两组。例如，第一组第一信号线和第二组第一信号线可以关于第一显示区A1沿第二方向Y的第一中线O1大致对称。第一组第一信号线内的第一信号线的数目和第二组第一信号线内的第一信号线的数目可以大致相同。第一组第一信号线内的第一信号线L1的第二子信号线L12可以位于第一显示区A1沿第二方向Y一侧的第二显示区内，第二组第一信号线内的第一信号线L1的第二子信号线L12可以位于第一显示区A1沿第二方向Y另一侧的第二显示区内。例如，第一组第一信号线的第二子信号线L12可以从第一显示区A1的上侧 绕过第一显示区A1，第二组第一信号线的第二子信号线L12可以从第一显示区A1的下侧绕过第一显示区A1。如此一来，可以避免走线聚集，影响显示效果。
在一些示例中，如图4所示，在第二方向Y上靠近第一显示区A1边缘的第一信号线L1的第二子信号线L12，可以位于靠近第一显示区A1沿第二方向Y的第一中线O1的第一信号线L1的第二子信号线L12靠近第一显示区A1的一侧。换言之，靠近第一显示区A1沿第二方向Y的第一中线O1的第一信号线L1的第二子信号线L12沿第二方向Y的长度，可以大于靠近第一显示区A1边缘的第一信号线L1的第二子信号线L12沿第二方向Y的长度。如此一来，可以减少走线交叠，有利于合理排布第二子信号线L12。
在一些示例中，如图4所示，第一信号可以通过第一子信号线L11在第一显示区A1内进行传输，还可以通过第二子信号线L12在第二显示区内进行传输。本示例通过设置并联且电连接的第一子信号线L11和第二子信号线L12进行第一信号的传输，可以降低第一显示区A1的第一信号的传输负载，从而改善第一显示区A1左右两侧的第二显示区存在的横向显示不良。
图5和图6为本公开至少一实施例的显示基板的局部走线示意图。图7为本公开至少一实施例的显示区域的局部平面示意图。图5中示意了一条第一信号线的第二子信号线，图6中示意了三条第一信号线的第二子信号线。图7中示意了第一显示区A1的多个第一发光元件12的阳极120、第二显示区A2的多个第二发光元件14的阳极140以及第二显示区A2的部分第二子信号线L12和辅助走线L3。
在一些示例中，如图7所示，第一显示区A1的像素密度(PPI)可以小于第二显示区A2的像素密度。然而，本实施例对此并不限定。在另一些示例中，第一显示区的像素密度可以等于第二显示区的像素密度。
在一些示例中，如图5和图7所示，第一信号线的第二子信号线L12在衬底基板的正投影与第二发光元件14的阳极140在衬底基板的正投影可以没有交叠。第二子信号线L12绕过第二发光元件14的阳极140，以保证第二发光元件14的平坦性，从而确保第二发光元件14的发光效果。
在一些示例中，如图5和图7所示，第一信号线的第二子信号线L12可 以包括：第一连接段L121、第二连接段L122、第三连接段L123和第四连接段L124。第一连接段L121可以为由多个直线段连接形成的非密闭形状，一个第二发光元件14的阳极140可以位于第一连接段L121所围绕的区域内。第一连接段L121可以部分包围一个第二发光元件14的阳极140。第二连接段L122可以为沿第一方向X延伸的直线段。第二连接段L122连接相邻的第一连接段L121。如图5所示，第一连接段L121和第二连接段L122可以间隔连接，使得第二子信号线L12可以沿第一方向X绕过多个第二发光元件14的阳极140。第三连接段L123可以为沿第二方向Y延伸的折线，第四连接段L124可以为沿第一方向X延伸的直线段。多个第四连接段L124可以连接在第三连接段L123的一侧。第四连接段L124仅一端与第三连接段L123连接。第四连接段L124可以位于沿第二方向Y排布的相邻第二发光元件14的阳极140之间。第二子信号线L12通过第三连接段L123可以沿第二方向Y绕过第二发光元件14的阳极140，通过第四连接段L124可以使得第二发光元件14的阳极140四周的走线环境一致。然而，本实施例对此并不限定。在另一些示例中，第一连接段L121可以由曲线段连接形成，第二连接段L122、第三连接段L123和第四连接段L124可以为曲线段。
在一些示例中，如图6所示，多条第一信号线的第二子信号线L12沿第一方向X延伸的部分可以在第二方向Y上相邻排布。多条第一信号线的第二子信号线L12沿第二方向Y延伸的部分可以相邻或者间隔多条辅助走线L3。如图6和图7所示，辅助走线L3可以包括：第一辅助段L31和第二辅助段L32。第一辅助段L31可以为沿第一方向X延伸的直线段。第二辅助段L32可以为沿第二方向Y延伸的折线。第一辅助段L31和第二辅助段L32相互连接。多个第一辅助段L31可以连接在第二辅助段L32的同一侧。辅助走线L3在衬底基板的正投影与第二发光元件14的阳极140在衬底基板的正投影可以没有交叠。辅助走线L3的形状与第二子信号线L12的形状可以类似。本示例通过设置辅助走线L3可以保证显示基板的显示区域的走线均一性排布。
在一些示例中，如图7所示，第二显示区A2内的至少一个第二发光元件14的阳极140可以被第二子信号线L12和辅助走线L3包围或者部分包围。 第二子信号线L12和辅助走线L3均绕过第二发光元件14的阳极140布线，可以保证第二发光元件14的平坦性，且确保第二发光元件14四周的走线环境均一性，避免对第二发光元件14的发光效果产生影响。
下面以扫描线为第一信号线为例进行说明。
图8为图7中区域A11的局部平面示意图。图9为图8中沿Q-Q’方向的局部剖面示意图。图10为图7中区域A12的局部平面示意图。图11为图7中区域A13的局部平面示意图。图8中示意了六个第一像素电路和六个第一发光元件；图10中示意了八个第二像素电路和八个第二发光元件；图11中示意了在第一显示区A1和第二显示区A2的交界处相邻的一个第一像素电路和一个第二像素电路。
在一些示例中，如图8所示，在平行于显示基板的平面内，第一显示区可以包括彼此隔开的多个显示岛区A1a以及位于相邻显示岛区A1a之间的透光区A1b。每个显示岛区A1a可以配置为进行图像显示，每个透光区A1b可以配置为提供光线透射空间。多个显示岛区A1a的形状可以大致相同，显示岛区A1a可以具有光滑边缘，从而降低光线衍射效果，有利于提高拍摄效果。第一显示区内的显示岛区A1a可以相互独立，第一显示区内的透光区A1b可以相互连通，透光区A1b可以围绕在显示岛区A1a的四周。每个显示岛区A1a可以包括一个子像素。第一发光元件与所电连接的第一像素电路在衬底基板的正投影存在交叠。
在一些示例中，如图10所示，在平行于显示基板的平面内，第二显示区内的一个像素单元可以包括：出射第一颜色光的子像素P1、出射第二颜色光的子像素P2、出射第三颜色光的子像素P3和出射第四颜色光的子像素P4。第二发光元件与所电连接的第二像素电路在衬底基板的正投影存在交叠。第二显示区的多个第二像素电路可以阵列排布，多个第二发光元件可以按照Pentile结构排布。例如，出射第一颜色光的第二发光元件和出射第二颜色光的第二发光元件可以沿第一方向X和第二方向Y交替排布，出射第三颜色光的第二发光元件和出射第四颜色光的第二发光元件可以沿第一方向X和第二方向Y交替排布；出射第一颜色光和第二颜色光的第二发光元件所在的行与出射第三颜色光和第四颜色光的第二发光元件所在的行存在错位，出射第一 颜色光和第二颜色光的第二发光元件所在的列与出射第三颜色光和第四颜色光的第二发光元件所在的列存在错位。例如，第一颜色光可以为红光，第二颜色光可以为蓝光，第三颜色光和第四颜色光可以为绿光。关于第一显示区内的第一像素电路和第一发光元件的排布方式可以参照第二发光元件的排布方式，故于此不再赘述。
在一些示例中，如图9所示，在垂直于显示基板的方向上，显示基板可以包括：衬底基板100、设置在衬底基板100上的电路结构层、发光结构层和封装结构层400。电路结构层可以包括：依次设置在衬底基板100上的半导体层201、第一导电层(或称为第一栅金属层)202、第二导电层(或称为第二栅金属层)203、第三导电层(或称为第一源漏金属层)204、透明导电层205、第四导电层(或称为第二源漏金属层)206。半导体层201和第一导电层202之间设置第一绝缘层(或称为第一栅绝缘层)101，第一导电层202和第二导电层203之间设置第二绝缘层(或称为第二栅绝缘层)102，第二导电层203和第三导电层204之间设置第三绝缘层(或称为层间绝缘层)103，第三导电层204和透明导电层205之间设置第四绝缘层104，透明导电层205和第四导电层206之间设置第五绝缘层105。第四导电层206远离衬底基板100的一侧设置第六绝缘层106。在一些示例中，第一绝缘层101至第三绝缘层103可以为无机绝缘层，第四绝缘层104至第六绝缘层106可以为有机绝缘层。然而，本实施例对此并不限定。
在一些示例中，如图9所示，发光结构层可以至少包括：依次设置在电路结构层上的阳极层301、像素定义层304、有机发光层302和阴极层303。阳极层301可以与电路结构层的像素电路(例如第一像素电路或第二像素电路)电连接，有机发光层302可以与阳极层301连接，阴极层303可以与有机发光层302连接，有机发光层302可以在阳极层301和阴极层303的驱动下出射相应颜色的光线。在一些示例中，封装结构层400可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层可以设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层。在一些可能的实现方式中，显示基板还可以 包括其它膜层，如触控结构层、彩色滤光层等，本实施例在此不做限定。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本说明书所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，或者A和B靠近衬底一侧的表面与衬底的距离基本相同，或者A和B靠近衬底一侧的表面与同一个膜层直接接触。膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本说明书中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底基板。在一些示例中，衬底基板可以为刚性基底或者柔性基底。例如，刚性基底可以为但不限于玻璃、石英中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些示例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用硅氮化物(SiNx)或硅氧化物(SiOx)等，用于提高衬底的抗水氧能力。
(2)、形成半导体层。在一些示例中，在衬底基板上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成设置在衬底基板上的半导体层。在一些示例中，半导体层的材料可以采用非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料。
图12A为图8中形成半导体层后的第一显示区的局部示意图。图12B为图10中形成半导体层后的第二显示区的局部示意图。图12C为图11中形成半导体层后的显示区域的局部示意图。
在一些示例中，如图12A和图12C所示，第一显示区的半导体层可以至少包括：第一像素电路的多个晶体管的有源层(例如包括：第一像素电路的第一复位晶体管的第一有源层210、阈值补偿晶体管的第二有源层220、驱动晶体管的第三有源层230、数据写入晶体管的第四有源层240、第一发光控制晶体管的第五有源层250、第二发光控制晶体管的第六有源层260、第二复位晶体管的第七有源层270)。每个有源层可以包括：沟道区、以及位于沟道区相对两侧的第一区和第二区。每个第一像素电路的七个晶体管的有源层可以为一体结构。不同第一像素电路的晶体管的有源层相互独立。例如，第一像素电路的第四有源层240、第五有源层250、第六有源层260和第七有源层270可以大致为I字型，第一有源层210和第三有源层230可以大致为n字型，第二有源层220可以大致为L字型。
在一些示例中，如图12B和图12C所示，第二显示区的半导体层可以至少包括：第二像素电路的多个晶体管的有源层(例如包括：第二像素电路的第一复位晶体管的第一有源层310、阈值补偿晶体管的第二有源层320、驱动晶体管的第三有源层330、数据写入晶体管的第四有源层340、第一发光控制晶体管的第五有源层350、第二发光控制晶体管的第六有源层360、第二复位晶体管的第七有源层370)。每个第二像素电路的七个晶体管的有源层可以为一体结构，且沿第二方向Y相邻的第二像素电路的晶体管的有源层可以为一体结构。例如，第二像素电路的第四有源层340可以大致为I字型，第一有源层310和第三有源层330可以大致为n字型，第二有源层320、第五有源层350、第六有源层360和第七有源层370可以大致为L字型。
(3)、形成第一导电层。在一些示例中，在形成前述结构的衬底基板上， 依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成第一绝缘层以及设置在第一绝缘层上的第一导电层。
图13A为图8中形成第一导电层后的第一显示区的局部示意图。图13B为图10中形成第一导电层后的第二显示区的局部示意图。图13C为图11中形成第一导电层后的显示区域的局部示意图。
在一些示例中，如图13A和图13C所示，第一显示区的第一导电层可以至少包括：第一像素电路的多个晶体管的栅极(例如包括：第一像素电路的第一复位晶体管21的栅极211、阈值补偿晶体管22的栅极221、驱动晶体管23的栅极231、数据写入晶体管24的栅极241、第一发光控制晶体管25的栅极251、第二发光控制晶体管26的栅极261、第二复位晶体管27的栅极271)、第一像素电路的存储电容28的第一极板281、以及第一金属连接线283和第二金属连接线284。其中，阈值补偿晶体管22的栅极221、数据写入晶体管24的栅极241以及第二复位晶体管27的栅极271可以为一体结构。驱动晶体管的栅极231和存储电容28的第一极板281可以为一体结构。第一发光控制晶体管25的栅极251和第二发光控制晶体管26的栅极261可以为一体结构。第一像素电路的第一复位晶体管21的栅极211与第一金属连接线283可以为一体结构。在靠近第一显示区和第二显示区的交界处的相邻第一像素电路的第一复位晶体管21的栅极211可以通过第一金属连接线283电连接。第一像素电路的第二发光控制晶体管26的栅极261与第二金属连接线284可以为一体结构。在靠近第一显示区和第二显示区的交界处的相邻第一像素电路的第一发光控制晶体管25的栅极251和第二发光控制晶体管26的栅极261可以通过第二金属连接线284电连接。
在一些示例中，如图13B和图13C所示，第二显示区的第一导电层可以至少包括：第二像素电路的多个晶体管的栅极(例如包括：第二像素电路的第一复位晶体管31的栅极、阈值补偿晶体管32的栅极、驱动晶体管33的栅极、数据写入晶体管34的栅极、第一发光控制晶体管35的栅极、第二发光控制晶体管36的栅极、第二复位晶体管37的栅极)、第二像素电路的存储电容38的第一极板381、多条扫描线(例如GL(n)和GL(n+1))、多条第一复位控制线(例如，RST1(n)和RST1(n+1))、多条发光控制线(例如EML(n) 和EML(n+1))。其中，本行第二像素电路的第一复位晶体管31的栅极、上一行第二像素电路的第二复位晶体管37的栅极以及第一复位控制线RST1(n)可以为一体结构。本行第二像素电路的阈值补偿晶体管32的栅极、数据写入晶体管34的栅极以及扫描线GL(n)可以为一体结构。第二像素电路的驱动晶体管33的栅极和存储电容38的第一极板381可以为一体结构。本行第二像素电路的第一发光控制晶体管35的栅极、第二发光控制晶体管36的栅极以及发光控制线EML(n)可以为一体结构。
在一些示例中，如图13C所示，在第一显示区和第二显示区的交界处，第一复位控制线RST1(n)与第一像素电路的第一复位晶体管21的栅极211电连接，例如可以为一体结构。发光控制线EML(n)与第一像素电路的第一发光控制晶体管25的栅极251电连接，例如可以为一体结构。扫描线GL(n)的第三子信号线L13与第一像素电路的数据写入晶体管24的栅极241电连接，例如可以为一体结构。扫描线GL(n)的第三子信号线L13还可以具有第一转接端501，以便通过第一转接端501与第二子信号线L12电连接。第一转接端501可以位于第一像素电路的存储电容28的第一极板281和第二像素电路的存储电容38的第一极板381之间。
在一些示例中，形成第一导电层后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成多个晶体管的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即晶体管的有源层的第一区和第二区均被导体化。
(4)、形成第二导电层。在一些示例中，在形成前述结构的衬底基板上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成第二绝缘层以及设置在第二绝缘层上的第二导电层。
图14A为图8中形成第二导电层后的第一显示区的局部示意图。图14B为图10中形成第二导电层后的第二显示区的局部示意图。图14C为图11中形成第二导电层后的显示区域的局部示意图。
在一些示例中，如图14A和图14C所示，第一显示区的第二导电层可以至少包括：第一像素电路的存储电容28的第二极板282、第三金属连接线285、第四金属连接线286。存储电容28的第二极板282与第一极板281在衬底基 板的正投影存在交叠。第三金属连接线285配置为在显示岛区(如图8所示的显示岛区A1a)内传输初始信号。第四金属连接线286配置为在显示岛区之间传输初始信号。在靠近第一显示区和第二显示区的交界处的相邻显示岛区内的第三金属连接线285可以通过第四金属连接线286电连接。第三金属连接线285和第四金属连接线286可以为一体结构。
在一些示例中，如图14B和图14C所示，第二显示区的第二导电层可以至少包括：第二像素电路的存储电容38的第二极板382、屏蔽电极383、初始信号线INIT。第二像素电路的存储电容38的第二极板382与第一极板381在衬底基板的正投影可以存在交叠。屏蔽电极383在衬底基板的正投影与第二像素电路的阈值补偿晶体管32的有源层在衬底基板的正投影可以存在交叠。屏蔽电极383配置为保护阈值补偿晶体管，屏蔽其他信号对阈值补偿晶体管的干扰。初始信号线INIT可以沿第一方向X延伸，并延伸至第一显示区与第四金属连接线286在第二方向Y上相邻。
(5)、形成第三绝缘层。在一些示例中，在形成前述图案的衬底基板上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层。
图15A为图8中形成第三绝缘层后的第一显示区的局部示意图。图15B为图10中形成第三绝缘层后的第二显示区的局部示意图。图15C为图11中形成第三绝缘层后的显示区域的局部示意图。
在一些示例中，如图15A至图15C所示，显示区域的第三绝缘层可以开设有多个过孔，例如可以包括：暴露半导体层表面的第一类型过孔、暴露出第一导电层表面的第二类型过孔以及暴露出第二导电层表面的第三类型过孔。
在一些示例中，如图15A和图15C所示，第一显示区的第一类型过孔可以包括第一过孔V1至第六过孔V6，第二类型过孔可以包括：第七过孔V7至第十三过孔V13，第三类型过孔可以包括：第十四过孔V14至第十七过孔V17。
在一些示例中，如图15B和图15C所示，第二显示区的第一类型过孔可以包括：第二十过孔V20至第二十五过孔V25，第二类型过孔可以包括：第二十六过孔V26和第十八过孔V18，第三类型过孔可以包括：第二十七过孔 V27至第二十九过孔V29。
(6)、形成第三导电层。在一些示例中，在形成前述图案的衬底基板上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第三绝缘层上形成第三导电层。
图16A为图8中形成第三导电层后的第一显示区的局部示意图。图16B为图10中形成第三导电层后的第二显示区的局部示意图。图16C为图11中形成第三导电层后的显示区域的局部示意图。
在一些示例中，如图16A和图16C所示，第一显示区的第三导电层可以至少包括：多个像素电极(例如包括第一像素电极291至第五像素电极295)、多个转接电极(例如包括第一转接电极401至第十转接电极410)、第六金属连接线288。
在一些示例中，如图12A至图16C所示，第一像素电极291可以通过第一过孔V1与第一像素电路的第一复位晶体管的第一有源层210的第一区电连接，还可以通过第十五过孔V15与第三金属连接线285电连接。第二像素电极292可以通过第二过孔V2与阈值补偿晶体管的第二有源层220的第一区电连接，还可以通过第十过孔V10与驱动晶体管的栅极231电连接。第三像素电极293可以通过第四过孔V4与第一发光控制晶体管的第五有源层250的第一区电连接，还可以通过第十六过孔V16与存储电容28的第二极板282电连接。第四像素电极294可以通过第五过孔V5与第二发光控制晶体管的第六有源层260的第二区电连接，还可以通过第六过孔V6与第二复位晶体管的第七有源层270的第二区电连接。第五像素电极295可以通过第三过孔V3与数据写入晶体管的第四有源层240的第一区电连接。
在一些示例中，如图12A至图16C所示，第一转接电极401可以通过第十四过孔V14与第三金属连接线285电连接。第二转接电极402可以通过第八过孔V8与第一复位晶体管的栅极211的一端电连接。第三转接电极403可以通过第七过孔V7与第一复位晶体管的栅极211的另一端电连接。第四转接电极404可以通过第九过孔V9与数据写入晶体管的栅极241电连接。第五转接电极405可以通过第十一过孔V11与第二复位晶体管的栅极271电连接。第六转接电极406可以通过第十二过孔V12与第一发光控制晶体管的 栅极251电连接。第七转接电极407可以通过第十三过孔V13与第二发光控制晶体管的栅极261电连接。第九转接电极409可以通过第十七过孔V17与初始信号线INIT1电连接。第十转接电极410可以通过一个第十四过孔V14与靠近第一显示区和第二显示区边界的第三金属连接线285的一端电连接。
在一些示例中，如图12A至图16C所示，第六金属连接线288配置为在显示岛区之间传输扫描信号。第六金属连接线288的一端与第一像素电路的第二复位晶体管27的栅极271电连接。在靠近第一显示区和第二显示区的交界处的相邻显示岛区内的第二复位晶体管的栅极和数据写入晶体管的栅极可以通过第六金属连接线288电连接。
在一些示例中，如图16B和图16C所示，第二显示区的第三导电层可以至少包括：数据线DL、第一电源线PL1、多个像素电极(例如包括第六像素电极296、第七像素电极297和第八像素电极298)、第五金属连接线287。数据线DL和第一电源线PL1可以均沿第二方向Y延伸。与同一列第二像素电路电连接的数据线DL和第一电源线PL1在第一方向X上相邻。
在一些示例中，如图12A至图16C所示，第六像素电极296可以通过第二十一过孔V21与第二像素电路的第一复位晶体管的第一有源层310的第一区电连接，还可以通过第二十七过孔V27与一条初始信号线INIT电连接。第六像素电极296还可以通过第二十过孔V20与第二复位晶体管的第七有源层370的第一区电连接，还可以通过第十九过孔V19与另一条初始信号线INIT电连接。本示例的第六像素电极296可以沿第二方向Y延伸，从而实现初始信号沿第二方向Y的传输。本示例的第六像素电极296和初始信号线INIT可以连接形成传输初始信号的网状结构，从而确保初始信号的均一性。
在一些示例中，如图12A至图16C所示，第七像素电极297可以通过第二十二过孔V22与第二像素电路的阈值补偿晶体管的第二有源层320的第一区电连接，还可以通过第二十六过孔V26与驱动晶体管33的栅极电连接。第八像素电极298可以通过第二十五过孔V25与第二发光控制晶体管36的第六有源层360的第二区电连接。
在一些示例中，如图12A至图16C所示，数据线DL可以通过第二十三过孔V23与数据写入晶体管34的第四有源层340的第一区电连接。第一电 源线PL1可以通过第二十八过孔V28与屏蔽电极383电连接，还可以通过竖排设置的两个第二十九过孔V29与存储电容38的第二极板382电连接，还可以通过第二十四过孔V24与第一发光控制晶体管35的第五有源层350的第一区电连接。
在一些示例中，如图16C所示，第五金属连接线287可以通过第十八过孔V18与扫描线GL(n)的第三子信号线L13的第一转接端501电连接。第五金属连接线287可以沿第二方向Y延伸，并与下一行像素电路电连接的第一复位控制线RST1(n+1)电连接。
(7)、形成第四绝缘层。在一些示例中，在形成前述图案的衬底基板上涂覆第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成第四绝缘层。
图17A为图8中形成第四绝缘层后的第一显示区的局部示意图。图17B为图11中形成第四绝缘层后的显示区域的局部示意图。
在一些示例中，如图17A和图17B所示，显示区域的第四绝缘层可以在第一显示区开设有多个过孔，例如可以包括暴露第三导电层表面的第四类型过孔。第一显示区的第四类型过孔可以包括：第三十一过孔V31至第四十二过孔V42。
(8)、形成透明导电层。在一些示例中，在形成前述图案的衬底基板上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，在第一显示区形成透明导电层。
图18A为图8中形成透明导电层后的第一显示区的局部示意图。图18B为图11中形成透明导电层后的显示区域的局部示意图。
在一些示例中，如图18A和图18B所示，第一显示区的透明导电层可以至少包括：数据连接线45、第一电源转接线419、第二电源转接线420、以及多条转接线(例如第一转接线411至第八转接线418)以及第一连接电极421。
在一些示例中，如图16A至图18B所示，数据连接线45可以沿第二方向Y延伸。数据连接线45可以通过第三十六过孔V36与第五像素电极295 电连接，从而实现数据连接线45与第一像素电路的数据写入晶体管24的第一极电连接。第一电源转接线419可以沿第二方向Y延伸，第一电源转接线419的一端可以通过第三十三过孔V33与第八转接电极408电连接，另一端可以与另一个第一像素电路的第三像素电极293电连接。第二电源转接线420可以沿第二方向Y延伸，第二电源转接线420的一端可以通过第四十一过孔V41与第三像素电极293电连接，另一端可以与另一个第一像素电路的第八转接电极408电连接。在第一显示区内，利用第一电源转接线419和第二电源转接线420可以沿第二方向Y传输第一电压信号。
在一些示例中，如图16A至图18B所示，第一转接线411的一端可以通过第三十一过孔V31与一个显示岛区内的第一转接电极401电连接，另一端可以延伸至另一显示岛区。第二转接线412的一端可以通过第三十二过孔V32与第一像素电极291电连接，另一端可以延伸至另一显示岛区。本示例中，在第一显示区内，利用第一转接线411、第一转接电极401、第三金属连接线285、第一像素电极291和第二转接线412可以实现初始信号的传输。
第三转接线413的一端可以通过第三十四过孔V34与一个显示岛区内的第三转接电极403电连接，另一端可以延伸至另一显示岛区。第四转接线414的一端可以通过第三十五过孔V35与第二转接电极402电连接，另一端可以延伸至另一显示岛区。在第一显示区内，利用第三转接线413、第三转接电极403、第一复位晶体管的栅极211、第二转接电极402和第四转接线414可以实现第一复位控制信号的传输。
第五转接线415的一端可以通过第三十七过孔V37与一个显示岛区内的第四转接电极404电连接，另一端可以延伸至另一显示岛区。第六转接线416的一端可以通过第三十九过孔V39与第五转接电极405电连接，另一端可以延伸至另一显示岛区。在第一显示区内，利用第五转接线415、第四转接电极404、数据写入晶体管的栅极241、阈值补偿晶体管的栅极221、第二复位晶体管的栅极271、第五转接电极405和第六转接线416可以实现扫描信号的传输。
第七转接线417的一端可以通过第三十八过孔V38与一个显示岛区内的第六转接电极406电连接，另一端可以延伸至另一显示岛区。第八转接线418 的一端可以通过第四十过孔V40与第七转接电极407电连接，另一端可以延伸至另一显示岛区。在第一显示区内，利用第七转接线417、第六转接电极406、第一发光控制晶体管的栅极251、第二发光控制晶体管的栅极261、第七转接电极407和第八转接线418可以实现发光控制信号的传输。
在一些示例中，如图18B所示，第一连接电极421可以通过第四十二过孔V42与第九转接电极409电连接，还可以通过一个第三十二过孔V32与第一像素电路的第一像素电极291电连接。在靠近第一显示区和第二显示区的交界处，利用初始信号线INIT、第九转接电极409、第一连接电极421、第一像素电极291传输初始信号。
(9)、形成第五绝缘层。在一些示例中，在形成前述图案的衬底基板上涂覆第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化，形成第五绝缘层。
图19A为图8中形成第五绝缘层后的第一显示区的局部示意图。图19B为图10中形成第五绝缘层后的第二显示区的局部示意图。图19C为图11中形成第五绝缘层后的显示区域的局部示意图。
在一些示例中，如图19A至图19C所示，显示区域的第五绝缘层可以开设有多个过孔，例如可以包括暴露第三导电层表面的第五类型过孔、以及暴露出透明导电层表面的第六类型过孔。
在一些示例中，如图19A和图19C所示，第一显示区的第六类型过孔可以包括：第五十一过孔V51和第五十二过孔V52，第五类型过孔可以包括第五十三过孔V53。
在一些示例中，如图19B和图19C所示，第二显示区的第五类型过孔可以包括第五十四过孔V54至第五十六过孔V56。
(10)、形成第四导电层。在一些示例中，在形成前述图案的衬底基板上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，在第一显示区形成第四导电层。
图20A为图8中形成第四导电层后的第一显示区的局部示意图。图20B为图10中形成第四导电层后的第二显示区的局部示意图。图11为形成第四 导电层后的显示区域的局部示意图。
在一些示例中，如图20A和图11所示，第一显示区的第四导电层可以至少包括：电源连接电极421、第一阳极连接电极422。电源连接电极421的一端可以通过第五十一过孔V51与第一电源转接线419电连接，另一端可以通过第五十二过孔V52与第二电源转接线420电连接。在第一显示区内，利用第一电源转接线419、电源连接电极421、第二电源转接线420实现沿第二方向Y的第一电压信号的传输。第一阳极连接电极422可以通过第五十三过孔V53与第四像素电极294电连接，从而实现与第二发光控制晶体管的第六有源层260的第二极电连接。
在一些示例中，如图20B和图11所示，第二显示区的第四导电层可以至少包括：第二阳极连接电极423、第二子信号线L12、辅助走线L3。第二阳极连接电极423可以通过第五十四过孔V54与第八像素电极298电连接。辅助走线L3可以包括沿第一方向X延伸的第一辅助段L31和沿第二方向Y延伸的第二辅助段L32。第二辅助段L32可以通过第五十五过孔V55与第一电源线PL1电连接。第一辅助段L31的一端与第二辅助段L32连接，另一端独立设置。本示例中，辅助走线L3与第一电源线PL1电连接，可以传输第一电压信号，有利于改善显示基板的显示均一性。
如图20B和图11所示，第二子信号线L12可以包括：第一连接段L121、沿第一方向X延伸的第二连接段L121、沿第二方向Y延伸的第三连接段L123、以及沿第一方向X延伸的第四连接段L124。第四连接段L124的一端与第三连接段L123连接，另一端独立设置。一条第二连接段L122的一端与第一连接段L121连接，另一端可以通过第五十六过孔V56与第五金属连接线287电连接。在本示例中，第二子信号线L12可以通过第五金属连接线287与第三子信号线L13电连接。然而，本实施例对此并不限定。在另一些示例中，第二子信号线L12可以直接与第三子信号线L13的第一连接端501电连接。
在一些示例中，第二子信号线L12和辅助走线L3在衬底基板的正投影与第二像素电路的第一节点(即驱动晶体管的栅极、阈值补偿晶体管的第一极、存储电容的第一极板的连接点)在衬底基板的正投影可以没有交叠。通过设置第二子信号线和辅助走线避开第二像素电路的第一节点，可以降低第 一信号(例如扫描信号)对第一节点N1的串扰。
本示例中的扫描线GL(n)的第三子信号线L13可以在第一显示区和第二显示区的交界处与第二子信号线L12电连接，并与第一显示区内的第一像素电路的数据写入晶体管的栅极、阈值补偿晶体管的栅极和第二复位晶体管的栅极电连接。在第一显示区内，相邻显示岛区内的第一像素电路的数据写入晶体管的栅极和第二复位晶体管的栅极可以通过第六转接线416电连接，邻近第一显示区边界的相邻显示岛区内的第一像素电路的数据写入晶体管的栅极和第二复位晶体管的栅极可以通过位于第三导电层的第六金属连接线288电连接。在本示例中，扫描线的第一子信号线可以包括多个第六转接线416，实现在第一显示区内扫描信号的传输。扫描线的第三子信号线可以通过第六金属连接线288、第一像素电路的数据写入晶体管的栅极、阈值补偿晶体管的栅极和第二复位晶体管的栅极与第一子信号线电连接，第三子信号线可以通过第五金属连接线287与第二子信号线电连接。
图22为本公开至少一实施例的第一显示区和第二显示区的交界处的走线示意图。在一些示例中，如图22所示，扫描线GL(n)的第四子信号线L14可以在第一显示区A1和第二显示区A2的交界处与第二子信号线L12电连接，并与第一显示区A1内的第一像素电路的数据写入晶体管的栅极241、阈值补偿晶体管的栅极221和第二复位晶体管的栅极271电连接。例如，第四子信号线L14与第一显示区A1内靠近第一显示区A1和第二显示区A2的交界处的第一像素电路的数据写入晶体管的栅极241、阈值补偿晶体管的栅极221和第二复位晶体管的栅极271可以为一体结构。扫描线GL(n)的第四子信号线L14可以通过第一像素电路的数据写入晶体管的栅极241、阈值补偿晶体管的栅极221和第二复位晶体管的栅极271与第一子信号线电连接，第四子信号线L14还可以通过第五金属连接线287与第二子信号线L12电连接。关于第一显示区和第二显示区的交界处的其他结构可以参照前述实施例的说明，故于此不再赘述。本示例的第四子信号线和第三子信号线与第一子信号线和第二子信号线的连接方式有利于像素电路的排布，可以节省空间，并方便走线排布。
(11)、依次形成第六绝缘层、发光结构层和封装结构层。
在一些示例中，在形成前述图案的衬底基板上涂覆第六绝缘薄膜，通过图案化工艺对第六绝缘薄膜进行图案化，形成第六绝缘层。在一些示例中，如图8所示，第一显示区的第六绝缘层可以开设有多个过孔，例如第六十一过孔V61。如图10所示，第二显示区的第六绝缘层可以开设有多个过孔，例如第六十二过孔V62。
在一些示例中，在形成前述图案的衬底基板上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。
在一些示例中，如图8和图10所示，第一显示区的阳极层可以包括：第一发光元件12的阳极120，第二显示区的阳极层可以包括：第二发光元件14的阳极140。第一发光元件12的阳极120可以通过第六十一过孔V61与第一阳极连接电极422电连接。第二发光元件14的阳极140可以通过第六十二过孔V62与第二阳极连接电极423电连接。
图21为图10中阳极层和第四导电层的示意图。在一些示例中，如图10和图21所示，辅助走线L3和第二子信号线L12在衬底基板的正投影与第二发光元件14的阳极140在衬底基板的正投影可以没有交叠。第二子信号线L12和辅助走线L3可以沿着相邻第二发光元件的阳极140之间的间隙延伸。
随后，涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层。像素定义层可以形成有暴露出阳极层的多个像素开口。在一些示例中，如图8所示，第一显示区的像素定义层可以形成暴露出第一发光元件12的阳极120的部分表面的第一像素开口OP1。如图10所示，第二显示区的像素定义层可以形成暴露出第二发光元件14的阳极140的部分表面的第二像素开口OP2。
在一些示例中，在前述形成的像素开口内形成有机发光层，有机发光层与阳极层连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极图案，阴极与有机发光层连接。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例中，第一导电层202、第二导电层203、第三导电层204、第四导电层206可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。 透明导电层205可以采用透明导电材料，例如氧化铟锡(ITO)等。第一绝缘层101、第二绝缘层102、第三绝缘层103可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第四绝缘层104、第五绝缘层105和第六绝缘层106可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层304可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层301可以采用金属等反射材料，阴极层303可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在另一些示例中，第一信号线还可以包括：发光控制线和第一复位控制线。关于发光控制线和第一复位控制线的绕线方式、以及子信号线之间的连接方式与扫描线的绕线方式和连接方式类似，故于此不再赘述。
本示例提供的显示基板，通过设置扫描线包括并联且电连接的第一子信号线和第二子信号线，可以降低第一显示区的扫描信号的负载，有利于改善第一显示区左右两侧的横向显示不良(Mura)，可以提高显示基板的显示均一性。
图23为本公开至少一实施例的显示基板的第二信号线的局部示意图。在一些示例中，如图23所示，显示基板可以包括多条第二信号线L2。第二信号线L2可以在第二方向Y上给第一显示区A1内的第二像素电路提供第二信号。例如，第二信号线L2可以包括以下至少之一：数据线、第一电源线。
在一些示例中，如图23所示，第二信号线L2可以包括：第五子信号线L21、第六子信号线L22、第七子信号线L23和第八子信号线L24。第七子信号线L23和第八子信号线L24可以均沿第二方向Y延伸，并位于第一显示区A1沿第二方向Y相对两侧的第二显示区内。第五子信号线L21可以位于第一显示区A1内，并沿第二方向Y延伸。第五子信号线L21的两端可以分别 与第七子信号线L23和第八子信号线L24电连接。第六子信号线L22可以位于第二显示区。第六子信号线L22可以绕过第一显示区A1，且第六子信号线L22的两端可以分别与第七子信号线L23和第八子信号线L24电连接。例如，第六子信号线L22可以沿第一方向X延伸，再沿第二方向Y延伸，再沿第一方向X延伸。第二信号线L2的第五子信号线L21和第六子信号线L22并联且电连接，并与第七子信号线L23和第八子信号线L24串联连接。
以第二信号线L2为数据线为例，前述实施例中的数据连接线45可以为位于第一显示区内的第五子信号线L21，在第二显示区还可以包括与数据连接线45并联且电连接的第六子信号线L22。第五子信号线L21可以位于透明导电层，第六子信号线L22可以为第四导电层。然而，本实施例对此并不限定。
在一些示例中，如图23所示，多条第二信号线L2可以被分为两组。例如，第一组第二信号线和第二组第二信号线可以关于第一显示区A1沿第一方向X的第二中线O2大致对称。第一组第二信号线内的第二信号线的数目和第二组第二信号线内的第二信号线的数目可以大致相同。第一组第二信号线内的第二信号线L2的第六子信号线L22可以位于第一显示区A1沿第一方向X一侧的第二显示区内，第二组第二信号线内的第二信号线L2的第六子信号线L22可以位于第一显示区A1沿第一方向X另一侧的第二显示区内。例如，第一组第二信号线的第六子信号线L22可以从第一显示区A1的左侧绕过第一显示区A1，第二组第二信号线的第六子信号线L22可以从第一显示区A1的右侧绕过第一显示区A1。如此一来，可以避免走线聚集，影响显示效果。
在一些示例中，如图23所示，在第一方向X上靠近第一显示区A1边缘的第二信号线L2的第六子信号线L22，可以位于靠近第一显示区A1沿第一方向X的第二中线O2的第二信号线L2的第六子信号线L22靠近第一显示区A1的一侧。换言之，靠近第一显示区A1沿第一方向X的第二中线O2的第二信号线L2的第六子信号线L22沿第一方向X的长度，可以大于靠近第一显示区A1边缘的第二信号线L2的第六子信号线L22沿第一方向X的长度。如此一来，可以减少走线交叠，有利于合理排布第六子信号线。
在一些示例中，如图23所示，第二信号可以通过第五子信号线L21在第一显示区A1内进行传输，还可以通过第六子信号线L22在第二显示区内进行传输。本示例通过设置并联且电连接的第五子信号线L21和第六子信号线L22进行第二信号的传输，可以降低第一显示区A1的第二信号的传输负载，从而改善第一显示区A1上下两侧的第二显示区存在的纵向显示不良。
关于本实施例的其他说明可以参照前述实施例的描述，故于此不再赘述。
图24为本公开至少一实施例的显示基板的第一信号线和第二信号线的局部示意图。在一些示例中，如图24所示，显示基板可以包括多条第一信号线L1和多条第二信号线L2。第一信号线L1可以包括并联且电连接的第一子信号线L11和第二子信号线L12，第二信号线L2可以包括并联且电连接的第五子信号线L21和第六子信号线L22。第一子信号线L11和第五子信号线L21可以位于第一显示区A1，第二子信号线L12和第六子信号线L22可以位于第二显示区A2。
在一些示例中，第一子信号线L11和第五子信号线L21可以位于透明导电层。第二子信号线L12和第六子信号线L22可以位于同一膜层，例如，可以位于第四导电层，从而节省制备工艺。在另一些示例中，第二子信号线L12和第六子信号线L22可以位于不同膜层，比如，第二子信号线L12可以位于第四导电层，第六子信号线L22可以位于第四导电层远离衬底基板一侧的第五导电层，从而避免走线交叉。
在一些示例中，显示基板还可以包括与第二子信号线同层设置的第一辅助走线、以及与第六子信号线同层设置的第二辅助走线。第一辅助走线的形态可以与第二子信号线的形态类似，第二辅助走线的形态可以与第六子信号线的形态类似，从而实现显示区域的布线和显示均一性。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图25为本公开至少一实施例的显示装置的示意图。如图25所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的显示结构层的出光侧的感光传感器92。感光传感器92在显示基板91上的正投 影与第一显示区A1存在交叠。
在一些示例中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和位于所述第一显示区至少一侧的第二显示区；
    多个第一像素电路和多个第一发光元件，位于所述第一显示区；所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件电连接，配置为驱动所述至少一个第一发光元件发光；
    至少一条第一信号线，配置为在第一方向上给所述多个第一像素电路提供第一信号；所述至少一条第一信号线包括并联且电连接的第一子信号线和第二子信号线，所述第一子信号线位于所述第一显示区，所述第二子信号线位于所述第二显示区。
  2. 根据权利要求1所述的显示基板，其中，所述第一子信号线采用透明导电材料，所述第二子信号线采用金属材料。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二子信号线位于所述第一子信号线远离所述衬底基板的一侧。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述至少一条第一信号线还包括：位于所述第二显示区的第三子信号线和第四子信号线，所述第三子信号线和所述第四子信号线位于所述第一显示区沿所述第一方向的相对两侧的第二显示区内；
    所述第一子信号线的两端分别与所述第三子信号线和所述第四子信号线电连接，所述第二子信号线的两端分别与所述第三子信号线和所述第四子信号线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一子信号线的至少一端通过至少一个第一像素电路的晶体管的栅极与第三子信号线或第四子信号线电连接。
  6. 根据权利要求1至5中任一项所述的显示基板，其中，所述显示基板包括多条第一信号线，所述多条第一信号线被分为两组，第一组第一信号线的第二子信号线位于所述第一显示区沿第二方向一侧的第二显示区内，第二 组第一信号线的第二子信号线位于所述第一显示区沿所述第二方向另一侧的第二显示区内，所述第二方向与所述第一方向交叉。
  7. 根据权利要求1至6中任一项所述的显示基板，还包括：位于所述第二显示区的多个第二像素电路和多个第二发光元件，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，配置为驱动所述至少一个第二发光元件发光；
    所述至少一条第一信号线的第二子信号线在所述衬底基板的正投影与所述第二发光元件的阳极在所述衬底基板的正投影没有交叠。
  8. 根据权利要求7所述的显示基板，其中，所述第二像素电路至少包括：驱动晶体管、阈值补偿晶体管和存储电容；所述驱动晶体管的栅极与所述存储电容的第一极板和所述阈值补偿晶体管的第一极电连接；
    所述至少一条第一信号线的第二子信号线在所述衬底基板的正投影与所述第二像素电路的驱动晶体管的栅极、所述阈值补偿晶体管的第一极和所述存储电容的第一极板的连接位置在所述衬底基板的正投影没有交叠。
  9. 根据权利要求7或8所述的显示基板，其中，所述第二子信号线包括：第一连接段、第二连接段、第三连接段和第四连接段；
    所述第二连接段为沿所述第一方向延伸的直线段，所述第二连接段与所述第一连接段电连接，所述第一连接段配置为至少部分包围一个第二发光元件的阳极；所述第三连接段为沿第二方向延伸的折线，所述第四连接段与所述第三连接段连接，所述第四连接段为沿所述第一方向延伸的直线段；所述第二方向与所述第一方向交叉。
  10. 根据权利要求8所述的显示基板，其中，所述第二显示区还设置有与所述第二子信号线同层设置的多条辅助走线，所述多条辅助走线在所述衬底基板的正投影与所述第二发光元件的阳极、以及所述第二像素电路的所述驱动晶体管的栅极、所述阈值补偿晶体管的第一极和所述存储电容的第一极板的连接位置在所述衬底基板的正投影没有交叠。
  11. 根据权利要求10所述的显示基板，其中，所述辅助走线被配置为与第一电源线电连接。
  12. 根据权利要求10或11所述的显示基板，其中，所述多条辅助走线中的至少一条包括：相互连接的第一辅助段和第二辅助段，所述第一辅助段为沿所述第一方向延伸的直线段，所述第二辅助段为沿第二方向延伸的折线，所述第二方向与所述第一方向交叉。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述至少一条第一信号线包括以下至少之一：扫描线、第一复位控制线、发光控制线。
  14. 根据权利要求1至13中任一项所述的显示基板，还包括：至少一条第二信号线，配置为在第二方向上给所述多个第一像素电路提供第二信号；所述至少一条第二信号线包括并联且电连接的第五子信号线和第六子信号线，所述第五子信号线位于所述第一显示区，所述第六子信号线位于所述第二显示区；所述第一方向与所述第二方向交叉。
  15. 根据权利要求14所述的显示基板，其中，所述第一方向垂直于所述第二方向。
  16. 根据权利要求14或15所述的显示基板，其中，所述至少一条第二信号线还包括：位于所述第二显示区的第七子信号线和第八子信号线，所述第七子信号线和所述第八子信号线位于所述第一显示区沿所述第二方向的相对两侧的第二显示区内；所述第五子信号线的两端分别与所述第七子信号线和所述第八子信号线电连接，所述第六子信号线的两端分别与所述第七子信号线和所述第八子信号线电连接。
  17. 根据权利要求14至16中任一项所述的显示基板，其中，所述第五子信号线与所述第一子信号线同层设置，所述第六子信号线与所述第二子信号线位于不同膜层。
  18. 根据权利要求1至17中任一项所述的显示基板，其中，所述第一显示区的像素密度小于或等于所述第二显示区的像素密度。
  19. 根据权利要求1至18中任一项所述的显示基板，其中，所述第一显示区的光透过率大于所述第二显示区的光透过率。
  20. 一种显示装置，包括如权利要求1至19中任一项所述的显示基板。
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