WO2022266896A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022266896A1
WO2022266896A1 PCT/CN2021/101880 CN2021101880W WO2022266896A1 WO 2022266896 A1 WO2022266896 A1 WO 2022266896A1 CN 2021101880 W CN2021101880 W CN 2021101880W WO 2022266896 A1 WO2022266896 A1 WO 2022266896A1
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WIPO (PCT)
Prior art keywords
sub
line
display area
data line
data
Prior art date
Application number
PCT/CN2021/101880
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English (en)
French (fr)
Inventor
蔡建畅
于池
石博
程羽雕
王智
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/780,999 priority Critical patent/US20240164156A1/en
Priority to CN202180001603.1A priority patent/CN115812347A/zh
Priority to PCT/CN2021/101880 priority patent/WO2022266896A1/zh
Publication of WO2022266896A1 publication Critical patent/WO2022266896A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • This article relates to but is not limited to the field of display technology, especially a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of a display device.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of pixel circuits, a plurality of first light emitting elements, and at least one first data line.
  • the base substrate includes a first display area and a second display area, the first display area at least partially surrounds the second display area, and the first display area includes: a first sub-display area and a second sub-display area on opposite sides of the area, and a third sub-display area located on at least one side of the second display area along a second direction, the first direction crossing the second direction .
  • a plurality of pixel circuits and a plurality of first light-emitting elements are located in the first display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixel circuits are distributed in Between the plurality of first pixel circuits; at least one pixel circuit in the plurality of first pixel circuits is connected to at least one light emitting element in the plurality of first light emitting elements.
  • At least one first data line is located in the first display area, and the first data line includes: a first sub-data line, a second sub-data line and a third sub-data line; the third sub-data line and the The first sub-data line is connected to the second sub-data line.
  • the first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area
  • the second sub-data line is located in the second sub-display area and is connected to the second sub-display area.
  • Pixel circuits in the sub-display area are connected
  • the third sub-data line is located in the third sub-display area and connected to at least one second pixel circuit in the third sub-display area.
  • both the first sub-data line and the second sub-data line extend along the first direction.
  • the third sub-data line at least includes: a first line segment and a second line segment, the first line segment extends along the second direction, and the second line segment extends along the first line segment. Extend in one direction. One end of the first line segment extends to the first sub-display area and is connected to the first sub-data line, and the other end of the first line segment is connected to the second line segment. The second line segment is connected to at least one second pixel circuit in the third sub-display area.
  • the first sub-data line, the second sub-data line, and the second segment of the third sub-data line are of the same layer structure, and the first segment of the third sub-data line is the same as The second line segment is a heterogeneous structure.
  • the first sub-data line and the second sub-data line have the same layer structure, and the third sub-data line and the first sub-data line have a different-layer structure.
  • the base substrate further includes: a frame area, and the frame area is located at the periphery of the first display area and the second display area.
  • the frame area is provided with at least one data connection line, and the data connection line is connected between the third sub-data line and the second sub-data line.
  • the data connection lines at least include: a first sub-data connection line, a second sub-data connection line and a third sub-data connection line.
  • the second sub-data connection line is connected between the first sub-data connection line and the third sub-data connection line
  • the first sub-data connection line is connected to the third sub-data line
  • the third sub-data connection line The connection line is connected with the second sub-data line.
  • the first and third sub-data connection lines extend along a first direction
  • the second sub-data connection lines extend along a second direction
  • the first sub-data connection line and the third sub-data connection line have a same-layer structure, and the first sub-data connection line and the second sub-data connection line have a different-layer structure.
  • the second sub-data connection line has the same layer structure as the first sub-data line and the second sub-data line.
  • the display substrate further includes: a plurality of second light emitting elements located in the second display area; at least one pixel circuit in the plurality of second pixel circuits is connected to the plurality of second light emitting elements At least one light-emitting element is connected by a conductive wire.
  • the display substrate at least includes: a semiconductor layer disposed on the base substrate, a first conductive layer, a second conductive layer, and a third conductive layer and the fourth conductive layer.
  • the semiconductor layer at least includes: an active layer of a plurality of transistors of the pixel circuit.
  • the first conductive layer at least includes: gates of multiple transistors of the pixel circuit and a first electrode of a storage capacitor.
  • the second conductive layer at least includes: a second electrode of a storage capacitor of the pixel circuit.
  • the third conductive layer at least includes: a first power line.
  • the fourth conductive layer at least includes: a first connection electrode connecting the pixel circuit and the light emitting element.
  • the second segment of the first sub-data line, the second sub-data line, and the third sub-data line is located in the third conductive layer, and the first segment of the third sub-data line Located in the fourth conductive layer; or, the first sub-data line and the second sub-data line are located in the third conductive layer, and the third sub-data line is located in the fourth conductive layer.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a plurality of pixel circuits, a plurality of first light emitting elements, and at least one first data line in a first display region of the base substrate.
  • the first display area at least partially surrounds the second display area; the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along the first direction; The third sub-display area located on at least one side of the second display area in the second direction; the first direction intersects with the second direction.
  • the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixel circuits are distributed among the plurality of first pixel circuits; at least one pixel in the plurality of first pixel circuits
  • the circuit is connected to at least one light emitting element among the plurality of first light emitting elements.
  • the first data line includes: a first sub-data line, a second sub-data line and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line.
  • the first sub-data line is located in the first sub-display area and is connected to the pixel circuit of the first sub-display area
  • the second sub-data line is located in the second sub-display area and is connected to the second sub-display area.
  • Pixel circuits in the sub-display area are connected
  • the third sub-data line is located in the third sub-display area and connected to at least one second pixel circuit in the third sub-display area.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure
  • 3A to 3C are partial structural schematic diagrams of the first display area of at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 6A is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 6B is a working timing diagram of the pixel circuit shown in FIG. 6A;
  • FIG. 7A is a schematic plan view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 7B is a schematic partial cross-sectional view along the direction of P-P' in Figure 7A;
  • FIG. 7C is a schematic diagram of a pixel circuit after forming a semiconductor layer according to at least one embodiment of the present disclosure
  • 7D is a schematic diagram of a pixel circuit after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 7E is a schematic diagram of a pixel circuit after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 7F is a schematic diagram of a pixel circuit after forming a third conductive layer according to at least one embodiment of the present disclosure.
  • 7G is a schematic diagram of a pixel circuit after forming a fourth conductive layer according to at least one embodiment of the present disclosure
  • FIG. 8A is a schematic diagram of connection positions of the first sub-data line and the third sub-data line according to at least one embodiment of the present disclosure
  • 8B is a schematic diagram of the connection position of the first line segment and the second line segment of the third sub-data line according to at least one embodiment of the present disclosure
  • FIG. 8C is a schematic diagram of the cut-off position of the second line segment of the third sub-data line according to at least one embodiment of the present disclosure
  • FIG. 8D is a schematic diagram of connection between a third sub-data line and a data connection line according to at least one embodiment of the present disclosure
  • 8E is a schematic diagram of connection between the second sub-data line and the data connection line in at least one embodiment of the present disclosure
  • FIG. 9 is another schematic diagram of the arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic diagram of the arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • connection includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of pixel circuits, a plurality of first light emitting elements, and at least one first data line.
  • the base substrate includes a first display area and a second display area.
  • the first display area at least partially surrounds the second display area.
  • the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along the first direction, and a third sub-display area located on at least one side of the second display area along the second direction display area.
  • the first direction intersects the second direction.
  • a plurality of pixel circuits and a plurality of first light emitting elements are located in the first display area.
  • the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixel circuits are distributed among the plurality of first pixel circuits. At least one pixel circuit among the plurality of first pixel circuits is connected to at least one light emitting element among the plurality of first light emitting elements. At least one first data line is located in the first display area. The first data line includes: a first sub-data line, a second sub-data line and a third sub-data line. The third sub-data line is connected to the first sub-data line and the second sub-data line.
  • the first sub-data line is located in the first sub-display area and is connected to the pixel circuit in the first sub-display area
  • the second sub-data line is located in the second sub-display area and is connected to the pixel circuit in the second sub-display area
  • the third sub-data line is connected to the pixel circuit in the second sub-display area.
  • the wire is located in the third sub-display area and connected to at least one second pixel circuit in the third sub-display area.
  • the multiple second pixel circuits are distributed among the multiple first pixel circuits, which may include: in the second direction, multiple first pixel circuits are arranged between two adjacent second pixel circuits .
  • a plurality of second pixel circuits may be sequentially arranged along the first direction.
  • this embodiment does not limit it.
  • the first sub-display area is provided with a plurality of first pixel circuits
  • the second sub-display area is provided with a plurality of first pixel circuits
  • the third sub-display area is provided with a plurality of first pixel circuits and a plurality of second pixels circuit
  • the first sub-data line of the first data line is connected to at least one first pixel circuit in the first sub-display area
  • the second sub-data line is connected to at least one first pixel circuit in the second sub-display area
  • the third sub-data line is connected to at least one first pixel circuit in the second sub-display area.
  • the data line is connected to at least one second pixel circuit in the third sub-display area.
  • the first sub-display area is provided with a plurality of first pixel circuits
  • the second sub-display area is provided with a plurality of first pixel circuits and a plurality of second pixel circuits
  • the third sub-display area is provided with a plurality of first pixel circuits.
  • a pixel circuit and a plurality of second pixel circuits, the first sub-data line of the first data line is connected to at least one first pixel circuit in the first sub-display area, and the second sub-data line is connected to at least one first pixel circuit in the second sub-display area.
  • a pixel circuit or at least one second pixel circuit is connected, and the third sub-data line is connected with at least one second pixel circuit in the third sub-display area.
  • the first sub-display area is provided with multiple first pixel circuits and multiple second pixel circuits
  • the second sub-display area is provided with multiple first pixel circuits and multiple second pixel circuits
  • the third The sub-display area is provided with a plurality of first pixel circuits and a plurality of second pixel circuits
  • the first sub-data line of the first data line is connected to at least one first pixel circuit or second pixel circuit in the first sub-display area
  • the second The second sub-data line is connected to at least one first pixel circuit or the second pixel circuit in the second sub-display area
  • the third sub-data line is connected to at least one second pixel circuit in the third sub-display area.
  • this embodiment does not limit it.
  • the first direction is parallel to the sub-pixel column direction in the display area
  • the second direction is parallel to the sub-pixel row direction in the display area.
  • the first direction is perpendicular to the second direction.
  • the second display area separates the first sub-display area from the second sub-display area in the first direction
  • the first sub-display area is realized by setting the third sub-data line in the third sub-display area.
  • the connection between the first sub-data line of the first sub-data line and the second sub-data line of the second sub-display area can realize the transmission of data signals, avoid wiring in the second display area and affect the light transmittance of the second display area, thereby improving the display Effect.
  • both the first sub-data line and the second sub-data line extend along the first direction.
  • extension lines of the first sub-data line and the second sub-data line included in one first data line may overlap.
  • this embodiment does not limit it.
  • the third sub-data line at least includes: a first line segment and a second line segment, the first line segment extends along the second direction, and the second line segment extends along the first direction.
  • One end of the first line segment extends to the first sub-display area and is connected to the first sub-data line, and the other end of the first line segment is connected to the second line segment.
  • the second line segment is connected with at least one second pixel circuit in the third sub-display area.
  • this embodiment does not limit it.
  • the third sub-data line may include: a first line segment, a second line segment and a third line segment, the first line segment and the third line segment extend along the second direction, and the second line segment extends along the first direction; One end of a line segment extends to the first sub-display area and is connected to the first sub-data line, and the other end of the first line segment is connected to the second line segment in the third sub-display area; one end of the third line segment extends to the second sub-display The area is connected to the second sub-data line, and the other end of the third line segment is connected to the second line segment in the third sub-display area.
  • the first sub-data line, the second sub-data line, and the second line segment of the third sub-data line may have the same layer structure, and the first line segment and the second line segment of the third sub-data line It can be a heterogeneous structure. However, this embodiment does not limit it.
  • the first sub-data line and the second sub-data line may have the same layer structure, and the third sub-data line and the first sub-data line may have a different-layer structure.
  • the first line segment and the second line segment of the third sub-data line may have an integrated structure. However, this embodiment does not limit it.
  • the base substrate further includes: a frame area.
  • the frame area is located on the periphery of the first display area and the second display area.
  • the frame area is provided with at least one data connection line, and the data connection line is connected between the third sub-data line and the second sub-data line.
  • the connection between the third sub-data line and the second sub-data line is realized by arranging a data connection line in the frame area.
  • this embodiment does not limit it.
  • the data connection line at least includes: a first sub-data connection line, a second sub-data connection line and a third sub-data connection line.
  • the second sub-data connection line is connected between the first sub-data connection line and the third sub-data connection line
  • the first sub-data connection line is connected to the third sub-data line
  • the third sub-data connection line is connected to the second sub-data line. connect.
  • the data connection line includes a plurality of sub-data connection lines connected in sequence.
  • the first sub-data connection line and the third sub-data connection line extend along a first direction
  • the second sub-data connection lines extend along a second direction
  • the first sub-data connection line and the third sub-data connection line have the same layer structure, and the first sub-data connection line and the second sub-data connection line have a different-layer structure.
  • this embodiment does not limit it.
  • the first sub-data connection line, the second sub-data connection line and the third sub-data connection line may be of an integral structure.
  • the second sub-data connection line has the same layer structure as the first sub-data line and the second sub-data line. However, this embodiment does not limit it.
  • the display substrate further includes: a plurality of second light emitting elements located in the second display area. At least one pixel circuit in the plurality of second pixel circuits is connected to at least one light emitting element in the plurality of second light emitting elements through conductive wires.
  • the display substrate at least includes: a semiconductor layer disposed on the base substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer Floor.
  • the semiconductor layer includes at least: an active layer of a plurality of transistors of the pixel circuit.
  • the first conductive layer at least includes: gates of multiple transistors of the pixel circuit and a first electrode of the storage capacitor.
  • the second conductive layer at least includes: a second electrode of the storage capacitor.
  • the third conductive layer at least includes: a first power line.
  • the fourth conductive layer at least includes: a first connection electrode connecting the pixel circuit and the light emitting element.
  • the pixel circuit can be a 7T1C structure. However, this embodiment does not limit it.
  • the second segment of the first sub-data line, the second sub-data line, and the third sub-data line are located in the third conductive layer, and the first segment of the third sub-data line is located in the fourth conductive layer.
  • the first sub-data line and the second sub-data line are located in the third conductive layer, and the third sub-data line is located in the fourth conductive layer.
  • this embodiment does not limit it.
  • the display substrate of this embodiment will be described below through several examples.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the base substrate of the display substrate includes: a display area and a frame area R3 located around the display area.
  • the frame area R3 surrounds the display area.
  • the display area includes: a first display area R1 and a second display area R2, and the first display area R1 at least partially surrounds the second display area R2.
  • the second display region R2 shown in FIG. 1 is located in the middle of the top of the display substrate, and one side of the second display region R2 is adjacent to the frame region R3.
  • this embodiment does not limit it.
  • the second display region R2 may be located at other positions such as the upper left corner or the upper right corner of the display substrate.
  • the display area may be a rectangle, for example, a rectangle with rounded corners.
  • the second display area R2 may be circular. However, this embodiment does not limit it.
  • the second display region R2 may be in other shapes such as rectangle, ellipse or the like.
  • the first display region R1 may be a non-light-transmitting display region
  • the second display region R2 may be a light-transmitting display region. That is, the first display region R1 is opaque, and the second display region R2 is permeable.
  • the orthographic projection of hardware such as a photosensitive sensor (eg, a camera) on the display substrate may be located in the second display region R2 of the display substrate.
  • the display substrate of this example does not need to be drilled, and can make a true full screen possible under the premise of ensuring the practicability of the display substrate.
  • the first display region R1 includes: a first sub-display region R11 and a second sub-display region located on opposite sides of the second display region R2 along the first direction D1, and the third sub-display regions located on opposite sides of the second display region R2 along the second direction D2.
  • the second sub-display area includes the second sub-display first sub-area R12a and the second sub-display second sub-area R12b
  • the third sub-display area includes: the third sub-display first sub-area R13a and the third sub-display second sub-area R13a Region R13b.
  • the first sub-display area R11 is located on the lower side of the second display area R2, and the second sub-display area is located on the upper side of the second display area R2.
  • the first sub-display area R11 and the second sub-display area are separated by the second display area R2 in the first direction D2, and the second sub-display area is separated by the second display area R2 in the second direction D2, that is, the second
  • the sub-display first sub-region R12a and the second sub-display second sub-region R12b are located on opposite sides of the second display region R2 in the second direction D2.
  • this embodiment does not limit it.
  • the second sub-display first sub-region R12a and the second sub-display second sub-region R12b may be connected in the second direction D2.
  • the third sub-display first sub-region R13a is located on the left side of the second display region R2
  • the third sub-display second sub-region R13b is located on the right side of the second display region R2.
  • the third sub-display first sub-region R13a and the third sub-display second sub-region R13b are separated by the first sub-display region R11, the second display region R2 and the second sub-display region.
  • the third sub-display first sub-region R13a communicates with the first sub-display region R11 and the second sub-display first sub-region R12a
  • the third sub-display second sub-region R13b communicates with the first sub-display region R11 and the second sub-display first sub-region R13b.
  • the second sub-region R12b is connected.
  • the first direction D1 intersects the second direction D2, for example, the first direction D1 is perpendicular to the second direction D2.
  • the first direction D1 is parallel to the sub-pixel column direction
  • the second direction D2 is parallel to the sub-pixel row direction.
  • this embodiment does not limit it.
  • the display substrate may include a plurality of sub-pixels disposed on a base substrate. At least one sub-pixel includes a pixel circuit and a light emitting element.
  • the pixel circuit is configured to drive a light emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light emitting element to emit light.
  • the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit.
  • OLED organic light-emitting diode
  • the color of light emitted by the light emitting element can be determined according to needs.
  • the light emitting element may include: a first pole (eg, anode), a second pole (eg, cathode), and an organic light emitting layer disposed between the first pole and the second pole.
  • the first pole can be connected with the pixel circuit.
  • the light emitting element may be a quantum dot light emitting diode (QLED, Quantum Dot Light Emitting Diode), a micro light emitting diode (Micro-LED, Micro Light Emitting Diode), or a miniature diode (Mini-LED).
  • a pixel unit may include three sub-pixels (for example, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), and the three sub-pixels may be arranged horizontally, vertically Arranged side by side or by character.
  • a pixel unit may include four sub-pixels (a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel), and the four sub-pixels may be arranged horizontally, vertically or squarely. arrangement.
  • the embodiments of the present disclosure are not limited here.
  • the pixel circuits for driving the light-emitting elements of the second display region R2 may be arranged in the second display region R2.
  • FIG. 2 is a schematic diagram of a partial structure of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes: a plurality of first pixel circuits 10 located in the first display region R1, a plurality of second pixel circuits 20 and a plurality of first light emitting elements 30, and A plurality of second light emitting elements 40 located in the second display region R2.
  • the plurality of second pixel circuits 20 may be distributed between the plurality of first pixel circuits 10 at intervals, for example, the plurality of first pixel circuits 10 are arranged between two adjacent second pixel circuits 20 in the first direction.
  • At least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light emitting element 30 among the plurality of first light emitting elements 30, and at least one first pixel circuit 10 on the base substrate
  • the orthographic projection and the orthographic projection of the at least one first light-emitting element 30 on the base substrate may at least partially overlap.
  • the first pixel circuit 10 can be configured to provide a driving signal to the connected first light emitting element 30 to drive the first light emitting element 30 to emit light.
  • At least one second pixel circuit 20 among the plurality of second pixel circuits 20 may be connected to at least one second light emitting element 40 among the plurality of second light emitting elements 40 through a conductive line L.
  • the second pixel circuit 20 can be configured to provide a driving signal to the connected second light emitting element 40 to drive the second light emitting element 40 to emit light. Since the second light emitting element 40 and the second pixel circuit 20 are located in different regions, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the base substrate and the orthographic projection of at least one second light emitting element 40 on the base substrate part.
  • the density of the second light emitting elements 40 in the second display region R2 may be approximately equal to the density of the first light emitting elements 30 in the first display region R1. That is, the resolution of the second display region R2 may be substantially the same as that of the first display region R1. However, this embodiment does not limit it. For example, the density of the second light emitting elements 40 may be greater than or less than that of the first light emitting elements 30 . That is, the resolution of the second display region R2 may be larger or smaller than the resolution of the first display region R1.
  • the light emitting area of the second light emitting element 40 may be smaller than the light emitting area of the first light emitting element 30 . That is, the light emitting area of the first light emitting element 30 is larger than the light emitting area of the second area light emitting element 40 . Wherein, the light emitting area of the light emitting element may correspond to the area of the opening of the pixel definition layer.
  • a light-transmitting region is provided between adjacent second light-emitting elements 40 .
  • a plurality of light-transmitting regions are connected to each other to form a continuous light-transmitting region separated by a plurality of second light-emitting elements 40 .
  • the conductive line L can be made of transparent conductive material to increase the light transmittance of the light-transmitting area as much as possible.
  • the area where the second pixel circuit 20 is disposed may be obtained by reducing the size of the first pixel circuit 10 in the second direction D2.
  • the size of the first pixel circuit 10 in the second direction D2 may be smaller than the size of the first light emitting element 30 in the second direction D2.
  • the second direction D2 is, for example, the sub-pixel row direction, but not limited thereto.
  • the second direction D2 may be a sub-pixel column direction. This exemplary embodiment is described by taking the second direction D2 as the sub-pixel row direction as an example.
  • the size of the first pixel circuit 10 and the second pixel circuit 20 in the second direction D2 can be the same, and the size of each pixel circuit in the second direction D2 is the same as the size of the first light emitting element 30 in the second direction D2.
  • the dimensions can vary by about 4 micrometers ( ⁇ m).
  • the size of each pixel circuit in the first direction D1 is substantially the same as the size of the first light emitting element 30 in the first direction D1.
  • the first direction D1 is perpendicular to the second direction D2.
  • the first sub-display region R11 , the second sub-display region, and the third sub-display region of the first display region R1 are each provided with a plurality of first pixel circuits 10 and second pixel circuits 20 .
  • the second light emitting element 40 in the second display region R2 may be connected to the second pixel circuit 20 in the third sub-display region.
  • the second pixel circuits 20 not connected to the light-emitting elements in the first display region R1 may be referred to as dummy (Dummy) pixel circuits.
  • this embodiment does not limit it.
  • the first pixel circuit 10 and the second pixel circuit 20 arranged among the plurality of first pixel circuits 10 may be arranged in the third sub-display area of the first display area R1, the first sub-display area R11 and the second The sub-display area may only be provided with the first pixel circuit 10 without the second pixel circuit 20 .
  • the first pixel circuit 10 and the second pixel circuit 20 arranged among the plurality of first pixel circuits 10 may be arranged in the third sub-display area and the second sub-display area of the first display area R1, the first sub-display area R1
  • the display region R11 may only be provided with the first pixel circuit 10 without the second pixel circuit 20 .
  • FIG. 3A to 3C are partial structural schematic diagrams of the first display area according to at least one embodiment of the present disclosure.
  • FIG. 3A shows a schematic structural diagram of sub-pixels in the first display region R1.
  • FIG. 3B shows a schematic diagram of a partial structure of the first display region R1 in FIG. 3A (including only pixel circuits)
  • FIG. 3C shows a schematic diagram of a partial structure of the first display region R1 in FIG. 3A (including only light-emitting elements).
  • the size of the pixel circuit in the second direction D2 is smaller than the size of the light emitting element in the second direction D2, so that the second direction from right to left can be
  • the pixel circuits in the first column and the ninth column are not connected to any first light-emitting element 30, and belong to multi-column pixel circuits, which can be used as the second pixel circuit 20 to connect to the second light-emitting element 40 in the second display region R2, or only as a The unused second pixel circuit 20 (ie dummy pixel circuit).
  • any first light emitting element 30 may be one of four types of light emitting elements including RG1BG2.
  • the first electrode E1 of the first light emitting element 30 may be connected to the first transfer electrode CE1 of the first pixel circuit 10 through the second transfer electrode CE2 .
  • R represents a light-emitting element that emits red light
  • G1 represents a light-emitting element that emits green light
  • B represents a light-emitting element that emits blue light
  • G2 represents a light-emitting element that emits green light.
  • At least one second pixel circuit 20 may have a first via electrode
  • at least one second light emitting element 40 may have a second via electrode.
  • connecting at least one second pixel circuit 20 and at least one second light-emitting element 40 through a conductive line L may include: connecting the conductive line L to the first transfer electrode of at least one second pixel circuit 20 and at least one second light-emitting element respectively. 40 second via electrodes.
  • the axes of the first via electrode and the second via electrode in the same row of sub-pixels may be located on a straight line.
  • this embodiment does not limit it.
  • one repeating unit RP includes two green (G) sub-pixels arranged in the first direction D1 and two green (G) sub-pixels arranged in the second Red (R) sub-pixels and blue (B) sub-pixels on both sides in the two directions D2.
  • the red sub-pixel and the green sub-pixel can form a pixel unit, and borrow the blue sub-pixel in another repeating unit adjacent to it to form a virtual pixel for display, wherein the blue sub-pixel and the green sub-pixel can form a pixel unit, and use the red sub-pixel in another repeating unit adjacent to it to form a virtual pixel for display.
  • this embodiment does not limit it.
  • FIG. 4 is a schematic diagram of arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a partial arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 and FIG. 5 only a few data lines are taken as an example for illustration.
  • Fig. 4 only several first pixel circuits 10 and second pixel circuits 20 are taken as an example for illustration.
  • the display substrate has a central axis OO' in the second direction D2, and the display substrate may be symmetrical about the central axis OO'.
  • the arrangement of the data lines on the left half of the display substrate is taken as an example for illustration.
  • the frame region R3 includes a driver chip region
  • the driver chip region may include an integrated circuit configured to be connected to a plurality of data lines of the display region.
  • the second sub-display area may be located on a side of the second display area R2 far away from the driving chip area, and the first sub-display area R11 is located on a side of the second display area R2 close to the driving chip area.
  • the first display region R1 is provided with a plurality of first data lines.
  • the frame region R3 is provided with a plurality of data connection lines 64 .
  • At least one first data line is connected to at least one pixel circuit in the first sub-display region R11, and is connected to at least one pixel circuit in the second sub-display first sub-region R12a of the second sub-display region through at least one data connection line 64 .
  • at least one first data line is connected to a column of first pixel circuits in the first sub-display region R11 and a column of first pixel circuits in the second sub-display first sub-region R12a.
  • At least one first data line includes: a first sub-data line 61 , a second sub-data line 62 and a third sub-data line 63 .
  • the third sub data line 63 is connected between the first sub data line 61 and the second sub data line 62 .
  • the first sub-data line 61 is located in the first sub-display region R11 and connected to a column of first pixel circuits in the first sub-display region R11.
  • the second sub-data line 62 is located in the second sub-display first sub-region R12a of the second sub-display region and is connected to a column of first pixel circuits in the second sub-display first sub-region R12a.
  • the third sub-data line 63 is located in the third sub-display first sub-region R13a of the third sub-display region, and extends to the first sub-display region R11 to connect with the first sub-data line 61 and the data connection line with the frame region R3 64 connections.
  • the third sub-data line 63 is connected to a plurality of second pixel circuits arranged along the first direction D1 in the first sub-region R13a of the third sub-display.
  • the data connection line 64 of the frame region R3 is connected to the second sub-data line 62 of the first sub-region R12a of the second sub-display.
  • the data signal provided by the driving chip area can be transmitted to the second sub-data line 62 through the first sub-data line 61, the third sub-data line 63 and the data connection line 64, and the third sub-data line 63 is used to
  • the third sub-display area provides data signals to the pixel circuits in the second sub-display area after winding, which can avoid the direct wiring of data lines in the second display area R2 and affect the light transmittance of the second display area R2, thereby improving the display effect .
  • the first display region R1 is provided with pixel circuits arranged in an array.
  • the third sub-display area is provided with n1 columns of pixel circuits
  • the first sub-display area R11 is provided with n2 columns of pixel circuits
  • the second sub-display area is provided with n3 columns of pixel circuits.
  • n3 may be smaller than n2.
  • this embodiment does not limit it.
  • n3 may be equal to n2.
  • the first sub-data lines 61 extend along the first direction D1, and the plurality of first sub-data lines 61 extend along the second direction.
  • the directions D2 are arranged sequentially.
  • One first sub-data line 61 may be connected to a column of first pixel circuits 10 and configured to provide the corresponding first pixel circuits 10 with data signals introduced from the driving chip area.
  • one first sub-data line 61 may be connected to one column of second pixel circuits.
  • the second sub-data lines 62 may extend along the first direction D1, and a plurality of second sub-data lines 62 are sequentially arranged along the second direction D2.
  • One second sub-data line 62 may be connected to a column of first pixel circuits 10 or a column of second pixel circuits 20 in the second sub-display area.
  • the first sub-data line 61 and the second sub-data line 62 are separated by the second display region R2.
  • the first sub-data lines 61 and the second sub-data lines 62 may have the same layer structure.
  • the third sub-data line 63 in the third sub-display region, includes: a first line segment 631 and a second line segment 632 connected to each other.
  • the first line segment 631 extends along the second direction D2, and a plurality of first line segments 631 are arranged in sequence along the first direction D1.
  • the second line segment 632 extends along the first direction D1, and a plurality of second line segments 632 are sequentially arranged along the second direction D2.
  • first line segment 631 extends to the first sub-display region R11 and is connected to the first sub-data line 61 , and the other end of the first line segment 631 is connected to the second line segment 632 in the third sub-display region.
  • the second line segment 632 is connected to a plurality of second pixel circuits 20 arranged along the first direction D1 in the third sub-display area.
  • the plurality of second pixel circuits 20 connected by the second line segment 632 are connected to the second light emitting elements 40 of the second display region R2.
  • this embodiment does not limit it.
  • the plurality of second pixel circuits 20 connected by the second line segment 632 may be dummy pixel circuits, that is, may not be connected to the light emitting element.
  • the first line segment 631 and the second line segment 632 may have a heterogeneous structure.
  • the second line segment 632 and the first sub-data line 61 may have the same layer structure, and the first line segment 631 and the first sub-data line 61 may have a different-layer structure.
  • the first line segment 631 and the second line segment 632 may be of an integrated structure and have a different layer structure with the first sub-data line 61 .
  • this embodiment does not limit it.
  • the multiple data connection lines 64 are located on the side of the second display region R2 away from the driving chip area, for example, in the upper frame area.
  • At least one data connection line 64 includes: a first sub-data connection line 641, a second sub-data connection line 642 and a third sub-data connection line 643.
  • the first sub-data connection line 641 and the third sub-data connection line 643 extend along the first direction D1
  • the second sub-data connection line 642 extends along the second direction D2.
  • the lengths of the plurality of second sub-data connection lines 642 along the second direction D2 may be the same.
  • a plurality of first sub-data connection lines 641 and a plurality of third sub-data connection lines 643 are sequentially arranged along the second direction D2, and a plurality of second sub-data connection lines 642 are sequentially arranged along the first direction D1.
  • the second sub-data connection line 642 is respectively connected to the first sub-data connection line 641 and the third sub-data connection line 643 .
  • the first sub-data connection line 641 is connected to the second segment 632 of the third sub-data line 63
  • the third sub-data connection line 643 is connected to the second sub-data line 62 .
  • the first sub-data connection line 641 and the third sub-data connection line 643 are of the same layer structure, and are of a different-layer structure from the second sub-data connection line 642 .
  • the second sub-data connection line 642 may have the same layer structure as the second segment 632 of the third sub-data line 63 and the second sub-data line 62 .
  • this embodiment does not limit it.
  • the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the second light-emitting element connected to the second pixel circuit connected to the corresponding third sub-data line 63 may be Located in the same column, the first light-emitting element connected to the first pixel circuit connected to the first sub-data line 61 and the first light-emitting element connected to the first pixel circuit connected to the corresponding second sub-data line 62 may be located in the same column.
  • this embodiment does not limit it.
  • the first line segments 631 of the plurality of third sub-data lines 63 are arranged along the first direction D1, the closer to the first line of the second display region R2
  • the segment 631 is connected to the first sub-data line 61 closer to the central axis OO'; the first segment 631 closer to the second display region R2 is connected to the second segment 632 farther away from the central axis OO'.
  • the lengths of the plurality of second line segments 632 in the first direction D2 gradually decrease.
  • the lengths of the plurality of first line segments 631 in the second direction D2 gradually decrease.
  • this embodiment does not limit it.
  • the lengths of the plurality of first line segments 631 in the second direction D2 remain unchanged.
  • the lengths of the plurality of second line segments 632 in the first direction D2 gradually increase.
  • the first display region R1 is further provided with a plurality of second data lines 71 .
  • the plurality of second data lines 71 all extend along the first direction D1 and are sequentially arranged along the second direction D2.
  • the second data line 71 in the first display region R1 does not need to be designed for winding.
  • At least one second data line 71 may be connected to a column of pixel circuits (first pixel circuit or second pixel circuit).
  • a part of the second pixel circuits 20 is connected to the second segment 632 of the third sub-data line 63, and another part may be connected to the second data line 71, and the third The second segment 632 of the sub-data line 63 is disconnected from the second data line 71 .
  • the pixel circuit of this embodiment will be described with an example below.
  • FIG. 6A is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 6B is a working timing diagram of the pixel circuit shown in FIG. 6A .
  • the pixel circuits in the first display region R1 may all have a 7T1C structure.
  • this embodiment does not limit it.
  • the pixel circuit may include other numbers of transistors and capacitors, such as 5T1C or 6T1C structures.
  • each pixel circuit includes six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes a first pole E1, a second pole E2, and an organic light emitting layer between the first pole E1 and the second pole E2.
  • the first pole E1 may be an anode
  • the second pole E2 may be a cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the display substrate includes scanning lines GL, data lines DL, first power lines PL1, second power lines PL2, light emission control lines EML, first initial signal lines INIT1, a second initial signal line INIT2, a first reset control line RST1 and a second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN.
  • this embodiment does not limit it.
  • the second reset control line RST2 may be input with a second reset control signal RESET2.
  • the first reset control line RST1 may be connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1 (n) is the same as the scan signal SCAN(n-1).
  • the first reset control line RST1 connected to the pixel circuit in the nth row and the second reset control line RST2 connected to the pixel circuit in the (n ⁇ 1)th row may have an integral structure. In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the first initial signal line INIT1 and the second initial signal line INIT2 may provide the same initial signal.
  • the first initial signal line INIT1 connected to the pixel circuits in the nth row and the second initial signal line INIT2 connected to the pixel circuits in the (n ⁇ 1)th row may have an integral structure.
  • this embodiment does not limit it.
  • the driving transistor T3 is electrically connected to the light emitting element EL, and is connected to the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, Under the control of the second voltage signal VSS and other signals, the driving current is output to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is connected to the scan line GL, the first pole of the data writing transistor T4 is connected to the data line DL, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3.
  • the gate of the threshold compensation transistor T2 is connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3.
  • the gate of the first light emission control transistor T5 is connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is connected to the first power line PL1, the second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T3 One pole connected.
  • the gate of the second light emission control transistor T6 is connected to the light emission control line EML, the first pole of the second light emission control transistor T6 is connected to the second pole of the driving transistor T3, and the second pole of the second light emission control transistor T6 is connected to the light emitting element EL.
  • the first pole E1 is connected.
  • the first reset transistor T1 is connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is connected to the first pole E1 of the light emitting element EL, and is configured to reset the gate of the light emitting element EL.
  • the first electrode E1 is reset.
  • the gate of the first reset transistor T1 is connected to the first reset control line RST1, the first pole of the first reset transistor T1 is connected to the first initial signal line INIT1, the second pole of the first reset transistor T1 is connected to the gate of the drive transistor T3 Pole connected.
  • the gate of the second reset transistor T7 is connected to the second reset control line RST2, the first pole of the second reset transistor T7 is connected to the second initial signal line INIT2, and the second pole of the second reset transistor T7 is connected to the first pole of the light emitting element EL.
  • One pole E1 is connected.
  • a first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and a second electrode of the storage capacitor Cst is connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T
  • the working process of the pixel circuit shown in FIG. 6A will be described below with reference to FIG. 6B .
  • the description will be made by taking a plurality of transistors included in the pixel circuit as P-type transistors as an example.
  • the working process of the pixel circuit with the first structure includes: a first stage A1 , a second stage A2 and a third stage A3 .
  • the first phase A1 is called the reset phase.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, so that the first reset transistor T1 is turned on, and the initial signal Vinit provided by the first initial signal line INIT1 is provided to the first node N1.
  • a node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off. At this stage, the light emitting element EL does not emit light.
  • the second phase A2 is called a data writing phase or a threshold compensation phase.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DT is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2.
  • a node N2 and the difference between the data voltage Vdata output by the data line DT and the threshold voltage of the drive transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the initial signal Vinit provided by the second initial signal line INIT2 is supplied to the first pole E1 of the light-emitting element EL, and the first pole E1 of the light-emitting element EL is initialized (reset), and its internal Prestore the voltage, complete the initialization, and ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage A3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5 , the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the first pole E1 of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*[(VDD-Vdata)] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 7A is a schematic plan view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 7B is a schematic partial cross-sectional view along the P-P' direction in Fig. 7A.
  • the first direction D1 may be the direction of sub-pixel columns (vertical direction)
  • the second direction D2 may be the direction of sub-pixel rows (horizontal direction).
  • the display substrate in a plane parallel to the display substrate, is provided with a scanning line GL, an emission control line EML, a first reset control line RST1, a first initial signal line INIT1, a second initial signal line INIT2 , a first power line PL1, a data line DL and a pixel circuit.
  • the pixel circuit may include a plurality of transistors and a storage capacitor Cst, and the plurality of transistors may include a drive transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first reset transistor T1, a second reset transistor T7, and a first light emission control transistor T5 and the second light emission control transistor T6.
  • the display substrate in a plane perpendicular to the display substrate, may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the base substrate 50 conductive layer.
  • the semiconductor layer may include active layers of a plurality of transistors.
  • the first conductive layer may include a scan line GL, a first reset control line RST1, a second reset control line RST2, an emission control line EML, a first electrode of a storage capacitor Cst, and gates of a plurality of transistors.
  • the second conductive layer may include a first initial signal line INIT1, a second initial signal line INIT2, a second electrode of the storage capacitor Cst, and a first shield electrode SE1.
  • the third conductive layer may include a first power line PL1, a data line DL, first poles and second poles of a plurality of transistors.
  • the fourth conductive layer may include: a second shielding electrode SE2 and a first connection electrode CE1.
  • the display substrate may include a first insulating layer 51 , a second insulating layer 52 , a third insulating layer 53 , a fourth insulating layer 54 and a fifth insulating layer 55 .
  • the first insulating layer 51 is arranged between the base substrate 50 and the semiconductor layer
  • the second insulating layer 52 is arranged between the semiconductor layer and the first conductive layer
  • the third insulating layer 53 is arranged between the first conductive layer and the second conductive layer.
  • the fourth insulating layer 54 is disposed between the second conductive layer and the third conductive layer
  • the fifth insulating layer 55 is disposed between the third conductive layer and the fourth conductive layer.
  • the first insulating layer 51 , the second insulating layer 52 , the third insulating layer 53 and the fourth insulating layer 54 may be inorganic insulating layers, and the fifth insulating layer 55 may be an organic insulating layer.
  • this embodiment does not limit it.
  • FIG. 7C is a schematic diagram of a pixel circuit after forming a semiconductor layer according to at least one embodiment of the present disclosure.
  • the semiconductor layer of at least one sub-pixel may include: a first active layer T10 of a first reset transistor T1, a second active layer T20 of a threshold compensation transistor T2, a driver The third active layer T30 of the transistor T3, the fourth active layer T40 of the data writing transistor T4, the fifth active layer T50 of the first light emission control transistor T5, the sixth active layer T60 of the second light emission control transistor T6 , the seventh active layer T70 of the second reset transistor T7.
  • the first active layer T10 to the seventh active layer T70 are interconnected integral structures.
  • the shape of the first active layer T10 may be in the shape of an "n"
  • the shape of the second active layer T20 may be in the shape of a "7”
  • the shape of the third active layer T30 may be
  • the shape of the fourth active layer T40 can be in the shape of "1”
  • the shape of the fifth active layer T50, the sixth active layer T06, and the seventh active layer T70 can be in the shape of "L”. " font.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the second region T10-2 of the first active layer T10 simultaneously serves as the first region T20-1 of the second active layer T20
  • the first region of the third active layer T30 T30-1 serves as the second region T40-2 of the fourth active layer T40 and the second region T50-2 of the fifth active layer T50 at the same time
  • the second region T30-2 of the third active layer T30 serves as the second
  • the second region T20-2 of the active layer T20 and the first region T60-1 of the sixth active layer T60, the second region T60-2 of the sixth active layer T60 simultaneously serves as the second region of the seventh active layer T70 District T70-2.
  • FIG. 7D is a schematic diagram of a pixel circuit after forming a first conductive layer according to at least one embodiment of the present disclosure.
  • the first conductive layer at least includes: a first electrode Cst-1 of a storage capacitor Cst, a scanning line GL extending along the second direction D2, an emission control line EML, a first A reset control line RST1 and a second reset control line RST2.
  • the first electrode Cst-1 of the storage capacitor Cst can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projections on the substrate substrate have overlapping regions.
  • the first electrode Cst-1 of the storage capacitor Cst also serves as the gate T33 of the driving transistor T3.
  • the scan line GL, the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 may be of an integral structure.
  • the light emission control line EML, the gate T53 of the first light emission control transistor T5 , and the gate T63 of the second light emission control transistor T6 may have an integral structure.
  • the first reset control line RST1 and the gate T13 of the first reset transistor T1 may have an integrated structure.
  • the second reset control line RST12 and the gate T73 of the second reset transistor T7 may have an integrated structure.
  • FIG. 7E is a schematic diagram of a pixel circuit after forming a second conductive layer according to at least one embodiment of the present disclosure.
  • the second conductive layer at least includes: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of a storage capacitor Cst, and a first shield Electrode BK. Both the first initial signal line INIT1 and the second initial signal line INIT2 extend along the second direction D2 and are located on opposite sides of the second electrode Cst-2 of the storage capacitor Cst in the first direction D1.
  • the orthographic projection of the second electrode Cst- 2 of the storage capacitor Cst on the substrate is located between the orthographic projections of the scanning line GL and the emission control line EML on the substrate. There is an overlapping area between the orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate and the orthographic projection of the first electrode Cst-1 on the substrate.
  • the second electrode Cst-2 is provided with an opening OP1, the opening OP1 exposes the third insulating layer 53 covering the first electrode Cst-1, and the orthographic projection of the first electrode Cst-1 on the substrate includes the opening OP1 on the substrate. Orthographic projection on the base substrate.
  • the opening OP1 is configured to accommodate the subsequently formed first via hole H1, the first via hole H1 is located in the opening OP1 and exposes the first electrode Cst-1, so that the first electrode Cst-1 of the subsequently formed first reset transistor T1 The diode is connected to the first electrode Cst-1.
  • the first shielding electrode SE1 is located on a side of the scan line GL away from the storage capacitor Cst.
  • the first shielding electrode SE1 is configured to shield the impact of data voltage jumps on key nodes, avoiding the impact of data voltage jumps on the potentials of key nodes of the pixel circuit, and improving the display effect.
  • FIG. 7F is a schematic diagram of a pixel circuit after forming a third conductive layer according to at least one embodiment of the present disclosure.
  • a first via hole H1 a plurality of second via holes V1 to V4 , and a plurality of third via holes K1 to K6 are formed on the fourth insulating layer.
  • the fourth insulating layer 54 and the third insulating layer 53 in the first via hole H1 are etched away, exposing the surface of the first conductive layer.
  • the fourth insulating layer 54 in the plurality of second via holes V1 to V4 is etched away, exposing the surface of the second conductive layer.
  • the fourth insulating layer 54 , the third insulating layer 53 and the second insulating layer 52 in the plurality of third via holes K1 to K8 are etched away, exposing the surface of the semiconductor layer.
  • the third conductive layer may include: a data line DL, a first power line PL1, a first pole T11 of the first reset transistor T1, a first electrode of the second reset transistor T7 pole T71, the first pole T21 of the threshold compensation transistor T2, and the second pole T62 of the second light emission control transistor T6.
  • the data line DL and the first power line PL1 extend in the first direction D1.
  • the data line DL is connected to the first region T40 - 1 of the fourth active layer T40 of the data writing transistor T4 through the third via hole K2 .
  • the first power line PL1 is connected to the second electrode Cst-2 of the storage capacitor Cst through the second via hole V1, connected to the first shielding electrode SE1 through the second via hole V2, and connected to the first light emission control transistor through the third via hole K4.
  • the first region T50-1 of the fifth active layer T50 of T5 is connected.
  • the first electrode T21 of the threshold compensation transistor T2 is connected to the first electrode Cst-1 of the storage capacitor Cst through the first via hole H1, and is connected to the first region of the second active layer T20 of the threshold compensation transistor T2 through the third via hole K1.
  • T20-1 is connected.
  • the second pole T62 of the second light emission control transistor T6 is connected to the second region T60-2 of the sixth active layer T60 of the second light emission control transistor T6 through the third via hole K5.
  • the first electrode T11 of the first reset transistor T1 is connected to the first initial signal line INIT1 through the second via hole V3, and connected to the first region T10- of the first active layer T10 of the first reset transistor T1 through the third via hole K3 1 connected.
  • the first pole T71 of the second reset transistor T7 is connected to the first region T70-1 of the seventh active layer T70 of the second reset transistor T7 through the third via hole K6, and the first pole T71 of the second reset transistor T7 is also connected through The second via hole V4 is connected to the second initial signal line INIT2.
  • FIG. 7G is a schematic diagram of a pixel circuit after forming a fourth conductive layer according to at least one embodiment of the present disclosure.
  • a plurality of fourth via holes F1 to F2 are formed on the fifth insulating layer 55 .
  • the fifth insulating layer 55 in the plurality of fourth via holes F1 to F2 is removed, exposing the surface of the third conductive layer.
  • the fourth conductive layer at least includes: the second shielding electrode SE2 and the first via electrode CE1.
  • the first transfer electrode CE1 is connected to the second pole T62 of the second light emitting control transistor T6 through the fourth via hole F1.
  • the first transfer electrode CE1 may be directly connected to the first regional light-emitting element, or connected to the second transfer electrode of the first regional light-emitting element, or connected to the second transfer electrode of the second regional light-emitting element through a conductive wire .
  • the second shielding electrode SE2 is connected to the first power line PL1 through the fourth via hole F2.
  • the orthographic projection of the second shielding electrode SE2 on the base substrate partly overlaps the orthographic projection of the driving transistor T3 on the base substrate.
  • the second shielding electrode SE2 is configured to shield the influence of the conductive wire on the driving transistor T3 to improve the display effect.
  • FIG. 8A is a schematic diagram of the connection position of the first segment of the first sub-data line and the third sub-data line according to at least one embodiment of the present disclosure.
  • FIG. 8B is a schematic diagram of connection positions of the first line segment and the second line segment of the third sub-data line according to at least one embodiment of the present disclosure.
  • the first sub-data line 61 is the data line DL connected to a column of pixel circuits (eg, the first pixel circuit).
  • a fourth via hole F3 is formed in the fifth insulating layer 55 .
  • the first segment 631 of the third sub-data line 63 is located on the fourth conductive layer.
  • the first segment 631 of the third sub-data line 63 is connected to the first sub-data line 61 through the fourth via hole F3 formed on the fifth insulating layer 55 .
  • the second line segment 632 of the third sub-data line 63 is the connecting edge A plurality of data lines DL of the second pixel circuits arranged in the first direction D1, the second data line 71 is the data line DL connected to a column of the first pixel circuits.
  • the second segment 632 of the third sub-data line 63 is located in the third conductive layer, and the first segment 631 is located in the fourth conductive layer.
  • the first line segment 631 is connected to the second line segment 632 through the fourth via hole F4 formed on the fifth insulating layer 55 .
  • the length of the first line segment 631 along the second direction D2 is greater than the distance between the fourth via holes F3 and F4 to ensure effective connection between the first line segment 631 , the second line segment 632 and the first sub-data line 61 .
  • the orthographic projection of the first line segment 631 on the base substrate 50 can be aligned with the first initial signal line INIT1 and the second reset control line RST2 on the base substrate.
  • the orthographic projections on 50 overlap, and the orthographic projection of the first line segment 631 on the substrate 50 may be located between the orthographic projections of the first initial signal line INIT1 and the second reset control line RST2 on the substrate 50 .
  • this embodiment does not limit it.
  • FIG. 8C is a schematic diagram of the cut-off position of the second line segment of the third sub-data line according to at least one embodiment of the present disclosure.
  • the second line segment 632 of the third sub-data line 63 may extend along the first direction D1 to a certain position. due.
  • the remaining second pixel circuits located in the same column as the second pixel circuit connected to the second line segment 632 may be connected to one second data line 71 , and the second line segment 632 is disconnected from the second data line 71 .
  • this embodiment does not limit it.
  • FIG. 8D is a schematic diagram of connection between the third sub-data line and the data connection line according to at least one embodiment of the present disclosure.
  • FIG. 8E is a schematic diagram of connection between the second sub-data line and the data connection line according to at least one embodiment of the present disclosure.
  • one end of the second line segment 632 of the third sub-data line 63 extends to the third sub-display area along the first direction D1 (for example, the third sub-display area A sub-region R13a) the adjacent frame region.
  • the first sub-data connection line 641 and the third sub-data connection line 643 may be located in the fourth conductive layer, and the second sub-data connection line 642 may be located in the third conductive layer.
  • the second segment 632 of the third sub-data line 63 can be connected to one end of the first sub-data connection line 641 through the fourth via hole F5 formed on the fifth insulating layer 55, and the other end of the first sub-data connection line 641 can pass through the fourth via hole F5 formed on the fifth insulating layer 55.
  • the fourth via hole F6 formed on the fifth insulating layer 55 is connected to one end of the second sub-data connection line 642 .
  • the other end of the second sub-data connection line 642 may be connected to one end of the third sub-data connection line 643 through the fourth via hole F7 formed on the fifth insulating layer 55 .
  • the other end of the third sub-data connection line 643 may be connected to one end of the second sub-data line 62 extending to the frame area through the fourth via hole F8 formed on the fifth insulating layer 55 .
  • the plurality of second sub-data connection lines 642 all extend along the second direction D2 and are arranged sequentially along the first direction D1 .
  • the lengths of the plurality of second sub-data connection lines 642 along the second direction D2 may be the same.
  • Both the plurality of first sub-data connection lines 641 and the plurality of third sub-data connection lines 643 extend along the first direction D1.
  • the multiple first sub-data connection lines 641 are sequentially arranged along the second direction D2, and the multiple third sub-data connection lines 643 are sequentially arranged along the second direction D2.
  • the lengths of the plurality of first sub-data connection lines 641 and the plurality of third sub-data connection lines 643 along the first direction D1 may be approximately the same. However, this embodiment does not limit it.
  • a plurality of first pixel circuits 10 and a plurality of second pixel circuits 20 are arranged in the second sub-display region (for example, the second sub-display first sub-region R12a).
  • a column of second pixel circuits 20 shown in FIG. 8E is used as a dummy pixel circuit, which is not connected to the second light-emitting element in the second display region R2 and does not need a data signal.
  • the second sub-data connection line 62 connected to the first pixel circuit 10 is connected to the second sub-data connection line 642 through the third sub-data connection line 643 to receive data signals.
  • this embodiment does not limit it.
  • the data lines connected to the column of second pixel circuits 20 can also be connected through the third sub-data connection.
  • the line 643 is connected to the second sub-data connection line 642 to receive a data signal.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the "layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of B's orthographic projection.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
  • the manufacturing process of the display substrate may include the following operations.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the base substrate 50, patterning the semiconductor film through a patterning process, and forming a first insulating film covering the base substrate 50.
  • the display substrate includes a first insulating layer 51 disposed on the base substrate 50 and a semiconductor layer disposed on the first insulating layer 51 , and the semiconductor layer may include active layers of multiple transistors of the pixel circuit.
  • the active layer of the second reset transistor of the pixel circuit and the active layer of the first reset transistor of the adjacent pixel circuit may have an integral structure.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the base substrate 50 forming the aforementioned pattern, and performing patterning on the first metal film. patterning to form a second insulating layer 52 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 52 .
  • the first conductive layer pattern may include: the gates of multiple transistors of the pixel circuit, the first reset control line RST1, the scan line GL, the light emission control line EML, and the first electrode Cst-1 of the storage capacitor Cst. , the second reset control line RST2.
  • the first reset control line RST1, the second reset control line RST2, the scan line GL and the light emission control line EML extend along the second direction D2, and the first electrode Cst-1 of the storage capacitor Cst is located between the scan line GT and the light emission control line EML .
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the region shielded by the first conductive layer forms channels of multiple transistors In the region, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer T10 to the seventh active layer T70 are all conductorized.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a second metal film on the substrate 50 forming the aforementioned pattern, and patterning the second metal film by a patterning process. , forming a third insulating layer 53 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 53 .
  • the second conductive layer pattern may include: a first initial signal line INIT1 , a second initial signal line INIT2 , a second electrode Cst- 2 of the storage capacitor Cst, and a first shielding electrode SE1 .
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the base substrate 50 formed with the aforementioned pattern, and patterning the fourth insulating film by a patterning process to form a pattern covering the first insulating layer.
  • the fourth insulating layer 54 of the second conductive layer As shown in FIG. 7F , a plurality of first via holes H1 , a plurality of second via holes V1 to V3 and a plurality of third via holes K1 to K6 are disposed on the fourth insulating layer.
  • the fourth insulating layer 54 and the third insulating layer 53 in the plurality of first via holes are etched away, exposing the surface of the first conductive layer, and the fourth insulating layer 54 in the plurality of second via holes is etched away , exposing the surface of the second conductive layer, the fourth insulating layer 54 , the third insulating layer 53 and the second insulating layer 52 in the plurality of third via holes are etched away, exposing the surface of the semiconductor layer.
  • forming the third conductive layer may include: depositing a third metal thin film on the base substrate 50 formed with the aforementioned pattern, patterning the third metal thin film by a patterning process, and forming the second conductive layer.
  • the third conductive layer may include: the second data line 71 located in the first display region R1, the first sub-data line 61, the second sub-data line 62, the third sub-data line The second line segment 632 of 63, the first power line PL1, the first pole and the second pole of a plurality of transistors of the pixel circuit, and the second sub-data connection line 642 located in the frame region R3.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • forming the pattern of the fifth insulating layer may include: coating a flat film on the base substrate 50 formed with the aforementioned pattern, and patterning the flat film by a patterning process to form a covering third conductive layer.
  • the fifth insulating layer 55 as shown in FIG. 7G.
  • a plurality of fourth via holes F1 to F8 are formed on the fifth insulating layer 55 .
  • the fifth insulating layer 55 in the plurality of fourth via holes is removed, exposing the surface of the third conductive layer.
  • the fifth insulating layer 55 may be called a flat layer.
  • forming the pattern of the fourth conductive layer may include: depositing a fourth metal thin film on the base substrate 50 formed with the aforementioned pattern, patterning the fourth metal thin film by a patterning process, forming a The fourth conductive layer on the fifth insulating layer 55 .
  • the fourth conductive layer pattern may include: the first connection electrode CE1 located in the first display region R1, the second shielding electrode SE, the first line segment 631 of the third sub-data line 63, and the first line segment 631 located in the frame area.
  • the second shielding electrode SE is connected to the first power line PL1 through the fourth via hole F2
  • the first connection electrode CE1 is connected to the second pole T62 of the second light emission control transistor T6 through the fourth via hole F1.
  • the first segment 631 of the third sub-data line 63 is connected to the first sub-data line 61 through the fourth via hole F3, and is connected to the second segment 632 of the third sub-data line 63 through the fourth via hole F4.
  • the first sub-data connection line 641 is connected to the second line segment 632 through the fourth via hole F5, and connected to the second sub-data connection line 642 through the fourth via hole F6.
  • the third sub-data connection line 643 is connected to the second sub-data connection line 642 through the fourth via hole F7, and connected to the second sub-data line 62 through the fourth via hole F8.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the subsequent manufacturing process may include: forming a conductive wire layer.
  • the plurality of conductive lines connecting the second pixel circuit in the first display area and the second light emitting element in the second display area may be of the same layer structure.
  • Forming the conductive line layer may include: coating a flat film on the base substrate forming the fourth conductive layer, patterning the flat film by a patterning process to form a sixth insulating layer covering the fourth conductive layer; then, depositing a transparent The conductive film is patterned by patterning the transparent conductive film to form a conductive line layer on the sixth insulating layer.
  • the first connection electrode CE1 of the second pixel circuit in the first display region R1 is connected to a conductive line, and the conductive line can extend from the first display region R1 to the second display region R2 so as to communicate with the second light emitting element in the second display region R2 connect.
  • this embodiment does not limit it.
  • the plurality of conductive lines connecting the second pixel circuit in the first display region R1 and the second light emitting element in the second display region R2 may be in a hetero-layer structure.
  • at least one conductive line may be formed by connecting multiple conductive line segments located in different conductive line layers.
  • the preparation process after forming the conductive line layer may include: forming a flat layer covering the conductive line layer; depositing a transparent conductive film, and patterning the transparent conductive film by a patterning process to form a flat An anode on the layer; coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode.
  • An organic light-emitting layer is formed by vapor deposition or an ink-jet printing process, and a cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting element.
  • the substrate substrate 50 may be a flexible substrate substrate, or may be a rigid substrate substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • PI polyimide
  • PET polyethylene terephthalate
  • SiNx silicon nitride
  • SiOx silicon oxide
  • a-si amorphous silicon
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/ Mo et al.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer 51, the second insulating layer 52, the third insulating layer 53 and the fourth insulating layer 54 can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) or multiple, can be a single layer, multi-layer or composite layer.
  • the first insulating layer 51 is called a buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer 52 and the third insulating layer 53 are called gate insulating (GI) layers
  • the fourth insulating layer 54 It is called an interlayer insulating (ILD) layer.
  • the planarization layer can use organic materials.
  • the transparent conductive film can use indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the active layer can be made of polysilicon (p-Si), that is, this embodiment is suitable for LTPS thin film transistors. However, this embodiment does not limit it.
  • the transistors in the pixel circuit may all use oxide thin film transistors.
  • the structure of the display substrate and the manufacturing process thereof in this embodiment are merely illustrative.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the second reset transistor in the pixel circuit can be connected to the second initial signal line.
  • the pixel circuit may include other numbers of transistors and storage capacitors, for example, 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, or the number of transistors is less than seven.
  • the first sub-data line, the second sub-data line, the second segment of the second data line, the third sub-data line, and the second sub-data connection line can be located in the fourth conductive layer, and the first sub-data line of the third sub-data line
  • the line segment, the first sub-data connection line and the third sub-data connection line may be located on the third conductive layer.
  • this embodiment does not limit it.
  • FIG. 9 is another schematic diagram of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • the first line segment and the second line segment of the third sub-data line 63 are integrally structured.
  • the first sub-data connection line, the second sub-data connection line and the third sub-data connection line of the data connection line 64 may have an integrated structure.
  • the data connection line 64 is connected between the third sub-data line 63 and the second sub-data line 62
  • the third sub-data line 63 is connected to the first sub-data line 61 .
  • the first sub-data line 61 and the data connection line 64 may be located in the third conductive layer, and the third sub-data line 63 and the second sub-data line 62 may be located in the fourth conductive layer.
  • this embodiment does not limit it.
  • FIG. 10 is another schematic diagram of arrangement of data lines of a display substrate according to at least one embodiment of the present disclosure.
  • the third sub-data line 63 includes: a first line segment 631 , a second line segment 632 and a third line segment 633 .
  • the second line segment 632 is connected to a plurality of second pixel circuits arranged along the first direction D1 in the third sub-display region.
  • the second line segment 632 is respectively connected with the first line segment 631 and the third line segment 633 .
  • the first line segment 631 and the third line segment 633 extend along the second direction D2, and the second line segment 632 extends along the first direction D1.
  • the first line segment 631 extends to the first sub-display region R11, and is connected to the first sub-data line 61 of the first sub-display region R11.
  • the third line segment 632 extends to the second sub-display region R12a, and is connected to the second sub-data line 62 of the second sub-display region R12a.
  • the first sub-data line 61 , the second sub-data line 62 and the second line segment 632 may be located in the third conductive layer, and the first line segment 631 and the third line segment 633 may be located in the fourth conductive layer.
  • this embodiment does not limit it.
  • FIG. 11 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the second display region R2 is located on the left half of the display substrate.
  • the first display area R1 includes: a first sub-display area R11 , a second sub-display area R12 and a third sub-display area R13 .
  • the first sub-display region R11 and the second sub-display region R12 are located on opposite sides of the second display region R2 along the first direction D1.
  • the first sub display area R11 and the second sub display area R12 are separated by the second display area R2 in the first direction D1.
  • the third sub-display region R13 is located on one side of the second display region R2, for example, on the right side of the second display region R2.
  • the first sub-data line 61 of the first sub-display area R11 can pass through the third sub-data line 63 of the third sub-display area R13 and the data connection line 64 of the frame area R3 and the second sub-data line of the second sub-display area R12. 62, so as to provide data signals to the pixel circuits (eg, the first pixel circuit, or the first pixel circuit and the second pixel circuit) of the second sub-display region R12.
  • FIG. 12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the second display region R2 may be rectangular and located in a central region of the display substrate.
  • the first display area R1 includes a first sub-display area R11 and a second sub-display area R12 located on opposite sides of the second display area R2 in the first direction D1, and a second sub-display area R12 located on opposite sides of the second display area R2 in the second direction D2.
  • the third sub-display area on both sides.
  • the third sub-display region includes: a third sub-display first sub-region R13a and a third sub-display second sub-region R13b.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, including: forming a plurality of pixel circuits, a plurality of first light-emitting elements, and at least one first data line in a first display region of the base substrate.
  • the first display area at least partially surrounds the second display area.
  • the first display area includes: a first sub-display area and a second sub-display area located on opposite sides of the second display area along the first direction, and a third sub-display area located on at least one side of the second display area along the second direction Display area; the first direction intersects the second direction.
  • the plurality of pixel circuits includes: a plurality of first pixel circuits and a plurality of second pixel circuits, and the plurality of second pixel circuits are distributed between the plurality of first pixel circuits. At least one pixel circuit among the plurality of first pixel circuits is connected to at least one light emitting element among the plurality of first light emitting elements.
  • the first data line includes: a first sub-data line, a second sub-data line and a third sub-data line; the third sub-data line is connected to the first sub-data line and the second sub-data line.
  • the first sub-data line is located in the first sub-display area and is connected to the pixel circuit in the first sub-display area
  • the second sub-data line is located in the second sub-display area and is connected to the pixel circuit in the second sub-display area
  • the third sub-data line is connected to the pixel circuit in the second sub-display area.
  • the wire is located in the third sub-display area and connected to at least one second pixel circuit in the third sub-display area.
  • FIG. 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the present embodiment provides a display device 91 including the display substrate 910 of the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device 91 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit it.

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Abstract

一种显示基板，包括：衬底基板、多个像素电路、多个第一发光元件和至少一条第一数据线。衬底基板包括：第一显示区和第二显示区，第一显示区至少部分包围第二显示区。第一显示区包括：沿第一方向上位于第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于第二显示区至少一侧的第三子显示区。第一数据线包括：第一子数据线、第二子数据线、以及与第一子数据线和第二子数据线连接的第三子数据线。第一子数据线位于第一子显示区并与第一子显示区的像素电路连接，第二子数据线位于第二子显示区并与第二子显示区的像素电路连接。第三子数据线位于第三子显示区并与第三子显示区的至少一个第二像素电路连接。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、多个像素电路、多个第一发光元件以及至少一条第一数据线。衬底基板，包括第一显示区和第二显示区，所述第一显示区至少部分包围所述第二显示区，所述第一显示区包括：沿第一方向上位于所述第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于所述第二显示区至少一侧的第三子显示区，所述第一方向与第二方向交叉。多个像素电路和多个第一发光元件，位于所述第一显示区；所述多个像素电路包括：多个第一像素电路和多个第二像素电路，多个第二像素电路分布在多个第一像素电路之间；多个第一像素电路中的至少一个像素电路与多个第一发光元件中的至少一个发光元件连接。至少一条第一数据线，位于所述第一显示区，所述第一数据线包括：第 一子数据线、第二子数据线和第三子数据线；所述第三子数据线与所述第一子数据线和第二子数据线连接。所述第一子数据线位于所述第一子显示区并与所述第一子显示区的像素电路连接，所述第二子数据线位于所述第二子显示区并与所述第二子显示区的像素电路连接，所述第三子数据线位于所述第三子显示区并与所述第三子显示区的至少一个第二像素电路连接。
在一些示例性实施方式中，所述第一子数据线和第二子数据线均沿所述第一方向延伸。
在一些示例性实施方式中，所述第三子数据线至少包括：第一线段和第二线段，所述第一线段沿所述第二方向延伸，所述第二线段沿所述第一方向延伸。所述第一线段的一端延伸到所述第一子显示区与第一子数据线连接，所述第一线段的另一端与所述第二线段连接。所述第二线段与所述第三子显示区的至少一个第二像素电路连接。
在一些示例性实施方式中，所述第一子数据线、第二子数据线、以及第三子数据线的第二线段为同层结构，所述第三子数据线的第一线段与第二线段为异层结构。
在一些示例性实施方式中，所述第一子数据线和第二子数据线为同层结构，所述第三子数据线与第一子数据线为异层结构。
在一些示例性实施方式中，所述衬底基板还包括：边框区域，所述边框区域位于所述第一显示区和第二显示区的外围。所述边框区域设置有至少一条数据连接线，所述数据连接线连接在所述第三子数据线和第二子数据线之间。
在一些示例性实施方式中，所述数据连接线至少包括：第一子数据连接线、第二子数据连接线和第三子数据连接线。所述第二子数据连接线连接在所述第一子数据连接线和第三子数据连接线之间，所述第一子数据连接线与第三子数据线连接，所述第三子数据连接线与第二子数据线连接。
在一些示例性实施方式中，所述第一子数据连接线和第三子数据连接线沿第一方向延伸，所述第二子数据连接线沿第二方向延伸。
在一些示例性实施方式中，所述第一子数据连接线和第三子数据连接线 为同层结构，所述第一子数据连接线和第二子数据连接线为异层结构。
在一些示例性实施方式中，所述第二子数据连接线与所述第一子数据线和第二子数据线为同层结构。
在一些示例性实施方式中，显示基板还包括：多个第二发光元件，位于所述第二显示区；多个第二像素电路中的至少一个像素电路与所述多个第二发光元件中的至少一个发光元件通过导电线连接。
在一些示例性实施方式中，在垂直于显示基板的平面内，所述显示基板至少包括：设置在所述衬底基板上的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。所述半导体层至少包括：所述像素电路的多个晶体管的有源层。所述第一导电层至少包括：所述像素电路的多个晶体管的栅极和存储电容的第一电极。所述第二导电层至少包括：所述像素电路的存储电容的第二电极。所述第三导电层至少包括：第一电源线。所述第四导电层至少包括：连接所述像素电路与发光元件的第一连接电极。
在一些示例性实施方式中，所述第一子数据线、第二子数据线、以及第三子数据线的第二线段位于第三导电层，所述第三子数据线的第一线段位于第四导电层；或者，所述第一子数据线、以及第二子数据线位于第三导电层，所述第三子数据线位于第四导电层。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法，包括：在衬底基板的第一显示区形成多个像素电路、多个第一发光元件以及至少一条第一数据线。所述第一显示区至少部分包围所述第二显示区；第一显示区包括：沿第一方向上位于第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于第二显示区至少一侧的第三子显示区；第一方向与第二方向交叉。所述多个像素电路包括：多个第一像素电路和多个第二像素电路，多个第二像素电路分布在多个第一像素电路之间；多个第一像素电路中的至少一个像素电路与多个第一发光元件中的至少一个发光元件连接。所述第一数据线包括：第一子数据线、第二子数据线和第三子数据线；所述第三子数据线与所述第一子数据线和第二子数据线连接。所述第一子数据线位于所述第一子显示区并与所述第一子显示区的像素电路连接，所述第二子数据线位 于所述第二子显示区并与所述第二子显示区的像素电路连接，所述第三子数据线位于所述第三子显示区并与所述第三子显示区的至少一个第二像素电路连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的显示基板的局部结构示意图；
图3A至图3C为本公开至少一实施例的第一显示区的局部结构示意图；
图4为本公开至少一实施例的显示基板的数据线的排布示意图；
图5为本公开至少一实施例的显示基板的数据线的局部排布示意图；
图6A为本公开至少一实施例的像素电路的等效电路图；
图6B为图6A所示的像素电路的工作时序图；
图7A为本公开至少一实施例的像素电路的平面示意图；
图7B为图7A中沿P-P’方向的局部剖面示意图；
图7C为本公开至少一实施例的形成半导体层后的像素电路的示意图；
图7D为本公开至少一实施例的形成第一导电层后的像素电路的示意图；
图7E为本公开至少一实施例的形成第二导电层后的像素电路的示意图；
图7F为本公开至少一实施例的形成第三导电层后的像素电路的示意图；
图7G为本公开至少一实施例的形成第四导电层后的像素电路的示意图；
图8A为本公开至少一实施例的第一子数据线和第三子数据线的连接位置示意图；
图8B为本公开至少一实施例的第三子数据线的第一线段和第二线段的连接位置示意图；
图8C为本公开至少一实施例的第三子数据线的第二线段的截止位置示意图；
图8D为本公开至少一实施例的第三子数据线与数据连接线的连接示意图；
图8E为本公开至少一实施例的第二子数据线与数据连接线的连接示意图；
图9为本公开至少一实施例的显示基板的数据线的另一排布示意图；
图10为本公开至少一实施例的显示基板的数据线的另一排布示意图；
图11为本公开至少一实施例的显示基板的另一示意图；
图12为本公开至少一实施例的显示基板的另一示意图；
图13为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开至少一实施例提供一种显示基板，包括：衬底基板、多个像素电路、多个第一发光元件以及至少一条第一数据线。衬底基板包括第一显示区和第二显示区。第一显示区至少部分包围第二显示区。第一显示区包括：沿第一方向上位于第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于第二显示区至少一侧的第三子显示区。第一方向与第二方向交叉。多个像素电路和多个第一发光元件，位于第一显示区。多个像素电路包括：多个第一像素电路和多个第二像素电路，多个第二像素电路分布在多个第一像素电路之间。多个第一像素电路中的至少一个像素电路与多个第一发光元件中的至少一个发光元件连接。至少一条第一数据线位于第一显示区。第一数据线包括：第一子数据线、第二子数据线和第三子数据线。第三子数据线与第一子数据线和第二子数据线连接。第一子数据线位于第一子显示区并与第一子显示区的像素电路连接，第二子数据线位于第二子显示区并与第二子显示区的像素电路连接，第三子数据线位于第三子显示区并与第三子显示区的至少一个第二像素电路连接。
在一些示例中，多个第二像素电路分布在多个第一像素电路之间，可以包括：在第二方向上，相邻两个第二像素电路之间排布有多个第一像素电路。多个第二像素电路可以沿第一方向依次排布。然而，本实施例对此并不限定。
在一些示例中，第一子显示区设置多个第一像素电路，第二子显示区设置多个第一像素电路，第三子显示区设置有多个第一像素电路和多个第二像素电路，第一数据线的第一子数据线与第一子显示区的至少一个第一像素电路连接，第二子数据线与第二子显示区的至少一个第一像素电路连接，第三子数据线与第三子显示区的至少一个第二像素电路连接。在另一些示例中，第一子显示区设置多个第一像素电路，第二子显示区设置多个第一像素电路和多个第二像素电路，第三子显示区设置有多个第一像素电路和多个第二像素电路，第一数据线的第一子数据线与第一子显示区的至少一个第一像素电路连接，第二子数据线与第二子显示区的至少一个第一像素电路或至少一个第二像素电路连接，第三子数据线与第三子显示区的至少一个第二像素电路 连接。在另一些示例中，第一子显示区设置有多个第一像素电路和多个第二像素电路，第二子显示区设置有多个第一像素电路和多个第二像素电路，第三子显示区设置有多个第一像素电路和多个第二像素电路，第一数据线的第一子数据线与第一子显示区的至少一个第一像素电路或第二像素电路连接，第二子数据线与第二子显示区的至少一个第一像素电路或第二像素电路连接，第三子数据线与第三子显示区的至少一个第二像素电路连接。然而，本实施例对此并不限定。
在一些示例中，第一方向平行于显示区域内的子像素列方向，第二方向平行于显示区域内的子像素行方向。第一方向垂直于第二方向。
本实施例提供的显示基板，第二显示区在第一方向上将第一子显示区和第二子显示区隔断，通过在第三子显示区域设置第三子数据线实现第一子显示区的第一子数据线和第二子显示区的第二子数据线的连接，可以实现数据信号的传输，避免在第二显示区布线而影响第二显示区的光透过率，从而提高显示效果。
在一些示例性实施方式中，第一子数据线和第二子数据线均沿第一方向延伸。例如，一条第一数据线包括的第一子数据线和第二子数据线的延伸线可以重合。然而，本实施例对此并不限定。
在一些示例性实施方式中，第三子数据线至少包括：第一线段和第二线段，第一线段沿第二方向延伸，第二线段沿第一方向延伸。第一线段的一端延伸到第一子显示区与第一子数据线连接，第一线段的另一端与第二线段连接。第二线段与第三子显示区的至少一个第二像素电路连接。然而，本实施例对此并不限定。在一些示例中，第三子数据线可以包括：第一线段、第二线段和第三线段，第一线段和第三线段沿第二方向延伸，第二线段沿第一方向延伸；第一线段的一端延伸到第一子显示区与第一子数据线连接，第一线段的另一端在第三子显示区与第二线段连接；第三线段的一端延伸到第二子显示区与第二子数据线连接，第三线段的另一端在第三子显示区与第二线段连接。
在一些示例性实施方式中，第一子数据线、第二子数据线、以及第三子数据线的第二线段可以为同层结构，第三子数据线的第一线段与第二线段可 以为异层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一子数据线和第二子数据线可以为同层结构，第三子数据线与第一子数据线可以为异层结构。在一些示例中，第三子数据线的第一线段和第二线段可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，衬底基板还包括：边框区域。边框区域位于第一显示区和第二显示区的外围。边框区域设置有至少一条数据连接线，数据连接线连接在第三子数据线和第二子数据线之间。在本示例性实施方式中，通过在边框区域设置数据连接线实现第三子数据线和第二子数据线之间的连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，数据连接线至少包括：第一子数据连接线、第二子数据连接线和第三子数据连接线。第二子数据连接线连接在第一子数据连接线和第三子数据连接线之间，第一子数据连接线与第三子数据线连接，第三子数据连接线与第二子数据线连接。在本示例中，数据连接线包括多个依次连接的子数据连接线。
在一些示例性实施方式中，第一子数据连接线和第三子数据连接线沿第一方向延伸，第二子数据连接线沿第二方向延伸。
在一些示例性实施方式中，第一子数据连接线和第三子数据连接线为同层结构，第一子数据连接线和第二子数据连接线为异层结构。然而，本实施例对此并不限定。例如，第一子数据连接线、第二子数据连接线和第三子数据连接线可以为一体结构。
在一些示例性实施方式中，第二子数据连接线与第一子数据线和第二子数据线为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示基板还包括：多个第二发光元件，位于第二显示区。多个第二像素电路中的至少一个像素电路与多个第二发光元件中的至少一个发光元件通过导电线连接。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示基板至少包括：设置在衬底基板上的半导体层、第一导电层、第二导电层、第三导电 层和第四导电层。半导体层至少包括：像素电路的多个晶体管的有源层。第一导电层至少包括：像素电路的多个晶体管的栅极和存储电容的第一电极。第二导电层至少包括：存储电容的第二电极。第三导电层至少包括：第一电源线。第四导电层至少包括：连接像素电路和发光元件的第一连接电极。在一些示例中，像素电路可以为7T1C结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一子数据线、第二子数据线、第三子数据线的第二线段位于第三导电层，第三子数据线的第一线段位于第四导电层。或者，第一子数据线、第二子数据线位于第三导电层，第三子数据线位于第四导电层。然而，本实施例对此并不限定。
下面通过多个示例对本实施例的显示基板进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，如图1所示，显示基板的衬底基板包括：显示区域和位于显示区域外围的边框区域R3。边框区域R3围绕在显示区域的四周。显示区域包括：第一显示区R1和第二显示区R2，第一显示区R1至少部分包围第二显示区R2。例如，图1示出的第二显示区R2位于显示基板的顶部正中间位置，第二显示区R2的一侧与边框区域R3相邻。然而，本实施例对此并不限定。例如，第二显示区R2可以位于显示基板的左上角位置或右上角位置等其他位置。
在一些示例性实施方式中，如图1所示，显示区域可以为矩形，例如，圆角矩形。第二显示区R2可以为圆形。然而，本实施例对此并不限定。例如，第二显示区R2可以为矩形、椭圆形等其他形状。
在一些示例性实施方式中，第一显示区R1可以为非透光显示区，第二显示区R2可以为透光显示区。即，第一显示区R1不透光，第二显示区R2可透光。例如，感光传感器(如，摄像头)等硬件在显示基板上的正投影可以位于显示基板的第二显示区R2内。本示例的显示基板无需打孔，在确保显示基板的实用性的前提下，可以使真全面屏成为可能。
在一些示例性实施方式中，如图1所示，第一显示区R1包括：沿第一方向D1上位于第二显示区R2相对两侧的第一子显示区R11和第二子显示区、以及沿第二方向D2上位于第二显示区R2相对两侧的第三子显示区。第二子显示区包括第二子显示第一子区R12a和第二子显示第二子区R12b，第 三子显示区包括：第三子显示第一子区R13a和第三子显示第二子区R13b。第一子显示区R11位于第二显示区R2的下侧，第二子显示区位于第二显示区R2的上侧。第一子显示区R11和第二子显示区在第一方向D2上被第二显示区R2隔开，第二子显示区在第二方向D2上被第二显示区R2隔开，即第二子显示第一子区R12a和第二子显示第二子区R12b在第二方向D2上位于第二显示区R2的相对两侧。然而，本实施例对此并不限定。例如，第二子显示第一子区R12a和第二子显示第二子区R12b在第二方向D2上可以连通。第三子显示第一子区R13a位于第二显示区R2的左侧，第三子显示第二子区R13b位于第二显示区R2的右侧。第三子显示第一子区R13a和第三子显示第二子区R13b之间被第一子显示区R11、第二显示区R2和第二子显示区隔开。第三子显示第一子区R13a与第一子显示区R11及第二子显示第一子区R12a连通，第三子显示第二子区R13b与第一子显示区R11及第二子显示第二子区R12b连通。其中，第一方向D1与第二方向D2交叉，例如，第一方向D1垂直于第二方向D2。在一些示例中，第一方向D1平行于子像素列方向，第二方向D2平行于子像素行方向。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示基板可以包括设置在衬底基板上的多个子像素。至少一个子像素包括像素电路和发光元件。像素电路配置为驱动发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。例如，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：第一极(例如，阳极)、第二极(例如，阴极)以及设置在第一极和第二极之间的有机发光层。其中，第一极可以与像素电路连接。然而，本实施例对此并不限定。在一些示例中，发光元件可以为量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微发光二极管(Micro-LED，Micro Light Emitting Diode)、或者迷你二极管(Mini-LED)。
在一些示例性实施方式中，一个像素单元可以包括三个子像素(例如，一个红色子像素R、一个蓝色子像素B，以及一个绿色子像素G)，三个子像素可以采用水平并列、竖直并列或品字方式排列。例如，一个像素单元可 以包括四个子像素(一个红色子像素R、一个蓝色子像素B、一个绿色子像素G以及一个白色子像素)，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本公开实施例在此不做限定。
在一些示例性实施方式中，为了提高第二显示区R2的光透过率，可以在第二显示区R2仅设置发光元件，而将驱动第二显示区R2的发光元件的像素电路设置在第一显示区R1。即，通过发光元件和像素电路分离设置的方式来提高第二显示区R2的光透过率。在本示例中，在第二显示区R2，不设置像素电路。
图2为本公开至少一实施例的显示基板的局部结构示意图。在一些示例性实施方式中，如图2所示，显示基板包括：位于第一显示区R1的多个第一像素电路10、多个第二像素电路20和多个第一发光元件30，以及位于第二显示区R2的多个第二发光元件40。多个第二像素电路20可以间隔分布于多个第一像素电路10之间，例如，在第一方向上相邻两个第二像素电路20之间排布多个第一像素电路10。多个第一像素电路10中的至少一个第一像素电路10可以与多个第一发光元件30中的至少一个第一发光元件30连接，且至少一个第一像素电路10在衬底基板上的正投影与至少一个第一发光元件30在衬底基板上的正投影可以至少部分交叠。第一像素电路10可以配置为给所连接的第一发光元件30提供驱动信号，以驱动第一发光元件30发光。多个第二像素电路20中的至少一个第二像素电路20可以与多个第二发光元件40中的至少一个第二发光元件40通过导电线L连接。第二像素电路20可以配置为给所连接的第二发光元件40提供驱动信号，以驱动第二发光元件40发光。由于第二发光元件40与第二像素电路20位于不同区域，至少一个第二像素电路20在衬底基板上的正投影与至少一个第二发光元件40在衬底基板上的正投影不存在重叠部分。
在一些示例性实施方式中，第二显示区R2的第二发光元件40的密度可以约等于第一显示区R1的第一发光元件30的密度。即，第二显示区R2的分辨率可以与第一显示区R1的分辨率大致相同。然而，本实施例对此并不限定。例如，第二发光元件40的密度可大于或小于第一发光元件30的密度。即，第二显示区R2的分辨率可大于或小于第一显示区R1的分辨率。
在一些示例性实施方式中，第二发光元件40的发光面积可以小于第一发光元件30的发光面积。即，第一发光元件30的发光面积大于第二区域发光元件40的发光面积。其中，发光元件的发光面积可以对应于像素定义层的开口的面积。在一些示例中，在第二显示区R2中，相邻的第二发光元件40之间设有透光区。例如，多个透光区彼此相连，形成被多个第二发光元件40间隔的连续透光区。导电线L可以采用透明导电材料制作以尽可能地提高透光区的透光率。
在一些示例性实施方式中，在第一显示区R1内，可以通过减小第一像素电路10在第二方向D2上的尺寸来获得设置第二像素电路20的区域。例如，第一像素电路10在第二方向D2上的尺寸可以小于第一发光元件30在第二方向D2上的尺寸。第二方向D2例如为子像素行方向，但不限于此。在另一些实施例中，第二方向D2可以为子像素列方向。本示例性实施方式以第二方向D2为子像素行方向为例进行说明。例如，第一像素电路10和第二像素电路20在第二方向D2上的尺寸可以相同，且每个像素电路在第二方向D2上的尺寸与第一发光元件30在第二方向D2上的尺寸可以相差约4微米(μm)。每个像素电路在第一方向D1上的尺寸与第一发光元件30在第一方向D1上的尺寸大致相同。其中，第一方向D1与第二方向D2垂直。
在一些示例性实施方式中，第一显示区R1的第一子显示区R11、第二子显示区、以及第三子显示区均设置有多个第一像素电路10和第二像素电路20。第二显示区R2内的第二发光元件40可以与第三子显示区内的第二像素电路20连接。第一显示区R1内未与发光元件连接的第二像素电路20可以称为虚拟(Dummy)像素电路。然而，本实施例对此并不限定。例如，可以在第一显示区R1的第三子显示区设置第一像素电路10和排布在多个第一像素电路10之间的第二像素电路20，第一子显示区R11和第二子显示区可以仅设置第一像素电路10，不设置第二像素电路20。或者，可以在第一显示区R1的第三子显示区和第二子显示区设置第一像素电路10和排布在多个第一像素电路10之间的第二像素电路20，第一子显示区R11可以仅设置第一像素电路10，不设置第二像素电路20。
图3A至图3C为本公开至少一实施例的第一显示区的局部结构示意图。 为了进一步体现出压缩像素电路后，多出多列像素电路，图3A示出了第一显示区R1的子像素的一种结构示意图。图3B示出了图3A中第一显示区R1的部分结构(仅包括像素电路)的示意图，图3C示出了图3A中第一显示区R1的部分结构(仅包括发光元件)的示意图。
在一些示例性实施方式中，如图3A至图3C所示，像素电路在第二方向D2上的尺寸较发光元件在第二方向D2上的尺寸小，如此，可以使得从右往左第2列和第9列的像素电路不连接任何第一发光元件30，属于多出列像素电路，其可以作为第二像素电路20以连接第二显示区R2内的第二发光元件40，或者仅作为不使用的第二像素电路20(即虚拟像素电路)。如图3C所示，任一第一发光元件30可以为RG1BG2共4种发光元件的一种。第一发光元件30的第一极E1可以通过第二转接电极CE2与第一像素电路10的第一转接电极CE1连接。R表示发红光的发光元件，G1表示发绿光的发光元件，B表示发蓝光的发光元件，G2表示发绿光的发光元件。至少一个第二像素电路20可以具有第一转接电极，至少一个第二发光元件40可以具有第二转接电极。例如，至少一个第二像素电路20和至少一个第二发光元件40通过导电线L连接可以包括：导电线L分别连接至少一个第二像素电路20的第一转接电极以及至少一个第二发光元件40的第二转接电极。为了具有充足的空间用来设置导电线L，同一行子像素中的第一转接电极和第二转接电极的轴线可以位于一条直线上。然而，本实施例对此并不限定。
在一些示例性实施方式中，图3C所示的子像素排列中，一个重复单元RP包括在第一方向D1上排列的两个绿色(G)子像素和分设在该两个绿色子像素在第二方向D2上的两侧的红色(R)子像素和蓝色(B)子像素。其中红色子像素和绿色子像素可以构成一个像素单元，并借用与其相邻的另一重复单元中的蓝色子像素构成一个虚拟像素以进行显示，其中蓝色子像素和绿色子像素可以构成一个像素单元，并借用与其相邻的另一重复单元中的红色子像素构成一个虚拟像素以进行显示。然而，本实施例对此并不限定。
图4为本公开至少一实施例的显示基板的数据线的排布示意图。图5为本公开至少一实施例的显示基板的数据线的局部排布示意图。图4和图5中仅以若干条数据线为例进行示意。图4中仅以若干个第一像素电路10和第二 像素电路20为例进行示意。在本示例中，显示基板在第二方向D2上具有中轴线OO’，显示基板可以关于中轴线OO’对称。下面以显示基板的左半部分的数据线排布为例进行说明。
在一些示例性实施方式中，边框区域R3包括驱动芯片区域，驱动芯片区域可以包括集成电路，配置为与显示区域的多条数据线连接。第二子显示区可以位于第二显示区R2远离驱动芯片区域的一侧，第一子显示区R11位于第二显示区R2靠近驱动芯片区域的一侧。
在一些示例性实施方式中，如图1和图4所示，第一显示区R1设置有多条第一数据线。边框区域R3设置有多条数据连接线64。至少一条第一数据线与第一子显示区R11的至少一个像素电路连接，并通过至少一条数据连接线64与第二子显示区的第二子显示第一子区R12a的至少一个像素电路连接。例如，至少一条第一数据线与第一子显示区R11的一列第一像素电路和第二子显示第一子区R12a的一列第一像素电路连接。
在一些示例性实施方式中，如图1和图4所示，至少一条第一数据线包括：第一子数据线61、第二子数据线62和第三子数据线63。第三子数据线63连接在第一子数据线61和第二子数据线62之间。第一子数据线61位于第一子显示区R11并与第一子显示区R11的一列第一像素电路连接。第二子数据线62位于第二子显示区的第二子显示第一子区R12a并与第二子显示第一子区R12a的一列第一像素电路连接。第三子数据线63位于第三子显示区的第三子显示第一子区R13a，并延伸到第一子显示区R11与第一子数据线61连接，以及与边框区域R3的数据连接线64连接。第三子数据线63与第三子显示第一子区R13a中沿第一方向D1排布的多个第二像素电路连接。边框区域R3的数据连接线64与第二子显示第一子区R12a的第二子数据线62连接。在本示例中，通过第一子数据线61、第三子数据线63和数据连接线64可以将驱动芯片区域提供的数据信号传输至第二子数据线62，利用第三子数据线63在第三子显示区绕线后给第二子显示区的像素电路提供数据信号，可以避免数据线在第二显示区R2直接布线而影响第二显示区R2的光透过率，从而提高显示效果。
在一些示例性实施方式中，第一显示区R1设置有阵列排布的像素电路。 例如，第三子显示区设置有n1列像素电路，第一子显示区R11设置有n2列像素电路，第二子显示区共设置有n3列像素电路。在本示例中，n3可以小于n2。然而，本实施例对此并不限定。例如，n3可以等于n2。
在一些示例性实施方式中，如图4和图5所示，在第一子显示区R11内，第一子数据线61沿第一方向D1延伸，多条第一子数据线61沿第二方向D2依次排布。一条第一子数据线61可以与一列第一像素电路10连接，配置为将从驱动芯片区域引入的数据信号提供给对应的第一像素电路10。或者，一条第一子数据线61可以与一列第二像素电路连接。在第二子显示区内，第二子数据线62可以沿第一方向D1延伸，多条第二子数据线62沿第二方向D2依次排布。一条第二子数据线62可以与第二子显示区内的一列第一像素电路10或一列第二像素电路20连接。第一子数据线61和第二子数据线62被第二显示区R2隔断。在一些示例中，第一子数据线61和第二子数据线62可以为同层结构。
在一些示例性实施方式中，如图4和图5所示，在第三子显示区内，第三子数据线63包括：相互连接的第一线段631和第二线段632。第一线段631沿第二方向D2延伸，多条第一线段631沿第一方向D1依次排布。第二线段632沿第一方向D1延伸，多条第二线段632沿第二方向D2依次排布。第一线段631的一端延伸到第一子显示区R11与第一子数据线61连接，第一线段631的另一端在第三子显示区与第二线段632连接。第二线段632与第三子显示区内的多个沿第一方向D1排布的第二像素电路20连接。在一些示例中，第二线段632连接的多个第二像素电路20与第二显示区R2的第二发光元件40连接。然而，本实施例对此并不限定。例如，第二线段632连接的多个第二像素电路20可以为虚拟像素电路，即可以不与发光元件连接。在一些示例中，第一线段631和第二线段632可以为异层结构。例如，第二线段632与第一子数据线61可以为同层结构，第一线段631与第一子数据线61可以为异层结构。在一些示例中，第一线段631和第二线段632可以为一体结构，且与第一子数据线61为异层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4和图5所示，多条数据连接线64位于第二显示区R2远离驱动芯片区域的一侧，例如，位于上边框区域内。至少 一条数据连接线64包括：第一子数据连接线641、第二子数据连接线642和第三子数据连接线643。第一子数据连接线641和第三子数据连接线643沿第一方向D1延伸，第二子数据连接线642沿第二方向D2延伸。例如，多条第二子数据连接线642沿第二方向D2的长度可以相同。多条第一子数据连接线641和多条第三子数据连接线643沿第二方向D2依次排布，多条第二子数据连接线642沿第一方向D1依次排布。第二子数据连接线642分别与第一子数据连接线641和第三子数据连接线643连接。第一子数据连接线641与第三子数据线63的第二线段632连接，第三子数据连接线643与第二子数据线62连接。在一些示例中，第一子数据连接线641和第三子数据连接线643为同层结构，且与第二子数据连接线642为异层结构。第二子数据连接线642可以与第三子数据线63的第二线段632和第二子数据线62为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一子数据线61连接的第一像素电路所连接的第一发光元件与其对应的第三子数据线63连接的第二像素电路所连接的第二发光元件可以位于同一列，第一子数据线61连接的第一像素电路所连接的第一发光元件与其对应的第二子数据线62连接的第一像素电路所连接的第一发光元件可以位于同一列。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4和图5所示，多条第三子数据线63的第一线段631沿第一方向D1排布，越靠近第二显示区R2的第一线段631与越靠近中轴线OO’的第一子数据线61连接；越靠近第二显示区R2的第一线段631与越远离中轴线OO’的第二线段632连接。沿着远离第二显示区R2的第二方向D2，多条第二线段632在第一方向D2上的长度逐渐减小。沿着远离第二显示区R2的第一方向D1，多条第一线段631在第二方向D2上的长度逐渐减小。然而，本实施例对此并不限定。例如，沿着远离第二显示区R2的第一方向D1，多条第一线段631在第二方向D2上的长度不变。例如，沿着远离第二显示区R2的第二方向D2，多条第二线段632在第一方向D2上的长度逐渐增加。
在一些示例性实施方式中，第一显示区R1还设置有多条第二数据线71。多条第二数据线71均沿第一方向D1延伸，且沿着第二方向D2依次排布。 第一显示区R1内的第二数据线71无需进行绕线设计。至少一条第二数据线71可以与一列像素电路(第一像素电路或第二像素电路)连接。在第三子显示区内，针对一列第二像素电路20，一部分第二像素电路20与第三子数据线63的第二线段632连接，另一部分可以与第二数据线71连接，且第三子数据线63的第二线段632和第二数据线71断开。
下面对本实施例的像素电路进行举例说明。
图6A为本公开至少一实施例的像素电路的等效电路图。图6B为图6A所示的像素电路的工作时序图。
在一些示例性实施方式中，第一显示区R1的像素电路可以均为7T1C结构。然而，本实施例对此并不限定。例如，像素电路可以包括其他数目的晶体管和电容器，例如，可以为5T1C或6T1C等结构。
在一些示例性实施方式中，如图6A所示，像素电路均包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括第一极E1、第二极E2以及位于第一极E1和第二极E2之间的有机发光层。例如，第一极E1可以为阳极，第二极E2可以为阴极。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物 (LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图6A和图6B所示，显示基板包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供扫描信号SCAN。例如，在一行像素电路中，第二复位控制线RST2可以与扫描线GL相连，以被输入扫描信号SCAN。然而，本实施例对此并不限定。例如，第二复位控制线RST2可以被输入第二复位控制信号RESET2。例如，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。在本示例中，第n行像素电路连接的第一复位控制线RST1与第n-1行像素电路连接的第二复位控制线RST2可以为一体结构。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例中，第一初始信号线INIT1和第二初始信号线INIT2可以提供相同的初始信号。例如，第n行像素电路连接的第一初始信号线INIT1与第n-1行像素电路连接的第二初始信号线INIT2可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图6A所示，在本实施例提供的像素电路中，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL相连，数据写入晶体管T4的第一极与数据线DL相连，数据写入晶体管T4的第二 极与驱动晶体管T3的第一极相连。阈值补偿晶体管T2的栅极与扫描线GL相连，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极相连，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极相连。第一发光控制晶体管T5的栅极与发光控制线EML相连，第一发光控制晶体管T5的第一极与第一电源线PL1相连，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极相连。第二发光控制晶体管T6的栅极与发光控制线EML相连，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极相连，第二发光控制晶体管T6的第二极与发光元件EL的第一极E1相连。第一复位晶体管T1与驱动晶体管T3的栅极相连，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的第一极E1相连，并配置为对发光元件EL的第一电极E1进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1相连，第一复位晶体管T1的第一极与第一初始信号线INIT1相连，第一复位晶体管T1的第二极与驱动晶体管T3的栅极相连。第二复位晶体管T7的栅极与第二复位控制线RST2相连，第二复位晶体管T7的第一极与第二初始信号线INIT2相连，第二复位晶体管T7的第二极与发光元件EL的第一极E1相连。存储电容Cst的第一电极与驱动晶体管T3的栅极相连，存储电容Cst的第二电极与第一电源线PL1相连。在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图6B对图6A示意的像素电路的工作过程进行说明。以像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图6B所示，在一帧显示时间段，第一结构的像素电路的工作过程包括：第一阶段A1、第二阶段A2和第三阶段A3。
第一阶段A1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的初始信号Vinit被提供至第一节点N1，对第一节点N1进行 初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DT输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N2，并将数据线DT输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DT输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的初始信号Vinit提供至发光元件EL的第一极E1，对发光元件EL的第一极E1进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段A3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向 发光元件EL的第一极E1提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(VDD-Vdata+|Vth|)-Vth] 2＝K*[(VDD-Vdata)] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图7A为本公开至少一实施例的像素电路的平面示意图。图7B为图7A中沿P-P’方向的局部剖面示意图。其中，第一方向D1可以是子像素列的方向(垂直方向)，第二方向D2可以是子像素行的方向(水平方向)。
在一些示例性实施方式中，在平行于显示基板的平面内，显示基板设置有扫描线GL、发光控制线EML、第一复位控制线RST1、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线PL1、数据线DL以及像素电路。像素电路可以包括多个晶体管和存储电容Cst，多个晶体管可以包括驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一复位晶体管T1、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括在衬底基板50上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。在一些示例中，半导体层可以包括多个晶体管的有源层。第一导电层可以包括扫描线GL、第一复位控制线RST1、第二复位控制线RST2、发光控制线EML、存储电容Cst的第一电极、以及多个晶体管的栅极。第二导电层可以包括第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极、第一屏蔽电极SE1。第三导电层可以包括第一电源线PL1、数据线DL、多个晶体管的第一极和第二极。第四导电层可以包括： 第二屏蔽电极SE2、第一连接电极CE1。
在一些示例性实施方式中，如图7B所示，显示基板可以包括第一绝缘层51、第二绝缘层52、第三绝缘层53、第四绝缘层54和第五绝缘层55。第一绝缘层51设置在衬底基板50与半导体层之间，第二绝缘层52设置在半导体层和第一导电层之间，第三绝缘层53设置在第一导电层与第二导电层之间，第四绝缘层54设置在第二导电层与第三导电层之间，第五绝缘层55设置在第三导电层和第四导电层之间。在一些示例中，第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54可以为无机绝缘层，第五绝缘层55可以为有机绝缘层。然而，本实施例对此并不限定。
图7C为本公开至少一实施例的形成半导体层后的像素电路的示意图。在一些示例性实施方式中，如图7C所示，至少一个子像素的半导体层可以包括：第一复位晶体管T1的第一有源层T10、阈值补偿晶体管T2的第二有源层T20、驱动晶体管T3的第三有源层T30、数据写入晶体管T4的第四有源层T40、第一发光控制晶体管T5的第五有源层T50、第二发光控制晶体管T6的第六有源层T60、第二复位晶体管T7的第七有源层T70。其中，第一有源层T10至第七有源层T70为相互连接的一体结构。
在一些示例性实施方式中，如图7C所示，第一有源层T10的形状可以呈“n”字形，第二有源层T20的形状可以呈“7”字形，第三有源层T30的形状可以呈“几”字形，第四有源层T40的形状可以呈“1”字形，第五有源层T50、第六有源层T06、第七有源层T70的形状可以呈“L”字形。
在一些示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在一些示例中，如图7C所示，第一有源层T10的第二区T10-2同时作为第二有源层T20的第一区T20-1，第三有源层T30的第一区T30-1同时作为第四有源层T40的第二区T40-2和第五有源层T50的第二区T50-2，第三有源层T30的第二区T30-2同时作为第二有源层T20的第二区T20-2和第六有源层T60的第一区T60-1，第六有源层T60的第二区T60-2同时作为第七有源层T70的第二区T70-2。
图7D为本公开至少一实施例的形成第一导电层后的像素电路的示意图。在一些示例性实施方式中，如图7D所示，第一导电层至少包括：存储电容 Cst的第一电极Cst-1、沿第二方向D2延伸的扫描线GL、发光控制线EML、第一复位控制线RST1和第二复位控制线RST2。存储电容Cst的第一电极Cst-1可以为矩形状，矩形状的角部可以设置倒角，第一电极Cst-1在衬底基板上的正投影与驱动晶体管T3的第三有源层T30在衬底基板上的正投影存在重叠区域。存储电容Cst的第一电极Cst-1同时作为驱动晶体管T3的栅极T33。扫描线GL、数据写入晶体管T4的栅极T43、以及阈值补偿晶体管T2的栅极T23可以为一体结构。发光控制线EML、第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63可以为一体结构。第一复位控制线RST1、第一复位晶体管T1的栅极T13可以为一体结构。第二复位控制线RST12、第二复位晶体管T7的栅极T73可以为一体结构。
图7E为本公开至少一实施例的形成第二导电层后的像素电路的示意图。在一些示例性实施方式中，如图7E所示，第二导电层至少包括：第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极Cst-2、以及第一屏蔽电极BK。第一初始信号线INIT1和第二初始信号线INIT2均沿第二方向D2延伸，且在第一方向D1上位于存储电容Cst的第二电极Cst-2的相对两侧。存储电容Cst的第二电极Cst-2在衬底基板上的正投影位于扫描线GL和发光控制线EML在衬底基板上的正投影之间。存储电容Cst的第二电极Cst-2在衬底基板上的正投影与第一电极Cst-1在衬底基板上的正投影存在重叠区域。第二电极Cst-2上设置有开口OP1，开口OP1暴露出覆盖第一电极Cst-1的第三绝缘层53，且第一电极Cst-1在衬底基板上的正投影包含开口OP1在衬底基板上的正投影。在一些示例中，开口OP1配置为容置后续形成的第一过孔H1，第一过孔H1位于开口OP1内并暴露出第一电极Cst-1，使后续形成的第一复位晶体管T1的第二极与第一电极Cst-1连接。
在一些示例性实施方式中，如图7E所示，第一屏蔽电极SE1位于扫描线GL远离存储电容Cst的一侧。第一屏蔽电极SE1配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素电路的关键节点的电位，提高显示效果。
图7F为本公开至少一实施例的形成第三导电层后的像素电路的示意图。在一些示例性实施方式中，如图7F所示，第四绝缘层上形成有第一过孔H1、 多个第二过孔V1至V4、以及多个第三过孔K1至K6。第一过孔H1内的第四绝缘层54和第三绝缘层53被刻蚀掉，暴露出第一导电层的表面。多个第二过孔V1至V4内的第四绝缘层54被刻蚀掉，暴露出第二导电层的表面。多个第三过孔K1至K8内的第四绝缘层54、第三绝缘层53和第二绝缘层52被刻蚀掉，暴露出半导体层的表面。
在一些示例性实施方式中，如图7F所示，第三导电层可以包括：数据线DL、第一电源线PL1、第一复位晶体管T1的第一极T11、第二复位晶体管T7的第一极T71、阈值补偿晶体管T2的第一极T21、第二发光控制晶体管T6的第二极T62。数据线DL和第一电源线PL1沿第一方向D1延伸。
在一些示例性实施方式中，如图7F所示，数据线DL通过第三过孔K2与数据写入晶体管T4的第四有源层T40的第一区T40-1相连。第一电源线PL1通过第二过孔V1与存储电容Cst的第二电极Cst-2相连，通过第二过孔V2与第一屏蔽电极SE1相连，通过第三过孔K4与第一发光控制晶体管T5的第五有源层T50的第一区T50-1相连。阈值补偿晶体管T2的第一极T21通过第一过孔H1与存储电容Cst的第一电极Cst-1相连，通过第三过孔K1与阈值补偿晶体管T2的第二有源层T20的第一区T20-1相连。第二发光控制晶体管T6的第二极T62通过第三过孔K5与第二发光控制晶体管T6的第六有源层T60的第二区T60-2相连。第一复位晶体管T1的第一极T11通过第二过孔V3与第一初始信号线INIT1相连，通过第三过孔K3与第一复位晶体管T1的第一有源层T10的第一区T10-1相连。第二复位晶体管T7的第一极T71通过第三过孔K6与第二复位晶体管T7的第七有源层T70的第一区T70-1相连，第二复位晶体管T7的第一极T71还通过第二过孔V4与第二初始信号线INIT2连接。
图7G为本公开至少一实施例的形成第四导电层后的像素电路的示意图。在一些示例性实施方式中，第五绝缘层55上形成有多个第四过孔F1至F2。多个第四过孔F1至F2内的第五绝缘层55被去掉，暴露出第三导电层的表面。
在一些示例性实施方式中，第四导电层至少包括：第二屏蔽电极SE2和第一转接电极CE1。第一转接电极CE1通过第四过孔F1与第二发光控制晶 体管T6的第二极T62连接。第一转接电极CE1可以直接连接至第一区域发光元件，或者，与第一区域发光元件的第二转接电极连接，或者，通过导电线与第二区域发光元件的第二转接电极连接。第二屏蔽电极SE2通过第四过孔F2与第一电源线PL1相连。第二屏蔽电极SE2在衬底基板上的正投影与驱动晶体管T3在衬底基板上的正投影部分交叠。第二屏蔽电极SE2配置为屏蔽导电线对驱动晶体管T3的影响，提高显示效果。
图8A为本公开至少一实施例的第一子数据线和第三子数据线的第一线段的连接位置的示意图。图8B为本公开至少一实施例的第三子数据线的第一线段和第二线段的连接位置示意图。
在一些示例性实施方式中，如图8A所示，在第一子显示区R11内，第一子数据线61即为连接一列像素电路(例如，第一像素电路)的数据线DL。在第五绝缘层55形成有第四过孔F3。第三子数据线63的第一线段631位于第四导电层。第三子数据线63的第一线段631通过第五绝缘层55上形成的第四过孔F3与第一子数据线61连接。
在一些示例性实施方式中，如图8B所示，在第三子显示区(例如，第三子显示第一子区R13a)内，第三子数据线63的第二线段632即为连接沿第一方向D1排布的多个第二像素电路的数据线DL，第二数据线71即为连接一列第一像素电路的数据线DL。第三子数据线63的第二线段632位于第三导电层，第一线段631位于第四导电层。第一线段631通过第五绝缘层55上形成的第四过孔F4与第二线段632连接。第一线段631沿第二方向D2的长度大于第四过孔F3与F4之间的距离，以确保第一线段631与第二线段632和第一子数据线61的有效连接。
在一些示例性实施方式中，如图8A和图8B所示，第一线段631在衬底基板50上的正投影可以与第一初始信号线INIT1和第二复位控制线RST2在衬底基板50上的正投影存在交叠，且第一线段631在衬底基板50上的正投影可以位于第一初始信号线INIT1和第二复位控制线RST2在衬底基板50上的正投影之间。然而，本实施例对此并不限定。
图8C为本公开至少一实施例的第三子数据线的第二线段的截止位置示意图。在一些示例性实施方式中，如图8C所示，第三子数据线63的第二线 段632通过第四过孔F4与第二线段632连接之后，可以沿第一方向D1延伸直至某一位置截止。与第二线段632所连接的第二像素电路位于同一列的其余第二像素电路可以与一条第二数据线71连接，且第二线段632和第二数据线71断开。然而，本实施例对此并不限定。
图8D为本公开至少一实施例的第三子数据线与数据连接线的连接示意图。图8E为本公开至少一实施例的第二子数据线与数据连接线的连接示意图。
在一些示例性实施方式中，如图8D和图8E所示，第三子数据线63的第二线段632的一端沿第一方向D1延伸到第三子显示区(例如，第三子显示第一子区R13a)相邻的边框区域。第一子数据连接线641和第三子数据连接线643可以位于第四导电层，第二子数据连接线642可以位于第三导电层。第三子数据线63的第二线段632可以通过第五绝缘层55上形成的第四过孔F5与第一子数据连接线641的一端连接，第一子数据连接线641的另一端可以通过第五绝缘层55上形成的第四过孔F6与第二子数据连接线642的一端连接。第二子数据连接线642的另一端可以通过第五绝缘层55上形成的第四过孔F7与第三子数据连接线643的一端连接。第三子数据连接线643的另一端可以通过第五绝缘层55上形成的第四过孔F8与延伸到边框区域的第二子数据线62的一端连接。
在一些示例性实施方式中，如图8D和图8E所示，多条第二子数据连接线642均沿第二方向D2延伸，且沿第一方向D1依次排布。多条第二子数据连接线642沿第二方向D2的长度可以相同。多条第一子数据连接线641和多条第三子数据连接线643均沿第一方向D1延伸。多条第一子数据连接线641沿第二方向D2依次排布，多条第三子数据连接线643沿第二方向D2依次排布。多条第一子数据连接线641和多条第三子数据连接线643沿第一方向D1的长度可以大致相同。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8E所示，在第二子显示区(例如，第二子显示第一子区R12a)设置有多个第一像素电路10和多个第二像素电路20。图8E所示的一列第二像素电路20作为虚拟像素电路，未与第二显示区R2的第二发光元件连接，无需数据信号。在本示例中，第二子显示区内，与 第一像素电路10连接的第二子数据连接线62通过第三子数据连接线643与第二子数据连接线642连接，以接收数据信号。然而，本实施例对此并不限定。在一些示例中，当图8E所示的一列第二像素电路20与第二显示区R2的第二发光元件连接时，该列第二像素电路20连接的数据线也可以通过第三子数据连接线643与第二子数据连接线642连接，以接收数据信号。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层图案。
在一些示例性实施方式中，形成半导体层图案可以包括：在衬底基板50上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖衬底基板50的第一绝缘层51，以及设置在第一绝缘层51上的半导体层，如图7C所示。
在本次工艺后，显示基板包括设置在衬底基板50上的第一绝缘层51和设置在第一绝缘层51上的半导体层，半导体层可以包括像素电路的多个晶体管的有源层。在本示例性实施方式中，像素电路的第二复位晶体管的有源层与相邻像素电路的第一复位晶体管的有源层可以为一体结构。
(2)、形成第一导电层图案。
在一些示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的衬底基板50上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层52，以及设置在第二绝缘层52上的第一导电层图案。如图7D所示，第一导电层图案可以包括：像素电路的多个晶体管的栅极、第一复位控制线RST1、扫描线GL、发光控制线EML、存储电容Cst的第一电极Cst-1、第二复位控制线RST2。第一复位控制线RST1、第二复位控制线RST2、扫描线GL和发光控制线EML沿第二方向D2延伸，存储电容Cst的第一电极Cst-1位于扫描线GT和发光控制线EML之间。在一些示例中，第一导电层可以称为第一栅金属(GATE 1)层。
在一些示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成多个晶体管的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层T10至第七有源层T70的第一区和第二区均被导体化。
(3)、形成第二导电层图案。
在一些示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基50上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层53，以及设置在第三绝缘层53上的第二导电层图案。如图7E所示，第二导电层图案可以包括：第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极Cst-2、第一屏蔽电极SE1。在一些示例中，第二导电层可以称为第二栅金属(GATE 2)层。
(4)、形成第四绝缘层图案。
在一些示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述 图案的衬底基板50上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层54。如图7F所示，第四绝缘层上设置有多个第一过孔H1、多个第二过孔V1至V3以及多个第三过孔K1至K6。多个第一过孔内的第四绝缘层54和第三绝缘层53被刻蚀掉，暴露出第一导电层的表面，多个第二过孔内的第四绝缘层54被刻蚀掉，暴露出第二导电层的表面，多个第三过孔内的第四绝缘层54、第三绝缘层53和第二绝缘层52被刻蚀掉，暴露出半导体层的表面。
(5)、形成第三导电层图案。
在一些示例性实施方式中，形成第三导电层可以包括：在形成前述图案的衬底基板50上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层54上的第三导电层。如图7F、图8D和8E所示，第三导电层可以包括：位于第一显示区R1的第二数据线71、第一子数据线61、第二子数据线62、第三子数据线63的第二线段632、第一电源线PL1、像素电路的多个晶体管的第一极和第二极，以及位于边框区域R3的第二子数据连接线642。在一些示例中，第三导电层可以称为第一源漏金属(SD1)层。
(6)、形成第五绝缘层图案。
在一些示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的衬底基板50上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第三导电层的第五绝缘层55，如图7G所示。第五绝缘层55上形成有多个第四过孔F1至F8。多个第四过孔内的第五绝缘层55被去掉，暴露出第三导电层的表面。在一些示例中，第五绝缘层55可以称为平坦层。
(7)、形成第四导电层图案。
在一些示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的衬底基板50上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第五绝缘层55上的第四导电层。
如图7G所示，第四导电层图案可以包括：位于第一显示区R1的第一连接电极CE1、第二屏蔽电极SE、第三子数据线63的第一线段631，以及位于边框区域R3的第一子数据连接线641和第三子数据连接线643。第二屏蔽 电极SE通过第四过孔F2与第一电源线PL1连接，第一连接电极CE1通过第四过孔F1与第二发光控制晶体管T6的第二极T62连接。第三子数据线63的第一线段631通过第四过孔F3与第一子数据线61连接，通过第四过孔F4与第三子数据线63的第二线段632连接。第一子数据连接线641通过第四过孔F5与第二线段632连接，通过第四过孔F6与第二子数据连接线642连接。第三子数据连接线643通过第四过孔F7与第二子数据连接线642连接，通过第四过孔F8与第二子数据线62连接。在一些示例中，第四导电层可以称为第二源漏金属(SD2)层。
在一些示例性实施方式中，后续制备流程可以包括：形成导电线层。在一些示例中，连接第一显示区的第二像素电路和第二显示区的第二发光元件的多条导电线可以为同层结构。形成导电线层可以包括：在形成第四导电层的衬底基板上涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第四导电层的第六绝缘层；然后，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第六绝缘层上的导电线层。第一显示区R1的第二像素电路的第一连接电极CE1与导电线连接，导电线可以从第一显示区R1延伸到第二显示区R2，以便与第二显示区R2的第二发光元件连接。然而，本实施例对此并不限定。在一些示例中，连接第一显示区R1的第二像素电路和第二显示区R2的第二发光元件的多条导电线可以为异层结构。或者，至少一条导电线可以由位于不同导电线层的多个导电线段连接形成。
在一些示例性实施方式中，在形成导电线层之后的制备流程可以包括：形成覆盖导电线层的平坦层；沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在平坦层上的阳极；涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件。
在一些示例性实施方式中，衬底基板50可以是柔性衬底基板，或者可以是刚性衬底基板。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些示例中，柔性衬底基板可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层51称为缓冲(Buffer)层，用于提高衬底基板的抗水氧能力，第二绝缘层52和第三绝缘层53称为栅绝缘(GI)层，第四绝缘层54称为层间绝缘(ILD)层。平坦层可以采用有机材料。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。有源层可以采用多晶硅(p-Si)，即本实施例适用于LTPS薄膜晶体管。然而，本实施例对此并不限定。例如，像素电路中的晶体管可以均采用氧化物薄膜晶体管。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，像素电路中的第二复位晶体管可以连接第二初始信号线。例如，像素电路可以包括其他数量的晶体管和存储电容，比如，7T2C结构、6T1C结构、6T2C结构或者9T2C结构、或者晶体管的数目小于7个。例如，第一子数据线、第二子数据线、第二数据线、第三子数据线的第二线段、第二子 数据连接线可以位于第四导电层，第三子数据线的第一线段、第一子数据连接线和第三子数据连接线可以位于第三导电层。然而，本实施例对此并不限定。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图9为本公开至少一实施例的显示基板的数据线的另一示意图。在一些示例性实施方式中，如图9所示，第三子数据线63的第一线段和第二线段为一体结构。数据连接线64的第一子数据连接线、第二子数据连接线和第三子数据连接线可以为一体结构。数据连接线64连接在第三子数据线63和第二子数据线62之间，第三子数据线63与第一子数据线61连接。在一些示例中，第一子数据线61和数据连接线64可以位于第三导电层，第三子数据线63和第二子数据线62可以位于第四导电层。然而，本实施例对此并不限定。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图10为本公开至少一实施例的显示基板的数据线的另一排布示意图。在一些示例性实施方式中，如图10所示，第三子数据线63包括：第一线段631、第二线段632和第三线段633。第二线段632与第三子显示区的沿第一方向D1设置的多个第二像素电路连接。第二线段632分别与第一线段631和第三线段633连接。第一线段631和第三线段633沿第二方向D2延伸，第二线段632沿第一方向D1延伸。第一线段631延伸到第一子显示区R11，与第一子显示区R11的第一子数据线61连接。第三线段632延伸到第二子显示区R12a，与第二子显示区R12a的第二子数据线62连接。在一些示例中，第一子数据线61、第二子数据线62和第二线段632可以位于第三导电层，第一线段631和第三线段633可以位于第四导电层。然而，本实施例对此并不限定。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图11为本公开至少一实施例的显示基板的另一示意图。在一些示例性实施方式中，如图11所示，第二显示区R2位于显示基板的左半部分。第一显示区R1包括：第一子显示区R11、第二子显示区R12和第三子显示区R13。第一子显示区R11和第二子显示区R12位于第二显示区R2沿第一方向D1的相对两侧。第一子显示区R11和第二子显示区R12在第一方向D1上被第二显示区R2隔开。第三子显示区R13位于第二显示区R2的一侧，例如位于第二显示区R2的右侧。第一子显示区R11的第一子数据线61可以通过第三子显示区R13的第三子数据线63和边框区域R3的数据连接线64与第二子显示区R12的第二子数据线62连接，以实现向第二子显示区R12的像素电路(例如，第一像素电路，或者第一像素电路和第二像素电路)提供数据信号。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图12为本公开至少一实施例的显示基板的另一示意图。在一些示例性实施方式中，如图12所示，第二显示区R2可以为矩形，且位于显示基板的中部区域。第一显示区R1包括在第一方向D1上位于第二显示区R2相对两侧的第一子显示区R11和第二子显示区R12、以及在第二方向D2上位于第二显示区R2相对两侧的第三子显示区。第三子显示区包括：第三子显示第一子区R13a和第三子显示第二子区R13b。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
本公开实施例还提供一种显示基板的制备方法，包括：在衬底基板的第一显示区形成多个像素电路、多个第一发光元件以及至少一条第一数据线。第一显示区至少部分包围第二显示区。第一显示区包括：沿第一方向上位于第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于第二显示区至少一侧的第三子显示区；第一方向与第二方向交叉。多个像素电路包括：多个第一像素电路和多个第二像素电路，多个第二像素电路分 布在多个第一像素电路之间。多个第一像素电路中的至少一个像素电路与多个第一发光元件中的至少一个发光元件连接。第一数据线包括：第一子数据线、第二子数据线和第三子数据线；第三子数据线与第一子数据线和第二子数据线连接。第一子数据线位于第一子显示区并与第一子显示区的像素电路连接，第二子数据线位于第二子显示区并与第二子显示区的像素电路连接，第三子数据线位于第三子显示区并与第三子显示区的至少一个第二像素电路连接。
关于本实施例的显示基板的制备方法可以参照前述实施例的说明，故于此不再赘述。
图13为本公开至少一实施例的显示装置的示意图。如图13所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，所述第一显示区至少部分包围所述第二显示区，所述第一显示区包括：沿第一方向上位于所述第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于所述第二显示区至少一侧的第三子显示区，所述第一方向与所述第二方向交叉；
    多个像素电路和多个第一发光元件，位于所述第一显示区；所述多个像素电路包括：多个第一像素电路和多个第二像素电路，所述多个第二像素电路分布在所述多个第一像素电路之间；所述多个第一像素电路中的至少一个像素电路与所述多个第一发光元件中的至少一个发光元件连接；
    至少一条第一数据线，位于所述第一显示区；所述第一数据线包括：第一子数据线、第二子数据线和第三子数据线；所述第三子数据线与所述第一子数据线和所述第二子数据线连接；
    所述第一子数据线位于所述第一子显示区并与所述第一子显示区的像素电路连接，所述第二子数据线位于所述第二子显示区并与所述第二子显示区的像素电路连接，所述第三子数据线位于所述第三子显示区并与所述第三子显示区的至少一个第二像素电路连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一子数据线和所述第二子数据线均沿所述第一方向延伸。
  3. 根据权利要求1或2所述的显示基板，其中，所述第三子数据线至少包括：第一线段和第二线段，所述第一线段沿所述第二方向延伸，所述第二线段沿所述第一方向延伸；
    所述第一线段的一端延伸到所述第一子显示区与所述第一子数据线连接，所述第一线段的另一端与所述第二线段连接；
    所述第二线段与所述第三子显示区的至少一个第二像素电路连接。
  4. 根据权利要求3所述的显示基板，其中，所述第一子数据线、所述第二子数据线、以及所述第三子数据线的所述第二线段为同层结构，所述第三子数据线的所述第一线段与所述第二线段为异层结构。
  5. 根据权利要求1或2所述的显示基板，其中，所述第一子数据线和所述第二子数据线为同层结构，所述第三子数据线与所述第一子数据线为异层结构。
  6. 根据权利要求1至5中任一项所述的显示基板，其中，所述衬底基板还包括：边框区域，所述边框区域位于所述第一显示区和所述第二显示区的外围；
    所述边框区域设置有至少一条数据连接线，所述数据连接线连接在所述第三子数据线和所述第二子数据线之间。
  7. 根据权利要求6所述的显示基板，其中，所述数据连接线至少包括：第一子数据连接线、第二子数据连接线和第三子数据连接线；
    所述第二子数据连接线连接在所述第一子数据连接线和所述第三子数据连接线之间，所述第一子数据连接线与所述第三子数据线连接，所述第三子数据连接线与所述第二子数据线连接。
  8. 根据权利要求7所述的显示基板，其中，所述第一子数据连接线和所述第三子数据连接线沿所述第一方向延伸，所述第二子数据连接线沿所述第二方向延伸。
  9. 根据权利要求7或8所述的显示基板，其中，所述第一子数据连接线和所述第三子数据连接线为同层结构，所述第一子数据连接线和所述第二子数据连接线为异层结构。
  10. 根据权利要求9所述的显示基板，其中，所述第二子数据连接线与所述第一子数据线和所述第二子数据线为同层结构。
  11. 根据权利要求1至10中任一项所述的显示基板，还包括：
    多个第二发光元件，位于所述第二显示区；
    多个第二像素电路中的至少一个像素电路与所述多个第二发光元件中的至少一个发光元件通过导电线连接。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板至少包括：设置在所述衬底基板上的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；
    所述半导体层至少包括：所述像素电路的多个晶体管的有源层；
    所述第一导电层至少包括：所述像素电路的多个晶体管的栅极和存储电容的第一电极；
    所述第二导电层至少包括：所述像素电路的存储电容的第二电极；
    所述第三导电层至少包括：第一电源线；
    所述第四导电层至少包括：连接所述像素电路与发光元件的第一连接电极。
  13. 根据权利要求12所述的显示基板，其中，所述第一子数据线、所述第二子数据线、以及所述第三子数据线的第二线段位于所述第三导电层，所述第三子数据线的第一线段位于所述第四导电层；或者，所述第一子数据线、以及所述第二子数据线位于所述第三导电层，所述第三子数据线位于所述第四导电层。
  14. 一种显示装置，包括：如权利要求1至13中任一项所述的显示基板。
  15. 一种显示基板的制备方法，包括：
    在衬底基板的第一显示区形成多个像素电路、多个第一发光元件以及至少一条第一数据线；
    所述第一显示区至少部分包围第二显示区；所述第一显示区包括：沿第一方向上位于所述第二显示区相对两侧的第一子显示区和第二子显示区、以及沿第二方向上位于所述第二显示区至少一侧的第三子显示区；所述第一方向与所述第二方向交叉；所述多个像素电路包括：多个第一像素电路和多个第二像素电路，所述多个第二像素电路分布在所述多个第一像素电路之间；所述多个第一像素电路中的至少一个像素电路与所述多个第一发光元件中的至少一个发光元件连接；所述第一数据线包括：第一子数据线、第二子数据线和第三子数据线；所述第三子数据线与所述第一子数据线和所述第二子数据线连接；所述第一子数据线位于所述第一子显示区并与所述第一子显示区的像素电路连接，所述第二子数据线位于所述第二子显示区并与所述第二子显示区的像素电路连接，所述第三子数据线位于所述第三子显示区并与所述第三子显示区的至少一个第二像素电路连接。
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