WO2024040389A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024040389A1
WO2024040389A1 PCT/CN2022/113940 CN2022113940W WO2024040389A1 WO 2024040389 A1 WO2024040389 A1 WO 2024040389A1 CN 2022113940 W CN2022113940 W CN 2022113940W WO 2024040389 A1 WO2024040389 A1 WO 2024040389A1
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WIPO (PCT)
Prior art keywords
light
line
substrate
voltage power
area
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PCT/CN2022/113940
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English (en)
French (fr)
Inventor
崔宏达
王琦伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/113940 priority Critical patent/WO2024040389A1/zh
Publication of WO2024040389A1 publication Critical patent/WO2024040389A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display panel, including: a display area, the display area including: a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, the conventional display area including a first area, a second area and a third area.
  • At least one circuit unit in the first area is connected to the light-emitting device in the light-transmitting display area.
  • At least one circuit unit in the third area includes a data connection line and is located in the first area.
  • the high-voltage power line located in the second area is the first high-voltage power line
  • the high-voltage power line located in the second area is the second high-voltage power line
  • the high-voltage power line located in the third area is the third high-voltage power line
  • the second high-voltage power supply line includes: a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected to each other.
  • the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base, so The first high-voltage power supply line and the second sub-high-voltage power supply line are arranged on the same layer, and the third high-voltage power supply line and the first sub-high-voltage power supply line are arranged on the same layer.
  • the data connection line includes: a first connection line connected to each other and a second connection line extending in the second direction, and the first connection line is located on a side of the third high-voltage power line close to the substrate. , the second connection line and the first high-voltage power line are arranged on the same layer;
  • the orthographic projection of the first connection line on the substrate and the orthographic projection of the data signal line on the substrate at least partially overlap, and the orthographic projection of the second connection line on the substrate and the third high-voltage power supply line on the substrate orthographic projections at least partially overlap.
  • the first connection line includes: a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, and the first data connection portion is connected to the second data connection portion respectively.
  • the data connection part is connected to the second connection line, and the first direction and the second direction intersect;
  • the orthographic projection of the first data connection portion on the substrate at least partially overlaps the orthographic projection of the data signal line on the substrate.
  • the length of the second sub-high-voltage power supply line along the first direction is less than the length of the first sub-high-voltage power supply line along the first direction, and the orthographic projection of the second sub-high-voltage power supply line on the substrate is the same as the length of the first sub-high-voltage power supply line. Orthographic projections of a high-voltage power line on the substrate at least partially overlap.
  • the lengths of the first high-voltage power supply line, the first sub-high-voltage power supply line, and the third high-voltage power supply line along the first direction are approximately equal, and the lengths of the first high-voltage power supply line and the third high-voltage power supply line are approximately equal in length along the first direction.
  • the shape of the power supply line, the shape of the first sub-high voltage power supply line and the shape of the third high voltage power supply line are substantially the same.
  • the length of the second sub-high-voltage power supply line along the first direction is approximately equal to the length of the second connection line along the first direction, and the shape of the second sub-high-voltage power supply line is the same as the length of the second sub-high-voltage power supply line.
  • the shapes of the two connecting lines are roughly the same.
  • the overlap area between the orthographic projection of the second sub-high-voltage power supply line on the substrate and the orthographic projection of the first sub-high-voltage power supply line on the substrate is larger than the area of the orthographic projection of the second connection line on the substrate and the orthographic projection of the first sub-high-voltage power supply line on the substrate.
  • the area of the overlapping area of the orthographic projections of the three high-voltage power lines on the substrate is larger than the area of the orthographic projection of the second connection line on the substrate and the orthographic projection of the first sub-high-voltage power supply line on the substrate.
  • the light-emitting device includes: an anode, an organic light-emitting layer and a cathode; the display panel further includes: a plurality of first anode connection lines extending along a first direction, the first anode connection lines are connected to The third high-voltage power supply line is arranged on the same layer and is configured to connect at least one circuit unit in the first area and the anode of the light-emitting device located in the light-transmitting display area.
  • the light-transmitting display area includes: a central area and an edge area surrounding the central area; the display panel further includes: a second anode connection line, the second anode connection line Located on the side of the first high-voltage power line away from the base;
  • the first anode connection line is configured to connect at least one circuit unit in the first area and an anode of the light-emitting device located in the edge area
  • the second anode connection line is configured to connect an anode of the light-emitting device in the edge area.
  • the first anode connection line includes a metal signal line
  • the second anode connection line includes a transparent conductive signal line
  • the light-emitting structure layer includes: a plurality of light-emitting units, at least one light-emitting unit includes: a first light-emitting device, a second light-emitting device, and a third light-emitting device, and different light-emitting devices emit light of different colors, so The first light-emitting device and the second light-emitting device emit red or blue light, and the third light-emitting device emits green light;
  • the length of the first anode connecting line connected to the third light-emitting device of the same light-emitting unit along the first direction is smaller than the length of the first anode connected to the first light-emitting device and the second light-emitting device of the same light-emitting unit. The length of the connecting line along the first direction.
  • the length of the first anode connection line connected to any third light-emitting device located in the edge area along the first direction is smaller than the length of the first anode connection line connected to any first light-emitting device located in the edge area.
  • the length of the first anode connection line connected to any second light-emitting device located in the edge region along the first direction is smaller than the length of the first anode connection line connected to any second light-emitting device located in the edge region along the first direction.
  • the edge area accounts for about 3% to 8% of the area of the light-transmitting display area, or the edge area includes a number of light-emitting units that is 5 times the number of light-emitting units in the light-transmitting display area. % to 10%.
  • the pixel circuit at least includes a capacitor and a plurality of transistors, the capacitor includes: a first plate and a second plate; the display panel includes a semiconductor layer, a first Insulating layer, first conductive layer, second insulating layer, second conductive layer, third insulating layer, third conductive layer, fourth insulating layer, fourth conductive layer, first flat layer, fifth conductive layer;
  • the semiconductor layer at least includes active layers of a plurality of transistors; the first conductive layer at least includes gate electrodes of a plurality of transistors and a first plate of a capacitor; the second conductive layer at least includes a second plate of a capacitor.
  • the third conductive layer at least includes first and second poles of a plurality of transistors and first connection lines
  • the fourth conductive layer at least includes a first anode connection line, a first sub-high voltage power supply line and a third high voltage Power supply line
  • the fifth conductive layer at least includes: data signal line, first high-voltage power supply line, second sub-high-voltage power supply line and second connection line.
  • the pixel circuit includes: a writing transistor connected to a data signal line; the second plate of the capacitor located in the third region includes: a capacitor body part and an auxiliary capacitor connected to each other part, the shape of the capacitor main part and the second plate of the capacitor located in the first region and the second region are substantially the same; the orthographic projection of the auxiliary capacitor part on the substrate is consistent with the active layer of the writing transistor. Orthographic projections on the substrate at least partially overlap.
  • the third conductive layer further includes: a data connection block, the orthographic projection of the data connection block on the substrate at least partially overlaps the orthographic projection of the auxiliary capacitor part and the second connection line on the substrate;
  • the data connection blocks are respectively connected to the first connection line and the second connection line.
  • the data connection block and the second data connection part are located on the same side of the first data connection part and are electrically connected to the first data connection part;
  • An orthographic projection of the first data connection portion on the substrate at least partially overlaps an orthographic projection of the second plate of the capacitor on the substrate.
  • the pixel circuit further includes: a first light-emitting transistor and a second light-emitting transistor, the first light-emitting transistor is connected to the high-voltage power line, the second light-emitting transistor is connected to the anode of the light-emitting device, and the fourth conductive
  • the layer further includes: a first connection electrode, a second connection electrode, a third connection electrode and a fourth connection electrode;
  • the orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the writing transistor of at least one circuit unit located in the first to third regions on the substrate, and overlaps with the orthographic projection of the first electrode located on the substrate in the first region
  • the first electrode of the writing transistor is electrically connected to at least one circuit unit in the third region
  • the orthographic projection of the second connection electrode on the substrate is with the second electrode in at least one circuit unit located in the first to third regions.
  • the orthographic projection of the second electrode of the light-emitting transistor on the substrate at least partially overlaps with the second electrode of the second light-emitting transistor located in at least one circuit unit in the first region to the third region, and the third connection electrode is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first pole of the first light-emitting transistor located in at least one circuit unit in the first region on the substrate, and overlaps with the orthographic projection on the substrate in at least one circuit unit located in the first region.
  • the first electrode of the first light-emitting transistor is connected, and the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the data connection block on the substrate, and at least partially overlaps with the orthographic projection of the data connection block on the substrate. .
  • the fifth conductive layer further includes: a fifth connection electrode, an orthographic projection of the fifth connection electrode on the substrate at least partially overlaps an orthographic projection of the second connection electrode on the substrate, and overlaps with the orthographic projection of the second connection electrode on the substrate. Two connecting electrodes are connected.
  • the orthographic projection of the plurality of first anode connection lines on the substrate may at least partially overlap with the orthographic projection of the second plate of the capacitor and the anode of the connected light-emitting device on the substrate.
  • the orthographic projection of the data signal line on the substrate at least partially overlaps the orthographic projection of the first connection electrode on the substrate and is connected to the first connection electrode, and the orthographic projection of the first high-voltage power line on the substrate
  • the projection at least partially overlaps with the orthographic projection of the third connection electrode on the substrate and is connected to the third connection electrode.
  • the orthographic projection of the second connection line on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode on the substrate. , and connected to the fourth connection electrode.
  • a transparent conductive layer located on the side of the second flat layer away from the substrate is further included.
  • the transparent conductive layer includes a second anode connection line, and the second anode connection line and the fifth connection electrode are on the substrate.
  • the orthographic projections at least partially overlap and are connected to the fifth connection electrode.
  • the present disclosure also provides a display device, including: the above-mentioned display panel and a light-sensitive sensor, the light-sensitive sensor being located in the light-transmitting display area of the display panel
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display panel
  • Figure 3 is a schematic plan view of a display area in a display panel
  • Figure 4A is an equivalent circuit schematic diagram of a pixel circuit
  • Figure 4B is a working timing diagram of a pixel circuit
  • Figure 5A is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure.
  • Figure 5B is a cross-sectional view along the A-A direction of Figure 5A;
  • Figure 5C is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of partitions of a display area according to an exemplary embodiment of the present disclosure.
  • Figure 7A is a schematic structural diagram of the E0 region, E1 region and E2 region in Figure 6 provided by an embodiment of the present disclosure
  • Figure 7B is a schematic structural diagram of the E0 region in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 7C is a schematic structural diagram of the E1 region in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 7D is a schematic structural diagram of the E2 region in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 8A is a schematic diagram of the wiring of the first anode connection line of a display panel
  • Figure 8B is a schematic connection diagram of the first anode connection line of a display panel
  • Figure 8C is a schematic diagram 1 of the partial wiring of the first anode connection line of a display panel
  • Figure 8D is a schematic diagram 2 of the partial wiring of the first anode connection line of a display panel
  • Figure 8E is another structural schematic diagram of the E0 region in Figure 6;
  • Figure 9 is a schematic diagram after forming semiconductor patterns in the E0 region, E1 region and E2 region;
  • Figure 10 is a schematic diagram of the first conductive layer pattern in the E0 region, E1 region and E2 region;
  • Figure 11 is a schematic diagram after the E0 region, E1 region and E2 region form the first conductive layer pattern
  • Figure 12 is a schematic diagram of the first conductive layer pattern in the E0 region and the E1 region;
  • Figure 13 is a schematic diagram after the first conductive layer pattern is formed in the E0 region and the E1 region;
  • Figure 14 is a schematic diagram of the first conductive layer pattern in the E2 region
  • Figure 15 is a schematic diagram after the first conductive layer pattern is formed in the E2 region
  • Figure 16 is a schematic diagram after the third insulating layer pattern is formed in the E0 region and the E1 region;
  • Figure 17 is a schematic diagram after the third insulating layer pattern is formed in the E2 region
  • Figure 18 is a schematic diagram of the third conductive layer pattern in the E0 region and the E1 region;
  • Figure 19 is a schematic diagram after the third conductive layer pattern is formed in the E0 region and the E1 region;
  • Figure 20 is a schematic diagram of the third conductive layer pattern in the E2 region
  • Figure 21 is a schematic diagram after the third conductive layer pattern is formed in the E2 region
  • Figure 22 is a schematic diagram after the fourth insulating layer pattern is formed in the E0 region and the E1 region;
  • Figure 23 is a schematic diagram after the fourth insulating layer pattern is formed in the E2 region
  • Figure 24A is a schematic diagram 1 of the fourth conductive layer pattern in the E0 region
  • Figure 24B is a schematic diagram 1 after the fourth conductive layer pattern is formed in the E0 region;
  • Figure 25A is a schematic diagram 2 of the fourth conductive layer pattern in the E0 region
  • Figure 25B is a schematic diagram 2 after the fourth conductive layer pattern is formed in the E0 region
  • Figure 26 is a schematic diagram of the fourth conductive layer pattern in the E1 region
  • Figure 27 is a schematic diagram after the fourth conductive layer pattern is formed in the E1 region
  • Figure 28 is a schematic diagram of the fourth conductive layer pattern in the E2 region
  • Figure 29 is a schematic diagram after the fourth conductive layer pattern is formed in the E2 region
  • Figure 30 is a schematic diagram after the first flat layer pattern is formed in the E0 region
  • Figure 31 is a schematic diagram after the first flat layer pattern is formed in the E1 region
  • Figure 32 is a schematic diagram after the first flat layer pattern is formed in the E2 region
  • Figure 33 is a schematic diagram of the fifth conductive layer pattern in the E0 region
  • Figure 34 is a schematic diagram after the fifth conductive layer pattern is formed in the E0 region
  • Figure 35 is a schematic diagram of the fifth conductive layer pattern in the E1 region
  • Figure 36 is a schematic diagram after the fifth conductive layer pattern is formed in the E1 region
  • Figure 37 is a schematic diagram of the fifth conductive layer pattern in the E2 region
  • Figure 38 is a schematic diagram after the fifth conductive layer pattern is formed in the E2 region
  • Figure 39 is a schematic diagram after the second flat layer pattern is formed in the E0 region
  • Figure 40 is a schematic diagram after the second flat layer pattern is formed in the E1 region
  • Figure 41 is a schematic diagram after the second flat layer pattern is formed in the E2 region
  • Figure 42 is a schematic diagram of the anode conductive layer pattern
  • Figure 43 is a schematic diagram after the anode conductive layer pattern is formed in the E0 region
  • Figure 44 is a schematic diagram after the anode conductive layer pattern is formed in the E1 region
  • Figure 45 is a schematic diagram after the anode conductive layer pattern is formed in the E2 region
  • Figure 46 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include: a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array.
  • the timing controller is connected to the data driver, scan driver and light-emitting driver respectively.
  • the data driver is respectively connected to a plurality of data signal lines (for example, D1 to Dn)
  • the scan driver is respectively connected to a plurality of scan signal lines (for example, S1 to Sm)
  • the light emitting driver is respectively connected to a plurality of light emitting signal lines (for example, E1 to Eo) connection.
  • n, m and o can be natural numbers.
  • the pixel array may include multiple sub-pixels Pxij, and i and j may be natural numbers. At least one sub-pixel Pxij may include: a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include at least a pixel circuit, and the pixel circuit may be connected to the scanning signal line, the light emitting signal line, and the data signal line respectively.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data driver may sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal .
  • the light-emitting driver may generate light-emitting control signals to be supplied to the light-emitting signal lines E1, E2, E3, ...
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the light-emitting control signal in a manner that sequentially transmits an emission stop signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal.
  • FIG. 2 is a schematic structural diagram of a display panel.
  • the display panel may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area, including a plurality of sub-pixels Pxij that constitute a pixel array.
  • the plurality of sub-pixels Pxij may be configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display panel may use a flexible substrate, and thus the display panel may be deformable, such as curling, bending, folding, or rolling.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area 100, and the fan-out area introduces signal lines of the integrated circuits and bonding pads in the bonding area to the wider display area in a fanout wiring manner.
  • the fan-out area at least includes data fan-out (Fanout) lines.
  • the plurality of data fan-out lines are configured to connect the data signal lines of the display area 100 in a fan-out wiring manner and extend to the bending area.
  • the bending area is connected to the fan-out area, may include a composite insulating layer provided with grooves, and is configured to bend the driver chip area and the bonding pin area to the back of the display area 100 .
  • the driver chip area can be provided with an integrated circuit (IC, Integrated Circuit), and the integrated circuit can be configured to be connected to multiple data fan-out lines.
  • the bonding pin area can include a bonding pad, and the bonding pad can be configured to be bonded to an external flexible circuit board (FPC, Flexible Printed Circuit).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate drive circuit connected to the scanning signal line, reset signal line and light-emitting signal line to which the pixel circuit in the display area 100 is connected.
  • the power line area is connected to the circuit area and may include at least a frame power lead.
  • the frame power lead extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulation layer. The cutting grooves are configured such that after all film layers of the display panel are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along Extending in a direction parallel to the edge of the display area, a ring-shaped structure surrounding the display area 100 is formed.
  • the edge of the display area is the edge of the display area 100 close to the binding area 200 or the frame area 300 .
  • Figure 3 is a schematic plan view of a display area in a display panel.
  • the display panel may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and third and fourth sub-pixels P3 and P4 emitting light of a third color.
  • Each sub-pixel may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel circuit. The pixel circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel circuit may be configured to operate between the scanning signal line and the light-emitting signal line. Under the control of the line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the light-emitting devices of the sub-pixels may be rectangular, rhombus, pentagon or hexagon, and the light-emitting devices of the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the light-emitting devices of the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the light-emitting devices of the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • the display panel in a direction perpendicular to the display panel, may include: a substrate, a driving circuit layer, a light-emitting structure layer, and a packaging structure layer sequentially disposed on the substrate.
  • the display panel may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer of each sub-pixel may include a pixel circuit composed of a plurality of transistors and capacitors.
  • the light-emitting structure layer of each sub-pixel may at least include an anode, a pixel definition layer, an organic light-emitting layer and a cathode.
  • the anode is connected to the pixel circuit
  • the organic light-emitting layer is connected to the anode
  • the cathode is connected to the organic light-emitting layer
  • the organic light-emitting layer is driven by the anode and cathode. Light of the corresponding color is emitted from below.
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of organic materials. It is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the organic light-emitting layer may include an emitting layer (EL) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together through a common layer. Layers, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • FIG. 4A is an equivalent circuit diagram of a pixel circuit.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel circuit of this exemplary embodiment is explained by taking the 7T1C structure as an example. However, this embodiment is not limited to this.
  • the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7 ) and one capacitor C.
  • the pixel circuit is respectively connected to eight signal lines (for example, including: data signal line DL, scanning signal line GL, reset signal line RL, light-emitting signal line EL, first initial signal line INIL1, second initial signal line INIL2, high-voltage power supply line VDD and low-voltage power line VSS) connection.
  • the seven transistors of the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in pixel circuits can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the seven transistors of the pixel circuit may include P-type transistors and N-type transistors.
  • the seven transistors of the pixel circuit may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display panel, that is, LTPS+Oxide (LTPO for short) Display panels can take advantage of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPS+Oxide LTPO for short
  • the high-voltage power supply line VDD may be configured to provide a constant first voltage signal to the pixel circuit
  • the low-voltage power supply line VSS may be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the first voltage signal.
  • the scanning signal line GL may be configured to provide a scanning signal to the pixel circuit
  • the data signal line DL may be configured to provide a data signal to the pixel circuit
  • the light emitting signal line EL may be configured to provide a light emitting control signal to the pixel circuit.
  • the reset signal line RL may be electrically connected to the scan signal line GL of the n-1-th row of pixel circuits to be input with the scan signal.
  • n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced and the narrow frame design of the display panel can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIL1 may be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIL2 may be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal provided by the high-voltage power line VDD and the second voltage signal provided by the low-voltage power line VSS, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the gate electrode of the first transistor T1 is electrically connected to the reset signal line RL
  • the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIL1
  • the first transistor T1 The second electrode is electrically connected to the gate electrode of the third transistor T3.
  • the gate electrode of the second transistor T2 is electrically connected to the scanning signal line GL.
  • the first electrode of the second transistor T2 is electrically connected to the gate electrode of the third transistor T3.
  • the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. Electrical connection.
  • the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the high-voltage power supply line VDD and the low-voltage power supply line VSS according to the potential difference between its gate electrode and the first electrode.
  • the gate electrode of the fourth transistor T4 is electrically connected to the scanning signal line GL, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3 .
  • the fourth transistor can become the write transistor.
  • the gate electrode of the fifth transistor T5 is electrically connected to the light-emitting signal line EL
  • the first electrode of the fifth transistor T5 is electrically connected to the high-voltage power supply line VDD
  • the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the fifth transistor may become the first light emitting transistor.
  • the gate electrode of the sixth transistor T6 is electrically connected to the light-emitting signal line EL
  • the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device L. connect.
  • the sixth transistor T6 may be called a second light emitting transistor.
  • the gate electrode of the seventh transistor T7 is electrically connected to the reset signal line RL, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIL2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device L.
  • the first plate of the capacitor C is electrically connected to the gate of the third transistor T3, and the second plate of the capacitor C is electrically connected to the high-voltage power line VDD.
  • the first node N1 is the connection point of the capacitor C, the first transistor T1, the third transistor T3 and the second transistor T2, and the second node N2 is the fifth transistor T5, the fourth transistor T4 and the third transistor T3.
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting device L.
  • the light-emitting device L may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode). ), quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the low-voltage power line VSS.
  • the signal of the low-voltage power line VSS is a continuously provided low-level signal
  • the signal of the high-voltage power line VDD is a continuously provided high-level signal.
  • FIG. 4B is a working timing diagram of a pixel circuit. As shown in FIGS. 4A and 4B, taking the first transistor T1 to the seventh transistor T7 included in the pixel circuit as an example, the pixel
  • the working process of the circuit can include the following stages.
  • the first phase A1 is called the reset phase.
  • the low-level signal provided by the reset signal line RL turns on the first transistor T1
  • the first initial signal provided by the first initial signal line INIL1 is provided to the first node N1, which initializes the first node N1 and clears the capacitor C.
  • Zhongyuan has data voltage.
  • the scanning signal line GL provides a high-level signal
  • the light-emitting signal line EL provides a high-level signal to turn off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. At this stage, the light-emitting device L does not emit light.
  • the second stage A2 is called the data writing stage or threshold compensation stage.
  • the scanning signal line GL provides a low-level signal
  • the reset signal line RL and the light-emitting signal line EL both provide high-level signals
  • the data signal line DL outputs the data signal DATA.
  • the third transistor T3 is turned on.
  • the scanning signal line GL provides a low level signal to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line DL is provided to
  • the first node N1 charges the difference between the data voltage Vdata output by the data signal line DL and the threshold voltage of the third transistor T3 into the capacitor C.
  • the voltage of the first plate of the capacitor C (ie, the first node N1) is Vdata-
  • the seventh transistor T7 is turned on, causing the second initial signal provided by the second initial signal line INIL2 to be provided to the anode of the light-emitting device L, initializing (resetting) the anode of the light-emitting device L, clearing its internal pre-stored voltage, and completing the initialization. Make sure that the light-emitting device L does not emit light.
  • the reset signal line RL provides a high level signal to turn off the first transistor T1.
  • the light-emitting signal line EL provides a high-level signal to turn off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the luminous stage.
  • the light-emitting signal line EL provides a low-level signal, and the scanning signal line GL and the reset signal line RL both provide high-level signals.
  • the light-emitting signal line EL provides a low-level signal to turn on the fifth transistor T5 and the sixth transistor T6.
  • the first voltage signal output by the high-voltage power line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor.
  • T6 provides a driving voltage to the anode of the light-emitting device L to drive the light-emitting device L to emit light.
  • the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [Vdd-Vdata] 2 .
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line DL
  • Vdd is the first voltage signal output by the high-voltage power supply line VDD.
  • the current flowing through the light-emitting device L has nothing to do with the threshold voltage of the third transistor T3.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the third transistor T3.
  • the bonding area usually includes a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area. Since the width of the bonding area is smaller than the width of the display area, the signal lines of the integrated circuits and bonding pads in the bonding area need to be introduced into the wider display area through the fan-out area in the fanout routing method.
  • the sector area takes up a larger space, resulting in a narrower design of the lower border. It is quite difficult, as the lower border has been maintained at around 2.0 millimeters (mm).
  • Full-screen mobile phones use the Full Display with Camera (FDC) structure, which means that the area where the camera is located will also be displayed.
  • FDC structure can make the front viewable area almost entirely the screen, allowing users to get better display effects.
  • Exemplary embodiments of the present disclosure provide a display panel that adopts a structure in which data connection lines are located in a display area (Fanout in AA, referred to as FIAA).
  • FIAA display area
  • One end of a plurality of data connection lines is correspondingly connected to a plurality of data signal lines in the display area.
  • the other ends of the plurality of data connection lines extend to the binding area and are correspondingly connected to the integrated circuits in the binding area. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, effectively reducing the width of the bottom border.
  • Exemplary embodiments of the present disclosure provide a display panel, including: a display area, the display area includes: a light-transmitting display area and a regular display area located on at least one side of the light-transmitting display area, the regular display area includes a first area, The second area and the third area. At least one circuit unit in the first area is connected to the light-emitting device in the light-transmitting display area. At least one circuit unit in the third area includes a data connection line. A high-voltage circuit unit located in the first area The power line is the first high-voltage power line, the high-voltage power line located in the second area is the second high-voltage power line, and the high-voltage power line located in the third area is the third high-voltage power line;
  • the second high-voltage power supply line includes: a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected to each other.
  • the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base, so The first high-voltage power supply line and the second sub-high-voltage power supply line are arranged on the same layer, and the third high-voltage power supply line and the first sub-high-voltage power supply line are arranged on the same layer.
  • the display area includes: a substrate and a driving circuit layer and a light-emitting structure layer sequentially stacked on the substrate.
  • the driving circuit layer includes a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines and a plurality of data connection lines.
  • the light-emitting structure layer includes a plurality of light-emitting devices, the circuit unit includes a pixel circuit, the data signal line is configured to provide a data signal to the pixel circuit, the high-voltage power line is configured to provide a high power supply voltage signal to the pixel circuit, and the data connection The wire is connected to the data signal wire.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal chips; the flexible substrate may be, but is not limited to, polyterephthalate. Ethylene glycol ester, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile One or more types of fiber.
  • the light-emitting structure layer may include a plurality of light-emitting devices, and at least one light-emitting device includes an anode, an organic light-emitting layer, and a cathode.
  • the shape of the light-emitting device may be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons and other polygons, which are not limited in this disclosure.
  • the display panel provided by the embodiment of the present disclosure includes: a display area.
  • the display area includes: a light-transmitting display area and a regular display area located on at least one side of the light-transmitting display area.
  • the regular display area includes a first area, a second area, and a third area.
  • at least one circuit unit in the first area is connected to the light-emitting device in the light-transmitting display area
  • at least one circuit unit in the third area includes a data connection line
  • the high-voltage power line located in the first area is the first high-voltage power line, and is located in the third area.
  • the high-voltage power line in the second area is the second high-voltage power line
  • the high-voltage power line in the third area is the third high-voltage power line
  • the second high-voltage power line includes: a first sub-high-voltage power supply line and a second sub-high-voltage power supply line that are connected to each other. line, the second high-voltage power line is located on the side of the first high-voltage power line away from the base, the first high-voltage power line and the second high-voltage power line are arranged on the same layer, and the third high-voltage power line is on the same layer as the first high-voltage power line. Layer settings.
  • the embodiment of the present disclosure sets different high-voltage power lines in different areas of the conventional display area, thereby ensuring the display effect while also achieving compatibility between the FIAA structure and the FDC structure.
  • the data connection line includes: a first connection line connected to each other and a second connection line extending in the second direction, and the first connection line is located on a side of the third high-voltage power line close to the substrate. , the second connection line and the first high-voltage power supply line are arranged on the same layer;
  • the orthographic projection of the first connection line on the substrate and the orthographic projection of the data signal line on the substrate at least partially overlap, and the orthographic projection of the second connection line on the substrate and the third high-voltage power supply line on the substrate orthographic projections at least partially overlap.
  • the first connection line includes: a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, and the first data connection portion is connected to the second data connection portion respectively.
  • the data connection part is connected to the second connection line, and the first direction and the second direction intersect;
  • the orthographic projection of the first data connection portion on the substrate at least partially overlaps the orthographic projection of the data signal line on the substrate.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • FIG. 5A is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure
  • FIG. 5B is a cross-sectional view along the A-A direction of FIG. 5A
  • the display panel may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and a The packaging structure layer 104 is on the side of the light-emitting structure layer 103 away from the substrate.
  • the display panel may at least include a display area 100 , a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on other sides of the display area 100 .
  • the driving circuit layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel circuit configured to provide a signal to a connected
  • the light-emitting device outputs a corresponding current.
  • the light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array. At least one sub-pixel may include a light-emitting device.
  • the light-emitting device is connected to the pixel circuit of the corresponding circuit unit.
  • the light-emitting device is configured to respond to the output of the connected pixel circuit.
  • the current emits light with corresponding brightness.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304.
  • the anode 301 is connected to the drain electrode of the transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the substrate may be a rigid substrate, or may be a flexible substrate.
  • the rigid substrate can be made of materials such as glass or quartz
  • the flexible substrate can be made of materials such as polyimide (PI)
  • the flexible substrate can be a single-layer structure, or can be composed of an inorganic material layer and a flexible material layer.
  • the laminate structure is not limited in this disclosure.
  • the driving circuit layer of the display area 100 may also include a plurality of data signal lines 60 and a plurality of data connection lines 70 .
  • At least one data signal line 60 is connected to a plurality of data connection lines in a unit column.
  • the data signal lines 60 are connected to the pixel circuits, and the data signal lines 60 are configured to provide data signals to the connected pixel circuits.
  • At least one data connection line 70 is connected correspondingly to the data signal lines 60 , and the data connection lines 70 are configured to enable the data signal lines 60 to pass the data.
  • the connection wire 70 is connected correspondingly to the lead wire 210 in the binding area 200 .
  • the sub-pixels mentioned in this disclosure refer to regions divided according to light-emitting devices, and the circuit units mentioned in this disclosure refer to regions divided according to pixel circuits.
  • the orthographic projection position of the sub-pixel on the substrate may correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the sub-pixel on the substrate corresponds to the orthographic projection position of the circuit unit on the substrate. The positions may not correspond.
  • a plurality of circuit units sequentially arranged along the first direction X may be called a unit row
  • a plurality of circuit units sequentially arranged along the second direction Y may be called a unit column.
  • a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X and the second direction Y intersect.
  • the second direction Y may be an extending direction of the data signal line (vertical direction)
  • the first direction X may be perpendicular to the second direction Y (horizontal direction).
  • the circuit units located in the first area, the second area and the third area may include: a driving circuit unit and a dummy circuit unit, and the pixel circuit in the driving circuit unit may be configured to drive the light emitting device to emit light,
  • the pixel circuit in the virtual circuit unit is configured to drive the light-emitting device to emit light, which is configured to ensure display uniformity of the display panel.
  • the virtual circuit units may be provided between the driving circuit units.
  • the binding area 200 may at least include a lead area 201, a bending area, and a driver chip area that are sequentially arranged in a direction away from the display area.
  • the lead area 201 is connected to the display area 100, and the bending area is connected to the lead. Area 201, the driver chip area is connected to the bending area.
  • the lead area 201 may be provided with a plurality of lead lines 210, and the plurality of lead lines 210 may extend along the second direction Y. The first ends of the plurality of lead lines 210 are connected to the integrated circuits in the composite circuit area, and the first ends of the plurality of lead lines 210 are connected to the integrated circuits of the composite circuit area.
  • the two ends extend across the bending area to the lead area 201 and are connected correspondingly to the data connection line 70, so that the integrated circuit applies data signals to the data signal line through the lead lines and the data connection line. Since the data connection line is arranged in the display area, the length of the second direction Y in the lead area can be effectively reduced, the width of the lower frame is greatly reduced, the screen-to-body ratio is increased, and it is conducive to realizing a full-screen display.
  • the shape of the plurality of data signal lines provided in the display area 100 may be a line shape extending along the second direction Y, and the shape of the plurality of data connection lines 70 provided in the display area 100 may be a polygonal line.
  • the data connection line 70 may include a first connection line partially extending along the first direction X and a second connection line extending along the second direction Y.
  • First ends of the plurality of first connection lines are correspondingly connected to the plurality of data signal lines 60 through connection holes, and the second ends of the plurality of first connection lines extend along the first direction X or the opposite direction of the first direction
  • the first end is connected, and the second ends of the plurality of second connection lines (the second ends of the data connection lines 70 ) extend in the direction of the binding area 200 and cross the display area boundary B, and are connected to the multiple leads of the lead area 201 Line 210 corresponds to the connection.
  • the display area boundary B may be the junction of the display area 100 and the binding area 200 .
  • the data connection line 70 and the lead-out line 210 may be directly connected or may be connected through a via hole, which is not limited in this disclosure.
  • a plurality of second connection lines may be disposed in parallel with the data signal line 60 .
  • the spacing between adjacent second connecting lines in the first direction X may be substantially the same, and the spacing between adjacent first connecting lines in the second direction Y may be substantially the same. This disclosure does not Make limitations.
  • the display area 100 may have a center line O, and the plurality of data signal lines 60 , the plurality of data connection lines 70 in the display area 100 and the plurality of lead lines 210 in the lead area 201 may be relative to the center line O.
  • O is arranged symmetrically, and the center line O may be a straight line that bisects the plurality of unit columns of the display area 100 and extends along the second direction Y.
  • FIG. 5C is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in FIG. 5A , illustrating the structure of 7 data signal lines, 7 data connection lines and 7 lead lines.
  • the plurality of data signal lines of the display area 100 may include first to seventh data signal lines 60 - 1 to 60 - 7 .
  • the plurality of data connection lines of the display area 100 The first to seventh data connection lines 70-1 to 70-7 may be included, and the plurality of lead lines of the lead area 201 may include the first to seventh lead lines 210-1 to 210-7.
  • the first to seventh data signal lines 60-1 to 60-7, the first to seventh data connection lines 70-1 to 70-7, and the first lead-out line 210-1 to the seventh lead-out line 210-7 can be arranged sequentially along the first direction
  • the distances between the plurality of connection holes corresponding to the data connection lines 70 and the data signal lines 60 and the edge B of the display area may be different.
  • the distance between the connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the edge B of the display area may be shorter than the distance between the second data connection line 70-2 and the second data signal line 60-2.
  • the distance between the connection hole and the edge B of the display area may be greater than the distance between the connection hole connecting the third data connection line 70-3 and the third data signal line 60-2.
  • the distance between the connection hole of 3 and the edge B of the display area may be different.
  • the distance between the connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the edge B of the display area may be shorter than the distance between the second data connection line 70-2 and the second data signal line 60-2.
  • the distance between the connection hole and the edge B of the display area may be greater than the distance between the connection hole connecting the third data connection line 70-3 and the third data signal line 60-2.
  • FIG. 6 is a schematic diagram of partitions of a display area according to an exemplary embodiment of the present disclosure.
  • the display area includes: a light-transmitting display area 10 and a regular display area.
  • the regular display area includes a first area 100A, a second area 100B, and a third area 100C.
  • At least one circuit unit of the first area 100A is connected to a light-emitting device in the light-transmitting display area.
  • the second area 100C is all areas of the regular display area except the first area and the third area.
  • At least one circuit unit of the third area 100C includes a data connection line.
  • the third area 100C may include a plurality of circuit units, in which the orthographic projection of the pixel circuit on the display panel plane overlaps with the orthographic projection of the data connection line 70 on the display panel plane.
  • the filling area in FIG. 6 refers to the third area 100C where the data connection lines are located.
  • the portion of the data connection lines 70 located in the third area 100C is in a different film layer than the data signal line 60 . And is located on the side of the data signal line close to the substrate, and the other part of the data connection line 70 is on the same film layer as the data signal line.
  • the portions of the data connection line 70 and the data signal line located on different film layers are connected to the data signal line 60 .
  • the portion of the data connection line 70 and the data signal line located on the same layer extend to the binding area 201 along the second direction Y.
  • the data connection line 70 may include a first connection line 71 extending partially along the first direction X and a second connection line 71 extending along the second direction Y.
  • the connecting line 72 , the first connecting line 71 and the second connecting line 72 form a zigzag-shaped data connecting line 70 .
  • the first end of the first connection line 71 is connected to the data signal line 60 through the first connection hole.
  • the first end of the connecting wire 72 is directly connected, and the second end of the second connecting wire 72 extends along the second direction Y toward the lead area 201 and then is connected to the lead wire 210 .
  • first connection line 71 and the data signal line 60 may be disposed in different conductive layers, and the second connection line 72 and the data signal line 60 may be disposed in the same conductive layer.
  • the first connection line includes: a first data connection part extending along the second direction and a second data connection part extending along the first direction, the first data connection part being connected to the second data connection part and the second data connection part respectively.
  • the second connection line is connected, and the first direction and the second direction cross.
  • each area shown in FIG. 6 is only an exemplary illustration.
  • the first area 100A and the second area 100B have no data connection lines, and the third area 100C has data connection lines.
  • the circuit unit of the first area 100A is connected to the light-emitting device of the light-transmitting display area, and the circuit unit of the second area 100B is not connected to the light-emitting device of the light-transmitting display area.
  • the light-emitting devices of the light display area are used as the basis for division, so the shapes of the three areas can be regular polygons or irregular polygons.
  • the display area can be divided into one or more first areas 100A and one or more second areas. 100B and one or more third areas 100C, this disclosure is not limited here.
  • the shape of the light-transmitting display area may be any one or more of the following: rectangular, polygonal, circular, and elliptical.
  • Figures 5A and 6 take a circle as an example for explanation.
  • the diameter of the circle may be about 3 mm to 5 mm.
  • the side length of the rectangle may be about 3 mm to 5 mm.
  • the shape of the first area in a plane parallel to the display panel, may be any one or more of the following: rectangular, polygonal, circular, and elliptical.
  • the area of the light-transmitting display area may be greater than the area of the first area, or the area of the light-transmitting display area may be equal to the area of the first area, or the area of the light-transmitting display area may be smaller than the area of the first area
  • FIG. 5A and FIG. 6 illustrate by taking the area of the light-transmitting display area being smaller than the area of the second display area as an example.
  • the resolutions of the light-transmitting display area and the first area may be the same, or may be different.
  • resolution Pixels Per Inch, referred to as PPI
  • PPI Pixel Per Inch
  • the resolution of the first area may be greater than the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is greater than the number of light-emitting devices included in the light-transmitting display area.
  • the resolution of the first area may be smaller than the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is smaller than the number of light-emitting devices included in the light-transmitting display area, or,
  • the resolution of an area may be equal to the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is equal to the number of light-emitting devices included in the light-transmitting display area.
  • the shape of the display area may be a rounded polygon, or may be a circle.
  • the display area may also include: a straight line display boundary.
  • Figure 5A and Figure 6 illustrate using the display area as a rounded rectangle as an example.
  • Figure 7A is a schematic structural diagram of the E0 area, E1 area and E2 area in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 7B is a schematic structural diagram of the E0 area in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 7C is a schematic structural diagram of the E0 area in Figure 6 provided by an embodiment of the present disclosure.
  • the example provides a schematic structural diagram of the E1 region in FIG. 6
  • FIG. 7D is a schematic structural diagram of the E2 region in FIG. 6 provided by an embodiment of the present disclosure.
  • the E0 area is located in the first area
  • the E1 area is located in the second area
  • the E3 area is located in the third area.
  • the high-voltage power line located in the first area is the first high-voltage power line
  • the high-voltage power line located in the second area is the second high-voltage power line
  • the high-voltage power line located in the third area is the third high-voltage power line.
  • the second high-voltage power supply line may include: a first sub-high-voltage power supply line VLB1 and a second sub-high-voltage power supply line VLB2 connected to each other.
  • the second sub-high-voltage power supply line VLB2 Located on the side of the first sub-high-voltage power line VLB1 away from the substrate, the first high-voltage power line VLA and the second sub-high-voltage power line VLB2 are arranged on the same layer, and the third high-voltage power line VLC and the first sub-high-voltage power line VLB1 are arranged on the same layer.
  • a first region is shown in FIGS. 7A and 7D .
  • the data signal lines in the second region and the third region may be the same data signal line, and the data signal line DL and the first high-voltage power supply line are arranged on the same layer.
  • the length of the second sub-high-voltage power supply line VLB2 along the first direction X may be smaller than the length of the first sub-high-voltage power supply line VLB1 along the first direction
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-high voltage power supply line VLB1 on the substrate.
  • the length of the first high-voltage power supply line VLA along the first direction X, the length of the first sub-high-voltage power supply line VLB1 along the first direction X, and the third high-voltage power supply line The lengths of VLC along the first direction
  • the shape of the first high-voltage power line VLA and the third high-voltage power line VLC is roughly the same as the shape of the first sub-high-voltage power line VLB1, which can eliminate afterimages caused by metal wires that appear when the display panel is turned off, and ensure the display effect of the display panel.
  • the data connection line may include: a first connection line 71 connected to each other and a second connection line 72 extending along the second direction.
  • the first connection line 71 is located at the first connection line 72 .
  • the three high-voltage power lines VLC are close to the side of the substrate, and the second connection line 72 is arranged on the same layer as the first high-voltage power line VLA.
  • low load and high refresh rate can be achieved by arranging the second connection line 72 and the first high-voltage power line VLA on the same layer.
  • the length of the second sub-high voltage power supply line VLB2 along the first direction X may be approximately equal to the length of the second connection line 72 along the first direction X, and the second The shape of the sub-high-voltage power supply line VLB2 is substantially the same as that of the second connection line 72 .
  • the orthographic projection of the first connection line 71 on the substrate at least partially overlaps the orthographic projection of the data signal line DL on the substrate, and the second connection line 72 is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the third high-voltage power line VLC on the substrate.
  • the area of the overlapping area of the orthographic projection of the second sub-high-voltage power supply line VLB2 on the substrate and the orthographic projection of the first sub-high-voltage power supply line VLB1 on the substrate is larger than that of the second connection line.
  • FIG. 8A is a schematic diagram of the wiring of the first anode connection line of a display panel
  • FIG. 8B is a schematic diagram of the connection of the first anode connection line and the second anode connection line of a display panel
  • FIG. 8C is Figure 8D is a partial wiring diagram of the first anode connection line of a display panel.
  • Figure 8D is a partial wiring diagram of the first anode connection line of a display panel.
  • Figure 8E is another structural diagram of the E0 area in Figure 6.
  • the light-emitting device may include: an anode, an organic light-emitting layer, and a cathode.
  • the display panel may further include: a plurality of first anode connection lines AL1 extending along the first direction.
  • the first anode connection lines AL1 and The third high-voltage power line VLC is provided on the same layer and is configured to connect at least one circuit unit in the first area 100A and the anode of the light-emitting device located in the light-transmitting display area 10 .
  • the circuit unit of the first area 100A may include: multiple circuit units, and the circuit unit connected to the light-emitting device of the light-transmitting display area may be located between the circuit units connected to the light-emitting device of the conventional display area. .
  • the light-transmitting display area 10 includes: a central area 10A and an edge area 10B surrounding the central area 10A.
  • the display panel may further include: a second anode connection line AL2.
  • the second anode connection line AL2 may be located on a side of the first high-voltage power line away from the substrate; the first anode connection line AL1 is configured to connect at least one circuit unit in the first area and an anode of the light-emitting device located in the edge area, and the second anode The connection line AL2 is configured to connect at least one circuit unit in the first area and the anode of the light emitting device located in the central area.
  • the first anode connection line may include a metal signal line.
  • the first anode connection line and the third high-voltage power line are arranged on the same layer, which can simplify the manufacturing process of the display panel, help save costs, and improve yield and production capacity.
  • the second anode connection line includes: a transparent conductive signal line
  • the second anode connection line includes: a transparent conductive signal line, which can ensure the light transmittance of the light-transmitting display area.
  • the aperture size of the light-transmitting display area is about 2.5 mm
  • the display panel all adopts the second anode connection line at least three transparent conductive layers and at least three transparent conductive layers need to be provided between the transparent conductive layers.
  • Flat layer or insulating layer At this time, the number of masks used in the display panel is relatively large.
  • the wiring pressure of the second anode connection line can be alleviated, and the number of masks used in the production of the display panel can be reduced. It is beneficial to save costs and improve yield and production capacity.
  • the light-emitting structure layer may include: a plurality of light-emitting units, at least one light-emitting unit includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, different light-emitting devices emit light of different colors, the first The light-emitting device and the second light-emitting device emit red or blue light, and the third light-emitting device emits green light.
  • the area of the first light-emitting device located in the light-emitting unit of the light-transmitting display area is smaller than the area of the first light-emitting device located in the light-emitting unit of the conventional display area.
  • the area of the second light-emitting device located in the light-emitting unit of the light-transmitting display area is smaller than the area of the second light-emitting device located in the light-emitting unit of the conventional display area.
  • the area of the third light-emitting device located in the light-emitting unit of the light-transmitting display area is smaller than the area of the third light-emitting device located in the light-emitting unit of the conventional display area.
  • the length of the first anode connection line AL1 connected to the third light-emitting device of the same light-emitting unit along the first direction is less than that of the same light-emitting unit.
  • the length of the first anode connection line AL1 connected to the third light-emitting device of the same light-emitting unit along the first direction is shorter than the length of the first anode connection line AL1 connected to the first light-emitting device and the second light-emitting device of the same light-emitting unit along the first direction.
  • the length can reduce the load of the sub-pixel where the third light-emitting device is located, and can improve the display effect of the light-emitting device in the light-transmitting display area.
  • the length of the first anode connection line AL1 connected to any third light-emitting device located in the edge region along the first direction The length along the first direction X of the first anode connection line AL1 connected to the first light-emitting device and the first anode connection line AL1 connected to any second light-emitting device located in the edge area.
  • the edge area 10B occupies approximately 3% to 8% of the area of the light-transmitting display area 10 , or the edge area 10B includes a number of light-emitting units that is 5% to 10% of the number of light-emitting units in the light-transmitting display area. %.
  • the edge area 10B accounts for about 3% to 8% of the area of the light-transmitting display area 10, or the number of light-emitting units included in the edge area 10B is 5% to 10% of the number of light-emitting units in the light-transmitting display area to ensure that the light-transmitting display area is of light transmittance.
  • the display panel may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third layer sequentially disposed on the substrate. Insulating layer, third conductive layer, fourth insulating layer, fourth conductive layer, first flat layer, fifth conductive layer;
  • the semiconductor layer at least includes active layers of a plurality of transistors; the first conductive layer at least includes gate electrodes of the plurality of transistors and a first plate of the capacitor; the second conductive layer at least includes a second plate of the capacitor; and the third conductive layer at least It includes first and second poles of a plurality of transistors and first connection lines.
  • the fourth conductive layer at least includes a first anode connection line, a first sub-high voltage power supply line and a third high voltage power supply line.
  • the fifth conductive layer at least includes: data signal line, first high-voltage power line, second sub-high-voltage power line and second connection line.
  • the pixel circuit includes: a writing transistor connected to the data signal line; the second plate of the capacitor located in the third region includes: a capacitor main part and an auxiliary capacitor part connected to each other, the capacitor main part
  • the shape of the portion is substantially the same as the second plate of the capacitor located in the first region and the second region; the orthographic projection of the auxiliary capacitor portion on the substrate at least partially overlaps the orthographic projection of the active layer of the writing transistor on the substrate.
  • the third conductive layer further includes: a data connection block, an orthographic projection of the data connection block on the substrate at least partially overlaps an orthographic projection of the auxiliary capacitor part and the second connection line on the substrate, the data connection block Connected to the first connection line and the second connection line respectively.
  • the data connection block and the second data connection part are located on the same side of the first data connection part and are electrically connected to the first data connection part;
  • An orthographic projection of the first data connection portion on the substrate at least partially overlaps an orthographic projection of the second plate of the capacitor on the substrate.
  • the pixel circuit further includes: a first light-emitting transistor and a second light-emitting transistor, the first light-emitting transistor is connected to the high-voltage power line, the second light-emitting transistor is connected to the anode of the light-emitting device, and the fourth conductive layer further includes: a first connection electrode, a second connection electrode, a third connection electrode and a fourth connection electrode;
  • the orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the writing transistor of at least one circuit unit located in the first to third regions on the substrate, and overlaps with the orthographic projection of the first electrode located on the substrate in the first region
  • the first electrode of the writing transistor is electrically connected to at least one circuit unit in the third region
  • the orthographic projection of the second connection electrode on the substrate is with the second electrode in at least one circuit unit located in the first to third regions.
  • the orthographic projection of the second electrode of the light-emitting transistor on the substrate at least partially overlaps with the second electrode of the second light-emitting transistor located in at least one circuit unit in the first region to the third region, and the third connection electrode is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first pole of the first light-emitting transistor located in at least one circuit unit in the first region on the substrate, and overlaps with the orthographic projection on the substrate in at least one circuit unit located in the first region.
  • the first electrode of the first light-emitting transistor is connected, and the orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the data connection block on the substrate, and at least partially overlaps with the orthographic projection of the data connection block on the substrate. .
  • the fifth conductive layer further includes: a fifth connection electrode, an orthographic projection of the fifth connection electrode on the substrate at least partially overlaps an orthographic projection of the second connection electrode on the substrate, and is connected with the second connection electrode. Electrode connections.
  • the orthographic projection of the plurality of first anode connection lines on the substrate may at least partially overlap with the orthographic projection of the second plate of the capacitor and the anode of the connected light-emitting device on the substrate.
  • the orthographic projection of the data signal line on the substrate at least partially overlaps the orthographic projection of the first connection electrode on the substrate and is connected to the first connection electrode, and the orthographic projection of the first high-voltage power line on the substrate
  • the projection at least partially overlaps with the orthographic projection of the third connection electrode on the substrate, and is connected to the third connection electrode.
  • the orthographic projection of the second connection line on the substrate at least partially overlaps the orthographic projection of the fourth connection electrode on the substrate, and is connected to the fourth connection electrode.
  • the display panel may further include a transparent conductive layer located on a side of the second flat layer away from the substrate.
  • the transparent conductive layer includes a second anode connection line, and the second anode connection line and the fifth connection electrode are on the substrate.
  • the orthographic projections at least partially overlap and are connected to the fifth connection electrode.
  • the following is an exemplary description through the preparation process of the display panel.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged in the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display panel.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display panel may include the following steps.
  • forming a semiconductor layer pattern may include: sequentially depositing a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, and forming a semiconductor layer pattern, as shown in Figure 9, which is the E0 region, A schematic diagram after the semiconductor pattern is formed in the E1 region and the E2 region.
  • the semiconductor layer patterns located in the E0 region, the E1 region, and the E2 region each include: an active layer T11 of the first transistor to an active layer T71 of the seventh transistor.
  • the active layer T11 of the first transistor to the active layer T61 of the sixth transistor is an integral structure connected to each other.
  • the active layer T21 of the second transistor and the active layer T61 of the sixth transistor may be located in the active layer T31 of the third transistor in this subpixel
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in this sub-pixel
  • the active layer T21 of the second transistor and the active layer T21 of the fourth transistor can be located on the same side of the sub-pixel.
  • the active layer T41 may be located on different sides of the active layer T31 of the third transistor of this sub-pixel.
  • the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor may be located in the third transistor of this sub-pixel.
  • the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on the other side of the active layer T31 of the third transistor in this sub-pixel.
  • the active layer T11 of the first transistor may be in an "n" shape
  • the active layer T21 of the second transistor may be in an "L” shape
  • the third transistor may be in an "L” shape.
  • the active layer T31 of The shape can be in the shape of an "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T11_2 of the active layer T11 of the first transistor may be the first region T21_1 of the active layer T21 of the second transistor
  • the first region T31_1 of the active layer T31 of the third transistor may be At the same time, the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor can be simultaneously used as the second region T31_2 of the active layer T31 of the third transistor.
  • the second region T61_2 of the active layer T61 of the sixth transistor may serve as the second region T61_2 of the active layer T61 of the seventh transistor.
  • Area T71_2 the first area T11_1 of the active layer T11 of the first transistor, the first area T41_1 of the active layer T41 of the fourth transistor, the first area T51_1 of the active layer T51_1 of the fifth transistor, and the active layer T51_1 of the seventh transistor.
  • the first area T71_1 of the source layer T71 can be set independently.
  • the first region T31_1 of the active layer T31 of the third transistor (also the second region T41_2 of the active layer T41 of the fourth transistor) and the active layer T51 of the fifth transistor
  • the shape of the second region T51_2) may be a strip structure extending along the second direction Y, and the length along the first direction X is greater than the first region T41_1 of the active layer T41 of the fourth transistor and the active layer of the fifth transistor.
  • the length of the first zone T51_1 of layer T51 may be a strip structure extending along the second direction Y, and the length along the first direction X is greater than the first region T41_1 of the active layer T41 of the fourth transistor and the active layer of the fifth transistor.
  • the semiconductor patterns of the E1 and E2 regions in FIG. 9 are substantially the same as the semiconductor patterns of the E0 region.
  • forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The first insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern located on the first insulating layer, as shown in Figures 10 and 11, wherein Figure 10 is the first conductive layer in the E0 region, E1 region and E2 region A schematic diagram of the layer pattern.
  • Figure 11 is a schematic diagram of the E0 region, the E1 region, and the E2 region after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer patterns in the E0 region, the E1 region, and the E2 region may each include: a scanning signal line GL, a reset signal line RL, a light emitting signal line EL, and a capacitor.
  • the shape of the first plate C1 of the capacitor may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the first plate C1 of the capacitor is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate.
  • the first plate C1 of the capacitor may simultaneously serve as the control electrode T32 of the third transistor.
  • the shape of the reset signal line RL may be a line shape extending along the first direction One side of the signal line EL.
  • the area where the reset signal line RL overlaps with the active layer of the first transistor serves as the control electrode T12 of the first transistor, and the area where the reset signal line RL overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor. Since the shape of the active layer T11 of the first transistor can be in an "n" shape, there are two areas where the reset signal line RL overlaps with the active layer of the first transistor. That is to say, the control electrode of the first transistor There are two T12, that is, the first transistor has a double-gate structure.
  • the shape of the scanning signal line GL may be a line shape extending along the first direction X, and the scanning signal line GL may be located between the first plate C1 of the capacitor and the reset between signal lines RL.
  • the area where the scanning signal line GL overlaps with the active layer of the second transistor serves as the control electrode T22 of the second transistor, and the area where the scanning signal line GL overlaps with the active layer of the fourth transistor serves as the control electrode T42 of the fourth transistor.
  • the shape of the light-emitting signal line EL may be a line shape extending along the first direction X, and the light-emitting signal line EL overlaps with the active layer of the fifth transistor.
  • the area serves as the control electrode T52 of the fifth transistor, and the area where the light-emitting signal line EL overlaps with the active layer of the sixth transistor serves as the control electrode T62 of the sixth transistor.
  • the scanning signal line GL, the reset signal line RL, and the light emitting signal line EL may be designed with equal widths, or may be designed with non-equal widths, may be straight lines, or may be Being a folded line not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in this disclosure.
  • the first conductive layer can be used as a shield to perform a conductive treatment on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms a second conductive layer.
  • the semiconductor layer in the region not blocked by the first conductive layer is conductive, that is, the first region and the active layer of the first transistor to the seventh transistor.
  • Both regions are conductive, and the conductive first region of the active layer of the third transistor (also the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) can be At the same time, as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, and the second electrode T54 of the fifth transistor, the second region of the active layer of the conductive third transistor (also the second region of the second transistor)
  • the second region of the active layer and the first region T61_1) of the active layer of the sixth transistor also simultaneously serve as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor. .
  • the first conductive layer patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the first conductive layer patterns of the E0 region.
  • forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and A second conductive layer pattern is formed on the second insulating layer.
  • Figure 12 is a schematic diagram of the first conductive layer pattern in the E0 region and the E1 region.
  • Figure 13 is a schematic diagram of the E0 region and the E1 region after the first conductive layer pattern is formed.
  • Figure 14 is a schematic diagram of the first conductive layer pattern in the E2 region.
  • Figure 15 is a schematic diagram of the E2 region after the first conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • GATE2 second gate metal
  • the second conductive layer patterns in the E0 region, the E1 region, and the E2 region may each include: a first initial signal line INIL1, a second initial signal line INIL2, and a capacitor.
  • the second plate C2 may include: a first initial signal line INIL1, a second initial signal line INIL2, and a capacitor.
  • the shapes of the first initial signal line INIL1 and the second initial signal line INIL2 may be a line shape in which the main body part may extend along the first direction X.
  • the first initial signal line INIL1 in the M-th row circuit unit may be located between the reset signal line RL and the scan signal line GL of this circuit unit, and the second initial signal line INIL2 may be located away from the reset signal line RL of this circuit unit away from the scan signal.
  • the outline shape of the second electrode plate C2 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projection of the second electrode plate C2 on the substrate There is an overlapping area with the orthographic projection of the first plate C1 on the substrate.
  • the second plate C2 serves as another plate of the capacitor and is located between the scanning signal line GL and the light-emitting signal line EL of this circuit unit.
  • the first plate C1 and the second plate C2 constitute the capacitor of the pixel circuit.
  • the second plates C2 of adjacent circuit units are connected to each other.
  • the interconnection of the second plates C2 of adjacent circuit units allows the second plates of multiple circuit units in a unit row to form an integrated structure that is connected to each other.
  • the second plates of the integrated structure can be reused as power signal connection lines. Ensuring that multiple second electrode plates in a unit row have the same potential is beneficial to improving the uniformity of the display panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.
  • the second electrode plate C2 is provided with an opening V, and the opening V may be located in the middle of the second electrode plate C2.
  • the opening V may be rectangular, so that the second electrode plate C2 forms a ring structure.
  • the opening V exposes the second insulating layer covering the first electrode plate C1, and the orthographic projection of the first electrode plate C1 on the substrate includes the orthographic projection of the opening V on the substrate.
  • the opening V is configured to accommodate a subsequently formed seventh via hole.
  • the seventh via hole is located in the opening V and exposes the first plate C1, so that the subsequently formed second transistor T1 can The pole is connected to the first plate C1.
  • the second conductive layer pattern of the E1 region is substantially the same as the second conductive layer pattern of the E0 region.
  • the second electrode plate in the second conductive layer pattern in the E2 region is different from the second electrode plate in the second conductive layer pattern in the E0 region.
  • the second plate in the second conductive layer pattern in the E2 region may include: an integrally formed capacitor main part C_main and an auxiliary capacitor part C0.
  • the shape of the capacitor main part C_main is the same as the shape of the second plate C2 in the second conductive layer pattern of the E0 region and the E1 region.
  • the orthographic projection of the auxiliary capacitor part C0 on the substrate at least partially overlaps the orthographic projection of the active layer of the fourth transistor on the substrate.
  • the auxiliary capacitor part can function to level the data connection block, which can improve the display effect of the display panel.
  • the first initial signal line INIL1 and the second initial signal line INIL2 may be designed with equal widths, or may be designed with non-equal widths, may be straight lines, or may be The folded lines can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between signal lines, which is not limited in this disclosure.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, patterning the third insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the third insulating layer is provided with multiple via holes, as shown in Figures 16 and 17.
  • Figure 16 is a schematic diagram of the E0 region and the E1 region after the third insulating layer pattern is formed, and Figure 17 is E2.
  • a schematic diagram after the third insulating layer pattern is formed in the area.
  • the plurality of via holes in the third insulating layer of the E0 region, the E1 region, and the E2 region may each include: a first via hole V1, a second via hole V2. , the third via V3, the fourth via V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9 and the tenth via V10.
  • the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor T1 on the substrate.
  • the first insulating layer and the second insulating layer in the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor T1, and the first via V1 is configured to enable subsequent formation
  • the first electrode of the first transistor T1 is connected to the first region of the active layer of the first transistor T1 through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located in the second region of the active layer of the first transistor T1 (also the active layer of the second transistor T2 (the first area) within the range of the orthographic projection on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away, exposing the second insulating layer of the active layer of the first transistor T1 area (also the first area of the active layer of the second transistor T2), the second via V2 is configured to enable the subsequently formed second electrode of the first transistor T1 (also the first electrode of the second transistor T2)
  • the via hole is connected to the first region of the active layer of the first transistor T1 (also the first region of the active layer of the second transistor T2).
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fourth transistor T4 on the substrate.
  • the first insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the surface of the first region of the active layer of the fourth transistor T4, and the third via hole V3 is configured to enable subsequent formation
  • the first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor T4 through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth transistor T5 on the substrate.
  • the first insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing the surface of the first region of the active layer of the fifth transistor T5, and the fourth via V4 is configured to enable subsequent formation
  • the first electrode of the fifth transistor T5 is connected to the first region of the active layer of the fifth transistor T5 through the via hole.
  • the orthographic projection of the fifth via V5 on the substrate is located in the second region of the active layer of the sixth transistor T6 (also the active layer of the seventh transistor T7 (the second area) within the range of the orthographic projection on the substrate, the first insulating layer and the second insulating layer in the fifth via hole V5 are etched away, exposing the second insulating layer of the active layer of the sixth transistor T6 area (also the second area of the active layer of the seventh transistor T7), the fifth via V5 is configured to enable the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7)
  • the via hole is connected to the second area of the active layer of the sixth transistor T6 (also the second area of the active layer of the seventh transistor T7).
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the seventh transistor T7 on the substrate.
  • the first insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the surface of the first region of the active layer of the seventh transistor T7, and the sixth via hole V6 is configured to enable subsequent formation
  • the first electrode of the seventh transistor T7 is connected to the first region of the active layer of the seventh transistor T7 through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the opening on the substrate, and the second insulation in the seventh via hole V7
  • the layer is etched away, exposing the surface of the first plate of the first capacitor (also the control electrode of the third transistor), and the seventh via V7 is configured to enable the second electrode of the subsequently formed first transistor T1 (also the control electrode of the third transistor).
  • the first electrode of the second transistor T2 is connected to the first plate of the first capacitor (which is also the control electrode of the third transistor T3) through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the first initial signal line INIL1 on the substrate, and the eighth via hole V8 The surface of the first initial signal line INIL1 is exposed, and the eighth via hole V8 is configured so that the first pole of the subsequently formed first transistor T1 is connected to the first initial signal line INIL1 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the second initial signal line INIL2 on the substrate, and the ninth via hole V9 The surface of the second initial signal line INIL2 is exposed, and the ninth via hole V9 is configured so that the first electrode of the subsequently formed seventh transistor is connected to the second initial signal line INIL2 through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second plate of the capacitor on the substrate, and the tenth via hole V10 The surface of the second plate of the capacitor is exposed, and the tenth via hole V10 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the second plate of the capacitor through the via hole.
  • there may be a plurality of tenth via holes V10 and the plurality of tenth via holes V10 may be arranged sequentially along the second direction Y to improve connection reliability.
  • the via hole patterns of the third insulating layer in the E1 region and the E2 region are substantially the same as the via hole patterns of the third insulating layer in the E0 region.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the third insulating layer.
  • the third conductive layer is shown in Figures 18 to 21.
  • Figure 18 is a schematic diagram of the third conductive layer pattern in the E0 region and E1 region.
  • Figure 19 is a schematic diagram of the third conductive layer pattern in the E0 region and E1 region.
  • Figure 20 is a schematic diagram of the third conductive layer pattern in the E2 region
  • FIG. 21 is a schematic diagram of the E2 region after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the third conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include: the first pole T13 and the second pole T14 of the first transistor, the second The first pole T23 of the transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, the second pole T64 of the sixth transistor, the first pole T73 and the second pole T74 of the seventh transistor. in,
  • the second electrode T14 of the first transistor can simultaneously serve as the first electrode T23 of the second transistor, and the second electrode T64 of the sixth transistor can simultaneously serve as the seventh transistor.
  • the second pole T74 of the first transistor, the first pole T13 of the first transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, and the first pole T73 of the seventh transistor can be set independently.
  • the third conductive layer pattern in the E2 region may further include: a data connection block 73 and a first connection line 71 .
  • the orthographic projection of the data connection block 73 on the substrate at least partially overlaps the orthographic projection of the auxiliary capacitor part on the substrate.
  • the first connection line 71 is connected to the data connection block 73 and is an integrally formed structure.
  • the first connection line 71 may include: a first data connection part 71A and a second data connection part 71B.
  • the first data connection part 71A is connected to the data connection block 73 and the second data connection part 71B respectively, and the data connection block 73 and the second data connection part 71B are located on the same side of the first data connection part 71A.
  • the orthographic projection of the first data connection portion 71A on the substrate at least partially overlaps the orthographic projection of the second plate of the capacitor on the substrate.
  • the main body portion of the first data connection portion 71A may be in the shape of a line extending in the second direction Y
  • the main body portion of the second data connection portion 71B may be in the shape of a line extending along the first direction Y.
  • the shape of the first electrode T13 of the first transistor may be a line shape with the main body portion extending along the first direction X, and the first electrode T13 of the first transistor may be located at Between the scan signal line GL and the reset signal line RL.
  • An orthographic projection of the first electrode T13 of the first transistor on the substrate may overlap with an orthographic projection of the first via hole and the first initial signal line INIL1 on the substrate.
  • the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via hole, and is connected to the first initial signal line INIL1 through the eighth via hole.
  • the shape of the second electrode T14 of the first transistor may be a linear shape extending along the second direction Y
  • the second pole T14 of the first transistor may be located on a side of the first initial signal line INIL1 away from the reset signal line RL.
  • the orthographic projection of the second pole T14 of the first transistor (also the first pole T13 of the second transistor) on the substrate can be aligned with the second via hole, the seventh via hole, the first plate and the second plate of the first capacitor. Orthographic projections on the substrate at least partially overlap.
  • the second electrode T14 of the first transistor passes through the second via hole and the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor) connected, and connected to the first plate of the first capacitor through the seventh via hole.
  • the shape of the first pole T43 of the fourth transistor may be a block structure, and the first pole T43 of the fourth transistor may be located between the first initial signal line INIL1 and the scanning between signal lines GL.
  • the orthographic projection of the first electrode T43 of the fourth transistor on the substrate at least partially overlaps with the third via hole.
  • the first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the third via hole.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) and the first electrode T53 of the fifth transistor are respectively located on the first electrode of the first transistor.
  • the diode T14 also the first pole T23 of the second transistor.
  • the shape of the first electrode T53 of the fifth transistor may be a linear shape extending along the second direction Y, and the shape of the fifth transistor of the Mth row circuit unit may be a line shape.
  • One pole T53 may be located between the scanning signal line GL of the M-th row circuit unit and the second initial signal line INIL2 of the M+1-th row circuit unit.
  • the orthographic projection of the first electrode T53 of the fifth transistor on the substrate may at least partially overlap with the orthographic projection of the fourth via hole, the tenth via hole, the light-emitting signal line and the second plate of the capacitor on the substrate.
  • the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the fourth via hole, and is connected to the orthographic projection of the second plate of the capacitor on the substrate through the tenth via hole.
  • the second electrode T64 of the sixth transistor may have a block structure.
  • the second pole T64 of the sixth transistor of the M-th row circuit unit (the second pole T74 of the seventh transistor) may be located on the scanning signal line GL of the M-th row circuit unit and the second initial signal line of the M+1-th row circuit unit. between INIL2.
  • the orthographic projection of the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) on the substrate may at least partially overlap with the orthographic projection of the fifth via hole on the substrate.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) is connected to the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) through the fifth via hole. .
  • the orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) of the virtual pixel circuit on the substrate is consistent with the projection of the light-emitting signal line on the substrate. Orthographic projections on do not overlap.
  • the orthographic projection of the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) of the pixel circuit on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line on the substrate.
  • the first electrode T73 of the seventh transistor may be in a linear shape extending along the second direction Y.
  • the first electrode T73 of the seventh transistor is located on a side of the first initial signal line INIL1 away from the scanning signal line GL.
  • the orthographic projection of the first electrode T73 of the seventh transistor on the substrate at least partially overlaps with the orthographic projection of the sixth via hole, the ninth via hole, the reset signal line RL and the second initial signal line INIL2 on the substrate.
  • the first electrode of the seventh transistor is connected to the first region of the active layer of the seventh transistor through the sixth via hole, and is connected to the second initial signal line through the ninth via hole.
  • the third conductive layer pattern of the E1 region is substantially the same as the third conductive layer pattern of the E0 region.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the third conductive layer.
  • the fourth insulating layer is provided with multiple via holes, as shown in Figures 22 and 23.
  • Figure 22 is a schematic diagram of the E0 region and the E1 region after the fourth insulating layer pattern is formed, and Figure 23 is E2. Schematic diagram after the fourth insulating layer pattern is formed in the area.
  • the multiple vias of the fourth insulating layer pattern in the E0, E1, and E2 regions may each include: an eleventh via V11, a twelfth via Hole V12 and the thirteenth via hole V13.
  • the plurality of via holes of the fourth insulation layer pattern in the E2 region may further include: a fourteenth via hole V14.
  • the orthographic projection of the eleventh via V11 on the substrate is located in the driving circuit units in the E0 region and the E1 region and the driving circuit unit and the virtual circuit in the E2 region.
  • the first pole of the fourth transistor in the unit is within the range of the orthographic projection on the substrate, and the eleventh via hole V11 exposes the driving circuit unit in the E0 area and the E1 area, as well as the driving circuit unit and the virtual circuit in the E2 area.
  • the first pole of the fourth transistor in the unit, the eleventh via hole V11 is configured to allow the subsequently formed first connection electrode to pass through the via hole and the drive circuit unit in the E0 region and the E1 region and the drive circuit in the E2 region
  • the first pole of the fourth transistor in the unit is connected to the virtual circuit unit.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate.
  • the via V12 exposes the first electrode of the fifth transistor.
  • the twelfth via hole V12 in the E0 region is configured so that a subsequently formed third connection electrode is connected to the first electrode of the fifth transistor through the via hole.
  • the twelfth via hole V12 in the E1 region is configured so that the first sub-high voltage power supply line formed later is connected to the first electrode of the fifth transistor through the via hole.
  • the twelfth via hole V12 located in the E2 region is configured so that the third high-voltage power supply line formed later is connected to the first electrode of the fifth transistor through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is consistent with the second projection of the sixth transistor located in the driving circuit unit of the E0 region, the E1 region, and the E2 region.
  • pole (the second pole of the seventh transistor) is within the range of the orthographic projection on the substrate, and the thirteenth via hole V13 exposes the second pole of the sixth transistor in the driving circuit unit of the E0 region, the E1 region, and the E2 region (Second pole T74 of the seventh transistor).
  • the thirteenth via hole V13 is configured to allow the subsequently formed second connection electrode to pass through the via hole and the second electrode of the sixth transistor (the second electrode of the seventh transistor) in the drive circuit unit of the E0 region, the E1 region, and the E2 region. pole) connection,
  • the orthographic projection of the fourteenth via hole V14 on the substrate is within the range of the orthographic projection of the data connection block on the substrate, and the fourteenth via hole V14 exposes the data connection block, the fourteenth via hole V14 is configured to enable the subsequently formed fourth connection electrode to be connected to the data connection block through the via hole.
  • the fourth insulating layer pattern of the E1 region is substantially the same as the fourth insulating layer pattern of the E0 region.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer.
  • the fourth conductive layer on the E0 region is shown in Figure 24A, Figure 24B, Figure 25A, Figure 25B and Figure 26 to Figure 29.
  • Figure 24A is a schematic diagram of the fourth conductive layer pattern in the E0 region.
  • Figure 24B is a schematic diagram of the fourth conductive layer pattern in the E0 region. Schematic diagram 1 after the four conductive layer pattern is formed.
  • Figure 25A is a schematic diagram 2 of the fourth conductive layer pattern in the E0 region.
  • Figure 25B is a schematic diagram 2 after the fourth conductive layer pattern is formed in the E0 region.
  • Figure 26 is a schematic diagram 2 of the fourth conductive layer pattern in the E1 region. Schematic diagram of the pattern.
  • Figure 27 is a schematic diagram after the fourth conductive layer pattern is formed in the E1 region.
  • Figure 28 is a schematic diagram of the fourth conductive layer pattern in the E2 region.
  • Figure 29 is a schematic diagram after the fourth conductive layer pattern is formed in the E2 region.
  • the fourth conductive layer may be referred to as an intermediate source-drain metal (SDM) layer.
  • Figures 24A and 24B illustrate using the example that the fourth conductive layer does not include the first anode connection line.
  • Figures 25A and 25B illustrate using the example that the fourth conductive layer includes the first anode connection line.
  • the fourth conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include: a first connection electrode VL1 and a second connection electrode VL2.
  • the fourth conductive layer pattern in the E0 region may further include: a third connection electrode VL3.
  • the fourth conductive layer pattern in the E0 region may further include: a third connection electrode VL3 and a plurality of first anode connection lines AL1 .
  • the fourth conductive layer pattern in the E1 region may further include: the first sub-high-voltage power supply line VLB1 in the second high-voltage power supply line.
  • the fourth conductive layer pattern in the E2 region may further include: a third high-voltage power line VLC and a fourth connection electrode VL4.
  • the shape of the first connection electrode VL1 may be a block structure.
  • An orthographic projection of the first connection electrode VL1 on the substrate may partially overlap with an orthographic projection of the eleventh via hole on the substrate.
  • the first connection electrode VL1 is connected to the first electrode of the fourth transistor in the driving circuit unit in the E0 region and the E1 region and the driving circuit unit in the E2 region and the dummy circuit unit through the eleventh via hole.
  • the first connection electrode serves to connect the data signal line and the first electrode of the fourth transistor. This avoids the unreliability of the connection caused by opening a deeper via hole, thereby improving the reliability of the display panel. sex.
  • the shape of the second connection electrode VL2 may be a block structure.
  • the orthographic projection of the second connection electrode VL2 on the substrate may partially overlap with the orthographic projection of the thirteenth via hole on the substrate.
  • the second connection electrode VL2 is connected to the second pole of the sixth transistor (the second pole of the seventh transistor) in the drive circuit units of the E0 region, the E1 region, and the E2 region through the thirteenth via hole.
  • the second connection electrode serves to connect the fifth connection electrode and the second electrode of the sixth transistor (the second electrode of the seventh transistor), thereby avoiding connection problems caused by opening a deeper via hole. Unreliability improves the reliability of the display panel.
  • the shape of the third connection electrode VL3 may be a block structure.
  • the orthographic projection of the third connection electrode VL3 on the substrate may partially overlap with the orthographic projection of the twelfth via hole on the substrate.
  • the third connection electrode VL3 is connected to the first electrode of the fifth transistor through the twelfth via hole.
  • the third connection electrode serves to connect the first high-voltage power line and the first electrode of the fifth transistor. This avoids the unreliability of the connection caused by opening a deep via hole, thereby improving the display panel. reliability.
  • the shape of the first anode connection line AL1 may be a line shape extending along the first direction X.
  • the orthographic projection of the plurality of first anode connection lines AL1 on the substrate may overlap with the orthographic projection of the first electrode of the seventh transistor and the second plate of the capacitor on the substrate in the E0 region.
  • the first anode connection line AL1 is configured to be connected to the anode of the subsequently formed light emitting device.
  • the shape of the first sub-high-voltage power supply line VLB1 may be a polygonal shape with a main body portion extending along the second direction Y, and the first sub-high-voltage power supply line VLB1 is configured as The first pole of the fifth transistor provides the high supply voltage signal.
  • the orthographic projection of the first sub-high voltage power supply line VLB1 on the substrate respectively overlaps with the orthographic projection of the twelfth via hole and the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate.
  • the first sub-high voltage power line VLB1 is connected to the first pole of the fifth transistor through the twelfth via hole.
  • the shape of the third high-voltage power line VLC may be a polygonal shape with a main body portion extending along the second direction Y, and the third high-voltage power line VLC is configured toward E2
  • the first pole of the fifth transistor of the region provides the high supply voltage signal.
  • the orthographic projection of the third high-voltage power line VLC on the substrate respectively overlaps with the orthographic projection of the twelfth via hole and the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate.
  • the third high-voltage power line VLC is connected to the first electrode of the fifth transistor through the twelfth via hole.
  • the pattern of the third high-voltage power supply line VLC is substantially the same as the pattern of the first sub-high-voltage power supply line VLB1 and are connected to each other.
  • the third high-voltage power line VLC and the first sub-high-voltage power line VLB1 have an integrated structure.
  • the length of the third high-voltage power supply line along the first direction X may be approximately equal to the length of the first sub-high-voltage power supply line VLB1 along the first direction X.
  • the shape of the fourth connection electrode VL4 may be a block structure.
  • An orthographic projection of the fourth connection electrode VL4 on the substrate may at least partially overlap with an orthographic projection of the data connection block on the substrate.
  • the fourth connection electrode VL4 is connected to the data connection block through the fourteenth via hole.
  • the fourth connection electrode serves to connect the data connection block and the second connection line. This avoids unreliability of connection caused by opening deeper via holes, thereby improving the reliability of the display panel.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering fourth conductive layer.
  • the first flat layer is provided with multiple via holes, as shown in Figures 30 to 32.
  • Figure 30 is a schematic diagram after the first flat layer pattern is formed in the E0 area
  • Figure 31 is the formation of the E1 area.
  • a schematic diagram after the first flat layer pattern is formed.
  • FIG. 32 is a schematic diagram after the first flat layer pattern is formed in the E2 region.
  • the plurality of vias of the first flat layer pattern in the E0 region, the E1 region, and the E2 region may each include: a fifteenth via V15 and a sixteenth via Hole V16.
  • the plurality of via holes of the first flat layer pattern in the E0 region may further include: a seventeenth via hole V17.
  • the plurality of via holes of the first flat layer pattern in the E1 region may further include: an eighteenth via hole V18.
  • the plurality of via holes of the first flat layer pattern in the E2 region may further include: a nineteenth via hole V19.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is within the range of the orthographic projection of the first connection electrode on the substrate, and the fifteenth via hole V15 The first connection electrode is exposed, and the fifteenth via hole V15 is configured to allow a subsequently formed data signal line to be connected to the first connection electrode through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is within the range of the orthographic projection of the second connection electrode on the substrate, and the sixteenth via hole V16 The second connection electrode is exposed, and the sixteenth via hole V16 is configured to allow the subsequently formed fifth connection electrode to be connected to the second connection electrode through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is within the range of the orthographic projection of the third connection electrode on the substrate, and the seventeenth via hole V17 exposes the Three connected electrodes.
  • the seventeenth via hole V17 is configured to allow the first high-voltage power supply line formed later to be connected to the third connection electrode through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the first sub-high-voltage power supply line on the substrate.
  • Eighteen vias V18 expose the first sub-high voltage power line.
  • the eighteenth via hole V18 is configured to allow the second sub-high voltage power supply line of the subsequently formed second high-voltage power supply line to be connected to the first sub-high voltage power supply line of the second high-voltage power supply line through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is within the range of the orthographic projection of the fourth connection electrode on the substrate, and the nineteenth via hole V19 exposes the Four connected electrodes.
  • the nineteenth via hole V19 is configured to allow a subsequently formed second connection line to be connected to the fourth connection electrode through the via hole.
  • forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the foregoing pattern is formed, patterning the fifth conductive film using a patterning process, and forming a pattern disposed on the first planar layer.
  • Figure 33 is a schematic diagram of the fifth conductive layer pattern in the E0 region.
  • Figure 34 is a schematic diagram of the fifth conductive layer pattern in the E0 region.
  • Figure 35 is a schematic diagram of the fifth conductive layer pattern in the E1 region.
  • FIG. 36 is a schematic diagram after the fifth conductive layer pattern is formed in the E1 region.
  • FIG. 37 is a schematic diagram of the fifth conductive layer pattern in the E2 region.
  • FIG. 38 is a schematic diagram after the fifth conductive layer pattern is formed in the E2 region.
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include: a data signal line DL and a fifth connection electrode VL5.
  • the fifth conductive layer pattern in the E0 region may further include: a first high-voltage power line VLA.
  • the fifth conductive layer pattern in the E1 region may further include: a second sub-high voltage power supply line VLB2.
  • the fifth conductive layer pattern in the E2 region may further include: a second connection line 72 .
  • the data signal lines DL located in the E0 region to the E2 region and connected to the driving circuit units of the same column are connected to each other and are the same data signal line.
  • the data signal lines DL located in the E2 area and connected to the virtual driving circuit units of the same column are connected to each other and are the same data signal line.
  • the data signal lines DL located in the E0 area and the E1 area and connected to adjacent circuit units are arranged at intervals.
  • the shape of the data signal line DL may be a line shape extending along the second direction Y.
  • the orthographic projection of the data signal line DL on the substrate at least partially overlaps the orthographic projection of the fifteenth via hole on the substrate.
  • the data signal line DL is connected to the first connection electrode through the fifteenth via hole.
  • the shape of the fifth connection electrode VL5 may be a block structure.
  • the orthographic projection of the fifth connection electrode VL5 on the substrate partially overlaps with the orthographic projection of the sixteenth via hole on the substrate.
  • the fifth connection electrode VL5 is connected to the second connection electrode through the sixteenth via hole.
  • the fifth connection electrode serves to connect the anode of the light-emitting device and the second connection line, which improves the reliability of the display panel by avoiding connection unreliability caused by opening a deep via hole.
  • the shape of the first high-voltage power line VLA may be a polygonal shape with a main body portion extending along the second direction Y, and the first high-voltage power line VLA is configured to be directed toward E0
  • the first pole of the fifth transistor of the region provides the high supply voltage signal.
  • the first high-voltage power supply line VLA is located between the data line DL and the fifth connection electrode VL5.
  • the orthographic projection of the first high-voltage power line VLA on the substrate overlaps with the orthographic projection of the seventeenth via hole and the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate respectively.
  • the first high-voltage power line VLA is connected to the third connection electrode through the seventeenth via hole.
  • the length of the data signal line DL along the first direction is smaller than the length of the first high-voltage power supply line VLA along the first direction.
  • the first high-voltage power supply line VLA may have substantially the same pattern as the third high-voltage power supply line and the first sub-high-voltage power supply line, respectively.
  • the length of the first high-voltage power supply line VLA along the first direction may be substantially the same as the lengths of the third high-voltage power supply line and the first sub-high-voltage power supply line along the first direction.
  • the shape of the second sub-high-voltage power supply line VLB2 may be a polygonal shape with a main part extending along the second direction Y, and the second sub-high-voltage power supply line VLB2 is configured as A high supply voltage signal is provided to the first pole of the fifth transistor in the E1 region.
  • the second sub-high voltage power supply line VLB2 is located between the data line DL and the fifth connection electrode VL5.
  • the orthographic projection of the second sub-high-voltage power line VLB2 on the substrate partially overlaps with the orthographic projection of the eighteenth via hole on the substrate.
  • the second sub-high voltage power line VLB2 is connected to the first sub-high voltage power line VLB2 through the eighteenth via hole.
  • the second sub-high-voltage power supply line VLB2 is connected to the first high-voltage power supply line.
  • the length of the data signal line DL along the first direction is substantially the same as the length of the second sub-high voltage power supply line VLB2 along the first direction.
  • the shape of the second connection line 72 may be a line shape in which the main body portion extends along the second direction Y.
  • the second connection line 72 is located between the data signal line DL and the fifth connection electrode VL5.
  • the orthographic projection of the second connection line 72 on the substrate partially overlaps with the orthographic projection of the nineteenth via hole and the first connection line on the substrate respectively.
  • the second connection line 72 is connected to the fourth connection electrode through the nineteenth via hole.
  • the pattern of the second connection line 72 may be substantially the same as the pattern of the second sub-high voltage power supply line.
  • the orthographic projections of the second connection line 72 and the third high-voltage power line on the substrate at least partially overlap.
  • the length of the data signal line DL along the first direction may be substantially the same as the length of the second connection line 72 along the first direction.
  • forming the second flat layer pattern may include: coating a second flat film on the substrate on which the foregoing pattern is formed, patterning the second flat film using a patterning process, and forming a covering fifth conductive layer.
  • the second flat layer is provided with multiple via holes, as shown in Figures 39 to 41.
  • Figure 39 is a schematic diagram after the second flat layer pattern is formed in the E0 area
  • Figure 40 is the formation of the E1 area.
  • a schematic diagram after the second flat layer pattern is formed.
  • FIG. 41 is a schematic diagram after the second flat layer pattern is formed in the E2 region.
  • the plurality of via holes of the second flat layer pattern in the E0 region, the E1 region, and the E2 region may each include: a twentieth via hole V20.
  • the orthographic projection of the twentieth via hole V20 on the substrate is within the range of the orthographic projection of the fifth connection electrode on the substrate, and the twentieth via hole V20 The fifth connection electrode is exposed.
  • the twentieth via hole V20 is configured to connect the anode of the subsequently formed light emitting device to the fifth connection electrode through the via hole.
  • the position of the twentieth via V20 in multiple circuit units may be different.
  • the via hole patterns of the second flat layer patterns of the E0 region, the E1 region, and the E2 region are substantially the same.
  • forming the third flat layer pattern may include: coating a transparent conductive film on the substrate on which the foregoing pattern is formed, patterning the transparent conductive film using a patterning process, and forming a pattern covering the second flat layer.
  • the transparent conductive layer is coated with a third flat film on the base on which the pattern of the transparent conductive layer is formed.
  • the third flat film is patterned using a patterning process to form a third flat layer covering the transparent conductive layer.
  • the third flat layer A via hole exposing the fifth connection electrode is provided on the top.
  • the transparent conductive layer may include: a second anode connection line.
  • the driver circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel circuit, as well as a scanning signal line, a reset signal line, a light-emitting signal line, and a data signal line connected to the pixel circuit.
  • the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third insulating layer sequentially stacked on the substrate.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polyether One or more of styrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • the transparent conductive layer may be indium tin oxide ITO or indium zinc oxide IZO, or may be a multi-layer composite structure, such as ITO/Ag/ITO, etc.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride Any one or more of (SiON) can be a single layer, multi-layer or composite layer.
  • the first insulating layer may be called a buffer layer
  • the second and third insulating layers may be called gate insulating (GI) layers
  • the fourth insulating layer may be called an interlayer insulating (ILD) layer
  • the fifth insulating layer may be called a gate insulating (GI) layer.
  • the layer may be called a passivation (PVX) layer.
  • the first flat layer, the second flat layer and the third flat layer may be made of organic materials, such as resin.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a light-emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light-emitting structure layer may include the following operations.
  • Form an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the foregoing pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode disposed on the third flat layer.
  • the conductive layer pattern is as shown in Figures 42 to 45.
  • Figure 42 is a schematic diagram of the anode conductive layer pattern.
  • Figure 43 is a schematic diagram of the E0 region after the anode conductive layer pattern is formed.
  • Figure 44 is a schematic diagram of the E1 region after the anode conductive layer pattern is formed.
  • Figure 45 is a schematic diagram after the anode conductive layer pattern is formed in the E2 region.
  • the anode conductive layer adopts a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may adopt a multi-layer composite structure, such as ITO/Ag/ITO, etc.
  • the anode conductive layer pattern may include a first anode 301R of the red light emitting device, a second anode 301B of the blue light emitting device, a third anode 301G1 of the first green light emitting device, and a third anode 301G1 of the second green light emitting device.
  • the area where the first anode 301R is located can form a red sub-pixel R emitting red light
  • the area where the second anode 301B is located can form a blue sub-pixel B emitting blue light
  • the area where the third anode 301G1 is located can form a green sub-pixel emitting
  • the area where the first green sub-pixel G1 and the fourth anode 301G2 are located may form a second green sub-pixel G2 that emits green light.
  • the first anode 301A and the second anode 301B may be disposed in sequence along the second direction Y
  • the third anode 301C and the fourth anode 301D may be disposed in sequence along the second direction Y
  • the third anode 301C and the fourth anode 301D may be disposed in sequence along the second direction Y.
  • the fourth anode 301D may be disposed on one side of the first anode 301A and the second anode 301B in the first direction X.
  • first anode 301A and the second anode 301B may be disposed in sequence along the first direction X
  • the third anode 301C and the fourth anode 301D may be disposed in sequence along the first direction X
  • third anode 301C and the fourth anode 301D may be Disposed on one side of the first anode 301A and the second anode 301B in the second direction Y.
  • the first anode 301R, the second anode 301B, the third anode 301G1 and the fourth anode 301G2 may be connected to the fifth connection electrode in the corresponding circuit unit through the twentieth via hole V20 respectively. Since the anode of each is connected to the second electrode of the sixth transistor (also the second electrode of the seventh active layer) through the fifth connection electrode and the second connection electrode in one circuit unit, four of the four light-emitting units in one light-emitting unit The anodes are respectively connected to the pixel circuits of the four circuit units, so that the pixel circuit can drive the light-emitting device to emit light.
  • the anode shape and area of four sub-pixels in one light-emitting unit may be the same or different, and the positional relationship between the four sub-pixels of one light-emitting unit and the four circuit units in one circuit unit group may be the same, Or they may be different.
  • the shapes and positions of the first anode 301R, the second anode 301B, the third anode 301G1 and the fourth anode 301G2 in different light-emitting units may be the same or different. This disclosure is not limited here.
  • At least one of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D may include a main body part and a connecting part connected to each other, and the shape of the main body part may be a rectangular shape, The corners of the rectangular shape can be provided with arc-shaped chamfers, and the shape of the connecting portion can be a strip shape extending in a direction away from the main body.
  • the connecting portion is connected to the fifth connecting electrode through twenty via holes V20.
  • the orthographic projection of the main body portions of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D on the substrate and the second connection line and the data signal line on the substrate orthographic projections at least partially overlap.
  • the orthographic projection of the main body parts of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D on the substrate is in line with the second sub-high voltage power supply line and the data signal line. Orthographic projections on the substrate at least partially overlap.
  • the orthographic projection of the main body portions of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D on the substrate is the same as the first high-voltage power supply line and the data signal line on the substrate. Orthographic projections on at least partially overlap.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.
  • the structural layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may use inorganic materials.
  • the second encapsulation layer may use organic materials.
  • the second encapsulation layer is provided Between the first encapsulation layer and the third encapsulation layer, it can be ensured that external water vapor cannot enter the light-emitting structure layer.
  • the display panel of the present disclosure may be applied to a display device having a pixel circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED). ), etc., this disclosure is not limited here.
  • a display device having a pixel circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED). ), etc., this disclosure is not limited here.
  • FIG. 46 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 46 , an embodiment of the present disclosure also provides a display device.
  • the display device includes the display panel 1 provided in any of the foregoing embodiments and a photosensitive sensor 2 .
  • the photosensitive sensor is located in the light-transmitting display area 10 of the display panel 1 . .
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the present disclosure is not limited thereto.
  • the orthographic projection area of the photosensitive sensor 2 on the substrate is less than or equal to the area of the inscribed circle of the light-transmitting display area 10 .
  • the photosensitive sensor 2 may include a camera module (for example, a front-facing camera module), a 3D structured light module (for example, a 3D structured light sensor), a time-of-flight 3D imaging module (for example, a flying At least one of time method sensor), infrared sensing module (for example, infrared sensing sensor), etc.
  • a camera module for example, a front-facing camera module
  • a 3D structured light module for example, a 3D structured light sensor
  • a time-of-flight 3D imaging module for example, a flying At least one of time method sensor
  • infrared sensing module for example, infrared sensing sensor
  • the front camera module is usually enabled when the user takes a selfie or makes a video call, and the display area of the display device displays the image obtained by taking a selfie for the user to view.
  • the front camera module includes, for example, a lens, an image sensor, an image processing chip, etc.
  • the optical image generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS) and converted into electrical signals. After analog-to-digital conversion by the image processing chip, it becomes a digital image signal and then sent to the processor for processing.
  • the image of the scene is output on the display screen.
  • a 3D structured light sensor and a Time of Flight (ToF) sensor may be used for face recognition to unlock the display device.
  • ToF Time of Flight
  • the display device provided by the embodiment of the present disclosure can display images in the light-transmitting display area to maintain the display integrity of the entire display device.

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Abstract

一种显示面板(1)和显示装置，显示面板(1)包括: 显示区域(100)，显示区域(100)包括: 透光显示区(10)和位于透光显示区(10)至少一侧的常规显示区，常规显示区包括第一区域(100A)、第二区域(100B)和第三区域(100C)；常规显示区中的第一区域(100A)的至少一个电路单元与透光显示区(10)中的发光器件(L)连接，常规显示区中的第三区域 (100C)的至少一个电路单元包括数据连接线(70),第二高压电源线包括: 相互连接的第一子高压电源线(VLB1)和第二子高压电源线(VLB2)，第二子高压电源线(VLB2)位于第一子高压电源线(VLB1)远离基底(101)的一侧，第一高压电源线(VLA)与第二子高压电源线(VLB2)同层设置，第三高压电源线(VLC)与第一子高压电源线(VLB1)同层设置。

Description

显示面板和显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示面板，包括：显示区域，所述显示区域包括：透光显示区和位于透光显示区至少一侧的常规显示区，所述常规显示区包括第一区域、第二区域和第三区域，所述第一区域的至少一个电路单元与透光显示区中的发光器件连接，所述第三区域的至少一个电路单元包括数据连接线，位于第一区域的高压电源线为第一高压电源线，位于第二区域的高压电源线为第二高压电源线，位于第三区域的高压电源线为第三高压电源线；
所述第二高压电源线包括：相互连接的第一子高压电源线和第二子高压电源线，所述第二子高压电源线位于所述第一子高压电源线远离基底的一侧，所述第一高压电源线与所述第二子高压电源线同层设置，所述第三高压电源线与所述第一子高压电源线同层设置。
在示例性实施方式中，所述数据连接线包括：相互连接的第一连接线和 沿第二方向延伸的第二连接线，所述第一连接线位于第三高压电源线靠近基底的一侧，所述第二连接线与所述第一高压电源线同层设置；
所述第一连接线在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，所述第二连接线在基底上的正投影与所述第三高压电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一连接线包括：沿第二方向延伸的第一数据连接部和沿第一方向延伸的第二数据连接部，所述第一数据连接部分别与第二数据连接部和第二连接线连接，所述第一方向和所述第二方向交叉；
所述第一数据连接部在基底上的正投影与数据信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第二子高压电源线沿第一方向的长度小于第一子高压电源线沿第一方向的长度，且第二子高压电源线在基底上的正投影与第一子高压电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一高压电源线沿第一方向、所述第一子高压电源线沿第一方向的长度和所述第三高压电源线近似相等，且所述第一高压电源线的形状、所述第一子高压电源线的形状和所述第三高压电源线的形状大致相同。
在示例性实施方式中，所述第二子高压电源线沿第一方向的长度与第二连接线沿第一方向的长度近似相等，且所述第二子高压电源线的形状与所述第二连接线的形状大致相同。
在示例性实施方式中，第二子高压电源线在基底上的正投影与第一子高压电源线在基底上的正投影的重叠区域的面积大于第二连接线在基底上的正投影与第三高压电源线在基底上的正投影的重叠区域的面积。
在示例性实施方式中，所述发光器件包括：阳极、有机发光层和阴极，所述显示面板还包括：沿第一方向延伸的多条第一阳极连接线，所述第一阳极连接线与所述第三高压电源线同层设置，且被配置为连接所述第一区域的至少一个电路单元和位于透光显示区的发光器件的阳极。
在示例性实施方式中，所述透光显示区包括：中心区域和围设在所述中 心区域外侧的边缘区域；所述显示面板还包括：第二阳极连接线，所述第二阳极连接线位于第一高压电源线远离基底的一侧；
所述第一阳极连接线被配置为连接所述第一区域的至少一个电路单元和位于所述边缘区域的发光器件的阳极，所述第二阳极连接线被配置为连接所述第一区域的至少一个电路单元和位于所述中心区域的发光器件的阳极。
在示例性实施方式中，所述第一阳极连接线包括：金属信号线，所述第二阳极连接线包括：透明导电信号线。
在示例性实施方式中，所述发光结构层包括：多个发光单元，至少一个发光单元包括：第一发光器件、第二发光器件和第三发光器件，不同发光器件发射不同颜色的光线，所述第一发光器件和所述第二发光器件发射红色或者蓝色光线，所述第三发光器件发射绿色光线；
对于位于边缘区域的发光单元，与同一发光单元的第三发光器件连接的第一阳极连接线沿第一方向的长度小于与同一发光单元的第一发光器件和第二发光器件连接的第一阳极连接线沿第一方向的长度。
在示例性实施方式中，与位于边缘区域的任一第三发光器件连接的第一阳极连接线沿第一方向的长度小于与位于边缘区域的任一第一发光器件连接的第一阳极连接线和位于边缘区域的任一第二发光器件连接的第一阳极连接线沿第一方向的长度。
在示例性实施方式中，所述边缘区域占所述透光显示区的面积约为3％至8％，或者所述边缘区域包括的发光单元的数量为透光显示区中发光单元数量的5％至10％。
在示例性实施方式中，所述像素电路至少包括电容和多个晶体管，所述电容包括：第一极板和第二极板；所述显示面板包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层、第一平坦层、第五导电层；
所述半导体层至少包括多个晶体管的有源层；所述第一导电层至少包括多个晶体管的栅电极和电容的第一极板，所述第二导电层至少包括电容的第二极板，所述第三导电层至少包括多个晶体管的第一极和第二极以及第一连 接线，所述第四导电层至少包括第一阳极连接线、第一子高压电源线和第三高压电源线，所述第五导电层至少包括：数据信号线、第一高压电源线、第二子高压电源线和第二连接线。
在示例性实施方式中，所述像素电路包括：写入晶体管，所述写入晶体管与数据信号线连接，位于第三区域的电容的第二极板包括：相互连接的电容主体部和辅助电容部，所述电容主体部与位于所述第一区域和所述第二区域的电容的第二极板的形状大致相同；辅助电容部在基底上的正投影与写入晶体管的有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第三导电层还包括：数据连接块，数据连接块在基底上的正投影与辅助电容部和第二连接线在基底上的正投影至少部分交叠；
所述数据连接块分别与第一连接线和第二连接线连接。
在示例性实施方式中，数据连接块和第二数据连接部位于第一数据连接部的同一侧，且与第一数据连接部电连接；
第一数据连接部在基底上的正投影与电容的第二极板在基底上的正投影至少部分交叠。
在示例性实施方式中，所述像素电路还包括：第一发光晶体管和第二发光晶体管，第一发光晶体管与高压电源线连接，第二发光晶体管与发光器件的阳极连接，所述第四导电层还包括：第一连接电极、第二连接电极、第三连接电极和第四连接电极；
第一连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极电连接，第二连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极，第三连接电极在基底上的正投影与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极连接，第四连接 电极在基底上的正投影与数据连接块在基底上的正投影至少部分交叠，且与数据连接块在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第五导电层还包括：第五连接电极，第五连接电极在基底上的正投影与第二连接电极在基底上的正投影至少部分交叠，且与第二连接电极连接。
在示例性实施方式中，多条第一阳极连接线在基底上的正投影可以与电容的第二极板和所连接的发光器件的阳极在基底上的正投影至少部分交叠。
在示例性实施方式中，数据信号线在基底上的正投影与第一连接电极在基底上的正投影至少部分交叠，且与第一连接电极连接，第一高压电源线在基底上的正投影与第三连接电极在基底上的正投影至少部分交叠，且与第三连接电极连接，第二连接线在基底上的正投影与第四连接电极在基底上的正投影至少部分交叠，且与第四连接电极连接。
在示例性实施方式中，还包括位于第二平坦层远离基底一侧的透明导电层，所述透明导电层包括第二阳极连接线，所述第二阳极连接线与第五连接电极在基底上的正投影至少部分交叠，且与第五连接电极连接。
第二方面，本公开还提供了一种显示装置，包括：上述显示面板和感光传感器，所述感光传感器位于所述显示面板的透光显示区内
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示面板的结构示意图；
图3为一种显示面板中显示区域的平面结构示意图；
图4A为一种像素电路的等效电路示意图；
图4B为一种像素电路的工作时序图；
图5A为本公开示例性实施例一种显示面板的平面结构示意图；
图5B为图5A沿A-A向的剖视图；
图5C为本公开示例性实施例一种数据连接线的排布示意图；
图6为本公开示例性实施例一种显示区域的分区示意图；
图7A为本公开实施例提供的图6中的E0区域、E1区域和E2区域的结构示意图；
图7B为本公开实施例提供的图6中的E0区域的结构示意图；
图7C为本公开实施例提供的图6中的E1区域的结构示意图；
图7D为本公开实施例提供的图6中的E2区域的结构示意图；
图8A为一种显示面板的第一阳极连接线的布线示意图；
图8B为一种显示面板的第一阳极连接线的连接示意图；
图8C为一种显示面板的第一阳极连接线的局部布线示意图一；
图8D为一种显示面板的第一阳极连接线的局部布线示意图二；
图8E为图6中E0区域的另一结构示意图；
图9为E0区域、E1区域和E2区域形成半导体图案后的示意图；
图10为E0区域、E1区域和E2区域的第一导电层图案的示意图；
图11为E0区域、E1区域和E2区域形成第一导电层图案后的示意图；
图12为E0区域和E1区域的第一导电层图案的示意图；
图13为E0区域和E1区域形成第一导电层图案后的示意图；
图14为E2区域的第一导电层图案的示意图；
图15为E2区域形成第一导电层图案后的示意图；
图16为E0区域和E1区域形成第三绝缘层图案后的示意图；
图17为E2区域形成第三绝缘层图案后的示意图；
图18为E0区域和E1区域的第三导电层图案的示意图；
图19为E0区域和E1区域形成第三导电层图案后的示意图；
图20为E2区域的第三导电层图案的示意图；
图21为E2区域形成第三导电层图案后的示意图；
图22为E0区域和E1区域形成第四绝缘层图案后的示意图；
图23为E2区域形成第四绝缘层图案后的示意图；
图24A为E0区域的第四导电层图案的示意图一；
图24B为E0区域形成第四导电层图案后的示意图一；
图25A为E0区域的第四导电层图案的示意图二；
图25B为E0区域形成第四导电层图案后的示意图二；
图26为E1区域的第四导电层图案的示意图；
图27为E1区域形成第四导电层图案后的示意图；
图28为E2区域的第四导电层图案的示意图；
图29为E2区域形成第四导电层图案后的示意图；
图30为E0区域形成第一平坦层图案后的示意图；
图31为E1区域形成第一平坦层图案后的示意图；
图32为E2区域形成第一平坦层图案后的示意图；
图33为E0区域的第五导电层图案的示意图；
图34为E0区域形成第五导电层图案后的示意图；
图35为E1区域的第五导电层图案的示意图；
图36为E1区域形成第五导电层图案后的示意图；
图37为E2区域的第五导电层图案的示意图；
图38为E2区域形成第五导电层图案后的示意图；
图39为E0区域形成第二平坦层图案后的示意图；
图40为E1区域形成第二平坦层图案后的示意图；
图41为E2区域形成第二平坦层图案后的示意图；
图42为阳极导电层图案的示意图；
图43为E0区域形成阳极导电层图案后的示意图；
图44为E1区域形成阳极导电层图案后的示意图；
图45为E2区域形成阳极导电层图案后的示意图；
图46为本公开实施例提供的显示装置的结构示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、 “连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”是指数值相差10％以内的情况。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括： 时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列。时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接。数据驱动器分别与多个数据信号线(例如，D1到Dn)连接，扫描驱动器分别与多个扫描信号线(例如，S1到Sm)连接，发光驱动器分别与多个发光信号线(例如，E1到Eo)连接。其中，n、m和o可以是自然数。像素阵列可以包括多个子像素Pxij，i和j可以是自然数。至少一个子像素Pxij可以包括：电路单元和与电路单元连接的发光器件。电路单元可以至少包括像素电路，像素电路可以分别与扫描信号线、发光信号线和数据信号线连接。
在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发光控制信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发光控制信号。
图2为一种显示面板的结构示意图。如图2所示，显示面板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在一些示例中，显示区域100可以是平坦的区域， 包括组成像素阵列的多个子像素Pxij，多个子像素Pxij可以被配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在一些示例中，显示面板可以采用柔性基板，因而显示面板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域100，扇出区以扇出(Fanout)走线方式将绑定区域中集成电路和绑定焊盘的信号线引入到较宽的显示区域。扇出区至少包括数据扇出(Fanout)线，多条数据扇出线被配置为以扇出走线方式连接显示区域100的数据信号线，并延伸至弯折区。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使驱动芯片区和绑定引脚区弯折到显示区域100的背面。驱动芯片区可以设置集成电路(IC，Integrated Circuit)，集成电路可以被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，绑定焊盘可以被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接。在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素电路所连接的扫描信号线、复位信号线和发光信号线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示面板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构。显示区域边缘是显示区域100靠近绑定区域200或者边框区域300一侧的边缘。
图3为一种显示面板中显示区域的平面结构示意图。如图3所示，显示 面板可以包括以矩阵方式排布的多个像素单元P。至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素电路，像素电路分别与扫描信号线、数据信号线和发光信号线连接，像素电路可以被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素电路连接，发光器件被配置为响应所在子像素的像素电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在一些示例中，子像素的发光器件的形状可以是矩形状、菱形、五边形或六边形，四个子像素的发光器件可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施例中，四个子像素的发光器件可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素的发光器件可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，在垂直于显示面板的方向上，显示面板可以包括：基底、依次设置在基底上的驱动电路层、发光结构层以及封装结构层。在一些可能的实现方式中，显示面板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层可以包括由多个晶体管和电容构成的像素电路。每个子像素的发光结构层可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以 采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，有机发光层可以包括发光层(EL)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在一些示例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是各自连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图4A为一种像素电路的等效电路示意图。在示例性实施方式中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。本示例性实施例的像素电路以7T1C结构为例进行说明。然而，本实施例对此并不限定。
在示例性实施方式中，如图4A所示，本示例的像素电路可以包括七个晶体管(即第一晶体管T1至第七晶体管T7)和一个电容C。像素电路分别与8个信号线(例如包括：数据信号线DL、扫描信号线GL、复位信号线RL、发光信号线EL、第一初始信号线INIL1、第二初始信号线INIL2、高压电源线VDD和低压电源线VSS)连接。
在示例性实施方式中，像素电路的七个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，像素电路的七个晶体管可以包括P型晶体管和N型晶体管。
在示例性实施方式中，像素电路的七个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示 面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，高压电源线VDD可以配置为向像素电路提供恒定的第一电压信号，低压电源线VSS可以配置为向像素电路提供恒定的第二电压信号，并且第一电压信大于第二电压信号。扫描信号线GL可以配置为向像素电路提供扫描信号，数据信号线DL可以配置为向像素电路提供数据信号，发光信号线EL可以配置为向像素电路提供发光控制信号。在一些示例中，在第n行像素电路中，复位信号线RL可以与第n-1行像素电路的扫描信号线GL电连接，以被输入扫描信号。其中，n为大于0的整数。如此，可以减少显示面板的信号线，实现显示面板的窄边框设计。然而，本实施例对此并不限定。
在示例性实施方式中，第一初始信号线INIL1可以配置为向像素电路提供第一初始信号，第二初始信号线INIL2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于高压电源线VDD提供的第一电压信号和低压电源线VSS提供的第二电压信号之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在示例性实施方式中，如图4A所示，第一晶体管T1的栅极与复位信号线RL电连接，第一晶体管T1的第一极与第一初始信号线INIL1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连接。第二晶体管T2的栅极与扫描信号线GL电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第三晶体管T3的栅极与第一节点N1电连接，第一极与第二节点N2电连接，第二极与第三节点N3电连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅极与第一极之间的电位差来确定在高压电源线VDD与低压电源线VSS之间流动的驱动电流的量。第四晶体管T4的栅极与扫描信号线GL电连接，第四晶体管T4的第一极与数据信号线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第四晶体管可以成为写入晶体 管。第五晶体管T5的栅极与发光信号线EL电连接，第五晶体管T5的第一极与高压电源线VDD电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第五晶体管可以成为第一发光晶体管。第六晶体管T6的栅极与发光信号线EL电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光器件L的阳极电连接。第六晶体管T6可以称为第二发光晶体管。第七晶体管T7的栅极与复位信号线RL电连接，第七晶体管T7的第一极与第二初始信号线INIL2电连接，第七晶体管T7的第二极与发光器件L的阳极电连接。电容C的第一极板与第三晶体管T3的栅极电连接，电容C的第二极板与高压电源线VDD电连接。
在本示例中，第一节点N1为电容C、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光器件L的连接点。
在示例性实施方式中，发光器件L可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。发光器件的第二极与低压电源线VSS连接，低压电源线VSS的信号为持续提供的低电平信号，高压电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，图4B为一种像素电路的工作时序图，如图4A和4B所示，以像素电路包括的第一晶体管T1至第七晶体管T7均为P型晶体管为例，像素电路的工作过程可以包括以下阶段。
第一阶段A1，称为复位阶段。复位信号线RL提供的低电平信号，使第一晶体管T1导通，第一初始信号线INIL1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除电容C中原有数据电压。扫描信号线GL提供高电平信号，发光信号线EL提供高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7断开。此阶段发光器件L不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。扫描信号线GL提 供低电平信号，复位信号线RL和发光信号线EL均提供高电平信号，数据信号线DL输出数据信号DATA。此阶段由于电容C的第一极板为低电平，因此第三晶体管T3导通。扫描信号线GL提供低电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通，使得数据信号线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线DL输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入电容C，电容C的第一极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据信号线DL输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通，使得第二初始信号线INIL2提供的第二初始信号提供至发光器件L的阳极，对发光器件L的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光器件L不发光。复位信号线RL提供高电平信号，使第一晶体管T1断开。发光信号线EL提供高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3，称为发光阶段。发光信号线EL提供低电平信号，扫描信号线GL和复位信号线RL均提供高电平信号。发光信号线EL提供低电平信号，使第五晶体管T5和第六晶体管T6导通，高压电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件L的阳极提供驱动电压，驱动发光器件L发光。
在像素电路的驱动过程中，流过第三晶体管T3(即驱动晶体管)的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(Vdd-Vdata+|Vth|)-Vth] 2＝K×[Vdd-Vdata] 2。
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线DL输出的数据电压，Vdd为高压电源线VDD输出的第一电压信号。
由上式中可以看到流经发光器件L的电流与第三晶体管T3的阈值电压无关。本实施例的像素电路可以较好地补偿第三晶体管T3的阈值电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示面板中，绑定区域通常包括沿着远离显示区域的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。由于绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出(Fanout)走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，因而扇形区占用空间较大，导致下边框的窄化设计难度较大，下边框一直维持在2.0毫米(mm)左右。
另外，全面屏手机的概念已在手机市场受到广泛的关注，也是未来手机的发展方向。全面屏手机中采用将摄像头设置在显示区内(Full Display with Camera，简称FDC)结构，即摄像头所在的区域也会显示。FDC结构可以使正面可视区域几乎全是屏幕，从而使用户得到较佳的显示效果。
本公开示例性实施例提供了一种显示面板，采用数据连接线位于显示区域(Fanout in AA，简称FIAA)结构，多条数据连接线的一端与显示区域中的多条数据信号线对应连接，多条数据连接线的另一端延伸到绑定区域，与绑定区域的集成电路对应连接。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，有效减小了下边框宽度。
本公开示例性实施例提供了一种显示面板，包括：显示区域，显示区域包括：透光显示区和位于透光显示区至少一侧的常规显示区，所述常规显示区包括第一区域、第二区域和第三区域，所述第一区域的至少一个电路单元与透光显示区中的发光器件连接，所述第三区域的至少一个电路单元包括数据连接线，位于第一区域的高压电源线为第一高压电源线，位于第二区域的高压电源线为第二高压电源线，位于第三区域的高压电源线为第三高压电源线；
所述第二高压电源线包括：相互连接的第一子高压电源线和第二子高压电源线，所述第二子高压电源线位于所述第一子高压电源线远离基底的一侧，所述第一高压电源线与所述第二子高压电源线同层设置，所述第三高压电源 线与所述第一子高压电源线同层设置。
在示例性实施方式中，显示区域包括：基底以及依次叠设在基底上的驱动电路层和发光结构层，驱动电路层包括多个电路单元、多条数据信号线、多条数据连接线和多条高压电源线；发光结构层包括多个发光器件，电路单元包括像素电路，数据信号线被配置为向像素电路提供数据信号，高压电源线被配置为向像素电路提供高电源电压信号，数据连接线与数据信号线连接。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，发光结构层可以包括：多个发光器件，至少一个发光器件包括：阳极、有机发光层和阴极。发光器件的形状可以是三角形、正方形、矩形、菱形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，本公开在此不做限定。
本公开实施例提供的显示面板包括：显示区域，显示区域包括：透光显示区和位于透光显示区至少一侧的常规显示区，常规显示区包括第一区域、第二区域和第三区域，第一区域的至少一个电路单元与透光显示区中的发光器件连接，第三区域的至少一个电路单元包括数据连接线，位于第一区域的高压电源线为第一高压电源线，位于第二区域的高压电源线为第二高压电源线，位于第三区域的高压电源线为第三高压电源线；第二高压电源线包括：相互连接的第一子高压电源线和第二子高压电源线，第二子高压电源线位于第一子高压电源线远离基底的一侧，第一高压电源线与第二子高压电源线同层设置，第三高压电源线与第一子高压电源线同层设置。本公开实施例通过常规显示区的不同区域设置不同的高压电源线，在保证了显示效果的同时，还实现了FIAA结构和FDC结构的兼容。
在示例性实施方式中，所述数据连接线包括：相互连接的第一连接线和沿第二方向延伸的第二连接线，所述第一连接线位于第三高压电源线靠近基底的一侧，所述第二连接线与所述第一高压电源线同层设置；
所述第一连接线在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，所述第二连接线在基底上的正投影与所述第三高压电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一连接线包括：沿第二方向延伸的第一数据连接部和沿第一方向延伸的第二数据连接部，所述第一数据连接部分别与第二数据连接部和第二连接线连接，所述第一方向和所述第二方向交叉；
所述第一数据连接部在基底上的正投影与数据信号线在基底上的正投影至少部分交叠。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
图5A为本公开示例性实施例一种显示面板的平面结构示意图，图5B为图5A沿A-A向的剖视图。如图5A和图5B所示，在垂直于显示面板的平面上，显示面板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装结构层104。在平行于显示面板的平面上，显示面板可以至少包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200和位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100的驱动电路层可以包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素电路，像素电路被配置为向所连接的发光器件输出相应的电流。显示区域100的发光结构层可以包括构成像素阵列的多个子像素，至少一个子像素可以包括发光器件，发光器件与对应电路单元的像素电路连接，发光器件被配置为响应所连接的像素电路输出的电流发出相应亮度的光。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素电路的多个晶体管和存储电容，图5B中仅以一个晶体管210和一个存储电 容220作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，基底可以是刚性基底，或者可以是柔性基底。在示例性实施方式中，刚性基底可以采用玻璃或石英等材料，柔性基底可以采用聚酰亚胺(PI)等材料，柔性基底可以是单层结构，或者可以是无机材料层和柔性材料层构成的叠层结构，本公开在此不做限定。
在示例性实施方式中，如图5A所示，显示区域100的驱动电路层还可以包括多条数据信号线60和多条数据连接线70，至少一条数据信号线60与一个单元列中的多个像素电路连接，数据信号线60被配置为向所连接的像素电路提供数据信号，至少一条数据连接线70与数据信号线60对应连接，数据连接线70被配置为使数据信号线60通过数据连接线70与绑定区域200中的引出线210对应连接。
在示例性实施方式中，本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素电路划分的区域。在示例性实施方式中，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施方式中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。在示例性实施方式中，第二方向Y可以是数据信号线的延伸方向(竖直方向)，第一方向X可以与第二方向Y垂直(水平方向)。
在示例性实施方式中，位于第一区域、第二区域和第三区域中的电路单 元可以包括：驱动电路单元和虚拟电路单元，驱动电路单元中的像素电路可以被配置为驱动发光器件发光，虚拟电路单元中的像素电路不会被配置为驱动发光器件发光，保证显示面板的显示均一性所设置的。虚拟电路单元可以设置在驱动电路单元之间。
在示例性实施方式中，绑定区域200可以至少包括沿着远离显示区域方向依次设置的引线区201、弯折区和驱动芯片区，引线区201连接到显示区域100，弯折区连接到引线区201，驱动芯片区连接到弯折区。引线区201可以设置多条引出线210，多条引出线210可以沿着第二方向Y延伸，多条引出线210的第一端与复合电路区的集成电路连接，多条引出线210的第二端跨过弯折区延伸到引线区201后与数据连接线70对应连接，使得集成电路通过引出线和数据连接线将数据信号施加到数据信号线。由于数据连接线设置在显示区域，因而可以有效减小引线区第二方向Y的长度，大大缩减下边框宽度，提高了屏占比，有利于实现全面屏显示。
在示例性实施方式中，设置在显示区域100的多条数据信号线的形状可以是沿着第二方向Y延伸的线形状，设置在显示区域100的多条数据连接线70的形状可以是折线状，数据连接线70可以包括部分沿着第一方向X延伸的第一连接线和沿着第二方向Y延伸的第二连接线，多条第一连接线的第一端(数据连接线70的第一端)通过连接孔与多条数据信号线60对应连接，多条第一连接线的第二端沿着第一方向X或者第一方向X的反方向延伸后与第二连接线的第一端连接，多条第二连接线的第二端(条数据连接线70的第二端)向着绑定区域200的方向延伸并跨过显示区域边界B，与引线区201的多条引出线210对应连接。在示例性实施方式中，显示区域边界B可以是显示区域100和绑定区域200的交界处。
在示例性实施方式中，数据连接线70与引出线210可以直接连接，或者可以通过过孔连接，本公开在此不做限定。
在示例性实施方式中，多条第二连接线可以设置成与数据信号线60平行。
在示例性实施方式中，相邻第二连接线之间第一方向X的间距可以基本上相同，相邻第一连接线之间第二方向Y的间距可以基本上相同，本公开在此不做限定。
在示例性实施方式中，显示区域100可以具有中心线O，显示区域100中的多条数据信号线60、多条数据连接线70和引线区201中的多条引出线210可以相对于中心线O对称设置，中心线O可以为平分显示区域100的多个单元列并沿着第二方向Y延伸的直线。
图5C为本公开示例性实施例一种数据连接线的排布示意图，为图5A中C1区域的放大图，示意了7条数据信号线、7条数据连接线和7条引出线的结构。图5C所示，在示例性实施方式中，显示区域100的多条数据信号线可以包括第一数据信号线60-1至第七数据信号线60-7，显示区域100的多条数据连接线可以包括第一数据连接线70-1至第七数据连接线70-7，引线区201的多条引出线可以包括第一引出线210-1至第七引出线210-7。
在示例性实施方式中，第一数据信号线60-1至第七数据信号线60-7、第一数据连接线70-1至第七数据连接线70-7以及第一引出线210-1至第七引出线210-7均可以沿着第一方向X顺序设置，第i数据连接线70-i的第一端在显示区域100通过连接孔与第i数据信号线60-i连接，第i数据连接线70-i的第二端延伸到引线区201后与第i引出线210-i连接，i＝1至7。
在示例性实施方式中，数据连接线70与数据信号线60对应连接的多个连接孔与显示区域边缘B的距离可以不同。例如，连接第一数据连接线70-1与第一数据信号线60-1的连接孔与显示区域边缘B的距离可以小于连接第二数据连接线70-2与第二数据信号线60-2的连接孔与显示区域边缘B的距离。又如，连接第二数据连接线70-2与第二数据信号线60-2的连接孔与显示区域边缘B的距离可以大于连接第三数据连接线70-3与第三数据信号线60-3的连接孔与显示区域边缘B的距离。
图6为本公开示例性实施例一种显示区域的分区示意图。如图6所示，显示区域包括：透光显示区10和常规显示区，常规显示区包括第一区域100A、第二区域100B和第三区域100C。
在示例性实施方式中，第一区域100A的至少一个电路单元与透光显示区中的发光器件连接。第二区域100C为常规显示区除了第一区域和第三区域之外的所有区域。
在示例性实施方式中，第三区域100C的至少一个电路单元包括数据连 接线。第三区域100C可以包括多个电路单元，第三区域100C的多个电路单元中像素电路在显示面板平面上的正投影与数据连接线70在显示面板平面上的正投影重叠。
在示例性实施方式中，图6中的填充区域指的是数据连接线所在的第三区域100C，位于第三区域100C的数据连接线70中的部分与数据信号线60所在的膜层不同，且位于数据信号线靠近基底的一侧，数据连接线70中另一部分与数据信号线在同一膜层。数据连接线70与数据信号线位于不同膜层的部分与数据信号线60连接，数据连接线70与数据信号线同层设置的部分沿第二方向Y延伸至绑定区域201。
在示例性实施方式中，如图5A、图5C和图6所示，数据连接线70可以包括部分沿着第一方向X延伸的第一连接线71和沿着第二方向Y延伸的第二连接线72，第一连接线71和第二连接线72构成折线状的数据连接线70。第一连接线71的第一端通过第一连接孔与数据信号线60连接，第一连接线71的第二端沿着第一方向X或者第一方向X的反方向延伸后，与第二连接线72的第一端直接连接，第二连接线72的第二端沿着第二方向Y向着引线区201的方向延伸后与引出线210连接。
在示例性实施方式中，第一连接线71和数据信号线60可以设置在不同的导电层中，第二连接线72与数据信号线60可以位于同一导电层中。
在示例性实施方式中，第一连接线包括：沿第二方向延伸的第一数据连接部和沿第一方向延伸的第二数据连接部，第一数据连接部分别与第二数据连接部和第二连接线连接，第一方向和第二方向交叉。
在示例性实施方式中，图6所示各个区域的划分仅仅是一种示例性说明。第一区域100A和第二区域100B没有数据连接线，第三区域100C是有数据连接线，第一区域100A的电路单元连接透光显示区的发光器件，第二区域100B的电路单元不连接透光显示区的发光器件作为划分依据，因而三个区域的形状可以是规则的多边形，或者是不规则的多边形，显示区域可以划分出一个或多个第一区域100A、一个或多个第二区域100B以及一个或多个第三区域100C，本公开在此不做限定。
在示例性实施方式中，在平行于显示面板的平面内，透光显示区的形状 可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形。图5A和图6是以圆形为例进行说明的。例如，透光显示区的形状为圆形时，圆形的直径可以约为3mm至5mm。又如，透光显示区的形状为矩形时，矩形的边长可以约为3mm至5mm。
在示例性实施方式中，在平行于显示面板的平面内，第一区域的形状可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形。
在示例性实施方式中，透光显示区的面积可以大于第一区域的面积，或者透光显示区的面积可以等于第一区域的面积，或者透光显示区的面积可以小于第一区域的面积，图5A和图6是以透光显示区的面积小于第二显示区的面积为例进行说明的。
在示例性实施方式中，透光显示区和第一区域的分辨率可以相同，或者可以不同。其中，分辨率(Pixels Per Inch，简称PPI)是指单位面积所拥有像素的数量，可以称为像素密度，PPI数值越高，代表显示面板以越高的密度显示画面，画面的细节丰富。
在示例性实施方式中，第一区域的分辨率可以大于透光显示区的分辨率，即在单位面积内第一区域所包括的发光器件的数量大于透光显示区所包括的发光器件的数量，或者，第一区域的分辨率可以小于透光显示区的分辨率，即在单位面积内第一区域所包括的发光器件的数量小于透光显示区所包括的发光器件的数量，或者，第一区域的分辨率可以等于透光显示区的分辨率，即在单位面积内第一区域所包括的发光器件的数量等于透光显示区所包括的发光器件的数量。
在示例性实施方式中，显示区域的形状可以为圆角多边形，或者可以为圆形。当显示区域的形状为圆角多边形时，显示区还可以包括：直线显示边界。图5A和图6是以显示区域为圆角矩形为例进行说明的。
图7A为本公开实施例提供的图6中的E0区域、E1区域和E2区域的结构示意图，图7B为本公开实施例提供的图6中的E0区域的结构示意图，图7C为本公开实施例提供的图6中的E1区域的结构示意图，图7D为本公开实施例提供的图6中的E2区域的结构示意图。E0区域位于第一区域中，E1区域位于第二区域中，E3区域位于第三区域中。位于第一区域的高压电源线 为第一高压电源线，位于第二区域的高压电源线为第二高压电源线，位于第三区域的高压电源线为第三高压电源线。
在示例性实施方式中，如图7A至图7D所示，第二高压电源线可以包括：相互连接的第一子高压电源线VLB1和第二子高压电源线VLB2，第二子高压电源线VLB2位于第一子高压电源线VLB1远离基底的一侧，第一高压电源线VLA与第二子高压电源线VLB2同层设置，第三高压电源线VLC与第一子高压电源线VLB1同层设置。
在示例性实施方式中，如图7A至图7D所示，如图7A和图7D所示，第一区域。第二区域和第三区域的数据信号线可以为同一数据信号线，且数据信号线DL与第一高压电源线同层设置。
如图7A和图7C所示，第二子高压电源线VLB2沿第一方向X的长度可以小于第一子高压电源线VLB1沿第一方向X的长度，且第二子高压电源线VLB2在基底上的正投影与第一子高压电源线VLB1在基底上的正投影至少部分交叠。
在示例性实施方式中，如图7A至图7C所示，第一高压电源线VLA沿第一方向X的长度、第一子高压电源线VLB1沿第一方向X的长度和第三高压电源线VLC沿第一方向X的长度近似相等，且第一高压电源线VLA的形状、第一子高压电源线VLB1的形状和第三高压电源线VLC的形状大致相同。第一高压电源线VLA和第三高压电源线VLC的形状与第一子高压电源线VLB1的形状大致相同可以消除显示面板熄屏时出现的金属线导致的残像，可以保证显示面板的显示效果。
在示例性实施方式中，如图7A和图7D所示，数据连接线可以包括：相互连接的第一连接线71和沿第二方向延伸的第二连接线72，第一连接线71位于第三高压电源线VLC靠近基底的一侧，第二连接线72与第一高压电源线VLA同层设置。
在示例性实施方式中，第二连接线72与第一高压电源线VLA同层设置可以实现低负载和高刷新率。
在示例性实施方式中，如图7A和图7D所示，第二子高压电源线VLB2沿第一方向X的长度可以与第二连接线72沿第一方向X的长度近似相等， 且第二子高压电源线VLB2的形状与第二连接线72的形状大致相同。
在示例性实施方式中，如图7A和图7D所示，第一连接线71在基底上的正投影与数据信号线DL在基底上的正投影至少部分交叠，第二连接线72在基底上的正投影与第三高压电源线VLC在基底上的正投影至少部分交叠。
在示例性实施方式中，如图7A所示，第二子高压电源线VLB2在基底上的正投影与第一子高压电源线VLB1在基底上的正投影的重叠区域的面积大于第二连接线72在基底上的正投影与第三高压电源线VLC在基底上的正投影的重叠区域的面积。
在示例性实施方式中，图8A为一种显示面板的第一阳极连接线的布线示意图，图8B为一种显示面板的第一阳极连接线和第二阳极连接线的连接示意图，图8C为一种显示面板的第一阳极连接线的局部布线示意图一，图8D为一种显示面板的第一阳极连接线的局部布线示意图二，图8E为图6中E0区域的另一结构示意图。如图8A至图8E所示，发光器件可以包括：阳极、有机发光层和阴极，显示面板还可以包括：沿第一方向延伸的多条第一阳极连接线AL1，第一阳极连接线AL1与第三高压电源线VLC同层设置，且被配置为连接第一区域100A的至少一个电路单元和位于透光显示区10的发光器件的阳极。
如图8B所示，第一区域100A的电路单元可以包括：多个电路单元，与透光显示区的发光器件所连接的电路单元可以位于与常规显示区的发光器件所连接的电路单元之间。
在示例性实施方式中，如图8A所示，透光显示区10包括：中心区域10A和围设在中心区域10A外侧的边缘区域10B。
在示例性实施方式中，如图8B所示，显示面板还可以包括：第二阳极连接线AL2。第二阳极连接线AL2可以位于第一高压电源线远离基底的一侧；第一阳极连接线AL1被配置为连接第一区域的至少一个电路单元和位于边缘区域的发光器件的阳极，第二阳极连接线AL2被配置为连接第一区域的至少一个电路单元和位于中心区域的发光器件的阳极。
在示例性实施方式中，第一阳极连接线可以包括：金属信号线。第一阳极连接线与第三高压电源线同层设置，可以简化显示面板的制作工艺，有利 于节约成本，提高良率和产能。
在示例性实施方式中，第二阳极连接线包括：透明导电信号线，第二阳极连接线包括：透明导电信号线可以保证透光显示区的透光率。
在示例性实施方式中，由于透光显示区的孔径大小约为2.5mm，若显示面板全部采用的第二阳极连接线的话，则需要设置至少三层透明导电层以及位于透明导电层之间的平坦层或者绝缘层，此时，显示面板所采用的掩膜版的数量较多。而本公开通过设置与第三高压电源线VLC同层设置的多条第一阳极连接线AL1，可以减缓第二阳极连接线的布线压力，可以减少显示面板制作时使用的掩膜版的数量，有利于节约成本，提高良率和产能。
在示例性实施方式中，发光结构层可以包括：多个发光单元，至少一个发光单元包括：第一发光器件、第二发光器件和第三发光器件，不同发光器件发射不同颜色的光线，第一发光器件和第二发光器件发射红色或者蓝色光线，第三发光器件发射绿色光线。
在示例性实施方式中，如图8C和图8D所示，位于透光显示区的发光单元中的第一发光器件的面积小于位于常规显示区的发光单元中的第一发光器件的面积。位于透光显示区的发光单元中的第二发光器件的面积小于位于常规显示区的发光单元中的第二发光器件的面积。位于透光显示区的发光单元中的第三发光器件的面积小于位于常规显示区的发光单元中的第三发光器件的面积。
在示例性实施方式中，如图8C和图8D所示，对于位于边缘区域的发光单元，与同一发光单元的第三发光器件连接的第一阳极连接线AL1沿第一方向的长度小于与同一发光单元的第一发光器件和第二发光器件连接的第一阳极连接线AL1沿第一方向的长度。与同一发光单元的第三发光器件连接的第一阳极连接线AL1沿第一方向的长度小于与同一发光单元的第一发光器件和第二发光器件连接的第一阳极连接线AL1沿第一方向的长度可以减少第三发光器件所在的子像素的负载，可以提升透光显示区的发光器件的显示效果。
在示例性实施方式中，如图8C和图8D所示，与位于边缘区域的任一第三发光器件连接的第一阳极连接线AL1沿第一方向X的长度小于与位于边 缘区域的任一第一发光器件连接的第一阳极连接线AL1和位于边缘区域的任一第二发光器件连接的第一阳极连接线AL1沿第一方向X的长度。与位于边缘区域的任一第三发光器件连接的第一阳极连接线沿第一方向X的长度较小可以提升透光显示区的发光器件的显示效果。
在示例性实施方式中，边缘区域10B占透光显示区10的面积约为3％至8％，或者边缘区域10B包括的发光单元的数量为透光显示区中发光单元数量的5％至10％。边缘区域10B占透光显示区10的面积约为3％至8％，或者边缘区域10B包括的发光单元的数量为透光显示区中发光单元数量的5％至10％可以保证透光显示区的透光率。
在示例性实施方式中，在垂直于基底的平面上，显示面板可以包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层、第一平坦层、第五导电层；
半导体层至少包括多个晶体管的有源层；第一导电层至少包括多个晶体管的栅电极和电容的第一极板，第二导电层至少包括电容的第二极板，第三导电层至少包括多个晶体管的第一极和第二极以及第一连接线，第四导电层至少包括第一阳极连接线、第一子高压电源线和第三高压电源线，第五导电层至少包括：数据信号线、第一高压电源线、第二子高压电源线和第二连接线。
在示例性实施方式中，像素电路包括：写入晶体管，写入晶体管与数据信号线连接，位于第三区域的电容的第二极板包括：相互连接的电容主体部和辅助电容部，电容主体部与位于第一区域和第二区域的电容的第二极板的形状大致相同；辅助电容部在基底上的正投影与写入晶体管的有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第三导电层还包括：数据连接块，数据连接块在基底上的正投影与辅助电容部和第二连接线在基底上的正投影至少部分交叠，数据连接块分别与第一连接线和第二连接线连接。
在示例性实施方式中，数据连接块和第二数据连接部位于第一数据连接部的同一侧，且与第一数据连接部电连接；
第一数据连接部在基底上的正投影与电容的第二极板在基底上的正投影至少部分交叠。
在示例性实施方式中，像素电路还包括：第一发光晶体管和第二发光晶体管，第一发光晶体管与高压电源线连接，第二发光晶体管与发光器件的阳极连接，第四导电层还包括：第一连接电极、第二连接电极、第三连接电极和第四连接电极；
第一连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极电连接，第二连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极，第三连接电极在基底上的正投影与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极连接，第四连接电极在基底上的正投影与数据连接块在基底上的正投影至少部分交叠，且与数据连接块在基底上的正投影至少部分交叠。
在示例性实施方式中，第五导电层还包括：第五连接电极，第五连接电极在基底上的正投影与第二连接电极在基底上的正投影至少部分交叠，且与第二连接电极连接。
在示例性实施方式中，多条第一阳极连接线在基底上的正投影可以与电容的第二极板和所连接的发光器件的阳极在基底上的正投影至少部分交叠。
在示例性实施方式中，数据信号线在基底上的正投影与第一连接电极在基底上的正投影至少部分交叠，且与第一连接电极连接，第一高压电源线在基底上的正投影与第三连接电极在基底上的正投影至少部分交叠，且与第三连接电极连接。第二连接线在基底上的正投影与第四连接电极在基底上的正投影至少部分交叠，且与第四连接电极连接。
在示例性实施方式中，显示面板还可以包括位于第二平坦层远离基底一侧的透明导电层，透明导电层包括第二阳极连接线，第二阳极连接线与第五 连接电极在基底上的正投影至少部分交叠，且与第五连接电极连接。
下面通过显示面板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示面板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以E0区域、E1区域和E2区域中的6个电路单元(2个单元行3个单元列)，其中，第N列和第N+1列电路单元中的电路单元为驱动电路单元，第N+2列电路单元为虚拟电路单元为例，显示面板的制备过程可以包括如下步骤。
(1)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图9所示，图9为E0区域、E1区域和E2区域形成半导体图案后的示意图。
在示例性实施方式中，如图9所示，位于E0区域、E1区域和E2区域的半导体层图案均包括：第一晶体管的有源层T11至第七晶体管的有源层T71。
在示例性实施方式中，如图9所示，第一晶体管的有源层T11至第六晶体管的有源层T61为相互连接的一体结构。
在示例性实施方式中，如图9所示，在第一方向X上，第二晶体管的有源层T21和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的同一侧，第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第三晶体管的有源层T31的同一侧，第二晶体管的有源层T21和第四晶体管的有源层T41可以位于本子像素的第三晶体管的有源层T31的不同侧。在第二方向Y上，第一晶体管的有源层T11、第二晶体管的有源层T21、第四晶体管的有源层T41和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31的同一层，第五晶体管的有源层T51和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的另一侧。
在示例性实施方式中，如图9所示，第一晶体管的有源层T11的形状可以呈“n”字形，第二晶体管的有源层T21的形状可以呈“L”字形，第三晶体管的有源层T31的形状可以呈“Ω”字形，第四晶体管的有源层T41、第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71的形状可以呈“I”字形。
在示例性实施方式中，如图9所示，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层T11的第二区T11_2可以作为第二晶体管的有源层T21的第一区T21_1，第三晶体管的有源层T31的第一区T31_1可以同时作为第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2，第三晶体管的有源层T31的第二区T31_2可以同时作为第二晶体管的有源层T21的第二区T21_2和第六晶体管的有源层T61的第一区T61_1，第六晶体管的有源层T61的第二区T61_2可以作为第七晶体管的有源层T71的第二区T71_2，第一晶体管的有源层T11的第一区T11_1、第四晶体管的有源层T41的第一区T41_1、第五晶体管的有源层T51_1的第一区T51_1和第七晶体管的有源层T71的第一区T71_1可以单独设置。
在示例性实施方式中，如图9所示，第三晶体管的有源层T31的第一区T31_1(也是第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2)的形状可以为沿第二方向Y延伸的条状结构，且沿 第一方向X的长度大于第四晶体管的有源层T41的第一区T41_1和第五晶体管的有源层T51的第一区T51_1的长度。
在示例性实施方式中，图9中E1区域和E2区域的半导体图案与E0区域的半导体图案基本上相同。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及位于第一绝缘层上的第一导电层图案，如图10和图11所示，其中，图10为E0区域、E1区域和E2区域的第一导电层图案的示意图，图11为E0区域、E1区域和E2区域形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图10和图11所示，E0区域、E1区域和E2区域的第一导电层图案均可以包括：扫描信号线GL、复位信号线RL、发光信号线EL以及电容的第一极板C1。
在示例性实施方式中，如图10和图11所示，电容的第一极板C1的形状可以为矩形状，且矩形状的角部可以设置倒角，电容的第一极板C1在基底上的正投影与第三晶体管T3的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，电容的第一极板C1可以同时作为第三晶体管的控制极T32。
在示例性实施方式中，如图10和图11所示，复位信号线RL的形状可以为沿着第一方向X延伸的线形状，复位信号线RL可以位于电容的第一极板C1远离发光信号线EL的一侧。复位信号线RL与第一晶体管的有源层相重叠的区域作为第一晶体管的控制极T12，复位信号线RL与第七晶体管的有源层相重叠的区域作为第七晶体管的控制极T72。由于第一晶体管的有源层T11的形状可以呈“n”字形，因此，复位信号线RL与第一晶体管的有源层相重叠的区域有两个，也就是说，第一晶体管的控制极T12有两个，即第一晶体管为双栅结构。
在示例性实施方式中，如图10和图11所示，扫描信号线GL的形状可以为沿着第一方向X延伸的线形状，扫描信号线GL可以位于电容的第一极 板C1与复位信号线RL之间。扫描信号线GL与第二晶体管的有源层相重叠的区域作为第二晶体管的控制极T22，扫描信号线GL与第四晶体管的有源层相重叠的区域作为第四晶体管的控制极T42。第二晶体管的控制极T22与第二晶体管的有源层T21相重叠的区域有两个，也就是说，第二晶体管的控制极T22有两个，第二晶体管为双栅结构。
在示例性实施方式中，如图10和图11所示，发光信号线EL的形状可以为沿着第一方向X延伸的线形状，发光信号线EL与第五晶体管的有源层相重叠的区域作为第五晶体管的控制极T52，发光信号线EL与第六晶体管的有源层相重叠的区域作为第六晶体管的控制极T62。
在示例性实施方式中，如图10和图11所示，扫描信号线GL、复位信号线RL和发光信号线EL可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图11所示，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管的有源层至第七晶体管的有源层的第一区和第二区均被导体化，且导体化后的第三晶体管的有源层的第一区(也是第四晶体管的有源层的第二区和第五晶体管的有源层的第二区)可以同时作为第三晶体管的第一极T33、第四晶体管的第二极T44和第五晶体管的第二极T54，导体化后的第三晶体管的有源层的第二区(也是第二晶体管的有源层的第二区和第六晶体管的有源层的第一区T61_1)也是同时作为第二晶体管的第二极T24、第三晶体管的第二极T34和第六晶体管的第一极T63。
在示例性实施方式中，图10中E1区域和E2区域的第一导电层图案与E0区域的第一导电层图案基本上相同。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成第二导电 层图案。图12至图15所示，图12为E0区域和E1区域的第一导电层图案的示意图，图13为E0区域和E1区域形成第一导电层图案后的示意图，图14为E2区域的第一导电层图案的示意图，图15为E2区域形成第一导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图12至图15所示，E0区域、E1区域和E2区域的第二导电层图案均可以包括：第一初始信号线INIL1、第二初始信号线INIL2和电容的第二极板C2。
在示例性实施方式中，如图12至图15所示，第一初始信号线INIL1和第二初始信号线INIL2的形状可以为主体部分可以沿第一方向X延伸的线形状。第M行电路单元中的第一初始信号线INIL1可以位于本电路单元的复位信号线RL和扫描信号线GL之间，第二初始信号线INIL2可以位于本电路单元的复位信号线RL远离扫描信号线GL的一侧。
在示例性实施方式中，如图12至图15所示，第二极板C2的轮廓形状可以为矩形状，矩形状的角部可以设置倒角，第二极板C2在基底上的正投影与第一极板C1在基底上的正投影存在重叠区域，第二极板C2作为电容的另一个极板，位于本电路单元的扫描信号线GL和发光信号线EL之间，第一极板C1和第二极板C2构成像素电路的电容。
在示例性实施方式中，相邻电路单元的第二极板C2相互连接。相邻电路单元的第二极板C2相互连接可以使一单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号连接线，保证一单元行中的多个第二极板具有相同的电位，有利于提高显示面板的均一性，避免显示面板的显示不良，保证显示面板的显示效果。
在示例性实施方式中，第二极板C2上设置有开口V，开口V可以位于第二极板C2的中部。开口V可以为矩形，使第二极板C2形成环形结构。开口V暴露出覆盖第一极板C1的第二绝缘层，且第一极板C1在基底上的正投影包含开口V在基底上的正投影。在示例性实施方式中，开口V被配置为容置后续形成的第七过孔，第七过孔位于开口V内并暴露出第一极板C1，使后续形成的第一晶体管T1的第二极与第一极板C1连接。
在示例性实施方式中，如图12和图13所示，E1区域的第二导电层图案与E0区域的第二导电层图案基本上相同。
在示例性实施方式中，E2区域的第二导电层图案中的第二极板与E0区域的第二导电层图案中的第二极板有不同之处。如图14和图15所示，E2区域的第二导电层图案中的第二极板可以包括：一体成型的电容主体部C_main和辅助电容部C0。
在示例性实施方式中，如图14和图15所示，电容主体部C_main的形状与E0区域和E1区域的第二导电层图案中的第二极板C2的形状相同。辅助电容部C0在基底上的正投影与第四晶体管的有源层在基底上的正投影至少部分交叠。
在示例性实施例方式中，辅助电容部可以起到垫平数据连接块，可以提升显示面板的显示效果。
在示例性实施方式中，如图12至图15所示，第一初始信号线INIL1和第二初始信号线INIL2可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图16和图17所示，其中，图16为E0区域和E1区域形成第三绝缘层图案后的示意图，图17为E2区域形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图16和图17所示，E0区域、E1区域和E2区域的第三绝缘层中的多个过孔可以均包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9和第十过孔V10。
在示例性实施方式中，如图16和图17所示，第一过孔V1在基底上的正投影位于第一晶体管T1的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管T1 的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一晶体管T1的有源层的第一区连接。
在示例性实施方式中，如图16和图17所示，第二过孔V2在基底上的正投影位于第一晶体管T1的有源层的第二区(也是第二晶体管T2的有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管T1的有源层的第二区(也是第二晶体管T2的有源层的第一区)的表面，第二过孔V2被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一晶体管T1的有源层的第一区(也是第二晶体管T2的有源层的第一区)连接。
在示例性实施方式中，如图16和图17所示，第三过孔V3在基底上的正投影位于第四晶体管T4的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管T4的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管T4的有源层的第一区连接。
在示例性实施方式中，如图16和图17所示，第四过孔V4在基底上的正投影位于第五晶体管T5的有源层的第一区在基底上的正投影的范围之内，第四过孔V4内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五晶体管T5的有源层的第一区的表面，第四过孔V4被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五晶体管T5的有源层的第一区连接。
在示例性实施方式中，如图16和图17所示，第五过孔V5在基底上的正投影位于第六晶体管T6的有源层的第二区(也是第七晶体管T7的有源层的第二区)在基底上的正投影的范围之内，第五过孔V5内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六晶体管T6的有源层的第二区(也是第七晶体T7的有源层的第二区)的表面，第五过孔V5被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六晶体管T6的有源层的第二区(也是第七晶体管T7的有源层的第二区)连接。
在示例性实施方式中，如图16和图17所示，第六过孔V6在基底上的正投影位于第七晶体管T7的有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七晶体管T7 的有源层的第一区的表面，第六过孔V6被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七晶体管T7的有源层的第一区连接。
在示例性实施方式中，如图16和图17所示，第七过孔V7在基底上的正投影位于开口在基底上的正投影的范围之内，第七过孔V7内的第二绝缘层被刻蚀掉，暴露出第一电容的第一极板(也是第三晶体管的控制极)的表面，第七过孔V7被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一电容的第一极板(也是第三晶体管T3的控制极)连接。
在示例性实施方式中，如图16和图17所示，第八过孔V8在基底上的正投影位于第一初始信号线INIL1在基底上的正投影的范围之内，第八过孔V8暴露出第一初始信号线INIL1的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线INIL1连接。
在示例性实施方式中，如图16和图17所示，第九过孔V9在基底上的正投影位于第二初始信号线INIL2在基底上的正投影的范围之内，第九过孔V9暴露出第二初始信号线INIL2的表面，第九过孔V9被配置为使后续形成的第七晶体管的第一极通过该过孔与第二初始信号线INIL2连接。
在示例性实施方式中，如图16和图17所示，第十过孔V10在基底上的正投影位于电容的第二极板在基底上的正投影的范围之内，第十过孔V10暴露出电容的第二极板的表面，第十过孔V10被配置为使后续形成的第五晶体管T5的第一极通过该过孔与电容的第二极板连接。在示例性实施方式中，第十过孔V10可以是多个，多个第十过孔V10可以沿着第二方向Y依次设置，以提高连接可靠性。
在示例性实施方式中，如图16和图17所示，E1区域和E2区域的第三绝缘层的过孔图案与E0区域的第三绝缘层的过孔图案基本上相同。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，图18至图21所示，图18为E0区域和E1区域的第三导电层图案的示意图，图19为E0区域和E1区域形成第三导电层图案后的示意图，图20为E2区域的第三 导电层图案的示意图，图21为E2区域形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图18至图21所示，E0区域、E1区域和E2区域的第三导电层图案可以均包括：第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74。其中，
在示例性实施方式中，如图18至图21所示，第一晶体管的第二极T14可以同时作为第二晶体管的第一极T23、第六晶体管的第二极T64可以同时作为第七晶体管的第二极T74，第一晶体管的第一极T13、第四晶体管的第一极T43、第五晶体管的第一极T53和第七晶体管的第一极T73可以单独设置。
在示例性实施方式中，如图20和图21所示，E2区域的第三导电层图案还可以包括：数据连接块73和第一连接线71。
在示例性实施方式中，如图20和图21所示，数据连接块73在基底上的正投影与辅助电容部在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20和图21所示，第一连接线71与数据连接块73连接，且为一体成型结构。
在示例性实施方式中，如图20和图21所示，第一连接线71可以包括：第一数据连接部71A和第二数据连接部71B。其中，第一数据连接部71A分别与数据连接块73和第二数据连接部71B连接，数据连接块73和第二数据连接部71B位于第一数据连接部71A的同一侧。第一数据连接部71A在基底上的正投影与电容的第二极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20和图21所示，第一数据连接部71A的主体部分可以为第二方向Y延伸的线形状，第二数据连接部71B的主体部分可以为沿第一方向X延伸的线形状。
在示例性实施方式中，如图18至图21所示，第一晶体管的第一极T13的形状可以为主体部分沿第一方向X延伸的线形状，第一晶体管的第一极 T13可以位于扫描信号线GL和复位信号线RL之间。第一晶体管的第一极T13在基底上的正投影可以与第一过孔和第一初始信号线INIL1在基底上的正投影部分交叠。第一晶体管的第一极T13通过第一过孔与第一晶体管的有源层的第一区连接，且通过第八过孔与第一初始信号线INIL1连接。
在示例性实施方式中，如图18至图21所示，第一晶体管的第二极T14(也是第二晶体管的第一极T23)的形状可以为沿第二方向Y延伸的线型状，第一晶体管的第二极T14(也是第二晶体管的第一极T13)可以位于第一初始信号线INIL1远离复位信号线RL的一侧。第一晶体管的第二极T14(也是第二晶体管的第一极T13)在基底上的正投影可以与第二过孔、第七过孔、第一电容的第一极板和第二极板在基底上的正投影至少部分交叠。第一晶体管的第二极T14(也是第二晶体管的第一极T23)通过第二过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)连接，且通过第七过孔与第一电容的第一极板连接。
在示例性实施方式中，如图18至图21所示，第四晶体管的第一极T43的形状可以为块状结构，第四晶体管的第一极T43可以位于第一初始信号线INIL1和扫描信号线GL之间。第四晶体管的第一极T43在基底上的正投影与第三过孔至少部分交叠。第四晶体管的第一极通过第三过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图18至图21所示，第六晶体管的第二极T64(第七晶体管的第二极T74)和第五晶体管的第一极T53分别位于第一晶体管的第二极T14(也是第二晶体管的第一极T23)的两侧。
在示例性实施方式中，如图18至图21所示，第五晶体管的第一极T53的形状可以为沿第二方向Y延伸的线型状，第M行电路单元的第五晶体管的第一极T53可以位于第M行电路单元的扫描信号线GL和第M+1行电路单元的第二初始信号线INIL2之间。第五晶体管的第一极T53在基底上的正投影可以与第四过孔、第十过孔、发光信号线和电容的第二极板在基底上的正投影至少部分交叠。第五晶体管的第一极T53通过第四过孔与第五晶体管的有源层的第一区连接，且通过第十过孔与电容的第二极板在基底上的正投影连接。
在示例性实施方式中，如图18至图21所示，第六晶体管的第二极T64(第七晶体管的第二极T74)可以为块状结构。第M行电路单元的第六晶体管的第二极T64(第七晶体管的第二极T74)可以位于第M行电路单元的扫描信号线GL和第M+1行电路单元的第二初始信号线INIL2之间。第六晶体管的第二极T64(第七晶体管的第二极T74)在基底上的正投影可以与第五过孔在基底上的正投影至少部分交叠。第六晶体管的第二极T64(第七晶体管的第二极T74)通过第五过孔与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，如图18至图21所示，虚拟像素电路的第六晶体管的第二极T64(第七晶体管的第二极T74)在基底上的正投影与发光信号线在基底上的正投影不交叠。像素电路的第六晶体管的第二极T64(第七晶体管的第二极T74)在基底上的正投影与发光信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，如图18至图21所示，第七晶体管的第一极T73可以为沿第二方向Y延伸的线型状。第七晶体管的第一极T73位于第一初始信号线INIL1远离扫描信号线GL的一侧。第七晶体管的第一极T73在基底上的正投影与第六过孔、第九过孔、复位信号线RL和第二初始信号线INIL2在基底上的正投影至少部分交叠。第七晶体管的第一极通过第六过孔与第七晶体管的有源层的第一区连接，且通过第九过孔与第二初始信号线连接。
在示例性实施方式中，如图18和图19所示，E1区域的第三导电层图案与E0区域的第三导电层图案基本上相同。
(6)形成第四绝缘层。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图22和图23所示，其中，图22为E0区域和E1区域形成第四绝缘层图案后的示意图，图23为E2区域形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图22和图23所示，E0区域、E1区域和E2区域的第四绝缘层图案的多个过孔可以均包括：第十一过孔V11、第十二过孔 V12和第十三过孔V13。
在示例性实施方式中，如图23所示，E2区域的第四绝缘层图案的多个过孔还可以包括：第十四过孔V14。
在示例性实施方式中，如图22和图23所示，第十一过孔V11在基底上的正投影位于E0区域和E1区域中的驱动电路单元以及E2区域中的驱动电路单元和虚拟电路单元中的第四晶体管的第一极在基底上的正投影的范围之内，第十一过孔V11暴露出E0区域和E1区域中的驱动电路单元以及E2区域中的驱动电路单元和虚拟电路单元中的第四晶体管的第一极，第十一过孔V11被配置为使后续形成的第一连接电极通过该过孔与E0区域和E1区域中的驱动电路单元以及E2区域中的驱动电路单元和虚拟电路单元中的第四晶体管的第一极连接。
在示例性实施方式中，如图22和图23所示，第十二过孔V12在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第十二过孔V12暴露出第五晶体管的第一极。E0区域的第十二过孔V12被配置为使后续形成的第三连接电极通过该过孔与第五晶体管的第一极连接。E1区域的第十二过孔V12被配置为使后续形成的第一子高压电源线通过该过孔与第五晶体管的第一极连接。位于E2区域的第十二过孔V12被配置为使后续形成的第三高压电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图22和图23所示，第十三过孔V13在基底上的正投影与位于E0区域、E1区域和E2区域的驱动电路单元中的第六晶体管的第二极(第七晶体管的第二极)在基底上的正投影的范围之内，第十三过孔V13暴露出E0区域、E1区域和E2区域的驱动电路单元中的第六晶体管的第二极(第七晶体管的第二极T74)。第十三过孔V13被配置为使后续形成的第二连接电极通过该过孔与E0区域、E1区域和E2区域的驱动电路单元中的第六晶体管的第二极(第七晶体管的第二极)连接，
在示例性实施方式中，如图23所示，第十四过孔V14在基底上的正投影位于数据连接块在基底上的正投影的范围之内，第十四过孔V14暴露出数据连接块，第十四过孔V14被配置为使后续形成的第四连接电极通过该过孔与数据连接块连接。
在示例性实施方式中，如图22所示，E1区域的第四绝缘层图案与E0区域的第四绝缘层图案基本上相同。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层，如图24A、图24B、图25A、图25B以及图26至图29所示，图24A为E0区域的第四导电层图案的示意图一，图24B为E0区域形成第四导电层图案后的示意图一，图25A为E0区域的第四导电层图案的示意图二，图25B为E0区域形成第四导电层图案后的示意图二，图26为E1区域的第四导电层图案的示意图，图27为E1区域形成第四导电层图案后的示意图，图28为E2区域的第四导电层图案的示意图，图29为E2区域形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为中间源漏金属(SDM)层。图24A和图24B是以第四导电层不包括第一阳极连接线为例进行说明的，图25A和图25B是以第四导电层包括第一阳极连接线为例进行说明的。
在示例性实施方式中，如图24A至图29所示，E0区域、E1区域和E2区域的第四导电层图案可以均包括：第一连接电极VL1和第二连接电极VL2。
在示例性实施方式中，如图24A和图24B所示，E0区域的第四导电层图案还可以包括：第三连接电极VL3。
在示例性实施方式中，如图25A和图25B所示，E0区域的第四导电层图案还可以包括：第三连接电极VL3和多条第一阳极连接线AL1。
在示例性实施方式中，如图26和图27所示，E1区域的第四导电层图案还可以包括：第二高压电源线中的第一子高压电源线VLB1。
在示例性实施方式中，如图28和图29所示，E2区域的第四导电层图案还可以包括：第三高压电源线VLC和第四连接电极VL4。
在示例性实施方式中，如图24A至图29所示，第一连接电极VL1的形状可以为块状结构。第一连接电极VL1在基底上的正投影可以与第十一过孔在基底上的正投影部分交叠。第一连接电极VL1通过第十一过孔与E0区域和E1区域中的驱动电路单元以及E2区域中的驱动电路单元和虚拟电路单元中的第四晶体管的第一极连接。
在示例性实施方式中，第一连接电极起到了承接数据信号线和第四晶体管的第一极的作用，由于避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
在示例性实施方式中，如图24A至图29所示，第二连接电极VL2的形状可以为块状结构。第二连接电极VL2在基底上的正投影可以与第十三过孔在基底上的正投影部分交叠。第二连接电极VL2通过第十三过孔与E0区域、E1区域和E2区域的驱动电路单元中的第六晶体管的第二极(第七晶体管的第二极)连接。
在示例性实施方式中，第二连接电极起到了承接第五连接电极和第六晶体管的第二极(第七晶体管的第二极)的作用，由于避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
在示例性实施方式中，如图24A、图24B、图25A和图25B所示，第三连接电极VL3的形状可以为块状结构。第三连接电极VL3在基底上的正投影可以与第十二过孔在基底上的正投影部分交叠。第三连接电极VL3通过第十二过孔与第五晶体管的第一极连接。
在示例性实施方式中，第三连接电极起到了承接第一高压电源线和第五晶体管的第一极的作用，由于避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
在示例性实施方式中，如图25A和图25B所示，第一阳极连接线AL1的形状可以为沿第一方向X延伸的线形状。多条第一阳极连接线AL1在基底上的正投影可以与E0区域中的第七晶体管的第一极和电容的第二极板在基底上的正投影交叠。第一阳极连接线AL1被配置为与后续形成的发光器件的阳极连接。
在示例性实施方式中，如图26和图27所示，第一子高压电源线VLB1的形状可以为主体部分沿着第二方向Y延伸的折线状，第一子高压电源线VLB1被配置为第五晶体管的第一极提供高电源电压信号。第一子高压电源线VLB1在基底上的正投影分别与第十二过孔和第一晶体管的第二极(也是第二晶体管的第一极)在基底上的正投影部分交叠。第一子高压电源线VLB1通过第十二过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图28和图29所示，第三高压电源线VLC的形状可以为主体部分沿着第二方向Y延伸的折线状，第三高压电源线VLC被配置为向E2区域的第五晶体管的第一极提供高电源电压信号。第三高压电源线VLC在基底上的正投影分别与第十二过孔和第一晶体管的第二极(也是第二晶体管的第一极)在基底上的正投影部分交叠。第三高压电源线VLC通过第十二过孔与第五晶体管的第一极连接。
在示例性实施方式中，第三高压电源线VLC的图案与第一子高压电源线VLB1的图案大致相同，且相互连接。第三高压电源线VLC与第一子高压电源线VLB1为一体成型结构。
在示例性实施方式中，第三高压电源线沿第一方向X的长度可以约等于与第一子高压电源线VLB1沿第一方向X的长度。
在示例性实施方式中，如图28和图29所示，第四连接电极VL4的形状可以为块状结构。第四连接电极VL4在基底上的正投影可以与数据连接块在基底上的正投影至少部分交叠。第四连接电极VL4通过第十四过孔与数据连接块连接。
在示例性实施方式中，第四连接电极起到了承接数据连接块和第二连接线的作用，由于避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第四导电层的第一平坦层，第一平坦层上设置有多个过孔，如图30至图32所示，其中，图30为E0区域形成第一平坦层图案后的示意图，图31为E1区域形成第一平坦层图案后的示意图，图32为E2区域形成第一平坦层图案后的示意图。
在示例性实施方式中，如图30至图32所示，E0区域、E1区域和E2区域的第一平坦层图案的多个过孔可以均包括：第十五过孔V15和第十六过孔V16。
在示例性实施方式中，如图30所示，E0区域的第一平坦层图案的多个过孔还可以包括：第十七过孔V17。
在示例性实施方式中，如图31所示，E1区域的第一平坦层图案的多个过孔还可以包括：第十八过孔V18。
在示例性实施方式中，如图32所示，E2区域的第一平坦层图案的多个过孔还可以包括：第十九过孔V19。
在示例性实施方式中，如图30至图32所示，第十五过孔V15在基底上的正投影位于第一连接电极在基底上的正投影的范围之内，第十五过孔V15暴露出第一连接电极，第十五过孔V15被配置为使后续形成的数据信号线通过该过孔与第一连接电极连接。
在示例性实施方式中，如图30至图32所示，第十六过孔V16在基底上的正投影位于第二连接电极在基底上的正投影的范围之内，第十六过孔V16暴露出第二连接电极，第十六过孔V16被配置为使后续形成的第五连接电极通过该过孔与第二连接电极连接。
在示例性实施方式中，如图30所示，第十七过孔V17在基底上的正投影位于第三连接电极在基底上的正投影的范围之内，第十七过孔V17暴露出第三连接电极。第十七过孔V17被配置为使后续形成的第一高压电源线通过该过孔与第三连接电极连接。
在示例性实施方式中，如图31所示，第十八过孔V18在基底上的正投影位于第二高压电源线的第一子高压电源线在基底上的正投影的范围之内，第十八过孔V18暴露出第一子高压电源线。第十八过孔V18被配置为使后续形成的第二高压电源线的第二子高压电源线通过该过孔与第二高压电源线的第一子高压电源线连接。
在示例性实施方式中，如图32所示，第十九过孔V19在基底上的正投影位于第四连接电极在基底上的正投影的范围之内，第十九过孔V19暴露出第四连接电极。第十九过孔V19被配置为使后续形成的第二连接线通过该过孔与第四连接电极连接。
(9)形成第五导电层图案。在示例性实施方式中，形成第五导电层图案可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第一平坦层上的第五导电层，图33为E0区域的第五导电层图案的示意图，图34为E0区域形成第五导电层图 案后的示意图，图35为E1区域的第五导电层图案的示意图，图36为E1区域形成第五导电层图案后的示意图，图37为E2区域的第五导电层图案的示意图，图38为E2区域形成第五导电层图案后的示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图33至图38所示，E0区域、E1区域和E2区域的第五导电层图案可以均包括：数据信号线DL和第五连接电极VL5。
在示例性实施方式中，如图33和图34所示，E0区域的第五导电层图案还可以包括：第一高压电源线VLA。
在示例性实施方式中，如图35和图36所示，E1区域的第五导电层图案还可以包括：第二子高压电源线VLB2。
在示例性实施方式中，如图37和图38所示，E2区域的第五导电层图案还可以包括：第二连接线72。
在示例性实施方式中，如图33至图38所示，位于E0区域至E2区域中，且与同一列的驱动电路单元连接的数据信号线DL相互连接，且为同一数据信号线。位于E2区域中，且同一列的虚拟驱动电路单元连接的数据信号线DL相互连接，且为同一数据信号线。位于E0区域和E1区域中，且与相邻电路单元连接的数据信号线DL间隔设置。
在示例性实施方式中，如图33至图38所示，数据信号线DL的形状可以为沿第二方向Y延伸的线形状。数据信号线DL在基底上的正投影与第十五过孔在基底上的正投影至少部分交叠。数据信号线DL通过第十五过孔与第一连接电极连接。
在示例性实施方式中，如图33至图38所示，第五连接电极VL5的形状可以为块状结构。第五连接电极VL5在基底上的正投影与第十六过孔在基底上的正投影部分交叠。第五连接电极VL5通过第十六过孔与第二连接电极连接。
在示例性实施方式中，第五连接电极起到了承接发光器件的阳极和第二连接线的作用，由于避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
在示例性实施方式中，如图33和图34所示，第一高压电源线VLA的形状可以为主体部分沿着第二方向Y延伸的折线状，第一高压电源线VLA被配置为向E0区域的第五晶体管的第一极提供高电源电压信号。第一高压电源线VLA位于数据线DL和第五连接电极VL5之间。第一高压电源线VLA在基底上的正投影分别与第十七过孔和第一晶体管的第二极(也是第二晶体管的第一极)在基底上的正投影部分交叠。第一高压电源线VLA通过第十七过孔与第三连接电极连接。
在示例性实施方式中，如图33和图34所示，数据信号线DL沿第一方向的长度小于第一高压电源线VLA沿第一方向的长度。
在示例性实施方式中，第一高压电源线VLA可以分别与第三高压电源线和第一子高压电源线的图案大致相同。
在示例性实施方式中，第一高压电源线VLA沿第一方向的长度可以与第三高压电源线和第一子高压电源线沿第一方向的长度大致相同。
在示例性实施方式中，如图35和图36所示，第二子高压电源线VLB2的形状可以为主体部分沿着第二方向Y延伸的折线状，第二子高压电源线VLB2被配置为向E1区域的第五晶体管的第一极提供高电源电压信号。第二子高压电源线VLB2位于数据线DL和第五连接电极VL5之间。第二子高压电源线VLB2在基底上的正投影分别与第十八过孔在基底上的正投影部分交叠。第二子高压电源线VLB2通过第十八过孔与第一子高压电源线VLB2连接。
在示例性实施方式中，第二子高压电源线VLB2与第一高压电源线连接。
在示例性实施方式中，如图35和图36所示，数据信号线DL沿第一方向的长度与第二子高压电源线VLB2沿第一方向的长度大致相同。
在示例性实施方式中，如图37和图38所示，第二连接线72的形状可以为主体部分沿着第二方向Y延伸的线形状。第二连接线72位于数据信号线DL和第五连接电极VL5之间。第二连接线72在基底上的正投影分别与第十九过孔和第一连接线在基底上的正投影部分交叠。第二连接线72通过第十九过孔与第四连接电极连接。
在示例性实施方式中，如图37和图38所示，第二连接线72的图案可以与第二子高压电源线的图案大致相同。
在示例性实施方式中，如图37和图38所示，第二连接线72与第三高压电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，如图37和图38所示，数据信号线DL沿第一方向的长度可以与第二连接线72沿第一方向的长度大致相同。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层的第二平坦层，第二平坦层上设置有多个过孔，如图39至图41所示，其中，图39为E0区域形成第二平坦层图案后的示意图，图40为E1区域形成第二平坦层图案后的示意图，图41为E2区域形成第二平坦层图案后的示意图。
在示例性实施方式中，如图39至图41所示，E0区域、E1区域和E2区域的第二平坦层图案的多个过孔可以均包括：第二十过孔V20。
在示例性实施方式中，如图39至图41所示，第二十过孔V20在基底上的正投影位于第五连接电极在基底上的正投影的范围之内，第二十过孔V20暴露出第五连接电极。第二十过孔V20被配置为使后续形成的发光器件的阳极通过该过孔与第五连接电极连接。为了适应与后续形成的阳极的连接，多个电路单元中第二十过孔V20的位置可以不同。
在示例性实施方式中，E0区域、E1区域和E2区域的第二平坦层图案的过孔图案基本上相同。
(11)形成第三平坦层图案。在示例性实施方式中，形成第三平坦层图案可以包括：在形成前述图案的基底上，涂覆透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成覆盖第二平坦层后的透明导电层，在形成透明导电层图案的基底上，涂覆第三平坦薄膜，采用图案化工艺对第三平坦薄膜进行图案化，形成覆盖透明导电层后的第三平坦层，第三平坦层上设置有暴露出第五连接电极的过孔。透明导电层可以包括：第二阳极连接线。
至此，在基底上制备完成驱动电路层。在平行于显示面板的平面上，驱 动电路层可以包括多个电路单元，每个电路单元可以包括像素电路，以及与像素电路连接的扫描信号线、复位信号线、发光信号线、数据信号线、高压电源线、低压电源线、第一初始信号线和第二初始信号线。在垂直于显示面板的平面上，驱动电路层可以包括在基底上依次叠设的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层第一平坦层、第五导电层、第二平坦层、透明导电层和第三平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施例中，透明导电层可以采用如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI)层，第四绝缘层可以称为层间绝缘(ILD)层，第五绝缘层可以称为钝化(PVX) 层。第一平坦层、第二平坦层和第三平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极导电层图案，如图42至图45所示，图42为阳极导电层图案的示意图，图43为E0区域形成阳极导电层图案后的示意图，图44为E1区域形成阳极导电层图案后的示意图，图45为E2区域形成阳极导电层图案后的示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，阳极导电层图案可以包括红色发光器件的第一阳极301R、蓝色发光器件的第二阳极301B、第一绿色发光器件的第三阳极301G1和第二绿色发光器件的第四阳极301G2，第一阳极301R所在区域可以形成出射红色光线的红色子像素R，第二阳极301B所在区域可以形成出射蓝色光线的蓝色子像素B，第三阳极301G1所在区域可以形成出射绿色光线的第一绿色子像素G1，第四阳极301G2所在区域可以形成出射绿色光线的第二绿色子像素G2。
在示例性实施方式中，第一阳极301A和第二阳极301B可以沿着第二方向Y依次设置，第三阳极301C和第四阳极301D可以沿着第二方向Y依次设置，第三阳极301C和第四阳极301D可以设置在第一阳极301A和第二阳极301B第一方向X的一侧。或者，第一阳极301A和第二阳极301B可以沿着第一方向X依次设置，第三阳极301C和第四阳极301D可以沿着第一方向X依次设置，第三阳极301C和第四阳极301D可以设置在第一阳极301A和第二阳极301B第二方向Y的一侧。
在示例性实施方式中，第一阳极301R、第二阳极301B、第三阳极301G1和第四阳极301G2可以分别通过第二十过孔V20与对应电路单元中的第五连接电极连接。由于每个的阳极通过一个电路单元中的第五连接电极、第二连接电极与第六晶体管的第二极(也是第七有源层的第二极)连接，因而一个发光单元中的四个阳极分别与四个电路单元的像素电路对应连接，实现了像素电路可以驱动发光器件发光。
在示例性实施方式中，一个发光单元中四个子像素的阳极形状和面积可以相同，或者可以不同，一个发光单元的四个子像素与一个电路单元组中的四个电路单元的位置关系可以相同，或者可以不同，不同发光单元中的第一阳极301R、第二阳极301B、第三阳极301G1和第四阳极301G2的形状和位置可以相同，或者可以不同，本公开在此不做限定。
在示例性实施方式中，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D中的至少一个可以包括相互连接的主体部和连接部，主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，连接部的形状可以为沿着远离主体部方向延伸的条形状，连接部通过二十过孔V20与第五连接电极连接。
如图45所示，在E2区域，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D的主体部在基底上的正投影与第二连接线和数据信号线在基底上的正投影至少部分交叠。
如图44所示，在E1区域，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D的主体部在基底上的正投影与第二子高压电源线和数据信号线在基底上的正投影至少部分交叠。
如图43所示，在E0区域，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D的主体部在基底上的正投影与第一高压电源线和数据信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装 层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示面板可以应用于具有像素电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
图46为本公开实施例提供的显示装置的结构示意图。如图46所示，本公开实施例还提供一种显示装置，显示装置包括前述任一实施例提供的显示面板1和感光传感器2，感光传感器位于显示面板1的透光显示区10内。。
在示例性实施方式中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开并不以此为限。
在示例性实施方式中，当透光显示区10为矩形时，感光传感器2在基底上的正投影面积小于等于透光显示区10的内切圆的面积。
在示例性实施方式中，感光传感器2可以包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
在示例性实施方式中，前置摄像模组通常在用户自拍或视频通话时启用，显示装置的显示区显示自拍所得到的图像供用户观看。前置摄像模组例如包括镜头、图像传感器、图像处理芯片等。景物通过镜头生成的光学图像投射到图像传感器表面(图像传感器包括CCD和CMOS两种)变换为电信号，通过图像处理芯片模数转换后变为数字图像信号，再送到处理器中加工处理，在显示屏上输出该景物的图像。
在示例性实施方式中，3D结构光传感器和飞行时间法(Time of Flight，ToF)传感器可以用于人脸识别以对显示装置进行解锁。
本公开实施例提供的显示装置，可以在透光显示区区显示图像，以保持整个显示装置的显示完整性。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示面板，包括：显示区域，所述显示区域包括：透光显示区和位于透光显示区至少一侧的常规显示区，所述常规显示区包括第一区域、第二区域和第三区域，所述第一区域的至少一个电路单元与透光显示区中的发光器件连接，所述第三区域的至少一个电路单元包括数据连接线，位于第一区域的高压电源线为第一高压电源线，位于第二区域的高压电源线为第二高压电源线，位于第三区域的高压电源线为第三高压电源线；
    所述第二高压电源线包括：相互连接的第一子高压电源线和第二子高压电源线，所述第二子高压电源线位于所述第一子高压电源线远离基底的一侧，所述第一高压电源线与所述第二子高压电源线同层设置，所述第三高压电源线与所述第一子高压电源线同层设置。
  2. 根据权利要求1所述的显示面板，其中，所述数据连接线包括：相互连接的第一连接线和沿第二方向延伸的第二连接线，所述第一连接线位于第三高压电源线靠近基底的一侧，所述第二连接线与所述第一高压电源线同层设置；
    所述第一连接线在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，所述第二连接线在基底上的正投影与所述第三高压电源线在基底上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示面板，其中，所述第一连接线包括：沿第二方向延伸的第一数据连接部和沿第一方向延伸的第二数据连接部，所述第一数据连接部分别与第二数据连接部和第二连接线连接，所述第一方向和所述第二方向交叉；
    所述第一数据连接部在基底上的正投影与数据信号线在基底上的正投影至少部分交叠。
  4. 根据权利要求1或2所述的显示面板，其中，所述第二子高压电源线沿第一方向的长度小于第一子高压电源线沿第一方向的长度，且第二子高压电源线在基底上的正投影与第一子高压电源线在基底上的正投影至少部分交叠。
  5. 根据权利要求4所述的显示面板，其中，所述第一高压电源线沿第一方向、所述第一子高压电源线沿第一方向的长度和所述第三高压电源线近似相等，且所述第一高压电源线的形状、所述第一子高压电源线的形状和所述第三高压电源线的形状大致相同。
  6. 根据权利要求4所述的显示面板，其中，所述第二子高压电源线沿第一方向的长度与第二连接线沿第一方向的长度近似相等，且所述第二子高压电源线的形状与所述第二连接线的形状大致相同。
  7. 根据权利要求6所述的显示面板，其中，第二子高压电源线在基底上的正投影与第一子高压电源线在基底上的正投影的重叠区域的面积大于第二连接线在基底上的正投影与第三高压电源线在基底上的正投影的重叠区域的面积。
  8. 根据权利要求1所述的显示面板，其中，所述发光器件包括：阳极、有机发光层和阴极，所述显示面板还包括：沿第一方向延伸的多条第一阳极连接线，所述第一阳极连接线与所述第三高压电源线同层设置，且被配置为连接所述第一区域的至少一个电路单元和位于透光显示区的发光器件的阳极。
  9. 根据权利要求8所述的显示面板，其中，所述透光显示区包括：中心区域和围设在所述中心区域外侧的边缘区域；所述显示面板还包括：第二阳极连接线，所述第二阳极连接线位于第一高压电源线远离基底的一侧；
    所述第一阳极连接线被配置为连接所述第一区域的至少一个电路单元和位于所述边缘区域的发光器件的阳极，所述第二阳极连接线被配置为连接所述第一区域的至少一个电路单元和位于所述中心区域的发光器件的阳极。
  10. 根据权利要求9所述的显示面板，其中，所述第一阳极连接线包括：金属信号线，所述第二阳极连接线包括：透明导电信号线。
  11. 根据权利要求9所述的显示面板，其中，所述显示区域包括：多个发光单元，至少一个发光单元包括：第一发光器件、第二发光器件和第三发光器件，不同发光器件发射不同颜色的光线，所述第一发光器件和所述第二发光器件发射红色或者蓝色光线，所述第三发光器件发射绿色光线；
    对于位于边缘区域的发光单元，与同一发光单元的第三发光器件连接的 第一阳极连接线沿第一方向的长度小于与同一发光单元的第一发光器件和第二发光器件连接的第一阳极连接线沿第一方向的长度。
  12. 根据权利要求11所述的显示面板，其中，与位于边缘区域的任一第三发光器件连接的第一阳极连接线沿第一方向的长度小于与位于边缘区域的任一第一发光器件连接的第一阳极连接线和位于边缘区域的任一第二发光器件连接的第一阳极连接线沿第一方向的长度。
  13. 根据权利要求9所述的显示面板，其中，所述边缘区域占所述透光显示区的面积约为3％至8％，或者所述边缘区域包括的发光单元的数量为透光显示区中发光单元数量的5％至10％。
  14. 根据权利要求2至13任一项所述的显示面板，其中，所述像素电路至少包括电容和多个晶体管，所述电容包括：第一极板和第二极板；所述显示面板包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层、第一平坦层、第五导电层；
    所述半导体层至少包括多个晶体管的有源层；所述第一导电层至少包括多个晶体管的栅电极和电容的第一极板，所述第二导电层至少包括电容的第二极板，所述第三导电层至少包括多个晶体管的第一极和第二极以及第一连接线，所述第四导电层至少包括第一阳极连接线、第一子高压电源线和第三高压电源线，所述第五导电层至少包括：数据信号线、第一高压电源线、第二子高压电源线和第二连接线。
  15. 根据权利要求14所述的显示面板，其中，所述像素电路包括：写入晶体管，所述写入晶体管与数据信号线连接，位于第三区域的电容的第二极板包括：相互连接的电容主体部和辅助电容部，所述电容主体部与位于所述第一区域和所述第二区域的电容的第二极板的形状大致相同；辅助电容部在基底上的正投影与写入晶体管的有源层在基底上的正投影至少部分交叠。
  16. 根据权利要求14所述的显示面板，其中，所述第三导电层还包括：数据连接块，数据连接块在基底上的正投影与辅助电容部和第二连接线在基底上的正投影至少部分交叠；
    所述数据连接块分别与第一连接线和第二连接线连接。
  17. 根据权利要求16所述的显示面板，其中，数据连接块和第二数据连接部位于第一数据连接部的同一侧，且与第一数据连接部电连接；
    第一数据连接部在基底上的正投影与电容的第二极板在基底上的正投影至少部分交叠。
  18. 根据权利要求14所述的显示面板，其中，所述像素电路还包括：第一发光晶体管和第二发光晶体管，第一发光晶体管与高压电源线连接，第二发光晶体管与发光器件的阳极连接，所述第四导电层还包括：第一连接电极、第二连接电极、第三连接电极和第四连接电极；
    第一连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元的写入晶体管的第一极电连接，第二连接电极在基底上的正投影与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极在基底上的正投影至少部分交叠，且与位于第一区域至第三区域中的至少一个电路单元中的第二发光晶体管的第二极，第三连接电极在基底上的正投影与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极在基底上的正投影至少部分交叠，且与位于第一区域中的至少一个电路单元中的第一发光晶体管的第一极连接，第四连接电极在基底上的正投影与数据连接块在基底上的正投影至少部分交叠，且与数据连接块在基底上的正投影至少部分交叠。
  19. 根据权利要求18所述的显示面板，其中，所述第五导电层还包括：第五连接电极，第五连接电极在基底上的正投影与第二连接电极在基底上的正投影至少部分交叠，且与第二连接电极连接。
  20. 根据权利要求19所述的显示面板，其中，多条第一阳极连接线在基底上的正投影与第五连接电极和所连接的发光器件的阳极在基底上的正投影至少部分交叠。
  21. 根据权利要求18所述的显示面板，其中，数据信号线在基底上的正投影与第一连接电极在基底上的正投影至少部分交叠，且与第一连接电极连接，第一高压电源线在基底上的正投影与第三连接电极在基底上的正投影至少部分交叠，且与第三连接电极连接，第二连接线在基底上的正投影与第四 连接电极在基底上的正投影至少部分交叠，且与第四连接电极连接。
  22. 根据权利要求19所述的显示面板，还包括位于第二平坦层远离基底一侧的透明导电层，所述透明导电层包括第二阳极连接线，所述第二阳极连接线与第五连接电极在基底上的正投影至少部分交叠，且与第五连接电极连接。
  23. 一种显示装置，包括：如权利要求1至22任一项所述的显示面板和感光传感器；所述感光传感器位于所述显示面板的透光显示区内。
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