WO2023040356A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023040356A1
WO2023040356A1 PCT/CN2022/096404 CN2022096404W WO2023040356A1 WO 2023040356 A1 WO2023040356 A1 WO 2023040356A1 CN 2022096404 W CN2022096404 W CN 2022096404W WO 2023040356 A1 WO2023040356 A1 WO 2023040356A1
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WIPO (PCT)
Prior art keywords
transistor
pixel driving
signal line
pole
base substrate
Prior art date
Application number
PCT/CN2022/096404
Other languages
English (en)
French (fr)
Inventor
王琦伟
黄炜赟
杨妮
徐元杰
卢彦伟
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/CN2021/118279 external-priority patent/WO2023039721A1/zh
Priority claimed from PCT/CN2022/082809 external-priority patent/WO2023178612A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22868733.1A priority Critical patent/EP4274403A1/en
Priority to CN202280001619.7A priority patent/CN116158209A/zh
Publication of WO2023040356A1 publication Critical patent/WO2023040356A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a plurality of pixel driving circuits, a first planarization layer, a plurality of light emitting devices, a first power signal line and a data signal line, and the base substrate It includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the light transmittance of the second display area is greater than the light transmittance of the first display area
  • a plurality of pixel drive circuits are located on the base substrate and located in the first display area; the first planarization layer is located on the side of the plurality of pixel drive circuits away from the base substrate; a plurality of light emitting devices Located on a side of the first planarization layer away from the base substrate; a first power signal line is located on a side of the first planarization layer away from the base substrate, and is located in the first display area; The data signal line is located on the side of the first planarization layer away from the
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first initialization signal line configured to provide a first initialization signal to at least one of a plurality of pixel driving circuits; wherein, the device connection via hole, the The shortest distances between the power supply via hole and the data via hole and the first initialization signal line are substantially equal.
  • the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit
  • the plurality of light emitting devices include a first pixel driving circuit located in the first display area.
  • a light-emitting device and a second light-emitting device located in the second display area the device connection via hole includes a first via hole and a second via hole, and the first light-emitting device communicates with the The first pixel driving circuit is electrically connected, and the second light-emitting device is electrically connected to the second pixel driving circuit through the first connection line located in the first display area and the second display area, and in the In the first display area, the first connecting wire is electrically connected to the second pixel driving circuit through the second via hole.
  • the plurality of pixel driving circuits include a plurality of pixel circuit groups extending along the first direction and arranged along the second direction, and the pixel circuit groups in the plurality of pixel circuit groups At least one group includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, and a plurality of first via holes, a plurality of A second via hole, a plurality of power supply via holes and a plurality of data via holes are arranged along the first direction, and the first direction intersects with the second direction.
  • the multiple first via holes, multiple The shortest distances between the first initialization signal line, the plurality of power supply vias and the plurality of data vias are basically the same.
  • the multiple first via holes, multiple A second via hole, a plurality of power supply via holes and a plurality of data via holes are located on the same straight line, and the same straight line extends along the first direction.
  • the first connection traces are located on at least one side of the same straight line.
  • the extending direction of the first connection wiring from the first display area to the second display area is parallel to the first direction.
  • the first pixel driving circuit and the second pixel driving circuit respectively include a first transistor serving as a reset transistor, a second transistor serving as a compensation transistor, and a second transistor serving as a driving transistor.
  • the third transistor the gate electrode of the first transistor is connected to the reset signal line, the first pole of the first transistor is connected to the first initialization signal line, and the second pole of the first transistor is respectively connected to the first
  • the first electrode of the second transistor is connected to the gate electrode of the third transistor, the gate electrode of the second transistor is connected to the scanning signal line, and the second electrode of the second transistor is connected to the second electrode of the third transistor.
  • the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the scanning signal line and the reset signal line are located on the first first substrate on the substrate
  • the first pixel driving circuit and the second pixel driving circuit further include a storage capacitor, a fourth transistor serving as a data writing transistor, and a fourth transistor serving as a light emission control transistor.
  • the fifth transistor the gate electrode of the fourth transistor is connected to the scanning signal line, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor
  • One electrode is connected, the gate electrode of the fifth transistor is connected to the light-emitting control line, the first electrode of the fifth transistor is connected to the second electrode plate of the storage capacitor, and the second electrode of the fifth transistor is connected to the second electrode of the storage capacitor.
  • the first electrode of the third transistor is connected; the light emission control line is located in the first conductive layer.
  • the first pixel driving circuit and the second pixel driving circuit further include a sixth transistor serving as an emission control transistor and a seventh transistor serving as a reset transistor, so
  • the gate electrode of the sixth transistor is connected to the light-emitting control line
  • the first pole of the sixth transistor is connected to the second pole of the third transistor
  • the first light-emitting device or the second light-emitting device is connected to the light-emitting control line.
  • the second electrode of the sixth transistor is connected, the gate electrode of the seventh transistor is connected to the reset signal line, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the reset signal line.
  • the pole is connected to the second pole of the sixth transistor; the second initialization signal line is located in the second conductive layer.
  • the second initialization signal line used for the same first pixel driving circuit or the second pixel driving circuit in the first direction parallel to the base substrate, the reset signal line, the first initialization signal line and the scanning signal line are arranged in sequence.
  • the second transistor includes an active layer and two gate electrodes, and the active layer is located between the first metal layer and the base substrate.
  • the shielding pattern is integrally connected with the first initialization signal line.
  • the semiconductor material layer includes a semiconductor pattern connecting the active layer of the second transistor and the active layer of the first transistor, and the semiconductor pattern is in the The orthographic projection on the base substrate overlaps with the orthographic projection of the shielding pattern on the base substrate.
  • the first pole and the second pole of the first transistor, the first pole and the second pole of the second transistor, the first pole of the third transistor are located on the third conductive layer, and the third conductive layer is located on a side of the second conductive layer away from the base substrate.
  • the first power signal line is located on the fourth conductive layer
  • the fourth conductive layer is located on the side of the third conductive layer away from the base substrate.
  • the data signal lines are located in the fourth conductive layer.
  • the third conductive layer further includes a connecting portion between the second electrode of the first transistor and the gate electrode of the third transistor, and the first A power signal line further includes a protruding portion, and the orthographic projection of the connecting portion on the base substrate overlaps with the orthographic projection of the protruding portion on the base substrate.
  • the orthographic projection of the connecting portion on the base substrate is located within the orthographic projection of the protruding portion on the base substrate.
  • the interval between the patterns of the third conductive layer of the first pixel driving circuit and the second pixel driving circuit located in two adjacent rows is 7.0 ⁇ m-10.0 ⁇ m.
  • two adjacent second pixel driving circuits are arranged between two a first pixel drive circuit.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the display substrate along line B-B in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of the display substrate along line A-A in FIG. 1;
  • FIG. 4 is a partial plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of some functional layers of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of some functional layers of another display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a first pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a circuit diagram of a second pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure.
  • 9-15 are schematic plan views of each functional layer of a display substrate provided by at least one embodiment of the present disclosure and a plan view of each functional layer overlapping in sequence;
  • 16A-16D are schematic plan views of some functional layers of another display substrate provided by at least one embodiment of the present disclosure and a schematic plan view of the overlapping of the partial functional layers in sequence.
  • the display sub-pixels set in the camera area under the screen usually only include light-emitting devices, and the pixel drive circuit for driving the light-emitting device can be set in other display areas to avoid setting the pixel drive circuit under the screen.
  • the imaging area the light transmittance of the imaging area under the screen is reduced.
  • the light-emitting device needs to be connected to the pixel driving circuit arranged in other display areas through a long line, and the long line often has a large resistance, causing a voltage drop phenomenon, and the long line
  • the line may also form parasitic capacitance with other circuit patterns on the display substrate, which affects the electrical signal transmission of the display substrate;
  • the charging time of the display sub-pixels set in the camera area under the screen is often not enough , thus affecting the luminous brightness of the light-emitting device;
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a plurality of pixel driving circuits, a first planarization layer, a plurality of light emitting devices, a first power signal line and a data signal line, and the base substrate It includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the light transmittance of the second display area is greater than the light transmittance of the first display area; a plurality of pixel driving circuits are located on the substrate on the base substrate and located in the first display area; the first planarization layer is located on the side of the plurality of pixel driving circuits away from the base substrate; the plurality of light-emitting devices is located on the side of the first planarization layer away from the base substrate; the first The power signal line is located on the side of the first planarization layer away from the base substrate, and is located in the first display area; the data signal line is located on the side of the first planarization layer away
  • various traces and circuit patterns are arranged on the first planarization layer, and by arranging a plurality of via holes in the first planarization layer along the first direction, the The layout space of multiple via holes is more compact and regular, so that various traces and circuit patterns arranged on the first planarization layer avoid these via holes, so as to avoid these traces or circuit patterns from collapsing at the position of the via holes , causing defects such as short circuits, thereby improving the stability of these wirings and circuit patterns, thereby improving the reliability of the display substrate.
  • FIG. 1 shows a schematic plan view of the display substrate.
  • FIG. 2 shows a schematic cross-sectional view of the display substrate in FIG. 1 along line B-B.
  • FIG. 4 shows a partial plan view of the display substrate in FIG. 1 in the first display area and the second display area.
  • the display substrate includes a base substrate BS, a plurality of pixel drive circuits DR1/DR2, a first planarization layer PLN1, a plurality of light emitting devices EM1/EM2, a first power signal line VDD and data Signal line DT and other structures.
  • the base substrate BS includes a first display area 10 and a second display area 20, the first display area 10 at least partially surrounds the second display area 20, and it is shown in FIG. 1 that the first display area 10 completely partially surrounds the second display area 20 , in other embodiments, the first display area 10 may also partially surround the second display area 20 .
  • the light transmittance of the second display area 20 is greater than the light transmittance of the first display area 10 .
  • the second display area 20 may be a light-transmitting display area of the display substrate, which can transmit some light signals.
  • a plurality of pixel driving circuits DR1/DR2 are located on the base substrate BS and located in the first display area 10, and the first planarization layer PLN1 is located on the side BS of the plurality of pixel driving circuits DR1/DR2 away from the base substrate.
  • the first light emitting device EM1/EM2 is located on the side of the first planarization layer PLN1 away from the base substrate BS;
  • the first power signal line VDD is located on the side of the first planarization layer PLN1 away from the base substrate BS, and is located Region 10 ;
  • the data signal line DT is located on the side of the first planarization layer PLN1 away from the base substrate 110 , and is located in the first display region 10 .
  • the first planarization layer PLN1 includes at least one (for example, each) of a plurality of pixel driving circuits DR1/DR2 and at least one of a plurality of light emitting devices EM1/EM2.
  • each electrically connected device connection vias V1/V2 a power supply via V3 electrically connecting at least one (for example, each) of a plurality of pixel driving circuits with the first power signal line VDD, and a plurality of pixels
  • At least one (for example, each) of the driving circuit is electrically connected to the data signal line DT through the data via V4, the device connection via V1/V2, the power via V3 and the data via V4 along the first direction (for example, in FIG. 6 ). horizontal direction) arrangement.
  • the display substrate further includes a first initialization signal line Vin1 configured to provide a first initialization signal to at least one of the plurality of pixel drive circuits DR1/DR2; the device connection via hole V1 /V2, the power via V3 and the data via V4 are basically equal to the shortest distances from the first initialization signal line Vin1, that is, the device connection via V1/V2, the power via V3 and the data via V4 are arranged in the same distance as the first initialization signal line Vin1.
  • the initialization signal lines Vin1 are located at substantially the same distance.
  • the first initialization signal line Vin1 extends along the above-mentioned first direction.
  • the arrangement space of the multiple first vias V1, the multiple second vias V2, the multiple power supply vias V3, and the multiple data vias V4 is more compact and regular, so that A variety of traces (such as the first connecting trace TL) and circuit patterns are provided to avoid these via holes, so as to improve the stability of these traces and circuit patterns, thereby improving the reliability of the display substrate.
  • the second display area 20 is a circle, and in other embodiments, the second display area 20 can also be other figures such as rectangle, triangle or ellipse.
  • the diameter of the circle can be about 3 mm to 5 mm; 3 mm to 5 mm, the embodiment of the present disclosure does not limit the specific shape and size of the second display area 20 .
  • a plurality of pixel driving circuits include a plurality of first pixel driving circuits DR1 and a plurality of second pixel driving circuits DR2, and a plurality of light emitting devices include a first light emitting device EM1 located in the first display area 10 and a plurality of light emitting devices located in the second display area 20
  • the second light emitting device EM2 the device connection via holes include a first via hole V1 and a second via hole V2
  • the first light emitting device EM1 is electrically connected to the first pixel driving circuit DR1 through the first via hole V1
  • the second light emitting device EM2 It is electrically connected to the second pixel driving circuit DR2 through the first connection line TL located in the first display area 10 and the second display area 20, and in the first display area 10, the first connection line TL passes through the second via hole V2 It is electrically connected with the second pixel driving circuit DR2.
  • the first display area 10 is configured to display images, including a plurality of first pixel drive circuits DR1 and a plurality of second pixel drive circuits DR2, a first planarization layer PLN1, and a plurality of pixel drive circuits.
  • a first light-emitting device EL1; a plurality of first pixel drive circuits DR1 and a plurality of second pixel drive circuits DR2 are arranged in multiple rows and multiple columns, as shown in Figure 4, the row direction is, for example, the horizontal direction in the figure, and the column direction is the vertical direction in the figure.
  • the first planarization layer PLN1 is disposed on a side away from the base substrate BS of the plurality of first pixel driving circuits DR1 and the plurality of second pixel driving circuits DR2 .
  • a plurality of first light emitting devices EL1 are disposed on a side of the first planarization layer PLN1 away from the base substrate BS.
  • the first pixel driving circuit DR1 and the second pixel driving circuit DR2 respectively include a 2T1C structure (that is, two transistors and a storage capacitor), a 3T1C structure, a 7T1C structure or an 8T2C structure composed of a transistor and a storage capacitor C, etc.
  • a 2T1C structure that is, two transistors and a storage capacitor
  • 3T1C structure that is, a 3T1C structure
  • a 7T1C structure or an 8T2C structure composed of a transistor and a storage capacitor C, etc.
  • Embodiments of the present disclosure do not limit the specific forms of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 .
  • FIG. 2 and FIG. 3 show a driving transistor, such as the third transistor T3 in the 7T1C structure described in detail later.
  • the third transistor T3 in the first pixel driving circuit DR1 and the second pixel driving circuit DR2 includes an active layer T3a, a gate electrode T3g, a first pole T3s and a second pole T3d.
  • the storage capacitor C includes a first plate C1 and a second plate C2.
  • the gate electrode T3g and the first electrode plate C1 are arranged on the first conductive layer Gate1 (described in detail later), and the second electrode plate C2 is arranged on the second conductive layer Gate2 on the side of the first conductive layer away from the substrate substrate (later described in detail).
  • the first pole T3s and the second pole T3d are arranged on the third conductive layer SD1 on the side of the second conductive layer away from the base substrate (detailed introduction later).
  • a first gate insulating layer GI1 is disposed between the active layer T3a and the gate electrode T3g
  • a second gate insulating layer GI2 is disposed between the first plate C1 and the second plate C2
  • the second plate C2 is connected to the second plate C2.
  • An interlayer insulating layer IDL is provided between the first pole T3s and the second pole T3d.
  • the active layer T3a includes a channel region and a first region and a second region located on both sides of the channel region, the semiconductor material of the first region and the second region is conductorized, and the first pole T3s and the second pole T3d are respectively It is respectively connected to the first region and the second region of the active layer T3 a through the via holes in the first gate insulating layer GI1 and the second gate insulating layer GI2 .
  • the first light-emitting device EL1 and the second light-emitting device EL2 can be electrically connected to the first pixel driving circuit DR1 and the second pixel driving circuit DR2 respectively through the connection electrode CE, and the connection electrode CE is arranged on the third conductive layer away from the base substrate.
  • the fourth conductive layer SD2 on one side (described in detail later).
  • the first light-emitting device EL1 and the second light-emitting device EL2 may be OLEDs, including a first electrode E1 (such as an anode), an organic light-emitting layer E2, and a second electrode E3 (such as a cathode) stacked, referring to FIGS. 2 and 3 or, the first light-emitting device EL1 and the second light-emitting device EL2 can also be QLEDs, including stacked first electrode E1 (such as anode), quantum dot layer E2 and second electrode E3 (such as cathode).
  • the second electrodes E3 of the first light emitting device EL1 and the second light emitting device EL2 may be surface electrodes disposed continuously on the display substrate.
  • an encapsulation layer EN is provided on the first light emitting device EL1 and the second light emitting device EL2, for example, the encapsulation layer EN may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer (not shown in the figure).
  • the first encapsulation layer and the third encapsulation layer can use inorganic materials, such as silicon oxide, silicon nitride or silicon oxynitride, etc.
  • the second encapsulation layer can use organic materials, such as polyimide, resin, etc.
  • the second encapsulation layer The layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the first light emitting device EL1 and the second light emitting device EL2.
  • FIG. 6 shows a schematic plan view of some functional layers of the display substrate in FIG. 1.
  • the first planarization layer PLN1 includes a plurality of first via holes V1, a plurality of The second via hole V2, a plurality of power supply via holes V3 and a plurality of data via holes V4, and a plurality of first light emitting devices EL1 are respectively connected to each other through a plurality of first via holes V1 (such as the first electrodes provided in the first via holes V1).
  • the electrode CE) is electrically connected to a plurality of first pixel driving circuits DR1, for example, is electrically connected to the first pole or the second pole of the third transistor.
  • the plurality of first light emitting devices EL1 are driven in an "in-situ" driving manner, as shown in FIG. 3 .
  • the second display area 20 is configured to display images and transmit light, and includes a plurality of second light emitting devices EL2, and the plurality of second light emitting devices EL2 pass through the first display respectively.
  • the plurality of first connecting traces TL extending from the region 10 and the second display region 20 are electrically connected to a plurality of second pixel driving circuits DR2, for example, electrically connected to the first electrode or the second electrode of the third transistor, and connected to the first In the display area 10, a plurality of first connecting traces TL are electrically connected to a plurality of second pixel driving circuits DR2 through a plurality of second via holes V2 (for example, through the first electrode connection electrodes CE provided in the second via holes V2) .
  • the multiple second light emitting devices EL2 are driven in a “remote” driving manner, as shown in FIG. 2 .
  • one structure is electrically connected to another structure through a via hole means that the one structure is directly electrically connected to the other structure through the via hole, or the one structure is indirectly connected through the via hole.
  • the connection structure provided in the via hole is electrically connected to the other structure, as long as the electrical connection between the one structure and the other structure is realized through the via hole.
  • the display substrate may further include a third display area 30, which is the main display area of the display substrate, and also includes a plurality of first pixel drive circuits DR1 and a plurality of a second pixel driving circuit DR2, and includes a plurality of third light-emitting devices, and a plurality of first pixel driving circuits DR1 in the third display area 30 are respectively electrically connected with a plurality of third light-emitting devices to drive the plurality of third light-emitting devices
  • the second pixel driving circuit DR2 in the third display area 30 is not connected to the light emitting device.
  • the first power signal line VDD is electrically connected to a plurality of first pixel driving circuits DR1 and a plurality of second pixel driving circuits DR2 through a plurality of power supply vias V3, so as to supply power to the first pixel driving circuit DR1. and a plurality of second pixel driving circuits DR2 to improve power supply signals, such as high-level signals.
  • a plurality of pixel driving circuits include a plurality of pixel circuit groups G (for example, a row of pixel driving circuits, one group/one row is shown in the figure as an example), at least one of the plurality of pixel circuit groups G includes a plurality of first pixel driving circuits DR1 and a plurality of second pixel driving circuits DR2, the plurality of A plurality of first vias V1, a plurality of second vias V2, a plurality of power supply vias V3 and a plurality of data vias V4 adopted by a first pixel driving circuit DR1 and a plurality of second pixel driving circuits DR2 are along the Arranged in one direction, the first direction and the second direction intersect.
  • the plurality of first via holes V1, the plurality of second via holes V2, the plurality of power The shortest distance between the via V3 and the plurality of data vias V4 and the first initialization signal line Vin1 is substantially the same.
  • the plurality of first via holes V1, the plurality of second via holes V2, the plurality of power The via V3 and the plurality of data vias V4 are located on the same straight line L1 extending along the first direction.
  • the arrangement space of the multiple first vias V1, the multiple second vias V2, the multiple power supply vias V3, and the multiple data vias V4 is more compact and regular, so that A variety of traces (such as the first connecting trace TL) and circuit patterns are provided to avoid these via holes, so as to improve the stability of these traces and circuit patterns, thereby improving the reliability of the display substrate.
  • a plurality of vias located on the same straight line means that the same straight line can be used to pass through the plurality of vias in sequence, such as passing through any position of each via, not limited to at the center of multiple vias.
  • the centers of the multiple first vias V1, the multiple second vias V2, the multiple power supply vias V3, and the multiple data vias V4 may be located on the same straight line L1 to maximize The arrangement of the plurality of first vias V1, the plurality of second vias V2, the plurality of power supply vias V3 and the plurality of data vias V4 is regularly arranged.
  • the plurality of first connection traces TL are located on at least one side of the same straight line (ie, the first straight line L1 ).
  • the plurality of first connection lines TL are located in the plurality of first via holes V1, the plurality of second via holes V2, the plurality of Between the straight line L1 where a power supply via V3 and a plurality of data vias V4 are located.
  • the extending direction of the plurality of first connection traces TL from the first display area 10 to the second display area 20 is parallel to the above-mentioned same straight line (that is, the first The straight line L1), for example, extends along the first direction, so that in the direction perpendicular to the base substrate, the plurality of first connection traces TL will not interfere with the plurality of first via holes set on the first straight line L1 V1, a plurality of second vias V2, a plurality of power supply vias V3, and a plurality of data vias V4 overlap, thereby preventing multiple first connection traces TL from being arranged above the via holes and resulting in multiple first connection traces TL Failures such as short circuit and open circuit have occurred.
  • the data signal lines DT are electrically connected to multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 through multiple data vias V4 .
  • the orthographic projections of the plurality of data vias V4 on the base substrate BS are located between the orthographic projections of two adjacent first connecting traces TL on the base substrate BS.
  • multiple first vias V1, multiple second vias V2 and multiple power supply vias V3 used by the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are located on the first straight line L1
  • the plurality of data vias V4 used by the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are located on a second straight line L2 different from the first straight line L1.
  • the embodiment of FIG. 6 Compared with the embodiment of FIG. 5 , in the embodiment of FIG. 6 , more than one part of the first planarization layer PLN1 on the first pixel driving circuit DR1 and the second pixel driving circuit DR2 located in the same group (for example, the same row)
  • the via holes are concentrated on the same straight line, thereby further saving the arrangement space of the via holes, and making the multiple first connection traces TL fully avoid the multiple via holes in the first planarization layer PLN1, thereby improving the efficiency of multiple via holes. Reliability of the first connection trace TL.
  • FIG. 7 shows a circuit diagram of the first pixel driving circuit DR1
  • FIG. 8 shows a circuit diagram of the second pixel driving circuit DR2.
  • the circuit DR2 includes a first transistor T1 as a reset transistor, a second transistor T2 as a compensation transistor, and a third transistor T3 as a drive transistor, the gate electrode of the first transistor T1 is connected to the reset signal line Res, and the gate electrode of the first transistor T1
  • the first pole is connected to the first initialization signal line Vin1
  • the second pole of the first transistor T1 is respectively connected to the first pole of the second transistor T2, the gate electrode of the third transistor T3 and the first plate C1 of the storage capacitor C
  • the gate electrode of the second transistor T2 is connected to the scanning signal line Gate
  • the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T2.
  • the second electrode of the first transistor T1, the gate electrode of the third transistor T3 and the first plate C1 of the storage capacitor C meet at the node N1.
  • the gate electrode of the first transistor T1, the gate electrode of the second transistor T2, the gate electrode of the third transistor T3, the first plate C1 of the storage capacitor C, the scanning signal line Gate and the reset signal line Res are located on the base substrate BS.
  • the first conductive layer above is also referred to as the Gate1 layer hereinafter.
  • the first initialization signal line Vin1 is located on the second conductive layer, also referred to as Gate2 layer hereinafter, and the second conductive layer is located on a side of the first conductive layer away from the base substrate BS.
  • the first pixel driving circuit DR1 and the second pixel driving circuit DR2 further include a storage capacitor C, a fourth transistor T4 as a data writing transistor, and a fifth transistor as a light emission control transistor.
  • the gate electrode of the fourth transistor T4 is connected to the scanning signal line Gate, the first pole of the fourth transistor T4 is connected to the data signal line DT, the second pole of the fourth transistor T4 is connected to the first pole of the third transistor T3,
  • the gate electrode of the fifth transistor T5 is connected to the light emission control line EM, the first electrode of the fifth transistor T5 is connected to the second plate C2 of the storage capacitor C, and the first electrode of the fifth transistor T5 is connected to the second plate C2 of the storage capacitor C.
  • the pole plate C2 is connected to the first power signal line VDD, and the second pole of the fifth transistor T5 is connected to the first pole of the third transistor T3.
  • the second pole of the fourth transistor T4, the first pole of the third transistor T3 and the second pole of the fifth transistor T5 meet at the node N2.
  • the gate electrode of the fourth transistor T4, the gate electrode of the fifth transistor T5 and the light emission control line EN are located on the first conductive layer.
  • the first pixel driving circuit DR1 and the second pixel driving circuit DR2 further include a sixth transistor T6 as a light emission control transistor and a seventh transistor T7 as a reset transistor, the sixth transistor T6
  • the gate electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the first electrode of the first light emitting device EL1 or the second light emitting device EL2 is connected to the second electrode of the sixth transistor T6.
  • the second pole is connected, the gate electrode of the seventh transistor T7 is connected to the reset signal line Res, the first pole of the seventh transistor T7 is connected to the second initialization signal line Vin2, the second pole of the seventh transistor T7 is connected to the sixth transistor T6 Second pole connection.
  • the first pole of the sixth transistor T6 meets the second pole of the third transistor T3 at the node N3.
  • the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 meet at the node N4.
  • the second electrodes of the first light emitting device EL1 and the second light emitting device EL2 are connected to the second power supply line VSS.
  • the signal transmitted by the second power supply line VSS is a low-level signal
  • the signal transmitted by the first power signal line VDD is a high-level signal.
  • the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are formed into a 7T1C structure (that is, including seven transistors and one storage capacitor).
  • the gate electrodes of the sixth transistor T6 and the seventh transistor T7 are located on the first conductive layer, and the second plate C2 of the storage capacitor C and the second initialization signal line Vin2 are located on the second conductive layer.
  • the second pole, the first pole and the second pole of the fifth transistor T5, the first pole and the second pole of the sixth transistor T6 are located, and the first pole and the second pole of the seventh transistor T7 are located in the third conductive layer (also referred to as SD1 layer), the third conductive layer is located on the side of the second conductive layer away from the base substrate BS.
  • the first pole may be the drain electrode of the transistor, and the second pole may be the source electrode of the transistor, or the first pole may be the source electrode of the transistor, and the second pole may be the drain electrode of the transistor.
  • the functions of the "source electrode” and “drain electrode” may be interchanged.
  • the above-mentioned first power signal line VDD is located on the fourth conductive layer (also referred to as SD2 layer), and the fourth conductive layer is located on the side of the third conductive layer away from the base substrate BS.
  • the data signal line DT is also located on the fourth conductive layer.
  • the thin film transistor connected to the first light emitting device EL1 and the second light emitting device EL2 is the third transistor T3 mentioned above.
  • the above-mentioned circuit structures of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are the same, the difference is that, as shown in FIG.
  • the longer first connection trace TL extended by 20 is connected to the second pixel driving circuit DR2, which is equivalent to connecting a resistor in series between the node N4 where the sixth thin film transistor T6 and the seventh thin film transistor meet and the second light emitting device EL2 R-TL and a capacitor C-TL are connected in parallel.
  • Two first pixel driving circuits DR1 are arranged between the pixel driving circuits DR2. That is, in the first display area 10 , every two first pixel driving circuits DR1 and one second pixel driving circuit DR2 constitute a repeating unit, and multiple repeating units are periodically arranged in the first display area 10 .
  • a plurality of second pixel driving circuits DR2 for connecting a plurality of second light emitting devices EL2 are disposed close to the second display region 20, so that the length of the first connecting trace TL is sufficiently reduced, thereby weakening or even Eliminate the resistance R-TL and capacitance C-TL between the node N4 and the second light emitting device EL2, and solve the problems of the second light emitting device EL2 in the second display area 20, such as dim luminous brightness and insufficient charging time under high frequency ;
  • the number of first pixel driving circuits DR1 that the first connecting lines TL pass through is reduced, so that problems such as disconnection of the first connecting lines TL in the first pixel driving circuit DR1 can also be reduced.
  • the above-mentioned first transistor T1 to seventh transistor T7 may be thin film transistors, such as P-type thin film transistors, or may be N-type thin film transistors.
  • Using the same type of transistors in the first pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon transistors, or may use oxide transistors, or may use low temperature polysilicon transistors and metal oxide transistors.
  • the active layer of the low temperature polysilicon transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide).
  • Low temperature polysilicon transistors have the advantages of high mobility and fast charging, and oxide transistors have the advantages of low leakage current.
  • the low temperature polysilicon transistors and metal oxide transistors are integrated on a display substrate to form low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide) , referred to as LTPO) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the working process of the first pixel driving circuit may include:
  • the first stage A1 is called the reset stage, the signal of the reset signal line Res is an on signal, and the signals of the scanning signal line Gate and the light emitting signal line EM are an off signal.
  • the conduction signal of the reset signal line Res turns on the first transistor T1, and the signal of the first initialization signal line Vin1 is provided to the first node N1 through the first transistor T1 to initialize (reset) the storage capacitor C and clear the storage capacitor C. There is a charge.
  • the turn-on signal of the reset signal line Res turns on the seventh transistor T7, and the signal of the second initialization signal line Vin2 is provided to the first electrode of the first light-emitting device EL1 or the second light-emitting device EL2 through the seventh transistor T7.
  • the first electrode of the light emitting device EL1 or the second light emitting device EL2 is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization.
  • the off signal of the scanning signal line Gate and the light emitting signal line EM turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, and at this stage the first light emitting device EL1 or the second light emitting device EL2 does not glow.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is an on signal
  • the signals of the reset signal line Res and the light emitting signal line EM are an off signal
  • the data signal line DT outputs a data voltage.
  • the third transistor T3 is turned on.
  • the turn-on signal of the scanning signal line Gate turns on the second transistor T2 and the fourth transistor T4, and the data voltage output by the data signal line DT passes through the second node N2, the turned-on third transistor T3, the third node N3, and turns on.
  • the off signal of the reset signal line Res turns off the first transistor T1 and the seventh transistor T7, and the off signal of the light emitting signal line EM turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is an on signal, and the signals of the scanning signal line Gate and the reset signal line Res are off signals.
  • the conduction signal of the light-emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power signal line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6 to the
  • the first electrode of the first light emitting device EL1 or the second light emitting device EL2 provides a driving voltage to drive the first light emitting device EL1 or the second light emitting device EL2 to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the first light-emitting device EL1 or the second light-emitting device EL2, K is a constant, and Vgs is the difference between the gate electrode and the first electrode of the third transistor T3.
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output from the data signal line D
  • Vdd is the power supply voltage output from the first power signal line VDD.
  • FIGS. 9-15 show schematic plan views of various functional layers of the display substrate in the embodiment shown in FIG. 5 .
  • FIG. 9 shows a schematic plan view of a semiconductor layer ACT disposed on a base substrate.
  • the semiconductor layer ACT includes an active layer T1a of the first transistor T1, an active layer T2a of the second transistor T2, an active layer T3a of the third transistor T3, an active layer T4a of the fourth transistor T4, The active layer T5a of the fifth transistor T5, the active layer T6a of the sixth transistor T6, and the seventh active layer T7a of the seventh transistor T7.
  • the active layers of these transistors are an integral structure connected to each other.
  • the active layer T6a of the sixth transistor T6 of the Mth row of pixel driving circuits is connected to the active layer T6a of the M+1th row of pixel driving circuits.
  • the seventh active layer T7a of the seventh transistor T7 is connected to each other, that is, the semiconductor layers of adjacent pixel driving circuits in each column of pixel driving circuits are connected to each other as an integral structure.
  • the shape of the active layer T1a of the first transistor T1 can be "n"
  • the shape of the active layer T2a of the second transistor T2 can be “L”
  • the shape of the active layer T3a of the third transistor T3 can be In the shape of " ⁇ ”
  • the shape of the active layer T4a of the fourth transistor T4 the active layer T5a of the fifth transistor T5, the active layer T6a of the sixth transistor T6 and the seventh active layer T7a of the seventh transistor T7 can be It is in the shape of "I”.
  • the active layer of each transistor may include a channel region and a first region and a second region located on both sides of the channel region.
  • the first pole and the second pole are electrically connected.
  • the first gate insulating layer GI1 is formed on the semiconductor layer ACT, which will not be repeated here.
  • FIG. 10A shows a schematic plan view of the first conductive layer Gate1 disposed on the semiconductor layer
  • FIG. 10B shows a schematic plan view of the overlapping of the first conductive layer Gate1 and the semiconductor layer ACT.
  • the pattern of the first conductive layer Gate1 of each first pixel driver circuit and each second pixel driver circuit at least includes a reset signal line Res, a scan signal line Gate, an emission control line EM and a memory
  • the first plate C1 of the capacitor C is a reset signal line Res, a scan signal line Gate, an emission control line EM and a memory
  • the shape of the first plate C1 of the storage capacitor C can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the first plate C1 on the base substrate is consistent with the active layer of the third transistor T3
  • the orthographic projections on the substrate substrate at least partially overlap.
  • the first plate C1 of the storage capacitor C can serve as the gate electrode of the third transistor T3 at the same time.
  • the shape of the reset signal line Res, the scan signal line Gate, and the emission control line EM may be a line shape whose main part extends along the row direction of the pixel driving circuit.
  • the area where the scanning signal line Gate overlaps the active layer of the second transistor T2 can be used as the gate electrode T2g of the second transistor T2, and the scanning signal line Gate is provided with a protrusion protruding to the side of the reset signal line Res.
  • the protruding portion, the orthographic projection of the protruding portion on the substrate at least partially overlaps the orthographic projection of the active layer of the second transistor T2 on the substrate, thereby forming the second transistor T2 with a double gate structure.
  • the area where the scanning signal line Gate overlaps with the active layer of the fourth transistor T4 is used as the gate electrode T4g of the fourth transistor T4, and the area where the reset signal line Res overlaps with the active layer of the first transistor is used as the double gate structure.
  • the gate electrode T1g of the first transistor T1 the area where the reset signal line Res overlaps with the active layer of the seventh transistor T7 is used as the gate electrode T7g of the seventh transistor T7, and the light emission control line EM is in phase with the active layer of the fifth transistor T5.
  • the overlapping area is used as the gate electrode T5g of the fifth transistor T5, and the area where the emission control line EM overlaps with the active layer of the sixth transistor T6 is used as the gate electrode T6g of the sixth transistor T6.
  • the second gate insulating layer GI2 is formed on the first conductive layer Gate1 , which will not be repeated here.
  • FIG. 11A shows a schematic plan view of the second conductive layer Gate2 disposed on the first conductive layer Gate1
  • FIG. 11B shows a schematic plan view of the second conductive layer Gate2 overlapping the first conductive layer Gate1 and the semiconductor layer ACT.
  • the pattern of the second conductive layer Gate2 of each first pixel driving circuit and each second pixel driving circuit at least includes a first initialization signal line Vin1, a second initialization signal line Vin2, a storage capacitor C's second pole plate C2 and the shielding pattern SH.
  • the active layer of the second transistor T2 has a first portion P1 between its two gate electrodes, and the orthographic projection of the first portion P1 on the base substrate is the same as that of the two gate electrodes on the base substrate.
  • the orthographic projections on do not overlap, and the orthographic projections of the first portion P1 on the substrate overlap with the orthographic projections of the shielding pattern SH (for example, the first shielding portion SH1 of the shielding pattern SH) on the substrate. Therefore, the shielding pattern SH can realize shielding and voltage stabilizing functions for the active layer of the second transistor T2.
  • the shape of the shielding pattern SH can be a broken line, and the shielding pattern SH is integrally connected with the first initialization signal line Vin1, so that the shielding pattern SH can obtain a constant voltage signal from the first initialization signal line Vin1 to fully achieve the function of voltage stabilization.
  • the semiconductor material layer ACT includes a semiconductor pattern P2 connecting the active layer of the second transistor T2 and the active layer of the first transistor T1, and the orthographic projection and the shielding pattern of the semiconductor pattern P2 on the base substrate Orthographic projections of SH (for example, the second shielding portion SH2 of the shielding pattern SH) on the base substrate overlap.
  • the shielding pattern SH can also shield the impact of data voltage jumps on key nodes (such as the N1 node), avoiding data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, and achieving the effect of voltage stabilization.
  • the second plate C2 of the storage capacitor C can be located between the scanning signal line Gate and the light emission control line EM, and the adjacent second plates C2 in the row direction can be electrically connected to ensure that multiple second plates C2 in the same row
  • the electrode plates C2 have the same potential, which is beneficial to improve the uniformity of the display substrate, and further improve the display effect of the display substrate.
  • the outline of the second pole plate C2 can be a rectangle, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second pole plate C2 on the base substrate and the orthographic projection of the first pole plate C1 on the base substrate are at least Partially overlap to form the storage capacitor C of the pixel driving circuit.
  • An opening is provided on the second pole plate C2, and the opening may be located in the middle of the second pole plate C2.
  • the opening may be rectangular, so that the second pole plate C2 forms a ring structure.
  • the opening is configured to accommodate a subsequently formed connection via hole
  • the connection via hole is located in the opening and exposes the first plate C1, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode plate C1 through the connection via hole.
  • a pole plate C1 is connected.
  • the shape of the first initialization signal line Vin1 and the second initialization signal line Vin2 may be a line shape in which the main part extends along the row direction.
  • the second initialization signal for the same first pixel driving circuit DR1 or the second pixel driving circuit DR2 The line Vin2, the reset signal line Res, the first initialization signal line Vin1 and the scanning signal line Gate are arranged in sequence.
  • the signal lines in the first conductive layer Gate1 and the second conductive layer Gate2 are arranged alternately, so as to avoid signal crosstalk, short circuit and other defects caused by too dense signal lines in the same conductive layer.
  • an interlayer insulating layer IDL is formed on the second conductive layer Gate2 , which will not be repeated here.
  • FIG. 12A shows a schematic plan view of the third conductive layer SD1 disposed on the second conductive layer Gate2, and FIG. 12B shows that the third conductive layer SD1 intersects with the second conductive layer Gate2, the first conductive layer Gate1 and the semiconductor layer ACT. Stacked floor plan.
  • the pattern of the third conductive layer SD1 of each first pixel driver circuit and each second pixel driver circuit at least includes a first connection electrode 11, a second connection electrode 12, a third connection electrode 13.
  • the fourth connection electrode 14 , the fifth connection electrode 15 and the sixth connection electrode 16 is a schematic plan view of the third conductive layer SD1 disposed on the second conductive layer Gate2
  • FIG. 12B shows that the third conductive layer SD1 intersects with the second conductive layer Gate2, the first conductive layer Gate1 and the semiconductor layer ACT. Stacked floor plan.
  • the pattern of the third conductive layer SD1 of each first pixel driver circuit and each second pixel driver circuit at least includes a first connection electrode 11, a second connection electrode 12, a third connection electrode 13.
  • the shape of the first connection electrode 11 can be a strip shape whose main part extends along the column direction, the first end of the first connection electrode 11 is connected to the first electrode plate C1 through a via hole, and the second end of the first connection electrode 11 is connected to the first electrode plate C1.
  • the terminal is connected to the second region of the active layer of the first transistor T1 (also the first region of the active layer of the second transistor T1) through a via hole, so that the first plate C1, the second electrode of the first transistor T1 and The first poles of the second transistor T2 have the same potential.
  • the first connection electrode 41 can serve as the second pole of the first transistor T1 and the first pole of the second transistor T2 at the same time.
  • the shape of the second connection electrode 12 can be a strip shape extending along the row direction, the first end of the second connection electrode 12 is connected to the first region of the active layer of the first transistor through a via hole, and the second connection electrode The second end of 12 is connected to the first initialization signal line Vin1 through a via hole.
  • the second connection electrode 12 can be used as the first electrode of the first transistor T1, so that the first initialization signal line Vin1 writes the first initial signal into the first transistor T1.
  • the shape of the third connection electrode 13 may be a zigzag shape, the first end of the third connection electrode 13 is connected to the first region of the active layer of the seventh transistor through a via hole, and the second end of the third connection electrode 13 is connected through The via hole is connected to the second initialization signal line Vint2.
  • the third connection electrode 13 can be used as the first electrode of the seventh transistor T7, so that the second initialization signal line Vint2 can write the second initial signal into the seventh transistor T7.
  • the shape of the fourth connection electrode 14 may be a dumbbell shape, and the fourth connection electrode 14 is connected to the first region of the active layer of the fourth transistor through a via hole.
  • the fourth connection electrode 14 can serve as the first pole of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to the subsequently formed data signal line DT.
  • the shape of the fifth connection electrode 15 can be approximately "Z" shape, the first end of the fifth connection electrode 15 is connected to the first region of the active layer of the fifth transistor T5 through a via hole, and the fifth connection electrode 15 The second end is connected to the second plate C2 through the via hole, so that the second plate C2 and the first region of the active layer of the fifth transistor T5 have the same potential.
  • the fifth connection electrode 15 can serve as the first electrode of the fifth transistor T5.
  • the shape of the sixth connection electrode 16 can be rectangular, and the sixth connection electrode 16 is connected to the second region of the active layer of the sixth transistor T6 (also the second region of the active layer of the seventh transistor T7) through the via hole. connected so that the second region of the active layer of the sixth transistor T6 and the second region of the active layer of the seventh transistor T7 have the same potential.
  • the sixth connection electrode 16 can serve as the second pole of the sixth transistor T6 (or the second pole of the seventh transistor T7).
  • the interval D1 between the patterns of the third conductive layer SD1 of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 located in two adjacent rows is 7.0 ⁇ m-10.0 ⁇ m, for example, 8.0 ⁇ m, 8.5 ⁇ m, Micron, 9.0 micron or 9.5 micron etc.
  • the patterns of the third conductive layer SD1 of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 in two adjacent rows have a relatively large interval, and the interval can provide for other circuit patterns and traces on the display substrate. Arrange space.
  • FIG. 13 shows a schematic plan view of the first flat layer PLN1 disposed on the third conductive layer SD1.
  • the first flat layer PLN1 includes a plurality of first via holes V1, a plurality of second via holes V2, multiple power vias V3 and multiple data vias V4.
  • a plurality of first via holes V1 are used to connect the first electrode CE used by the first light emitting device EL1 with the first pixel driving circuit DR1, and a plurality of second via holes V2 are used to connect the first electrode CE used by the second light emitting device EL2.
  • the electrode is connected to the electrode CE and the second pixel driving circuit DR2, a plurality of power supply vias V3 are used to connect the subsequent first power supply signal line VDD and the first pixel driving circuit DR1/second pixel driving circuit DR2, and a plurality of data vias V4 It is used to connect the subsequent data signal line DT with the first pixel driving circuit DR1/the second pixel driving circuit DR2.
  • the plurality of first vias V1, the plurality of second vias V2 and the plurality of power supply vias V3 are located on the same straight line, that is, on the first straight line L1
  • the plurality of data vias V4 are located on another On a straight line, that is, on the second straight line L2.
  • FIG. 14A shows a schematic plan view of the fourth conductive layer SD2 disposed on the first planarization layer PLN1
  • FIG. 14B shows a schematic plan view of the overlapping of the fourth conductive layer SD2 and the third conductive layer SD1
  • FIG. 14C shows A schematic plan view of the overlapping of the fourth conductive layer SD2 with the third conductive layer SD1, the second conductive layer Gate2, the first conductive layer Gate1 and the semiconductor layer ACT is shown.
  • the pattern of the fourth conductive layer SD2 of each first pixel driving circuit and each second pixel driving circuit includes at least the first electrode connecting electrode CE, the data signal line DT and the second pixel driving circuit.
  • a power signal line VDD A power signal line VDD.
  • the first electrode connection electrode CE is used to connect the first light emitting device EL1 and the first pixel driving circuit DR1 or connect the first electrode E1 of the second light emitting device EL2 and the second pixel driving circuit DR2.
  • the shape of the data signal line DT may be a straight line whose main part extends along the column direction, and the data signal line TD is connected to the fourth connection electrode 14 through the data via hole V4. Since the fourth connection electrode 14 is connected to the first region of the active layer of the fourth transistor T4 through the via hole, the data signal line DT can write the data signal into the first electrode of the fourth transistor T4.
  • the first power signal line VDD may be in the shape of a zigzag line whose main body extends along the column direction, and the first power signal line VDD is connected to the fifth connection electrode 15 through the power via hole V3. Since the fifth connection electrode 15 is simultaneously connected to the second plate C2 and the first area of the active layer of the fifth transistor T5 through the via hole, it is realized that the first power signal line VDD writes the first power signal into the fifth transistor The first pole of T5, and make the second plate C2 and the first pole of the fifth transistor T5 have the same potential.
  • the third conductive layer SD1 includes a connection portion between the second electrode of the first transistor T1 and the gate electrode of the third transistor T3 (that is, the above-mentioned first connection electrode 11), and the first power supply
  • the signal line VDD further includes a protruding portion VDP, and the orthographic projection of the connecting portion (that is, the above-mentioned first connecting electrode 11 ) on the base substrate overlaps with the orthographic projection of the protruding portion VDP on the base substrate.
  • the orthographic projection of the connecting portion (that is, the above-mentioned first connecting electrode 11 ) on the base substrate is located within the orthographic projection of the protruding portion VDP on the base substrate.
  • the protruding portion VDP can shield the N1 node.
  • the third conductive layer SD1 only includes connection electrodes (first to sixth connection electrodes 11-16), which are used to transfer signals and jump wires, so a large area can be reserved
  • the interval D1 is convenient for other circuits or wiring, as shown in FIG. 12A .
  • the fourth conductive layer SD2 includes a first power signal line VDD and a data signal line DT at the same time.
  • the first power signal line VDD includes a protrusion VDP to shield the N1 point.
  • the data signal line DT is arranged on the fourth conductive layer SD2. Reduce signal transmission voltage drop, reduce charging time, and achieve high refresh rate display.
  • a second planar layer PLN2 is provided on the fourth conductive layer SD2, and a first connecting trace TL may be provided on the second planar layer PLN2. As shown in FIG. 15, the first connecting trace A third planarization layer PLN3 is disposed on the TL.
  • the first connection traces TL can be arranged in multiple functional layers, at this time, part of the first connection traces TL can be arranged on the second planar layer PLN2, and the part of the first connection traces A third planarization layer PLN3 is disposed on the TL, and another part of the first connection traces TL is disposed on the third planarization layer PLN3, and a fourth planarization layer is disposed on the other part of the first connection traces TL, and the fourth planarization layer Another part of the first connection traces TL is disposed on the planarization layer, and a fifth planarization layer PLN5 is disposed on the further part of the first connection traces TL.
  • first light emitting device EL1 and second light emitting device EL2 may be disposed on the fifth planarization layer PLN5.
  • An encapsulation layer EN is disposed on the first light emitting device EL1 and the second light emitting device EL2.
  • the material of the first connection trace TL can be transparent conductive material, such as transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), so as to further improve the light transmittance of the second display area 20 .
  • transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO)
  • the third conductive layer SD1 and the first planarization layer PLN1 of the display substrate are slightly different from the above embodiments.
  • the pattern of the fourth connection electrode 14 in the third conductive layer SD1 has a longer straight line portion; as shown in FIG. 16B, multiple The first via V1, multiple second vias V2, multiple power vias V3 and multiple data vias V4 are located on the same straight line, that is, on the first straight line L1;
  • FIG. 16C shows the fourth conductive layer A schematic diagram of the overlapping of SD2 and the first conductive layer SD1.
  • FIG. 16D shows a schematic diagram of the overlapping of the first connecting trace TL with the fourth conductive layer SD2 and the first conductive layer SD1.
  • the first connecting trace The extending direction of the line TL is parallel to the extending direction of the above-mentioned first straight line L1, and is the row direction of the plurality of first pixel driving circuits DR1 and the second pixel driving circuits DR2.
  • the base substrate BS may be a flexible substrate, or may be a rigid substrate.
  • Rigid substrates may include, but are not limited to, one or more of glass and quartz
  • flexible substrates may include, but are not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1 and the fourth conductive layer SD2 can use metal materials, such as titanium (Ti), copper (Cu), aluminum (Al) and molybdenum (Mo) Any one or more of them, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be single-layer structure, or multi-layer composite structure, such as Mo/Cu/Mo, etc. .
  • metal materials such as titanium (Ti), copper (Cu), aluminum (Al) and molybdenum (Mo) Any one or more of them, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first connection trace TL can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO/Ag/ITO and the like.
  • the first gate insulating layer GI1, the second gate insulating layer GI2 and the first interlayer insulating layer IDL can use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) , which can be single layer, multilayer or composite layer.
  • the planarization layers such as the first planarization layer PLN1 , the second planarization layer PLN2 and the third planarization layer PLN3 can be made of organic materials such as polyimide, resin and the like.
  • the semiconductor material layer ACT can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , Hexathiophene or polythiophene and other materials.
  • the first electrodes E1 of the first light-emitting device EL1 and the second light-emitting device EL2 can use transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or transparent metal oxides.
  • transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or transparent metal oxides.
  • the material of the second electrode E2 can be lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag) and other metal materials.
  • the embodiments of the present disclosure do not specifically limit the materials of the various functional layers on the display substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板和显示装置，该显示基板包括衬底基板（BS）、多个像素驱动电路（DR1/DR2）、第一平坦化层（PLN1）、多个发光器件（EL1/EL2）、第一电源信号线（VDD）以及数据信号线（DT），衬底基板（BS）包括第一显示区（10）和第二显示区（20），第一平坦化层（PLN1）包括将多个像素驱动电路（DR1/DR2）中的至少一个与多个发光器件（EL1/EL2）中的至少一个电连接的器件连接过孔（V1/V2）、将多个像素驱动电路（DR1/DR2）中的至少一个与第一电源信号线（VDD）电连接的电源过孔（V3）以及将多个像素驱动电路（DR1/DR2）中的至少一个与数据信号线DT电连接的数据过孔（V4），器件连接过孔（V1/V2）、电源过孔（V3）以及数据过孔（V4）沿第一方向排列。该显示基板具有更好的信赖性。

Description

显示基板和显示装置
本申请要求于2021年9月14日递交的PCT国际申请第PCT/CN2021/118279号的优先权以及于2022年3月24日递交的PCT国际申请第PCT/CN2022/082809号的优先权，在此全文引用上述专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、多个像素驱动电路、第一平坦化层、多个发光器件、第一电源信号线以及数据信号线，衬底基板包括第一显示区和第二显示区，其中，所述第一显示区至少部分围绕所述第二显示区，所述第二显示区的透光率大于所述第一显示区的透光率；多个像素驱动电路位于所述衬底基板上，且位于所述第一显示区；第一平坦化层位于所述多个像素驱动电路的远离所述衬底基板一侧；多个发光器件位于所述第一平坦化层的远离所述衬底基板一侧；第一电源信号线位于所述第一平坦化层的远离所述衬底基板一侧，且位于所述第一显示区；数据信号线位于所述第一平坦化层的远离所述衬底基板一侧，且位于所述第一显示区；其中，所述第一平坦化层包括将所述多个像素驱动电路中的至少一个与所述多个发光 器件中的至少一个电连接的器件连接过孔、将所述多个像素驱动电路中的至少一个与所述第一电源信号线电连接的电源过孔以及将所述多个像素驱动电路中的至少一个与所述数据信号线电连接的数据过孔，所述器件连接过孔、电源过孔以及数据过孔沿第一方向排列。
例如，本公开至少一实施例提供的显示基板还包括：第一初始化信号线，配置为向多个像素驱动电路中的至少一个提供第一初始化信号；其中，所述器件连接过孔、所述电源过孔以及所述数据过孔与所述第一初始化信号线的最短距离基本相等。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路包括第一像素驱动电路和第二像素驱动电路，所述多个发光器件包括位于所述第一显示区的第一发光器件和位于所述第二显示区的第二发光器件，所述器件连接过孔包括第一过孔和第二过孔，所述第一发光器件通过所述第一过孔与所述第一像素驱动电路电连接，所述第二发光器件通过位于所述第一显示区和所述第二显示区的第一连接走线与所述第二像素驱动电路电连接，并且在所述第一显示区，所述第一连接走线通过所述第二过孔与所述第二像素驱动电路电连接。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路包括沿第一方向延伸且沿第二方向排布的多个像素电路组，所述多个像素电路组中的至少一组包括多个第一像素驱动电路和多个第二像素驱动电路，所述多个第一像素驱动电路和所述多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔沿所述第一方向排列，所述第一方向和所述第二方向交叉。
例如，本公开至少一实施例提供的显示基板中，所述至少一组像素电路组中的多个第一像素驱动电路和多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔与所述第一初始化信号线的最短距离基本相同。
例如，本公开至少一实施例提供的显示基板中，所述至少一组像素电路组中的多个第一像素驱动电路和多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔位于同一直线上，所述同一直线沿所述第一方向延伸。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底 基板的方向上，所述第一连接走线位于所述同一直线的至少一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一连接走线从所述第一显示区到所述第二显示区的延伸方向平行于所述第一方向。
例如，本公开至少一实施例提供的显示基板中，所述第一像素驱动电路和所述第二像素驱动电路分别包括作为复位晶体管的第一晶体管、作为补偿晶体管的第二晶体管和作为驱动晶体管的第三晶体管，所述第一晶体管的栅电极与复位信号线连接，所述第一晶体管的第一极与第一初始化信号线连接，所述第一晶体管的第二极分别与所述第二晶体管的第一极和所述第三晶体管的栅电极连接，所述第二晶体管的栅电极与扫描信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；所述第一晶体管的栅电极、所述第二晶体管的栅电极、所述第三晶体管的栅电极、所述扫描信号线与所述复位信号线位于所述衬底基板上的第一导电层；所述第一初始化信号线位于第二导电层，所述第二导电层位于所述第一导电层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一像素驱动电路和所述第二像素驱动电路还分别包括存储电容、作为数据写入晶体管的第四晶体管和作为发光控制晶体管的第五晶体管，所述第四晶体管的栅电极与扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第三晶体管的第一极连接，所述第五晶体管的栅电极与发光控制线连接，所述第五晶体管的第一极与所述存储电容的第二极板连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接；所述发光控制线位于所述第一导电层。
例如，本公开至少一实施例提供的显示基板中，所述第一像素驱动电路和所述第二像素驱动电路还分别包括作为发光控制晶体管的第六晶体管以及作为复位晶体管的第七晶体管，所述第六晶体管的栅电极与所述发光控制线连接，所述第六晶体管的第一极与所述第三晶体管的第二极连接，所述第一发光器件或者所述第二发光器件与所述第六晶体管的第二极连接，所述第七晶体管的栅电极与复位信号线连接，所述第七晶体管的第一极与第二初始化信号线连接，所述第七晶体管的第二极与所述第六晶体管的第二极连接；所述第二初始化信号线位于所述第二导电层。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的第一方向上，用于同一第一像素驱动电路或第二像素驱动电路的所述第二初始化信号线、所述复位信号线、所述第一初始化信号线以及所述扫描信号线依次排布。
例如，本公开至少一实施例提供的显示基板中，所述第二晶体管包括有源层以及两个栅电极，所述有源层位于所述第一金属层与所述衬底基板之间的半导体材料层，所述有源层包括第一部分，所述第一部分在所述衬底基板上的正投影与所述两个栅电极在所述衬底基板上的正投影不交叠，所述第二导电层包括遮挡图案，所述第一部分在所述衬底基板上的正投影与所述遮挡图案在所述衬底基板上的正投影交叠。
例如，本公开至少一实施例提供的显示基板中，所述遮挡图案与所述第一初始化信号线一体连接。
例如，本公开至少一实施例提供的显示基板中，所述半导体材料层包括连接所述第二晶体管的有源层和所述第一晶体管的有源层的半导体图案，所述半导体图案在所述衬底基板上的正投影与所述遮挡图案在所述衬底基板上的正投影交叠。
例如，本公开至少一实施例提供的显示基板中，所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第三晶体管的第一极和第二极位于第三导电层，所述第三导电层位于所述第二导电层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一电源信号线位于第四导电层，所述第四导电层位于所述第三导电层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述数据信号线位于所述第四导电层。
例如，本公开至少一实施例提供的显示基板中，所述第三导电层还包括位于所述第一晶体管的第二极和所述第三晶体管的栅电极之间的连接部，所述第一电源信号线还包括突出部，所述连接部在所述衬底基板上的正投影与所述突出部在所述衬底基板上的正投影交叠。
例如，本公开至少一实施例提供的显示基板中，所述连接部在所述衬底基板上的正投影位于所述突出部在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，位于相邻两行的第一像素驱动电路和第二像素驱动电路的第三导电层的图案的间隔为7.0微米-10.0微米。
例如，本公开至少一实施例提供的显示基板中，位于同一行的多个第一像素驱动电路和多个第二像素驱动电路中，每相邻的两个第二像素驱动电路之间设置两个第一像素驱动电路。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板的平面示意图；
图2为图1中的显示基板沿B-B线的截面示意图；
图3为图1中的显示基板沿A-A线的截面示意图；
图4为本公开至少一实施例提供的显示基板中第一显示区和第二显示区的部分平面示意图；
图5为本公开至少一实施例提供的显示基板的部分功能层的平面示意图；
图6为本公开至少一实施例提供的另一显示基板的部分功能层的平面示意图；
图7为本公开至少一实施例提供的显示基板的第一像素驱动电路的电路图；
图8为本公开至少一实施例提供的显示基板的第二像素驱动电路的电路图；
图9-图15为本公开至少一实施例提供的显示基板的各个功能层的平面示意图以及各个功能层依次交叠的平面示意图；以及
图16A-图16D为本公开至少一实施例提供的另一显示基板的部分功能层的平面示意图以及该部分功能层依次交叠的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，全面屏或窄边框等产品以其较大的屏占比和超窄边框，已逐步成为显示产品的发展趋势。对于智能终端等产品，通常需要设置前置摄像头、指纹传感器或光线传感器等硬件，为提高屏占比，全面屏或窄边框产品通常采用屏下摄像头技术(Full display with camera，简称FDC)或者屏下指纹技术，将摄像头等传感器放置于显示基板的屏下摄像区域(Under Display Camera，简称UDC)，屏下摄像区域不仅具有一定的透过率，而且具有显示功能，由此实现摄像头区全显示(Full Display in Camera，简称FDC)。
为了提高屏下摄像区域的光透过率，屏下摄像区域设置的显示子像素通常只包括发光器件，驱动发光器件的像素驱动电路可以设置在其他显示区域，以避免像素驱动电路设置在屏下摄像区域中而降低屏下摄像区域的光透过率。在上述方案中，发光器件需要通过较长的走线连接到设置在其他显示区域的像素驱动电路，该较长的走线往往具有较大的电阻，造成压降现象，并且该较长的走线还可能与显示基板上的其他电路图案形成寄生电容，影响显示基板的电信号传输；另一方面，在显示基板的高刷新率下，屏下摄像区域设置的显示子像素的充电时间往往不够，因此影响发光器件的发光亮度； 再一方面，为了电路之间的电连接，显示基板中通常具有许多过孔，这些过孔上方的电路或者走线在过孔的位置容易形成凹陷，进而造成断路等不良，因此降低了显示基板的信赖性。
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、多个像素驱动电路、第一平坦化层、多个发光器件、第一电源信号线以及数据信号线，衬底基板包括第一显示区和第二显示区，其中，第一显示区至少部分围绕第二显示区，第二显示区的透光率大于第一显示区的透光率；多个像素驱动电路位于衬底基板上，且位于第一显示区；第一平坦化层位于多个像素驱动电路的远离衬底基板一侧；多个发光器件位于第一平坦化层的远离衬底基板一侧；第一电源信号线位于第一平坦化层的远离衬底基板一侧，且位于第一显示区；数据信号线位于第一平坦化层的远离衬底基板一侧，且位于第一显示区；其中，第一平坦化层包括将多个像素驱动电路中的至少一个与多个发光器件中的至少一个电连接的器件连接过孔、将多个像素驱动电路中的至少一个与第一电源信号线电连接的电源过孔以及将多个像素驱动电路中的至少一个与数据信号线电连接的数据过孔，器件连接过孔、电源过孔以及数据过孔沿第一方向排列。
在本公开实施例提供的上述显示基板中，第一平坦化层上设置有多种走线、电路图案，通过将第一平坦化层所具有的多个过孔沿第一方向排列，可以使多个过孔的排布空间更紧凑且规律，从而便于第一平坦化层上设置的多种走线、电路图案避让这些过孔，以避免这些走线或者电路图案在过孔的位置产生塌陷，造成短路等不良现象，从而提高这些走线以及电路图案的稳定性，进而提高显示基板的信赖性。
下面，通过举个具体的实施例来详细介绍本公开实施例提供的显示基板。
本公开至少一实施例提供一种显示基板，图1示出了该显示基板的平面示意图，图2示出了图1中的显示基板沿B-B线的截面示意图，图3示出了图1中的显示基板沿A-A线的截面示意图，图4示出了图1中的显示基板在第一显示区和第二显示区的部分平面示意图。如图1-图4所示，该显示基板包括衬底基板BS、多个像素驱动电路DR1/DR2、第一平坦化层PLN1、多个发光器件EM1/EM2、第一电源信号线VDD 以及数据信号线DT等结构。衬底基板BS包括第一显示区10和第二显示区20，第一显示区10至少部分围绕第二显示区20，图1中示出为第一显示区10完全部分围绕第二显示区20，在其他实施例中，也可以第一显示区10部分围绕第二显示区20。
第二显示区20的透光率大于第一显示区10的透光率。例如，第二显示区20可以为显示基板的透光显示区，可以透光一些光信号。
例如，多个像素驱动电路DR1/DR2位于衬底基板BS上，且位于第一显示区10，第一平坦化层PLN1位于多个像素驱动电路DR1/DR2的远离衬底基板一侧BS，多个发光器件EM1/EM2位于第一平坦化层PLN1的远离衬底基板BS的一侧；第一电源信号线VDD位于第一平坦化层PLN1的远离衬底基板BS一侧，且位于第一显示区10；数据信号线DT位于第一平坦化层PLN1的远离衬底基板110一侧，且位于第一显示区10。
参考图6，第一平坦化层PLN1包括将多个像素驱动电路DR1/DR2中的至少一个(例如每个)与多个发光器件EM1/EM2中的至少一个
(例如每个)电连接的器件连接过孔V1/V2、将多个像素驱动电路中的至少一个(例如每个)与第一电源信号线VDD电连接的电源过孔V3以及将多个像素驱动电路中的至少一个(例如每个)与数据信号线DT电连接的数据过孔V4，器件连接过孔V1/V2、电源过孔V3以及数据过孔V4沿第一方向(例如图6中的水平方向)排列。
例如，参考图12B等，显示基板还包括第一初始化信号线Vin1，第一初始化信号线Vin1配置为向多个像素驱动电路DR1/DR2中的至少一个提供第一初始化信号；器件连接过孔V1/V2、电源过孔V3以及数据过孔V4与第一初始化信号线Vin1的最短距离基本相等，也即，器件连接过孔V1/V2、电源过孔V3以及数据过孔V4设置在与第一初始化信号线Vin1距离基本相同的位置上。例如，第一初始化信号线Vin1沿上述第一方向延伸。
由此，多个第一过孔V1、多个第二过孔V2以及多个电源过孔V3、多个数据过孔V4的排布空间更紧凑且规律，从而便于第一平坦化层PLN1上设置有多种走线(例如第一连接走线TL)、电路图案避让这些过孔，提高这些走线以及电路图案的稳定性，进而提高显示基板的信赖性。
例如，在图1的实施例中，第二显示区20为圆形，在其他实施例 中，第二显示区20也可以为矩形、三角形或者椭圆形等其他图形。例如，在第二显示区20的形状为圆形时，圆形的直径可以约为3mm至5mm；在第二显示区20的形状为矩形时，矩形的长边长和端边长可以约为3mm至5mm，本公开的实施例对第二显示区20的具体形状和尺寸不做限定。
例如，多个像素驱动电路包括多个第一像素驱动电路DR1和多个第二像素驱动电路DR2，多个发光器件包括位于第一显示区10的第一发光器件EM1和位于第二显示区20的第二发光器件EM2，器件连接过孔包括第一过孔V1和第二过孔V2，第一发光器件EM1通过第一过孔V1与第一像素驱动电路DR1电连接，第二发光器件EM2通过位于第一显示区10和第二显示区20的第一连接走线TL与第二像素驱动电路DR2电连接，并且在第一显示区10，第一连接走线TL通过第二过孔V2与第二像素驱动电路DR2电连接。
例如，如图2和图3所示，第一显示区10被配置为进行图像显示，包括多个第一像素驱动电路DR1和多个第二像素驱动电路DR2、第一平坦化层PLN1以及多个第一发光器件EL1；多个第一像素驱动电路DR1和多个第二像素驱动电路DR2排布为多行多列，如图4所示，行方向例如为图中的水平方向，列方向为图中的竖直方向。第一平坦化层PLN1设置在多个第一像素驱动电路DR1和多个第二像素驱动电路DR2的远离衬底基板BS一侧。多个第一发光器件EL1设置在第一平坦化层PLN1的远离衬底基板BS一侧。
例如，第一像素驱动电路DR1和第二像素驱动电路DR2分别包括晶体管和存储电容C等组成的2T1C结构(也即包括两个晶体管和一个存储电容)、3T1C结构、7T1C结构或者8T2C结构等，本公开的实施例对第一像素驱动电路DR1和第二像素驱动电路DR2的具体形式不做限定。例如，图2和图3中示出为驱动晶体管，例如为后续详细介绍的7T1C结构中的第三晶体管T3。
例如，如图2和图3所示，第一像素驱动电路DR1和第二像素驱动电路DR2中的第三晶体管T3包括有源层T3a、栅电极T3g、第一极T3s和第二极T3d。存储电容C包括第一极板C1和第二极板C2。例如，栅电极T3g和第一极板C1设置在第一导电层Gate1(后续详细介绍)， 第二极板C2设置在位于第一导电层远离衬底基板一侧的第二导电层Gate2(后续详细介绍)，第一极T3s和第二极T3d设置在位于第二导电层远离衬底基板一侧的第三导电层SD1(后续详细介绍)。
例如，有源层T3a与栅电极T3g之间设置有第一栅绝缘层GI1，第一极板C1和第二极板C2之间设置有第二栅绝缘层GI2，第二极板C2与第一极T3s和第二极T3d之间设置有层间绝缘层IDL。例如，有源层T3a包括沟道区以及位于沟道区两侧的第一区和第二区，第一区和第二区的半导体材料被导体化，第一极T3s和第二极T3d分别通过第一栅绝缘层GI1和第二栅绝缘层GI2中的过孔与有源层T3a的第一区和第二区分别连接。
例如，第一发光器件EL1和第二发光器件EL2可以分别通过连接电极CE与第一像素驱动电路DR1和第二像素驱动电路DR2电连接，连接电极CE设置在位于第三导电层远离衬底基板一侧的第四导电层SD2(后续详细介绍)。
例如，第一发光器件EL1和第二发光器件EL2可以是OLED，包括叠设的第一电极E1(例如阳极)、有机发光层E2和第二电极E3(例如阴极)，参考图2和图3；或者，第一发光器件EL1和第二发光器件EL2也可以是QLED，包括叠设的第一电极E1(例如阳极)、量子点层E2和第二电极E3(例如阴极)。例如，在一些实施例中，第一发光器件EL1和第二发光器件EL2的第二电极E3可以是显示基板上连续设置的面电极。
例如，第一发光器件EL1和第二发光器件EL2上设置有封装层EN，例如，封装层EN可以包括叠设的第一封装层、第二封装层和第三封装层(图中未示出)，第一封装层和第三封装层可以采用无机材料，例如氧化硅、氮化硅或者氮氧化硅等，第二封装层可以采用有机材料，例如聚酰亚胺、树脂等，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入第一发光器件EL1和第二发光器件EL2中。
例如，图6示出了图1中的显示基板的部分功能层的平面示意图，如图2、图3和图6所示，第一平坦化层PLN1包括多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4，多个第一发光器件EL1分别通过多个第一过孔V1(例如第一过孔V1中设置的 第一电极连接电极CE)与多个第一像素驱动电路DR1电连接，例如与第三晶体管的第一极或者第二极电连接。由此，多个第一发光器件EL1采用“原位”驱动的方式进行驱动，如图3所示。
如图2、图4和图6所示，第二显示区20被配置为进行图像显示和透过光线，包括多个第二发光器件EL2，多个第二发光器件EL2分别通过在第一显示区10和第二显示区20延伸的多条第一连接走线TL与多个第二像素驱动电路DR2电连接，例如与第三晶体管的第一极或者第二极电连接，并且在第一显示区10，多条第一连接走线TL分别通过多个第二过孔V2(例如通过第二过孔V2中设置的第一电极连接电极CE)与多个第二像素驱动电路DR2电连接。由此，多个第二发光器件EL2采用“远程”驱动的方式进行驱动，如图2所示。
需要注意的是，本公开的实施例，一个结构通过过孔与另一个结构电连接指的是，该一个结构直接通过该过孔与该另一个结构电连接，或者，该一个结构间接地通过该过孔中设置的连接结构与该另一个结构电连接，只要该一个结构与该另一结构的电连接通过该过孔实现即可。
例如，在一些实施例中，如图1所述，显示基板还可以包括第三显示区30，第三显示区30为显示基板的主体显示区，也包括多个第一像素驱动电路DR1和多个第二像素驱动电路DR2，且包括多个第三发光光器件，第三显示区30中的多个第一像素驱动电路DR1分别与多个第三发光器件电连接以驱动该多个第三发光器件，但是，与第二显示区20不同的是，第三显示区30中的第二像素驱动电路DR2不连接发光器件。
例如，如图6所示，第一电源信号线VDD通过多个电源过孔V3与多个第一像素驱动电路DR1和多个第二像素驱动电路DR2电连接，以向第一像素驱动电路DR1和多个第二像素驱动电路DR2提高电源信号，例如高电平信号。
例如，如图6所示，多个像素驱动电路包括沿第一方向(图中的水平方向)延伸且沿第二方向(例如图中的竖直方向)排布的多个像素电路组G(例如像素驱动电路行，图中示出一组/一行作为示例)，多个像素电路组G中的至少一组包括多个第一像素驱动电路DR1和多个第二像素驱动电路DR2，该多个第一像素驱动电路DR1和多个第二像素 驱动电路DR2所采用的多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4沿第一方向排列，第一方向和第二方向交叉。
例如，至少一组像素电路组G中的多个第一像素驱动电路DR1和多个第二像素驱动电路DR2所采用的多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4与第一初始化信号线Vin1的最短距离基本相同。
例如，至少一组像素电路组G中的多个第一像素驱动电路DR1和多个第二像素驱动电路DR2所采用的多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4位于同一直线L1上，该同一直线L1沿第一方向延伸。
由此，多个第一过孔V1、多个第二过孔V2以及多个电源过孔V3、多个数据过孔V4的排布空间更紧凑且规律，从而便于第一平坦化层PLN1上设置有多种走线(例如第一连接走线TL)、电路图案避让这些过孔，提高这些走线以及电路图案的稳定性，进而提高显示基板的信赖性。
例如，在本公开的实施例中，多个过孔位于同一直线上指的是，可以采用同一直线依次穿过该多个过孔，例如穿过每个过孔的任意位置，而不仅仅局限于穿过多个过孔的中心。当然，在一些实施例中，多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4的中心可以位于同一直线L1上，以在最大程度上规律多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4的排列。
例如，在一些实施例中，在平行于衬底基板BS的方向上，多条第一连接走线TL位于上述同一直线(也即第一直线L1)的至少一侧。例如，多条第一连接走线TL位于每相邻的两行第一像素驱动电路DR1和第二像素驱动电路DR2所采用的多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4所在的直线L1之间。
例如，在一些实施例中，多条第一连接走线TL从第一显示区10到第二显示区20的延伸方向(也即图中的水平方向)平行于上述同一直线(也即第一直线L1)，例如沿第一方向延伸，由此在垂直于衬底基板的方向上，多条第一连接走线TL不会与该第一直线L1上设置的 多个第一过孔V1、多个第二过孔V2以及多个电源过孔V3、多个数据过孔V4交叠，进而避免多条第一连接走线TL设置在过孔上方导致多条第一连接走线TL出现短路、断路等不良。
例如，在一些显示基板中，如图5所示，数据信号线DT通过多个数据过孔V4与多个第一像素驱动电路DR1和多个第二像素驱动电路DR2电连接。多个数据过孔V4在衬底基板BS上的正投影位于相邻的两条第一连接走线TL在衬底基板BS上的正投影之间。在图5中，第一像素驱动电路DR1和第二像素驱动电路DR2所采用的多个第一过孔V1、多个第二过孔V2和多个电源过孔V3位于第一直线L1上，第一像素驱动电路DR1和第二像素驱动电路DR2所采用的多个数据过孔V4位于不同于第一直线L1的第二直线L2上。
相比于图5的实施例，在图6的实施例中，位于同一组(例如同一行)的第一像素驱动电路DR1和第二像素驱动电路DR2上的第一平坦化层PLN1中的多个过孔集中在同一直线上，由此可以进一步节省过孔的排布空间，并使多条第一连接走线TL充分避让第一平坦化层PLN1中的多个过孔，从而提高多条第一连接走线TL的信赖性。
例如，图7示出了第一像素驱动电路DR1的电路图，图8示出了第二像素驱动电路DR2的电路图，如图7和图8所示，第一像素驱动电路DR1和第二像素驱动电路DR2分别包括作为复位晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2和作为驱动晶体管的第三晶体管T3，第一晶体管T1的栅电极与复位信号线Res连接，第一晶体管T1的第一极与第一初始化信号线Vin1连接，第一晶体管T1的第二极分别与第二晶体管T2的第一极、第三晶体管T3的栅电极以及存储电容C的第一极板C1连接，第二晶体管T2的栅电极与扫描信号线Gate连接，第二晶体管T2的第二极与第三晶体管T2的第二极连接。
例如，第一晶体管T1的第二极、第三晶体管T3的栅电极以及存储电容C的第一极板C1在节点N1交汇。
例如，第一晶体管T1的栅电极、第二晶体管T2的栅电极、第三晶体管T3的栅电极、存储电容C的第一极板C1、扫描信号线Gate与复位信号线Res位于衬底基板BS上的第一导电层，后文也称为Gate1层。第一初始化信号线Vin1位于第二导电层，后文也称为Gate2层， 第二导电层位于第一导电层的远离衬底基板BS的一侧。
例如，如图7和图8所示，第一像素驱动电路DR1和第二像素驱动电路DR2还分别包括存储电容C、作为数据写入晶体管的第四晶体管T4和作为发光控制晶体管的第五晶体管T5，第四晶体管T4的栅电极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线DT连接，第四晶体管T4的第二极与第三晶体管T3的第一极连接，第五晶体管T5的栅电极与发光控制线EM连接，第五晶体管T5的第一极与存储电容C的第二极板C2连接，且第五晶体管T5的第一极和存储电容C的第二极板C2与第一电源信号线VDD连接，第五晶体管T5的第二极与第三晶体管T3的第一极连接。
例如，第四晶体管T4的第二极、第三晶体管T3的第一极以及第五晶体管T5的第二极在节点N2交汇。
例如，第四晶体管T4的栅电极、第五晶体管T5的栅电极以及发光控制线EN位于第一导电层。
例如，如图7和图8所示，第一像素驱动电路DR1和第二像素驱动电路DR2还分别包括作为发光控制晶体管的第六晶体管T6以及作为复位晶体管的第七晶体管T7，第六晶体管T6的栅电极与发光控制线EM连接，第六晶体管T6的第一极与第三晶体管T3的第二极连接，第一发光器件EL1或者第二发光器件EL2的第一电极与第六晶体管T6的第二极连接，第七晶体管T7的栅电极与复位信号线Res连接，第七晶体管T7的第一极与第二初始化信号线Vin2连接，第七晶体管T7的第二极与第六晶体管T6的第二极连接。
例如，第六晶体管T6的第一极与第三晶体管T3的第二极在节点N3交汇。第六晶体管T6的第二极以及第七晶体管T7的第二极在节点N4交汇。
例如，第一发光器件EL1和第二发光器件EL2的第二电极与第二电源线VSS连接。例如，第二电源线VSS传输的信号为低电平信号，第一电源信号线VDD传输的信号为高电平信号。
由此，图7和图8所示的实施例中，第一像素驱动电路DR1和第二像素驱动电路DR2形成为7T1C结构(即包括七个晶体管和一个存储电容)。
例如，第六晶体管T6的栅电极、第七晶体管T7的栅电极位于第一导电层，存储电容C的第二极板C2以及第二初始化信号线Vin2位于第二导电层。
例如，第一晶体管T1的第一极和第二极、第二晶体管T2的第一极和第二极、第三晶体管T3的第一极和第二极、第四晶体管T4的第一极和第二极、第五晶体管T5的第一极和第二极、第六晶体管T6的第一极和第二极位于以及第七晶体管T7的第一极和第二极位于第三导电层(也称为SD1层)，第三导电层位于第二导电层的远离衬底基板BS的一侧。
在本公开的实施例中，第一极可以为晶体管的漏电极、第二极可以为晶体管的源电极，或者第一极可以为晶体管的源电极、第二极可以为晶体管的漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。
例如，上述第一电源信号线VDD位于第四导电层(也称为SD2层)，第四导电层位于第三导电层的远离衬底基板BS的一侧。例如，数据信号线DT也位于第四导电层。
例如，在图2和图3示出的第一像素驱动电路DR1和第二像素驱动电路DR2中，与第一发光器件EL1和第二发光器件EL2连接的薄膜晶体管为上述第三晶体管T3。
例如，第一像素驱动电路DR1和第二像素驱动电路DR2的上述电路结构均相同，不同点在于，如图8所示，由于第二发光器件EL2通过在第一显示区10和第二显示区20延伸的较长的第一连接走线TL连接至第二像素驱动电路DR2，相当于在第六薄膜晶体管T6和第七薄膜晶体管交汇的节点N4与第二发光器件EL2之间串联了一个电阻R-TL且并联了一个电容C-TL。
例如，在本公开的实施例中，如图4-图6所示，位于同一行的多个第一像素驱动电路DR1和多个第二像素驱动电路DR2中，每相邻的两个第二像素驱动电路DR2之间设置两个第一像素驱动电路DR1。也即，在第一显示区10中，每两个第一像素驱动电路DR1和一个第二像素驱动电路DR2构成一个重复单元，多个重复单元在第一显示区10中周期排列。
由此，用于连接多个第二发光器件EL2的多个第二像素驱动电路DR2设置在靠近第二显示区20的位置，从而第一连接走线TL的长度被充分减小，进而减弱甚至消除节点N4与第二发光器件EL2之间的电阻R-TL和电容C-TL，并且解决第二显示区20中的第二发光器件EL2的发光亮度偏暗以及高频下充电时间不够等问题；另一方面，第一连接走线TL经过的第一像素驱动电路DR1的数量减少，从而也可以减小第一连接走线TL在第一像素驱动电路DR1中出现断路等不良问题。
例如，在一些实施例中，上述第一晶体管T1至第七晶体管T7可以是薄膜晶体管，例如是P型薄膜晶体管，或者可以是N型薄膜晶体管。第一像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。
例如，在一些实施例中，第一晶体管T1至第七晶体管T7可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
例如，以第一晶体管T1至第七晶体管T7均为P型薄膜晶体管为例，第一像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线Res的信号为导通信号，扫描信号线Gate和发光信号线EM的信号为断开信号。复位信号线Res的导通信号使第一晶体管T1导通，第一初始化信号线Vin1的信号通过第一晶体管T1提供至第一节点N1，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。复位信号线Res的导通信号使第七晶体管T7导通，第二初始化信号线Vin2的信号通过第七晶体管T7提供至第一发光器件EL1或者第二发光器件EL2的第一电极，对第一发光器件EL1或者第二发光器件EL2的第一电极进行初始化(复位)，清空其 内部的预存电压，完成初始化。扫描信号线Gate和发光信号线EM的断开信号使第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6断开，此阶段第一发光器件EL1或者第二发光器件EL2不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为导通信号，复位信号线Res和发光信号线EM的信号为断开信号，数据信号线DT输出数据电压。此阶段由于存储电容C的第一极板为低电平，因此第三晶体管T3导通。扫描信号线Gate的导通信号使第二晶体管T2和第四晶体管T4导通，数据信号线DT输出的数据电压经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线DT输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第一极板(第一节点N1)的电压为Vd-|Vth|，Vd为数据信号线DT输出的数据电压，Vth为第三晶体管T3的阈值电压。复位信号线Res的断开信号使第一晶体管T1和第七晶体管T7断开，发光信号线EM的断开信号使第五晶体管T5和第六晶体管T6断开。
第三阶段A3，称为发光阶段，发光信号线EM的信号为导通信号，扫描信号线Gate和复位信号线Res的信号为断开信号。发光信号线EM的导通信号使第五晶体管T5和第六晶体管T6导通，第一电源信号线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向第一发光器件EL1或者第二发光器件EL2的第一电极提供驱动电压，驱动第一发光器件EL1或者第二发光器件EL2发光。
在第一像素驱动电路DR1和第二像素驱动电路DR2驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动第一发光器件EL1或者第二发光器件EL2的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源信号线VDD输出的电源电压。
例如，图9-图15示出了图5示出的实施例中显示基板的各个功能层的平面示意图。
图9示出了设置在衬底基板上的半导体层ACT的平面示意图。如图9所示，半导体层ACT包括第一晶体管T1的有源层T1a、第二晶体管T2的有源层T2a、第三晶体管T3的有源层T3a、第四晶体管T4的有源层T4a、第五晶体管T5的有源层T5a、第六晶体管T6的有源层T6a以及第七晶体管T7的第七有源层T7a。
例如，这些晶体管的有源层为相互连接的一体结构，例如，每列像素驱动电路中，第M行像素驱动电路的第六晶体管T6的有源层T6a与第M+1行像素驱动电路的第七晶体管T7的第七有源层T7a相互连接，即每列像素驱动电路中相邻的像素驱动电路的半导体层为相互连接的一体结构。
例如，第一晶体管T1的有源层T1a的形状可以呈“n”字形，第二晶体管T2的有源层T2a的形状可以呈“L”字形，第三晶体管T3的有源层T3a的形状可以呈“Ω”字形，第四晶体管T4的有源层T4a、第五晶体管T5的有源层T5a、第六晶体管T6的有源层T6a以及第七晶体管T7的第七有源层T7a的形状可以呈“I”字形。
例如，每个晶体管的有源层可以包括沟道区以及位于沟道区两侧的第一区和第二区，第一区和第二区具有导电性，分别用于与每个晶体管的第一极和第二极电连接。
例如，参考图2和图3，半导体层ACT上形成有第一栅绝缘层GI1，这里不再赘述。
图10A示出了设置在半导体层上的第一导电层Gate1的平面示意图，图10B示出了第一导电层Gate1与半导体层ACT交叠的平面示意图。如图10A和图10B所示，每个第一像素驱动电路和每个第二像素驱动电路的第一导电层Gate1的图案至少包括复位信号线Res、扫描信号线Gate、发光控制线EM和存储电容C的第一极板C1。
例如，存储电容C的第一极板C1的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板C1在衬底基板上的正投影与第三晶体管T3的有源层在衬底基板上的正投影至少部分交叠。例如，存储电容C的第一极板C1可以同时作为第三晶体管T3的栅电极。
例如，复位信号线Res、扫描信号线Gate和发光控制线EM的形状可以是主体部分沿着像素驱动电路的行方向延伸的线形状。
如图10B所示，扫描信号线Gate与第二晶体管T2的有源层相重叠的区域可以作为第二晶体管T2的栅电极T2g，扫描信号线Gate设置有向复位信号线Res一侧凸起的突出部，突出部在衬底基板上的正投影与第二晶体管T2的有源层在衬底基板上的正投影至少部分交叠，由此形成双栅结构的第二晶体管T2。
例如，扫描信号线Gate与第四晶体管T4的有源层相重叠的区域作为第四晶体管T4的栅电极T4g，复位信号线Res与第一晶体管的有源层相重叠的区域作为双栅结构的第一晶体管T1的栅电极T1g，复位信号线Res与第七晶体管T7的有源层相重叠的区域作为第七晶体管T7的栅电极T7g，发光控制线EM与第五晶体管T5的有源层相重叠的区域作为第五晶体管T5的栅电极T5g，发光控制线EM与第六晶体管T6的有源层相重叠的区域作为第六晶体管T6的栅电极T6g。
例如，参考图2和图3，第一导电层Gate1上形成有第二栅绝缘层GI2，这里不再赘述。
图11A示出了设置在第一导电层Gate1上的第二导电层Gate2的平面示意图，图11B示出了第二导电层Gate2与第一导电层Gate1和半导体层ACT交叠的平面示意图。如图11A和图11B所示，每个第一像素驱动电路和每个第二像素驱动电路的第二导电层Gate2的图案至少包括第一初始化信号线Vin1、第二初始化信号线Vin2、存储电容C的第二极板C2以及遮挡图案SH。
例如，如图11B所示，第二晶体管T2的有源层在其两个栅电极之间具有第一部分P1，第一部分P1在衬底基板上的正投影与该两个栅电极在衬底基板上的正投影不交叠，第一部分P1在衬底基板上的正投影与遮挡图案SH(例如遮挡图案SH的第一遮挡部SH1)在衬底基板上的正投影交叠。由此，遮挡图案SH可以为第二晶体管T2的有源层实现遮挡、稳压的作用。
例如，遮挡图案SH的形状可以为折线状，遮挡图案SH与第一初始化信号线Vin1一体连接，从而遮挡图案SH可以从第一初始化信号线Vin1获取恒压信号，以充分达到稳压的作用。
例如，如图11B所示，半导体材料层ACT包括连接第二晶体管T2的有源层和第一晶体管T1的有源层的半导体图案P2，半导体图案P2在衬底基板上的正投影与遮挡图案SH(例如遮挡图案SH的第二遮挡部SH2)在衬底基板上的正投影交叠。
由此，遮挡图案SH还可以屏蔽数据电压跳变对关键节点(例如N1节点)的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，达到稳压的效果。
例如，存储电容C的第二极板C2可以位于扫描信号线Gate和发光控制线EM之间，行方向上相邻的第二极板C2可以电连接，以保证处于同一行中的多个第二极板C2具有相同的电位，由此有利于提高显示基板的均一性，进而提高显示基板的显示效果。
例如，第二极板C2的轮廓可以为矩形，矩形的角部可以设置倒角，第二极板C2在衬底基板上的正投影与第一极板C1在衬底基板上的正投影至少部分交叠，以构成像素驱动电路的存储电容C。第二极板C2上设置有开口，开口可以位于第二极板C2的中部。开口可以为矩形，使第二极板C2形成环形结构。例如，该开口被配置为容置后续形成的连接过孔，连接过孔位于开口内并暴露出第一极板C1，使后续形成的第一晶体管T1的第二极通过该连接过孔与第一极板C1连接。
例如，第一初始化信号线Vin1和第二初始化信号线Vin2的形状可以是主体部分沿着行方向延伸的线形。
例如，如图11B所示，在平行于衬底基板的第一方向上，也即图中的列方向上，用于同一第一像素驱动电路DR1或第二像素驱动电路DR2的第二初始化信号线Vin2、复位信号线Res、第一初始化信号线Vin1以及扫描信号线Gate依次排布。由此，第一导电层Gate1和第二导电层Gate2中的信号线交替排布，以避免同一导电层中的信号线过于密集而产生信号串扰、短路等不良。
例如，参考图2和图3，第二导电层Gate2上形成有层间绝缘层IDL，这里不再赘述。
图12A示出了设置在第二导电层Gate2上的第三导电层SD1的平面示意图，图12B示出了第三导电层SD1与第二导电层Gate2、第一导电层Gate1和半导体层ACT交叠的平面示意图。如图12A和图12B所 示，每个第一像素驱动电路和每个第二像素驱动电路的第三导电层SD1的图案至少包括第一连接电极11、第二连接电极12、第三连接电极13、第四连接电极14、第五连接电极15和第六连接电极16。
例如，第一连接电极11的形状可以为主体部分沿着列方向延伸的条形状，第一连接电极11的第一端通过过孔与第一极板C1连接，第一连接电极11的第二端通过过孔与第一晶体管T1的有源层的第二区(也是第二晶体管T1的有源层的第一区)连接，使第一极板C1、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。例如，第一连接电极41可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极。
例如，第二连接电极12的形状可以为沿着行方向延伸的条形状，第二连接电极12的第一端通过过孔与第一晶体管的有源层的第一区连接，第二连接电极12的第二端通过过孔与第一初始化信号线Vin1连接。例如，第二连接电极12可以作为第一晶体管T1的第一极，实现了第一初始化信号线Vin1将第一初始信号写入第一晶体管T1。
例如，第三连接电极13的形状可以为折线形，第三连接电极13的第一端通过过孔与第七晶体管的有源层的第一区连接，第三连接电极13的第二端通过过孔与第二初始化信号线Vint2连接。例如，第三连接电极13可以作为第七晶体管T7的第一极，实现了第二初始化信号线Vint2将第二初始信号写入第七晶体管T7。
例如，第四连接电极14的形状可以为哑铃状，第四连接电极14通过过孔与第四晶体管的有源层的第一区连接。例如，第四连接电极14可以作为第四晶体管T4的第一极，第四连接电极44被配置为与后续形成的数据信号线DT连接。
例如，第五连接电极15的形状可以近似为“Z”字形，第五连接电极15的第一端通过过孔与第五晶体管T5的有源层的第一区连接，第五连接电极15的第二端通过过孔与第二极板C2连接，实现了第二极板C2和第五晶体管T5的有源层的第一区具有相同的电位。例如，第五连接电极15可以作为第五晶体管T5的第一极。
例如，第六连接电极16的形状可以为矩形状，第六连接电极16通过过孔与第六晶体管T6的有源层的第二区(也是第七晶体管T7的 有源层的第二区)连接，使第六晶体管T6的有源层的第二区和第七晶体管T7的有源层的第二区具有相同的电位。例如，第六连接电极16可以作为第六晶体管T6的第二极(或者第七晶体管T7的第二极)。
例如，如图12A所示，位于相邻两行的第一像素驱动电路DR1和第二像素驱动电路DR2的第三导电层SD1的图案的间隔D1为7.0微米-10.0微米，例如8.0微米、8.5微米、9.0微米或者9.5微米等。由此，相邻两行的第一像素驱动电路DR1和第二像素驱动电路DR2的第三导电层SD1的图案具有较大的间隔，该间隔可以为显示基板上的其他电路图案以及走线提供排布空间。
例如，图13示出了第三导电层SD1上设置的第一平坦层PLN1的平面示意图，如图13所示，第一平坦层PLN1包括多个第一过孔V1、多个第二过孔V2、多个电源过孔V3以及多个数据过孔V4。多个第一过孔V1用于连接第一发光器件EL1采用的第一电极连接电极CE与第一像素驱动电路DR1，多个第二过孔V2用于连接第二发光器件EL2采用的第一电极连接电极CE与第二像素驱动电路DR2，多个电源过孔V3用于连接后续的第一电源信号线VDD与第一像素驱动电路DR1/第二像素驱动电路DR2，多个数据过孔V4用于连接后续的数据信号线DT与第一像素驱动电路DR1/第二像素驱动电路DR2。
在该实施例中，多个第一过孔V1、多个第二过孔V2和多个电源过孔V3位于同一直线上，也即第一直线L1上，多个数据过孔V4位于另一直线上，也即第二直线L2上。
图14A示出了设置在第一平坦化层PLN1上的第四导电层SD2的平面示意图，图14B示出了第四导电层SD2与第三导电层SD1交叠的平面示意图；图14C示出了第四导电层SD2与第三导电层SD1、第二导电层Gate2、第一导电层Gate1和半导体层ACT交叠的平面示意图。如图14A、图14B以及图14C所示，每个第一像素驱动电路和每个第二像素驱动电路的第四导电层SD2的图案至少包括第一电极连接电极CE、数据信号线DT和第一电源信号线VDD。
例如，第一电极连接电极CE用于连接第一发光器件EL1与第一像素驱动电路DR1或者连接第二发光器件EL2的第一电极E1与第二像素驱动电路DR2。
例如，数据信号线DT的形状可以为主体部分沿着列方向延伸的直线状，数据信号线TD通过数据过孔V4与第四连接电极14连接。由于第四连接电极14通过过孔与第四晶体管T4的有源层的第一区连接，因而实现了数据信号线DT将数据信号写入第四晶体管T4的第一极。
例如，第一电源信号线VDD可以为主体部分沿着列方向延伸的折线状，第一电源信号线VDD通过电源过孔V3与第五连接电极15连接。由于第五连接电极15通过过孔同时与第二极板C2和第五晶体管T5的有源层的第一区连接，因而实现了第一电源信号线VDD将第一电源信号写入第五晶体管T5的第一极，并使第二极板C2和第五晶体管T5的第一极具有相同的电位。
例如，如图14B所示，第三导电层SD1包括位于第一晶体管T1的第二极和第三晶体管T3的栅电极之间的连接部(也即上述第一连接电极11)，第一电源信号线VDD还包括突出部VDP，连接部(也即上述第一连接电极11)在衬底基板上的正投影与突出部VDP在衬底基板上的正投影交叠。例如，连接部(也即上述第一连接电极11)在衬底基板上的正投影位于突出部VDP在衬底基板上的正投影内。由此，突出部VDP可以对N1节点起到屏蔽作用。
由此，在本公开的实施例中，第三导电层SD1仅包括连接电极(第一到第六连接电极11-16)，用于转接信号和跳线作用，因此可以预留处较大的间隔D1，以便于其他电路或者走线，如图12A所示。第四导电层SD2同时包括第一电源信号线VDD和数据信号线DT，第一电源信号线VDD包括突出部VDP以对N1点起到屏蔽作用，数据信号线DT设置在第四导电层SD2可以减小信号传输压降，减小充电时间，实现高刷新率显示。
例如，参考图2和图3，第四导电层SD2上设置有第二平坦层PLN2，第二平坦层PLN2上可以设置有第一连接走线TL，如图15所示，第一连接走线TL上设置有第三平坦化层PLN3。
例如，在一些实施例中，第一连接走线TL可以设置在多个功能层中，此时，第二平坦层PLN2上可以设置有部分第一连接走线TL，该部分第一连接走线TL上设置有第三平坦化层PLN3，第三平坦化层PLN3上设置有另一部分第一连接走线TL，该另一部分第一连接走线 TL上设置有第四平坦化层，第四平坦化层上设置有再一部分第一连接走线TL，该再一部分第一连接走线TL上设置有第五平坦化层PLN5。
例如，第五平坦化层PLN5上可以设置上述第一发光器件EL1和第二发光器件EL2。第一发光器件EL1和第二发光器件EL2上设置有封装层EN。
例如，第一连接走线TL的材料可以采用透明导电材料，如氧化铟锡(ITO)或氧化铟锌(IZO)等透明金属氧化物，以进一步提高第二显示区20的透光率。
例如，在图6的实施例中，显示基板的第三导电层SD1和第一平坦化层PLN1与上述实施例略有不同。如图16A所示，在图6的实施例中，第三导电层SD1中第四连接电极14的图案具有较长的直线部分；如图16B所示，第一平坦化层PLN1中的多个第一过孔V1、多个第二过孔V2、多个电源过孔V3和多个数据过孔V4位于同一直线上，也即第一直线L1上；图16C示出了第四导电层SD2与第一导电层SD1交叠的示意图，图16D示出了第一连接走线TL与第四导电层SD2和第一导电层SD1交叠的示意图，如图16D所示，第一连接走线TL的延伸方向与上述第一直线L1的延伸方向平行，为多个第一像素驱动电路DR1和第二像素驱动电路DR2的行方向。
例如，在本公开的实施例中，衬底基板BS可以是柔性基底，或者可以是刚性基底。刚性衬底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。例如，在一些示例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
例如，第一导电层Gate1、第二导电层Gate2、第三导电层SD1和第四导电层SD2可以采用金属材料，如钛(Ti)、铜(Cu)、铝(Al) 和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一连接走线TL可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。第一栅绝缘层GI1、第二栅绝缘层GI2和第层间绝缘层IDL可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3等平坦化层可以采用有机材料，如聚酰亚胺、树脂等。半导体材料层ACT可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料。
例如，第一发光器件EL1和第二发光器件EL2的第一电E1可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物，或者采用透明金属氧化物与金属(例如银)的叠层，第二电极E2的材料可以采用锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
本公开的实施例对显示基板上各个功能层的材料不作具体限定。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此， 本公开的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，其中，所述第一显示区至少部分围绕所述第二显示区，所述第二显示区的透光率大于所述第一显示区的透光率；
    多个像素驱动电路，位于所述衬底基板上，且位于所述第一显示区；
    第一平坦化层，位于所述多个像素驱动电路的远离所述衬底基板一侧；
    多个发光器件，位于所述第一平坦化层的远离所述衬底基板一侧；
    第一电源信号线，位于所述第一平坦化层的远离所述衬底基板一侧，且位于所述第一显示区；以及
    数据信号线，位于所述第一平坦化层的远离所述衬底基板一侧，且位于所述第一显示区；
    其中，所述第一平坦化层包括将所述多个像素驱动电路中的至少一个与所述多个发光器件中的至少一个电连接的器件连接过孔、将所述多个像素驱动电路中的至少一个与所述第一电源信号线电连接的电源过孔以及将所述多个像素驱动电路中的至少一个与所述数据信号线电连接的数据过孔，
    所述器件连接过孔、电源过孔以及数据过孔沿第一方向排列。
  2. 根据权利要求1所述的显示基板，还包括：
    第一初始化信号线，配置为向多个像素驱动电路中的至少一个提供第一初始化信号；
    其中，所述器件连接过孔、所述电源过孔以及所述数据过孔与所述第一初始化信号线的最短距离基本相等。
  3. 根据权利要求2所述的显示基板，其中，所述多个像素驱动电路包括第一像素驱动电路和第二像素驱动电路，所述多个发光器件包括位于所述第一显示区的第一发光器件和位于所述第二显示区的第二发光器件，
    所述器件连接过孔包括第一过孔和第二过孔，所述第一发光器件通过所述第一过孔与所述第一像素驱动电路电连接，所述第二发光器 件通过位于所述第一显示区和所述第二显示区的第一连接走线与所述第二像素驱动电路电连接，并且在所述第一显示区，所述第一连接走线通过所述第二过孔与所述第二像素驱动电路电连接。
  4. 根据权利要求3所述的显示基板，其中，所述多个像素驱动电路包括沿第一方向延伸且沿第二方向排布的多个像素电路组，所述多个像素电路组中的至少一组包括多个第一像素驱动电路和多个第二像素驱动电路，
    所述多个第一像素驱动电路和所述多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔沿所述第一方向排列，所述第一方向和所述第二方向交叉。
  5. 根据权利要求4所述的显示基板，其中，所述至少一组像素电路组中的多个第一像素驱动电路和多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔与所述第一初始化信号线的最短距离基本相同。
  6. 根据权利要求4或5所述的显示基板，其中，所述至少一组像素电路组中的多个第一像素驱动电路和多个第二像素驱动电路所采用的多个第一过孔、多个第二过孔、多个电源过孔以及多个数据过孔位于同一直线上，所述同一直线沿所述第一方向延伸。
  7. 根据权利要求6所述的显示基板，其中，在平行于所述衬底基板的方向上，所述第一连接走线位于所述同一直线的至少一侧。
  8. 根据权利要求7所述的显示基板，其中，所述第一连接走线从所述第一显示区到所述第二显示区的延伸方向平行于所述第一方向。
  9. 根据权利要求2-8任一所述的显示基板，其中，所述第一像素驱动电路和所述第二像素驱动电路分别包括作为复位晶体管的第一晶体管、作为补偿晶体管的第二晶体管和作为驱动晶体管的第三晶体管，
    所述第一晶体管的栅电极与复位信号线连接，所述第一晶体管的第一极与第一初始化信号线连接，所述第一晶体管的第二极分别与所述第二晶体管的第一极和所述第三晶体管的栅电极连接，所述第二晶体管的栅电极与扫描信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；
    所述第一晶体管的栅电极、所述第二晶体管的栅电极、所述第三晶体管的栅电极、所述扫描信号线与所述复位信号线位于所述衬底基板上 的第一导电层；
    所述第一初始化信号线位于第二导电层，所述第二导电层位于所述第一导电层的远离所述衬底基板的一侧。
  10. 根据权利要求9所述的显示基板，其中，所述第一像素驱动电路和第二像素驱动电路还分别包括存储电容、作为数据写入晶体管的第四晶体管和作为发光控制晶体管的第五晶体管，
    所述第四晶体管的栅电极与扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第三晶体管的第一极连接，所述第五晶体管的栅电极与发光控制线连接，所述第五晶体管的第一极与所述存储电容的第二极板连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接；
    所述发光控制线位于所述第一导电层。
  11. 根据权利要求10所述的显示基板，其中，所述第一像素驱动电路和所述第二像素驱动电路还分别包括作为发光控制晶体管的第六晶体管以及作为复位晶体管的第七晶体管，
    所述第六晶体管的栅电极与所述发光控制线连接，所述第六晶体管的第一极与所述第三晶体管的第二极连接，所述第一发光器件或者所述第二发光器件与所述第六晶体管的第二极连接，所述第七晶体管的栅电极与复位信号线连接，所述第七晶体管的第一极与第二初始化信号线连接，所述第七晶体管的第二极与所述第六晶体管的第二极连接；
    所述第二初始化信号线位于所述第二导电层。
  12. 根据权利要求11所述的显示基板，其中，在平行于所述衬底基板的第一方向上，用于同一第一像素驱动电路或第二像素驱动电路的所述第二初始化信号线、所述复位信号线、所述第一初始化信号线以及所述扫描信号线依次排布。
  13. 根据权利要求10-12任一所述的显示基板，其中，所述第二晶体管包括有源层以及两个栅电极，所述有源层位于所述第一金属层与所述衬底基板之间的半导体材料层，
    所述有源层包括第一部分，所述第一部分在所述衬底基板上的正投影与所述两个栅电极在所述衬底基板上的正投影不交叠，
    所述第二导电层包括遮挡图案，所述第一部分在所述衬底基板上的 正投影与所述遮挡图案在所述衬底基板上的正投影交叠。
  14. 根据权利要求13所述的显示基板，其中，所述遮挡图案与所述第一初始化信号线一体连接。
  15. 根据权利要求13或14所述的显示基板，其中，所述半导体材料层包括连接所述第二晶体管的有源层和所述第一晶体管的有源层的半导体图案，
    所述半导体图案在所述衬底基板上的正投影与所述遮挡图案在所述衬底基板上的正投影交叠。
  16. 根据权利要求9-15任一所述的显示基板，其中，所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第三晶体管的第一极和第二极位于第三导电层，所述第三导电层位于所述第二导电层的远离所述衬底基板的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述第一电源信号线位于第四导电层，所述第四导电层位于所述第三导电层的远离所述衬底基板的一侧。
  18. 根据权利要求17所述的显示基板，其中，所述数据信号线位于所述第四导电层。
  19. 根据权利要求16-18任一所述的显示基板，其中，所述第三导电层还包括位于所述第一晶体管的第二极和所述第三晶体管的栅电极之间的连接部，
    所述第一电源信号线还包括突出部，
    所述连接部在所述衬底基板上的正投影与所述突出部在所述衬底基板上的正投影交叠。
  20. 根据权利要求19所述的显示基板，其中，所述连接部在所述衬底基板上的正投影位于所述突出部在所述衬底基板上的正投影内。
  21. 根据权利要求9-20任一所述的显示基板，其中，位于相邻两行的第一像素驱动电路和第二像素驱动电路的第三导电层的图案的间隔为7.0微米-10.0微米。
  22. 根据权利要求2-21任一所述的显示基板，其中，在所述至少一组像素电路组的多个第一像素驱动电路和多个第二像素驱动电路中，每相邻的两个第二像素驱动电路之间设置两个第一像素驱动电路。
  23. 一种显示装置，包括权利要求1-22任一所述的显示基板。
PCT/CN2022/096404 2021-09-14 2022-05-31 显示基板和显示装置 WO2023040356A1 (zh)

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