WO2023173424A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023173424A1
WO2023173424A1 PCT/CN2022/081777 CN2022081777W WO2023173424A1 WO 2023173424 A1 WO2023173424 A1 WO 2023173424A1 CN 2022081777 W CN2022081777 W CN 2022081777W WO 2023173424 A1 WO2023173424 A1 WO 2023173424A1
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WO
WIPO (PCT)
Prior art keywords
display area
sub
light
pixel circuit
emitting element
Prior art date
Application number
PCT/CN2022/081777
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English (en)
French (fr)
Inventor
杜丽丽
曹席磊
张振华
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/081777 priority Critical patent/WO2023173424A1/zh
Priority to CN202280000484.2A priority patent/CN117223410A/zh
Publication of WO2023173424A1 publication Critical patent/WO2023173424A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of display devices.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • embodiments of the present disclosure provide a display substrate, including: a base substrate, a plurality of pixel circuits and a plurality of light-emitting elements.
  • the base substrate includes a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the plurality of pixel circuits includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display area
  • the plurality of light-emitting elements includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • a plurality of second light-emitting elements in the display area is a plurality of pixel circuits and a plurality of light-emitting elements.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the At least one first light-emitting element emits light.
  • At least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the At least one second light emitting element emits light.
  • the first display area includes: a first first sub-display area to an N-th first sub-display area arranged sequentially in the first direction along a side away from the second display area, where N is An integer greater than 1.
  • the second display area includes at least one second sub-display area, the second light-emitting element of the second sub-display area is electrically connected to the second pixel circuit of the n-th first sub-display area, the n-th The first light-emitting element of a sub-display area is electrically connected to the first pixel circuit of the n+i-th first sub-display area, where n and i are both integers greater than 0 and less than N.
  • the first light-emitting element of the n+i-th first sub-display area is electrically connected to the first pixel circuit of the n+i+j-th first sub-display area, where j is An integer greater than 0 and less than N.
  • j i.
  • the at least one first pixel circuit and the at least one first light-emitting element are electrically connected through a first conductive line, and the at least one second pixel circuit and the at least one second light-emitting element are electrically connected.
  • the electrical connection is via a second conductive wire.
  • the first conductive line or the second conductive line electrically connected to at least one pixel circuit in the at least one first sub-display area and the first conductive line electrically connected to the at least one first light-emitting element The lines have a heterogeneous structure.
  • the second conductive line electrically connecting the second pixel circuit of the n-th first sub-display area and the second light-emitting element of the second sub-display area is electrically connected to the second conductive line of the n-th first sub-display area.
  • the first light-emitting elements of the n first sub-display areas and the first conductive lines of the first pixel circuit of the n+i-th first sub-display area have different layer structures.
  • the first conductive line electrically connects the first light-emitting element of the n+i-th first sub-display area and the first pixel circuit of the n+i+j-th first sub-display area.
  • the first conductive line electrically connecting the first pixel circuit of the n+i-th first sub-display area and the first light-emitting element of the n-th first sub-display area have a different layer structure.
  • the number of pixel circuits in the at least one first sub-display area is greater than the number of first light-emitting elements.
  • the pixel circuits in the n-th first sub-display area are all second pixel circuits.
  • the number of pixel circuits of the n-th first sub-display area is greater than or equal to the number of pixel circuits of the n+1-th first sub-display area, and the n-th first sub-display area
  • the number of first light-emitting elements in the display area is greater than or equal to the number of first light-emitting elements in the (n+1)th first sub-display area.
  • the second light-emitting element in the second sub-display area close to the n-th first display area is the same as the second light-emitting element in the n-th first sub-display area close to the second sub-display area.
  • the second pixel circuit in the second sub-display area is electrically connected to the second light-emitting element in the second sub-display area that is far away from the n-th first sub-display area and the second light-emitting element in the n-th first sub-display area that is far away from the second sub-display area.
  • the second pixel circuit of the sub-display area is electrically connected.
  • the pixel circuits in the first display area are arranged in an array, and the first direction is a row direction of the pixel circuits.
  • the second display area includes: M-th second sub-display area to first M-th second sub-display area arranged sequentially in the first direction along a side away from the first sub-display area.
  • a second sub-display area where M is an integer greater than 1 and less than N.
  • the second light-emitting element in the m-th second sub-display area is electrically connected to the first sub-display area where the second pixel circuit is located
  • the second light-emitting element located in the m+1-th second sub-display area is electrically connected to The first sub-display area where the second pixel circuit is located is close to the side of the second display area, and m is an integer greater than 0 and less than M.
  • the second conductive lines electrically connected to the second light-emitting elements in the adjacent second sub-display area are located on different conductive layers, and the second conductive lines electrically connected to the first light-emitting elements in the adjacent first sub-display area are located in different conductive layers.
  • a conductive line is located in different conductive layers.
  • the second conductive lines electrically connected to the plurality of second light-emitting elements in the second sub-display area have a same layer structure.
  • the second conductive lines electrically connected to the second light-emitting elements adjacent in the first direction in the second sub-display area have a hetero-layer structure.
  • the first conductive line and the second conductive line are transparent conductive lines.
  • the first display area further includes: a first third sub-display area to an H-th sub-display area arranged sequentially along a side away from the second display area in the second direction. Three sub-display areas, where H is an integer greater than 1.
  • the second display area also includes: at least one fourth sub-display area, the second light-emitting element of the fourth sub-display area is electrically connected to the second pixel circuit of the h-th third sub-display area, the h-th third sub-display area has The first light-emitting element of the third sub-display area is electrically connected to the first pixel circuit of the h+s-th third sub-display area, where h and s are both integers greater than 0 and less than H.
  • the second direction is parallel to the first direction, or the second direction crosses the first direction.
  • the first display area further includes: a first fifth sub-display area to an R-th sub-display area arranged sequentially along a side away from the second display area in the third direction.
  • Five sub display area where R is an integer greater than 1.
  • the second display area also includes: at least one sixth sub-display area, the second light-emitting element of the sixth sub-display area is electrically connected to the second pixel circuit of the r-th fifth sub-display area, the r-th
  • the first light-emitting element of the fifth sub-display area is electrically connected to the first pixel circuit of the r+k-th fifth sub-display area, where r and k are both integers greater than 0 and less than R.
  • the first display area further includes: a first seventh sub-display area to a G-th sub-display area sequentially arranged along a side away from the second display area in the fourth direction. Seven sub-display areas, where G is an integer greater than 1.
  • the second display area also includes: at least one eighth sub-display area, the second light-emitting element of the eighth sub-display area is electrically connected to the second pixel circuit of the g-th seventh sub-display area, the g-th The first light-emitting element of the seventh sub-display area is electrically connected to the first pixel circuit of the g+d seventh sub-display area, where g and d are both integers greater than 0 and less than G.
  • the density of the second light-emitting elements is less than or equal to the density of the first light-emitting elements.
  • the resolution of the first display area is less than or equal to the resolution of the second display area.
  • embodiments of the present disclosure provide a display device including the display substrate as described above.
  • Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a working timing diagram of the pixel circuit provided in Figure 2;
  • Figure 4 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a partial cross-sectional schematic diagram along the Q-Q’ direction in Figure 4.
  • Figure 6A is a top view of the pixel circuit after forming the semiconductor layer in Figure 4.
  • Figure 6B is a top view of the pixel circuit after forming the first conductive layer in Figure 4.
  • Figure 6C is a top view of the pixel circuit in Figure 4 after the second conductive layer is formed;
  • Figure 6D is a top view of the pixel circuit after forming the third insulating layer in Figure 4.
  • Figure 7 is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a display area according to at least one embodiment of the present disclosure.
  • Figure 9 is a schematic connection diagram of the first display area and the second display area according to at least one embodiment of the present disclosure.
  • Figure 10 is an example diagram of a transparent conductive thread according to at least one embodiment of the present disclosure.
  • Figure 11A is a schematic diagram of the connection of transparent conductive lines in the first and second sub-display areas according to at least one embodiment of the present disclosure
  • FIG. 11B is a schematic diagram of the connection of transparent conductive lines in the second second sub-display area according to at least one embodiment of the present disclosure
  • Figure 11C is a schematic diagram of the connection of transparent conductive lines in the first first sub-display area according to at least one embodiment of the present disclosure
  • 11D is a schematic diagram of the connection of transparent conductive lines in the second first sub-display area according to at least one embodiment of the present disclosure
  • 11E is a schematic diagram of the connection of transparent conductive lines in the third first sub-display area and the fourth first sub-display area in at least one embodiment of the present disclosure
  • 11F is a schematic diagram of the connection of transparent conductive lines in the fifth first sub-display area and the sixth first sub-display area in at least one embodiment of the present disclosure
  • 11G is a schematic diagram of the connection of transparent conductive lines from the seventh first sub-display area to the tenth first sub-display area according to at least one embodiment of the present disclosure
  • Figure 12 is a schematic diagram of a first transparent conductive layer according to at least one embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of a second transparent conductive layer according to at least one embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a third transparent conductive layer according to at least one embodiment of the present disclosure.
  • Figure 15 is a schematic diagram of three transparent conductive layers according to at least one embodiment of the present disclosure.
  • Figure 16 is another connection schematic diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure
  • Figure 17 is another connection schematic diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure
  • Figure 18 is another connection schematic diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure
  • Figure 19 is another connection schematic diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure
  • Figure 20 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 21 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 22 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 23 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 24 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 25 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 26 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 27 is another connection schematic diagram of the first display area and the second display area of at least one embodiment of the present disclosure.
  • Figure 28 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 29 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • Figure 30 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure
  • FIG. 31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • Light transmittance in this disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • This embodiment provides a display substrate, including: a base substrate, a plurality of pixel circuits and a plurality of light-emitting elements.
  • the base substrate includes a first display area and a second display area, and the first display area is located on at least one side of the second display area.
  • the plurality of pixel circuits includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display area.
  • the plurality of light-emitting elements includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element.
  • the light-emitting element emits light.
  • At least one second pixel circuit of the plurality of second pixel circuits is electrically connected to at least one second light-emitting element of the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element.
  • the light-emitting element emits light.
  • the first display area includes: the first first sub-display area to the N-th first sub-display area arranged sequentially in the first direction along the side away from the second display area, where N is an integer greater than 1. .
  • the second display area includes at least one second sub-display area.
  • the second light-emitting element of the second sub-display area is electrically connected to the second pixel circuit of the n-th first sub-display area.
  • the n-th first sub-display area The first light-emitting element is electrically connected to the first pixel circuit of the n+i-th first sub-display area, where n and i are both integers greater than 0 and less than N.
  • i can be 1 or 2, etc.
  • the n-th first sub-display area is located on a side of the (n+1)-th first sub-display area close to the second display area.
  • the second display area may include only one second sub-display area.
  • the second display area may include a plurality of second sub-display areas.
  • the plurality of second sub-display areas may be arranged sequentially in the first direction along a side away from the first sub-display area.
  • this embodiment is not limited to this.
  • the display substrate provided in this embodiment divides the first display area and the second display area, and the second light-emitting element of the second sub-display area of the second display area and the first sub-display area of the first display area are
  • the two pixel circuits are electrically connected, and the first light-emitting element of the first sub-display area is electrically connected to the first pixel circuit in the other first sub-display area, thereby realizing staggered connection of the pixel circuits and light-emitting elements in different partitions.
  • This embodiment can reduce the length difference of the conductive lines electrically connecting the second light-emitting element and the second pixel circuit.
  • the length of the conductive wire will determine the overlap area between the conductive wire and other signal traces, thereby affecting the size of the parasitic capacitance.
  • the difference in parasitic capacitance will lead to uneven screen display.
  • This embodiment uses staggered connections between pixel circuits and light-emitting elements in different partitions to reduce the length difference of conductive lines, thereby improving the poor uniformity of the display screen, improving display uniformity, and achieving a more uniform full-screen visual display. Effect.
  • At least one first pixel circuit and at least one first light-emitting element may be electrically connected through a first conductive line
  • at least one second pixel circuit and at least one second light-emitting element may be electrically connected through a second conductive line.
  • both the first conductive line and the second conductive line may be transparent conductive lines.
  • the first conductive line and the second conductive line may be made of transparent conductive material (eg, indium tin oxide (ITO)).
  • ITO indium tin oxide
  • the first conductive line may be a non-transparent conductive line
  • the second conductive line may be a transparent conductive line.
  • the first conductive line can be made of metal material
  • the second conductive line can be made of transparent conductive material (eg, ITO).
  • the first light-emitting element of the n+i-th first sub-display area may be electrically connected to the first pixel circuit of the n+i+j-th first sub-display area, where j is greater than An integer that is 0 and less than N.
  • the first light-emitting element of the first sub-display area of the first display area can be connected in a staggered manner with the first pixel circuits of other first sub-display areas to support the placement of the second pixel circuit in the second display area. near or around, thereby improving the situation where the length difference of the second conductive line electrically connecting the second pixel circuit and the second light-emitting element is too large.
  • j can equal i.
  • i and j can both be 1 or 2.
  • the first light-emitting element of the n+i-th first sub-display area may be electrically connected to the first pixel circuit of the n+2 ⁇ i-th first sub-display area, and the n+2 ⁇ i-th first sub-display area
  • the first light-emitting element of the region may be electrically connected to the first pixel circuit of the n+3 ⁇ i-th first sub-display region.
  • this embodiment is not limited to this.
  • j can be different from i.
  • i can be 2 and j can be 1.
  • the first conductive line or the second conductive line electrically connected to at least one pixel circuit in at least one first sub-display area and the first conductive line electrically connected to at least one first light-emitting element may be It is a heterogeneous structure.
  • a and B are heterolayer structures, which means that A and B are located on different conductive layers. In this way, mutual interference between different conductive lines can be avoided.
  • the second conductive line electrically connecting the second light-emitting element of the second sub-display area and the second pixel circuit of the n-th first sub-display area is electrically connected to the second conductive line electrically connecting the n-th first sub-display area.
  • a light-emitting element and the first conductive line of the first pixel circuit of the n+i-th first sub-display area may have different layer structures.
  • the first conductive line electrically connecting the first light emitting element of the n+ith first sub-display area and the first pixel circuit of the n+i+jth first sub-display area is electrically connected to the first conductive line of the first pixel circuit of the n+i+jth first sub-display area.
  • the first light-emitting elements of the n first sub-display areas and the first conductive lines of the first pixel circuit of the n+i-th first sub-display area may have different layer structures.
  • the pixel circuits of the n-th first sub-display area may all be second pixel circuits.
  • the second pixel circuits may be advantageous to reduce the length of the second conductive line that electrically connects the second light-emitting element and the second pixel circuit.
  • the number of pixel circuits in at least one first sub-display area may be greater than the number of first light-emitting elements.
  • a space for disposing the second pixel circuit is formed by compressing the pixel circuits in the first display area. Therefore, the number of pixel circuits in the first display area is greater than the number of the first light-emitting elements.
  • the number of pixel circuits of the n-th first sub-display area may be greater than or equal to the number of pixel circuits of the n+1-th first sub-display area.
  • the number of first light-emitting elements may be greater than or equal to the number of first light-emitting elements of the (n+1)th first sub-display area.
  • the number of pixel circuits in the plurality of first sub-display areas may be gradually reduced, and the number of first light-emitting elements may also be gradually reduced.
  • the second light-emitting element in the second sub-display area close to the n-th first display area may be electrically connected to the second pixel circuit in the n-th first sub-display area close to the second sub-display area.
  • the second light-emitting element in the second sub-display area that is far away from the n-th first sub-display area can be electrically connected to the second pixel circuit in the n-th first sub-display area that is far away from the second sub-display area.
  • the connection method of the second light-emitting element and the second pixel circuit in the corresponding area helps to arrange the conductive lines and reduce mutual interference caused by overlapping of the conductive lines.
  • this embodiment is not limited to this.
  • a plurality of pixel circuits in the first display area may be arranged in an array, and the first direction may be a row direction of the pixel circuits.
  • the first direction may be a column direction of the pixel circuit, or may be a direction crossing the row direction, or may be a direction crossing the column direction.
  • the second display area may include: the Mth second sub-display area to the first second sub-display area arranged sequentially in the first direction along a side away from the first sub-display area. district.
  • M is an integer greater than 1 and less than N.
  • the first sub-display area where the second pixel circuit is electrically connected to the second light-emitting element in the m-th second sub-display area may be located in the m+1-th second sub-display area where the second light-emitting element is electrically connected.
  • the side of the first sub-display area where the second pixel circuit is located is close to the second display area, and m is an integer greater than 0 and less than M.
  • the second light-emitting element in the second sub-display area far away from the first display area may be electrically connected to the second pixel circuit in the first sub-display area close to the second display area, and the second pixel circuit in the first sub-display area close to the first display area
  • the second light-emitting element in the second sub-display area may be electrically connected to the second pixel circuit in the first sub-display area away from the second display area. In this way, it may be helpful to reduce the length difference between the second conductive lines electrically connecting the second light-emitting element and the second pixel circuit.
  • the entire second display area may be divided into a plurality of second sub-display areas, or a part of the second display area may be divided into a plurality of second sub-display areas. However, this embodiment is not limited to this.
  • the second conductive lines electrically connected to the second light-emitting elements in the adjacent second sub-display area may be located on different conductive layers, and the second conductive lines electrically connected to the first light-emitting elements in the adjacent first sub-display area
  • the first conductive lines may be located on different conductive layers. In this way, mutual interference due to overlapping of conductive lines can be reduced.
  • the second conductive lines electrically connected to the plurality of second light-emitting elements in the second sub-display area may be of the same layer structure.
  • the second conductive lines electrically connected to the second light-emitting elements adjacent in the first direction in the second sub-display area may have a hetero-layer structure.
  • this embodiment is not limited to this.
  • the second conductive line electrically connected to the second light-emitting element may be formed by connecting multiple conductive line segments, and adjacent conductive line segments may be located on different conductive layers.
  • the first display area may further include: a first third sub-display area to an H-th third sub-display area sequentially arranged along a side away from the second display area in the second direction. area, where H is an integer greater than 1.
  • the second display area may also include: at least one fourth sub-display area, the second light-emitting element of the fourth sub-display area is electrically connected to the second pixel circuit of the h-th third sub-display area, and the h-th third sub-display area
  • the first light-emitting element of the area is electrically connected to the first pixel circuit of the h+s-th third sub-display area, where h and s are both integers greater than 0 and less than H.
  • h and s can both be 1, or h can be 1 and s can be 2.
  • the second direction may be parallel to the first direction, or the second direction may cross the first direction.
  • the first display area and the second display area are divided into multiple partitions in the first direction and the second direction, and staggered connections between the light-emitting elements and the pixel circuits are performed in the multiple partitions, which is beneficial to reducing the electrical connection of the second light-emitting area.
  • the first display area may further include: a first fifth sub-display area to an R-th fifth sub-display area arranged sequentially in the third direction along a side away from the second display area. area, where R is an integer greater than 1.
  • the second display area may also include: at least one sixth sub-display area. The second light-emitting element of the sixth sub-display area is electrically connected to the second pixel circuit of the r-th fifth sub-display area, and the first light-emitting element of the r-th fifth sub-display area is electrically connected to the r+k-th fifth sub-display area.
  • the first pixel circuit of the area is electrically connected, where r and k are both integers greater than 0 and less than R.
  • r and k can both be 1, or r can be 1 and k can be 2.
  • the third direction may be parallel to the first direction or the second direction, or the third direction may intersect the first direction, or the third direction may intersect the second direction.
  • the first display area and the second display area are divided into multiple partitions, and the light-emitting elements and the pixel circuits are connected in a staggered manner in the multiple partitions, which is beneficial to reducing the electrical connection between the second light-emitting element and the second display area. Differences in length of the conductive lines of the pixel circuit.
  • the first display area may further include: a first seventh sub-display area to a G-th seventh sub-display area arranged sequentially in the fourth direction along a side away from the second display area. area, where G is an integer greater than 1.
  • the second display area may also include: at least one eighth sub-display area.
  • the second light-emitting element of the eighth sub-display area is electrically connected to the second pixel circuit of the g-th seventh sub-display area
  • the first light-emitting element of the g-th seventh sub-display area is electrically connected to the g+d-th seventh sub-display area.
  • the first pixel circuit of the area is electrically connected.
  • g and d are both integers greater than 0 and less than G.
  • g and d can both be 1, or g can be 1 and d can be 2.
  • the fourth direction may be parallel to the first direction, the second direction, or the third direction; or the fourth direction may cross the first direction, the second direction, or the third direction.
  • the first display area and the second display area can be divided into multiple partitions in multiple directions, and the light-emitting elements and the pixel circuits can be connected in a staggered manner in the multiple partitions, which is beneficial to reducing the electrical connection between the second light-emitting element and the second display area. Differences in length of the conductive lines of the pixel circuit.
  • N, H, R, and G may be the same; or, at least two of N, H, R, and G may be the same; or, N, H, R, and G may each be different.
  • this embodiment is not limited to this.
  • i, s, k, and d may be the same, or at least two of i, s, k, and d may be the same, or i, s, k, and d may each be different.
  • this embodiment is not limited to this.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2, and the first display area A1 is located at at least one side of the second display area A2.
  • the first display area A1 may surround the second display area A2.
  • this embodiment is not limited to this.
  • the first display area A1 may partially surround the second display area A2.
  • the second display area A2 is a light-transmissive display area, which can also be called an under-display camera (UDC, Under Display Camera) area; the first display area A1 is a non-light-transmitting display area.
  • the display area can also be called the normal display area.
  • the orthographic projection of the photosensitive sensor (eg, camera and other hardware) on the display substrate may be located in the second display area A2 of the display substrate.
  • the second display area A2 may be circular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be smaller than or equal to the size of the second display area A2 .
  • this embodiment is not limited to this.
  • the second display area A2 may be rectangular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be less than or equal to the size of the inscribed circle of the second display area A2.
  • the second display area A2 may be located at the top middle position of the display area AA.
  • the first display area A1 may surround the second display area A2.
  • this embodiment is not limited to this.
  • the second display area A2 may be located at other locations such as the upper left corner or the upper right corner of the display area AA.
  • the first display area A1 may surround at least one side of the second display area A2.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the second display area A2 may be circular or elliptical. However, this embodiment is not limited to this.
  • the second display area A2 may be in a rectangular, semicircular, pentagonal or other shape.
  • the display area AA may be provided with multiple sub-pixels.
  • At least one sub-pixel may include a pixel circuit and a light emitting element.
  • the pixel circuit may be configured to drive connected light emitting elements.
  • the pixel circuit may be configured to provide a driving current to drive the light emitting element to emit light.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C (ie, 3 transistors and 1 capacitor) structure, a 7T1C (ie, 7 transistors and 1 capacitor) structure, or a 5T1C (ie, 5 transistors) structure.
  • the light-emitting element may be an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the light-emitting element emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the color of the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • one pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • the shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically or vertically.
  • the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically or horizontally. Arranged in straight rows or squares. However, this embodiment is not limited to this.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 3 is an operating timing diagram of the pixel circuit provided in FIG. 2 .
  • the pixel circuit of this exemplary embodiment is explained by taking the 7T1C structure as an example. However, this embodiment is not limited to this.
  • the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7.
  • the light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.
  • the drive transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield. In some possible implementations, the drive transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switching transistors may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Polysilicon
  • oxide thin film transistors uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO).
  • LTPO low-temperature polycrystalline Oxide
  • the display substrate may include a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, The second initial signal line INIT2, the first reset control line RST1 and the second reset control line RST2.
  • the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the scan line GL may be configured to provide the scan signal SCAN to the pixel circuit
  • the data line DL may be configured to provide the data signal DATA to the pixel circuit
  • the emission control line EML may be configured to provide the emission control signal EM to the pixel circuit
  • the first reset control line RST1 The second reset control line RST2 may be configured to provide the first reset control signal RESET1 to the pixel circuit
  • the second reset control line RST2 may be configured to provide the second reset control signal RESET2 to the pixel circuit.
  • the first reset control line RST1 may be electrically connected to the scan line GL of the z-1-th row pixel circuit to be input with the scan signal SCAN(z-1), that is, the first The reset control signal RESET1(z) is the same as the scan signal SCAN(z-1).
  • the second reset control line RST2 may be electrically connected to the scan line GL of the z-th row pixel circuit to receive the scan signal SCAN(z), that is, the second reset control signal RESET2(z) is the same as the scan signal SCAN(z).
  • the second reset control line RST2 electrically connected to the z-th row pixel circuit and the first reset control line RST1 electrically connected to the z+1-th row pixel circuit may be an integrated structure.
  • z is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced and the narrow frame design of the display substrate can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the driving transistor T3 is electrically connected to the light-emitting element EL and is controlled by the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.
  • a driving current is output to drive the light-emitting element EL to emit light.
  • the gate electrode of the data writing transistor T4 is electrically connected to the scan line GL
  • the first electrode of the data writing transistor T4 is electrically connected to the data line DL
  • the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan line GL
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3.
  • the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML.
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power line PL1.
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3.
  • the second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the anode of element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3.
  • the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the gate of the light-emitting element EL.
  • the anode is reset.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the gate is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the light-emitting element EL. anode electrical connection.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, and the second node N2 is the connection point of the first light emission control transistor T5, the data writing transistor T4 and the threshold compensation transistor T2.
  • the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6.
  • the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting transistor T7. Connection point of component EL.
  • the working process of the pixel circuit illustrated in FIG. 2 will be described below with reference to FIG. 3 .
  • the pixel circuit shown in FIG. 2 includes a plurality of transistors that are all P-type transistors as an example for explanation.
  • the working process of the pixel circuit may include: a first stage S1 , a second stage S2 , and a third stage S3 .
  • the first phase S1 is called the reset phase.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized and the original data voltage in the storage capacitor Cst is cleared.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, causing data to be written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, and the third light-emitting control transistor T5.
  • the two light-emitting control transistors T6 and the second reset transistor T7 are turned off. At this stage, the light-emitting element EL does not emit light.
  • the second stage S2 is called the data writing stage or threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light-emitting control signal EM provided by the light-emitting control line EML are both high-level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 is turned on.
  • the scan signal SCAN is a low-level signal, turning on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the third node N2 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst.
  • the voltage of the first capacitor plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. , ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, causing the first reset transistor T1 to turn off.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the third stage S3 is called the luminous stage.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned-on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3
  • Vth is the driving transistor T3
  • the threshold voltage of , Vdata is the data voltage output by the data line DL
  • VDD is the first voltage signal output by the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 4 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a partial cross-sectional view along the Q-Q’ direction in Figure 4.
  • FIG. 6A is a top view of the pixel circuit in FIG. 4 after the semiconductor layer is formed.
  • FIG. 6B is a top view of the pixel circuit in FIG. 4 after the first conductive layer is formed.
  • FIG. 6C is a top view of the pixel circuit in FIG. 4 after the second conductive layer is formed.
  • FIG. 6D is a top view of the pixel circuit in FIG. 4 after the third insulating layer is formed.
  • the display substrate may include: a base substrate 100 , and a semiconductor layer 10 , a first conductive layer 11 , a second conductive layer 10 , and a second conductive layer 10 , which are sequentially provided on the base substrate 100 .
  • layer 12 and the third conductive layer 13 .
  • a first insulating layer 101 is provided between the semiconductor layer 10 and the first conductive layer 11
  • a second insulating layer 102 is provided between the first conductive layer 11 and the second conductive layer 12
  • a third insulating layer 103 is provided between 13 .
  • the first insulation layer 101, the second insulation layer 102 and the third insulation layer 103 may be inorganic insulation layers.
  • the first insulating layer 101 and the second insulating layer 102 may also be called a gate insulating layer, and the third insulating layer 103 may also be called an interlayer insulating layer.
  • a fourth conductive layer may be disposed on the side of the third conductive layer 13 away from the base substrate 100.
  • the fourth conductive layer may include an anode connection electrode, and the anode connection electrode may connect the pixel circuit and the light-emitting element.
  • At least one transparent conductive layer may be further disposed on the side of the fourth conductive layer away from the base substrate.
  • the transparent conductive layer may include a transparent conductive line configured to connect the anode connection electrode and the anode of the light-emitting element.
  • a flat layer may be provided between the fourth conductive layer and the transparent conductive layer, and a flat layer may be provided between adjacent transparent conductive layers.
  • An anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer can be disposed in sequence on the side of the transparent conductive layer away from the base substrate. However, this embodiment is not limited to this.
  • the semiconductor layer 10 of the display substrate may include: an active layer of a plurality of transistors of the pixel circuit (for example, a first active layer of the first reset transistor T1 T10, the second active layer T20 of the threshold compensation transistor T2, the third active layer T30 of the driving transistor T3, the fourth active layer T40 of the data writing transistor T4, and the fifth active layer of the first light emission control transistor T5. T50, the sixth active layer T60 of the second light emission control transistor T6, and the seventh active layer T70 of the second reset transistor T7).
  • the active layers of multiple transistors of a pixel circuit may have an integrated structure.
  • At least one active layer may include: a channel region, a first doped region and a second doped region.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the first doped region and the second doped region may On both sides of the channel region, they are doped with impurity particles and are therefore conductive. Impurities can vary depending on the type of transistor.
  • the first doped region or the second doped region of the semiconductor layer may be interpreted as a source electrode or a drain electrode of the transistor.
  • the first conductive layer 11 of the display substrate may include: control electrodes of a plurality of transistors of the pixel circuit (for example, control electrodes T11 of the first reset transistor T1 , The control electrode T21 of the threshold compensation transistor T2, the control electrode T31 of the driving transistor T3, the control electrode T41 of the data writing transistor T4, the control electrode T51 of the first light emitting control transistor T5, the control electrode T61 of the second light emitting control transistor T6, and The control electrode T71 of the two reset transistors T7), the light emitting control line EML, the scanning line GL, and the first reset control line (including the first reset control line RST1 electrically connected to the pixel circuit of this row and the first reset electrically connected to the pixel circuit of the next row).
  • control electrodes of a plurality of transistors of the pixel circuit for example, control electrodes T11 of the first reset transistor T1 , The control electrode T21 of the threshold compensation transistor T2, the control electrode T31 of the driving transistor T3, the control electrode T41 of the data writing transistor
  • control line RST1' and the first electrode Cst-1 of the storage capacitor Cst.
  • the control electrode T11 of the first reset transistor T1 of the pixel circuit of this row, the control electrode of the second reset transistor of the pixel circuit of the previous row, and the first reset control line RST1 may be of an integrated structure.
  • the control electrode T21 of the threshold compensation transistor T2, the control electrode T41 of the data writing transistor T4, and the scanning line GL may have an integrated structure.
  • the control electrode T31 of the driving transistor T3 and the first electrode Cst-1 of the storage capacitor Cst may have an integrated structure.
  • the control electrode T51 of the first light-emitting control transistor T5, the control electrode T61 of the second light-emitting control transistor T6, and the light-emitting control line EML may have an integrated structure.
  • the control electrode T71 of the second reset transistor T7 of the pixel circuit of this row, the control electrode of the first reset transistor of the pixel circuit of the next row, and the first reset control line RST1' may be an integrated structure.
  • this embodiment is not limited to this.
  • the second conductive layer 12 of the display substrate may include: a first initial signal line (eg, first initial signal lines INIT1a and INIT1b), a second initial signal line (for example, the second initial signal lines INIT2a and INIT2b), the second electrode Cst-2 of the storage capacitor Cst, and the shield electrode BK.
  • the second electrode Cst-2 of the storage capacitor Cst has a hollow area.
  • the orthographic projection of the control electrode T31 of the driving transistor T3 on the base substrate can cover the orthographic projection of the hollow area on the base substrate.
  • the orthographic projection of the hollow area on the base substrate may be a polygon. However, this embodiment is not limited to this.
  • the third insulating layer 103 of the display substrate is provided with a plurality of via holes, including, for example, first via holes V1 to fifteenth via holes V15 .
  • the third insulating layer 103 , the second insulating layer 102 and the first insulating layer 101 in the first to eighth vias V1 to V6 are removed, exposing the surface of the semiconductor layer 10 .
  • the third insulating layer 103 and the second insulating layer 102 in the ninth via hole V9 are removed, exposing the surface of the first conductive layer 11 .
  • the third insulating layer 103 in the tenth to fifteenth via holes V10 to V15 is removed, exposing the surface of the second conductive layer 12 .
  • the third conductive layer 13 of the display substrate may include: a data line DL, a first power line PL1 and a plurality of connection electrodes (for example, the first connection electrode CP1 to the sixth connection electrode CP6).
  • the data line DL may be electrically connected to the first doped region of the active layer T40 of the data writing transistor T4 through the third via hole V3.
  • the first power line PL1 can be electrically connected to the shield electrode BK through the twelfth via hole V12, and can also be electrically connected to the second electrode Cst-2 of the storage capacitor Cst through the thirteenth via hole V13.
  • the shielding electrode BK is configured to shield the impact of the data voltage jump on the key nodes, prevent the data voltage jump from affecting the potential of the key nodes of the pixel circuit, and improve the display effect.
  • the first connection electrode CP1 may be electrically connected to the first doped region of the active layer T10 of the first reset transistor T1 through the first via hole V1, and may also be electrically connected to the first initial signal line INIT1a through the tenth via hole V10.
  • the second connection electrode CP2 can be electrically connected to the first doping region of the active layer T20 of the threshold compensation transistor T2 through the second via hole V2, and can also be electrically connected to the control electrode T31 of the driving transistor T3 through the ninth via hole V9.
  • the third connection electrode CP3 may be electrically connected to the second doped region of the active layer T60 of the second light emission control transistor T6 through the fifth via hole V5.
  • the fourth connection electrode CP4 can be electrically connected to the first doped region of the active layer T70 of the second reset transistor T7 through the sixth via hole V6, and can also be electrically connected to the second initial signal line INIT2b through the fifteenth via hole V15.
  • the fifth connection electrode CP5 can be electrically connected to the first doped region of the active layer of the second reset transistor of the previous row of pixel circuits through the seventh via hole V7, and can also be connected to the second initial signal line through the eleventh via hole V11. INIT2a electrical connection.
  • the sixth connection electrode CP6 can be electrically connected to the first doped region of the active layer of the first reset transistor of the next row of pixel circuits through the eighth via hole V8, and can also be connected to the first initial signal line through the fourteenth via hole V14. INIT1b electrical connection.
  • the first display area A1 may be provided with a plurality of first light-emitting elements 21 and a plurality of pixel circuits
  • the second display area A2 may be provided with a plurality of second light-emitting elements 22 .
  • the plurality of pixel circuits may include: a plurality of first pixel circuits 31, a plurality of second pixel circuits 32, and a plurality of invalid pixel circuits.
  • At least one first pixel circuit 31 and at least one first light-emitting element 21 may be electrically connected through a first conductive line L1, and at least one first pixel circuit 31 is configured to drive at least one first light-emitting element 21 to emit light.
  • the at least one second pixel circuit 32 and the at least one second light-emitting element 22 may be electrically connected through the second conductive line L2, and the at least one second pixel circuit 32 is configured to drive the at least one second light-emitting element 22 to emit light.
  • Setting up an invalid pixel circuit can help improve the uniformity of components with multiple film layers in the etching process.
  • the invalid pixel circuit has the same structure as the first pixel circuit 31 and the second pixel circuit 32 of the row or column in which it is located, except that it is not connected to any light-emitting element.
  • the light transmittance of the first display area A1 is smaller than the light transmittance of the second display area A2. Only pixel circuits are provided in the first display area A1 and no pixel circuits are provided in the second display area A2, which can improve the light transmittance of the second display area A2.
  • the density of the second light-emitting elements 22 in the second display area A2 may be less than or equal to the density of the first light-emitting elements 21 in the first display area A1.
  • this embodiment is not limited to this.
  • the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2.
  • this embodiment is not limited to this.
  • FIG. 7 is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • several first light-emitting elements 21 and pixel circuits 30 in the first display area A1 are taken as an example for schematic illustration.
  • a plurality of pixel circuits arranged in sequence along the row direction X may be called a row of pixel circuits
  • a plurality of pixel circuits arranged in sequence along the column direction Y may be called a column of pixel circuits.
  • the row direction X intersects the column direction Y.
  • the row direction X may be perpendicular to the column direction Y.
  • the first display area A1 is not only provided with the first pixel circuit 31 electrically connected to the first light-emitting element 21 , but is also provided with the second light-emitting element 22
  • the second pixel circuits 32 are electrically connected. Therefore, the number of pixel circuits 30 in the first display area A1 is greater than the number of the first light-emitting elements 21 .
  • the area where the second pixel circuit is provided is obtained by reducing the size of the first pixel circuit in the first direction.
  • the size of the pixel circuit in the first direction may be smaller than the size of the first light emitting element in the first direction.
  • the first direction may be the row direction X.
  • the original pixel circuits of each column a can be compressed along the horizontal direction
  • the space occupied by the circuit is the same.
  • a can be an integer greater than 1.
  • a can be equal to 2.
  • the first direction may be the column direction Y.
  • the original b-row pixel circuit can be compressed along the vertical direction Y, thereby adding a new row of pixel circuit arrangement space, and the space occupied by the b-row pixel circuit before compression and the b+1 row pixel circuit after compression is same.
  • b can be an integer greater than 1.
  • the area where the second pixel circuit is provided may be obtained by reducing the size of the first pixel circuit in the row and column directions.
  • one pixel circuit 30 can be electrically connected to the first light-emitting element 21 or the second light-emitting element through the first connection hole 300 , and the first light-emitting element 21 can be electrically connected through the second connection hole 300 .
  • the hole 210 is electrically connected to the corresponding first pixel circuit.
  • the first pixel circuit may be electrically connected to the first conductive line through the first connection hole 300, and the first conductive line may be electrically connected to the corresponding first light-emitting element 21 through the second connection hole 210.
  • the second pixel circuit can be electrically connected to the second conductive line through the first connection hole 300, and the second conductive line can extend to the second display area and be electrically connected to the second light-emitting element in the second display area.
  • FIG. 8 is a schematic diagram of a display area according to at least one embodiment of the present disclosure.
  • the second display area A2 is generally symmetrical about the central axis OO' in the row direction X.
  • the second display area A2 may include a first area A21 and a second area A22, and the first area A21 and the second area A22 may be substantially symmetrical about the central axis OO'.
  • the first display area A1 may include a first auxiliary area A11 adjacent to the first partition A21 of the second display area A2 in the row direction X, and a second auxiliary area adjacent to the second partition A22 in the row direction X.
  • the second pixel circuit electrically connected to the second light-emitting element of the first sub-area A21 may be disposed in the first auxiliary area A11; the second pixel circuit electrically connected to the second light-emitting element of the second sub-area A22 may be disposed in the second auxiliary area A12.
  • the following takes the conductive lines electrically connecting the pixel circuit and the light-emitting element between the first partition A21 and the first auxiliary area A11 as an example for illustration.
  • FIG. 9 is a schematic connection diagram of the second display area and the first display area according to at least one embodiment of the present disclosure.
  • the first partition A21 of the second display area A2 may include: sequentially arranged along the side away from the first auxiliary area A11 in the row direction X.
  • Multiple second sub-display areas for example, include two second sub-display areas (that is, M in this example may be 2).
  • the first second sub-display area A2a may be located on a side of the second second sub-display area A2b away from the first auxiliary area A11.
  • the first auxiliary area A11 of the first display area A1 may include: a plurality of first sub-display areas arranged sequentially along the side away from the first partition A21 in the row direction X, for example, including a first first sub-display area Area A1a to the tenth first sub-display area A1j (that is, N in this example may be 10), where the first first sub-display area A1a is closest to the first partition A21, and the tenth first sub-display area A1j It is farthest from the first subdivision A21.
  • the two adjacent first sub-display areas may be continuous areas, that is, no other pixel circuits and light-emitting elements may be disposed between the two adjacent first sub-display areas.
  • the first first sub-display area A1a and the second second sub-display area A2b may be adjacent and continuous areas, that is, there may be no gap between the first sub-display area A1a and the second second sub-display area A2b. other areas.
  • the second pixel circuit may be arranged immediately adjacent to the second display area A2.
  • this embodiment is not limited to this.
  • first first sub-display area A1a and the second second sub-display area A2b may be discontinuous areas, such as the first first sub-display area A1a and the second second sub-display area A1a.
  • a first pixel circuit and a first light-emitting element that do not belong to the first sub-display area may be disposed between the areas A2b.
  • the arrangement position of the second pixel circuit is not adjacent to the second display area A2, and the arrangement position of the second pixel circuit and the second display area A2 may be separated by a certain distance.
  • the first conductive line electrically connecting the first light-emitting element and the first pixel circuit is a transparent conductive line
  • the second conductive line electrically connecting the second light-emitting element and the second pixel circuit is a transparent conductive line.
  • the second conductive line may include: a first transparent conductive line 52a and a second transparent conductive line 52b; and the first conductive line may include: a third transparent conductive line 51a to a twelfth transparent conductive line 51j.
  • the second light-emitting element of the first second sub-display area A2a can be connected to the second pixel of the first first sub-display area A1a through the first transparent conductive line 52a. Circuit electrical connection.
  • the second light-emitting element of the second second sub-display area A2b may be electrically connected to the second pixel circuit of the second second sub-display area A1b through the second transparent conductive line 52b.
  • the second light-emitting element in the second sub-display area (eg, the second sub-display area A2a) far away from the first auxiliary area A11 may be connected to the first sub-display area (eg, the first sub-display area A2a) close to the first sub-area A21.
  • the second pixel circuit in the sub-display area A1a) is electrically connected, and the second light-emitting element in the second sub-display area (for example, the second sub-display area A2b) close to the first auxiliary area A11 can be connected to the second pixel circuit far away from the first sub-area A21.
  • the second pixel circuit in a sub-display area (for example, the first sub-display area A1b) is electrically connected.
  • the second light-emitting elements in the second sub-display area eg, the second sub-display area A2a
  • the first auxiliary area A11 may be different from the first sub-display area (eg, the second sub-display area A2a) away from the first sub-area A21.
  • the second pixel circuit of the first sub-display area A1b) is electrically connected, and the second light-emitting element of the second sub-display area (for example, the second sub-display area A2b) close to the first auxiliary area A11 can be connected to the second pixel circuit close to the first sub-area A21.
  • the second pixel circuit in the first sub-display area eg, the first sub-display area A1a is electrically connected.
  • the first light-emitting element of the first first sub-display area A1a can pass through the third transparent conductive line 51a and the first pixel of the third first sub-display area A1c. Circuit electrical connection.
  • the first light-emitting element of the second first sub-display area A1b may be electrically connected to the first pixel circuit of the fourth first sub-display area A1d through the fourth transparent conductive line 51b.
  • the first light-emitting element of the third first sub-display area A1c may be electrically connected to the first pixel circuit of the fifth first sub-display area A1e through the fifth transparent conductive line 51c.
  • the first light-emitting element of the fourth first sub-display area A1d may be electrically connected to the first pixel circuit of the sixth first sub-display area A1f through the sixth transparent conductive line 51d.
  • the first light-emitting element of the fifth first sub-display area A1e may be electrically connected to the first pixel circuit of the seventh first sub-display area A1g through the seventh transparent conductive line 51e.
  • the first light-emitting element of the sixth first sub-display area A1f may be electrically connected to the first pixel circuit of the eighth first sub-display area A1h through the eighth transparent conductive line 51f.
  • the first light-emitting element of the seventh first sub-display area A1g may be electrically connected to the first pixel circuit of the ninth first sub-display area A1i through the ninth transparent conductive line 51g.
  • the first light-emitting element of the eighth first sub-display area A1h may be electrically connected to the first pixel circuit of the tenth first sub-display area A1j through the tenth transparent conductive line 51h.
  • the first light-emitting element of the ninth first sub-display area A1i can be connected to the area away from the tenth first sub-display area A1j through the eleventh transparent conductive line 51i (for example, an eleventh first sub-display area A1j can be provided).
  • the first pixel circuit in the display area is electrically connected, and the first light-emitting element of the tenth first sub-display area Alj can be connected to the area away from the tenth first sub-display area Alj (for example, through the twelfth transparent conductive line 51j
  • the first pixel circuit in the twelfth first sub-display area can be electrically connected until all the first light-emitting elements in the first auxiliary area A11 can be electrically connected to the first pixel circuit.
  • This example does not limit the number of first sub-display areas. In some examples, the number of first sub-display areas may be determined based on the number of pixel circuits or light-emitting elements in the first sub-display area.
  • the number of pixel circuits in the last first sub-display area may be less than or equal to 2. .
  • the number of first sub-display areas may be determined based on the length of transparent conductive lines electrically connected to the light-emitting elements or pixel circuits in the first sub-display area, for example, the number of first sub-display areas in the last sub-display area.
  • the length of the transparent conductive wire electrically connected to the light-emitting element is less than or equal to the preset value.
  • this embodiment is not limited to this.
  • the first light-emitting element of the n-th first sub-display area is electrically connected to the first pixel circuit of the n+2-th first sub-display area, that is, i in this example may be 2.
  • this embodiment is not limited to this.
  • the first light-emitting element of the first first sub-display area A1a may be electrically connected to the first pixel circuit of the fourth first sub-display area A1d
  • a light-emitting element may be electrically connected to the first pixel circuit of the third first sub-display area A1d, and so on.
  • the pixel circuits in the first first sub-display area A1a and the second first sub-display area A1b may both be second pixel circuits in order to drive the first partition.
  • the pixel circuits in the third to tenth first sub-display areas A1c to A1j may all be first pixel circuits in order to drive the first light-emitting element.
  • the electrical connection between the second pixel circuits and the second light-emitting elements can be reduced.
  • the length of the transparent conductive lines between components improves the situation where the length difference of the transparent conductive lines is too large, thereby improving the uniformity of the display effect.
  • FIG. 10 is an example diagram of a transparent conductive thread according to at least one embodiment of the present disclosure.
  • the display substrate may include: multiple transparent conductive layers located on the side of the pixel circuit away from the substrate substrate, for example, including three transparent conductive layers, namely the first transparent conductive layer 41 , the second transparent conductive layer 42 and the third transparent conductive layer 43.
  • the second transparent conductive layer 42 may be located on a side of the first transparent conductive layer 41 away from the base substrate
  • the third transparent conductive layer 43 may be located on a side of the second transparent conductive layer 42 away from the base substrate.
  • Any transparent conductive layer may include a plurality of transparent conductive lines.
  • both the first transparent conductive layer 41 and the second transparent conductive layer 42 may include a plurality of first conductive lines electrically connecting the first light-emitting element and the first pixel circuit, and a plurality of first conductive lines electrically connecting the second light-emitting element and the second pixel.
  • the third transparent conductive layer 43 may include a plurality of first conductive lines electrically connecting the first light emitting element and the first pixel circuit.
  • this embodiment is not limited to this.
  • the second conductive line electrically connecting the second light-emitting element and the second pixel circuit may be provided on the second transparent conductive layer and the third transparent conductive layer, or may be provided on the first transparent conductive layer and the third transparent conductive layer.
  • the transparent conductive lines of the first transparent conductive layer 41 are represented by solid lines
  • the transparent conductive lines of the second transparent conductive layer 42 are represented by dotted lines
  • the transparent conductive lines of the third transparent conductive layer 43 are represented by dotted lines.
  • FIG. 11A is a schematic diagram of the connection of transparent conductive lines in the first and second sub-display areas according to at least one embodiment of the present disclosure.
  • FIG. 11B is a schematic diagram of the connection of transparent conductive lines in the second second sub-display area according to at least one embodiment of the present disclosure.
  • Figure 11C is a schematic diagram of the connection of transparent conductive lines in the first first sub-display area according to at least one embodiment of the present disclosure.
  • 11D is a schematic diagram of the connection of transparent conductive lines in the second first sub-display area according to at least one embodiment of the present disclosure.
  • 11E is a schematic diagram of the connection of transparent conductive lines in the third first sub-display area and the fourth first sub-display area according to at least one embodiment of the present disclosure.
  • 11F is a schematic diagram of the connection of transparent conductive lines in the fifth first sub-display area and the sixth first sub-display area according to at least one embodiment of the present disclosure.
  • 11G is a schematic diagram of the connection of transparent conductive lines from the seventh first sub-display area to the tenth first sub-display area according to at least one embodiment of the present disclosure. In FIGS. 11A to 11G , only the connection relationship between one row of pixel circuits and light-emitting elements is illustrated.
  • each second sub-display area may include only one column of second light-emitting elements.
  • the second light-emitting element 22 in the first second sub-display area A2a can be connected to the first first sub-display area A1b through the first transparent conductive line 52a.
  • the second pixel circuit 32 is electrically connected.
  • the plurality of first transparent conductive lines 52a electrically connected to the plurality of second light-emitting elements 22 in the first second sub-display area A2a may all be located on the first transparent conductive layer 41.
  • the first transparent conductive line 52a may extend from the first second sub-display area A2a through the second second sub-display area A2b into the first first sub-display area A1a.
  • the second light-emitting element 22 in the second second sub-display area A2b may be electrically connected to the second pixel circuit 32 in the second second sub-display area A1b through the second transparent conductive line 52b.
  • the plurality of second transparent conductive lines 52b electrically connected to the plurality of second light-emitting elements 22 in the second second sub-display area A2b may all be located on the second transparent conductive layer 42.
  • the second transparent conductive line 52b may extend from the second second sub-display area A2b through the first first sub-display area A1a into the second first sub-display area A1b.
  • the second light-emitting element 22 in the first second sub-display area A2a that is far away from the first auxiliary area A11 may be connected to the first first sub-display area A1a
  • the second pixel circuit 32 in the first second sub-display area A2a is electrically connected to the second pixel circuit 32 far away from the second display area A2.
  • the second pixel circuit 32 close to the second display area A2 is electrically connected.
  • the second light-emitting element 22 in the second second sub-display area A2b that is far away from the first auxiliary area A11 can be electrically connected to the second pixel circuit 32 in the second first sub-display area A1b that is far away from the second display area A2.
  • the second light-emitting element 22 in the two second sub-display areas A2b close to the first auxiliary area A11 may be electrically connected to the second pixel circuit 32 in the second first sub-display area A1b close to the second display area A2.
  • the connection method between the second light-emitting element 22 and the second pixel circuit 32 in this example can avoid problems such as short circuit or interference caused by overlapping of transparent conductive lines.
  • the number of second pixel circuits 32 in the first first sub-display area A1a is the same as the number of second pixel circuits 32 in the first second sub-display area A2a.
  • the number of elements 22 may be the same, and the number of second pixel circuits 32 in the second first sub-display area A1b and the number of second light-emitting elements 22 in the second second sub-display area A2b may be the same.
  • the number of the second light-emitting elements 22 in the first second sub-display area A2a and the number of the second light-emitting elements 22 in the second second sub-display area A2b may be approximately the same.
  • the number of second pixel circuits 32 in the first first sub-display area A1a and the number of second pixel circuits 32 in the second first sub-display area A1b may be approximately the same. However, this embodiment is not limited to this. For example, the number of second light-emitting elements 22 in the first second sub-display area A2a and the second second sub-display area A2b may be different. The number of second pixel circuits 32 in the first first sub-display area A1a and the second first sub-display area A1b may be different.
  • the first first sub-display area A1a and the second first sub-display area A1b may each include multiple columns of second pixel circuits 32 and multiple columns of second pixel circuits 32 .
  • a light-emitting element 21 Since the size of the second pixel circuit 32 in the row direction X is smaller than the size of the first light-emitting elements 21 in the row direction The number of circuits 32 and the number of first light-emitting elements 21 in the second first sub-display area A1b is smaller than the number of second pixel circuits 32 .
  • the first light-emitting element 21 of the first first sub-display area A1a can be connected to the third first sub-display area A1c through the third transparent conductive line 51a.
  • the first pixel circuit 31 is electrically connected.
  • the plurality of third transparent conductive lines 51a electrically connected to the plurality of first light-emitting elements 21 in the first first sub-display area A1a may all be located on the third transparent conductive layer 43.
  • the third transparent conductive line 51a may extend from the first first sub-display area A1a through the second first sub-display area A1b to the third first sub-display area A1c.
  • the first light-emitting element 21 in the second first sub-display area A1b may be electrically connected to the first pixel circuit 31 in the fourth second sub-display area A1d through the fourth transparent conductive line 51b.
  • the plurality of fourth transparent conductive lines 51b electrically connected to the plurality of first light-emitting elements 21 in the second first sub-display area A1b may all be located on the first transparent conductive layer 41.
  • the fourth transparent conductive line 51b may extend from the second first sub-display area A1b through the third first sub-display area A1c to the fourth first sub-display area A1d.
  • the first light-emitting element 21 in the first first sub-display area A1a close to the second display area A2 and the third first sub-display area A1c are The first pixel circuit 31 far away from the second display area A2 is electrically connected, and the first light-emitting element 21 far away from the second display area A2 in the first first sub-display area A1a is close to the first light-emitting element 21 in the third first sub-display area A1c.
  • the first pixel circuits 31 of the two display areas A2 are electrically connected.
  • the first light-emitting element 21 in the second first sub-display area A1b close to the second display area A2 is electrically connected to the first pixel circuit 31 in the fourth first sub-display area A1d far away from the second display area A2.
  • the first light-emitting element 21 in the first sub-display area A1b that is far away from the second display area A2 is electrically connected to the first pixel circuit 31 in the fourth first sub-display area A1d that is close to the second display area A2.
  • the connection method between the first light-emitting element 21 and the first pixel circuit 31 in this example can avoid problems such as short circuit or interference caused by overlap of transparent conductive lines.
  • the first light-emitting element 21 in the third first sub-display area A1c and the first pixel circuit 31 in the fifth first sub-display area A1e are electrically connected.
  • the fifth transparent conductive line 51c may be located on the second transparent conductive layer 42.
  • the sixth transparent conductive line 51d electrically connecting the first light-emitting element 21 in the fourth first sub-display area A1d and the first pixel circuit 31 in the sixth first sub-display area A1f may be located on the third transparent conductive layer 43 .
  • the seventh transparent conductive line 51e electrically connecting the first light-emitting element 21 in the fifth first sub-display area A1e and the first pixel circuit 31 in the seventh first sub-display area A1g may be located on the first transparent conductive layer 41 .
  • the eighth transparent conductive line 51f electrically connecting the first light-emitting element 21 in the sixth first sub-display area A1f and the first pixel circuit 31 in the eighth first sub-display area A1h may be located on the second transparent conductive layer 42 .
  • the ninth transparent conductive line 51g electrically connecting the first light-emitting element 21 in the seventh first sub-display area A1g and the first pixel circuit 31 in the ninth first sub-display area A1i may be located on the third transparent conductive layer 43 .
  • the tenth transparent conductive line 51h electrically connecting the first light-emitting element 21 in the eighth first sub-display area A1h and the first pixel circuit 31 in the tenth first sub-display area A1j may be located on the first transparent conductive layer 41 .
  • the eleventh transparent conductive line 51i electrically connected to the first light-emitting element 21 of the ninth first sub-display area A1i may be located on the second transparent conductive layer 42, and the first light-emitting element 21 of the tenth first sub-display area Alj is electrically connected.
  • the connected twelfth transparent conductive line 51j may be located on the third transparent conductive layer 43.
  • connection method between the first light-emitting element 21 of one first sub-display area and the first pixel circuit 31 of another first sub-display area reference can be made to the connection method of the second light-emitting element 22 and the second pixel circuit 32. Therefore, here No longer.
  • the pixel circuits in the first first sub-display area A1a and the second first sub-display area A1b may both be second pixel circuits.
  • the pixel circuits in the third to tenth first sub-display areas A1c to A1j may all be first pixel circuits.
  • the number of first light-emitting elements in any first sub-display area may be less than or equal to the number of first light-emitting elements in an adjacent first sub-display area on the side of the first sub-display area close to the second display area.
  • the number of light-emitting elements For example, the number of first light-emitting elements 21 in the second first sub-display area A1b may be smaller than the number of first light-emitting elements 21 in the first first sub-display area A1a, and the number of first light-emitting elements 21 in the third first sub-display area A1c
  • the number of first light-emitting elements 21 may be smaller than the number of first light-emitting elements in the second first sub-display area A1a.
  • the size of the first sub-display area may decrease as the side moves away from the first partition A21.
  • the pixel circuits in the third first sub-display area A1c and the first sub-display area on the side of the third first sub-display area A1c away from the second display area may both be first pixel circuits.
  • the number of first pixel circuits 31 in the third first sub-display area A1c may be smaller than the number of first pixel circuits 31 in the first first sub-display area A1a.
  • the number of first pixel circuits 31 in any first sub-display area may be less than or equal to the number of the first sub-display area close to the first sub-display area A1j.
  • the transparent conductive lines electrically connected to the plurality of first light-emitting elements 21 in a first sub-display area may be of the same layer structure.
  • the transparent conductive lines electrically connected to the first light-emitting element 21 in a first sub-display area and the transparent conductive lines electrically connected to the pixel circuit in the first sub-display area may have different layer structures.
  • the third transparent conductive line 51a electrically connected to the first light-emitting element 21 in the first first sub-display area A1a may be located on the third transparent conductive layer, and the second pixel circuit in the first first sub-display area A1a
  • the electrically connected first transparent conductive line 52a may be located on the first transparent conductive layer. In this way, mutual interference between transparent conductive lines can be reduced.
  • FIG. 12 is a schematic diagram of a first transparent conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a second transparent conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a third transparent conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of three transparent conductive layers according to at least one embodiment of the present disclosure.
  • Figures 12 to 15 illustrate the connection relationship between multi-row pixel circuits and light-emitting elements. The connection relationship between single-row pixel circuits and light-emitting elements can be referred to Figures 11A to 11G.
  • the first transparent conductive line 52a, the fourth transparent conductive line 51b, the seventh transparent conductive line 51e, and the tenth transparent conductive line 51h may be located on the first transparent conductive line 52a.
  • the second transparent conductive line 52b, the fifth transparent conductive line 51c, the eighth transparent conductive line 51f, and the eleventh transparent conductive line 51i may be located on the second transparent conductive layer 42.
  • the third transparent conductive line 51a, the sixth transparent conductive line 51d, the ninth transparent conductive line 51g, and the twelfth transparent conductive line 51j may be located on the third transparent conductive layer 43.
  • this embodiment is not limited to this.
  • the first transparent conductive line 52a, the fourth transparent conductive line 51b, the seventh transparent conductive line 51e and the tenth transparent conductive line 51h may be located on the second transparent conductive layer 42; the second transparent conductive line 52b, the fifth transparent conductive line 51c, the eighth transparent conductive line 51f and the eleventh transparent conductive line 51i may be located on the third transparent conductive layer 43; the third transparent conductive line 51a, the sixth transparent conductive line 51d, the ninth transparent conductive line 51g and the twelfth transparent conductive line 51c.
  • the conductive line 51j may be located on the first transparent conductive layer 41.
  • the display substrate may include four transparent conductive layers.
  • the first to twelfth transparent conductive lines 52a to 51j may be respectively arranged in four transparent conductive layers.
  • the longest transparent conductive line in this example can be used to electrically connect the second light-emitting element farthest from the first display area A1 in the first second sub-display area A2a and the first second sub-display area A2a.
  • this example can reduce The length of the transparent conductive wire that electrically connects the second light-emitting element 22 and the second pixel circuit 32 improves the situation where the length difference between the transparent conductive wires is too large, thereby improving the problem of poor picture uniformity in the under-screen display area and achieving a more uniform full-screen visual display effect.
  • the second auxiliary area A12 of the first display area A1 may include: in the second direction (parallel to the row direction X in this example) along a line away from the second partition A22 Multiple third sub-display areas arranged sequentially on one side.
  • the second partition A22 may include: a plurality of fourth sub-display areas sequentially arranged along a side away from the second auxiliary area A12 in the second direction.
  • the second light-emitting element in the fourth sub-display area can be electrically connected to the second pixel circuit in a third sub-display area through the second conductive line, and the first light-emitting element in the third sub-display area can be electrically connected through the first conductive line.
  • the line is electrically connected to the first pixel circuit in another third sub-display area on the side away from the second area A22.
  • the connection between the second partition A22 and the second auxiliary area A12 may be mirrored with respect to the central axis OO' according to the connection between the first partition A21 and the first auxiliary area A11.
  • the number of the third sub-display area may be the same as the number of the first sub-display area
  • the number of the second sub-display area may be the same as the number of the fourth sub-display area.
  • the connection pattern between the second partition A22 and the second auxiliary area A12 can be obtained with reference to the connection rule between the first partition A21 and the first auxiliary area A11.
  • the number of the third sub-display area and the number of the first sub-display area may be different, the number of the second sub-display area and the number of the fourth sub-display area may be different, and the third sub-display area and the fourth sub-display area may be different.
  • the connection mode of the pixel circuit and the light-emitting element may be different from the connection mode of the pixel circuit and the light-emitting element of the first sub-display area and the second sub-display area.
  • the first sub-display area and the second display area may be connected in the manner shown in FIG. 9
  • the third sub-display area and the fourth sub-display area may be connected in the similar manner shown in FIG. 18 or FIG. 19 .
  • this embodiment is not limited to this.
  • the preparation process of the display substrate is exemplified below.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the preparation process of the display substrate may include the following operations.
  • forming the semiconductor layer may include: depositing a semiconductor film on the base substrate 100, patterning the semiconductor film through a patterning process, and forming the semiconductor layer 10 in the first display area A1, as shown in FIG. 6A Show.
  • the active layer of seven transistors of a pixel circuit may be an integral structure connected to each other.
  • the material of the semiconductor layer 10 may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the plurality of doped regions may be on both sides of the channel region and be doped with impurities and thus be conductive. Impurities can vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as the source or drain electrode of the transistor. Portions of the active layer between transistors can be interpreted as wiring doped with impurities that can be used to electrically connect the transistors.
  • the substrate substrate 100 may be a rigid substrate, such as a glass substrate.
  • the base substrate may be a flexible substrate.
  • a first insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned through a patterning process to form a third layer covering the semiconductor layer.
  • a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form a layer covering the first conductive layer. 11 of the second insulating layer 102, and the second conductive layer 12 disposed on the second insulating layer 102 in the first display area A1, as shown in FIG. 6C.
  • a third insulating film is deposited on the base substrate 100 on which the foregoing pattern is formed, and the third insulating film is patterned through a patterning process to form a third insulating layer 103, as shown in FIG. 6D.
  • a third conductive film is deposited on the base substrate on which the foregoing pattern is formed, the third conductive film is patterned through a patterning process, and is formed on the third insulating layer 103 of the first display area A1
  • the third conductive layer 13 is shown in Figure 4 .
  • the second display area A2 may include: a base substrate 100 and a first insulating layer 101 , a second insulating layer 102 and a third insulating layer 103 stacked on the base substrate 100 .
  • first flattening layer a first transparent conductive layer, a second flattening layer, a second transparent conductive layer, a third flattening layer, a third transparent conductive layer, a fourth flattening layer, an anode layer, and a pixel definition layer in sequence.
  • organic light-emitting layer and cathode layer a first transparent conductive layer, a second flattening layer, a second transparent conductive layer, a third flattening layer, a third transparent conductive layer, a fourth flattening layer, an anode layer, and a pixel definition layer in sequence.
  • organic light-emitting layer and cathode layer organic light-emitting layer and cathode layer.
  • a first flat film is coated on the base substrate 100 on which the foregoing pattern is formed, and the first flat film is patterned through a patterning process to form a first flat layer.
  • a first transparent conductive film is deposited on the base substrate with the foregoing pattern, and the first transparent conductive film is patterned through a patterning process to form a first transparent conductive layer.
  • a second flat film is coated on the base substrate with the foregoing pattern, and the second flat film is patterned through a patterning process to form a second flat layer.
  • a second transparent conductive film is deposited on the base substrate with the foregoing pattern, and the second transparent conductive film is patterned through a patterning process to form a second transparent conductive layer.
  • a third flat film is coated on the base substrate with the foregoing pattern, and the third flat film is patterned through a patterning process to form a third flat layer.
  • a third transparent conductive film is deposited on the base substrate with the foregoing pattern, and the third transparent conductive film is patterned through a patterning process to form a third transparent conductive layer.
  • FIGS. 10 to 15 Regarding the arrangement of the transparent conductive lines of the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer, reference can be made to FIGS. 10 to 15 .
  • an anode film is deposited on the base substrate with the foregoing pattern, and the anode film is patterned through a patterning process to form an anode layer.
  • a pixel definition film is coated on the substrate on which the foregoing pattern is formed, and a pixel definition layer is formed through masking, exposure and development processes.
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer.
  • an organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode layer.
  • the cathode layer is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first conductive layer 11 , the second conductive layer 12 and the third conductive layer 13 may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). Any one or more of them, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). Any one or more of them, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Be single layer, multi-layer or composite layer.
  • the first insulating layer 101 and the second insulating layer 102 may be called a gate insulating (GI) layer, and the third insulating layer 103 may be called an interlayer insulating (ILD) layer.
  • the first to fourth flat layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited to this.
  • a fourth insulating layer and a fourth conductive layer may be provided on a side of the third conductive layer away from the base substrate, and the fourth conductive layer may include an anode connection electrode connecting the pixel circuit and the transparent conductive line.
  • the first conductive line electrically connecting the first light-emitting element and the first pixel circuit may be disposed on the fourth conductive layer.
  • one or two transparent conductive layers may be provided. However, this embodiment is not limited to this.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, and is well compatible with existing preparation processes.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • FIG. 16 is another schematic diagram of the connection between the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure.
  • the first second sub-display area A2a and the first first sub-display area A1a are taken as an example for illustration.
  • the second conductive lines electrically connected to the adjacent second light-emitting elements 22 may have a different-layer structure.
  • one of the second light-emitting elements 22 can be electrically connected to the second pixel circuit 32 in the first first sub-display area A1a through the thirteenth transparent conductive line 52a, and is connected to the second light-emitting element 22 in the row direction X.
  • An adjacent second light-emitting element 22 may be electrically connected to another second pixel circuit 32 in the first first sub-display area A1a through a fourteenth transparent conductive line 52b.
  • the thirteenth transparent conductive line 52a and the fourteenth transparent conductive line 52b may have a different layer structure, that is, they may be located on different transparent conductive layers.
  • the thirteenth transparent conductive line 52a may be located on the first transparent conductive layer
  • the fourteenth transparent conductive line 52b may be located on the fourth transparent conductive layer
  • the fourth transparent conductive layer may be located on a side of the third transparent conductive layer away from the substrate. side.
  • this embodiment is not limited to this.
  • connection method between the first light-emitting element in one first sub-display area and the first pixel circuit in another first sub-display area can be the same as that of the second light-emitting element 22 and the second pixel circuit 32 in this example.
  • the connection methods are similar, so I won’t go into details here.
  • FIG. 17 is another connection diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure.
  • the first second sub-display area A2a and the first first sub-display area A1a are taken as an example for illustration.
  • the second light-emitting element 22 in the first second sub-display area A2a close to the first display area can be connected with the second pixel circuit 32 in the first first sub-display area A1a far away from the second display area.
  • the second light-emitting element 22 in the first second sub-display area A2a that is far away from the first display area can be electrically connected with the second pixel circuit 32 in the first first sub-display area A1a that is close to the second display area.
  • the second light-emitting element 22 may be electrically connected to the second pixel circuit 32 in the first first sub-display area A1a through the fifteenth transparent conductive line 52c.
  • the fifteenth transparent conductive line 52c may be formed by connecting multiple conductive line segments. The plurality of conductive line segments may be located on different transparent conductive layers.
  • a fifteenth transparent conductive line 52c may include: a first conductive line segment located on the first transparent conductive layer, a second conductive line segment located on the second transparent conductive layer, and a third conductive line segment located on the first transparent conductive layer.
  • the first conductive line segment may be electrically connected to the second light-emitting element 22
  • the third conductive line segment may be electrically connected to the second pixel circuit 32
  • the second conductive line segment may connect the first conductive line segment and the third conductive line segment.
  • this embodiment is not limited to this.
  • connection method between the first light-emitting element in one first sub-display area and the first pixel circuit in another first sub-display area can be the same as that of the second light-emitting element 22 and the second pixel circuit 32 in this example.
  • the connection methods are similar, so I won’t go into details here.
  • Figure 18 is another schematic diagram of the connection between the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure.
  • the second light-emitting element of the first second sub-display area A2a may be electrically connected to the second pixel circuit of the second first sub-display area A1b through the sixteenth transparent conductive line 53a.
  • the second light-emitting element of the second sub-display area A2b may be electrically connected to the second pixel circuit of the first second sub-display area A1a through the seventeenth transparent conductive line 53b.
  • the sixteenth transparent conductive line 53a and the seventeenth transparent conductive line 53b may be located on the same transparent conductive layer, for example, may be located on the first transparent conductive layer. However, this embodiment is not limited to this. In other examples, the sixteenth transparent conductive line 53a and the seventeenth transparent conductive line 53b may be located on different transparent conductive layers.
  • FIG. 19 is yet another connection diagram of the first sub-display area and the second sub-display area according to at least one embodiment of the present disclosure.
  • the entire first partition A21 of the second display area can be used as a second sub-display area.
  • the first auxiliary area A11 adjacent to the second sub-display area may include: a plurality of first sub-display areas (for example, including the first first sub-area A11 sequentially arranged along the side away from the first partition A21 in the row direction sub-display area A1-1 to the fifth first sub-display area A1-5).
  • the second light-emitting element in the first sub-area A21 may be electrically connected to the second pixel circuit in the first first sub-display area A1-1 through the eighteenth transparent conductive line 61a.
  • the first light-emitting element in the first first sub-display area A1-1 may be electrically connected to the first pixel circuit in the second first sub-display area A1-2 through the nineteenth transparent conductive line 61b.
  • the first light-emitting element in the second first sub-display area A1-2 may be electrically connected to the first pixel circuit in the third first sub-display area A1-3 through the twentieth transparent conductive line 61c.
  • the first light-emitting element in the third first sub-display area A1-3 may be electrically connected to the first pixel circuit of the fourth first sub-display area A1-4 through the twenty-first transparent conductive line 61d.
  • the first light-emitting element in the fourth first sub-display area A1-4 may be electrically connected to the first pixel circuit in the fifth first sub-display area A1-5 through the twenty-second transparent conductive line 61e.
  • the first light-emitting element in the fifth first sub-display area A1-5 can be connected to the area on the side of the fifth first sub-display area A1-5 away from the second display area through the twenty-third transparent conductive line 61f.
  • the first pixel circuit is electrically connected.
  • the first light-emitting element of one first sub-display area may be electrically connected to the first pixel circuit in the adjacent first sub-display area on the side away from the second display area.
  • n can be 1
  • i can be 1.
  • the second conductive line may include: an eighteenth transparent conductive line 61a and a nineteenth transparent conductive line 61b; the first conductive line may include: a twentieth to twenty-third transparent conductive line 61c 61f.
  • the eighteenth transparent conductive line 61a and the nineteenth transparent conductive line 61b may have a different layer structure, that is, they may be located on different transparent conductive layers. This example sets up two transparent conductive layers.
  • the eighteenth transparent conductive line 61a, the twentieth transparent conductive line 61c, and the twenty-second transparent conductive line 61e may have the same layer structure and be located on the first transparent conductive layer.
  • the first transparent conductive line 61d and the twenty-third transparent conductive line 61f may have the same layer structure and be located on the second transparent conductive layer.
  • the second transparent conductive layer may be located on a side of the first transparent conductive layer away from the base substrate.
  • this embodiment is not limited to this.
  • the film layer arrangement of the transparent conductive thread in this embodiment reference can be made to the description of the previous embodiment, and therefore the details will not be described again.
  • FIG. 20 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the area where the second pixel circuit is provided can be obtained by reducing the size of the first pixel circuit in the column direction Y.
  • the first direction may be the column direction Y.
  • the first display area A1 may include: a third auxiliary area A13 adjacent to the second display area A2 in the column direction Y, and the third auxiliary area A13 may include: a third auxiliary area A13 along the column direction Y away from the second display area A13 .
  • a plurality of first sub-display areas are arranged sequentially on one side of the second display area A2.
  • the second display area A2 may include a plurality of second sub-display areas divided along the column direction Y, such as two second sub-display areas.
  • the second light-emitting element of the second sub-display area can be electrically connected to the second pixel circuit of the first sub-display area through the second conductive line 52, and the first light-emitting element of the first sub-display area can be electrically connected to the second pixel circuit of the first sub-display area through the first conductive line 51.
  • the first pixel circuit in the other first sub-display area on the side away from the second display area A2 in the column direction Y is electrically connected.
  • connection relationship between the first sub-display area and the second sub-display area and the connection method between the pixel circuit and the light-emitting element of this embodiment please refer to the description of the previous embodiment, and it can be obtained by simply changing the direction. Therefore no further details will be given here.
  • FIG. 21 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the top of the display area and on one side of the first display area A1 in the column direction Y.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the column direction Y.
  • this embodiment is not limited to this.
  • the first display area A1 may include: a plurality of first display areas A1 sequentially arranged along a side away from the second display area A2 in a first direction (parallel to the column direction Y in this example).
  • the second display area A2 may include a plurality of second sub-display areas divided along the column direction Y, or may be entirely used as one second sub-display area.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the second display area A2 through the second conductive line 52.
  • the first sub-display area A11a The first light-emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a away from the second display area A2 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area and the connection method between the pixel circuit and the light-emitting element in this embodiment reference can be made to the description of the previous embodiment, and therefore will not be described again.
  • FIG. 22 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located in the left half of the display area and on one side of the first display area A1 in the row direction X.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X.
  • this embodiment is not limited to this.
  • the first display area A1 may include: a plurality of first display areas A1 sequentially arranged along a side away from the second display area A2 in a first direction (parallel to the row direction X in this example).
  • the second display area A2 may include a plurality of second sub-display areas divided along the row direction X, or may be entirely used as one second sub-display area.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the second display area A2 through the second conductive line 52.
  • the first sub-display area A11a The first light-emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the second display area A2 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area and the connection method between the pixel circuit and the light-emitting element in this embodiment reference can be made to the description of the previous embodiment, and therefore will not be described again.
  • FIG. 23 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located in the middle area of the display area and adjacent to the first display area A1 on both sides in the row direction X.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X.
  • this embodiment is not limited to this.
  • the second display area A2 may include: a first partition A21 and a second partition A22 divided along the row direction X.
  • the first partition A21 may include a plurality of second sub-display areas divided along the first direction (parallel to the row direction X in this example), or the first partition A21 may serve as a second sub-display area as a whole.
  • the second partition A22 may include a plurality of fourth sub-display areas divided along the second direction (parallel to the row direction X in this example), or the second partition A22 may serve as a fourth sub-display area as a whole.
  • the first partition A21 and the second partition A22 may be substantially symmetrical about the central axis of the second display area A2 in the row direction X. However, this embodiment is not limited to this.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, and a plurality of first sub-display areas A11a in the second direction.
  • a plurality of third sub-display areas A12a are arranged sequentially along the side away from the second partition A22.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area Regarding the connection relationship between the first sub-display area and the second sub-display area, the connection relationship between the third sub-display area and the fourth sub-display area, and the connection method between the pixel circuit and the light-emitting element of this embodiment Reference may be made to the description of the foregoing embodiments, so the details are not repeated here.
  • FIG. 24 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the upper left corner of the display area, and the second display area A2 is adjacent to the first display area A1 in both the row direction X and the column direction Y.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y.
  • this embodiment is not limited to this.
  • the second display area A2 may include: a first partition A21 and a second partition A22.
  • the first partition A21 may include a plurality of second sub-display areas divided along the first direction (parallel to the column direction Y in this example), or the first partition A21 as a whole may serve as one second sub-display area.
  • the second partition A22 may include a plurality of fourth sub-display areas divided along the second direction (parallel to the row direction X in this example), or the entire second partition A22 may serve as one fourth sub-display area.
  • the first area A21 and the second area A22 may be substantially symmetrical about a diagonal line of the second display area A2.
  • this embodiment is not limited to this.
  • the first partition A21 and the second partition A22 may be substantially symmetrical about the central axis of the second display area A2 in the row direction X or the column direction Y.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, and a plurality of first sub-display areas A11a in the second direction.
  • a plurality of third sub-display areas A12a are arranged sequentially along the side away from the second partition A22.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area Regarding the connection relationship between the first sub-display area and the second sub-display area, the connection relationship between the third sub-display area and the fourth sub-display area, and the connection method between the pixel circuit and the light-emitting element of this embodiment Reference may be made to the description of the foregoing embodiments, so the details are not repeated here.
  • FIG. 25 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area A2.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y.
  • the second display area A2 may include a first partition A21 and a second partition A22.
  • the first partition A21 and the second partition A22 may be substantially symmetrical about the central axis OO' of the second display area A2 in the row direction X. .
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction (parallel to the row direction X in this example), and a plurality of first sub-display areas A11a in the second direction.
  • a plurality of third sub-display areas A12a are sequentially arranged along the side away from the second partition A22 (parallel to the column direction Y in this example).
  • the first partition A21 may include a plurality of second sub-display areas divided along the first direction, or the entire first partition A21 may serve as one second sub-display area.
  • the second area A22 may include a plurality of fourth sub-display areas divided along the second direction, or the entire second area A22 may serve as a fourth sub-display area.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • FIG. 26 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area A2.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y.
  • the second display area A2 may include: a first area A21, a second area A22, and a third area A23.
  • the first partition A21, the second partition A22, and the third partition A23 can be obtained by dividing the second display area A2 in the row direction X.
  • the first partition A21 may include a plurality of second sub-display areas divided along the first direction (parallel to the row direction X in this example), or the first partition A21 may serve as one second sub-display area as a whole.
  • the second area A22 may include a plurality of fourth sub-display areas divided along the second direction (parallel to the row direction X in this example), or the second area A22 may serve as a fourth sub-display area as a whole.
  • the third partition A23 may include a plurality of sixth sub-display areas divided along the third direction (parallel to the column direction Y in this example), or the third partition A23 may serve as a sixth sub-display area as a whole.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, A plurality of third sub-display areas A12a are arranged in sequence along the side away from the second partition A22, and a plurality of fifth sub-display areas A13a are arranged in sequence along the side away from the third partition A23 in the third direction.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • the second light-emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third area A23 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area the connection relationship between the third sub-display area and the fourth sub-display area, the fifth sub-display area and the sixth sub-display area in this embodiment
  • connection relationship between them and the connection method between the pixel circuit and the light-emitting element can refer to the description of the previous embodiments, and therefore will not be described again here.
  • FIG. 27 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area A2.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the column direction Y and the row direction X.
  • this embodiment is not limited to this.
  • the second display area A2 may include: a first area A21, a second area A22, a third area A23, and a fourth area A24.
  • the first partition A21, the second partition A22, the third partition A23 and the fourth partition A24 can be obtained by dividing the second display area A2 in the row direction X and the column direction Y, or can be obtained by dividing the second display area A2 Divided along the diagonal direction.
  • this embodiment is not limited to this.
  • the first partition A21 may include a plurality of second sub-display areas divided along the first direction (parallel to the row direction).
  • the second area A22 may include a plurality of fourth sub-display areas divided along the second direction (parallel to the row direction X in this example), or the second area A22 may serve as a fourth sub-display area as a whole.
  • the third partition A23 may include a plurality of sixth sub-display areas divided along the third direction (parallel to the column direction Y in this example), or the third partition A23 may serve as a sixth sub-display area as a whole.
  • the fourth partition A24 may include a plurality of eighth sub-display areas divided along the fourth direction (parallel to the column direction Y in this example), or the fourth partition A24 may serve as an entire eighth sub-display area.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, A plurality of third sub-display areas A12a are arranged in sequence along the side away from the second partition A22, a plurality of fifth sub-display areas A13a are arranged in sequence along the side away from the third partition A23 in the third direction, and in the fourth A plurality of seventh sub-display areas A14a are arranged sequentially along the side away from the fourth partition A24.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • the second light-emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third area A23 through the first conductive line 51.
  • the second light-emitting element in the eighth sub-display area may be electrically connected to the second pixel circuit in the seventh sub-display area A14a closest to the fourth sub-area A24 through the second conductive line 52.
  • the seventh sub-display area A14a The first light-emitting element may be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth area A24 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area the connection relationship between the third sub-display area and the fourth sub-display area, the fifth sub-display area and the sixth sub-display area in this embodiment
  • connection relationship between them, the connection relationship between the seventh sub-display area and the eighth sub-display area, and the connection method between the pixel circuit and the light-emitting element can refer to the description of the previous embodiments, and will not be described again here.
  • FIG. 28 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the second display area A2 may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area A2 on three sides.
  • the upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, left side and right side of the second display area A2.
  • FIG. 26 Regarding the area division and connection relationship between the first display area and the second display area in this embodiment, reference can be made to FIG. 26 , so the details will not be described again.
  • FIG. 29 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the area where the second pixel circuit is disposed may be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y.
  • this embodiment is not limited to this.
  • the second display area may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area.
  • the second display area may include: a first area A21, a second area A22, a third area A23, and a fourth area A24.
  • the first partition A21, the second partition A22, the third partition A23 and the fourth partition A24 can be divided by dividing the second display area A2 according to the central axis RR' in the fifth direction F and the central axis PP' in the sixth direction E. get.
  • both the fifth direction F and the sixth direction E intersect the row direction X and the column direction Y.
  • the fifth direction F and the sixth direction E may intersect perpendicularly, the fifth direction F may be located between the row direction X and the column direction Y, and the clockwise angle between the fifth direction F and the row direction X may be approximately is 45 degrees.
  • this embodiment is not limited to this.
  • the angle in the clockwise direction between the fifth direction F and the row direction X may be about 30 degrees to 60 degrees.
  • the first partition A21 may include: a plurality of second sub-display areas divided along the first direction (parallel to the row direction X in this example), or the first partition A21 may be entirely As a second sub-display area.
  • the second partition A22 may include a plurality of fourth sub-display areas divided along the second direction (parallel to the row direction X in this example), or the second partition A22 may serve as a fourth sub-display area as a whole.
  • the third partition A23 may include a plurality of sixth sub-display areas divided along the third direction (parallel to the column direction Y in this example), or the third partition A23 may serve as a sixth sub-display area as a whole.
  • the fourth partition A24 may include a plurality of eighth sub-display areas divided along the fourth direction (parallel to the column direction Y in this example), or the fourth partition A24 may serve as an eighth sub-display area as a whole.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, A plurality of third sub-display areas A12a are arranged in sequence along the side away from the second partition A22, a plurality of fifth sub-display areas A13a are arranged in sequence along the side away from the third partition A23 in the third direction, and in the A plurality of seventh sub-display areas A14a are arranged sequentially in four directions along the side away from the fourth partition A24.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • the second light-emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third area A23 through the first conductive line 51.
  • the second light-emitting element in the eighth sub-display area may be electrically connected to the second pixel circuit in the seventh sub-display area A14a closest to the fourth sub-area A24 through the second conductive line 52.
  • the seventh sub-display area A14a The first light-emitting element may be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth area A24 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area the connection relationship between the third sub-display area and the fourth sub-display area, the fifth sub-display area and the sixth sub-display area in this embodiment
  • connection relationship between them, the connection relationship between the seventh sub-display area and the eighth sub-display area, and the connection method between the pixel circuit and the light-emitting element can refer to the description of the previous embodiments, and will not be described again here.
  • FIG. 30 is another schematic diagram of the connection between the first display area and the second display area according to at least one embodiment of the present disclosure.
  • the area where the second pixel circuit is provided can be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y.
  • the second display area may be located at the top middle position of the display area, and the first display area A1 surrounds the second display area.
  • the second display area may include: a first area A21, a second area A22, a third area A23, and a fourth area A24.
  • the first to fourth partitions A21 to A24 can be divided according to the central axis OO' of the second display area in the row direction X and the central axis UU' of the column direction Y.
  • the first partition A21 may include: a plurality of second sub-display areas divided along the first direction (parallel to the sixth direction E in this example), or the first partition A21 may The whole is used as a second sub-display area.
  • the second area A22 may include: a plurality of fourth sub-display areas divided along the second direction (parallel to the fifth direction F in this example), or the second area A22 may be entirely used as a fourth sub-display area.
  • the third partition A23 may include a plurality of sixth sub-display areas divided along the third direction (parallel to the sixth direction E in this example), or the third partition A23 may serve as a sixth sub-display area as a whole.
  • the fourth partition A24 may include a plurality of eighth sub-display areas divided along the fourth direction (parallel to the fifth direction F in this example), or the fourth partition A24 may serve as an eighth sub-display area as a whole.
  • the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along a side away from the first partition A21 in the first direction, A plurality of third sub-display areas A12a are arranged in sequence along the side away from the second partition A22, a plurality of fifth sub-display areas A13a are arranged in sequence along the side away from the third partition A23 in the third direction, and in the A plurality of seventh sub-display areas A14a are arranged sequentially in four directions along the side away from the fourth partition A24.
  • the second light-emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51.
  • the second light-emitting element in the fourth sub-display area may be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second area A22 through the first conductive line 51.
  • the second light-emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52.
  • the first light-emitting element may be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third area A23 through the first conductive line 51.
  • the second light-emitting element in the eighth sub-display area may be electrically connected to the second pixel circuit in the seventh sub-display area A14a closest to the fourth sub-area A24 through the second conductive line 52.
  • the seventh sub-display area A14a The first light-emitting element may be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth area A24 through the first conductive line 51.
  • connection relationship between the first sub-display area and the second sub-display area the connection relationship between the third sub-display area and the fourth sub-display area, the fifth sub-display area and the sixth sub-display area in this embodiment
  • connection relationship between them, the connection relationship between the seventh sub-display area and the eighth sub-display area, and the connection method between the pixel circuit and the light-emitting element can refer to the description of the previous embodiments, and will not be described again here.
  • At least one embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • FIG. 31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 31 , this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light-emitting side of the display structure layer away from the display substrate 91 . The orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the second display area A2.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板，包括：衬底基板(100)、位于第一显示区(A1)的多个第一发光元件(21)、多个第一像素电路(31)和多个第二像素电路(32)、以及位于第二显示区(A2)的多个第二发光元件(22)。第一显示区(A1)包括在第一方向沿着远离第二显示区(A2)的一侧依次排布的第一个第一子显示区至第N个第一子显示区，其中，N为大于1的整数。第二显示区(A2)包括至少一个第二子显示区。第二子显示区的第二发光元件(22)与第n个第一子显示区的第二像素电路(32)电连接，第n个第一子显示区的第一发光元件(21)与第n+i个第一子显示区的第一像素电路(31)电连接。n和i均为大于0且小于N的整数。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、多个像素电路和多个发光元件。衬底基板包括第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧。多个像素电路包括位于第一显示区的多个第一像素电路和多个第二像素电路，多个发光元件包括位于所述第一显示区的多个第一发光元件和位于所述第二显示区的多个第二发光元件。所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件电连接，所述至少一个第一像素电路被配置为驱动所述至少一个第一发光元件发光。所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，所述至少一个第二像素电路被配置为驱动所述至少一个第二发光元件发光。所述第一显示区包括：在第一方向沿着远离所述第二显示区的一侧依次排布的第一个第一子显示区至第N个第一子显示区，其中，N为大于1的整数。所述第 二显示区包括至少一个第二子显示区，所述第二子显示区的第二发光元件与第n个第一子显示区的第二像素电路电连接，所述第n个第一子显示区的第一发光元件与第n+i个第一子显示区的第一像素电路电连接，其中，n和i均为大于0且小于N的整数。
在一些示例性实施方式中，所述第n+i个第一子显示区的第一发光元件与第n+i+j个第一子显示区的第一像素电路电连接，其中，j为大于0且小于N的整数。
在一些示例性实施方式中，j等于i。
在一些示例性实施方式中，所述至少一个第一像素电路与所述至少一个第一发光元件通过第一导电线电连接，所述至少一个第二像素电路与所述至少一个第二发光元件通过第二导电线电连接。
在一些示例性实施方式中，所述至少一个第一子显示区内的至少一个像素电路所电连接的第一导电线或第二导电线与至少一个第一发光元件所电连接的第一导电线为异层结构。
在一些示例性实施方式中，电连接所述第n个第一子显示区的第二像素电路和所述第二子显示区的第二发光元件的第二导电线，与电连接所述第n个第一子显示区的第一发光元件和第n+i个第一子显示区的第一像素电路的第一导电线为异层结构。
在一些示例性实施方式中，电连接所述第n+i个第一子显示区的第一发光元件和第n+i+j个第一子显示区的第一像素电路的第一导电线，与电连接所述第n+i个第一子显示区的第一像素电路和所述第n个第一子显示区的第一发光元件的第一导电线为异层结构。
在一些示例性实施方式中，所述至少一个第一子显示区内的像素电路的数目大于第一发光元件的数目。
在一些示例性实施方式中，所述第n个第一子显示区内的像素电路均为第二像素电路。
在一些示例性实施方式中，所述第n个第一子显示区的像素电路的数目大于或等于第n+1个第一子显示区的像素电路的数目，所述第n个第一子显 示区的第一发光元件的数目大于或等于第n+1个第一子显示区的第一发光元件的数目。
在一些示例性实施方式中，所述第二子显示区内靠近所述第n个第一显示区的第二发光元件与所述第n个第一子显示区内靠近所述第二子显示区的第二像素电路电连接，所述第二子显示区内远离所述第n个第一子显示区的第二发光元件与所述第n个第一子显示区内远离所述第二子显示区的第二像素电路电连接。
在一些示例性实施方式中，所述第一显示区的像素电路阵列排布，所述第一方向为所述像素电路的行方向。
在一些示例性实施方式中，所述第二显示区包括：在所述第一方向沿着远离所述第一子显示区的一侧依次排布的第M个第二子显示区至第一个第二子显示区，其中，M为大于1且小于N的整数。其中，第m个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区，位于第m+1个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区，靠近所述第二显示区的一侧，m为大于0且小于M的整数。
在一些示例性实施方式中，相邻第二子显示区内的第二发光元件电连接的第二导电线位于不同导电层，相邻第一子显示区内的第一发光元件电连接的第一导电线位于不同导电层。
在一些示例性实施方式中，所述第二子显示区内的多个第二发光元件电连接的第二导电线为同层结构。
在一些示例性实施方式中，所述第二子显示区内在所述第一方向上相邻的第二发光元件电连接的第二导电线为异层结构。
在一些示例性实施方式中，所述第一导电线和第二导电线为透明导电线。
在一些示例性实施方式中，所述第一显示区还包括：在第二方向沿着远离所述第二显示区的一侧依次排布的第一个第三子显示区至第H个第三子显示区，其中，H为大于1的整数。所述第二显示区还包括：至少一个第四子显示区，所述第四子显示区的第二发光元件与第h个第三子显示区的第二像素电路电连接，所述第h个第三子显示区的第一发光元件与第h+s个第三子 显示区的第一像素电路电连接，其中，h和s均为大于0且小于H的整数。
在一些示例性实施方式中，所述第二方向与所述第一方向平行，或者，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述第一显示区还包括：在第三方向沿着远离所述第二显示区的一侧依次排布的第一个第五子显示区至第R个第五子显示区，其中，R为大于1的整数。所述第二显示区还包括：至少一个第六子显示区，所述第六子显示区的第二发光元件与第r个第五子显示区的第二像素电路电连接，所述第r个第五子显示区的第一发光元件与第r+k个第五子显示区的第一像素电路电连接，其中，r和k均为大于0且小于R的整数。
在一些示例性实施方式中，所述第一显示区还包括：在第四方向沿着远离所述第二显示区的一侧依次排布的第一个第七子显示区至第G个第七子显示区，其中，G为大于1的整数。所述第二显示区还包括：至少一个第八子显示区，所述第八子显示区的第二发光元件与第g个第七子显示区的第二像素电路电连接，所述第g个第七子显示区的第一发光元件与第g+d个第七子显示区的第一像素电路电连接，其中，g和d均为大于0且小于G的整数。
在一些示例性实施方式中，所述第二发光元件的密度小于或等于所述第一发光元件的密度。
在一些示例性实施方式中，所述第一显示区的分辨率小于或等于所述第二显示区的分辨率。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为图2提供的像素电路的工作时序图；
图4为本公开至少一实施例的一个像素电路的俯视示意图；
图5为图4中沿Q-Q’方向的局部剖面示意图；
图6A为图4中形成半导体层后的像素电路的俯视图；
图6B为图4中形成第一导电层后的像素电路的俯视图；
图6C为图4中形成第二导电层后的像素电路的俯视图；
图6D为图4中形成第三绝缘层后的像素电路的俯视图；
图7为本公开至少一实施例的第一显示区的局部示意图；
图8为本公开至少一实施例的显示区域的示意图；
图9为本公开至少一实施例的第一显示区和第二显示区的连接示意图；
图10为本公开至少一实施例的透明导电线的示例图；
图11A为本公开至少一实施例的第一个第二子显示区的透明导电线的连接示意图；
图11B为本公开至少一实施例的第二个第二子显示区的透明导电线的连接示意图；
图11C为本公开至少一实施例的第一个第一子显示区的透明导电线的连接示意图；
图11D为本公开至少一实施例的第二个第一子显示区的透明导电线的连接示意图；
图11E为本公开至少一实施例的第三个第一子显示区和第四个第一子显示区的透明导电线的连接示意图；
图11F为本公开至少一实施例的第五个第一子显示区和第六个第一子显示区的透明导电线的连接示意图；
图11G为本公开至少一实施例的第七个第一子显示区至第十个第一子显示区的透明导电线的连接示意图；
图12为本公开至少一实施例的第一透明导电层的示意图；
图13为本公开至少一实施例的第二透明导电层的示意图；
图14为本公开至少一实施例的第三透明导电层的示意图；
图15为本公开至少一实施例的三个透明导电层的示意图；
图16为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图；
图17为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图；
图18为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图；
图19为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图；
图20为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图21为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图22为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图23为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图24为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图25为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图26为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图27为本公开至少一实施例的第一显示区和第二显示区的另一连接示 意图；
图28为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图29为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图30为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图；
图31为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成 要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量 误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
本实施例提供一种显示基板，包括：衬底基板、多个像素电路和多个发光元件。衬底基板包括第一显示区和第二显示区，第一显示区位于第二显示区的至少一侧。多个像素电路包括位于第一显示区的多个第一像素电路和多个第二像素电路。多个发光元件包括位于第一显示区的多个第一发光元件和位于第二显示区的多个第二发光元件。多个第一像素电路中的至少一个第一像素电路与多个第一发光元件中的至少一个第一发光元件电连接，所述至少一个第一像素电路被配置为驱动所述至少一个第一发光元件发光。多个第二像素电路中的至少一个第二像素电路与多个第二发光元件中的至少一个第二发光元件电连接，所述至少一个第二像素电路被配置为驱动所述至少一个第二发光元件发光。第一显示区包括：在第一方向沿着远离第二显示区的一侧依次排布的第一个第一子显示区至第N个第一子显示区，其中，N为大于1的整数。第二显示区包括至少一个第二子显示区，所述第二子显示区的第二发光元件与第n个第一子显示区的第二像素电路电连接，第n个第一子显示区的第一发光元件与第n+i个第一子显示区的第一像素电路电连接，其中，n和i均为大于0且小于N的整数。例如，i可以为1或2等。在本示例中，第n个第一子显示区位于第n+1个第一子显示区靠近第二显示区的一侧。
在一些示例中，第二显示区可以仅包括一个第二子显示区。或者，第二显示区可以包括多个第二子显示区。例如，多个第二子显示区可以在第一方向沿着远离第一子显示区的一侧依次排布。然而，本实施例对此并不限定。
本实施例提供的显示基板，对第一显示区和第二显示区进行分区，第二显示区的第二子显示区的第二发光元件与第一显示区的一个第一子显示区的第二像素电路电连接，且所述第一子显示区的第一发光元件与另一个第一子显示区内的第一像素电路电连接，从而实现不同分区内的像素电路和发光元件的错位连接。本实施例可以减小电连接第二发光元件和第二像素电路的导电线的长度差异。导电线的长度会决定导电线与其他信号走线的交叠面积大小，从而影响寄生电容的大小，而寄生电容差异大会导致画面显示不均一。本实施例通过不同分区内的像素电路和发光元件的错位连接，来减小导电线 的长度差异，从而改善显示画面均匀度不佳的情况，提升显示均一性，实现更均匀的全面屏视觉显示效果。
在一些示例性实施方式中，至少一个第一像素电路与至少一个第一发光元件可以通过第一导电线电连接，至少一个第二像素电路与至少一个第二发光元件可以通过第二导电线电连接。例如，第一导电线和第二导电线可以均为透明导电线。第一导电线和第二导电线可以采用透明导电材料(例如，氧化铟锡(ITO))制备。然而，本实施例对此并不限定。在另一些示例中，第一导电线可以为非透明导电线，第二导电线可以为透明导电线。例如，第一导电线可以采用金属材料制备，第二导电线可以采用透明导电材料(例如，ITO)制备。
在一些示例性实施方式中，第n+i个第一子显示区的第一发光元件可以与第n+i+j个第一子显示区的第一像素电路电连接，其中，j为大于0且小于N的整数。在本示例中，第一显示区的第一子显示区的第一发光元件可以与其他第一子显示区的第一像素电路进行错位连接，以支持将第二像素电路设置在第二显示区的附近或周围，从而改善电连接第二像素电路和第二发光元件的第二导电线的长度差异过大的情况。
在一些示例中，j可以等于i。比如，i和j可以均为1或2。例如，第n+i个第一子显示区的第一发光元件可以与第n+2×i个第一子显示区的第一像素电路电连接，第n+2×i个第一子显示区的第一发光元件可以与第n+3×i个第一子显示区的第一像素电路电连接。然而，本实施例对此并不限定。例如，j可以不同于i。比如，i可以为2，j可以为1。
在一些示例性实施方式中，至少一个第一子显示区内的至少一个像素电路所电连接的第一导电线或第二导电线与至少一个第一发光元件所电连接的第一导电线可以为异层结构。在本公开中，A和B为异层结构表示A和B位于不同的导电层。如此一来，可以避免不同导电线之间相互干扰。在一些示例中，电连接第二子显示区的第二发光元件和第n个第一子显示区的第二像素电路的第二导电线，与电连接第n个第一子显示区的第一发光元件和第n+i个第一子显示区的第一像素电路的第一导电线可以为异层结构。在一些示例中，电连接第n+i个第一子显示区的第一发光元件和第n+i+j个第一子 显示区的第一像素电路的第一导电线，与电连接第n个第一子显示区的第一发光元件和第n+i个第一子显示区的第一像素电路的第一导电线可以为异层结构。
在一些示例性实施方式中，第n个第一子显示区的像素电路可以均为第二像素电路。在本示例中，通过将第二像素电路集中设置在第二显示区的附近，可以有利于减小电连接第二发光元件和第二像素电路的第二导电线的长度。
在一些示例性实施方式中，至少一个第一子显示区内的像素电路的数目可以大于第一发光元件的数目。在一些示例中，通过对第一显示区内的像素电路进行压缩来形成设置第二像素电路的空间，因此，第一显示区内的像素电路的数目大于第一发光元件的数目。
在一些示例性实施方式中，第n个第一子显示区的像素电路的数目可以大于或等于第n+1个第一子显示区的像素电路的数目，第n个第一子显示区的第一发光元件的数目可以大于或等于第n+1个第一子显示区的第一发光元件的数目。在一些示例中，在第一方向沿着远离第二显示区的一侧，多个第一子显示区内的像素电路的数目可以逐渐减少，第一发光元件的数目也可以逐渐减小。
在一些示例性实施方式中，第二子显示区内靠近第n个第一显示区的第二发光元件可以与第n个第一子显示区内靠近第二子显示区的第二像素电路电连接，第二子显示区内远离第n个第一子显示区的第二发光元件可以与第n个第一子显示区内远离第二子显示区的第二像素电路电连接。本示例提供的相应区域内的第二发光元件和第二像素电路的连接方式，有助于排布导电线，减少因导电线交叠而引起相互干扰的情况。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一显示区的多个像素电路可以阵列排布，第一方向可以为像素电路的行方向。然而，本实施例对此并不限定。例如，第一方向可以为像素电路的列方向，或者可以为与行方向交叉的方向，或者，可以为与列方向交叉的方向。
在一些示例性实施方式中，第二显示区可以包括：在第一方向沿着远离 第一子显示区的一侧依次排布的第M个第二子显示区至第一个第二子显示区。其中，M为大于1且小于N的整数。第m个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区，可以位于第m+1个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区靠近所述第二显示区的一侧，m为大于0且小于M的整数。在本示例中，远离第一显示区的第二子显示区内的第二发光元件可以与靠近第二显示区的第一子显示区内的第二像素电路电连接，靠近第一显示区的第二子显示区内的第二发光元件可以与远离第二显示区的第一子显示区内的第二像素电路电连接。如此一来，可以有助于减小电连接第二发光元件和第二像素电路的第二导电线之间的长度差异。在一些示例中，整个第二显示区可以被划分为多个第二子显示区，或者，第二显示区的一部分可以被划分为多个第二子显示区。然而，本实施例对此并不限定。
在一些示例性实施方式中，相邻第二子显示区内的第二发光元件电连接的第二导电线可以位于不同导电层，相邻第一子显示区内的第一发光元件电连接的第一导电线可以位于不同导电层。如此一来，可以减少由于导电线交叠而相互干扰的情况。
在一些示例性实施方式中，第二子显示区内的多个第二发光元件电连接的第二导电线可以为同层结构。或者，第二子显示区内在第一方向上相邻的第二发光元件电连接的第二导电线可以为异层结构。然而，本实施例对此并不限定。在另一些示例中，第二发光元件电连接的第二导电线可以由多个导电线段连接形成，且相邻导电线段可以位于不同的导电层。
在一些示例性实施方式中，第一显示区还可以包括：在第二方向沿着远离第二显示区的一侧依次排布的第一个第三子显示区至第H个第三子显示区，其中，H为大于1的整数。第二显示区还可以包括：至少一个第四子显示区，第四子显示区的第二发光元件与第h个第三子显示区的第二像素电路电连接，第h个第三子显示区的第一发光元件与第h+s个第三子显示区的第一像素电路电连接，其中，h和s均为大于0且小于H的整数。比如，h和s可以均为1，或者，h可以为1，s可以为2。在一些示例中，第二方向可以与第一方向平行，或者，第二方向可以与第一方向交叉。本示例通过在第一方向和第二 方向对第一显示区和第二显示区划分多个分区，并在多个分区进行发光元件和像素电路的错位连接，有利于减小电连接第二发光元件和第二像素电路的导电线的长度差异。
在一些示例性实施方式中，第一显示区还可以包括：在第三方向沿着远离第二显示区的一侧依次排布的第一个第五子显示区至第R个第五子显示区，其中，R为大于1的整数。第二显示区还可以包括：至少一个第六子显示区。第六子显示区的第二发光元件与第r个第五子显示区的第二像素电路电连接，第r个第五子显示区的第一发光元件与第r+k个第五子显示区的第一像素电路电连接，其中，r和k均为大于0且小于R的整数。比如，r和k可以均为1，或者，r可以为1，k可以为2。在一些示例中，第三方向可以与第一方向或第二方向平行，或者，第三方向可以与第一方向交叉，或者，第三方向可以与第二方向交叉。本示例可以通过在多个对第一显示区和第二显示区划分多个分区，并在多个分区进行发光元件和像素电路的错位连接，有利于减小电连接第二发光元件和第二像素电路的导电线的长度差异。
在一些示例性实施方式中，第一显示区还可以包括：在第四方向沿着远离第二显示区的一侧依次排布的第一个第七子显示区至第G个第七子显示区，其中，G为大于1的整数。第二显示区还可以包括：至少一个第八子显示区。第八子显示区的第二发光元件与第g个第七子显示区的第二像素电路电连接，第g个第七子显示区的第一发光元件与第g+d个第七子显示区的第一像素电路电连接。其中，g和d均为大于0且小于G的整数。比如，g和d可以均为1，或者，g可以为1，d可以为2。在一些示例中，第四方向可以与第一方向、第二方向或第三方向平行；或者，第四方向可以与第一方向、第二方向或第三方向交叉。本示例可以通过多个方向对第一显示区和第二显示区划分多个分区，并在多个分区进行发光元件和像素电路的错位连接，有利于减小电连接第二发光元件和第二像素电路的导电线的长度差异。
在一些示例中，N、H、R和G可以相同；或者，N、H、R和G中的至少两个可以相同；或者，N、H、R和G可以各不相同。然而，本实施例对此并不限定。
在一些示例中，i、s、k和d可以相同，或者，i、s、k和d中的至少两 个可以相同，或者，i、s、k和d可以各不相同。然而，本实施例对此并不限定。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA外围的周边区域BB。显示基板的显示区域AA可以包括：第一显示区A1和第二显示区A2，第一显示区A1位于第二显示区A2的至少一侧。例如，第一显示区A1可以围绕在第二显示区A2的四周。然而，本实施例对此并不限定。例如，第一显示区A1可以部分围绕第二显示区A2。
在一些示例性实施方式中，如图1所示，第二显示区A2为透光显示区，还可以称为屏下摄像头(UDC，Under Display Camera)区域；第一显示区A1为非透光显示区，还可以称为正常显示区。例如，感光传感器(如，摄像头等硬件)在显示基板上的正投影可以位于显示基板的第二显示区A2内。在一些示例中，如图1所示，第二显示区A2可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第二显示区A2的尺寸。然而，本实施例对此并不限定。在另一些示例中，第二显示区A2可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第二显示区A2的内切圆的尺寸。
在一些示例性实施方式中，如图1所示，第二显示区A2可以位于显示区域AA的顶部正中间位置。第一显示区A1可以围绕在第二显示区A2的四周。然而，本实施例对此并不限定。例如，第二显示区A2可以位于显示区域AA的左上角或者右上角等其他位置。例如，第一显示区A1可以围绕在第二显示区A2的至少一侧。
在一些示例性实施方式中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。第二显示区A2可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第二显示区A2可以为矩形、半圆形、五边形等其他形状。
在一些示例性实施方式中，显示区域AA可以设置有多个子像素。至少一个子像素可以包括像素电路和发光元件。像素电路可以配置为驱动所连接的发光元件。例如，像素电路可以配置为提供驱动电流以驱动发光元件发光。 像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(即3个晶体管和1个电容)结构、7T1C(即7个晶体管和1个电容)结构、5T1C(即5个晶体管和1个电容)结构、8T1C(即8个晶体管和1个电容)结构或者8T2C(即8个晶体管和2个电容)结构等。在一些示例中，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例性实施方式中，发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。图3为图2提供的像素电路的工作时序图。本示例性实施例的像素电路以7T1C结构为例进行说明。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，本示例的像素电路可以包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL可以包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶 体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图2所示，显示基板可以包括扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1可以配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2可以配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL可以配置为向像素电路提供扫描信号SCAN，数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM，第一复位控制线RST1可以配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2可以配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，在第z行像素电路中，第一复位控制线RST1可以与第z-1行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(z-1)，即第一复位控制信号RESET1(z)与扫描信号SCAN(z-1)相同。第二复位控制线RST2可以与第z行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(z)，即第二复位控制信号RESET2(z)与扫描信号SCAN(z)相同。在一些示例中，第z行像素电路所电连接的第二复位控制线RST2与第z+1行像素电路所电连接的第一复位控制线 RST1可以为一体结构。其中，z为大于0的整数。如此，可以减少显示基板的信号线，实现显示基板的窄边框设计。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些示例性实施方式中，如图2所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电容极板与驱动晶体管T3的栅极电连接，存储电容Cst 的第二电容极板与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图3对图2示意的像素电路的工作过程进行说明。以图2所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图3所示，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第一电容极板为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电 容极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图4为本公开至少一实施例的一个像素电路的俯视示意图。图5为图4中沿Q-Q’方向的局部剖面示意图。图6A为图4中形成半导体层后的像素电路的俯视图。图6B为图4中形成第一导电层后的像素电路的俯视图。图6C 为图4中形成第二导电层后的像素电路的俯视图。图6D为图4中形成第三绝缘层后的像素电路的俯视图。
在一些示例性实施例中，如图4至图6D所示，显示基板可以包括：衬底基板100、以及依次设置在衬底基板100上的半导体层10、第一导电层11、第二导电层12以及第三导电层13。半导体层10和第一导电层11之间设置有第一绝缘层101，第一导电层11和第二导电层12之间设置有第二绝缘层102，第二导电层12和第三导电层13之间设置有第三绝缘层103。第一绝缘层101、第二绝缘层102和第三绝缘层103可以为无机绝缘层。第一绝缘层101和第二绝缘层102还可以称为栅绝缘层，第三绝缘层103还可以称为层间绝缘层。在一些示例中，在第三导电层13远离衬底基板100一侧还可以设置第四导电层，第四导电层可以包括阳极连接电极，阳极连接电极可以连接像素电路和发光元件。在第四导电层远离衬底基板一侧还可以设置至少一个透明导电层，透明导电层可以包括透明导电线，配置为连接阳极连接电极和发光元件的阳极。第四导电层和透明导电层之间可以设置平坦层，相邻透明导电层之间可以设置平坦层。在透明导电层远离衬底基板一侧可以依次设置阳极层、像素定义层、有机发光层和阴极层。然而，本实施例对此并不限定。
在一些示例性实施例中，如图4至图6A所示，显示基板的半导体层10可以包括：像素电路的多个晶体管的有源层(例如，第一复位晶体管T1的第一有源层T10、阈值补偿晶体管T2的第二有源层T20、驱动晶体管T3的第三有源层T30、数据写入晶体管T4的第四有源层T40、第一发光控制晶体管T5的第五有源层T50、第二发光控制晶体管T6的第六有源层T60、第二复位晶体管T7的第七有源层T70)。一个像素电路的多个晶体管的有源层可以为一体结构。至少一个有源层可以包括：沟道区、第一掺杂区和第二掺杂区，沟道区可以不掺杂杂质，并具有半导体特性，第一掺杂区和第二掺杂区可以在沟道区的两侧，并且掺杂有杂质微粒，并因此具有导电性。杂质可以根据晶体管的类型而变化。半导体层的第一掺杂区或第二掺杂区可以被解释为晶体管的源电极或漏电极。
在一些示例性实施例中，如图4至图6B所示，显示基板的第一导电层11可以包括：像素电路的多个晶体管的控制极(例如，第一复位晶体管T1 的控制极T11、阈值补偿晶体管T2的控制极T21、驱动晶体管T3的控制极T31、数据写入晶体管T4的控制极T41、第一发光控制晶体管T5的控制极T51、第二发光控制晶体管T6的控制极T61、第二复位晶体管T7的控制极T71)、发光控制线EML、扫描线GL、第一复位控制线(包括本行像素电路电连接的第一复位控制线RST1和下一行像素电路电连接的第一复位控制线RST1’)以及存储电容Cst的第一电极Cst-1。其中，本行像素电路的第一复位晶体管T1的控制极T11、上一行像素电路的第二复位晶体管的控制极和第一复位控制线RST1可以为一体结构。阈值补偿晶体管T2的控制极T21、数据写入晶体管T4的控制极T41和扫描线GL可以为一体结构。驱动晶体管T3的控制极T31和存储电容Cst的第一电极Cst-1可以为一体结构。第一发光控制晶体管T5的控制极T51、第二发光控制晶体管T6的控制极T61和发光控制线EML可以为一体结构。本行像素电路的第二复位晶体管T7的控制极T71、下一行像素电路的第一复位晶体管的控制极以及第一复位控制线RST1’可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施例中，如图4至图6C所示，显示基板的第二导电层12可以包括：第一初始信号线(例如第一初始信号线INIT1a和INIT1b)、第二初始信号线(例如第二初始信号线INIT2a和INIT2b)、存储电容Cst的第二电极Cst-2以及屏蔽电极BK。存储电容Cst的第二电极Cst-2具有一个镂空区域。驱动晶体管T3的控制极T31在衬底基板上的正投影可以覆盖该镂空区域在衬底基板上的正投影。镂空区域在衬底基板上的正投影可以为多边形。然而，本实施例对此并不限定。
在一些示例性实施例中，如图4至图6D所示，显示基板的第三绝缘层103开设有多个过孔，例如包括第一过孔V1至第十五过孔V15。其中，第一过孔V1至第八过孔V6内的第三绝缘层103、第二绝缘层102和第一绝缘层101被去掉，暴露出半导体层10的表面。第九过孔V9内的第三绝缘层103和第二绝缘层102被去掉，暴露出第一导电层11的表面。第十过孔V10至第十五过孔V15内的第三绝缘层103被去掉，暴露出第二导电层12的表面。
在一些示例性实施方式中，如图4至图6D所示，显示基板的第三导电层13可以包括：数据线DL、第一电源线PL1以及多个连接电极(例如，第 一连接电极CP1至第六连接电极CP6)。数据线DL可以通过第三过孔V3与数据写入晶体管T4的有源层T40的第一掺杂区电连接。第一电源线PL1可以通过第十二过孔V12与屏蔽电极BK电连接，还可以通过第十三过孔V13与存储电容Cst的第二电极Cst-2电连接。屏蔽电极BK配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素电路的关键节点的电位，提高显示效果。第一连接电极CP1可以通过第一过孔V1与第一复位晶体管T1的有源层T10的第一掺杂区电连接，还可以通过第十过孔V10与第一初始信号线INIT1a电连接。第二连接电极CP2可以通过第二过孔V2与阈值补偿晶体管T2的有源层T20的第一掺杂区电连接，还可以通过第九过孔V9与驱动晶体管T3的控制极T31电连接。第三连接电极CP3可以通过第五过孔V5与第二发光控制晶体管T6的有源层T60的第二掺杂区电连接。第四连接电极CP4可以通过第六过孔V6与第二复位晶体管T7的有源层T70的第一掺杂区电连接，还可以通过第十五过孔V15与第二初始信号线INIT2b电连接。第五连接电极CP5可以通过第七过孔V7与上一行像素电路的第二复位晶体管的有源层的第一掺杂区电连接，还可以通过第十一过孔V11与第二初始信号线INIT2a电连接。第六连接电极CP6可以通过第八过孔V8与下一行像素电路的第一复位晶体管的有源层的第一掺杂区电连接，还可以通过第十四过孔V14与第一初始信号线INIT1b电连接。
上述仅为像素电路的俯视图的一种示例。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，第一显示区A1可以设置有多个第一发光元件21和多个像素电路，第二显示区A2可以设置有多个第二发光元件22。多个像素电路可以包括：多个第一像素电路31、多个第二像素电路32和多个无效像素电路。至少一个第一像素电路31与至少一个第一发光元件21可以通过第一导电线L1电连接，至少一个第一像素电路31被配置为驱动至少一个第一发光元件21发光。至少一个第二像素电路32与至少一个第二发光元件22可以通过第二导电线L2电连接，至少一个第二像素电路32被配置为驱动至少一个第二发光元件22发光。设置无效像素电路可以利于提高多个膜层的部件在刻蚀工艺中的均一性。例如，无效像素电路与其所在行或所在列的第一像素电路31和第二像素电路32的结构相同，只是其不 与任何发光元件相连。在本示例中，第一显示区A1的光透过率小于第二显示区A2的光透过率。仅在第一显示区A1设置像素电路，第二显示区A2不设置像素电路，可以提高第二显示区A2的光透过率。
在一些示例中，为了提高显示效果，第二显示区A2的第二发光元件22的密度可以小于或等于第一显示区A1的第一发光元件21的密度。然而，本实施例对此并不限定。
在一些示例中，第一显示区A1的分辨率可以小于或等于第二显示区A2的分辨率。然而，本实施例对此并不限定。
图7为本公开至少一实施例的第一显示区的局部示意图。图7中以第一显示区A1的若干第一发光元件21和像素电路30为例进行示意。在本示例中，沿行方向X依次排布的多个像素电路可以称为一行像素电路，沿列方向Y依次排布的多个像素电路可以称为一列像素电路。行方向X与列方向Y交叉，例如，行方向X可以垂直于列方向Y。
在一些示例性实施方式中，如图1和图7所示，由于第一显示区A1不仅设置有与第一发光元件21电连接的第一像素电路31，还设置有与第二发光元件22电连接的第二像素电路32，因此，第一显示区A1的像素电路30的数目大于第一发光元件21的数目。在本示例中，通过减小第一像素电路在第一方向上的尺寸来获得设置第二像素电路的区域。例如，像素电路在第一方向上的尺寸可以小于第一发光元件在第一方向上的尺寸。在本示例中，第一方向可以为行方向X。如图7所示，可以将原来的每a列像素电路通过沿水平方向X压缩，从而新增一列像素电路的排布空间，且压缩前的a列像素电路和压缩后的a+1列像素电路所占用的空间是相同。其中，a可以为大于1的整数。在本示例中，a可以等于2。然而，本实施例对此并不限定。例如，a可以等于3或4。在另一些示例中，第一方向可以为列方向Y。可以将原来的b行像素电路通过沿竖直方向Y压缩，从而新增一行像素电路的排布空间，且压缩前的b行像素电路和压缩后的b+1行像素电路所占用的空间是相同。其中，b可以为大于1的整数。或者，可以通过减小第一像素电路在行方向和列方向上的尺寸来获得设置第二像素电路的区域。
在本示例性实施方式中，如图7所示，一个像素电路30可以通过第一连 接孔300与第一发光元件21或者第二发光元件实现电连接，第一发光元件21可以通过第二连接孔210与对应的第一像素电路实现电连接。例如，第一像素电路可以通过第一连接孔300与第一导电线电连接，且所述第一导电线可以通过第二连接孔210与对应的第一发光元件21电连接。第二像素电路可以通过第一连接孔300与第二导电线电连接，所述第二导电线可以延伸至第二显示区，与第二显示区内的第二发光元件电连接。
图8为本公开至少一实施例的显示区域的示意图。在一些示例性实施方式中，如图8所示，第二显示区A2关于行方向X上的中轴线OO’大致对称。第二显示区A2可以包括第一分区A21和第二分区A22，第一分区A21和第二分区A22可以关于中轴线OO’大致对称。第一显示区A1可以包括在行方向X上与第二显示区A2的第一分区A21相邻的第一辅助区A11、以及在行方向X上与第二分区A22相邻的第二辅助区A12。与第一分区A21的第二发光元件电连接的第二像素电路可以设置在第一辅助区A11；与第二分区A22的第二发光元件电连接的第二像素电路可以设置在第二辅助区A12。
下面以第一分区A21和第一辅助区A11之间的电连接像素电路和发光元件的导电线为例进行示意。
图9为本公开至少一实施例的第二显示区和第一显示区的连接示意图。在一些示例性实施方式中，如图8和图9所示，第二显示区A2的第一分区A21可以包括：在行方向X上沿着远离第一辅助区A11的一侧依次排布的多个第二子显示区，例如包括两个第二子显示区(即本示例的M可以为2)。其中，第一个第二子显示区A2a可以位于第二个第二子显示区A2b远离第一辅助区A11的一侧。第一显示区A1的第一辅助区A11可以包括：在行方向X上沿着远离第一分区A21的一侧依次排布的多个第一子显示区，例如包括第一个第一子显示区A1a至第十个第一子显示区A1j(即本示例的N可以为10)，其中，第一个第一子显示区A1a最靠近第一分区A21，第十个第一子显示区A1j距离第一分区A21最远。
在本示例中，相邻两个第一子显示区可以为连续的区域，即相邻两个第一子显示区之间可以没有设置其他像素电路和发光元件。第一个第一子显示区A1a和第二个第二子显示区A2b可以相邻且为连续的区域，即第一子显示 区A1a和第二个第二子显示区A2b之间可以没有间隔其他区域。在本示例中，第二像素电路可以紧邻第二显示区A2排布。然而，本实施例对此并不限定。在另一些示例中，第一个第一子显示区A1a和第二个第二子显示区A2b可以为不连续的区域，例如第一个第一子显示区A1a和第二个第二子显示区A2b之间可以设置不属于第一子显示区的第一像素电路和第一发光元件。第二像素电路的排布位置没有与第二显示区A2相邻，第二像素电路的排布位置与第二显示区A2可以间隔一定距离。
在本示例中，以电连接第一发光元件和第一像素电路的第一导电线为透明导电线，电连接第二发光元件和第二像素电路的第二导电线为透明导电线为例进行说明。例如，第二导电线可以包括：第一透明导电线52a和第二透明导电线52b；第一导电线可以包括：第三透明导电线51a至第十二透明导电线51j。
在一些示例性实施方式中，如图9所示，第一个第二子显示区A2a的第二发光元件可以通过第一透明导电线52a与第一个第一子显示区A1a的第二像素电路电连接。第二个第二子显示区A2b的第二发光元件可以通过第二透明导电线52b与第二个第二子显示区A1b的第二像素电路电连接。在本示例中，远离第一辅助区A11的第二子显示区(例如，第二子显示区A2a)内的第二发光元件可以与靠近第一分区A21的第一子显示区(例如第一子显示区A1a)内的第二像素电路电连接，靠近第一辅助区A11的第二子显示区(例如第二子显示区A2b)内的第二发光元件可以与远离第一分区A21的第一子显示区(例如，第一子显示区A1b)内的第二像素电路电连接。如此一来，可以更好地改善不同区域的第二发光元件所电连接的透明导电线的长度差异过大的情况。然而，本实施例对此并不限定。在另一些示例中，远离第一辅助区A11的第二子显示区(例如，第二子显示区A2a)内的第二发光元件可以与远离第一分区A21的第一子显示区(例如，第一子显示区A1b)的第二像素电路电连接，靠近第一辅助区A11的第二子显示区(例如，第二子显示区A2b)的第二发光元件可以与靠近第一分区A21的第一子显示区(例如，第一子显示区A1a)内的第二像素电路电连接。
在一些示例性实施方式中，如图9所示，第一个第一子显示区A1a的第 一发光元件可以通过第三透明导电线51a与第三个第一子显示区A1c的第一像素电路电连接。第二个第一子显示区A1b的第一发光元件可以通过第四透明导电线51b与第四个第一子显示区A1d的第一像素电路电连接。第三个第一子显示区A1c的第一发光元件可以通过第五透明导电线51c与第五个第一子显示区A1e的第一像素电路电连接。第四个第一子显示区A1d的第一发光元件可以通过第六透明导电线51d与第六个第一子显示区A1f的第一像素电路电连接。第五个第一子显示区A1e的第一发光元件可以通过第七透明导电线51e与第七个第一子显示区A1g的第一像素电路电连接。第六个第一子显示区A1f的第一发光元件可以通过第八透明导电线51f与第八个第一子显示区A1h的第一像素电路电连接。第七个第一子显示区A1g的第一发光元件可以通过第九透明导电线51g与第九个第一子显示区A1i的第一像素电路电连接。第八个第一子显示区A1h的第一发光元件可以通过第十透明导电线51h与第十个第一子显示区A1j的第一像素电路电连接。依次类推，第九个第一子显示区A1i的第一发光元件可以通过第十一透明导电线51i与远离第十个第一子显示区Alj的区域(例如可以设置第十一个第一子显示区)内的第一像素电路电连接，第十个第一子显示区Alj的第一发光元件可以通过第十二透明导电线51j与远离第十个第一子显示区Alj的区域(例如可以设置第十二个第一子显示区)内的第一像素电路电连接，直至第一辅助区A11内的第一发光元件均可以与第一像素电路电连接即可。本示例对于第一子显示区的数目并不限定。在一些示例中，可以根据第一子显示区内的像素电路或发光元件的数目来确定第一子显示区的数目，比如，最后一个第一子显示区内的像素电路可以小于或等于2个。或者，在一些示例中，可以根据第一子显示区内的发光元件或像素电路所电连接的透明导电线的长度来确定第一子显示区的数目，比如，最后一个第一子显示区内的发光元件所电连接的透明导电线的长度小于或等于预设值。然而，本实施例对此并不限定。
在本示例中，第n个第一子显示区的第一发光元件与第n+2个第一子显示区的第一像素电路电连接，即本示例的i可以为2。然而，本实施例对此并不限定。在另一些示例中，第一个第一子显示区A1a的第一发光元件可以与第四个第一子显示区A1d的第一像素电路电连接，第二个第一子显示区A1b的第一发光元件可以与第三个第一子显示区A1d的第一像素电路电连接， 并依次类推。
在一些示例性实施方式中，如图9所示，第一个第一子显示区A1a和第二个第一子显示区A1b内的像素电路可以均为第二像素电路，以便驱动第一分区A21内的第二发光元件。第三个第一子显示区A1c至第十个第一子显示区A1j内的像素电路可以均为第一像素电路，以便驱动第一发光元件。本示例中，通过在靠近第二显示区A2的位置集中设置第二像素电路，并对第一像素电路和第一发光元件进行分区错位连接，可以减小电连接第二像素电路和第二发光元件之间的透明导电线的长度，改善透明导电线的长度差异过大的情况，从而提升显示效果的均一性。
图10为本公开至少一实施例的透明导电线的示例图。在一些示例性实施方式中，如图10所示，显示基板可以包括：位于像素电路远离衬底基板一侧的多个透明导电层，例如包括三个透明导电层，即第一透明导电层41、第二透明导电层42和第三透明导电层43。在一些示例中，第二透明导电层42可以位于第一透明导电层41远离衬底基板的一侧，第三透明导电层43可以位于第二透明导电层42远离衬底基板的一侧。任一个透明导电层可以包括多个透明导电线。例如，第一透明导电层41和第二透明导电层42均可以包括多条电连接第一发光元件和第一像素电路的第一导电线、以及多条电连接第二发光元件和第二像素电路的第二导电线。第三透明导电层43可以包括多条电连接第一发光元件和第一像素电路的第一导电线。然而，本实施例对此并不限定。例如，电连接第二发光元件和第二像素电路的第二导电线可以设置在第二透明导电层和第三透明导电层，或者可以设置在第一透明导电层和第三透明导电层。
在本示例中，以实线表示第一透明导电层41的透明导电线，以虚线表示第二透明导电层42的透明导电线，以点划线表示第三透明导电层43的透明导电线。
下面结合图10以一行像素电路和发光元件的连接关系为例进行说明。图11A为本公开至少一实施例的第一个第二子显示区的透明导电线的连接示意图。图11B为本公开至少一实施例的第二个第二子显示区的透明导电线的连接示意图。图11C为本公开至少一实施例的第一个第一子显示区的透明导电 线的连接示意图。图11D为本公开至少一实施例的第二个第一子显示区的透明导电线的连接示意图。图11E为本公开至少一实施例的第三个第一子显示区和第四个第一子显示区的透明导电线的连接示意图。图11F为本公开至少一实施例的第五个第一子显示区和第六个第一子显示区的透明导电线的连接示意图。图11G为本公开至少一实施例的第七个第一子显示区至第十个第一子显示区的透明导电线的连接示意图。在图11A至图11G中仅示意一行像素电路和发光元件的连接关系。
在一些示例性实施方式中，如图10至图11D所示，第一个第二子显示区A2a和第二个第二子显示区A2b内均设置有多列第二发光元件22。然而，本实施例对此并不限定。例如，每个第二子显示区可以仅包括一列第二发光元件。
在一些示例中，如图10至图11D所示，第一个第二子显示区A2a内的第二发光元件22可以通过第一透明导电线52a与第一个第一子显示区A1b内的第二像素电路32电连接。第一个第二子显示区A2a内的多个第二发光元件22所电连接的多条第一透明导电线52a可以均位于第一透明导电层41。第一透明导电线52a可以从第一个第二子显示区A2a经过第二个第二子显示区A2b延伸至第一个第一子显示区A1a内。第二个第二子显示区A2b内的第二发光元件22可以通过第二透明导电线52b与第二个第二子显示区A1b内的第二像素电路32电连接。第二个第二子显示区A2b内的多个第二发光元件22所电连接的多条第二透明导电线52b可以均位于第二透明导电层42。第二透明导电线52b可以从第二个第二子显示区A2b经过第一个第一子显示区A1a延伸至第二个第一子显示区A1b内。
在一些示例性实施方式中，如图10至图11D所示，第一个第二子显示区A2a内远离第一辅助区A11的第二发光元件22可以与第一个第一子显示区A1a内远离第二显示区A2的第二像素电路32电连接，第一个第二子显示区A2a内靠近第一辅助区A11的第二发光元件22可以与第一个第一子显示区A1a内靠近第二显示区A2的第二像素电路32电连接。第二个第二子显示区A2b内远离第一辅助区A11的第二发光元件22可以与第二个第一子显示区A1b内远离第二显示区A2的第二像素电路32电连接，第二个第二子显示 区A2b内靠近第一辅助区A11的第二发光元件22可以与第二个第一子显示区A1b内靠近第二显示区A2的第二像素电路32电连接。本示例的第二发光元件22和第二像素电路32的连接方式可以避免透明导电线交叠引起的短路或干扰等问题。
在一些示例性实施方式中，如图11A至图11D所示，第一个第一子显示区A1a内的第二像素电路32的数目与第一个第二子显示区A2a内的第二发光元件22的数目可以相同，第二个第一子显示区A1b内的第二像素电路32的数目与第二个第二子显示区A2b内的第二发光元件22的数目可以相同。在一些示例中，第一个第二子显示区A2a内的第二发光元件22的数目与第二个第二子显示区A2b内的第二发光元件22的数目可以大致相同。第一个第一子显示区A1a内的第二像素电路32的数目与第二个第一子显示区A1b内的第二像素电路32的数目可以大致相同。然而，本实施例对此并不限定。例如，第一个第二子显示区A2a和第二个第二子显示区A2b内的第二发光元件22的数目可以不同。第一个第一子显示区A1a和第二个第一子显示区A1b内的第二像素电路32的数目可以不同。
在一些示例性实施方式中，如图10至图11E所示，第一个第一子显示区A1a和第二个第一子显示区A1b可以均包括多列第二像素电路32和多列第一发光元件21。由于第二像素电路32在行方向X上的尺寸小于第一发光元件21在行方向X上的尺寸，因此，第一个第一子显示区A1a内第一发光元件21的数目小于第二像素电路32的数目，第二个第一子显示区A1b内第一发光元件21的数目小于第二像素电路32的数目。
在一些示例性实施方式中，如图10至图11E所示，第一个第一子显示区A1a的第一发光元件21可以通过第三透明导电线51a与第三个第一子显示区A1c的第一像素电路31电连接。第一个第一子显示区A1a内的多个第一发光元件21所电连接的多条第三透明导电线51a可以均位于第三透明导电层43。第三透明导电线51a可以从第一个第一子显示区A1a经过第二个第一子显示区A1b延伸至第三个第一子显示区A1c内。第二个第一子显示区A1b内的第一发光元件21可以通过第四透明导电线51b与第四个第二子显示区A1d内的第一像素电路31电连接。第二个第一子显示区A1b内的多个第一 发光元件21所电连接的多条第四透明导电线51b可以均位于第一透明导电层41。第四透明导电线51b可以从第二个第一子显示区A1b经过第三个第一子显示区A1c延伸至第四个第一子显示区A1d内。
在一些示例性实施方式中，如图10至图11E所示，第一个第一子显示区A1a内靠近第二显示区A2的第一发光元件21与第三个第一子显示区A1c内远离第二显示区A2的第一像素电路31电连接，第一个第一子显示区A1a内远离第二显示区A2的第一发光元件21与第三个第一子显示区A1c内靠近第二显示区A2的第一像素电路31电连接。第二个第一子显示区A1b内靠近第二显示区A2的第一发光元件21与第四个第一子显示区A1d内远离第二显示区A2的第一像素电路31电连接，第二个第一子显示区A1b内远离第二显示区A2的第一发光元件21与第四个第一子显示区A1d内靠近第二显示区A2的第一像素电路31电连接。本示例的第一发光元件21和第一像素电路31的连接方式可以避免透明导电线交叠引起短路或干扰等问题。
在一些示例中，如图10至图11G所示，电连接第三个第一子显示区A1c内的第一发光元件21和第五个第一子显示区A1e内的第一像素电路31的第五透明导电线51c可以位于第二透明导电层42。电连接第四个第一子显示区A1d内的第一发光元件21和第六个第一子显示区A1f内的第一像素电路31的第六透明导电线51d可以位于第三透明导电层43。电连接第五个第一子显示区A1e内的第一发光元件21和第七个第一子显示区A1g内的第一像素电路31的第七透明导电线51e可以位于第一透明导电层41。电连接第六个第一子显示区A1f内的第一发光元件21和第八个第一子显示区A1h内的第一像素电路31的第八透明导电线51f可以位于第二透明导电层42。电连接第七个第一子显示区A1g内的第一发光元件21和第九个第一子显示区A1i内的第一像素电路31的第九透明导电线51g可以位于第三透明导电层43。电连接第八个第一子显示区A1h内的第一发光元件21和第十个第一子显示区A1j内的第一像素电路31的第十透明导电线51h可以位于第一透明导电层41。第九个第一子显示区A1i的第一发光元件21电连接的第十一透明导电线51i可以位于第二透明导电层42，第十个第一子显示区Alj的第一发光元件21电连接的第十二透明导电线51j可以位于第三透明导电层43。关于一个第一 子显示区的第一发光元件21和另一个第一子显示区的第一像素电路31的连接方式可以参照第二发光元件22和第二像素电路32的连接方式，故于此不再赘述。
在本示例中，第一个第一子显示区A1a和第二个第一子显示区A1b内的像素电路可以均为第二像素电路。第三个第一子显示区A1c至第十个第一子显示区A1j内的像素电路可以均为第一像素电路。通过将第二像素电路集中设置在一起且靠近第二显示区，可以减小电连接第二发光元件和第二像素电路的透明导电线的长度。
在本示例中，任一个第一子显示区内的第一发光元件的数目可以小于或等于所述第一子显示区靠近第二显示区一侧的相邻第一子显示区内的第一发光元件的数目。例如，第二个第一子显示区A1b内的第一发光元件21的数目可以小于第一个第一子显示区A1a内的第一发光元件的数目，第三个第一子显示区A1c内的第一发光元件21的数目可以小于第二个第一子显示区A1a内的第一发光元件的数目。在本示例中，第一子显示区的大小可以随着远离第一分区A21一侧减小。
在本示例中，第三个第一子显示区A1c以及第三个第一子显示区A1c远离第二显示区一侧的第一子显示区内的像素电路可以均为第一像素电路。第三个第一子显示区A1c内的第一像素电路31的数目可以小于第一个第一子显示区A1a内的第一像素电路31的数目。在第三个第一子显示区A1c至第十个第一子显示区A1j中，任一第一子显示区内的第一像素电路31的数目可以小于或等于所述第一子显示区靠近第二显示区一侧的相邻第一子显示区内的第一像素电路31的数目。
在本示例中，一个第一子显示区内的多个第一发光元件21所电连接的透明导电线可以为同层结构。一个第一子显示区内的第一发光元件21所电连接的透明导电线与该第一子显示区内的像素电路所电连接的透明导电线可以为异层结构。例如，第一个第一子显示区A1a内的第一发光元件21电连接的第三透明导电线51a可以位于第三透明导电层，第一个第一子显示区A1a内的第二像素电路32电连接的第一透明导电线52a可以位于第一透明导电层。如此一来，可以减小透明导电线之间的相互干扰。
图12为本公开至少一实施例的第一透明导电层的示意图。图13为本公开至少一实施例的第二透明导电层的示意图。图14为本公开至少一实施例的第三透明导电层的示意图。图15为本公开至少一实施例的三个透明导电层的示意图。图12至图15中示意了多行像素电路和发光元件的连接关系，单行像素电路和发光元件的连接关系可以参照图11A至图11G所示。
在一些示例性实施方式中，如图10至图15所示，第一透明导电线52a、第四透明导电线51b、第七透明导电线51e和第十透明导电线51h可以位于第一透明导电层41。第二透明导电线52b、第五透明导电线51c、第八透明导电线51f和第十一透明导电线51i可以位于第二透明导电层42。第三透明导电线51a、第六透明导电线51d、第九透明导电线51g和第十二透明导电线51j可以位于第三透明导电层43。然而，本实施例对此并不限定。例如，第一透明导电线52a、第四透明导电线51b、第七透明导电线51e和第十透明导电线51h可以位于第二透明导电层42；第二透明导电线52b、第五透明导电线51c、第八透明导电线51f和第十一透明导电线51i可以位于第三透明导电层43；第三透明导电线51a、第六透明导电线51d、第九透明导电线51g和第十二透明导电线51j可以位于第一透明导电层41。或者，在另一些示例中，显示基板可以包括四个透明导电层。第一透明导电线52a至第十二透明导电线51j可以分别排布在四个透明导电层。
如图10至图15所示，本示例中的最长透明导电线可以为电连接第一个第二子显示区A2a内距离第一显示区A1最远的第二发光元件与第一个第一子显示区A1a内距离第二显示区A2最远的第二像素电路的第一透明导电线52a。相较于在一些实现方式中，将第二子显示区A2a内的第二发光元件与第十个第一子显示区的第二像素电路通过透明导电线电连接而言，本示例可以减小电连接第二发光元件22和第二像素电路32的透明导电线的长度，改善透明导电线之间长度差异过大的情况，从而可以改善屏下显示区画面均匀度差的问题，实现更加均匀的全面屏视觉显示效果。
在一些示例性实施方式中，如图8所示，第一显示区A1的第二辅助区A12可以包括：在第二方向(本示例中平行于行方向X)沿着远离第二分区A22的一侧依次排布的多个第三子显示区。第二分区A22可以包括：在第二 方向沿着远离第二辅助区A12的一侧依次排布的多个第四子显示区。第四子显示区内的第二发光元件可以通过第二导电线与一个第三子显示区内的第二像素电路电连接，该第三子显示区内的第一发光元件可以通过第一导电线与远离第二分区A22一侧的另一个第三子显示区内的第一像素电路电连接。在一些示例中，第二分区A22和第二辅助区A12之间的连接方式可以根据第一分区A21和第一辅助区A11之间的连接方式关于中轴线OO’镜像得到。此时，第三子显示区的数目和第一子显示区的数目可以相同，第二子显示区的数目和第四子显示区的数目可以相同。在另一些示例中，可以参照第一分区A21和第一辅助区A11之间的连接规律来得到第二分区A22和第二辅助区A12之间的连接方式。此时，第三子显示区的数目和第一子显示区的数目可以不同，第二子显示区的数目和第四子显示区的数目可以不同，第三子显示区和第四子显示区的像素电路和发光元件的连接方式可以不同于第一子显示区和第二子显示区的像素电路和发光元件的连接方式。例如，第一子显示区和第二显示区可以采用图9所示的连接方式，第三子显示区和第四子显示区可以采用图18或图19类似的连接方式。然而，本实施例对此并不限定。
下面对显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层。
在一些示例性实施方式中，形成半导体层可以包括：在衬底基板100上 沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，在第一显示区A1形成半导体层10，如图6A所示。一个像素电路的七个晶体管的有源层可以为相互连接的一体结构。
在一些示例性实施方式中，半导体层10的材料例如可以包括多晶硅。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。多个掺杂区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。在一些示例中，有源层的掺杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
在一些示例性实施方式中，衬底基板100可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如衬底基板可以为柔性基板。
(2)、形成第一导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板100上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层的第一绝缘层101，以及在第一显示区A1设置在第一绝缘层101上的第一导电层11，如图6B所示。
(3)、形成第二导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板100上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层11的第二绝缘层102，以及在第一显示区A1设置在第二绝缘层102上的第二导电层12，如图6C所示。
(4)、形成第三绝缘层。
在一些示例性实施方式中，在形成前述图案的衬底基板100上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层103，如图6D所示。
(5)、形成第三导电层。
在一些示例性实施方式中，在形成前述图案的衬底基板上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第一显示区A1的第 三绝缘层103上形成第三导电层13，如图4所示。
至此，制备完成第一显示区A1的像素电路。第二显示区A2可以包括：衬底基板100以及叠设在衬底基板100上的第一绝缘层101、第二绝缘层102和第三绝缘层103。
(6)、依次形成第一平坦层、第一透明导电层、第二平坦层、第二透明导电层、第三平坦层、第三透明导电层、第四平坦层、阳极层、像素定义层、有机发光层以及阴极层。
在一些示例性实施方式中，在形成前述图案的衬底基板100上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成第一平坦层。随后，在形成前述图案的衬底基板上沉积第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成第一透明导电层。随后，在形成前述图案的衬底基板上涂覆第二平坦薄膜，通过图案化工艺对第二平坦薄膜进行图案化，形成第二平坦层。随后，在形成前述图案的衬底基板上沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行图案化，形成第二透明导电层。随后，在形成前述图案的衬底基板上涂覆第三平坦薄膜，通过图案化工艺对第三平坦薄膜进行图案化，形成第三平坦层。随后，在形成前述图案的衬底基板上沉积第三透明导电薄膜，通过图案化工艺对第三透明导电薄膜进行图案化，形成第三透明导电层。关于第一透明导电层、第二透明导电层和第三透明导电层的透明导电线的排布可以参照图10至图15所示。
随后，在形成前述图案的衬底基板上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。随后，在形成前述图案的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层。像素定义层形成有暴露出阳极层的多个像素开口。随后，在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极层，阴极层分别与有机发光层和第二电源线电连接。在一些示例中，在阴极层上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例性实施方式中，第一导电层11、第二导电层12和第三导电层13可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中 的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层101、第二绝缘层102和第三绝缘层103可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层101和第二绝缘层102可以称之为栅绝缘(GI)层，第三绝缘层103可以称之为层间绝缘(ILD)层。第一平坦层至第四平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极层可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，在第三导电层远离衬底基板一侧可以设置第四绝缘层和第四导电层，第四导电层可以包括连接像素电路和透明导电线的阳极连接电极。在一些示例中，电连接第一发光元件和第一像素电路的第一导电线可以设置在第四导电层。在另一些示例中，可以设置一个或两个透明导电层。然而，本实施例对此并不限定。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与已有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图16为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图。在本示例中，以第一个第二子显示区A2a和第一个第一子显示区A1a为例进行示意。如图16所示，在第一个第二子显示区A2a内，相邻第二发光元件22所电连接的第二导电线可以为异层结构。比如，其中一个第二发光元件22可以通过第十三透明导电线52a与第一个第一子显示区A1a内的第二像素电路32电连接，在行方向X上与该第二发光元件22相邻的一个第二发光元件22可以通过第十四透明导电线52b与第一个第一子显示区A1a内的另一个第二像素电路32电连接。其中，第十三透明导电线52a和第十四透明导电线52b可以为异层结构，即位于不同的透明导电层。例如，第十三 透明导电线52a可以位于第一透明导电层，第十四透明导电线52b可以位于第四透明导电层，第四透明导电层可以位于第三透明导电层远离衬底基板的一侧。然而，本实施例对此并不限定。在本示例中，一个第一子显示区内的第一发光元件与另一个第一子显示区内的第一像素电路的连接方式可以与本示例的第二发光元件22和第二像素电路32的连接方式相似，故于此不再赘述。
关于本实施例的显示基板的像素电路和发光元件的其余连接方式可以参照前述实施例的说明，故于此不再赘述。
图17为本公开至少一实施例的第一子显示区和第二子显示区的另一连接示意图。在本示例中，以第一个第二子显示区A2a和第一个第一子显示区A1a为例进行示意。如图17所示，第一个第二子显示区A2a内靠近第一显示区的第二发光元件22可以与第一个第一子显示区A1a内远离第二显示区的第二像素电路32电连接，第一个第二子显示区A2a内远离第一显示区的第二发光元件22可以与第一个第一子显示区A1a内靠近第二显示区的第二像素电路32电连接。在第一个第二子显示区A2a内，第二发光元件22可以通过第十五透明导电线52c与第一个第一子显示区A1a内的第二像素电路32电连接。在一些示例中，第十五透明导电线52c可以由多个导电线段连接形成。所述多个导电线段可以位于不同透明导电层。例如，一个第十五透明导电线52c可以包括：位于第一透明导电层的第一导电线段、位于第二透明导电层的第二导电线段和位于第一透明导电层的第三导电线段。第一导电线段可以与第二发光元件22电连接，第三导电线段可以与第二像素电路32电连接，第二导电线段可以连接第一导电线段和第三导电线段。然而，本实施例对此并不限定。
在本示例中，一个第一子显示区内的第一发光元件与另一个第一子显示区内的第一像素电路的连接方式可以与本示例的第二发光元件22和第二像素电路32的连接方式相似，故于此不再赘述。
关于本实施例的显示基板的像素电路和发光元件的其余连接关系可以参照前述实施例的说明，故于此不再赘述。
图18为本公开至少一实施例的第一子显示区和第二子显示区的另一连 接示意图。如图18所示，第一个第二子显示区A2a的第二发光元件可以通过第十六透明导电线53a与第二个第一子显示区A1b的第二像素电路电连接。第二个第二子显示区A2b的第二发光元件可以通过第十七透明导电线53b与第一个第二子显示区A1a的第二像素电路电连接。在一些示例中，第十六透明导电线53a和第十七透明导电线53b可以位于同一透明导电层，例如可以位于第一透明导电层。然而，本实施例对此并不限定。在另一些示例中，第十六透明导电线53a和第十七透明导电线53b可以位于不同的透明导电层。
关于本实施例的显示基板的像素电路和发光元件的其余连接关系可以参照前述实施例的说明，故于此不再赘述。
图19为本公开至少一实施例的第一子显示区和第二子显示区的再一连接示意图。在本示例中，如图19所示，第二显示区的第一分区A21整体可以作为一个第二子显示区。与第二子显示区相邻的第一辅助区A11可以包括：多个第一子显示区(例如包括在行方向X上沿着远离第一分区A21一侧依次排布的第一个第一子显示区A1-1至第五个第一子显示区A1-5)。第一分区A21内的第二发光元件可以通过第十八透明导电线61a与第一个第一子显示区A1-1内的第二像素电路电连接。第一个第一子显示区A1-1内的第一发光元件可以通过第十九透明导电线61b与第二个第一子显示区A1-2内的第一像素电路电连接。第二个第一子显示区A1-2内的第一发光元件可以通过第二十透明导电线61c与第三个第一子显示区A1-3内的第一像素电路电连接。第三个第一子显示区A1-3内的第一发光元件可以通过第二十一透明导电线61d与第四个第一子显示区A1-4的第一像素电路电连接。第四个第一子显示区A1-4内的第一发光元件可以通过第二十二透明导电线61e与第五个第一子显示区A1-5内的第一像素电路电连接。第五个第一子显示区A1-5内的第一发光元件可以通过第二十三透明导电线61f与第五个第一子显示区A1-5远离第二显示区一侧的区域内的第一像素电路电连接。在本示例中，一个第一子显示区的第一发光元件可以与远离第二显示区一侧的相邻第一子显示区内的第一像素电路电连接。在本示例中，n可以为1，i可以为1。关于本示例中的不同区域的发光元件和像素电路的连接方式可以参照前述实施例的说明，故于此不再赘述。
在本示例中，第二导电线可以包括：第十八透明导电线61a和第十九透明导电线61b；第一导电线可以包括：第二十透明导电线61c至第二十三透明导电线61f。第十八透明导电线61a和第十九透明导电线61b可以为异层结构，即位于不同透明导电层。本示例可以设置两个透明导电层。例如，第十八透明导电线61a、第二十透明导电线61c和第二十二透明导电线61e可以为同层结构且位于第一透明导电层，第十九透明导电线61b、第二十一透明导电线61d和第二十三透明导电线61f可以为同层结构且位于第二透明导电层。第二透明导电层可以位于第一透明导电层远离衬底基板的一侧。然而，本实施例对此并不限定。关于本实施例的透明导电线的膜层设置可以参照前述实施例的说明，故于此不再赘述。
图20为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，可以通过减小第一像素电路在列方向Y上的尺寸来获得设置第二像素电路的区域。在本示例中，第一方向可以为列方向Y。如图20所示，第一显示区A1可以包括：在列方向Y上与第二显示区A2相邻的第三辅助区A13，第三辅助区A13可以包括：在列方向Y沿着远离第二显示区A2一侧依次设置的多个第一子显示区。第二显示区A2可以包括沿列方向Y划分的多个第二子显示区，例如两个第二子显示区。第二子显示区的第二发光元件可以通过第二导电线52与第一子显示区的第二像素电路电连接，第一子显示区的第一发光元件可以通过第一导电线51与在列方向Y上远离第二显示区A2一侧的另一个第一子显示区内的第一像素电路电连接。关于本实施例的第一子显示区和第二子显示区之间的连接关系、像素电路和发光元件之间的连接方式可以参照前述实施例的说明，经过方向上的简单变换即可得到，故于此不再赘述。
图21为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图21所示，第二显示区A2可以位于显示区域的顶部，且在列方向Y上位于第一显示区A1的一侧。在一些示例中，可以通过减小第一像素电路在列方向Y上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图21所示，第一显示区A1可以包括：在第一方向(本 示例中平行于列方向Y)沿着远离第二显示区A2的一侧依次设置的多个第一子显示区A11a。第二显示区A2可以包括：沿列方向Y划分的多个第二子显示区，或者可以整体作为一个第二子显示区。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第二显示区A2的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与远离第二显示区A2的另一个第一子显示区A11a内的第一像素电路电连接。关于本实施例的第一子显示区和第二子显示区之间的连接关系、像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图22为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图22所示，第二显示区A2可以位于显示区域的左半区域，且在行方向X上位于第一显示区A1的一侧。在一些示例中，可以通过减小第一像素电路在行方向X上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图22所示，第一显示区A1可以包括：在第一方向(本示例中平行于行方向X)沿着远离第二显示区A2的一侧依次设置的多个第一子显示区A11a。第二显示区A2可以包括：沿行方向X划分的多个第二子显示区，或者可以整体作为一个第二子显示区。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第二显示区A2的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第二显示区A2一侧的另一个第一子显示区A11a内的第一像素电路电连接。关于本实施例的第一子显示区和第二子显示区之间的连接关系、像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图23为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图23所示，第二显示区A2可以位于显示区域的中间区域，且在行方向X上在两侧均与第一显示区A1相邻。在一些示例中，可以通过减小第一像素电路在行方向X上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图23所示，第二显示区A2可以包括：沿行方向X划分的第一分区A21和第二分区A22。第一分区A21可以包括：沿第一方向(本示例中平行于行方向X)划分的多个第二子显示区，或者，第一分区A21可以整体作为一个第二子显示区。第二分区A22可以包括：沿第二方向(本示例中平行于行方向X)划分的多个第四子显示区，或者，第二分区A22可以整体作为一个第四子显示区。在一些示例中，第一分区A21和第二分区A22可以关于第二显示区A2在行方向X上的中轴线大致对称。然而，本实施例对此并不限定。
在一些示例中，如图23所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、以及在第二方向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图24为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图24所示，第二显示区A2可以位于显示区域的左上角，第二显示区A2在行方向X和列方向Y均与第一显示区A1相邻。在一些示例中，可以通过减小第一像素电路在行方向X和列方向Y上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图24所示，第二显示区A2可以包括：第一分区A21和第二分区A22。第一分区A21可以包括：沿第一方向(本示例中平行于列 方向Y)划分的多个第二子显示区，或者，第一分区A21整体作为一个第二子显示区。第二分区A22可以包括：沿第二方向(本示例中平行于行方向X)划分的多个第四子显示区，或者，第二分区A22整体作为一个第四子显示区。在一些示例中，第一分区A21和第二分区A22可以关于第二显示区A2的对角线大致对称。然而，本实施例对此并不限定。例如，第一分区A21和第二分区A22可以关于第二显示区A2在行方向X或列方向Y的中轴线大致对称。
在一些示例中，如图24所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、以及在第二方向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图25为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图25所示，第二显示区A2可以位于显示区域的顶部中间位置，且第一显示区A1围绕在第二显示区A2的四周。在一些示例中，可以通过减小第一像素电路在行方向X和列方向Y上的尺寸来获得设置第二像素电路的区域。如图25所示，第二显示区A2可以包括第一分区A21和第二分区A22，第一分区A21和第二分区A22可以关于第二显示区A2在行方向X的中轴线OO’大致对称。第一显示区A1可以包括：在第一方向(本示例中平行于行方向X)上沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、以及在第二方向(本示例中平行于列方向Y)沿着远离第二 分区A22的一侧依次设置的多个第三子显示区A12a。第一分区A21可以包括沿第一方向划分的多个第二子显示区，或者第一分区A21整体作为一个第二子显示区。第二分区A22可以包括沿第二方向划分的多个第四子显示区，或者，第二分区A22整体作为一个第四子显示区。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图26为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图26所示，第二显示区A2可以位于显示区域的顶部中间位置，且第一显示区A1围绕在第二显示区A2的四周。在一些示例中，可以通过减小第一像素电路在行方向X和列方向Y上的尺寸来获得设置第二像素电路的区域。如图26所示，第二显示区A2可以包括：第一分区A21、第二分区A22和第三分区A23。例如，第一分区A21、第二分区A22和第三分区A23可以通过对第二显示区A2在行方向X上划分得到。然而，本实施例对此并不限定。第一分区A21可以包括沿第一方向(本示例中平行于行方向X)划分的多个第二子显示区，或者，第一分区A21可以整体作为一个第二子显示区。第二分区A22可以包括沿第二方向(本示例中平行于行方向X)划分的多个第四子显示区，或者，第二分区A22可以整体作为一个第四子显示区。第三分区A23可以包括沿第三方向(本示例中平行于列方向Y)划分的多个第六子显示区，或者第三分区A23可以整体作为一个第六子显示区。
在一些示例中，如图26所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、在第二方 向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a、以及在第三方向沿着远离第三分区A23的一侧依次设置的多个第五子显示区A13a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。第六子显示区内的第二发光元件可以通过第二导电线52与最靠近第三分区A23的一个第五子显示区A13a内的第二像素电路电连接，该第五子显示区A13a内的第一发光元件可以通过第一导电线51与沿着远离第三分区A23一侧的另一个第五子显示区A13a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、第五子显示区和第六子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图27为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图27所示，第二显示区A2可以位于显示区域的顶部中间位置，且第一显示区A1围绕在第二显示区A2的四周。在一些示例中，可以通过减小第一像素电路在列方向Y和行方向X上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图27所示，第二显示区A2可以包括：第一分区A21、第二分区A22、第三分区A23和第四分区A24。例如，第一分区A21、第二分区A22、第三分区A23和第四分区A24可以通过对第二显示区A2在行方向X和列方向Y划分得到，或者，可以通过对第二显示区A2沿对角线方向划分得到。然而，本实施例对此并不限定。第一分区A21可以包括：沿第一方向(本示例中平行于行方向X)划分的多个第二子显示区，或者，第一分 区A21可以整体作为一个第二子显示区。第二分区A22可以包括沿第二方向(本示例中平行于行方向X)划分的多个第四子显示区，或者，第二分区A22可以整体作为一个第四子显示区。第三分区A23可以包括沿第三方向(本示例中平行于列方向Y)划分的多个第六子显示区，或者，第三分区A23可以整体作为一个第六子显示区。第四分区A24可以包括沿第四方向(本示例中平行于列方向Y)划分的多个第八子显示区，或者，第四分区A24可以整体作为一个第八子显示区。
在一些示例中，如图27所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、在第二方向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a、在第三方向沿着远离第三分区A23的一侧依次设置的多个第五子显示区A13a、在第四方向沿着远离第四分区A24的一侧依次设置的多个第七子显示区A14a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。第六子显示区内的第二发光元件可以通过第二导电线52与最靠近第三分区A23的一个第五子显示区A13a内的第二像素电路电连接，该第五子显示区A13a内的第一发光元件可以通过第一导电线51与沿着远离第三分区A23一侧的另一个第五子显示区A13a内的第一像素电路电连接。第八子显示区内的第二发光元件可以通过第二导电线52与最靠近第四分区A24的一个第七子显示区A14a内的第二像素电路电连接，该第七子显示区A14a内的第一发光元件可以通过第一导电线51与沿着远离第四分区A24一侧的另一个第七子显示区A14a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子 显示区和第四子显示区之间的连接关系、第五子显示区和第六子显示区之间的连接关系、第七子显示区和第八子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图28为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，如图28所示，第二显示区A2可以位于显示区域的顶部中间位置，且第一显示区A1在三侧围绕在第二显示区A2的周围。第二显示区A2的上侧直接与周边区域BB相邻，第一显示区A1围绕在第二显示区A2的下侧、左侧和右侧。关于本实施例的第一显示区和第二显示区的区域划分和连接关系可以参照图26所示，故于此不再赘述。
图29为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在一些示例中，可以通过减小第一像素电路在行方向X和列方向Y上的尺寸来获得设置第二像素电路的区域。然而，本实施例对此并不限定。
在一些示例中，如图29所示，第二显示区可以位于显示区域的顶部中间位置，且第一显示区A1围绕在第二显示区的四周。第二显示区可以包括：第一分区A21、第二分区A22、第三分区A23和第四分区A24。第一分区A21、第二分区A22、第三分区A23和第四分区A24可以通过对第二显示区A2按照第五方向F上的中轴线RR’和第六方向E上的中轴线PP’划分得到。在一些示例中，第五方向F和第六方向E均与行方向X和列方向Y交叉。例如，第五方向F和第六方向E可以垂直相交，第五方向F可以位于行方向X和列方向Y之间，第五方向F和行方向X之间沿顺时针方向的夹角可以约为45度。然而，本实施例对此并不限定。例如，第五方向F和行方向X之间沿顺时针方向的夹角可以约为30度至60度。
在一些示例中，如图29所示，第一分区A21可以包括：沿第一方向(本示例中平行于行方向X)划分的多个第二子显示区，或者，第一分区A21可以整体作为一个第二子显示区。第二分区A22可以包括：沿第二方向(本示例中平行于行方向X)划分的多个第四子显示区，或者，第二分区A22可以整体作为一个第四子显示区。第三分区A23可以包括：沿第三方向(本示例中平行于列方向Y)划分的多个第六子显示区，或者，第三分区A23可以整体作为一个第六子显示区。第四分区A24可以包括：沿第四方向(本示例中 平行于列方向Y)划分的多个第八子显示区，或者第四分区A24可以整体作为一个第八子显示区。
在一些示例中，如图29所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、在第二方向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a、在第三方向沿着远离第三分区A23的一侧依次设置的多个第五子显示区A13a、以及在第四方向沿着远离第四分区A24的一侧依次设置的多个第七子显示区A14a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。第六子显示区内的第二发光元件可以通过第二导电线52与最靠近第三分区A23的一个第五子显示区A13a内的第二像素电路电连接，该第五子显示区A13a内的第一发光元件可以通过第一导电线51与沿着远离第三分区A23一侧的另一个第五子显示区A13a内的第一像素电路电连接。第八子显示区内的第二发光元件可以通过第二导电线52与最靠近第四分区A24的一个第七子显示区A14a内的第二像素电路电连接，该第七子显示区A14a内的第一发光元件可以通过第一导电线51与沿着远离第四分区A24一侧的另一个第七子显示区A14a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、第五子显示区和第六子显示区之间的连接关系、第七子显示区和第八子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
图30为本公开至少一实施例的第一显示区和第二显示区的另一连接示意图。在本示例中，可以通过减小第一像素电路在行方向X和列方向Y上的 尺寸来获得设置第二像素电路的区域。在本示例中，如图30所示，第二显示区可以位于显示区域的顶部中间位置，且第一显示区A1围绕在第二显示区的四周。第二显示区可以包括：第一分区A21、第二分区A22、第三分区A23和第四分区A24。第一分区A21至第四分区A24可以按照第二显示区在行方向X上的中轴线OO’和列方向Y的中轴线UU’划分得到。
在一些示例中，如图30所示，第一分区A21可以包括：沿第一方向(本示例中平行于第六方向E)划分的多个第二子显示区，或者，第一分区A21可以整体作为一个第二子显示区。第二分区A22可以包括：沿第二方向(本示例中平行于第五方向F)划分的多个第四子显示区，或者，第二分区A22可以整体作为一个第四子显示区。第三分区A23可以包括：沿第三方向(本示例中平行于第六方向E)划分的多个第六子显示区，或者，第三分区A23可以整体作为一个第六子显示区。第四分区A24可以包括：沿第四方向(本示例中平行于第五方向F)划分的多个第八子显示区，或者，第四分区A24可以整体作为一个第八子显示区。
在一些示例中，如图30所示，第一显示区A1可以包括：在第一方向沿着远离第一分区A21的一侧依次设置的多个第一子显示区A11a、在第二方向沿着远离第二分区A22的一侧依次设置的多个第三子显示区A12a、在第三方向沿着远离第三分区A23的一侧依次设置的多个第五子显示区A13a、以及在第四方向沿着远离第四分区A24的一侧依次设置的多个第七子显示区A14a。第二子显示区内的第二发光元件可以通过第二导电线52与最靠近第一分区A21的一个第一子显示区A11a内的第二像素电路电连接，该第一子显示区A11a内的第一发光元件可以通过第一导电线51与沿着远离第一分区A21一侧的另一个第一子显示区A11a内的第一像素电路电连接。第四子显示区内的第二发光元件可以通过第二导电线52与最靠近第二分区A22的一个第三子显示区A12a内的第二像素电路电连接，该第三子显示区A12a内的第一发光元件可以通过第一导电线51与沿着远离第二分区A22一侧的另一个第三子显示区A12a内的第一像素电路电连接。第六子显示区内的第二发光元件可以通过第二导电线52与最靠近第三分区A23的一个第五子显示区A13a内的第二像素电路电连接，该第五子显示区A13a内的第一发光元件可 以通过第一导电线51与沿着远离第三分区A23一侧的另一个第五子显示区A13a内的第一像素电路电连接。第八子显示区内的第二发光元件可以通过第二导电线52与最靠近第四分区A24的一个第七子显示区A14a内的第二像素电路电连接，该第七子显示区A14a内的第一发光元件可以通过第一导电线51与沿着远离第四分区A24一侧的另一个第七子显示区A14a内的第一像素电路电连接。
关于本实施例的第一子显示区和第二子显示区之间的连接关系、第三子显示区和第四子显示区之间的连接关系、第五子显示区和第六子显示区之间的连接关系、第七子显示区和第八子显示区之间的连接关系、以及像素电路和发光元件之间的连接方式可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图31为本公开至少一实施例的显示装置的示意图。如图31所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的显示结构层的出光侧的感光传感器92。感光传感器92在显示基板91上的正投影与第二显示区A2存在交叠。
在一些示例性实施方式中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (24)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧；
    多个像素电路，包括位于所述第一显示区的多个第一像素电路和多个第二像素电路；
    多个发光元件，包括位于所述第一显示区的多个第一发光元件和位于所述第二显示区的多个第二发光元件；
    所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件电连接，所述至少一个第一像素电路被配置为驱动所述至少一个第一发光元件发光，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接，所述至少一个第二像素电路被配置为驱动所述至少一个第二发光元件发光；
    所述第一显示区包括：在第一方向沿着远离所述第二显示区的一侧依次排布的第一个第一子显示区至第N个第一子显示区，其中，N为大于1的整数；
    所述第二显示区包括至少一个第二子显示区，所述第二子显示区的第二发光元件与第n个第一子显示区的第二像素电路电连接，所述第n个第一子显示区的第一发光元件与第n+i个第一子显示区的第一像素电路电连接，其中，n和i均为大于0且小于N的整数。
  2. 根据权利要求1所述的显示基板，其中，所述第n+i个第一子显示区的第一发光元件与第n+i+j个第一子显示区的第一像素电路电连接，其中，j为大于0且小于N的整数。
  3. 根据权利要求2所述的显示基板，其中，j等于i。
  4. 根据权利要求2或3所述的显示基板，其中，所述至少一个第一像素电路与所述至少一个第一发光元件通过第一导电线电连接，所述至少一个第二像素电路与所述至少一个第二发光元件通过第二导电线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述至少一个第一子显示区 内的至少一个像素电路所电连接的第一导电线或第二导电线与至少一个第一发光元件所电连接的第一导电线为异层结构。
  6. 根据权利要求5所述的显示基板，其中，电连接所述第n个第一子显示区的第二像素电路和所述第二子显示区的第二发光元件的第二导电线，与电连接所述第n个第一子显示区的第一发光元件和第n+i个第一子显示区的第一像素电路的第一导电线为异层结构。
  7. 根据权利要求5所述的显示基板，其中，电连接所述第n+i个第一子显示区的第一发光元件和第n+i+j个第一子显示区的第一像素电路的第一导电线，与电连接所述第n+i个第一子显示区的第一像素电路和所述第n个第一子显示区的第一发光元件的第一导电线为异层结构。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述至少一个第一子显示区内的像素电路的数目大于第一发光元件的数目。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述第n个第一子显示区内的像素电路均为第二像素电路。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述第n个第一子显示区的像素电路的数目大于或等于第n+1个第一子显示区的像素电路的数目，所述第n个第一子显示区的第一发光元件的数目大于或等于第n+1个第一子显示区的第一发光元件的数目。
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述第二子显示区内靠近所述第n个第一显示区的第二发光元件与所述第n个第一子显示区内靠近所述第二子显示区的第二像素电路电连接，所述第二子显示区内远离所述第n个第一子显示区的第二发光元件与所述第n个第一子显示区内远离所述第二子显示区的第二像素电路电连接。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，所述第一显示区的像素电路阵列排布，所述第一方向为所述像素电路的行方向。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述第二显示区包括：在所述第一方向沿着远离所述第一子显示区的一侧依次排布的第M个第二子显示区至第一个第二子显示区，其中，M为大于1且小于N的整 数；
    其中，第m个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区，位于第m+1个第二子显示区内的第二发光元件电连接的第二像素电路所在的第一子显示区靠近所述第二显示区的一侧，m为大于0且小于M的整数。
  14. 根据权利要求4至13中任一项所述的显示基板，其中，相邻第二子显示区内的第二发光元件电连接的第二导电线位于不同导电层，相邻第一子显示区内的第一发光元件电连接的第一导电线位于不同导电层。
  15. 根据权利要求4至14中任一项所述的显示基板，其中，所述第二子显示区内的多个第二发光元件电连接的第二导电线为同层结构。
  16. 根据权利要求4至13中任一项所述的显示基板，其中，所述第二子显示区内在所述第一方向上相邻的第二发光元件电连接的第二导电线为异层结构。
  17. 根据权利要求4至7以及14至16中任一项所述的显示基板，其中，所述第一导电线和第二导电线为透明导电线。
  18. 根据权利要求1至17中任一项所述的显示基板，其中，所述第一显示区还包括：在第二方向沿着远离所述第二显示区的一侧依次排布的第一个第三子显示区至第H个第三子显示区，其中，H为大于1的整数；
    所述第二显示区还包括：至少一个第四子显示区，所述第四子显示区的第二发光元件与第h个第三子显示区的第二像素电路电连接，所述第h个第三子显示区的第一发光元件与第h+s个第三子显示区的第一像素电路电连接，其中，h和s均为大于0且小于H的整数。
  19. 根据权利要求18所述的显示基板，其中，所述第二方向与所述第一方向平行，或者，所述第二方向与所述第一方向交叉。
  20. 根据权利要求18或19所述的显示基板，其中，所述第一显示区还包括：在第三方向沿着远离所述第二显示区的一侧依次排布的第一个第五子显示区至第R个第五子显示区，其中，R为大于1的整数；
    所述第二显示区还包括：至少一个第六子显示区，所述第六子显示区的 第二发光元件与第r个第五子显示区的第二像素电路电连接，所述第r个第五子显示区的第一发光元件与第r+k个第五子显示区的第一像素电路电连接，其中，r和k均为大于0且小于R的整数。
  21. 根据权利要求20所述的显示基板，其中，所述第一显示区还包括：在第四方向沿着远离所述第二显示区的一侧依次排布的第一个第七子显示区至第G个第七子显示区，其中，G为大于1的整数；
    所述第二显示区还包括：至少一个第八子显示区，所述第八子显示区的第二发光元件与第g个第七子显示区的第二像素电路电连接，所述第g个第七子显示区的第一发光元件与第g+d个第七子显示区的第一像素电路电连接，其中，g和d均为大于0且小于G的整数。
  22. 根据权利要求1至21中任一项所述的显示基板，其中，所述第二发光元件的密度小于或等于所述第一发光元件的密度。
  23. 根据权利要求1至22中任一项所述的显示基板，其中，所述第一显示区的分辨率小于或等于所述第二显示区的分辨率。
  24. 一种显示装置，包括：如权利要求1至23中任一项所述的显示基板。
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CN111834399A (zh) * 2020-01-19 2020-10-27 昆山国显光电有限公司 显示面板及显示装置
CN111916486A (zh) * 2020-08-27 2020-11-10 武汉天马微电子有限公司 显示面板及显示装置
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WO2021237540A1 (zh) * 2020-05-27 2021-12-02 京东方科技集团股份有限公司 显示面板及显示装置
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