WO2023159509A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2023159509A1
WO2023159509A1 PCT/CN2022/078071 CN2022078071W WO2023159509A1 WO 2023159509 A1 WO2023159509 A1 WO 2023159509A1 CN 2022078071 W CN2022078071 W CN 2022078071W WO 2023159509 A1 WO2023159509 A1 WO 2023159509A1
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Prior art keywords
sub
light
display area
emitting element
display
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PCT/CN2022/078071
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English (en)
French (fr)
Inventor
杜丽丽
黄炜赟
张宇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/078071 priority Critical patent/WO2023159509A1/zh
Priority to CN202280000318.2A priority patent/CN116965175A/zh
Publication of WO2023159509A1 publication Critical patent/WO2023159509A1/zh

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  • This article relates to but not limited to the field of display technology, especially a display substrate, a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of a display device.
  • Embodiments of the disclosure provide a display substrate, a display panel, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a first display area and a second display area at least partially surrounding the first display area.
  • the display substrate includes: a base substrate, a pixel circuit and a light emitting element.
  • the pixel circuit is located on the base substrate of the second display area, and the pixel circuit includes first pixel circuits and second pixel circuits arranged alternately.
  • the light-emitting element is located on the side of the pixel circuit away from the base substrate, and the light-emitting element includes a first light-emitting element located in the first display area, a second sub-light-emitting element and a third sub-light-emitting element located in the second display area.
  • the first pixel circuit is electrically connected to the first light emitting element through at least part of the transparent conductive wire.
  • the second pixel circuit is electrically connected to the second sub-light-emitting element through a first transfer hole, and the orthographic projection of the first transfer hole on the base substrate is connected to the third sub-light-emitting element on the There is overlap in the orthographic projection of the substrate substrate.
  • the third sub-light-emitting element is disposed adjacent to the second sub-light-emitting element.
  • At least one second pixel circuit in the second display area is electrically connected to a first transfer line through the first transfer hole, and the first transfer line is connected to the second sub- The light-emitting element is electrically connected, and the connection position between the first transfer line and the second sub-light-emitting element does not exist in the orthographic projection of the base substrate and the orthographic projection of the third sub-light-emitting element on the base substrate overlap.
  • a first flat layer is provided between the first transfer line and the pixel circuit, and the first transfer line passes through the first transfer hole opened in the first flat layer and the pixel circuit.
  • the second pixel circuit is electrically connected.
  • a second flat layer is provided between the first transfer line and the light-emitting element, and the first transfer line is electrically connected to the second sub-light-emitting element through a third transfer hole opened in the second flat layer . There is no overlap between the orthographic projection of the third via hole on the base substrate and the orthographic projection of the third sub-light-emitting element on the base substrate.
  • the second display area includes: at least one third sub-display area, and the first pixel circuit in the third sub-display area is connected to the first display area through the first transparent conductive line.
  • the first light-emitting element inside is electrically connected, and the first transparent conductive line extends at least along the first direction.
  • At least one second pixel circuit in the third sub-display area is electrically connected to the second sub-light-emitting element through a first transfer line extending along the first direction.
  • the second display area includes: at least one fourth sub-display area, and the first pixel circuit in the fourth sub-display area is connected to the first display area through a second transparent conductive line.
  • the first light-emitting element inside is electrically connected, and the second transparent conductive line extends at least along a second direction, and the second direction intersects with the first direction.
  • At least one second pixel circuit in the fourth sub-display area is electrically connected to the second sub-light-emitting element through a first transfer line extending along the second direction.
  • the second display area further includes: a fifth sub-display area, and the first pixel circuits in the fifth sub-display area are invalid pixel circuits. At least one second pixel circuit in the fifth sub-display area is electrically connected to the second sub-light-emitting element through a first transfer line extending along any direction.
  • the first display area includes: at least one first sub-display area and at least one second sub-display area.
  • the third sub-display area is adjacent to at least one first sub-display area in the first direction
  • the fourth sub-display area is adjacent to at least one second sub-display area in the second direction.
  • the length ranges of the first transparent conductive wire and the second transparent conductive wire are approximately the same.
  • the light emitting element further includes a fourth sub light emitting element located in the second display area. At least one second pixel circuit in the second display area is electrically connected to the fourth sub-light-emitting element through a first via hole, and the orthographic projection of the first via hole on the base substrate and the The light-emitting regions of the fourth sub-light-emitting elements overlap in the orthographic projection of the base substrate.
  • the second pixel circuit is electrically connected to a second transfer wire through the first transfer hole, and the second transfer wire is electrically connected to the fourth sub-light-emitting element. There is no overlap between the orthographic projection of the base substrate and the light emitting region of the fourth sub-light-emitting element on the orthographic projection of the connection position between the second transfer line and the fourth sub-light-emitting element. .
  • the second display area includes at least: a third sub-display area and a fourth sub-display area.
  • the first pixel circuit in the third sub-display area is electrically connected to the first light-emitting element in the first display area through a first transparent conductive line, and the first transparent conductive line extends at least along a first direction.
  • the first pixel circuit in the fourth sub-display area is electrically connected to the first light-emitting element in the first display area through a second transparent conductive line, and the second transparent conductive line extends at least along the second direction, so The second direction intersects the first direction.
  • At least one second pixel circuit in the third sub-display area is electrically connected to the fourth sub-light-emitting element through a second transfer line extending along the first direction. At least one second pixel circuit in the fourth sub-display area is electrically connected to the fourth sub-light-emitting element through a second transfer line extending along the second direction.
  • the first pixel circuits and the second pixel circuits are alternately arranged in the first direction and the second direction; direction cross.
  • first direction four columns of second pixel circuits and one column of first pixel circuits are arranged alternately; in the second direction, four rows of second pixel circuits and one row of first pixel circuits are arranged alternately.
  • the pixel circuits are arranged alternately.
  • the pixel circuit includes: a driving transistor and a first transistor; a first electrode of the first transistor is electrically connected to a gate of the driving transistor.
  • the first transistor is a double-gate transistor.
  • the pixel circuit is electrically connected to the first initial signal line, and the orthographic projection of the first initial signal line on the base substrate is connected to the channel region of the active layer of the first transistor on the base substrate. Orthographic projections overlap.
  • the channel region of the active layer of the first transistor includes: a first channel region, a second channel region and a third channel region, and the third channel region is located in the between the first channel region and the second channel region;
  • the positive projection of the first gate of the first transistor on the base substrate covers the positive projection of the first channel region on the base substrate projection
  • the orthographic projection of the second gate of the first transistor on the base substrate covers the orthographic projection of the second channel region on the base substrate.
  • the orthographic projection of the first initial signal line on the substrate overlaps with the orthographic projection of the third channel region of the active layer of the first transistor on the substrate.
  • the orthographic projection of the third channel region on the base substrate is an inverted L shape.
  • the first initial signal line includes: a body portion extending along the first direction and an extension portion extending from the body portion along the second direction.
  • An orthographic projection of the protruding portion on the base substrate overlaps with an orthographic projection of the channel region of the active layer of the first transistor on the base substrate.
  • the pixel circuit includes a plurality of transistors and at least one storage capacitor; the transistor includes: an active layer, a gate, a first electrode and a second electrode, and the storage capacitor includes a first capacitor
  • the pole plate and the second capacitor plate, the gate of the transistor and one of the capacitor plates of the storage capacitor have the same layer structure, and the first pole and the second pole of the transistor have the same layer structure.
  • the first initial signal line and the other capacitive plate of the storage capacitor of the pixel circuit have the same layer structure.
  • an embodiment of the present disclosure provides a display panel, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display panel, and a photosensitive sensor disposed on a side of the non-display surface of the display panel, and the photosensitive sensor is projected on the orthographic projection of the display panel There is overlap with the first display area of the display substrate of the display panel.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit in at least one embodiment of the present disclosure
  • FIG. 3 is a working timing diagram of the pixel circuit provided in FIG. 2;
  • FIG. 4 is a partial schematic diagram of a display area of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the arrangement of the second light-emitting elements in the second display area of at least one embodiment of the present disclosure
  • FIG. 6 is a schematic partial plan view of a third sub-display area of the second display area in FIG. 1;
  • Fig. 7 A is the partial sectional schematic diagram along P-P ' direction in Fig. 6;
  • Figure 7B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 6;
  • FIG. 8 is a schematic partial plan view of the third sub-display region after the formation of the first flat layer in FIG. 6;
  • FIG. 9 is a partial plan view of the third sub-display area after the electrical connection layer is formed in FIG. 6;
  • FIG. 10 is a schematic partial plan view of the third sub-display area after forming the second flat layer in FIG. 6;
  • Fig. 11 is a partial plan view of the fourth sub-display area of the second display area in Fig. 1;
  • FIG. 12 is a schematic partial plan view of the fourth sub-display area after the electrical connection layer is formed in FIG. 11;
  • FIG. 13 is a schematic partial plan view of a fifth sub-display area of the second display area in FIG. 1;
  • FIG. 14 is a partial plan view of the fifth sub-display area after the electrical connection layer is formed in FIG. 11;
  • FIG. 15 is another partial plan view of the third sub-display area of the second display area in FIG. 1;
  • Figure 16A is a schematic partial cross-sectional view along the P-P' direction in Figure 15;
  • Figure 16B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 15;
  • FIG. 17 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 18 is a schematic partial cross-sectional view along the R-R' direction in Fig. 17;
  • FIG. 19 is a schematic partial top view of a second display area according to at least one embodiment of the present disclosure.
  • FIG. 20 is a schematic top view of a second display region after forming a semiconductor layer according to at least one embodiment of the present disclosure
  • FIG. 21 is a schematic top view of a second display area after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 22 is a schematic top view of a second display area after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 23 is a schematic top view of the second display area after forming the third insulating layer according to at least one embodiment of the present disclosure
  • FIG. 24 is a schematic top view of the second display area after forming the third conductive layer according to at least one embodiment of the present disclosure
  • 25 is a schematic top view of the second display area after forming the fourth insulating layer according to at least one embodiment of the present disclosure
  • FIG. 26 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 27 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 28 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • a transistor refers to an element including at least three terminals of a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • the gate may also be referred to as a control electrode.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • the "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body and its incident light flux.
  • An embodiment of the present disclosure provides a display substrate, including: a first display area and a second display area at least partially surrounding the first display area.
  • the display substrate includes: a base substrate, a pixel circuit and a light emitting element.
  • the pixel circuit is located on the base substrate of the second display area, and the pixel circuit includes first pixel circuits and second pixel circuits arranged alternately.
  • the light-emitting element is located on the side of the pixel circuit away from the base substrate, and the light-emitting element includes a first light-emitting element located in the first display area, a second sub-light-emitting element and a third sub-light-emitting element located in the second display area.
  • the first pixel circuit is electrically connected to the first light-emitting element through at least part of the transparent conductive wire.
  • the second pixel circuit is electrically connected to the second sub-light-emitting element through the first via hole, and the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the third sub-light-emitting element on the base substrate.
  • the third sub-light-emitting element of the second display area is disposed adjacent to the second sub-light-emitting element.
  • this embodiment does not limit it.
  • the second sub-light-emitting element and the third sub-light-emitting element may not be arranged adjacently, and other sub-light-emitting elements are arranged between the second sub-light-emitting element and the third sub-light-emitting element.
  • At least one second pixel circuit in the second display area is electrically connected to the first transfer line through the first via hole, and the first transfer line is electrically connected to the second sub-light-emitting element.
  • the first transfer line is electrically connected to the second sub-light-emitting element.
  • the second pixel circuit is directly electrically connected to the light-emitting element Connection, there will be a short circuit of the light-emitting element.
  • the second pixel circuit and the second sub-light-emitting element are electrically connected through the first transfer line, which can avoid the short-circuit of the second sub-light-emitting element and the third sub-light-emitting element , thereby improving the display effect.
  • a first flat layer is disposed between the first transfer wire and the pixel circuit, and the first transfer wire is electrically connected to the second pixel circuit through a first transfer hole opened in the first flat layer.
  • a second flat layer is provided between the first transfer wire and the light-emitting element, and the first transfer wire is electrically connected to the second sub-light-emitting element through a third transfer hole opened in the second flat layer.
  • connection position between the second pixel circuit and the second sub-light-emitting element is transferred from the position where the first via hole is located to the position where the third via hole is located by using the first transfer wire, so that the second pixel circuit
  • the connection position with the second sub-light-emitting element and the orthographic projection of the third sub-light-emitting element on the base substrate may partially overlap or do not overlap.
  • this embodiment does not limit it.
  • the second display area includes: at least one third sub-display area, the first pixel circuit in the third sub-display area communicates with the first light-emitting element in the first display area through the first transparent conductive line electrical connection.
  • the first transparent conductive line extends at least along the first direction.
  • At least one second pixel circuit in the third sub-display area is electrically connected to the second sub-light-emitting element through the first transfer line extending along the first direction.
  • the second display area may include: at least one fourth sub-display area, the first pixel circuit in the fourth sub-display area communicates with the first light-emitting element in the first display area through the second transparent conductive line electrical connection.
  • the second transparent conductive line extends at least along the second direction.
  • the second direction intersects the first direction.
  • At least one second pixel circuit in the fourth sub-display area is electrically connected to the second sub-light-emitting element through the first transfer line extending along the second direction.
  • more wiring space can be reserved for the second transparent conductive line .
  • the second display area may further include: a fifth sub-display area.
  • the first pixel circuits in the fifth sub-display area are invalid pixel circuits.
  • At least one second pixel circuit in the fifth sub-display area is electrically connected to the second sub-light-emitting element through the first transfer wire extending along any direction.
  • the fifth sub-display area is not arranged with the first transparent conductive line and the second transparent conductive line, therefore, the extension direction of the first transfer line may not be limited by the transparent conductive line.
  • the first display area may include: at least one first sub-display area and at least one second sub-display area.
  • the third sub-display area is adjacent to at least one first sub-display area in the first direction
  • the fourth sub-display area is adjacent to at least one second sub-display area in the second direction.
  • the length ranges of the first transparent conductive line and the second transparent conductive line are approximately the same.
  • the first display area by dividing the first display area into a first sub-display area and a second sub-display area, and making the first light-emitting element of the first sub-display area adjacent to the second display area in the first direction
  • a pixel circuit is electrically connected
  • the first light-emitting element of the second sub-display area is electrically connected with the first pixel circuit in the second display area adjacent to the second direction, which is beneficial to reduce the first transparent conductive line and the second transparent conductive line.
  • the length of the conductive line improves the display effect, and is beneficial to improve the size restriction on the first display area.
  • this implementation when the size of the first display area is constant, compared with the scheme that the first light-emitting element in the first display area is only electrically connected to the first pixel circuit in the second display area adjacent to the first direction, this implementation For example, by setting the first light-emitting element of the first sub-display area to be electrically connected to the first pixel circuit of the second display area adjacent to the first direction, and the first light-emitting element of the second sub-display area to be adjacent to the pixel circuit in the second direction
  • the electrical connection of the first pixel circuit in the second display area can prevent the transparent conductive line electrically connecting the first light-emitting element and the first pixel circuit from being too long, and can expand the arrangement range of the first transparent conductive line and the second transparent conductive line , not limiting the numbers of the first transparent conductive lines and the second transparent conductive lines.
  • the first light-emitting element of the first sub-display area is electrically connected with the first pixel circuit of the second display area adjacent to the first direction
  • the first light-emitting element of the second sub-display area is electrically connected to the first pixel circuit in the second display area adjacent to the second direction, which can increase the size of the first display area.
  • the first display area may include: two first sub-display areas sequentially arranged along the first direction, and two second sub-display areas sequentially arranged along the second direction.
  • the second display area may include: two third sub-display areas arranged along the first direction, and two fourth sub-display areas arranged along the second direction.
  • a third sub-display area is adjacent to a first sub-display area; in the second direction, a fourth sub-display area is adjacent to a second sub-display area.
  • this embodiment does not limit it.
  • the first transfer wire, the first transparent conductive wire and the second transparent conductive wire may have the same layer structure.
  • this embodiment does not limit it.
  • at least two of the first transfer wire, the first transparent conductive wire and the second transparent conductive wire may have a heterogeneous structure.
  • the first transparent conductive line and the second transparent conductive line may be a multi-layer structure.
  • the light emitting element may further include a fourth sub light emitting element located in the second display area. At least one second pixel circuit in the second display area is electrically connected to the fourth sub-light-emitting element through the first transfer hole, and the orthographic projection of the first transfer hole on the base substrate is on the substrate with the light-emitting area of the fourth sub-light-emitting element. The orthographic projection of the base substrate overlaps.
  • the second pixel circuit is electrically connected to the second transfer wire through the first transfer hole, and the second transfer wire is electrically connected to the fourth sub-light-emitting element.
  • the second transfer wire is electrically connected to the fourth sub-light-emitting element.
  • the second pixel circuit is directly electrically connected to the light-emitting element Connection, there may be a situation that causes the light-emitting element to lose the aperture ratio.
  • the second pixel circuit and the fourth sub-light-emitting element are electrically connected through the second transfer line, which can avoid the loss of aperture ratio of the fourth sub-light-emitting element, thereby improving the display. Effect.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2 at least partially surrounding the first display area A1.
  • the second display area A2 surrounds the first display area A1.
  • the first display area A1 is a light-transmitting display area, which can also be called an under-display camera (UDC, Under Display Camera) area; the second display area A2 is a non-light-transmitting display area, which can also be called For the normal display area.
  • the orthographic projection of the photosensitive sensor (eg, hardware such as a camera) on the display substrate may be located in the first display area A1 of the display substrate.
  • the first display area A1 may be circular, and the size of the orthographic projection of the photosensor on the display substrate may be smaller than or equal to the size of the first display area A1 .
  • this embodiment does not limit it.
  • the first display area A1 may be rectangular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be smaller than or equal to the size of the inscribed circle of the first display area A1.
  • the first display area A1 may be located in the middle of the top of the display area AA.
  • the second display area A2 may surround the first display area A1.
  • this embodiment does not limit it.
  • the first display area A1 may be located in other positions such as the upper left corner or the upper right corner of the display area AA.
  • the second display area A2 may surround at least one side of the first display area A1.
  • the display area AA may be a rectangle, such as a rectangle with rounded corners.
  • the first display area A1 may be circular or elliptical. However, this embodiment does not limit it.
  • the first display area A1 may be in other shapes such as a rectangle, a semicircle, or a pentagon.
  • the display area AA is provided with a plurality of sub-pixels.
  • At least one sub-pixel includes a pixel circuit and a light emitting element.
  • the pixel circuit is configured to drive the connected light emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light emitting element to emit light.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. Capacitor) structure, etc.
  • the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit.
  • OLED organic light-emitting diode
  • the color of light emitted by the light emitting element can be determined according to needs.
  • the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the anode of the light emitting element can be electrically connected with the corresponding pixel circuit.
  • this embodiment does not limit it.
  • one pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • the shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, Arranged side by side or square.
  • this embodiment does not limit it.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 3 is a working timing diagram of the pixel circuit provided in FIG. 2 .
  • the pixel circuit of this exemplary embodiment may include: six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL may include an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the pixel circuit is connected to the scan line GL, the data line DL, the first power line PL1 , the second power line PL2 , the emission control line EML, the first initial signal line INIT1 , the second power line
  • the two initial signal lines INIT2, the first reset control line RST1 and the second reset control line RST2 are electrically connected.
  • the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GL is configured to provide a scan signal SCAN to the pixel circuit
  • the data line DL is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a second reset signal RESET2 to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN.
  • the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row.
  • the second reset control signal line RST2 may be input with a second reset control signal RESET2 different from the scan signal SCAN.
  • the first reset control line RST1 may be connected to the scan line GL of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first reset The control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the drive transistor T3 is electrically connected to the light emitting element EL, and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS. Output driving current to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is electrically connected to the scanning line GL
  • the first pole of the data writing transistor T4 is electrically connected to the data line DL
  • the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3 .
  • the threshold compensation transistor T2 is a double-gate transistor, the first gate and the second gate of the threshold compensation transistor T2 are electrically connected to the scanning line GL, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the drive transistor T3, and the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3.
  • the second pole of the transistor T2 is electrically connected with the second pole of the driving transistor T3.
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first pole of the first light emission control transistor T5 is electrically connected to the first power line PL1, and the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML
  • the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3
  • the second pole of the second light emission control transistor T6 is connected to the light emission control line EML.
  • the anode of the element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL, and is configured to reset the gate of the light emitting element EL. Anode resets.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the grid is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the second reset transistor T7 is connected to the light emitting element EL. anode electrical connection.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and The connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T
  • the multiple transistors included in the pixel circuit shown in FIG. 2 are all P-type transistors as an example for description.
  • the working process of the pixel circuit may include: a first stage S1 , a second stage S2 and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal to turn on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off. At this stage, the light emitting element EL does not emit light.
  • the second stage S2 is called a data writing stage or a threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the first electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the drive transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is supplied to the anode of the light-emitting element EL, and the anode of the light-emitting element EL is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization. , to ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage S3 is called the lighting stage.
  • the emission control signal EM provided by the emission control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light emission control signal EM provided by the light emission control signal line EML is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 ;
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line DL
  • VDD is the first voltage signal output from the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 4 is a partial schematic diagram of a display area of a display substrate according to at least one embodiment of the present disclosure.
  • the first display area A1 includes two first sub-display areas A11a and A12a sequentially arranged along the first direction F1, and two first sub-display areas A11a and A12a sequentially arranged along the second direction F2.
  • Two second sub-display areas A12a and A12b are arranged.
  • the first direction F1 intersects the second direction F2, for example, the first direction F1 is perpendicular to the second direction F2.
  • the second display area A2 includes: a third sub-display area A21a adjacent to the first sub-display area A11a in the first direction F1, a third sub-display area A21a adjacent to the first sub-display area A11b in the first direction F1 area A21b, a fourth sub-display area A22a adjacent to the second sub-display area A12a in the second direction F2, a fourth sub-display area A22b adjacent to the second sub-display area A12b in the second direction F2, and The fifth sub-display area A23.
  • the fifth sub-display area A23 is an area in the second display area A2 except for the third sub-display areas A21a and A21b and the fourth sub-display areas A22a and A22b.
  • the third sub-display area A21a faces the first sub-display area A11a in the first direction F1
  • the third sub-display area A21b faces the first sub-display area A11b in the first direction F1
  • the fourth sub-display area A22a The second sub-display area A12a is opposite to the second sub-display area A12a in the second direction F2
  • the fourth sub-display area A22b is directly opposite to the second sub-display area A12b in the second direction F2.
  • the first display area A1 can be divided into four sub-display areas along the center line of the third direction F3 and the center line of the fourth direction F4, that is, two first sub-display areas Areas A11a and A11b and two second sub-display areas A12a and A12b.
  • the third direction F3 intersects both the first direction F1 and the second direction F2, and the fourth direction F4 may be perpendicular to the third direction F3.
  • this embodiment does not limit it.
  • the first display area A1 can be divided into four sub-display areas along the center line of the first direction F1 and the center line of the second direction F2 (for example, two first sub-display areas arranged in sequence along the third direction and one along the second direction F2).
  • two second sub-display areas arranged sequentially in the fourth direction the third sub-display area of the second display area A2 may be adjacent to the first sub-display area in the third direction
  • the fourth sub-display area may be in the fourth It is adjacent to the second sub-display area in the direction.
  • the first display area A1 may be circular, and the two first sub-display areas A11a and A11b and the two second sub-display areas A12a and A12b may be of the same size. sector.
  • the two third sub-display areas A21a and A21b and the two fourth sub-display areas A22a and A22b may both be circular.
  • this embodiment does not limit it.
  • the sizes of the two first sub-display areas and the two second sub-display areas may be different.
  • the first display area may be rectangular, the first sub-display area and the second sub-display area may be rectangular, and the third sub-display area and the fourth sub-display area may be rectangular.
  • the first display area A1 is provided with a plurality of first light emitting elements EL1 .
  • the second display area A2 is provided with a plurality of second light emitting elements and a plurality of pixel circuits.
  • the plurality of pixel circuits of the second display area A2 may include a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12. At least one first pixel circuit 11 in the second display area A2 is electrically connected to at least one first light emitting element EL1 in the first display area A1.
  • the first light-emitting element EL1 in the first display area A1 and the first pixel circuit 11 in the second display area A2 may have a one-to-one or many-to-one relationship, in other words, a first pixel circuit in the second display area A2 11 may be configured to drive one or more first light emitting elements EL1 in the first display area A1 to emit light.
  • At least one second pixel circuit 12 in the second display area A2 is electrically connected to at least one second light emitting element.
  • the plurality of second pixel circuits 12 in the second display area A2 may have a one-to-one correspondence with the plurality of second light-emitting elements.
  • one second pixel circuit 12 in the second display area A2 may be configured to drive one first pixel circuit.
  • the second light emitting element emits light.
  • this embodiment does not limit it.
  • the first light-emitting element EL1 in the first sub-display area A11a of the first display area A1 can communicate with the second display area A2 through the first transparent conductive line L1.
  • the first pixel circuits 11 in the third sub-display area A21a are electrically connected.
  • the first light emitting element EL1 in the first sub-display area A11b of the first display area A1 can be electrically connected to the first pixel circuit 11 in the third sub-display area A21b of the second display area A2 through the first transparent conductive line L1.
  • the first light emitting element EL1 in the second sub-display area A12a of the first display area A1 can be electrically connected to the first pixel circuit 11 in the fourth sub-display area A22a of the second display area A2 through the second transparent conductive line L2.
  • the first light emitting element EL1 in the second sub-display area A12b of the first display area A1 can be electrically connected to the first pixel circuit 11 in the fourth sub-display area A22b of the second display area A2 through the second transparent conductive line L2.
  • the first transparent conductive line L1 and the second transparent conductive line L2 may use transparent conductive materials. In this way, the light transmittance of the first display area A1 can be improved.
  • the first transparent conductive line L1 may generally extend along the first direction F1
  • the second transparent conductive line L2 may generally extend along the second direction F2.
  • the first transparent conductive line L1 can be a single-layer wiring or a multi-layer wiring (that is, the wiring of different film layers is formed in series or in parallel)
  • the second transparent conductive line L2 can be a single-layer wiring or Multiple layers of routing.
  • first transparent conductive line and the second transparent conductive line electrically connected to the first light-emitting elements of the same color may be in the same layer structure, and the first transparent conductive lines electrically connected to the first light-emitting elements of different colors may be located in different film layers, The second transparent conductive lines electrically connecting the second light-emitting elements of different colors may be located in different film layers.
  • this embodiment does not limit it.
  • the first The first light-emitting element EL1 close to the third sub-display area A21a in the sub-display area A11a is electrically connected to the first pixel circuit 11 in the third sub-display area A21a far away from the first sub-display area A11a;
  • the first light emitting element EL1 away from the third sub-display area A21a is electrically connected to the first pixel circuit 11 in the third sub-display area A21a close to the first sub-display area A11a.
  • the lengths of the multiple first transparent conductive lines L1 connecting different first light emitting elements EL1 and the first pixel circuits 11 may be approximately the same.
  • the lengths of the plurality of second transparent conductive lines L2 connecting different first light emitting elements EL1 and the first pixel circuits 11 may be approximately the same.
  • the length ranges of the first transparent conductive line L1 and the second transparent conductive line L2 may be approximately the same. In this way, the maximum length of the transparent conductive lines can be reduced as a whole, and the difference in the trace lengths of the transparent conductive lines can be reduced, so that the display picture shows better uniformity.
  • the first light-emitting elements in the first display area to be electrically connected to the first pixel circuits arranged in two different directions (namely, the first direction F1 and the second direction F2), it is beneficial to reduce the The maximum routing length of the first transparent conductive line and the second transparent conductive line can also improve the size restriction on the first display area and help to increase the size of the first display area.
  • the first pixel circuits 11 and the second pixel circuits in the second display area may be alternately arranged along the first direction F1 and the second direction F2.
  • a plurality of pixel circuits sequentially arranged along the first direction F1 may be referred to as a row of pixel circuits
  • a plurality of pixel circuits sequentially arranged along the second direction F2 may be referred to as a column of pixel circuits.
  • At least one first pixel circuit 11 is disposed between the plurality of second pixel circuits 12 arranged along the first direction F1, and the plurality of second pixel circuits 12 arranged along the second direction F2 At least one first pixel circuit 11 is arranged between the second pixel circuits 12 .
  • the first pixel circuits 11 may be arranged between rows and columns of the second pixel circuits 12 . For example, in the first direction F1, four columns of second pixel circuits 12 are alternately arranged with one column of first pixel circuits 11, and in the second direction F2, four rows of second pixel circuits 12 are alternately arranged with one row of first pixel circuits 11. cloth.
  • a row of first pixel circuits 11 is arranged between every four rows of second pixel circuits 12
  • a column of first pixel circuits 11 is arranged between every four rows of second pixel circuits 12 .
  • the arrangement space of a new column of the first pixel circuits 11 can be added, and the original By compressing every four rows of the second pixel circuits along the second direction F2, the arrangement space for one row of the first pixel circuits 11 can be added.
  • a plurality of pixel circuits arranged in a 5*5 array for example, including a 4*4 array Arranged compressed second pixel circuits and newly added row and column of first pixel circuits
  • the pixel circuits arranged in a 4*4 array before compression and the pixel circuits arranged in a 5*5 array after compression The space occupied is the same.
  • this embodiment does not limit it.
  • the second pixel circuits and the first pixel circuits may be arranged according to the same rule in the second display area A2.
  • the first pixel circuits in the third sub-display area and the fourth sub-display area of the second display area A2 are electrically connected to the first light-emitting elements in the first display area, and the first pixel circuits in the fifth sub-display area A23 have no It is electrically connected with the first light emitting element in the first display area.
  • the first pixel circuit in the fifth sub-display area A23 can serve as a dummy pixel circuit.
  • this embodiment does not limit it.
  • the first pixel circuit may be added by compressing the second pixel circuit only in the third sub-display area and the fourth sub-display area, and the first pixel circuit may not be added in the fifth sub-display area.
  • FIG. 5 is a schematic diagram of the arrangement of the second light emitting elements in the second display area according to at least one embodiment of the present disclosure.
  • the plurality of second light-emitting elements in the second display area A2 may include: a plurality of green second light-emitting elements 221 and 224, a plurality of red second light-emitting elements 222, and A plurality of blue second light emitting elements 223 .
  • At least one pixel unit of the second display area A2 may include: a blue second light emitting element 223 , two green second light emitting elements 221 and 224 , and a red second light emitting element 222 .
  • the green second light emitting elements 221 and 224 are arranged sequentially in the second direction F2, and the red second light emitting elements 222 and blue second light emitting elements 223 are arranged sequentially in the first direction F1.
  • the second light-emitting elements of the same color in adjacent rows are dislocated in the first direction F1.
  • the plurality of first light-emitting elements in the first display area A1 may include: a plurality of first green light-emitting elements, a plurality of first red light-emitting elements, and a plurality of first blue light-emitting elements.
  • the arrangement of the plurality of first light-emitting elements in the first display area A1 may be consistent with the arrangement of the plurality of second light-emitting elements in the second display area A2, so details will not be repeated here.
  • At least one light emitting element of the display area AA may include: an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • the orthographic projection of the anodes of the green second light-emitting elements 221 and 224 on the base substrate of the second display area A2 can be a pentagon, and the red second light-emitting element 222 and the blue third light-emitting element 223
  • the orthographic projection of the anode on the base substrate can be a hexagon.
  • the anode area of the first light emitting element in the first display area A1 may be smaller than the anode area of the second light emitting element emitting light of the same color in the second display area A2.
  • the orthographic projection of the anode of the green first light-emitting element in the first display area on the substrate can be a circle
  • the orthographic projections of the anodes of the red first light-emitting element and the blue first light-emitting element on the substrate can be an ellipse shape.
  • the above-mentioned ellipse may be a combined shape of a square and two semicircles, wherein the two semicircles are connected to opposite ends of the square.
  • FIG. 6 is a partial plan view of a third sub-display area of the second display area in FIG. 1 .
  • Fig. 7A is a schematic partial cross-sectional view along the P-P' direction in Fig. 6 .
  • Fig. 7B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 6 .
  • FIG. 8 is a partial plan view of the third sub-display region after the formation of the first flat layer in FIG. 6 .
  • FIG. 9 is a partial plan view of the third sub-display area after the electrical connection layer is formed in FIG. 6 .
  • FIG. 10 is a schematic partial plan view of the third sub-display region after the formation of the second flat layer in FIG. 6 .
  • FIG. 10 is a schematic partial plan view of the third sub-display region after the formation of the second flat layer in FIG. 6 .
  • FIG. 11 is a partial plan view of a fourth sub-display area of the second display area in FIG. 1 .
  • FIG. 12 is a partial plan view of the fourth sub-display region after the electrical connection layer is formed in FIG. 11 .
  • FIG. 13 is a partial plan view of the fifth sub-display area of the second display area in FIG. 1 .
  • FIG. 14 is a partial plan view of the fifth sub-display region after the electrical connection layer is formed in FIG. 11 .
  • the number of rows of pixel circuits in the second display area A2 is greater than that of the second pixel circuit.
  • the number of rows and columns of the light-emitting element is greater than that of the second light-emitting element, resulting in misalignment between the second pixel circuit and the electrically connected second light-emitting element, and the second pixel circuit is directly electrically connected to the second light-emitting element.
  • the anode of the element will cause a short circuit between adjacent second light-emitting elements and cause loss of aperture ratio.
  • the second display area A2 may include: a base substrate 30 , and pixel circuits sequentially arranged on the base substrate 30 layer 40, a first planar layer 41, an electrical connection layer, a second planar layer 42 and a light emitting structure layer.
  • the pixel circuit layer 40 may include: a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 .
  • the electrical connection layer may include: a plurality of connection electrodes (for example, connection electrodes 431b), a plurality of transition lines (for example, including first transition lines and second transition lines), a plurality of first transparent conductive lines and a plurality of second transparent conductive lines Wire.
  • the light emitting structure layer may include: an anode layer (for example, an anode including a plurality of second light emitting elements), a pixel definition layer 54 , an organic light emitting layer (for example, organic light emitting layers 52 a and 52 b ), and a cathode layer 53 .
  • the organic light-emitting layer of at least one second light-emitting element is interposed between the anode and the cathode.
  • the cathodes of the plurality of second light-emitting elements may be of an integral structure.
  • the plurality of second light emitting elements of the second display area A2 may include second sub light emitting elements and third sub light emitting elements.
  • the second sub-light-emitting element is electrically connected to the second pixel circuit through the first via hole, and the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the third sub-light-emitting element on the base substrate.
  • the second sub-light-emitting element and the third sub-light-emitting element may be arranged adjacent to each other.
  • this embodiment does not limit it.
  • the second sub-light-emitting element and the third sub-light-emitting element may not be disposed adjacently.
  • the plurality of second light-emitting elements in the second display area A2 may further include: fourth sub-light-emitting elements.
  • the fourth sub-light-emitting element is electrically connected to the second pixel circuit through the first via hole, and there is an intersection between the orthographic projection of the first via hole on the substrate and the orthographic projection of the light-emitting region of the fourth sub-light-emitting element on the substrate. stack.
  • the structure of the third sub-display area will be described by taking the green second light emitting elements 231 to 233 , the red second light emitting element 234 , and the blue second light emitting element 235 in FIG. 6 as examples.
  • the second sub-light-emitting element takes the second green light-emitting element 233 as an example
  • the third sub-light-emitting element takes the second blue light-emitting element 235 as an example
  • the fourth sub-light-emitting element takes the second green light-emitting element 232 as an example for illustration.
  • a plurality of first via holes K11 and a plurality of second via holes K12 are opened on the first planar layer 41 covering the pixel circuit layer.
  • the first flat layer 41 in the first transfer hole K11 and the second transfer hole K12 is removed, the second transfer hole K12 can expose the anode connection end of the first pixel circuit 11, and the first transfer hole K11 can expose out of the anode connection terminal of the second pixel circuit 12.
  • the first transfer holes K11 and the second transfer holes K12 in the same row are arranged in sequence along the first direction F1, and the first transfer holes K11 and the second transfer holes K12 in the same row are arranged along the second direction F2 Arranged in sequence.
  • this embodiment does not limit it.
  • the electrical connection layer of the third sub-display area of the second display area A2 may include: a plurality of connection electrodes (for example, connection electrodes 431a to 431c), and A plurality of patch cords (for example, the second patch cord 432a and the first patch cord 432b).
  • connection electrodes for example, connection electrodes 431a to 431c
  • a plurality of patch cords for example, the second patch cord 432a and the first patch cord 432b.
  • Each connection electrode can be electrically connected to the anode connection end of a second pixel circuit 12 through a first transfer hole K11, and each transfer line can be connected to the anode of a second pixel circuit 12 through a first transfer hole K11 electrical connection.
  • the first transition line and the second transition line in the third sub-display area may both extend along the first direction F1.
  • the first transparent conductive line electrically connected to the anode connection terminal of the first pixel circuit 11 through the second via hole K12 is omitted.
  • the first transparent conductive line may extend to the first display area A1 approximately along the first direction F1 to realize the electrical connection between the first pixel circuit 11 and the first light emitting element.
  • the connection position between the anode of the second light-emitting element and the second pixel circuit can be changed, thereby giving the first transparent conductive
  • the arrangement of the lines leaves more space gaps.
  • a plurality of third via holes K13 are opened on the second planar layer 42 covering the electrical connection layer.
  • the second flat layer 42 in the third via hole K13 is removed, exposing the surface of the electrical connection layer.
  • the anode 232a of the green second light-emitting element 232 is electrically connected to the second transition line 432a through a third transition hole K13, and the second transition line 432a is electrically connected to the second transition line 432a through a
  • the first via hole K11 is electrically connected to the corresponding anode connection end of the second pixel circuit 12 .
  • the orthographic projection of the light-emitting region 232b of the green second light-emitting element 232 on the base substrate 30 overlaps with the orthographic projection of the first transfer hole K11 on the base substrate 30, if the anode 232a of the green second light-emitting element 232 passes through
  • the first transfer hole K11 is directly electrically connected to the anode connection end of the second pixel circuit 12, which will affect the flatness of the film layer of the light emitting region 232b of the green second light emitting element 232, thus causing the green second light emitting element 232 to lose its opening.
  • the rate affects the display effect.
  • the orthographic projection of the connection position between the second transfer line 432a and the anode connection end of the second pixel circuit 12 (that is, the first transfer hole K11 ) on the base substrate 30 is in the same position as the light emitting region 232b of the second light emitting element 232 .
  • the orthographic projection of the base substrate 30 overlaps, and the orthographic projection of the second transfer line 432a and the second light emitting element 232 (that is, the third transfer hole K13) on the base substrate 30 overlaps with the light emission of the second light emitting element 232
  • the orthographic projections of the regions 232b on the base substrate 30 do not overlap.
  • the orthographic projections of the first via hole K11 and the third via hole K13 to which the second via line 432 a is connected do not overlap on the base substrate 30 .
  • the connection position of the anode 232a of the green second light-emitting element 232 is transferred to an area outside the light-emitting area 232b (that is, the green second light-emitting element 232 through the second transfer line 432a extending along the first direction F1).
  • the third transfer hole K13 electrically connected to the anode 232a in the orthographic projection of the light emitting region 232b on the base substrate 30 does not overlap in the orthographic projection of the base substrate 30), and the film layer planarization process is performed through the second flat layer 42, The film layer flatness of the light emitting region 232b can be ensured to ensure the aperture ratio and display effect of the green second light emitting element 232 .
  • the anode 233a of the green second light-emitting element 233 can be electrically connected to the first transfer wire 432b through a third transfer hole K13, and the first transfer wire 432b can be It is electrically connected to the anode connection end of the corresponding second pixel circuit 12 through a first transfer hole K11 .
  • the anode 233a of the second light-emitting element 233 is directly electrically connected to the anode connection end of the second pixel circuit 12 through the first transfer hole K11, and there will be an anode 233a of the second green light-emitting element 233 and an anode of the second blue light-emitting element 235. If the anode 235a is short-circuited, it is easy to cause display failure.
  • connection position of the anode 233a of the green second light emitting element 233 is moved to an area other than the anode 235a of the blue second light emitting element 235 through the first transfer line 432b extending along the first direction F1 (for example, The connection position is moved to a side close to the red second light emitting element 234 ), so that the anode 233 a of the green second light emitting element 233 is electrically connected to the second pixel circuit 12 .
  • the orthographic projection of the connection position between the first transfer line 432b and the anode connection end of the second pixel circuit 12 (that is, the first transfer hole K11 ) on the base substrate 30 is in line with the anode 235a of the second light emitting element 235 .
  • the orthographic projection of the base substrate 30 overlaps, and the orthographic projection of the connection position between the first transfer line 432b and the second light emitting element 233 (that is, the third transfer hole K13) on the base substrate 30 and the anode 235a of the second light emitting element 235 There is no overlap in the orthographic projections of the base substrate 30 .
  • the orthographic projections of the first via hole K11 and the third via hole K13 connected to the first via line 432b on the base substrate 30 do not overlap.
  • the orthographic projection of the anode 235a of the blue second light-emitting element 235 on the base substrate 30 does not overlap with the orthographic projection of the anode 233a of the green second light-emitting element 233 on the base substrate 30, so that adjacent In the event of a short circuit of the second light-emitting element, the display effect can be ensured.
  • the anode 231a of the green second light emitting element 231 can be electrically connected to a corresponding second pixel circuit 12 through a first transfer hole K11 through a connection electrode 431a
  • the anode 234a of the red second light emitting element 234 can be electrically connected to a corresponding second pixel circuit 12 through the connecting electrode 431b via a first transfer hole K11
  • the anode 235a of the blue second light emitting element 235 can be electrically connected through the connecting electrode 431c It is electrically connected to a corresponding second pixel circuit 12 via a first transfer hole K11.
  • the light emitting area may refer to the opening area of the anode exposed by the pixel definition layer, that is, the overlapping area of the anode, the organic light emitting layer and the cathode of the light emitting element.
  • the dislocated second pixel circuit and the second sub-light-emitting element in the third sub-display region, can be electrically connected through the first transfer line, and the first transfer line extends along the first direction, which can The electrical connection between the anode of the second sub-light-emitting element and the corresponding second pixel circuit is realized, and the risk of short circuit between the second sub-light-emitting element and the third sub-light-emitting element is avoided.
  • the dislocated second pixel circuit and the fourth sub-light-emitting element can be electrically connected through the second transfer line, and the second transfer line extends along the first direction, which can improve the loss of aperture ratio of the second sub-light-emitting element.
  • both the first transfer wire and the second transfer wire are arranged to extend along the first direction, it is possible to provide an arrangement space for the first transparent conductive wire electrically connecting the first pixel circuit and the first light-emitting element, avoiding interference with the first transparent conductive wire.
  • the arrangement of the lines has an effect.
  • the structure of the fourth sub-display area will be described by taking the green second light emitting elements 241 to 243 , the red second light emitting element 244 , and the blue second light emitting element 245 in FIG. 11 as examples.
  • the second sub-light-emitting element takes the second green light-emitting element 243 as an example
  • the third sub-light-emitting element takes the second blue light-emitting element 245 as an example
  • the fourth sub-light-emitting element takes the second green light-emitting element 242 as an example for illustration.
  • the electrical connection layer of the fourth sub-display area of the second display area A2 may include: a plurality of connection electrodes (for example, connection electrodes 431a to 433c), and A plurality of patch lines (eg, the second patch line 434a and the first patch line 434b).
  • connection electrodes for example, connection electrodes 431a to 433c
  • a plurality of patch lines eg, the second patch line 434a and the first patch line 434b.
  • Each connection electrode can be electrically connected to an anode connection end of a second pixel circuit 12 through a first via hole K11 .
  • Each transfer line can be electrically connected to an anode connection end of a second pixel circuit 12 through a first transfer hole K11 .
  • the first transition line and the second transition line in the fourth sub-display area may both extend along the second direction F2.
  • the second transparent conductive lines electrically connected to the second via holes are omitted.
  • the second transparent conductive line may extend to the first display area substantially along the second direction F2, so as to realize the electrical connection between the first pixel circuit and the first light emitting element.
  • the connection position between the anode of the second light-emitting element and the second pixel circuit can be changed, thereby giving the second transparent conductive
  • the arrangement of the lines leaves more space gaps.
  • the anode 242a of the green second light-emitting element 242 is electrically connected to the second transition line 434a through a third transition hole, and the second transition line 434a is electrically connected to the second transition line 434a through a first transition hole.
  • a via hole K11 is electrically connected to the corresponding anode terminal of the second pixel circuit 12 .
  • the orthographic projection of the light-emitting region 242b of the green second light-emitting element 242 on the base substrate 30 overlaps with the orthographic projection of the first transfer hole K11 on the base substrate 30, if the anode 242a of the green second light-emitting element 242 passes through
  • the first transfer hole K11 is directly electrically connected to the anode connection end of the second pixel circuit 12, which will affect the flatness of the film layer of the light emitting region 242b of the green second light emitting element 242, thus causing the green second light emitting element 242 to lose its opening.
  • the rate affects the display effect.
  • connection position of the anode 242a of the green second light-emitting element 242 is transferred to an area outside the light-emitting area 242b (that is, the green second light-emitting element 242 through the second transfer line 434a extending along the second direction F2).
  • the third transfer hole K13 electrically connected to the anode 242a in the orthographic projection of the base substrate 30 of the light emitting region 242b does not overlap in the orthographic projection of the base substrate 30), and the film layer planarization process is performed through the second flat layer 42,
  • the film layer flatness of the light emitting region 242b can be ensured to ensure the aperture ratio and display effect of the green second light emitting element 242 .
  • the anode 243a of the green second light-emitting element 243 can be electrically connected to the first transfer wire 434b through a third transfer hole K13, and the first transfer wire 434b can be It is electrically connected to the anode connection end of the corresponding second pixel circuit 12 through a first transfer hole K11 .
  • the anode 243a of the second light-emitting element 243 is directly electrically connected to the second pixel circuit 12 through the first transfer hole K11, and there may be a short circuit between the anode 243a of the second green light-emitting element 243 and the anode 245a of the second blue light-emitting element 245. In this case, it is easy to cause poor display.
  • connection position of the anode 243a of the green second light emitting element 243 is moved to an area other than the anode 245a of the blue second light emitting element 245 through the first transfer line 434b extending along the second direction F2 (for example, The connection position is moved to a side close to the red second light emitting element 244 ), so that the anode 243 a of the green second light emitting element 243 is electrically connected to the second pixel circuit 12 .
  • the orthographic projection of the anode 245a of the blue second light-emitting element 245 on the base substrate 30 does not overlap with the orthographic projection of the anode 243a of the green second light-emitting element 243 on the base substrate 30, so that adjacent In the event of a short circuit of the second light-emitting element, the display effect can be ensured.
  • the anode 241a of the green second light-emitting element 241 can be electrically connected to a corresponding second pixel circuit 12 through a first transfer hole K11 through a connection electrode 433a
  • the anode 244a of the red second light-emitting element 244 can be electrically connected to a corresponding second pixel circuit 12 through the connection electrode 433b via a first transfer hole K11
  • the anode 245a of the blue second light-emitting element 245 can be electrically connected to the corresponding second pixel circuit 12 through the connection electrode 433c. It is electrically connected to a corresponding second pixel circuit 12 via a first transfer hole K11.
  • the dislocated second pixel circuit and the second sub-light-emitting element in the fourth sub-display region, can be electrically connected through the first transfer line, and the first transfer line extends along the second direction, which can The electrical connection between the anode of the second sub-light-emitting element and the corresponding second pixel circuit is realized, and the risk of short circuit between the second sub-light-emitting element and the third sub-light-emitting element is avoided.
  • the dislocated second pixel circuit and the fourth sub-light-emitting element can be electrically connected through the second transfer line, and the second transfer line extends along the second direction, which can improve the loss of aperture ratio of the fourth sub-light-emitting element.
  • both the first transfer wire and the second transfer wire are arranged to extend along the second direction, it is possible to provide an arrangement space for the second transparent conductive wire electrically connecting the first pixel circuit and the first light-emitting element, so as to avoid interference with the second transparent conductive wire.
  • the arrangement of the lines has an effect.
  • the structure of the fifth sub-display area will be described by taking the green second light emitting elements 251 to 253 , the red second light emitting element 254 , and the blue second light emitting element 255 in FIG. 13 as examples.
  • the second sub-light-emitting element takes the second green light-emitting element 253 as an example
  • the third sub-light-emitting element takes the second blue light-emitting element 255 as an example
  • the fourth sub-light-emitting element takes the second green light-emitting element 252 as an example for illustration.
  • the electrical connection layer of the fifth sub-display area A23 of the second display area A2 may include: a plurality of connection electrodes (for example, connection electrodes 435a to 435c), And a plurality of third patch cords (for example, the second patch cord 436a and the first patch cord 436b).
  • connection electrode can be electrically connected to an anode connection end of a second pixel circuit 12 through a first via hole K11 .
  • Each transfer line can be electrically connected to an anode connection end of a second pixel circuit 12 through a first transfer hole K11 .
  • the extension direction of the first transition line and the second transition line in the fifth sub-display area A23 is not limited, for example, it can be along the first direction F1, the second direction F2, extending in the third direction F3 or in the fourth direction F4.
  • the anode 252a of the green second light-emitting element 252 is electrically connected to the second transfer wire 436a through a third transfer hole, and the second transfer wire 436a is electrically connected to the second transfer wire 436a through a first transfer hole.
  • a via hole K11 is electrically connected to the corresponding anode terminal of the second pixel circuit 12 .
  • the connection position of the anode 252a of the green second light-emitting element 252 is transferred to an area outside the light-emitting area 252b (that is, the green second light-emitting element 252 ) through the second transfer line 436a extending along the second direction F2.
  • the third transfer hole K13 electrically connected to the anode 252a in the orthographic projection of the light emitting region 252b on the base substrate 30 does not overlap in the orthographic projection of the base substrate 30), and the film layer planarization process is performed through the second flat layer 42,
  • the film layer flatness of the light emitting region 252b can be ensured to ensure the aperture ratio and display effect of the green second light emitting element 252 .
  • the anode 253a of the green second light-emitting element 253 can be electrically connected to the first transfer wire 436b through a third transfer hole K13, and the first transfer wire 436b can be It is electrically connected to the anode connection end of the corresponding second pixel circuit 12 through a first transfer hole K11 .
  • connection position of the anode 253a of the green second light emitting element 253 is moved to an area other than the anode 255a of the blue second light emitting element 255 through the first transfer line 436b extending along the fourth direction F4 (for example, The connection position is moved to a side close to the red second light emitting element 254 ), so that the anode 253 a of the green second light emitting element 253 is electrically connected to the second pixel circuit 12 .
  • the orthographic projection of the anode 255a of the blue second light-emitting element 255 on the base substrate 30 does not overlap with the orthographic projection of the anode 253a of the green second light-emitting element 253 on the base substrate 30, so that adjacent In the event of a short circuit of the second light-emitting element, the display effect can be ensured.
  • the anode 251a of the green second light-emitting element 251 can be electrically connected to a corresponding second pixel circuit 12 through a first transfer hole K11 through a connection electrode 435a
  • the anode 254a of the red second light emitting element 254 can be electrically connected to a corresponding second pixel circuit 12 through the connecting electrode 435b via a first transfer hole K11
  • the anode 255a of the blue second light emitting element 255 can be electrically connected through the connecting electrode 435c It is electrically connected to a corresponding second pixel circuit 12 via a first transfer hole K11.
  • at least one transfer line of the fifth sub-display area may extend along the third direction F3, or may first extend along the second direction F2 and then extend along the fourth direction F4. However, this embodiment does not limit it.
  • the first direction F1 intersects the second direction F2 horizontally and vertically vertically
  • the third direction F3 is located between the first direction F1 and the second direction F2
  • the third direction F3 intersects vertically with the second direction F2.
  • the included angle along the clockwise direction between the three directions F3 and the first direction F1 is about 45 degrees.
  • the clockwise angle between the third direction F3 and the first direction F1 may be about 30 degrees to 60 degrees.
  • the dislocated second pixel circuit and the second sub-light-emitting element can be electrically connected through the first transfer line, and the dislocated second pixel circuit and the fourth sub-light emitting element
  • the elements can be electrically connected through the second transfer wire, and the extension direction of the first transfer wire and the second transfer wire is not limited, so that the electrical connection between the anode of the second light-emitting element and the corresponding second pixel circuit can be realized, and the fourth pixel circuit can be improved.
  • FIG. 15 is another partial plan view of the third sub-display area of the second display area in FIG. 1 .
  • Fig. 16A is a schematic partial cross-sectional view along the P-P' direction in Fig. 15 .
  • Fig. 16B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 15 .
  • the electrical connection layer of the second display area A2 may include: a plurality of transition lines (for example, including a first transition line 432b, a second transition line 432a), A plurality of first transparent conductive lines and a plurality of second transparent conductive lines.
  • the anode 234a of the red second light emitting element 234 is directly electrically connected to the anode connection end of a second pixel circuit 12 through the transfer hole opened in the first flat layer 41 and the second flat layer 42. connection without transition via connecting electrodes.
  • the pixel circuit may include a plurality of transistors and at least one storage capacitor.
  • a transistor may include an active layer, a gate, a first electrode and a second electrode.
  • the storage capacitor may include a first capacitor plate and a second capacitor plate.
  • the gate of the transistor and one of the capacitive plates of the storage capacitor may have the same layer structure, and the first electrode and the second electrode of the transistor may have the same layer structure.
  • the structure of the pixel circuit layer will be illustrated below by taking the pixel circuit in the second display area as an example with the 7T1C structure shown in FIG. 2 .
  • the first transistor is the aforementioned threshold compensation transistor T2.
  • FIG. 17 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 18 is a schematic partial cross-sectional view along the R-R' direction in Fig. 17 .
  • Fig. 19 is a schematic partial top view of the second display area of at least one embodiment of the present disclosure.
  • FIG. 20 is a schematic top view of a second display region after forming a semiconductor layer according to at least one embodiment of the present disclosure.
  • FIG. 21 is a schematic top view of the second display region after forming the first conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 22 is a schematic top view of the second display region after forming the second conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 23 is a schematic top view of the second display region after forming the third insulating layer according to at least one embodiment of the present disclosure.
  • FIG. 24 is a schematic top view of the second display region after forming the third conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 25 is a schematic top view of the second display region after forming the fourth insulating layer according to at least one embodiment of the present disclosure. The planar structures of four pixel circuits are illustrated in FIGS. 19 to 25 .
  • the pixel circuit layer of the second display area A2 may include: a semiconductor layer disposed on the base substrate 30 , a second A conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer.
  • a first insulating layer 31 is arranged between the semiconductor layer and the first conductive layer
  • a second insulating layer 32 is arranged between the first conductive layer and the second conductive layer
  • a third insulating layer is arranged between the second conductive layer and the third conductive layer 33.
  • a fourth insulating layer 34 is disposed between the third conductive layer and the fourth conductive layer.
  • the first insulating layer 31 to the fourth insulating layer 34 may all be inorganic insulating layers.
  • the first conductive layer can also be called the first gate metal layer
  • the second conductive layer can also be called the second gate metal layer
  • the third conductive layer can also be called the first source-drain metal layer
  • the fourth conductive layer can also be called is the second source-drain metal layer.
  • this embodiment does not limit it.
  • the semiconductor layer of the second display area A2 at least includes: active layers of a plurality of transistors of the pixel circuit.
  • the first conductive layer at least includes: gates of a plurality of transistors of the pixel circuit, a first capacitive plate of a storage capacitor, a scanning line, a light emission control line, and a first reset control line.
  • the second conductive layer at least includes: a second capacitive plate of a storage capacitor of the pixel circuit, a first initial signal line, and a second initial signal line.
  • the third conductive layer at least includes: a first pole and a second pole of at least one transistor of the pixel circuit.
  • the fourth conductive layer at least includes: data lines and first power lines.
  • the manufacturing process of the display substrate will be illustrated below with reference to FIGS. 17 to 25 and FIGS. 6 to 14 .
  • the "patterning process" mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • Thin film refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • the manufacturing process of the display substrate may include the following operations.
  • forming the semiconductor layer may include: depositing a semiconductor thin film on the base substrate 30 , patterning the semiconductor thin film through a patterning process, and forming the semiconductor layer in the second display area.
  • the semiconductor layer of the second display area A1 at least includes: active layers of multiple transistors of the pixel circuit, for example, the active layer T10 of the first reset transistor T1, the active layer T20 of the threshold compensation transistor T2 , the active layer T30 of the drive transistor T3, the active layer T40 of the data writing transistor T4, the active layer T50 of the first light emission control transistor T5, the active layer T60 of the second light emission control transistor T6, and the second reset transistor T7
  • the active layer T70 may be an integral structure connected to each other.
  • the material of the semiconductor layer may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • a plurality of doped regions may be on both sides of the channel region, and be doped with impurities and thus have conductivity. Impurities can vary depending on the type of transistor.
  • a doped region of an active layer may be interpreted as a source or drain electrode of a transistor.
  • the portion of the active layer between the transistors can be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors.
  • the base substrate 30 may be a rigid substrate, such as a glass substrate.
  • the base substrate may be a flexible substrate.
  • a first insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned by a patterning process to form a second layer covering the semiconductor layer.
  • the first conductive layer of the second display area A2 includes at least: the gates of multiple transistors of the pixel circuit (for example, the gate T13 of the first reset transistor T1, the first gate of the threshold compensation transistor T2 T23a and the second gate T23b, the gate T33 of the drive transistor T3, the gate T43 of the data writing transistor T4, the gate T53 of the first light emission control transistor T5, the gate T63 of the second light emission control transistor T6, and the second Gate T73 of the reset transistor T7), the first capacitor plate C1-1 of the storage capacitor Cst of the pixel circuit, a plurality of scanning lines (for example, scanning lines GL(i-1) and GL(i)), a plurality of light emitting control lines (eg, light emission control lines EML(i-1) and EML(i)), and a plurality of first reset control lines (eg, first reset control lines RST1(i-1) and RST1(i)).
  • i is an integer.
  • the first capacitive plate C1-1 of the storage capacitor Cst of the i-th row of pixel circuits and the gate T33 of the driving transistor T3 may have an integrated structure.
  • the gate T73 of the second reset transistor T7 of the i-th row of pixel circuits, the first reset control line RST1(i), and the gate of the first reset transistor T1' of the i+1-th row of pixel circuits may have an integral structure.
  • the gate T13 of the first reset transistor T1 of the i-th row of pixel circuits, the gate of the second reset transistor of the i-1th row of pixel circuits, and the first reset control line RST1(i-1) may have an integral structure.
  • the first gate T23a and the second gate T23b of the threshold compensation transistor T2 of the pixel circuit in the i-th row, the gate T43 of the data writing transistor T4de and the scan line GL(i) may be of an integral structure.
  • the gate T53 of the first light emission control transistor T5, the gate T63 of the second light emission control transistor T6, and the light emission control line EML(i) of the i-th row of pixel circuits may have an integral structure. However, this embodiment does not limit it.
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate 30 forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a layer covering the first conductive layer.
  • the second insulating layer 32 , and the second conductive layer disposed on the second insulating layer 32 As shown in FIG.
  • the second conductive layer of the second display area A2 includes at least: the second capacitor plate C1-2 of the storage capacitor Cst of the pixel circuit, a plurality of first initial signal lines (for example, the first initial signal line INIT1(i ⁇ 1), INIT1(i) and INIT1(i+1)) and a plurality of second initial signal lines (eg, second initial signal lines INIT2(i ⁇ 1) and INIT2(i)).
  • first initial signal lines for example, the first initial signal line INIT1(i ⁇ 1), INIT1(i) and INIT1(i+1)
  • second initial signal lines eg, second initial signal lines INIT2(i ⁇ 1) and INIT2(i)
  • both the plurality of first initial signal lines and the plurality of second initial signal lines extend along the first direction F1.
  • the orthographic projection of the first initial signal line INIT1(i) on the base substrate 30 is located between the scan line GL(i) and the orthographic projection of the first reset control line RST1(i-1) on the base substrate 30.
  • the orthographic projection of the second initial signal line INIT2(i) on the substrate 30 is located between the emission control line EML(i) and the orthographic projection of the first reset control line RST1(i) on the substrate 30 .
  • the first initial signal line INIT1(i) includes a body portion 61 and an extension portion 62 .
  • the main body portion 61 extends along the first direction F1
  • the extension portion 62 extends from the main body portion 61 along the second direction F2.
  • the protruding portion 62 of the first initial signal line INIT1(i) extends toward a side close to the scan line GL(i) along the second direction F2.
  • the active layer T20 of the threshold compensation transistor T2 (ie, the first transistor) may include a first channel region, a second channel region and a third channel region. The third channel region is connected between the first channel region and the second channel region.
  • the first channel region extends along the second direction F2, the second channel region extends along the first direction F1, the third channel region is a corner connecting the first channel region and the second channel region, and the third channel region
  • the orthographic projection on the base substrate 30 may be an inverted L shape.
  • the orthographic projection of the first gate T23a of the threshold compensation transistor T2 on the substrate 30 can cover the orthographic projection of the first channel region on the substrate 30, and the orthographic projection of the second gate T23b on the substrate 30 can cover the first channel region on the substrate 30.
  • the orthographic projection of the second channel region on the base substrate 30 .
  • the first channel region and the second channel region are overlapping regions of the active layer and the gate; the third channel region does not overlap the gate, but serves as the first channel region and the second channel region.
  • the orthographic projection of the protruding portion 62 of the first initial signal line INIT1(i) on the substrate 30 overlaps with the orthographic projection of the third channel region of the threshold compensation transistor T2 on the substrate 30 . That is, the protruding portion 62 of the first initial signal line INIT1(i) may block the third channel region of the active layer of the threshold compensation transistor T2.
  • the first initial signal line can provide a fixed voltage signal, effective shielding of the active layer of the threshold compensation transistor T2 can be achieved to ensure the stability of the threshold compensation transistor T2.
  • Using the first initial signal line to shield the active layer of the threshold compensation transistor can save space, and can meet the pixel design requirements of high resolution and high image quality, thereby improving the performance of the display substrate.
  • a third insulating film is deposited on the base substrate 30 formed with the foregoing pattern, and the third insulating film is patterned by a patterning process to form the third insulating layer 33 .
  • the third insulating layer 33 of the second display area A2 is provided with a plurality of via holes, and the plurality of via holes may at least include: a first via hole H1 to a ninth via hole H9 .
  • the third insulating layer 33 , the second insulating layer 32 and the first insulating layer 31 in the first via hole H1 to the sixth via hole H6 are removed to expose the surface of the semiconductor layer.
  • the third insulating layer 33 and the second insulating layer 32 in the seventh via hole H7 are removed, exposing the surface of the first conductive layer.
  • the third insulating layer 33 inside the eighth via hole H8 and the ninth via hole H9 is removed, exposing the surface of the second conductive layer.
  • a third conductive film is deposited on the base substrate 30 formed with the foregoing pattern, and the third conductive film is patterned by a patterning process to form a third conductive layer on the third insulating layer 33 .
  • the third conductive layer of the second display area A2 at least includes: the first pole and the second pole of a plurality of transistors of the pixel circuit (for example, the first pole T11 of the first reset transistor T1, the threshold compensation transistor The first pole T21 of T2, the first pole T41 of the data writing transistor T4, the first pole T51 of the first light emission control transistor T5, the second pole T62 of the second light emission control transistor T6 and the first pole T7 of the second reset transistor T7 Pole T71).
  • the first electrode T11 of the first reset transistor T1 may be electrically connected to the first doped region of the active layer T10 of the first reset transistor T1 through the first via hole H1 , may also be electrically connected to the first initial signal line INIT1(i) through the eighth via hole H8.
  • the first electrode T21 of the threshold compensation transistor T2 can be electrically connected to the second doped region of the active layer of the threshold compensation transistor T2 through the second via hole H2, and can also be connected to the gate T33 of the driving transistor T3 through the seventh via hole H7. electrical connection.
  • the first electrode T41 of the data writing transistor T4 may be electrically connected to the first doped region of the active layer T40 of the data writing transistor T4 through the third via hole H3.
  • the second electrode T62 of the second light emission control transistor T6 may be electrically connected to the second doped region of the active layer T60 of the second light emission control transistor T6 through the fourth via hole H4.
  • the first electrode T51 of the first light emission control transistor T5 may be electrically connected to the first doped region of the active layer T50 of the first light emission control transistor T5 through the fifth via hole H5.
  • the first electrode T71 of the second reset transistor T7 can be electrically connected to the first doped region of the active layer T70 of the second reset transistor T7 through the sixth via hole H6, and can also be connected to the second initial signal through the ninth via hole H9.
  • Line INIT2(i) is electrically connected.
  • a fourth insulating film is deposited on the base substrate 30 formed with the aforementioned pattern, and the fourth insulating film is patterned by a patterning process to form the fourth insulating layer 34 .
  • the fourth insulating layer 34 of the second display area A2 is provided with a plurality of via holes, for example, the plurality of via holes may include: a tenth via hole H10 to a thirteenth via hole H13 .
  • the fourth insulating layer 34 in the tenth via hole H10 to the thirteenth via hole H13 is removed, exposing the surface of the third conductive layer.
  • a fourth conductive film is deposited on the base substrate 30 formed with the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fourth insulating layer 34 .
  • the fourth conductive layer of the second display area A2 at least includes: an anode connection terminal (for example, an anode connection terminal 36), a plurality of data lines (for example, data lines DL(j) and DL(j+1 )) and a plurality of first power lines (eg, first power lines PL1(j) and PL1(j+1)). Both the data lines and the first power lines extend along the second direction F2, and the data lines and the first power lines are arranged at intervals along the first direction F1.
  • j is an integer.
  • the data line DL(j) may be electrically connected to the first pole T41 of the data writing transistor T4 through the tenth via hole H10 .
  • the first power line PL1(j) may be electrically connected to the first pole T51 of the first light emission control transistor T5 through the twelfth via hole H12 and the thirteenth via hole H13.
  • the anode connection terminal 36 may be electrically connected to the second pole T62 of the second light emission control transistor T6 through the eleventh via hole H11 .
  • the anode connection terminal 36 of the pixel circuit can subsequently be electrically connected to the light emitting element.
  • the first display area A1 may include a base substrate 30 and a first insulating layer 31 , a second insulating layer 32 , a third insulating layer 33 and a fourth insulating layer 34 stacked on the base substrate 30 .
  • a first flat film is coated on the base substrate 30 formed with the aforementioned pattern, and the first flat film is patterned by a patterning process to form the first flat layer 41 .
  • the first flat layer 41 is provided with a plurality of first via holes K11 and a plurality of second via holes K12 .
  • the first flat layer 41 in the first via hole K11 is removed to expose the anode connection end of the second pixel circuit, and the first flat layer 41 in the second via hole K12 is removed to expose the first pixel.
  • Anode connection terminal of the circuit is
  • a transparent conductive film is deposited on the aforementioned base substrate 30 , and the transparent conductive film is patterned by a patterning process to form an electrical connection layer.
  • the electrical connection layer may include: a plurality of connection electrodes, a plurality of transition lines (for example, a first transition line, a second transition line), a plurality of first transparent conductive lines, and a plurality of transition lines. a second transparent conductive line.
  • a second planar film is coated on the base substrate 30 formed with the aforementioned pattern, and the second planar film is patterned by a patterning process to form the second planar layer 41 .
  • the second flat layer 42 defines a plurality of third via holes K13 .
  • the second flat layer 42 in the third via hole K13 is removed, exposing the surface of the electrical connection layer.
  • an anode film is deposited on the base substrate 30 formed with the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer.
  • a pixel-defining film is coated on the base substrate 30 formed with the aforementioned pattern, and a pixel-defining layer 54 is formed by masking, exposing and developing processes.
  • the pixel definition layer 54 is formed with a plurality of pixel openings exposing the anode layer.
  • an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode.
  • a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode layer 53, which is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be single-layer structure, or multi-layer composite structure, such as Mo/Cu /Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer 31, the second insulating layer 32, the third insulating layer 33 and the fourth insulating layer 34 can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) Or more, can be a single layer, multi-layer or composite layer.
  • the first insulating layer 31 and the second insulating layer 32 may be referred to as a gate insulating (GI) layer
  • the third insulating layer 33 and the fourth insulating layer 34 may be referred to as an interlayer insulating (ILD) layer.
  • Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the first planar layer 41 and the second planar layer 42 .
  • the pixel definition layer 54 can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can use reflective materials such as metal, and the cathode layer can use transparent conductive materials. However, this embodiment does not limit it.
  • the structure of the display substrate and the manufacturing process thereof in this embodiment are merely illustrative.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • a transfer hole exposing the fourth conductive layer can be opened, so that there is no need to connect the second pixel circuit electrically through the transfer wire.
  • the second light-emitting element can be directly electrically connected to the anode connection terminal of the second pixel circuit through the via hole penetrating the first planar layer and the second planar layer, without connecting through the connecting electrode.
  • this embodiment does not limit it.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and is well compatible with existing preparation processes.
  • the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • FIG. 26 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the first display area A1 may be semicircular.
  • the first display area A1 may include: two first sub-display areas A11a and A11b sequentially arranged along the first direction F1, and a second sub-display area A12a between the two first sub-display areas A11a and A11b.
  • the second display area A2 may include: two third sub-display areas A21a and A21b, a fourth sub-display area A22a and a fifth sub-display area A23.
  • the third sub-display area A21a is adjacent to the first sub-display area A11a in the first direction F1, and the first pixel circuit in the third sub-display area A21a is electrically connected to the first light emitting element in the first sub-display area A11a.
  • the third sub-display area A21b is adjacent to the first sub-display area A11b in the first direction F1, and the first pixel circuit in the third sub-display area A21b is electrically connected to the first light-emitting element in the first sub-display area A11b.
  • the fourth sub-display area A22a is adjacent to the second sub-display area A12a, and the first pixel circuit in the fourth sub-display area A22a is electrically connected to the first light-emitting element in the second sub-display area A12a.
  • FIG. 27 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display panel 91 of this embodiment may include a display substrate 910 .
  • the display substrate 910 may be as described in the foregoing embodiments, so details will not be repeated here.
  • At least one embodiment of the present disclosure further provides a display device, including: the above-mentioned display panel, and a photosensitive sensor disposed on a side of a non-display surface of the display panel.
  • the orthographic projection of the photosensitive sensor on the display panel overlaps with the first display area of the display substrate.
  • FIG. 28 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • this embodiment provides a display device, including: a display panel 91 and a photosensitive sensor 92 located on the light-emitting side of the display structure layer away from the display panel 91 (that is, the photosensitive sensor 92 is located on the non-display surface of the display panel 91 ). side).
  • the orthographic projection of the photosensitive sensor 92 on the display panel 91 overlaps with the first display area A1 .
  • the display panel 91 may be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel.
  • the display device can be any product or component with a display function such as an OLED display, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present disclosure are not limited thereto.

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Abstract

一种显示基板，包括：第一显示区(A1)和至少部分围绕第一显示区(A1)的第二显示区(A2)。显示基板包括：衬底基板(30)、像素电路以及发光元件。像素电路位于第二显示区(A2)的衬底基板(30)上，像素电路包括交替排布的第一像素电路(11)和第二像素电路(12)。发光元件位于像素电路远离衬底基板(30)的一侧，发光元件包括位于第一显示区(A1)的第一发光元件(EL1)以及位于第二显示区(A2)的第二子发光元件和第三子发光元件。第一像素电路(11)通过至少部分透明导电线与第一发光元件电连接。第二像素电路(12)通过第一转接孔与第二子发光元件电连接，第一转接孔在衬底基板的正投影与第三子发光元件在衬底基板的正投影存在交叠。

Description

显示基板、显示面板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板、显示面板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板、显示面板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：第一显示区和至少部分围绕第一显示区的第二显示区。显示基板包括：衬底基板、像素电路以及发光元件。像素电路位于第二显示区的衬底基板上，像素电路包括交替排布的第一像素电路和第二像素电路。发光元件位于像素电路远离衬底基板的一侧，发光元件包括位于第一显示区的第一发光元件以及位于第二显示区的第二子发光元件和第三子发光元件。所述第一像素电路通过至少部分透明导电线与所述第一发光元件电连接。所述第二像素电路通过第一转接孔与所述第二子发光元件电连接，所述第一转接孔在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述第三子发光元件与所述第二子发光元件相邻设置。
在一些示例性实施方式中，所述第二显示区内的至少一个第二像素电路通过所述第一转接孔与第一转接线电连接，所述第一转接线与所述第二子发光元件电连接，所述第一转接线与所述第二子发光元件的连接位置在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影不存在交叠。
在一些示例性实施方式中，所述第一转接线与所述像素电路之间设置有第一平坦层，所述第一转接线通过所述第一平坦层开设的第一转接孔与所述第二像素电路电连接。所述第一转接线与所述发光元件之间设置有第二平坦层，所述第一转接线通过所述第二平坦层开设的第三转接孔与所述第二子发光元件电连接。所述第三转接孔在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影不存在交叠。
在一些示例性实施方式中，所述第二显示区包括：至少一个第三子显示区，所述第三子显示区内的第一像素电路通过第一透明导电线与所述第一显示区内的第一发光元件电连接，所述第一透明导电线至少沿第一方向延伸。所述第三子显示区内的至少一个第二像素电路通过沿所述第一方向延伸的第一转接线与所述第二子发光元件电连接。
在一些示例性实施方式中，所述第二显示区包括：至少一个第四子显示区，所述第四子显示区内的第一像素电路通过第二透明导电线与所述第一显示区内的第一发光元件电连接，所述第二透明导电线至少沿第二方向延伸，所述第二方向与所述第一方向交叉。所述第四子显示区内的至少一个第二像素电路通过沿所述第二方向延伸的第一转接线与所述第二子发光元件电连接。
在一些示例性实施方式中，所述第二显示区还包括：第五子显示区，所述第五子显示区内的第一像素电路为无效像素电路。所述第五子显示区的至少一个第二像素电路通过沿任一方向延伸的第一转接线与所述第二子发光元件电连接。
在一些示例性实施方式中，所述第一显示区包括：至少一个第一子显示区和至少一个第二子显示区。所述第三子显示区在所述第一方向与至少一个第一子显示区相邻，所述第四子显示区在所述第二方向与至少一个第二子显示区相邻。所述第一透明导电线和第二透明导电线的长度取值范围大致相同。
在一些示例性实施方式中，所述发光元件还包括位于第二显示区的第四 子发光元件。所述第二显示区内的至少一个第二像素电路通过第一转接孔与所述第四子发光元件电连接，所述第一转接孔在所述衬底基板的正投影与所述第四子发光元件的发光区域在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述第二像素电路通过所述第一转接孔与第二转接线电连接，所述第二转接线与所述第四子发光元件电连接。所述第二转接线与所述第四子发光元件的连接位置在所述衬底基板的正投影与所述第四子发光元件的发光区域在所述衬底基板的正投影不存在交叠。
在一些示例性实施方式中，所述第二显示区至少包括：第三子显示区和第四子显示区。所述第三子显示区内的第一像素电路通过第一透明导电线与所述第一显示区内的第一发光元件电连接，所述第一透明导电线至少沿第一方向延伸。所述第四子显示区内的第一像素电路通过第二透明导电线与所述第一显示区内的第一发光元件电连接，所述第二透明导电线至少沿第二方向延伸，所述第二方向与所述第一方向交叉。所述第三子显示区内的至少一个第二像素电路通过沿所述第一方向延伸的第二转接线与所述第四子发光元件电连接。所述第四子显示区内的至少一个第二像素电路通过沿所述第二方向延伸的第二转接线与所述第四子发光元件电连接。
在一些示例性实施方式中，在所述第二显示区内，所述第一像素电路和第二像素电路在第一方向和第二方向上均交替排布；所述第一方向与第二方向交叉。
在一些示例性实施方式中，在所述第一方向上，四列第二像素电路和一列第一像素电路交替排布，在所述第二方向上，四行第二像素电路和一行第一像素电路交替排布。
在一些示例性实施方式中，所述像素电路包括：驱动晶体管以及第一晶体管；所述第一晶体管的第一极与所述驱动晶体管的栅极电连接。所述第一晶体管为双栅晶体管。所述像素电路与第一初始信号线电连接，所述第一初始信号线在所述衬底基板的正投影与所述第一晶体管的有源层的沟道区在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述第一晶体管的有源层的沟道区包括：第一沟道区、第二沟道区和第三沟道区，所述第三沟道区位于所述第一沟道区 和第二沟道区之间；所述第一晶体管的第一栅极在所述衬底基板的正投影覆盖所述第一沟道区在所述衬底基板的正投影，所述第一晶体管的第二栅极在所述衬底基板的正投影覆盖所述第二沟道区在所述衬底基板的正投影。所述第一初始信号线在所述衬底基板的正投影与所述第一晶体管的有源层的第三沟道区在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述第三沟道区在所述衬底基板的正投影为倒L形。
在一些示例性实施方式中，所述第一初始信号线包括：沿所述第一方向延伸的本体部和沿所述第二方向从所述本体部延伸出的伸出部。所述伸出部在所述衬底基板的正投影与所述第一晶体管的有源层的沟道区在所述衬底基板的正投影存在交叠。
在一些示例性实施方式中，所述像素电路包括多个晶体管以及至少一个存储电容；所述晶体管包括：有源层、栅极、第一极和第二极，所述存储电容包括第一电容极板和第二电容极板，所述晶体管的栅极与存储电容的其中一个电容极板为同层结构，所述晶体管的第一极和第二极为同层结构。
在一些示例性实施方式中，所述第一初始信号线与所述像素电路的存储电容的另一个电容极板为同层结构。
另一方面，本公开实施例提供一种显示面板，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板，以及设置于所述显示面板非显示面一侧的感光传感器，所述感光传感器在所述显示面板的正投影与所述显示面板的显示基板的第一显示区存在交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为图2提供的像素电路的工作时序图；
图4为本公开至少一实施例的显示基板的显示区域的局部示意图；
图5为本公开至少一实施例的第二显示区的第二发光元件的排布示意图；
图6为图1中的第二显示区的第三子显示区的局部平面示意图；
图7A为图6中沿P-P’方向的局部剖面示意图；
图7B为图6中沿Q-Q’方向的局部剖面示意图；
图8为图6中形成第一平坦层后的第三子显示区的局部平面示意图；
图9为图6中形成电连接层后的第三子显示区的局部平面示意图；
图10为图6中形成第二平坦层后的第三子显示区的局部平面示意图；
图11为图1中的第二显示区的第四子显示区的局部平面示意图；
图12为图11中形成电连接层后的第四子显示区的局部平面示意图；
图13为图1中的第二显示区的第五子显示区的局部平面示意图；
图14为图11中形成电连接层后的第五子显示区的局部平面示意图；
图15为图1中的第二显示区的第三子显示区的另一局部平面示意图；
图16A为图15中沿P-P’方向的局部剖面示意图；
图16B为图15中沿Q-Q’方向的局部剖面示意图；
图17为本公开至少一实施例的一个像素电路的俯视示意图；
图18为图17中沿R-R’方向的局部剖面示意图；
图19为本公开至少一实施例的第二显示区的局部俯视示意图；
图20为本公开至少一实施例的形成半导体层后的第二显示区的俯视示意图；
图21为本公开至少一实施例的形成第一导电层后的第二显示区的俯视示意图；
图22为本公开至少一实施例的形成第二导电层后的第二显示区的俯视 示意图；
图23为本公开至少一实施例的形成第三绝缘层后的第二显示区的俯视示意图；
图24为本公开至少一实施例的形成第三导电层后的第二显示区的俯视示意图；
图25为本公开至少一实施例的形成第四绝缘层后的第二显示区的俯视示意图；
图26为本公开至少一实施例的显示基板的另一示意图；
图27为本公开至少一实施例的显示面板的示意图；
图28为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描 述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
本公开实施例提供一种显示基板，包括：第一显示区和至少部分围绕第一显示区的第二显示区。显示基板包括：衬底基板、像素电路以及发光元件。像素电路位于第二显示区的衬底基板上，像素电路包括交替排布的第一像素电路和第二像素电路。发光元件位于像素电路远离衬底基板的一侧，发光元件包括位于第一显示区的第一发光元件以及位于第二显示区的第二子发光元件和第三子发光元件。第一像素电路通过至少部分透明导电线与第一发光元件电连接。第二像素电路通过第一转接孔与第二子发光元件电连接，第一转接孔在衬底基板的正投影与第三子发光元件在衬底基板的正投影存在交叠。
在一些示例中，第二显示区的第三子发光元件与第二子发光元件相邻设置。然而，本实施例对此并不限定。例如，第二子发光元件和第三子发光元件可以不相邻设置，第二子发光元件和第三子发光元件之间还排布其余子发光元件。
在一些示例性实施方式中，第二显示区内的至少一个第二像素电路通过第一转接孔与第一转接线电连接，第一转接线与第二子发光元件电连接。第一转接线与第二子发光元件的连接位置在衬底基板的正投影与第三子发光元件在衬底基板的正投影不存在交叠。本示例提供的显示基板，由于在第二显示区设置有第二像素电路和第一像素电路，第二像素电路和对应电连接的发光元件会存在错位，若第二像素电路直接与发光元件电连接，会存在发光元件短接的情况。本实施例针对存在短接情况的第二子发光元件，通过第一转接线电连接第二像素电路和第二子发光元件，可以避免第二子发光元件和第三子发光元件短接的情况，从而改善显示效果。
在一些示例性实施方式中，第一转接线与像素电路之间设置有第一平坦层，第一转接线通过第一平坦层开设的第一转接孔与第二像素电路电连接。第一转接线与发光元件之间设置有第二平坦层，第一转接线通过第二平坦层开设的第三转接孔与第二子发光元件电连接。第三转接孔在衬底基板的正投影与第三子发光元件在衬底基板的正投影不存在交叠。本示例提供的显示基 板，利用第一转接线，将第二像素电路与第二子发光元件的连接位置从第一转接孔所在位置转移到第三转接孔所在位置，使得第二像素电路与第二子发光元件的连接位置与第三子发光元件在衬底基板的正投影不存在交叠，从而避免发光元件短接的情况。在一些示例中，第一转接孔在衬底基板的正投影与第三转接孔在衬底基板的正投影可以部分交叠或者不存在交叠。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二显示区包括：至少一个第三子显示区，第三子显示区内的第一像素电路通过第一透明导电线与第一显示区内的第一发光元件电连接。第一透明导电线至少沿第一方向延伸。第三子显示区内的至少一个第二像素电路通过沿第一方向延伸的第一转接线与第二子发光元件电连接。本示例中，通过在第三子显示区采用沿第一方向延伸的第一转接线电连接第二像素电路和第二子发光元件，可以给第一透明导电线留出更多的走线空间。
在一些示例性实施方式中，第二显示区可以包括：至少一个第四子显示区，第四子显示区的第一像素电路通过第二透明导电线与第一显示区内的第一发光元件电连接。第二透明导电线至少沿第二方向延伸。第二方向与第一方向交叉。第四子显示区内的至少一个第二像素电路通过沿第二方向延伸的第一转接线与第二子发光元件电连接。本示例中，通过在第四子显示区采用沿第二方向延伸的第一转接线电连接第二像素电路和第二子发光元件，可以给第二透明导电线留出更多的走线空间。
在一些示例性实施方式中，第二显示区还可以包括：第五子显示区。第五子显示区内的第一像素电路为无效像素电路。第五子显示区的至少一个第二像素电路通过沿任一方向延伸的第一转接线与第二子发光元件电连接。在本示例中，第五子显示区没有排布第一透明导电线和第二透明导电线，因此，第一转接线的延伸方向可以不受透明导电线的限制。
在一些示例性实施方式中，第一显示区可以包括：至少一个第一子显示区和至少一个第二子显示区。第三子显示区在第一方向与至少一个第一子显示区相邻，第四子显示区在所述第二方向与至少一个第二子显示区相邻。第一透明导电线和第二透明导电线的长度取值范围大致相同。
本示例中，通过将第一显示区划分为第一子显示区和第二子显示区，并使得第一子显示区的第一发光元件与第一方向相邻的第二显示区内的第一像素电路电连接，以及第二子显示区的第一发光元件与第二方向相邻的第二显示区内的第一像素电路电连接，有利于减小第一透明导电线和第二透明导电线的长度，改善显示效果，而且有利于改善对第一显示区的尺寸限制。
例如，在第一显示区的尺寸一定的情况下，相较于第一显示区的第一发光元件仅与第一方向相邻的第二显示区的第一像素电路电连接的方案，本实施例通过设置第一子显示区的第一发光元件与第一方向相邻的第二显示区的第一像素电路电连接，以及第二子显示区的第一发光元件与第二方向相邻的第二显示区的第一像素电路电连接，可以避免电连接第一发光元件和第一像素电路的透明导电线过长，而且可以扩展第一透明导电线和第二透明导电线的排布范围，并不局限第一透明导电线和第二透明导电线的数目。
例如，在第一透明导电线和第二透明导电线的最大长度一定的情况下，相较于第一显示区的第一发光元件仅与第一方向相邻的第二显示区的第一像素电路电连接的方案，本实施例通过设置第一子显示区的第一发光元件与第一方向相邻的第二显示区的第一像素电路电连接，以及第二子显示区的第一发光元件与第二方向相邻的第二显示区的第一像素电路电连接，可以增加第一显示区的尺寸。
在一些示例性实施方式中，第一显示区可以包括：沿第一方向依次排布的两个第一子显示区、以及沿第二方向依次排布的两个第二子显示区。第二显示区可以包括：沿第一方向排布的两个第三子显示区、以及沿第二方向排布的两个第四子显示区。在第一方向上，一个第三子显示区与一个第一子显示区相邻；在第二方向上，一个第四子显示区与一个第二子显示区相邻。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一转接线、第一透明导电线和第二透明导电线可以为同层结构。然而，本实施例对此并不限定。例如，第一转接线、第一透明导电线和第二透明导电线中至少两个可以为异层结构。或者，例如，第一透明导电线和第二透明导电线可以为多层结构。
在一些示例性实施方式中，发光元件还可以包括位于第二显示区的第四 子发光元件。第二显示区内的至少一个第二像素电路通过第一转接孔与第四子发光元件电连接，第一转接孔在衬底基板的正投影与第四子发光元件的发光区域在衬底基板的正投影存在交叠。
在一些示例性实施方式中，第二像素电路通过第一转接孔与第二转接线电连接，第二转接线与第四子发光元件电连接。第二转接线与第四子发光元件的连接位置在衬底基板的正投影与第四子发光元件的发光区域在衬底基板的正投影不存在交叠。本示例提供的显示基板，由于在第二显示区设置有第二像素电路和第一像素电路，第二像素电路和对应电连接的发光元件会存在错位，若第二像素电路直接与发光元件电连接，会存在导致发光元件损失开口率的情况。本实施例针对存在开口率损失情况的第四子发光元件，通过第二转接线电连接第二像素电路和第四子发光元件，可以避免第四子发光元件损失开口率的情况，从而改善显示效果。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA周边的周边区域BB。显示基板的显示区域AA可以包括：第一显示区A1和至少部分围绕第一显示区A1的第二显示区A2。在本示例中，第二显示区A2围绕在第一显示区A1的四周。
在一些示例性实施方式中，第一显示区A1为透光显示区，还可以称为屏下摄像头(UDC，Under Display Camera)区域；第二显示区A2为非透光显示区，还可以称为正常显示区。例如，感光传感器(如，摄像头等硬件)在显示基板上的正投影可以位于显示基板的第一显示区A1内。在一些示例中，如图1所示，第一显示区A1可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的尺寸。然而，本实施例对此并不限定。在另一些示例中，第一显示区A1可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的内切圆的尺寸。
在一些示例性实施方式中，如图1所示，第一显示区A1可以位于显示区域AA的顶部正中间位置。第二显示区A2可以围绕在第一显示区A1的四周。然而，本实施例对此并不限定。例如，第一显示区A1可以位于显示区 域AA的左上角或者右上角等其他位置。例如，第二显示区A2可以围绕在第一显示区A1的至少一侧。
在一些示例性实施方式中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。第一显示区A1可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第一显示区A1可以为矩形、半圆形、五边形等其他形状。
在一些示例性实施方式中，显示区域AA设置有多个子像素。至少一个子像素包括像素电路和发光元件。像素电路配置为驱动所连接的发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(3个晶体管和1个电容)结构、7T1C(7个晶体管和1个电容)结构或者5T1C(5个晶体管和1个电容)结构等。在一些示例中，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例性实施方式中，发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。图3为图2提供的像素电路的工作时序图。
在一些示例性实施方式中，如图2所示，本示例性实施例的像素电路可以包括：六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体 管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL可以包括阳极、阴极以及位于阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图2所示，像素电路与扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2电连接。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL配置为向像素电路提供扫描信号SCAN，数据线DL配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供第二复位信号RESET2。在一些示例中，在一行像素电路中，第二复位控制线RST2可以与扫描线GL相连，以被输入扫描信号SCAN。即，第n行像素电路接收的第二复位信号RESET2(n)为第n行像素电路接收的扫描信号SCAN(n)。 然而，本实施例对此并不限定。例如，第二复位控制信号线RST2可以被输入不同于扫描信号SCAN的第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例性实施方式中，如图2所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2为双栅晶体管，阈值补偿晶体管T2的第一栅极和第二栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电极与驱动晶体管T3的栅极电连接，存储电容Cst的第二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图3对图2所示的像素电路的工作过程进行说明。其中，以图2所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图2和图3所示，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第一电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据 电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段S3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2；
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图4为本公开至少一实施例的显示基板的显示区域的局部示意图。在一些示例性实施方式中，如图1和图4所示，第一显示区A1包括沿第一方向F1依次排布的两个第一子显示区A11a和A12a、以及沿第二方向F2依次排布的两个第二子显示区A12a和A12b。第一方向F1与第二方向F2交叉，例 如第一方向F1垂直于第二方向F2。第二显示区A2包括：在第一方向F1上与第一子显示区A11a相邻的第三子显示区A21a、在第一方向F1上与第一子显示区A11b相邻的第三子显示区A21b、在第二方向F2上与第二子显示区A12a相邻的第四子显示区A22a、在第二方向F2上与第二子显示区A12b相邻的第四子显示区A22b、以及第五子显示区A23。第五子显示区A23为第二显示区A2中除第三子显示区A21a和A21b以及第四子显示区A22a和A22b以外的区域。第三子显示区A21a在第一方向F1上正对第一子显示区A11a，第三子显示区A21b在第一方向F1上正对第一子显示区A11b；第四子显示区A22a在第二方向F2上正对第二子显示区A12a，第四子显示区A22b在第二方向F2上正对第二子显示区A12b。
在本示例中，如图1和图4所示，第一显示区A1可以沿第三方向F3的中心线和第四方向F4的中心线划分为四个子显示区，即两个第一子显示区A11a和A11b以及两个第二子显示区A12a和A12b。第三方向F3与第一方向F1和第二方向F2均交叉，第四方向F4可以垂直于第三方向F3。然而，本实施例对此并不限定。例如，第一显示区A1可以沿第一方向F1的中心线和第二方向F2的中心线划分为四个子显示区(例如，沿第三方向依次排布的两个第一子显示区和沿第四方向依次排布的两个第二子显示区)，第二显示区A2的第三子显示区可以在第三方向上与第一子显示区相邻，第四子显示区可以在第四方向上与第二子显示区相邻。
在一些示例性实施方式中，如图1所示，第一显示区A1可以为圆形，两个第一子显示区A11a和A11b以及两个第二子显示区A12a和A12b可以为大小相同的扇形。两个第三子显示区A21a和A21b以及两个第四子显示区A22a和A22b可以均为圆形。然而，本实施例对此并不限定。例如，两个第一子显示区和两个第二子显示区的大小可以不同。又例如，第一显示区可以为矩形，第一子显示区和第二子显示区可以为矩形，第三子显示区和第四子显示区可以为矩形。
在一些示例性实施方式中，如图1和图4所示，第一显示区A1设置有多个第一发光元件EL1。第二显示区A2设置有多个第二发光元件以及多个像素电路。第二显示区A2的多个像素电路可以包括多个第一像素电路11和 多个第二像素电路12。第二显示区A2的至少一个第一像素电路11与第一显示区A1的至少一个第一发光元件EL1电连接。例如，第一显示区A1的第一发光元件EL1和第二显示区A2的第一像素电路11可以为一对一或者多对一的关系，换言之，第二显示区A2的一个第一像素电路11可以配置为驱动第一显示区A1内的一个或多个第一发光元件EL1发光。第二显示区A2的至少一个第二像素电路12与至少一个第二发光元件电连接。例如，第二显示区A2的多个第二像素电路12与多个第二发光元件可以为一一对应关系，换言之，第二显示区A2内的一个第二像素电路12可以配置为驱动一个第二发光元件发光。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1和图4所示，第一显示区A1的第一子显示区A11a内的第一发光元件EL1可以通过第一透明导电线L1与第二显示区A2的第三子显示区A21a内的第一像素电路11电连接。第一显示区A1的第一子显示区A11b内的第一发光元件EL1可以通过第一透明导电线L1与第二显示区A2的第三子显示区A21b内的第一像素电路11电连接。第一显示区A1的第二子显示区A12a内的第一发光元件EL1可以通过第二透明导电线L2与第二显示区A2的第四子显示区A22a内的第一像素电路11电连接。第一显示区A1的第二子显示区A12b内的第一发光元件EL1可以通过第二透明导电线L2与第二显示区A2的第四子显示区A22b内的第一像素电路11电连接。其中，第一透明导电线L1和第二透明导电线L2可以采用透明导电材料。如此一来，可以提高第一显示区A1的光透过率。在本示例中，第一透明导电线L1大致可以沿第一方向F1延伸，第二透明导电线L2大致可以沿第二方向F2延伸。在一些示例中，第一透明导电线L1可以为单层走线或者多层走线(即由不同膜层的走线串联或并联形成)，第二透明导电线L2可以为单层走线或者多层走线。例如，相同颜色的第一发光元件电连接的第一透明导电线和第二透明导电线可以为同层结构，不同颜色的第一发光元件电连接的第一透明导电线可以位于不同膜层，不同颜色的第二发光元件电连接的第二透明导电线可以位于不同膜层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1和图4所示，以第一子显示区A11a内的第一发光元件EL1和第三子显示区A21a内的第一像素电路11为例，第 一子显示区A11a内靠近第三子显示区A21a的第一发光元件EL1，与第三子显示区A21a内远离第一子显示区A11a的第一像素电路11电连接；第一子显示区A11a内远离第三子显示区A21a的第一发光元件EL1，与第三子显示区A21a内靠近第一子显示区A11a的第一像素电路11电连接。连接不同第一发光元件EL1和第一像素电路11的多条第一透明导电线L1的长度可以大致相同。同理，在第二方向F2上，连接不同第一发光元件EL1和第一像素电路11的多条第二透明导电线L2的长度可以大致相同。在一些示例中，第一透明导电线L1和第二透明导电线L2的长度取值范围可以大致相同。如此一来，可以整体减小透明导电线的最大长度，减小透明导电线的走线长度差异，使得显示画面呈现更好的均一性。
本示例性通过将第一显示区的第一发光元件设置为与排布在两个不同方向(即第一方向F1和第二方向F2)上的第一像素电路电连接，有利于减小第一透明导电线和第二透明导电线的最大走线长度，还可以改善对第一显示区的尺寸限制，有助于增加第一显示区的大小。
在一些示例性实施方式中，第二显示区的第一像素电路11和第二像素电路可以沿第一方向F1和第二方向F2交替排布。在本示例中，沿第一方向F1依次排布的多个像素电路可以称为一行像素电路，沿第二方向F2依次排布的多个像素电路可以称为一列像素电路。
在一些示例性实施方式中，如图4所示，沿第一方向F1排布的多个第二像素电路12之间设置有至少一个第一像素电路11，沿第二方向F2排布的多个第二像素电路12之间设置有至少一个第一像素电路11。第一像素电路11可以排布在多行和多列第二像素电路12之间。例如，在第一方向F1上，四列第二像素电路12与一列第一像素电路11交替排布，在第二方向F2上，四行第二像素电路12和一行第一像素电路11交替排布。换言之，每四行第二像素电路12之间设置一行第一像素电路11，每四列第二像素电路12之间设置一列第一像素电路11。相较于仅设置第二像素电路的第二显示区，本示例将原来的每四列第二像素电路通过沿第一方向F1压缩可以新增一列第一像素电路11的排布空间，将原来的每四行第二像素电路通过沿第二方向F2压缩，可以新增一行第一像素电路11的设置空间。例如，原来按照4*4阵列 排布的多个像素电路在沿第一方向F1和第二方向F2压缩之后，可以得到5*5阵列排布的多个像素电路(例如，包括4*4阵列排布的压缩后的第二像素电路以及新增的一行和一列第一像素电路)，且压缩前的4*4阵列排布的像素电路和压缩后的5*5阵列排布的像素电路所占用的空间是相同的。然而，本实施例对此并不限定。
在一些示例性实施方式中，为了显示均一性，第二显示区A2内可以按照相同规律排布第二像素电路和第一像素电路。第二显示区A2的第三子显示区和第四子显示区内的第一像素电路与第一显示区内的第一发光元件电连接，第五子显示区A23内的第一像素电路没有与第一显示区的第一发光元件电连接。换言之，第五子显示区A23的第一像素电路可以作为无效(Dummy)像素电路。然而，本实施例对此并不限定。例如，可以仅在第三子显示区和第四子显示区通过压缩第二像素电路来增设第一像素电路，第五子显示区可以不增设第一像素电路。
图5为本公开至少一实施例的第二显示区的第二发光元件的排布示意图。在一些示例性实施方式中，如图5所示，第二显示区A2的多个第二发光元件可以包括：多个绿色第二发光元件221和224、多个红色第二发光元件222、以及多个蓝色第二发光元件223。第二显示区A2的至少一个像素单元可以包括：一个蓝色第二发光元件223、两个绿色第二发光元件221和224、以及一个红色第二发光元件222。绿色第二发光元件221和224在第二方向F2上依次排布，红色第二发光元件222和蓝色第二发光元件223在第一方向F1上依次排布。相邻行的同色第二发光元件在第一方向F1上存在错位。
在一些示例性实施方式中，第一显示区A1的多个第一发光元件可以包括：多个绿色第一发光元件、多个红色第一发光元件以及多个蓝色第一发光元件。第一显示区A1内的多个第一发光元件的排布方式与第二显示区A2内的多个第二发光元件的排布方式可以一致，故于此不再赘述。
在一些示例性实施方式中，显示区域AA的至少一个发光元件可以包括：阳极、阴极以及设置在阳极和阴极之间的有机发光层。如图5所示，第二显示区A2的绿色第二发光元件221和224的阳极在衬底基板上的正投影可以为五边形，红色第二发光元件222和蓝色第三发光元件223的阳极在衬底基 板上的正投影可以为六边形。第一显示区A1的第一发光元件的阳极面积可以小于第二显示区A2的发出相同颜色光的第二发光元件的阳极面积。例如，第一显示区的绿色第一发光元件的阳极在衬底基板的正投影可以为圆形，红色第一发光元件和蓝色第一发光元件的阳极在衬底基板的正投影可以为椭圆形。例如，上述椭圆形可以为一个方形和两个半圆形的组合形状，其中两个半圆形连接在方形的相对两端。在本示例中，通过对第一显示区的第一发光元件的阳极进行角部平滑设计，可以有利于降低显示基板的第一显示区下方的摄像头在拍摄时的衍射，从而提高拍摄效果。然而，本实施例对此并不限定。
图6为图1中的第二显示区的第三子显示区的局部平面示意图。图7A为图6中沿P-P’方向的局部剖面示意图。图7B为图6中沿Q-Q’方向的局部剖面示意图。图8为图6中形成第一平坦层后的第三子显示区的局部平面示意图。图9为图6中形成电连接层后的第三子显示区的局部平面示意图。图10为图6中形成第二平坦层后的第三子显示区的局部平面示意图。图11为图1中的第二显示区的第四子显示区的局部平面示意图。图12为图11中形成电连接层后的第四子显示区的局部平面示意图。图13为图1中的第二显示区的第五子显示区的局部平面示意图。图14为图11中形成电连接层后的第五子显示区的局部平面示意图。
在一些示例性实施方式中，如图6、图11和图13所示，由于在第二像素电路12之间增设了第一像素电路11，第二显示区A2的像素电路行数比第二发光元件的行数多，列数比第二发光元件的列数多，导致第二像素电路和所电连接的第二发光元件之间会存在错位，直接电连接第二像素电路与第二发光元件的阳极，会导致相邻第二发光元件短路以及造成开口率损失的情况。
在一些示例性实施方式中，如图7A和图7B所示，在垂直于显示基板的方向上，第二显示区A2可以包括：衬底基板30、依次设置在衬底基板30上的像素电路层40、第一平坦层41、电连接层、第二平坦层42以及发光结构层。像素电路层40可以包括：多个第一像素电路11和多个第二像素电路12。电连接层可以包括：多个连接电极(例如，连接电极431b)、多个转接线(例如包括第一转接线以及第二转接线)、多条第一透明导电线以及多条 第二透明导电线。发光结构层可以包括：阳极层(例如包括多个第二发光元件的阳极)、像素定义层54、有机发光层(例如，有机发光层52a和52b)以及阴极层53。至少一个第二发光元件的有机发光层夹设在阳极和阴极之间。多个第二发光元件的阴极可以为一体结构。
在一些示例中，第二显示区A2的多个第二发光元件可以包括第二子发光元件和第三子发光元件。第二子发光元件通过第一转接孔与第二像素电路电连接，且第一转接孔在衬底基板的正投影与第三子发光元件在衬底基板的正投影存在交叠。其中，第二子发光元件与第三子发光元件可以相邻设置。然而，本实施例对此并不限定。例如，第二子发光元件与第三子发光元件可以不相邻设置。
在一些示例中，第二显示区A2的多个第二发光元件还可以包括：第四子发光元件。第四子发光元件通过第一转接孔与第二像素电路电连接，且第一转接孔在衬底基板的正投影与第四子发光元件的发光区域在衬底基板的正投影存在交叠。
下面参照图6至图10，以图6中的绿色第二发光元件231至233、红色第二发光元件234、以及蓝色第二发光元件235为例说明第三子显示区的结构。其中，第二子发光元件以绿色第二发光元件233为例，第三子发光元件以蓝色第二发光元件235为例，第四子发光元件以绿色第二发光元件232为例进行说明。
在一些示例性实施方式中，如图6至图8所示，覆盖像素电路层的第一平坦层41上开设有多个第一转接孔K11和多个第二转接孔K12。第一转接孔K11和第二转接孔K12内的第一平坦层41被去掉，第二转接孔K12可以暴露出第一像素电路11的阳极连接端，第一转接孔K11可以暴露出第二像素电路12的阳极连接端。如图8所示，同一行第一转接孔K11和第二转接孔K12沿第一方向F1依次排布，同一列第一转接孔K11和第二转接孔K12沿第二方向F2依次排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图6至图9所示，第二显示区A2的第三子显示区的电连接层可以包括：多个连接电极(例如，连接电极431a至431c)、以及多个转接线(例如，第二转接线432a和第一转接线432b)。每个连接 电极可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接，每个转接线可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接。第三子显示区内的第一转接线和第二转接线可以均沿第一方向F1延伸。图9中省略示意了通过第二转接孔K12与第一像素电路11的阳极连接端电连接的第一透明导电线。第一透明导电线可以大致沿第一方向F1延伸至第一显示区A1，以实现第一像素电路11与第一发光元件之间的电连接。在第三子显示区内，通过设置沿第一方向F1延伸的第一转接线和第二转接线，可以改变第二发光元件的阳极与第二像素电路的连接位置，从而给第一透明导电线的排布留出更多的空间间隙。
在一些示例性实施方式中，如图10所示，覆盖电连接层的第二平坦层42上开设有多个第三转接孔K13。第三转接孔K13内的第二平坦层42被去掉，暴露出电连接层的表面。
在一些示例性实施方式中，如图6至图10所示，绿色第二发光元件232的阳极232a通过一个第三转接孔K13与第二转接线432a电连接，第二转接线432a通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。由于绿色第二发光元件232的发光区域232b在衬底基板30的正投影与该第一转接孔K11在衬底基板30的正投影存在交叠，若绿色第二发光元件232的阳极232a通过该第一转接孔K11与该第二像素电路12的阳极连接端直接电连接，会影响绿色第二发光元件232的发光区域232b的膜层平坦性，从而造成绿色第二发光元件232损失开口率，影响显示效果。在本示例中，第二转接线432a与第二像素电路12的阳极连接端的连接位置(即第一转接孔K11)在衬底基板30的正投影与第二发光元件232的发光区域232b在衬底基板30的正投影存在交叠，第二转接线432a与第二发光元件232的连接位置(即第三转接孔K13)在衬底基板30的正投影与第二发光元件232的发光区域232b在衬底基板30的正投影没有交叠。第二转接线432a所连接的第一转接孔K11和第三转接孔K13在衬底基板30的正投影没有交叠。在本示例中，通过沿第一方向F1延伸的第二转接线432a将绿色第二发光元件232的阳极232a的连接位置转移至发光区域232b之外的区域(即，绿色第二发光元件232的发光区域232b在衬底基板30的正投影与阳极232a电连接的第 三转接孔K13在衬底基板30的正投影没有交叠)，并通过第二平坦层42进行膜层平坦化处理，可以确保发光区域232b的膜层平坦性，以保证绿色第二发光元件232的开口率和显示效果。
在一些示例性实施方式中，如图6至图10所示，绿色第二发光元件233的阳极233a可以通过一个第三转接孔K13与第一转接线432b电连接，第一转接线432b可以通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。由于绿色第二发光元件233所对应的第一转接孔K11在衬底基板30的正投影与蓝色第二发光元件235的阳极235a在衬底基板30的正投影存在交叠，若绿色第二发光元件233的阳极233a通过该第一转接孔K11与该第二像素电路12的阳极连接端直接电连接，会存在绿色第二发光元件233的阳极233a和蓝色第二发光元件235的阳极235a短路的情况，容易造成显示不良。在本示例中，通过沿第一方向F1延伸的第一转接线432b将绿色第二发光元件233的阳极233a的连接位置移动至蓝色第二发光元件235的阳极235a以外的区域(例如，将连接位置移动至靠近红色第二发光元件234的一侧)，以便于绿色第二发光元件233的阳极233a与第二像素电路12进行电连接。在本示例中，第一转接线432b与第二像素电路12的阳极连接端的连接位置(即第一转接孔K11)在衬底基板30的正投影与第二发光元件235的阳极235a在衬底基板30的正投影存在交叠，第一转接线432b与第二发光元件233的连接位置(即第三转接孔K13)在衬底基板30的正投影与第二发光元件235的阳极235a在衬底基板30的正投影没有交叠。第一转接线432b所连接的第一转接孔K11和第三转接孔K13在衬底基板30的正投影没有交叠。在本示例中，蓝色第二发光元件235的阳极235a在衬底基板30的正投影与绿色第二发光元件233的阳极233a在衬底基板30的正投影没有交叠，如此可以规避相邻第二发光元件短路的情况，从而确保显示效果。
在一些示例性实施方式中，如图6至图10所示，绿色第二发光元件231的阳极231a可以通过连接电极431a经由一个第一转接孔K11与对应的一个第二像素电路12电连接，红色第二发光元件234的阳极234a可以通过连接电极431b经由一个第一转接孔K11与对应的一个第二像素电路12电连接，蓝色第二发光元件235的阳极235a可以通过连接电极431c经由一个第一转 接孔K11与对应的一个第二像素电路12电连接。
在本示例中，发光区域可以指像素定义层暴露出的阳极的开口区域，即发光元件的阳极、有机发光层以及阴极的交叠区域。
在本示例性实施方式中，在第三子显示区内，存在错位的第二像素电路和第二子发光元件可以通过第一转接线电连接，且第一转接线沿第一方向延伸，可以实现第二子发光元件的阳极与对应的第二像素电路的电连接，并避免第二子发光元件与第三子发光元件的短路风险。存在错位的第二像素电路和第四子发光元件可以通过第二转接线电连接，且第二转接线沿第一方向延伸，可以改善第二子发光元件的开口率损失情况。而且，通过设置第一转接线和第二转接线均沿第一方向延伸，可以给电连接第一像素电路和第一发光元件的第一透明导电线提供排布空间，避免对第一透明导电线的排布产生影响。
下面参照图11和图12，以图11中的绿色第二发光元件241至243、红色第二发光元件244、以及蓝色第二发光元件245为例说明第四子显示区的结构。其中，第二子发光元件以绿色第二发光元件243为例，第三子发光元件以蓝色第二发光元件245为例，第四子发光元件以绿色第二发光元件242为例进行说明。
在一些示例性实施方式中，如图11和图12所示，第二显示区A2的第四子显示区的电连接层可以包括：多个连接电极(例如，连接电极431a至433c)、以及多个转接线(例如，第二转接线434a和第一转接线434b)。每个连接电极可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接。每个转接线可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接。第四子显示区内的第一转接线和第二转接线可以均沿第二方向F2延伸。图11和图12中省略示意了与第二转接孔电连接的第二透明导电线。第二透明导电线可以大致沿第二方向F2延伸至第一显示区，以实现第一像素电路与第一发光元件之间的电连接。在第四子显示区内，通过设置沿第二方向F2延伸的第一转接线和第二转接线，可以改变第二发光元件的阳极与第二像素电路的连接位置，从而给第二透明导电线的排布留出更多的空间间隙。
在一些示例性实施方式中，如图11和图12所示，绿色第二发光元件242的阳极242a通过一个第三转接孔与第二转接线434a电连接，第二转接线434a通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。由于绿色第二发光元件242的发光区域242b在衬底基板30的正投影与该第一转接孔K11在衬底基板30的正投影存在交叠，若绿色第二发光元件242的阳极242a通过该第一转接孔K11与该第二像素电路12的阳极连接端直接电连接，会影响绿色第二发光元件242的发光区域242b的膜层平坦性，从而造成绿色第二发光元件242损失开口率，影响显示效果。在本示例中，通过沿第二方向F2延伸的第二转接线434a将绿色第二发光元件242的阳极242a的连接位置转移至发光区域242b之外的区域(即，绿色第二发光元件242的发光区域242b在衬底基板30的正投影与阳极242a电连接的第三转接孔K13在衬底基板30的正投影没有交叠)，并通过第二平坦层42进行膜层平坦化处理，可以确保发光区域242b的膜层平坦性，以保证绿色第二发光元件242的开口率和显示效果。
在一些示例性实施方式中，如图11和图12所示，绿色第二发光元件243的阳极243a可以通过一个第三转接孔K13与第一转接线434b电连接，第一转接线434b可以通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。由于绿色第二发光元件243所对应的第一转接孔K11在衬底基板30的正投影与蓝色第二发光元件245的阳极245a在衬底基板30的正投影存在交叠，若绿色第二发光元件243的阳极243a通过该第一转接孔K11与该第二像素电路12直接电连接，会存在绿色第二发光元件243的阳极243a和蓝色第二发光元件245的阳极245a短路的情况，容易造成显示不良。在本示例中，通过沿第二方向F2延伸的第一转接线434b将绿色第二发光元件243的阳极243a的连接位置移动至蓝色第二发光元件245的阳极245a以外的区域(例如，将连接位置移动至靠近红色第二发光元件244的一侧)，以便于绿色第二发光元件243的阳极243a与第二像素电路12进行电连接。在本示例中，蓝色第二发光元件245的阳极245a在衬底基板30的正投影与绿色第二发光元件243的阳极243a在衬底基板30的正投影没有交叠，如此可以规避相邻第二发光元件短路的情况，从而确保显示效果。
在一些示例性实施方式中，如图11和图12所示，绿色第二发光元件241的阳极241a可以通过连接电极433a经由一个第一转接孔K11与对应的一个第二像素电路12电连接，红色第二发光元件244的阳极244a可以通过连接电极433b经由一个第一转接孔K11与对应的一个第二像素电路12电连接，蓝色第二发光元件245的阳极245a可以通过连接电极433c经由一个第一转接孔K11与对应的一个第二像素电路12电连接。
在本示例性实施方式中，在第四子显示区内，存在错位的第二像素电路和第二子发光元件可以通过第一转接线电连接，且第一转接线沿第二方向延伸，可以实现第二子发光元件的阳极与对应的第二像素电路的电连接，并避免第二子发光元件和第三子发光元件的短路风险。存在错位的第二像素电路和第四子发光元件可以通过第二转接线电连接，且第二转接线沿第二方向延伸，可以改善第四子发光元件的开口率损失情况。而且，通过设置第一转接线和第二转接线均沿第二方向延伸，可以给电连接第一像素电路和第一发光元件的第二透明导电线提供排布空间，避免对第二透明导电线的排布产生影响。
下面参照图13和图14，以图13中的绿色第二发光元件251至253、红色第二发光元件254、以及蓝色第二发光元件255为例说明第五子显示区的结构。其中，第二子发光元件以绿色第二发光元件253为例，第三子发光元件以蓝色第二发光元件255为例，第四子发光元件以绿色第二发光元件252为例进行说明。
在一些示例性实施方式中，如图13和图14所示，第二显示区A2的第五子显示区A23的电连接层可以包括：多个连接电极(例如，连接电极435a至435c)、以及多个第三转接线(例如，第二转接线436a和第一转接线436b)。每个连接电极可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接。每个转接线可以通过一个第一转接孔K11与一个第二像素电路12的阳极连接端电连接。由于第五子显示区A23的第一像素电路无需与第一显示区A1的第一发光元件电连接，则无需在第五子显示区A23内排布电连接第一像素电路和第一发光元件的第一透明导电线和第二透明导电线，因此，第五子显示区A23内的第一转接线和第二转接线的延伸方向并不限定， 例如可以沿第一方向F1、第二方向F2、第三方向F3或第四方向F4延伸。
在一些示例性实施方式中，如图13和图14所示，绿色第二发光元件252的阳极252a通过一个第三转接孔与第二转接线436a电连接，第二转接线436a通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。在本示例中，通过沿第二方向F2延伸的第二转接线436a将绿色第二发光元件252的阳极252a的连接位置转移至发光区域252b之外的区域(即，绿色第二发光元件252的发光区域252b在衬底基板30的正投影与阳极252a电连接的第三转接孔K13在衬底基板30的正投影没有交叠)，并通过第二平坦层42进行膜层平坦化处理，可以确保发光区域252b的膜层平坦性，以保证绿色第二发光元件252的开口率和显示效果。
在一些示例性实施方式中，如图13和图14所示，绿色第二发光元件253的阳极253a可以通过一个第三转接孔K13与第一转接线436b电连接，第一转接线436b可以通过一个第一转接孔K11与对应的第二像素电路12的阳极连接端电连接。在本示例中，通过沿第四方向F4延伸的第一转接线436b将绿色第二发光元件253的阳极253a的连接位置移动至蓝色第二发光元件255的阳极255a以外的区域(例如，将连接位置移动至靠近红色第二发光元件254的一侧)，以便于绿色第二发光元件253的阳极253a与第二像素电路12进行电连接。在本示例中，蓝色第二发光元件255的阳极255a在衬底基板30的正投影与绿色第二发光元件253的阳极253a在衬底基板30的正投影没有交叠，如此可以规避相邻第二发光元件短路的情况，从而确保显示效果。
在一些示例性实施方式中，如图13和图14所示，绿色第二发光元件251的阳极251a可以通过连接电极435a经由一个第一转接孔K11与对应的一个第二像素电路12电连接，红色第二发光元件254的阳极254a可以通过连接电极435b经由一个第一转接孔K11与对应的一个第二像素电路12电连接，蓝色第二发光元件255的阳极255a可以通过连接电极435c经由一个第一转接孔K11与对应的一个第二像素电路12电连接。如图14所示，第五子显示区的至少一条转接线可以沿第三方向F3，或者可以先沿第二方向F2延伸再沿第四方向F4延伸。然而，本实施例对此并不限定。
在一些示例中，第一方向F1与第二方向F2水平竖直垂直相交，第三方 向F3和第四方向F4垂直相交，第三方向F3位于第一方向F1和第二方向F2之间，第三方向F3和第一方向F1之间沿顺时针方向的夹角约为45度。然而，本实施例对此并不限定。例如，第三方向F3和第一方向F1之间沿顺时针方向的夹角可以约为30度至60度。
在本示例性实施方式中，在第五子显示区内，存在错位的第二像素电路和第二子发光元件可以通过第一转接线电连接，存在错位的第二像素电路和第四子发光元件可以通过第二转接线电连接，且第一转接线和第二转接线的延伸方向并不限定，可以实现第二发光元件的阳极与对应的第二像素电路的电连接，并改善第四子发光元件的开口率损失情况以及第二子发光元件和第三子发光元件的短路风险。
图15为图1中的第二显示区的第三子显示区的另一局部平面示意图。图16A为图15中沿P-P’方向的局部剖面示意图。图16B为图15中沿Q-Q’方向的局部剖面示意图。在一些示例性实施方式中，如图15至图16B所示，第二显示区A2的电连接层可以包括：多个转接线(例如，包括第一转接线432b、第二转接线432a)、多条第一透明导电线以及多条第二透明导电线。以红色第二发光元件234为例，红色第二发光元件234的阳极234a通过开设在第一平坦层41和第二平坦层42的转接孔与一个第二像素电路12的阳极连接端直接电连接，无需通过连接电极转接。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例性实施方式中，像素电路可以包括多个晶体管和至少一个存储电容。晶体管可以包括有源层、栅极、第一极和第二极。存储电容可以包括第一电容极板和第二电容极板。晶体管的栅极与存储电容的其中一个电容极板可以为同层结构，晶体管的第一极和第二极可以为同层结构。
下面以第二显示区的像素电路为图2所示的7T1C结构为例对像素电路层的结构进行举例说明。在本示例中，第一晶体管即为前述的阈值补偿晶体管T2。
图17为本公开至少一实施例的一个像素电路的俯视示意图。图18为图17中沿R-R’方向的局部剖面示意图。图19为本公开至少一实施例的第二显 示区的局部俯视示意图。图20为本公开至少一实施例的形成半导体层后的第二显示区的俯视示意图。图21为本公开至少一实施例的形成第一导电层后的第二显示区的俯视示意图。图22为本公开至少一实施例的形成第二导电层后的第二显示区的俯视示意图。图23为本公开至少一实施例的形成第三绝缘层后的第二显示区的俯视示意图。图24为本公开至少一实施例的形成第三导电层后的第二显示区的俯视示意图。图25为本公开至少一实施例的形成第四绝缘层后的第二显示区的俯视示意图。图19至图25中示意了四个像素电路的平面结构。
在一些示例性实施方式中，如图17至图25所示，在垂直于显示基板的方向上，第二显示区A2的像素电路层可以包括：设置在衬底基板30上的半导体层、第一导电层、第二导电层、第三导电层以及第四导电层。半导体层和第一导电层之间设置第一绝缘层31，第一导电层和第二导电层之间设置第二绝缘层32，第二导电层和第三导电层之间设置第三绝缘层33，第三导电层和第四导电层之间设置第四绝缘层34。在一些示例中，第一绝缘层31至第四绝缘层34可以均为无机绝缘层。第一导电层还可以称为第一栅金属层，第二导电层还可以称为第二栅金属层，第三导电层还可以称为第一源漏金属层，第四导电层还可以称为第二源漏金属层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图17至图25所示，第二显示区A2的半导体层至少包括：像素电路的多个晶体管的有源层。第一导电层至少包括：像素电路的多个晶体管的栅极和存储电容的第一电容极板、扫描线、发光控制线、以及第一复位控制线。第二导电层至少包括：像素电路的存储电容的第二电容极板、第一初始信号线以及第二初始信号线。第三导电层至少包括：像素电路的至少一个晶体管的第一极和第二极。第四导电层至少包括：数据线和第一电源线。
下面参照图17至图25以及图6至图14对显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和 喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层。
在一些示例性实施方式中，形成半导体层可以包括：在衬底基板30上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，在第二显示区形成半导体层。如图20所示，第二显示区A1的半导体层至少包括：像素电路的多个晶体管的有源层，例如，第一复位晶体管T1的有源层T10、阈值补偿晶体管T2的有源层T20、驱动晶体管T3的有源层T30、数据写入晶体管T4的有源层T40、第一发光控制晶体管T5的有源层T50、第二发光控制晶体管T6的有源层T60以及第二复位晶体管T7的有源层T70。一个像素电路的七个晶体管的有源层T10至T70可以为相互连接的一体结构。
在一些示例性实施方式中，半导体层的材料例如可以包括多晶硅。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。多个掺杂区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。在一些示例中，有源层的掺杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
在一些示例性实施方式中，衬底基板30可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如衬底基板可以为柔性基板。
(2)、形成第一导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板30上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层的第一绝缘层31，以及设置在第一绝缘层31上的第一导 电层。如图21所示，第二显示区A2的第一导电层至少包括：像素电路的多个晶体管的栅极(例如，第一复位晶体管T1的栅极T13、阈值补偿晶体管T2的第一栅极T23a和第二栅极T23b、驱动晶体管T3的栅极T33、数据写入晶体管T4的栅极T43、第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63以及第二复位晶体管T7的栅极T73)、像素电路的存储电容Cst的第一电容极板C1-1、多条扫描线(例如，扫描线GL(i-1)和GL(i))、多条发光控制线(例如，发光控制线EML(i-1)和EML(i))、以及多条第一复位控制线(例如，第一复位控制线RST1(i-1)和RST1(i))。其中，i为整数。
在一些示例性实施方式中，如图21所示，第i行像素电路的存储电容Cst的第一电容极板C1-1与驱动晶体管T3的栅极T33可以为一体结构。第i行像素电路的第二复位晶体管T7的栅极T73、第一复位控制线RST1(i)、以及第i+1行像素电路的第一复位晶体管T1’的栅极可以为一体结构。第i行像素电路的第一复位晶体管T1的栅极T13、第i-1行像素电路的第二复位晶体管的栅极、以及第一复位控制线RST1(i-1)可以为一体结构。第i行像素电路的阈值补偿晶体管T2的第一栅极T23a和第二栅极T23b、数据写入晶体管T4de栅极T43以及扫描线GL(i)可以为一体结构。第i行像素电路的第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63以及发光控制线EML(i)可以为一体结构。然而，本实施例对此并不限定。
(3)、形成第二导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板30上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第二绝缘层32，以及设置在第二绝缘层32上的第二导电层。如图22所示，第二显示区A2的第二导电层至少包括：像素电路的存储电容Cst的第二电容极板C1-2、多条第一初始信号线(例如，第一初始信号线INIT1(i-1)、INIT1(i)及INIT1(i+1))以及多条第二初始信号线(例如，第二初始信号线INIT2(i-1)及INIT2(i))。
在一些示例性实施方式中，多条第一初始信号线和多条第二初始信号线均沿第一方向F1延伸。例如，第一初始信号线INIT1(i)在衬底基板30的正 投影位于扫描线GL(i)和第一复位控制线RST1(i-1)在衬底基板30的正投影之间。第二初始信号线INIT2(i)在衬底基板30的正投影位于发光控制线EML(i)和第一复位控制线RST1(i)在衬底基板30的正投影之间。
在一些示例性实施方式中，如图17所示，以第一初始信号线INIT1(i)为例，第一初始信号线INIT1(i)包括本体部61和伸出部62。本体部61沿第一方向F1延伸，伸出部62沿第二方向F2从本体部61延伸出来。第一初始信号线INIT1(i)的伸出部62沿第二方向F2向靠近扫描线GL(i)的一侧延伸。阈值补偿晶体管T2(即第一晶体管)的有源层T20可以包括第一沟道区、第二沟道区和第三沟道区。第三沟道区连接在第一沟道区和第二沟道区之间。第一沟道区沿第二方向F2延伸，第二沟道区沿第一方向F1延伸，第三沟道区为连接第一沟道区和第二沟道区的拐角，第三沟道区在衬底基板30的正投影可以为倒L形。阈值补偿晶体管T2的第一栅极T23a在衬底基板30的正投影可以覆盖第一沟道区在衬底基板30的正投影，第二栅极T23b在衬底基板30的正投影可以覆盖第二沟道区在衬底基板30的正投影。在本示例中，第一沟道区和第二沟道区为有源层和栅极的重叠区域；第三沟道区与栅极不存在交叠，而是作为第一沟道区和第二沟道区之间的连接区。第一初始信号线INIT1(i)的伸出部62在衬底基板30的正投影与阈值补偿晶体管T2的第三沟道区在衬底基板30的正投影存在交叠。即，第一初始信号线INIT1(i)的伸出部62可以遮挡阈值补偿晶体管T2的有源层的第三沟道区。由于第一初始信号线可以提供固定电压信号，可以实现对阈值补偿晶体管T2的有源层的有效屏蔽，以保证阈值补偿晶体管T2的稳定性。利用第一初始信号线遮挡阈值补偿晶体管的有源层可以节省空间，而且可以实现高分辨率和高画质的像素设计需求，从而提高显示基板的性能。
(4)、形成第三绝缘层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层33。如图23所示，第二显示区A2的第三绝缘层33开设有多个过孔，多个过孔可以至少包括：第一过孔H1至第九过孔H9。其中，第一过孔H1至第六过孔H6内的第三绝缘层33、第二绝缘层32和第一绝缘层31被去掉，暴露出 半导体层的表面。第七过孔H7内的第三绝缘层33和第二绝缘层32被去掉，暴露出第一导电层的表面。第八过孔H8和第九过孔H9内的第三绝缘层33被去掉，暴露出第二导电层的表面。
(5)、形成第三导电层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第三绝缘层33上形成第三导电层。如图24所示，第二显示区A2的第三导电层至少包括：像素电路的多个晶体管的第一极和第二极(例如，第一复位晶体管T1的第一极T11、阈值补偿晶体管T2的第一极T21、数据写入晶体管T4的第一极T41、第一发光控制晶体管T5的第一极T51、第二发光控制晶体管T6的第二极T62以及第二复位晶体管T7的第一极T71)。
在一些示例性实施方式中，如图24所示，第一复位晶体管T1的第一极T11可以通过第一过孔H1与第一复位晶体管T1的有源层T10的第一掺杂区电连接，还可以通过第八过孔H8与第一初始信号线INIT1(i)电连接。阈值补偿晶体管T2的第一极T21可以通过第二过孔H2与阈值补偿晶体管T2的有源层的第二掺杂区电连接，还可以通过第七过孔H7与驱动晶体管T3的栅极T33电连接。数据写入晶体管T4的第一极T41可以通过第三过孔H3与数据写入晶体管T4的有源层T40的第一掺杂区电连接。第二发光控制晶体管T6的第二极T62可以通过第四过孔H4与第二发光控制晶体管T6的有源层T60的第二掺杂区电连接。第一发光控制晶体管T5的第一极T51可以通过第五过孔H5与第一发光控制晶体管T5的有源层T50的第一掺杂区电连接。第二复位晶体管T7的第一极T71可以通过第六过孔H6与第二复位晶体管T7的有源层T70的第一掺杂区电连接，还可以通过第九过孔H9与第二初始信号线INIT2(i)电连接。
(6)、形成第四绝缘层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成第四绝缘层34。如图25所示，第二显示区A2的第四绝缘层34开设有多个过孔，例如多个过孔可以包括：第十过孔H10至第十三过孔H13。第十过孔H10至第十三过 孔H13内的第四绝缘层34被去掉，暴露出第三导电层的表面。
(7)、形成第四导电层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，在第四绝缘层34上形成第四导电层。如图19所示，第二显示区A2的第四导电层至少包括：阳极连接端(例如，阳极连接端36)、多条数据线(例如，数据线DL(j)和DL(j+1))和多条第一电源线(例如，第一电源线PL1(j)和PL1(j+1))。数据线和第一电源线均沿第二方向F2延伸，且数据线和第一电源线沿第一方向F1间隔设置。其中，j为整数。
在一些示例性实施方式中，数据线DL(j)可以通过第十过孔H10与数据写入晶体管T4的第一极T41电连接。第一电源线PL1(j)可以通过第十二过孔H12和第十三过孔H13与第一发光控制晶体管T5的第一极T51电连接。阳极连接端36可以通过第十一过孔H11与第二发光控制晶体管T6的第二极T62电连接。像素电路的阳极连接端36后续可以与发光元件电连接。
至此，制备完成第二显示区A2的像素电路层。第一显示区A1可以包括衬底基板30以及叠设在衬底基板30的第一绝缘层31、第二绝缘层32、第三绝缘层33和第四绝缘层34。
(8)、形成第一平坦层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成第一平坦层41。如图8所示，第一平坦层41开设有多个第一转接孔K11和多个第二转接孔K12。第一转接孔K11内的第一平坦层41被去掉，可以暴露出第二像素电路的阳极连接端，第二转接孔K12内的第一平坦层41被去掉，可以暴露出第一像素电路的阳极连接端。
(9)、形成电连接层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成电连接层。如图9、图12和图14所示，电连接层可以包括：多个连接电极、多个转接线(例 如，第一转接线、第二转接线)、多个第一透明导电线以及多个第二透明导电线。
(10)、形成第二平坦层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上涂覆第二平坦薄膜，通过图案化工艺对第二平坦薄膜进行图案化，形成第二平坦层41。如图10所示，第二平坦层42开设有多个第三转接孔K13。第三转接孔K13内的第二平坦层42被去掉，暴露出电连接层的表面。
(11)、形成阳极层、像素定义层、有机发光层以及阴极层。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。随后，在形成前述图案的衬底基底30上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层54。像素定义层54形成有暴露出阳极层的多个像素开口。随后，在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极层53，阴极层53分别与有机发光层和第二电源线电连接。在一些示例中，在阴极层上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层31、第二绝缘层32、第三绝缘层33和第四绝缘层34可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层31和第二绝缘层32可以称之为栅绝缘(GI)层，第三绝缘层33和第四绝缘层34可以称之为层间绝缘(ILD)层。第一平坦层41和第二平坦层42可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层54可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极层可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一 些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，在如图15和图16所示的示例中，可以在形成第二平坦层的过程中开设暴露出第四导电层的转接孔，使得无需通过转接线与第二像素电路电连接的第二发光元件可以直接通过贯穿第一平坦层和第二平坦层的转接孔与第二像素电路的阳极连接端电连接，而无需通过连接电极进行连接。然而，本实施例对此并不限定。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与已有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图26为本公开至少一实施例的显示基板的另一示意图。在一些示例性实施方式中，如图26所示，第一显示区A1可以为半圆形。第一显示区A1可以包括：两个沿第一方向F1依次排布的第一子显示区A11a和A11b、以及位于两个第一子显示区A11a和A11b之间的第二子显示区A12a。第二显示区A2可以包括：两个第三子显示区A21a和A21b、一个第四子显示区A22a以及第五子显示区A23。第三子显示区A21a在第一方向F1上与第一子显示区A11a相邻，第三子显示区A21a内的第一像素电路与第一子显示区A11a内的第一发光元件电连接。第三子显示区A21b在第一方向F1上与第一子显示区A11b相邻，第三子显示区A21b内的第一像素电路与第一子显示区A11b内的第一发光元件电连接。第四子显示区A22a与第二子显示区A12a相邻，第四子显示区A22a内的第一像素电路与第二子显示区A12a内的第一发光元件电连接。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示面板，包括如上所述的显示基板。图27为本公开至少一实施例的显示面板的示意图。如图27所示，本实施例的显示面板91可以包括显示基板910。显示基板910可以如前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括：如上所述的显示面板、以及设置在显示面板非显示面一侧的感光传感器。感光传感器在显示面板的 正投影与显示基板的第一显示区存在交叠。
图28为本公开至少一实施例的显示装置的示意图。如图28所示，本实施例提供一种显示装置，包括：显示面板91以及位于远离显示面板91的显示结构层的出光侧的感光传感器92(即感光传感器92位于显示面板91的非显示面一侧)。感光传感器92在显示面板91上的正投影与第一显示区A1存在交叠。
在一些示例性实施方式中，显示面板91可以为柔性OLED显示面板、QLED显示面板、Micro-LED显示面板、或者Mini-LED显示面板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (21)

  1. 一种显示基板，包括第一显示区和至少部分围绕所述第一显示区的第二显示区，其中，所述显示基板包括：
    衬底基板；
    像素电路，位于所述第二显示区的衬底基板上，所述像素电路包括交替排布的第一像素电路和第二像素电路；
    发光元件，位于所述像素电路远离所述衬底基板的一侧，所述发光元件包括位于所述第一显示区的第一发光元件和位于所述第二显示区的第二子发光元件和第三子发光元件，所述第一像素电路通过至少部分透明导电线与所述第一发光元件电连接；
    所述第二像素电路通过第一转接孔与所述第二子发光元件电连接，所述第一转接孔在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影存在交叠。
  2. 根据权利要求1所述的显示基板，其中，所述第三子发光元件与所述第二子发光元件相邻设置。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二显示区内的至少一个第二像素电路通过所述第一转接孔与第一转接线电连接，所述第一转接线与所述第二子发光元件电连接，所述第一转接线与所述第二子发光元件的连接位置在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影不存在交叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一转接线与所述像素电路之间设置有第一平坦层，所述第一转接线通过所述第一平坦层开设的第一转接孔与所述第二像素电路电连接；
    所述第一转接线与所述发光元件之间设置有第二平坦层，所述第一转接线通过所述第二平坦层开设的第三转接孔与所述第二子发光元件电连接；
    所述第三转接孔在所述衬底基板的正投影与所述第三子发光元件在所述衬底基板的正投影不存在交叠。
  5. 根据权利要求3或4所述的显示基板，其中，所述第二显示区包括： 至少一个第三子显示区，所述第三子显示区内的第一像素电路通过第一透明导电线与所述第一显示区内的第一发光元件电连接，所述第一透明导电线至少沿第一方向延伸；
    所述第三子显示区内的至少一个第二像素电路通过沿所述第一方向延伸的第一转接线与所述第二子发光元件电连接。
  6. 根据权利要求5所述的显示基板，其中，所述第二显示区包括：至少一个第四子显示区，所述第四子显示区内的第一像素电路通过第二透明导电线与所述第一显示区内的第一发光元件电连接，所述第二透明导电线至少沿第二方向延伸，所述第二方向与所述第一方向交叉；
    所述第四子显示区内的至少一个第二像素电路通过沿所述第二方向延伸的第一转接线与所述第二子发光元件电连接。
  7. 根据权利要求3至6中任一项所述的显示基板，其中，所述第二显示区包括：第五子显示区；所述第五子显示区内的第一像素电路为无效像素电路；
    所述第五子显示区内的至少一个第二像素电路通过沿任一方向延伸的第一转接线与所述第二子发光元件电连接。
  8. 根据权利要求6所述的显示基板，其中，所述第一显示区包括：至少一个第一子显示区和至少一个第二子显示区；
    所述第三子显示区在所述第一方向与至少一个第一子显示区相邻，所述第四子显示区在所述第二方向与至少一个第二子显示区相邻；
    所述第一透明导电线和第二透明导电线的长度取值范围大致相同。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述发光元件还包括位于所述第二显示区的第四子发光元件；
    所述第二显示区内的至少一个第二像素电路通过第一转接孔与所述第四子发光元件电连接，所述第一转接孔在所述衬底基板的正投影与所述第四子发光元件的发光区域在所述衬底基板的正投影存在交叠。
  10. 根据权利要求9所述的显示基板，其中，所述第二像素电路通过所述第一转接孔与第二转接线电连接，所述第二转接线与所述第四子发光元件 电连接；
    所述第二转接线与所述第四子发光元件的连接位置在所述衬底基板的正投影与所述第四子发光元件的发光区域在所述衬底基板的正投影不存在交叠。
  11. 根据权利要求10所述的显示基板，其中，所述第二显示区至少包括：第三子显示区和第四子显示区；
    所述第三子显示区内的第一像素电路通过第一透明导电线与所述第一显示区内的第一发光元件电连接，所述第一透明导电线至少沿第一方向延伸；
    所述第四子显示区内的第一像素电路通过第二透明导电线与所述第一显示区内的第一发光元件电连接，所述第二透明导电线至少沿第二方向延伸，所述第二方向与所述第一方向交叉；
    所述第三子显示区内的至少一个第二像素电路通过沿所述第一方向延伸的第二转接线与所述第四子发光元件电连接；
    所述第四子显示区内的至少一个第二像素电路通过沿所述第二方向延伸的第二转接线与所述第四子发光元件电连接。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，在所述第二显示区内，所述第一像素电路和第二像素电路在第一方向和第二方向上均交替排布；所述第一方向与第二方向交叉。
  13. 根据权利要求12所述的显示基板，其中，在所述第一方向上，四列第二像素电路和一列第一像素电路交替排布，在所述第二方向上，四行第二像素电路和一行第一像素电路交替排布。
  14. 根据权利要求1至13中任一项所述的显示基板，其中，所述像素电路包括：驱动晶体管以及第一晶体管；所述第一晶体管的第一极与所述驱动晶体管的栅极电连接；
    所述第一晶体管为双栅晶体管；
    所述像素电路与第一初始信号线电连接，所述第一初始信号线在所述衬底基板的正投影与所述第一晶体管的有源层的沟道区在所述衬底基板的正投影存在交叠。
  15. 根据权利要求14所述的显示基板，其中，所述第一晶体管的有源层 的沟道区包括：第一沟道区、第二沟道区和第三沟道区，所述第三沟道区位于所述第一沟道区和第二沟道区之间；所述第一晶体管的第一栅极在所述衬底基板的正投影覆盖所述第一沟道区在所述衬底基板的正投影，所述第一晶体管的第二栅极在所述衬底基板的正投影覆盖所述第二沟道区在所述衬底基板的正投影；
    所述第一初始信号线在所述衬底基板的正投影与所述第一晶体管的有源层的第三沟道区在所述衬底基板的正投影存在交叠。
  16. 根据权利要求15所述的显示基板，其中，所述第三沟道区在所述衬底基板的正投影为倒L形。
  17. 根据权利要求14至16中任一项所述的显示基板，其中，所述第一初始信号线包括：沿第一方向延伸的本体部和沿第二方向从所述本体部延伸出的伸出部；所述第一方向与第二方向交叉；
    所述伸出部在所述衬底基板的正投影与所述第一晶体管的有源层的沟道区在所述衬底基板的正投影存在交叠。
  18. 根据权利要求14至17中任一项所述的显示基板，其中，所述像素电路包括多个晶体管以及至少一个存储电容；所述晶体管包括：有源层、栅极、第一极和第二极，所述存储电容包括第一电容极板和第二电容极板，所述晶体管的栅极与存储电容的其中一个电容极板为同层结构，所述晶体管的第一极和第二极为同层结构。
  19. 根据权利要求18所述的显示基板，其中，所述第一初始信号线与所述像素电路的存储电容的另一个电容极板为同层结构。
  20. 一种显示面板，包括如权利要求1至19中任一项所述的显示基板。
  21. 一种显示装置，包括如权利要求20所述的显示面板，以及设置于所述显示面板非显示面一侧的感光传感器，所述感光传感器在所述显示面板的正投影与所述显示面板的显示基板的第一显示区存在交叠。
PCT/CN2022/078071 2022-02-25 2022-02-25 显示基板、显示面板及显示装置 WO2023159509A1 (zh)

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