WO2024021001A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024021001A1
WO2024021001A1 PCT/CN2022/108886 CN2022108886W WO2024021001A1 WO 2024021001 A1 WO2024021001 A1 WO 2024021001A1 CN 2022108886 W CN2022108886 W CN 2022108886W WO 2024021001 A1 WO2024021001 A1 WO 2024021001A1
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Prior art keywords
gate
transistor
electrode
pixel
sub
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PCT/CN2022/108886
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English (en)
French (fr)
Inventor
丛宁
范龙飞
李大超
张粲
玄明花
陈小川
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22952452.5A priority Critical patent/EP4418249A1/en
Priority to CN202280002467.2A priority patent/CN117796176A/zh
Priority to PCT/CN2022/108886 priority patent/WO2024021001A1/zh
Publication of WO2024021001A1 publication Critical patent/WO2024021001A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • Micro Organic Light-Emitting Diode is a micro-display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also can prepare structures such as pixel drive circuits on silicon-based substrates, which is beneficial to reducing system volume and achieving lightweight. Silicon-based OLEDs are manufactured using the mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process and have the advantages of small size, high resolution (Pixels Per Inch, referred to as PPI), and high refresh rate.
  • CMOS Complementary Metal Oxide Semiconductor
  • embodiments of the present disclosure provide a display substrate, including a display area and a frame area.
  • the display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns.
  • the sub-pixels include a plurality of sub-pixels along a pixel row.
  • the first area, the gap area and the second area are arranged in sequence; at least one sub-pixel includes a pixel driving circuit, a first scanning signal line and a second scanning signal line, and the pixel driving circuit includes at least a first transistor and a second transistor.
  • the first transistor at least includes a first gate electrode, a first active layer and a first electrode of the first transistor and a second electrode of the first transistor; the second transistor at least includes a second gate electrode and a second active layer; source layer, the third transistor at least includes a third gate electrode and a third active layer; the first active layer is provided in the first region, and the second active layer and the third active layer are provided In the second area, the second active layer is disposed on one side of the third active layer in the pixel column direction; the first scanning signal line passes through the first gate via hole and the first gate electrode.
  • the second electrode of the first transistor is connected to the second gate electrode through a second gate via hole
  • the second scanning signal line is connected to the third gate electrode through a third gate via hole
  • the The first gate via hole, the second gate via hole and the third gate via hole are provided in the gap area.
  • the first area has a first width
  • the second area has a second width
  • the gap area has a third width
  • the third width is less than Or equal to 0.5*first width
  • the third width is less than or equal to 0.5*second width.
  • the first gate electrodes of two adjacent sub-pixels on the pixel row are an integral structure connected to each other, and the third gate electrodes of two adjacent sub-pixels on the pixel row are connected to each other.
  • One-piece structure is
  • the first gate electrode of the integrated structure is connected to the first scanning signal line through two first gate vias
  • the third gate electrode of the integrated structure is connected to the first scanning signal line through two third gate vias.
  • the hole is connected to the second scanning signal line.
  • the first transistor, the second transistor and the third transistor of two adjacent sub-pixels on the pixel row are mirror symmetrical with respect to a pixel center line, and the pixel center line is A straight line located between two adjacent sub-pixels on the pixel row and extending along the pixel column direction.
  • the first gate electrode in at least one sub-pixel, includes a first gate body portion and a first gate connection portion that are connected to each other, and the first gate connection portion is disposed in the gap region, so The first scanning signal line is connected to the first gate connection portion through the first gate via hole.
  • the second gate electrode in at least one sub-pixel, includes a second gate body portion and a second gate connection portion that are connected to each other, and the second gate connection portion is disposed in the gap region, so The second electrode of the first transistor is connected to the second gate connection portion through the second gate via hole.
  • the third gate electrode in at least one sub-pixel, includes a third gate body portion and a third gate connection portion that are connected to each other, and the third gate connection portion is disposed in the gap region, so The second scanning signal line is connected to the third gate connection portion through the third gate via hole.
  • the first gate electrode in at least one sub-pixel, includes a first gate body portion and a first gate connection portion connected to each other, the first gate connection portion is provided with the first gate body portion Near the side of the third gate electrode, the third gate electrode includes a third gate main body portion and a third gate connecting portion connected to each other, and the third gate connecting portion is disposed close to the third gate main body portion.
  • the first gate connecting portion and the third gate connecting portion are offset in the pixel column direction.
  • the first gate body portion and the first gate connecting portion are flush with an edge on a side away from the second transistor, and the third gate body portion and the third gate connecting portion are close to the third gate connecting portion.
  • the edges on one side of the two transistors are flush.
  • the second gate electrode in at least one sub-pixel, includes a second gate body portion and a second gate connection portion that are connected to each other, and the second gate connection portion is disposed in the gap region, so The edge of the second gate body portion and the second gate connection portion close to the third transistor are flush.
  • the shape of the first scanning signal line and the second scanning signal line is a line shape with a main part extending along the pixel row direction, and the first scanning signal line is on the display substrate.
  • the orthographic projection on the plane at least partially overlaps the orthographic projection of the first gate electrode and the third gate electrode on the plane of the display substrate, and the orthogonal projection of the second scanning signal line on the plane of the display substrate. The projection at least partially overlaps an orthographic projection of the first gate electrode and the third gate electrode on the plane of the display substrate.
  • the second transistor further includes a first electrode of the second transistor and a second electrode of the second transistor
  • the third transistor further includes a first electrode of the third transistor and a third electrode of the third transistor.
  • the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first plate and a second plate, and the first plate is on the display substrate.
  • the orthographic projection on the plane at least partially overlaps the orthographic projection of the second electrode plate on the plane of the display substrate, and the first electrode plate is connected to the second electrode of the first transistor through a connecting electrode, so The second plate is connected to the first power line.
  • At least one sub-pixel further includes a contact electrode, the contact electrode is disposed in the first region, and the contact electrode is disposed on one side of the first active layer in the pixel column direction.
  • At least one sub-pixel further includes a bias voltage line, the bias voltage line is connected to the contact electrode through a via hole, and the bias voltage line is in a positive direction on the plane of the display substrate.
  • the projection at least partially overlaps an orthographic projection of the second gate electrode on the plane of the display substrate.
  • the contact electrode has a shape extending along the pixel column direction
  • the bias voltage line has a shape extending along the pixel row direction.
  • Line shape, one side or both sides of the bias voltage line in the pixel column direction are connected to a bias connection line, and the orthographic projection of the bias connection line on the plane of the display substrate is in line with the contact electrode.
  • Orthographic projections on the plane of the display substrate at least partially overlap, and the bias connection line is connected to the contact electrode through a via hole.
  • the bias voltage line and the bias connection line are an integral structure connected to each other.
  • the frame area at least includes a light emitting control transistor, a gate electrode of the light emitting control transistor is connected to a light emitting control line, a first electrode of the light emitting control transistor is connected to a frame power supply lead, and the light emitting control transistor
  • the second electrode of the transistor is connected to a light-emitting voltage line, the light-emitting voltage line is connected to the first electrodes of the second transistors of multiple sub-pixels in a pixel row, and the frame power supply lead is connected to the first power line.
  • the display substrate at least includes a first conductive layer and a second conductive layer sequentially disposed on a silicon substrate, and the silicon substrate at least includes the first conductive layer.
  • active layer, a second active layer and a third active layer the first conductive layer at least includes the first gate electrode, the second gate electrode and the third gate electrode, the second conductive layer at least includes the the first scanning signal line and the second scanning signal line.
  • the display substrate further includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a third conductive layer disposed on a side of the second conductive layer away from the silicon substrate.
  • the third conductive layer at least includes a data signal line and a reference signal line
  • the fourth conductive layer at least includes a light-emitting voltage line
  • the sixth conductive layer at least includes a first line of a storage capacitor.
  • the seventh conductive layer at least includes a second plate of the storage capacitor
  • the eighth conductive layer at least includes an anode connecting electrode and a first power line.
  • embodiments of the present disclosure provide a display device, including the aforementioned display substrate.
  • an embodiment of the present disclosure provides a method for preparing a display substrate.
  • the display substrate includes a display area and a frame area.
  • the display area includes a plurality of sub-pixels forming pixel rows and pixel columns.
  • the sub-pixels include A first area, a gap area and a second area arranged sequentially along the pixel row direction; at least one sub-pixel includes a pixel driving circuit, a first scanning signal line and a second scanning signal line, the pixel driving circuit including at least a first transistor , a second transistor and a third transistor, the first scanning signal line is configured to control the conduction or disconnection of the first transistor, the second scanning signal line is configured to control the conduction of the second transistor.
  • the first transistor at least includes a first gate electrode, a first active layer and a first electrode of the first transistor and a second electrode of the first transistor, and the second transistor at least includes a second gate electrode and a second active layer, the third transistor includes at least a third gate electrode and a third active layer;
  • the preparation method includes:
  • the first transistor, the second transistor, the third transistor, the first scanning signal line and the second scanning signal line are formed, the first active layer is provided in the first region, the second active layer and The third active layer is disposed in the second region, and the second active layer is disposed on one side of the third active layer in the pixel column direction; the first gate electrode is connected to the third active layer through a first gate via hole.
  • a scanning signal line is connected, the second gate electrode is connected to the second electrode of the first transistor through a second gate via hole, and the third gate electrode is connected to the second scanning signal line through a third gate via hole,
  • the first gate via hole, the second gate via hole and the third gate via hole are provided in the gap area.
  • Figure 1 is a schematic structural diagram of a silicon-based OLED display device
  • Figure 2 is a schematic plan view of a silicon-based OLED display device
  • Figure 3 is a schematic cross-sectional structural diagram of a silicon-based OLED display device
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • Figure 5 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 6 is a schematic diagram after the first conductive layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram after forming a second insulating layer pattern according to an embodiment of the present disclosure.
  • FIGS. 8A and 8B are schematic diagrams after forming a second conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram after forming a third insulating layer pattern according to an embodiment of the present disclosure.
  • FIGS. 10A and 10B are schematic diagrams after forming a third conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram after forming a fourth insulating layer pattern according to an embodiment of the present disclosure.
  • 12A and 12B are schematic diagrams after forming a fourth conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram after the fifth insulating layer pattern is formed according to an embodiment of the present disclosure.
  • FIGS. 14A and 14B are schematic diagrams after the fifth conductive layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 15 is a schematic diagram after forming a sixth insulating layer pattern according to an embodiment of the present disclosure.
  • 16A and 16B are schematic diagrams after forming a sixth conductive layer pattern according to an embodiment of the present disclosure.
  • 17A and 17B are schematic diagrams after forming a seventh conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 18 is a schematic diagram after forming an eighth insulating layer pattern according to an embodiment of the present disclosure.
  • 19A and 19B are schematic diagrams after forming an eighth conductive layer pattern according to an embodiment of the present disclosure.
  • FIG. 20 is an equivalent circuit diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • 103 Light-emitting structural layer
  • 104 First encapsulation layer
  • 105 Color film structural layer
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels and the number of sub-pixels in each pixel in the display device are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • first pole in order to distinguish the two poles of the transistor except the gate electrode, one pole is directly described as the first pole and the other pole is the second pole.
  • the first pole can be the drain electrode and the second pole can be the source electrode.
  • the first electrode can be the source electrode and the second electrode can be the drain electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the "same layer arrangement" used refers to structures formed by patterning two (or more than two) structures through the same patterning process, and their materials may be the same or different.
  • the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a silicon-based OLED display device.
  • the silicon-based OLED display device may include a timing controller, a data signal driver, a scanning signal driver, and a pixel array.
  • the pixel array may include a plurality of scanning signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn) and multiple sub-pixels Pxij.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver. Provided to scan signal driver.
  • the data signal driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data signal driver may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in sub-pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be configured in the form of a shift register, and may generate the scan in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal.
  • Signal, m can be a natural number.
  • the sub-pixel array may include a plurality of pixel sub-PXij. Each pixel sub-PXij can be connected to the corresponding data signal line and the corresponding scanning signal line, and i and j can be natural numbers.
  • the sub-pixel PXij may refer to a sub-pixel in which the transistor is connected to the i-th scanning signal line and connected to the j-th data signal line.
  • Figure 2 is a schematic plan view of a silicon-based OLED display device.
  • the display device may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, a third sub-pixel that emits light of a second color. The second sub-pixel P2 and the third sub-pixel P3 that emits light of the third color.
  • the three sub-pixels each include a pixel drive circuit and a light-emitting device.
  • the pixel drive circuit in the sub-pixel is connected to the scanning signal line and the data signal line respectively.
  • the pixel drive circuit It is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the display light-emitting device.
  • the display light-emitting device in the sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the display light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel emitting red (R) light
  • the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light
  • the third sub-pixel P3 It can be a green sub-pixel that emits green (G) light.
  • the shape of the sub-pixels may be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons and other polygons, and three sub-pixels may be Arrangement in horizontal juxtaposition, vertical juxtaposition, Z-shaped arrangement, etc. is not limited in this disclosure.
  • the pixel unit may include four sub-pixels, which is not limited in this disclosure.
  • FIG. 3 is a schematic cross-sectional structural diagram of a silicon-based OLED display device, illustrating a structure that uses white light + color film to achieve full color.
  • a silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 provided on the silicon substrate 101, a light-emitting structure layer 103 provided on the side of the driving circuit layer 102 away from the silicon substrate 101, and The light-emitting structural layer 103 is located on the first encapsulation layer 104 on the side away from the silicon substrate 101 , the color filter structural layer 105 is disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101 , and the color filter structural layer 105 is disposed on the side away from the silicon substrate 101 the second encapsulation layer 106, and the cover layer 107 provided on the side of the second encapsulation layer 106 away from the silicon substrate 101.
  • the silicon-based OLED display device may include other film layers, which is not limited in this disclosure
  • the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI, Silicon-On-Insulator) substrate.
  • the driving circuit layer 102 can be prepared on the silicon substrate 101 through a silicon semiconductor process (such as a CMOS process).
  • the driving circuit layer 102 can include a plurality of circuit units.
  • the circuit units can at least include pixel driving circuits.
  • the pixel driving circuits are respectively connected to the scanning signal lines and The data signal lines are connected, and the pixel driving circuit may include multiple transistors and storage capacitors. Only one transistor is used as an example in FIG. 3 .
  • the transistor may include a gate electrode G, a first electrode S, and a second electrode D.
  • the gate electrode G, the first electrode S, and the second electrode D may be connected to the gate electrode G, the first electrode S, and the second electrode D through a tungsten metal-filled via hole (ie, a tungsten via hole, W-via), respectively.
  • a tungsten metal-filled via hole ie, a tungsten via hole, W-via
  • connection electrodes are connected, and can be connected to other electrical structures (such as wiring, etc.) through the connection electrodes.
  • the light-emitting structure layer 103 may include a plurality of light-emitting devices.
  • the light-emitting device may at least include an anode, an organic light-emitting layer, and a cathode.
  • the anode may be connected to the second electrode D of the transistor through a connecting electrode, and the organic light-emitting layer may be connected to the anode.
  • connection, the cathode is connected to the organic light-emitting layer, the cathode is connected to the second power line, and the organic light-emitting layer emits light driven by the anode and the cathode.
  • the organic light-emitting layer may include an light-emitting layer (EML for short), and any one of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML light-emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • EIL electron injection layer
  • the organic light-emitting layers of all sub-pixels may be a common layer connected together.
  • the first encapsulation layer 104 and the second encapsulation layer 106 can adopt a thin film encapsulation (TFE) method, which can ensure that external water vapor cannot enter the light-emitting structure layer, and the cover layer 107 can adopt glass. Or use plastic colorless polyimide with flexible properties.
  • TFE thin film encapsulation
  • the color filter structure layer 105 may include a black matrix (BM) and a color filter (CF).
  • the color filters are respectively provided in red sub-pixels, green sub-pixels and blue sub-pixels to emit light.
  • the white light emitted by the device is filtered into red (R) light, green (G) light and blue (B) light, and the black matrix can be located between adjacent color filters.
  • Exemplary embodiments of the present disclosure provide a display substrate, including a display area and a frame area.
  • the display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns.
  • the sub-pixels include a display substrate along a pixel row direction.
  • the first area, the gap area and the second area are arranged in sequence; at least one sub-pixel includes a pixel driving circuit, a first scanning signal line and a second scanning signal line, and the pixel driving circuit includes at least a first transistor, a second transistor and a third transistor, the first scan signal line is configured to control the conduction or disconnection of the first transistor, and the second scan signal line is configured to control the conduction or disconnection of the second transistor;
  • the first transistor at least includes a first gate electrode, a first active layer, a first electrode of the first transistor, and a second electrode of the first transistor.
  • the second transistor at least includes a second gate electrode and a second active layer.
  • the third transistor at least includes a third gate electrode and a third active layer; the first active layer is provided in the first region, and the second active layer and the third active layer are provided in In the second area, the second active layer is disposed on one side of the third active layer in the pixel column direction; the first scanning signal line is connected to the first gate electrode through a first gate via hole. , the second electrode of the first transistor is connected to the second gate electrode through a second gate via hole, and the second scanning signal line is connected to the third gate electrode through a third gate via hole.
  • a gate via hole, a second gate via hole and a third gate via hole are provided in the gap area.
  • the first area has a first width
  • the second area has a second width
  • the gap area has a third width
  • the third width is less than Or equal to 0.5*first width
  • the third width is less than or equal to 0.5*second width.
  • the first gate electrodes of two adjacent sub-pixels on the pixel row are an integral structure connected to each other, and the third gate electrodes of two adjacent sub-pixels on the pixel row are connected to each other.
  • One-piece structure is
  • the first gate electrode of the integrated structure is connected to the first scanning signal line through two first gate vias
  • the third gate electrode of the integrated structure is connected to the first scanning signal line through two third gate vias.
  • the hole is connected to the second scanning signal line.
  • the first transistor, the second transistor and the third transistor of two adjacent sub-pixels on the pixel row are mirror symmetrical with respect to a pixel center line, and the pixel center line is A straight line located between two adjacent sub-pixels on the pixel row and extending along the pixel column direction.
  • the second transistor further includes a first electrode of the second transistor and a second electrode of the second transistor
  • the third transistor further includes a first electrode of the third transistor and a third electrode of the third transistor.
  • Exemplary embodiments of the present disclosure provide an ultra-high PPI display substrate. By adopting minimal designs such as gate electrode overlapping positions being set at the same interval, common gate electrodes, common drain electrodes, sub-pixel flipping, etc., minimizing design can maximize the performance of the display substrate. It reduces the PPI of the display substrate and achieves the highest PPI design of Real RGB silicon-based OLED in the industry.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • the pixel driving circuit according to the exemplary embodiment of the present disclosure may have a 3T1C structure, including 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C.
  • the pixel driving circuit Connected to seven signal lines (the first scanning signal line S1, the second scanning signal line S1, the data signal line D, the reference signal line VE, the first power supply line VDD and the light-emitting voltage line VF), the first node N1 and the second Node N2 is a meeting point representing relevant electrical connections in the circuit diagram.
  • a first end of the storage capacitor C may be connected to the first node N1, and a second end of the storage capacitor C may be connected to the first power line VDD.
  • the gate electrode of the first transistor T1 is connected to the first scanning signal line S1
  • the first electrode of the first transistor T1 is connected to the data signal line D
  • the second electrode of the first transistor T1 is connected to the first node. N1 connection.
  • the gate electrode of the second transistor T2 is connected to the first node N1
  • the first electrode of the second transistor T2 is connected to the light-emitting voltage line VF
  • the second electrode of the second transistor T2 is connected to the second node N2.
  • the gate electrode of the third transistor T3 is connected to the second scanning signal line S2, the first electrode of the third transistor T3 is connected to the reference signal line VE, and the second electrode of the third transistor T3 is connected to the second node. N2 connection.
  • the first pole of the light-emitting device XL is connected to the second node N2, and the second pole of the light-emitting device XL is connected to the second power line VSS.
  • the first transistor T1 is configured to receive the data voltage transmitted by the data signal line D under the control of the signal of the first scanning signal line S1, store the data voltage into the storage capacitor C, and transmit it to the second transistor T1.
  • the gate electrode of transistor T2 provides the data voltage.
  • the second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode to drive the display light-emitting device XL to emit light.
  • the third transistor T3 is configured to receive the reference voltage transmitted by the reference signal line VE under the control of the signal of the second scanning signal line S2, and provide the reference voltage to the second node N2.
  • the storage capacitor C is configured to store the potential of the gate electrode of the second transistor T2, and the light-emitting device XL is configured to emit light with corresponding brightness in response to the current of the second electrode of the second transistor T2.
  • the signal of the first power line VDD may be a continuously provided high-level signal
  • the signal of the light-emitting voltage line VF may be a voltage signal output by the light-emitting control transistor
  • the signal of the second power line VSS may be a continuously provided high-level signal. provided low level signal.
  • the first, second, and third transistors T1, T2, and T3 may be P-type transistors. In another exemplary embodiment, the first, second, and third transistors T1, T2, and T3 may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In yet another exemplary embodiment, the first, second, and third transistors T1, T2, and T3 may include P-type transistors and N-type transistors.
  • the first transistor T1 and the third transistor T3 may be P-type metal oxide semiconductor transistors (PMOS), and the second transistor T2 may be an N-type metal oxide semiconductor transistor (NMOS).
  • the light-emitting device XL may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels in a pixel unit.
  • the display substrate may at least include a silicon substrate, a driving circuit layer provided on the silicon substrate, a light-emitting structure layer provided on a side of the driving circuit layer away from the silicon substrate, and a An encapsulation layer on the side of the light-emitting structure layer away from the silicon substrate.
  • the driving circuit layer of the display substrate may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns.
  • the first sub-pixel P1 and the second sub-pixel are sequentially arranged along the first direction D1.
  • P2 and the third sub-pixel P3 form a pixel unit.
  • the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 each include a pixel driving circuit, a first scanning signal line 26 and a second scanning signal line 27.
  • the pixel driving circuit may include at least a first transistor T1, a second transistor T1 and a second scanning signal line 27.
  • the transistor T2 and the third transistor T3, the first scanning signal line 26 is configured to control the conduction or disconnection of the first transistor T1, and the second scanning signal line 27 is configured to control the conduction or disconnection of the second transistor T2.
  • the first transistor T1 may include a first active layer 1 , a first gate electrode 11 , a first electrode (twenty-first connection electrode) 21 of the first transistor T1 and The second electrode (twenty-second connection electrode) 22 of the first transistor T1.
  • the second transistor T2 may include a second active layer 2, a second gate electrode 12, a first electrode (twenty-third connection electrode) 23 of the second transistor T2, and a second electrode (twenty-fourth connection electrode) of the second transistor T2. Connect the electrode)24.
  • the third transistor T3 may include a third active layer 3, a third gate electrode 13, a first electrode (the twenty-fifth connection electrode) 25 of the third transistor T3, and a second electrode (the twenty-fourth connection electrode) of the third transistor T3. Connect the electrode)24.
  • each of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 may include a first area q1, a gap area q3 and a second area q2 sequentially arranged along the pixel row direction.
  • the gap area Area q3 may be provided between the first area q1 and the second area q2.
  • the first sub-pixel P1 and the third sub-pixel P3 may include a first area q1, a gap area q3 and a second area q2 sequentially arranged along the first direction D1
  • the second sub-pixel P2 may include an area along the first direction D1.
  • the first area q1, the gap area q3 and the second area q2 are arranged in the opposite direction of D1.
  • the setting positions of the three areas in the first sub-pixel P1 and the second sub-pixel P2 are mirror symmetrical with respect to the pixel center line A.
  • the second area The arrangement positions of the three areas in the sub-pixel P2 and the third sub-pixel P3 are mirror symmetrical with respect to the pixel center line A.
  • the pixel center line A is located between two adjacent sub-pixels in the first direction D1 and along the second direction. The straight line extended by D2.
  • the first area q1 may have a first width
  • the second area q2 may have a second width
  • the gap area q3 may have a third width
  • the third width may be less than or equal to 0.5*first width
  • the third width can be less than or equal to 0.5*second width.
  • the first active layer 1 may be disposed in the first area q1, the second active layer 2 and the third active layer 3 may be disposed in the second area q2, and the second active layer 1 may be disposed in the first area q1.
  • the active layer 2 may be disposed on one side of the third active layer 3 in the second direction D2, and no active layer is disposed in the gap area q3.
  • the gap area q3 serves as an active layer in the first area q1 and an active layer in the second area q2.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are formed in an "L" shape.
  • the first transistor T1 and the third transistor T3 can be arranged sequentially along the first direction D1.
  • the second transistor T2 and the third transistor T3 are arranged in an "L” shape.
  • the three transistors T3 may be arranged sequentially along the second direction D2.
  • the first scanning signal line 26 is connected to the first gate electrode 11 of the first transistor T1 through the first gate via K1, and the second electrode 22 of the first transistor passes through the second gate via K1.
  • the gate via K2 is connected to the second gate electrode 12 of the second transistor T2.
  • the second scanning signal line 27 is connected to the third gate electrode of the third transistor T3 through the third gate via K3.
  • the first gate via K1 The second gate via K2 and the third gate via K3 can both be provided in the gap area q3, forming a structure in which the overlapping positions of the gate electrodes in the sub-pixel are located in the same gap area.
  • the first electrode 21 of the first transistor T1 may be connected to the data signal line
  • the first electrode 23 of the second transistor T2 may be connected to the light-emitting voltage line
  • the first electrode 25 of the third transistor T3 may be connected to the data signal line.
  • the second electrode 24 of the second transistor T2 and the second electrode 24 of the third transistor T3 can be arranged on the same layer and form an integrated structure connected to each other through the same patterning process to form a common drain electrode in the sub-pixel. structure.
  • the first transistor T1, the second transistor T2 and the third transistor T3 of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A, forming a sub-pixel with respect to the pixel center line A.
  • the first gate electrodes 11 of two adjacent sub-pixels in the first direction D1 can be arranged on the same layer and form an interconnected integrated structure through the same patterning process.
  • the third gate electrode 13 of the pixel can be arranged on the same layer, and formed into an integrated structure connected to each other through the same patterning process, forming a structure shared by adjacent sub-pixel gate electrodes.
  • the third gate electrode 13 of the first sub-pixel P1 and the third gate electrode 13 of the second sub-pixel P2 are an integral structure connected to each other
  • the first gate electrode 11 of the second sub-pixel P2 and the third sub-pixel P3 are The first gate electrode 11 is an integral structure connected to each other.
  • the first gate electrode 11 of the first transistor T1 may include a first gate body portion 11-1 and a first gate connection portion 11-2. 2 can be disposed on the side of the first gate body part 11-1 close to the third transistor T3, and connected to the first gate body part 11-1, so that the first gate connection part 11-2 is located in the gap area q3, and the first scan
  • the signal line 26 may be connected to the first gate connection part 11-2 through the first gate via K1.
  • the second gate electrode 12 of the second transistor T2 may include a second gate body portion 12-1 and a second gate connection portion 12-2. 2 may be disposed on a side of the second gate body part 12-1 close to the first transistor T1, and connected to the second gate body part 12-1, so that the second gate connection part 12-2 is located in the gap area q3, and the first transistor
  • the second electrode 22 is connected to the second gate connection portion 12-2 through the second gate via K2.
  • the third gate electrode 13 of the third transistor T3 may include a third gate body portion 13-1 and a third gate connection portion 13-2. 2 may be disposed on a side of the third gate body part 13-1 close to the first transistor T1, and connected to the third gate body part 13-1, so that the third gate connection part 13-2 is located in the gap area q3, and the second scan
  • the signal line 27 may be connected to the third gate connection part 13-2 through the third gate via K3.
  • the first gate connection part 11-2 and the third gate connection part 13-2 are disposed offset in the second direction D2, with an interval therebetween.
  • edges of the first gate body portion 11 - 1 and the first gate connection portion 11 - 2 on a side away from the second transistor T2 may be flush.
  • edges of the third gate body portion 13-1 and the third gate connection portion 13-2 close to the second transistor T2 may be flush.
  • the shape of the first scanning signal line 26 and the second scanning signal line 27 may be a line shape with a main body portion extending along the first direction D1, and the first scanning signal line 26 is in a plane on the display substrate.
  • the orthographic projection at least partially overlaps with the orthographic projection of the first gate electrode 11 and the third gate electrode 13 on the plane of the display substrate, and the orthographic projection of the second scanning signal line 27 on the plane of the display substrate overlaps with the orthographic projection of the first gate electrode 11 and the third gate electrode 13 on the plane of the display substrate. Orthographic projections of the third gate electrode 13 on the plane of the display substrate at least partially overlap.
  • At least one sub-pixel may further include a contact electrode 4.
  • the contact electrode 4 may be disposed in the first region q1.
  • the contact electrode 4 may be disposed on one side of the first active layer 1 in the second direction D2.
  • the electrode 4 is configured to perform a low-voltage bias on the silicon substrate, thereby avoiding changes in the threshold voltage caused by parasitic effects such as the silicon substrate bias effect and improving the stability of the circuit. .
  • At least one sub-pixel may further include a bias voltage line 28 , and an orthographic projection of the bias voltage line 28 on the plane of the display substrate is consistent with the second gate electrode 12 of the second transistor T2 on the display substrate. Orthographic projections on the plane at least partially overlap.
  • the bias voltage line 28 can be connected to the contact electrode 4 through a via hole, so that the bias voltage line 28 provides a low voltage to the contact electrode 4 .
  • the shape of the contact electrode 4 may be a line shape with the main body portion extending along the second direction D2, and the shape of the bias voltage line 28 may be a shape such that the main body portion extends along the first direction D1.
  • one or both sides of the bias voltage line 28 in the second direction D2 may be connected to a bias connection line 29 , and the shape of the bias connection line 29 may be a strip shape with the main part extending along the second direction D2 , the orthographic projection of the bias connection line 29 on the plane of the display substrate at least partially overlaps with the orthographic projection of the contact electrode 4 on the plane of the display substrate, and the bias connection line 29 is connected to the contact electrode 4 through a plurality of via holes.
  • the bias voltage line 28 and the bias connection line 29 may be arranged on the same layer and formed into an integrated structure connected to each other through the same patterning process.
  • the driving circuit layer of the display substrate may include a first conductive layer and a second conductive layer sequentially disposed on a silicon substrate, and the silicon substrate may include at least a first conductive layer.
  • the source layer 1, the second active layer 2, the third active layer 3 and the contact electrode 4, the first conductive layer may at least include a first gate electrode 11, a second gate electrode 12 and a third gate electrode 13, the second conductive layer
  • the layer may include at least a first electrode 21 of the first transistor T1, a second electrode 22 of the first transistor T1, a first electrode 23 of the second transistor T2, a second electrode of the second transistor T2 (also a third electrode of the third transistor T3). (two poles) 24, the first pole 25 of the third transistor T3, the first scanning signal line 26, the second scanning signal line 27, the bias voltage line 28 and the bias connection line 29.
  • the driving circuit layer may further include a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer disposed on a side of the second conductive layer away from the silicon substrate, and
  • the eighth conductive layer the third conductive layer may at least include a data signal line and a reference signal line
  • the fourth conductive layer may at least include a light-emitting voltage line
  • the fifth conductive layer may at least include a plurality of connection electrodes
  • the sixth conductive layer may at least include The first plate of the storage capacitor
  • the seventh conductive layer may include at least the second plate of the storage capacitor
  • the eighth conductive layer may include at least the anode connection electrode and the first power line.
  • the following is an exemplary description through the preparation process of the display device.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display device.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display device may include the following steps.
  • forming the silicon substrate may include: providing a silicon substrate of P-type silicon material, such as P-type single crystal silicon, and the P-type single crystal silicon may serve as a channel region of the N-type transistor.
  • the silicon substrate can be made of N-type silicon material as the channel region of the P-type transistor, which is not limited in this disclosure.
  • forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate, first patterning the polysilicon film through a patterning process, and forming a first insulating film covering the silicon substrate. layer and the polysilicon layer pattern provided on the first insulating layer, and then use the polysilicon layer pattern as a shield to perform a doping process to form the first conductive layer and active layer pattern, as shown in Figure 6.
  • the doping process may adopt an N-type doping process
  • the doping element may be boron, etc.
  • the formed active layer pattern may include at least the first active layer 1 and the second active layer 1 of the first transistor T1.
  • the first conductive layer pattern formed by the second active layer 2 of the transistor T2, the third active layer 3 of the third transistor T3, and the contact electrode 4 may at least include the first gate electrode 11 of the first transistor T1, the first gate electrode 11 of the second transistor T1, and the contact electrode 4 of the third transistor T3.
  • the doping process can use an ion implantation process. Since the polysilicon layer is a semiconductor material, during the ion implantation process, on the one hand, the polysilicon layer can be used as a shield, so that ions can be implanted into both sides of the polysilicon layer to form The first and second regions of multiple transistors can achieve self-alignment. On the other hand, the polysilicon layer can be doped at the same time, so that the polysilicon layer with higher resistance becomes the first conductive layer with lower resistance, forming a plurality of transistors. gate electrode. By using polysilicon material as the first conductive layer, the present disclosure can save process costs and reduce process difficulty.
  • the first active layer 1 and the contact electrode 4 in each sub-pixel may be disposed in the first region q1
  • the second active layer 2 and the third active layer 3 may be disposed in the second region q2
  • no active layer is provided in the gap area q3
  • the gap area q3 serves as a gap area between the active layer in the first area q1 and the active layer in the second area q2.
  • the first active layer 1 , the second active layer 2 , the third active layer 3 and the contact electrode 4 may have a strip shape extending along the second direction D2.
  • the contact electrode 4 may be disposed on one side of the first active layer 1 in the second direction D2, and the second active layer 2 may be disposed on one side of the third active layer 3 in the second direction D2.
  • the third active layer 3 may be disposed on one side of the first active layer 1 in the first direction D1 or on the opposite side of the first direction D1, and the second active layer 2 may be disposed on the first side of the contact electrode 4
  • the first active layer 1 and the third active layer 3 may be located on the side of the sub-pixel in the second direction D2, contacting the electrode 4 and the second active layer 3.
  • Layer 2 may be located on the other side of the second direction D2 of the sub-pixel, and the first active layer 1, the second active layer 2 and the third active layer 3 in each sub-pixel form an "L" shaped layout.
  • the present disclosure facilitates the realization of the second area of the second active layer 2 and the third active layer 3 by arranging the second active layer 2 and the third active layer 3 on the same side of the first direction D1 of the sub-pixel.
  • the connection of the second area can not only simplify the structure, but also reduce the area occupied by the pixel drive circuit, thereby achieving the resolution of the display product.
  • the active layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the active layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A. It may be basically the same.
  • the pixel center line A is a straight line located between two adjacent sub-pixels in the first direction D1 and extending along the second direction D2.
  • the active layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the active layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • first gate electrode 11 and the third gate electrode 13 in each sub-pixel may be sequentially disposed along the first direction D1, and the second gate electrode 12 and the third gate electrode 13 may be arranged along the second direction.
  • D2 is set in sequence, forming an "L" shaped layout in the sub-pixels.
  • the first conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the first conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the first conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the first conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • the first gate electrodes 11 of two adjacent sub-pixels in the first direction D1 may be an integral structure connected to each other.
  • the third gate electrodes 13 of the two sub-pixels may be an integral structure connected to each other.
  • the third gate electrode 13 of the first sub-pixel P1 and the second sub-pixel P2 may be an integral structure connected to each other.
  • the first gate electrode 11 of the second sub-pixel P2 and the third sub-pixel P3 may be an integral structure connected to each other.
  • the present disclosure by arranging the first gate electrodes of two adjacent sub-pixels into an integral structure connected to each other, and arranging the third gate electrodes of two adjacent sub-pixels into an integrated structure connected to each other, it is possible to meet the design rules on the premise of satisfying the design rules.
  • the arrangement of the pixel driving circuit is made more compact, which helps to improve the resolution of the display device.
  • the first gate electrode 11 of the first transistor T1 may include a first gate body part 11-1 and a first gate connection part 11-2.
  • the shape of the first gate body part 11-1 may be a rectangle, and the area where the first gate body part 11-1 overlaps with the first active layer 1 may serve as the first channel region of the first active layer 1.
  • the first region 1-1 of an active layer 1 may be located on one side of the first channel region in the second direction D2 (the side away from the contact electrode 4), and the second region 1-2 of the first active layer 1 may be It is located on the side opposite to the second direction D2 of the first channel region (the side close to the contact electrode 4).
  • the first gate connection part 11-2 may be rectangular in shape, may be disposed on a side of the first gate body part 11-1 close to the third transistor T3, and be connected to the first gate body part 11-1, so that the first gate connection part 11-2 may be in a rectangular shape.
  • the gate connection portion 11-2 is located in the gap region q3, and the first gate connection portion 11-2 is configured to be connected to a first scanning signal line formed subsequently through a first gate via hole.
  • the second gate electrode 12 of the second transistor T2 may include a second gate body portion 12-1 and a second gate connection portion 12-2.
  • the shape of the second gate body part 12-1 may be a rectangular shape, and the area where the second gate body part 12-1 overlaps with the second active layer 2 may serve as the second channel region of the second active layer 2.
  • the first region 2-1 of the second active layer 2 may be located on the side opposite to the second direction D2 of the second channel region (the side away from the third active layer 3).
  • the second region 2-2 may be located on one side of the second channel region in the second direction D2 (the side close to the third active layer 3).
  • the shape of the second gate connecting part 12-2 may be rectangular, may be provided on the side of the second gate main body part 12-1 close to the contact electrode 4, and be connected to the second gate main body part 12-1, so that the second gate connecting part 12-2 may be in a rectangular shape.
  • the connection portion 12-2 is located in the gap region q3, and the second gate connection portion 12-2 is configured to be connected to the second electrode of the subsequently formed first transistor through the second gate via hole.
  • the third gate electrode 13 of the third transistor T3 may include a third gate body portion 13-1 and a third gate connection portion 13-2.
  • the shape of the third gate body part 13-1 may be a rectangular shape, and the area where the third gate body part 13-1 overlaps the third active layer 3 may serve as the third channel region of the third active layer 3.
  • the first region 3-1 of the third active layer 3 may be located on one side of the third channel region in the second direction D2 (the side away from the second active layer 2), and the second region 3 of the third active layer 3 -2 may be located on the side opposite to the second direction D2 of the third channel region (the side close to the second active layer 2).
  • the third gate connection part 13-2 may be rectangular in shape, may be disposed on a side of the third gate main body part 13-1 close to the first transistor T1, and be connected to the third gate main body part 13-1, so that the third gate connection part 13-2 may be in a rectangular shape.
  • the gate connection part 13-2 is located in the gap area q3, and the third gate connection part 13-2 is configured to be connected to the second scanning signal line formed later through the third gate via hole.
  • first gate connection portion 11-2, the second gate connection portion 12-2, and the third gate connection portion 13-2 are all located in the gap region q3, and are respectively configured to communicate with the subsequently formed third gate connection portion
  • the first scanning signal line, the second electrode of the first transistor and the second scanning signal line are connected so that the overlapping positions of the three gate electrodes are located in the same spacing area, which not only makes the pixel driving circuit possible while meeting the design rules.
  • the arrangement is more compact, which helps to improve the resolution of the display device, and the gate via holes will not affect the electrical performance of the transistor, improving the working reliability of the pixel drive circuit.
  • first gate connection portion 11-2 and the third gate connection portion 13-2 located in the gap region q3 may be offset in the second direction D2, and the first gate connection portion 11-2 and the third gate connection portion 13-2 may be offset in the second direction D2. There is a gap between the three gate connecting parts 13-2.
  • the first gate connection part 11-2 may be located at one end of the gap region q3 in the second direction D2, and the third gate connection part 13-2 may be located at one end of the gap region q3 in the opposite direction to the second direction D2,
  • the edges of the first gate body part 11-1 and the first gate connection part 11-2 away from the second transistor T2 may be flush, and the third gate body part 13-1 and the third gate connection part 13-2 are close to the second transistor T2.
  • the edge on one side of transistor T2 can be flush.
  • the first gate connection part 11-2 may be located at one end of the gap region q3 in the opposite direction to the second direction D2, and the third gate connection part 13-2 may be located at one end of the gap region q3 in the second direction D2.
  • the edges of the first gate body portion 11-1 and the first gate connection portion 11-2 close to the second transistor T2 can be flush, and the third gate body portion 13-1 and the third gate connection portion 13-2 are far away from the second transistor T2.
  • the edges on one side of the two transistors T2 can be flush.
  • the contact electrode 4 may be an N-type doped region (N+), and the contact electrode 4 is configured to perform a low-voltage bias on the silicon substrate, thereby avoiding threshold voltage changes caused by parasitic effects such as silicon substrate bias effects. , improve the stability of the circuit.
  • N+ N-type doped region
  • the contact electrode 4 is configured to perform a low-voltage bias on the silicon substrate, thereby avoiding threshold voltage changes caused by parasitic effects such as silicon substrate bias effects. , improve the stability of the circuit.
  • the devices between sub-pixels can be electrically isolated, the parasitic effects between the devices can be reduced, and the stability of the circuit can be improved.
  • forming the second insulating layer pattern may include: depositing a second insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the second insulating film through a patterning process, and forming a pattern covering the first conductive layer.
  • the second insulating layer is provided with multiple via holes, as shown in Figure 7.
  • the plurality of via holes in each sub-pixel may include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, and a third via hole V4.
  • the orthographic projection of the first via hole V1 on the silicon substrate may be located within the range of the orthogonal projection of the first region of the first active layer 1 on the silicon substrate.
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the first region of the first active layer 1, and the first via hole V1 is configured to allow the subsequently formed twenty-first connection electrode to pass through the via hole.
  • the hole is connected to the first area of the first active layer 1 .
  • the orthographic projection of the second via hole V2 on the silicon substrate may be located within the range of the orthogonal projection of the second region of the first active layer 1 on the silicon substrate.
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the second region of the first active layer 1, and the second via hole V2 is configured to allow the subsequently formed twenty-second connection electrode to pass through the via hole.
  • the hole is connected to the second area of the first active layer 1 .
  • the orthographic projection of the third via hole V3 on the silicon substrate may be located within the range of the orthogonal projection of the first region of the second active layer 2 on the silicon substrate.
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the first region of the second active layer 2, and the third via hole V3 is configured to allow the subsequently formed twenty-third connection electrode to pass through the via hole.
  • the hole is connected to the first area of the second active layer 2 .
  • the orthographic projection of the fourth via hole V4 on the silicon substrate may be located within the range of the orthogonal projection of the second region of the second active layer 2 on the silicon substrate.
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the second region of the second active layer 2, and the fourth via hole V4 is configured to allow the subsequently formed twenty-fourth connection electrode to pass through the via hole.
  • the hole is connected to the second area of the second active layer 2 .
  • the orthographic projection of the fifth via hole V5 on the silicon substrate may be located within the range of the orthogonal projection of the first region of the third active layer 3 on the silicon substrate, and the orthogonal projection of the fifth via hole V5 on the silicon substrate
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the first region of the third active layer 3, and the third via hole V3 is configured to allow the subsequently formed twenty-fifth connection electrode to pass through the via hole.
  • the hole is connected to the first area of the third active layer 3 .
  • the orthographic projection of the sixth via hole V6 on the silicon substrate may be located within the range of the orthogonal projection of the second region of the third active layer 3 on the silicon substrate.
  • the first insulating layer and the second insulating layer are etched away to expose the surface of the second region of the third active layer 3, and the sixth via hole V6 is configured to allow the subsequently formed twenty-fourth connection electrode to pass through the via hole.
  • the hole is connected to the second area of the third active layer 3 .
  • the orthographic projection of the seventh via hole V7 on the silicon substrate may be located within the range of the orthographic projection of the first gate connection portion 11 - 2 of the first gate electrode 11 on the silicon substrate.
  • the second insulating layer in the hole V7 is etched away, exposing the surface of the first gate connection portion 11-2.
  • the seventh via hole V7 is configured to allow the subsequently formed first scanning signal line to pass through the via hole and the first gate connecting portion 11-2.
  • the gate connecting portion 11-2 is connected, and the seventh via V7 can be used as the first gate via of the present disclosure.
  • first gate electrodes 11 of two adjacent sub-pixels in the first direction D1 are an integral structure connected to each other, two seventh via holes are provided in the area where the first gate electrode 11 of the integral structure is located.
  • V7 first gate via hole
  • the two seventh via holes V7 are respectively located at both ends of the first gate electrode 11 of the integrated structure in the first direction D1, so that the first gate electrode 11 of the same integrated structure can pass through the two second gate electrodes 11.
  • the seven vias V7 are connected to the first scanning signal line formed later.
  • the orthographic projection of the eighth via hole V8 on the silicon substrate may be located within the range of the orthographic projection of the second gate connection portion 12 - 2 of the second gate electrode 12 on the silicon substrate.
  • the second insulating layer in the hole V8 is etched away, exposing the surface of the second gate connection portion 12-2, and the eighth via hole V8 is configured to allow the subsequently formed twenty-second connection electrode to pass through the via hole and connect to the second gate connecting portion 12-2.
  • the second gate connecting portion 12-2 is connected, and the eighth via V8 can be used as the second gate via of the present disclosure.
  • the orthographic projection of the ninth via hole V9 on the silicon substrate may be located within the range of the orthographic projection of the third gate connection portion 13 - 2 of the third gate electrode 13 on the silicon substrate.
  • the second insulating layer in the hole V9 is etched away, exposing the surface of the third gate connection portion 13-2.
  • the ninth via hole V9 is configured to allow the subsequently formed second scanning signal line to pass through the via hole and the third gate connecting portion 13-2.
  • the gate connecting portion 13-2 is connected, and the ninth via V9 can be used as the third gate via of the present disclosure.
  • the third gate electrodes 13 of two adjacent sub-pixels in the first direction D1 are an integral structure connected to each other, two ninth via holes are provided in the area where the third gate electrode 13 of the integral structure is located.
  • V9 third gate via hole
  • the two ninth via holes V9 are respectively located at both ends of the third gate electrode 13 of the integrated structure in the first direction D1, so that the third gate electrode 13 of the same integrated structure can pass through the two third gate electrodes 13.
  • the nine vias V9 are connected to the second scanning signal line formed later.
  • the orthographic projection of the tenth via hole V10 on the silicon substrate may be located within the range of the orthographic projection of the contact electrode 4 on the silicon substrate, and the first insulating layer and the second insulating layer in the tenth via hole V10 The insulating layer is etched away to expose the surface of the contact electrode 4, and the tenth via hole V10 is configured so that the subsequently formed reference signal line is connected to the contact electrode 4 through the via hole.
  • forming the second conductive layer pattern may include: depositing a second conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the second conductive film through a patterning process, and forming a second conductive layer on the second insulating layer.
  • a second conductive layer pattern is formed, as shown in Figures 8A and 8B.
  • Figure 8B is a schematic diagram of the second conductive layer in Figure 8A.
  • the second conductive layer may be referred to as a first metal (Metal1) layer.
  • the second conductive layer pattern in each sub-pixel may include at least: a twenty-first connection electrode 21, a twenty-second connection electrode 22, a twenty-third connection electrode 23, a twenty-fourth connection electrode The electrode 24, the first scanning signal line 26, the second scanning signal line 27, the bias voltage line 28 and the bias connection line 29.
  • the shape of the twenty-first connection electrode 21 may be a rectangular shape, and the twenty-first connection electrode 21 may be connected to the first region of the first active layer through the first via hole V1.
  • One connection electrode 21 may serve as the first electrode of the first transistor T1, and the twenty-first connection electrode 21 is configured to be connected to a subsequently formed data signal line.
  • the shape of the twenty-second connection electrode 22 may be an “L” shape, and the first end of the twenty-second connection electrode 22 may be connected to the second end of the first active layer through the second via hole V2. area connection, the second end of the twenty-second connection electrode 22 is bent and extended toward the direction of the second gate electrode 12, and is connected to the second gate connection portion 12-2 of the second gate electrode 12 through the eighth via hole V8. Connection, the twenty-second connection electrode 22 can be used as the second electrode of the first transistor T1, realizing the connection between the second electrode of the first transistor T1 and the second gate electrode 12 of the second transistor T2.
  • the shape of the twenty-third connection electrode 23 may be a strip shape with a main body portion extending along the second direction D2, and the first end of the twenty-third connection electrode 23 may be connected to the third via hole V3 through the third via hole V3.
  • the first area of the second active layer is connected, and the second end of the twenty-third connection electrode 23 extends to the middle position of the second gate electrode 12 along the second direction D2.
  • the twenty-third connection electrode 23 can serve as the second The first pole of the transistor T2, the twenty-third connection electrode 23, is configured to be connected to the thirty-second connection electrode formed subsequently.
  • the shape of the twenty-fourth connection electrode 24 may be a rectangular shape, and the first end of the twenty-fourth connection electrode 24 may be connected to the second area of the second active layer 2 through the fourth via hole V4 connection, the second end of the twenty-fourth connection electrode 24 can be connected to the second region of the third active layer 3 through the sixth via hole V6, and the twenty-fourth connection electrode 24 can simultaneously serve as the second end of the second transistor T2.
  • electrode and the second electrode of the third transistor T3, that is, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected to each other.
  • the twenty-fourth connection electrode 24 is configured to be connected to the subsequently formed first electrode. Thirty-three connection electrode connections.
  • the shape of the twenty-fifth connection electrode 25 may be a rectangular shape, and the twenty-fifth connection electrode 25 may be connected to the first region of the third active layer 3 through the fifth via hole V5.
  • the fifteenth connection electrode 25 may serve as the first pole of the third transistor T3, and the twenty-fifth connection electrode 25 is configured to be connected to a subsequently formed reference signal line.
  • the shape of the first scanning signal line 26 may be a line shape with the main body portion extending along the first direction D1, and the first scanning signal line 26 may be connected to the first scanning signal of each sub-pixel through the seventh via V7.
  • the gate connecting portion 11-2 is connected, thus realizing the connection between the first scanning signal line 26 and the first gate electrode 11 of each sub-pixel.
  • the first scanning signal line 26 can provide control of the first transistor T1 of each sub-pixel.
  • the first scan signal indicates that the transistor T1 is turned on or off.
  • first gate via holes V7 are provided in the area where the integrated structure first gate electrodes 11 are located. (first gate via hole), therefore the first scanning signal line 26 is connected to the first gate electrode 11 of the same integrated structure through the two seventh via holes V7.
  • the shape of the second scanning signal line 27 may be a line shape with the main body portion extending along the first direction D1, and the second scanning signal line 27 may be connected to the third through hole V9 of each sub-pixel.
  • the gate connecting portion 13-2 is connected, thus realizing the connection between the second scanning signal line 27 and the third gate electrode 13 of each sub-pixel.
  • the second scanning signal line 27 can provide control of the third transistor T3 of each sub-pixel.
  • the second scan signal indicates that the transistor T3 is turned on or off.
  • the third gate electrodes 13 of two adjacent sub-pixels in the first direction D1 are an integral structure connected to each other, two ninth vias V9 are provided in the area where the third gate electrode 13 of the integral structure is located. (third gate via hole), therefore the second scanning signal line 27 is connected to the third gate electrode 13 of the same integrated structure through the two ninth via holes V9.
  • the orthographic projection of the first scanning signal line 26 on the silicon substrate at least partially overlaps the orthographic projection of the first gate electrode 11 and the third gate electrode 13 on the silicon substrate, and the second scanning signal line 27
  • the orthographic projection on the silicon substrate at least partially overlaps with the orthographic projection of the first gate electrode 11 and the third gate electrode 13 on the silicon substrate.
  • the shape of the bias voltage line 28 of each sub-pixel may be a line shape with the main body portion extending along the first direction D1, and the bias voltage line 28 may be connected to each sub-pixel through the tenth via V10.
  • the contact electrode 4 is connected to realize that the bias voltage line 28 provides low voltage to the contact electrode 4 and performs low-voltage bias on the silicon substrate to achieve electrical isolation of the devices, reduce parasitic effects between devices, and improve the stability of the pixel drive circuit. .
  • the shape of the bias connection line 29 of each sub-pixel may be a strip shape with a main body portion extending along the second direction D2, and may be provided on one side or both sides of the bias voltage line 28 in the second direction D2. side and connected to the bias voltage line 28.
  • the bias connection line 29 of each sub-pixel can be connected to the contact electrode 4 through a plurality of tenth via holes V10 to reduce contact resistance and improve connection reliability.
  • the first scanning signal line 26 may be located on a side close to the twenty-first connection electrode 21
  • the second scanning signal line 27 may be located on a side of the first scanning signal line 26 away from the twenty-first connection electrode 21 . one side.
  • the bias voltage line 28 may be located between the twenty-second connection electrode 22 and the twenty-third connection electrode 23 , and an orthographic projection of the bias voltage line 28 on the silicon substrate is in contact with the second gate electrode 12 The orthographic projections on the silicon substrate at least partially overlap.
  • the width of the bias voltage line 28 may be greater than the width of the first scan signal line 26 , and the width of the bias voltage line 28 may be greater than the width of the second scan signal line 27 to reduce the bias voltage line 28 resistance to improve the uniformity of the power supply voltage.
  • the second conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the second conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the second conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the second conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the third insulating film through a patterning process, and forming a covering second conductive layer pattern.
  • the third insulating layer is provided with multiple via holes, as shown in Figure 9.
  • the plurality of via holes in each sub-pixel may include an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, and a fifteenth via hole V14.
  • Hole V15 may include an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, and a fifteenth via hole V14.
  • the orthographic projection of the eleventh via hole V11 on the silicon substrate may be located within the range of the orthographic projection of the twenty-first connection electrode 21 on the silicon substrate, and the The three insulating layers are etched away to expose the surface of the twenty-first connection electrode 21, and the eleventh via hole V11 is configured so that the subsequently formed data signal line is connected to the twenty-first connection electrode 21 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the silicon substrate may be located within the range of the orthographic projection of the twenty-second connecting electrode 22 on the silicon substrate, and the orthogonal projection of the twelfth via hole V12 on the silicon substrate may be The three insulating layers are etched away to expose the surface of the twenty-second connection electrode 22, and the twelfth via hole V12 is configured to allow the subsequently formed thirty-first connection electrode to communicate with the twenty-second connection electrode through the via hole. 22 connections.
  • the orthographic projection of the thirteenth via hole V13 on the silicon substrate may be located within the range of the orthographic projection of the twenty-third connection electrode 23 on the silicon substrate, and the orthogonal projection of the thirteenth via hole V13 on the silicon substrate
  • the three insulating layers are etched away, exposing the surface of the twenty-third connection electrode 23, and the thirteenth via hole V13 is configured to allow the subsequently formed thirty-second connection electrode to communicate with the twenty-third connection electrode through the via hole. 23 connections.
  • the orthographic projection of the fourteenth via hole V14 on the silicon substrate may be located within the range of the orthographic projection of the twenty-fourth connection electrode 24 on the silicon substrate, and the orthogonal projection of the fourteenth via hole V14 on the silicon substrate
  • the three insulating layers are etched away to expose the surface of the twenty-fourth connection electrode 24.
  • the fourteenth via hole V14 is configured to allow the subsequently formed thirty-third connection electrode to communicate with the twenty-fourth connection electrode through the via hole. 24 connections.
  • the orthographic projection of the fifteenth via hole V15 on the silicon substrate may be located within the range of the orthographic projection of the twenty-fifth connecting electrode 25 on the silicon substrate, and the orthogonal projection of the fifteenth via hole V15 on the silicon substrate
  • the three insulating layers are etched away to expose the surface of the twenty-fifth connection electrode 25, and the fifteenth via hole V15 is configured so that the reference signal line formed later is connected to the twenty-fifth connection electrode 25 through the via hole.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive film on the third insulating layer.
  • a third conductive layer pattern is formed, as shown in Figures 10A and 10B.
  • Figure 10B is a schematic diagram of the third conductive layer in Figure 10A.
  • the third conductive layer may be referred to as a second metal (Metal2) layer.
  • the third conductive layer pattern in each sub-pixel may include at least: a thirty-first connection electrode 31, a thirty-second connection electrode 32, a thirty-third connection electrode 33, a data signal line 34, and Reference signal line 35.
  • the shape of the thirty-first connection electrode 31 may be a strip shape extending along the second direction D2, and the end of the thirty-first connection electrode 31 in the opposite direction of the second direction D2 (near the second The end of the transistor T2) may be connected to the twenty-second connection electrode 22 through the twelfth via V12, and the thirty-first connection electrode 31 is configured to be connected to the forty-first connection electrode formed subsequently.
  • the shape of the thirty-second connection electrode 32 may be a rectangular shape, and the thirty-second connection electrode 32 may be connected to the twenty-third connection electrode 23 through the thirteenth via hole V13.
  • the connection electrode 32 is configured to be connected to a subsequently formed light-emitting voltage line.
  • the shape of the thirty-third connection electrode 33 may be a polygonal shape extending along the second direction D2, and the end of the thirty-third connection electrode 33 in the second direction D2 (near the end of the third transistor T3 end) may be connected to the twenty-fourth connection electrode 24 through the fourteenth via hole V14, and the thirty-third connection electrode 33 is configured to be connected to the forty-second connection electrode formed subsequently.
  • the shape of the data signal line 34 may be a line shape extending along the second direction D2, and the data signal line 34 may be connected to the twenty-first connection electrode 21 through the eleventh via hole V11. Since the twenty-first connection electrode 21 is connected to the first area of the first active layer, the data signal line 34 is realized to write the data signal into the first electrode of the first transistor T1.
  • the shape of the reference signal line 35 may be a line shape extending along the second direction D2, and the reference signal line 35 may be connected to the twenty-fifth connection electrode 25 through the fifteenth via hole V15. Since the twenty-fifth connection electrode 25 is connected to the first region of the third active layer, the reference signal line 35 is implemented to write the reference signal into the first electrode of the third transistor T3.
  • the third conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the third conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the third conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the third conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • Form a fourth insulating layer pattern may include: depositing a fourth insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the fourth insulating film through a patterning process, and forming a covering third conductive layer pattern.
  • the fourth insulating layer is provided with multiple via holes, as shown in Figure 11.
  • the plurality of via holes in each sub-pixel may include: a twenty-first via hole V21, a twenty-second via hole V22, and a twenty-third via hole V23.
  • the orthographic projection of the twenty-first via hole V21 on the silicon substrate may be located within the range of the orthographic projection of the end of the thirty-first connection electrode 31 in the second direction D2 on the silicon substrate.
  • the fourth insulating layer in the twenty-first via hole V21 is etched away, exposing the surface of the thirty-first connection electrode 31, and the twenty-first via hole V21 is configured to allow the subsequently formed forty-first connection electrode to pass through This via hole is connected to the thirty-first connection electrode 31 .
  • the orthographic projection of the twenty-second via hole V22 on the silicon substrate may be located within the range of the orthographic projection of the thirty-second connection electrode 32 on the silicon substrate, within the twenty-second via hole V22
  • the fourth insulating layer is etched away, exposing the surface of the thirty-second connection electrode 32, and the twenty-second via hole V22 is configured to allow the subsequently formed light-emitting voltage line to pass through the via hole and the thirty-second connection electrode 32 connections.
  • the orthographic projection of the twenty-third via hole V23 on the silicon substrate is within the range of the orthographic projection of the end of the thirty-third connection electrode 33 in the opposite direction to the second direction D2 on the silicon substrate.
  • the fourth insulating layer in the twenty-third via hole V23 is etched away, exposing the surface of the thirty-third connection electrode 33, and the twenty-third via hole V23 is configured to enable the subsequently formed forty-second connection
  • the electrode is connected to the 33rd connection electrode 33 through this via hole.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer on the fourth insulating layer.
  • the fourth conductive layer pattern is as shown in Figures 12A and 12B.
  • Figure 12B is a schematic diagram of the fourth conductive layer in Figure 12A.
  • the fourth conductive layer may be referred to as a third metal (Metal3) layer.
  • the fourth conductive layer pattern in each sub-pixel may include at least: a forty-first connection electrode 41, a forty-second connection electrode 42, and a light-emitting voltage line 43.
  • the shape of the forty-first connection electrode 41 may be a "T" shape, and the forty-first connection electrode 41 may be connected to the thirty-first connection electrode 31 through the twenty-first via hole V21.
  • the forty-first connection electrode 41 is configured to be connected to the fifty-first connection electrode formed later.
  • the shape of the forty-second connection electrode 42 may be a "T" shape, and the forty-second connection electrode 42 may be connected to the thirty-third connection electrode 33 through the twenty-third via hole V23.
  • the forty-second connection electrode 42 is configured to be connected to the fifty-second connection electrode formed later.
  • the shape of the light-emitting voltage line 43 may be a line shape with the main body portion extending along the first direction D1, and the light-emitting voltage line 43 may be connected to the thirty-second connection electrode 32 through the twenty-second via hole V22. . Since the light-emitting voltage line 43 is connected to the second electrode of the light-emitting control transistor located in the frame area and is configured to output a light-emitting voltage signal, the thirty-second connection electrode 32 is connected to the twenty-third connection electrode 23 through the via hole. The three connection electrodes 23 are connected to the first region of the second active layer through via holes, thereby enabling the light-emitting voltage line 43 to write the light-emitting voltage signal into the first electrode of the second transistor T2.
  • the fourth conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the fourth conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the fourth conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the fourth conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the fifth insulating film through a patterning process, and forming a covering fourth conductive layer pattern.
  • the fifth insulating layer is provided with multiple via holes, as shown in Figure 13.
  • the plurality of via holes in each sub-pixel may include: a thirty-first via hole V31 and a thirty-second via hole V32.
  • the orthographic projection of the thirty-first via hole V31 on the silicon substrate is within the range of the orthogonal projection of the forty-first connection electrode 41 on the silicon substrate, and the orthogonal projection of the thirty-first via hole V31 on the silicon substrate is
  • the fifth insulating layer is etched away, exposing the surface of the forty-first connection electrode 41, and the thirty-first via hole V31 is configured to allow the subsequently formed fifty-first connection electrode to pass through the via hole and the forty-first connection electrode 41.
  • a connecting electrode 41 is connected.
  • the orthographic projection of the thirty-second via hole V32 on the silicon substrate is within the range of the orthographic projection of the forty-second connection electrode 42 on the silicon substrate, and the orthogonal projection of the thirty-second via hole V32 is
  • the fifth insulating layer is etched away to expose the surface of the 42nd connection electrode 42, and the 32nd via hole V32 is configured to allow the subsequently formed 52nd connection electrode to pass through the via hole and the 42nd connection electrode 42.
  • the connection electrode 41 is connected.
  • a plurality of thirty-first via holes V31 and a plurality of thirty-second via holes V32 may be sequentially disposed along the first direction D1 to reduce contact resistance and improve connection reliability.
  • forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the fifth conductive film through a patterning process, and forming a fifth conductive layer on the fifth insulating layer.
  • the pattern of the fifth conductive layer is as shown in Figures 14A and 14B.
  • Figure 14B is a schematic diagram of the fifth conductive layer in Figure 14A.
  • the fifth conductive layer may be called a fourth metal (Metal4) layer.
  • the fifth conductive layer pattern in each sub-pixel may include at least: a fifty-first connection electrode 51 and a fifty-second connection electrode 52 .
  • the fifty-first connection electrode 51 may be in a strip shape extending along the first direction D1, and the fifty-first connection electrode 51 may be connected to the fourth through a plurality of thirty-first via holes V31.
  • the eleven connection electrodes 41 are connected, and the fifty-first connection electrode 51 is configured to be connected to the first electrode plate formed subsequently.
  • the shape of the fifty-second connection electrode 52 may be a strip shape extending along the first direction D1, and the fifty-second connection electrode 52 may be connected to the fourth through a plurality of thirty-second via holes V32. Twelve connection electrodes 42 are connected, and the fifty-second connection electrode 52 is configured to be connected to the sixty-first connection electrode formed subsequently.
  • the fifth conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the fifth conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the fifth conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the fifth conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • Form a sixth insulating layer pattern may include: depositing a sixth insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the sixth insulating film through a patterning process, and forming a pattern covering the fifth conductive layer.
  • the sixth insulating layer is provided with multiple via holes, as shown in Figure 15.
  • the plurality of via holes in each sub-pixel may include: a forty-first via hole V41 and a forty-second via hole V42.
  • the orthographic projection of the forty-first via hole V41 on the silicon substrate is within the range of the orthographic projection of the fifty-first connecting electrode 51 on the silicon substrate, and the orthogonal projection of the forty-first via hole V41 on the silicon substrate is
  • the sixth insulating layer is etched away to expose the surface of the fifty-first connection electrode 51, and the forty-first via hole V41 is configured to allow the subsequently formed first plate to communicate with the fifty-first connection electrode through the via hole. 51 connections.
  • the orthographic projection of the forty-second via hole V42 on the silicon substrate is within the range of the orthographic projection of the fifty-second connecting electrode 52 on the silicon substrate, and the orthogonal projection of the forty-second via hole V42 on the silicon substrate is
  • the sixth insulating layer is etched away to expose the surface of the 52nd connection electrode 52, and the 42nd via hole V42 is configured to allow the subsequently formed 61st connection electrode to pass through the via hole and the 52nd connection electrode 52.
  • the connection electrode 52 is connected.
  • a plurality of forty-first via holes V41 and a plurality of forty-second via holes V42 may be sequentially disposed along the first direction D1 to reduce contact resistance and improve connection reliability.
  • forming the sixth conductive layer pattern may include: depositing a sixth conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the sixth conductive film through a patterning process, and forming a sixth conductive film on the sixth insulating layer.
  • the pattern of the sixth conductive layer is as shown in Figures 16A and 16B.
  • Figure 16B is a schematic diagram of the sixth conductive layer in Figure 16A.
  • the sixth conductive layer may be called a fifth metal (Metal5) layer.
  • the sixth conductive layer pattern in each sub-pixel may include at least: a sixty-first connection electrode 61 and a first plate 91 of a storage capacitor.
  • the shape of the sixty-first connection electrode 61 may be a rectangular shape, and the sixty-first connection electrode 61 may be connected to the fifty-second connection electrode 52 through a plurality of forty-second via holes V42. Sixty-one connection electrodes 61 are configured to be connected to the subsequently formed anode connection electrode.
  • the shape of the first plate 91 of the storage capacitor may be rectangular, and the first plate 91 may be connected to the fifty-first connection electrode 51 through a plurality of forty-first vias V41.
  • Plate 91 is configured as a plate of a storage capacitor. Since the fifty-first connection electrode 51 is connected to the forty-first connection electrode 41 through the via hole, the forty-first connection electrode 41 is connected to the thirty-first connection electrode 31 through the via hole, and the thirty-first connection electrode 31 is connected through the via hole.
  • the hole is connected to the 22nd connection electrode 22, and the 22nd connection electrode 22 is connected to the second region of the first active layer and the gate electrode of the second transistor T2 through the via hole, thereby realizing the first plate 91 , the second electrode of the first transistor T1 and the gate electrode of the second transistor T2 have the same potential (the first node N1 of the pixel driving circuit).
  • the sixth conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the sixth conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the sixth conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the sixth conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • forming the seventh conductive layer pattern may include: sequentially depositing a seventh insulating film and a seventh conductive film on the silicon substrate forming the foregoing pattern, patterning the seventh conductive film through a patterning process, forming The seventh insulating layer covering the sixth conductive layer pattern, and the seventh conductive layer pattern disposed on the seventh insulating layer, are shown in Figures 17A and 17B.
  • Figure 17B is a schematic diagram of the seventh conductive layer in Figure 17A.
  • the seventh conductive layer may be called a Metal-Insulator-Metal (MIM) layer.
  • MIM Metal-Insulator-Metal
  • the seventh conductive layer in each sub-pixel may at least include: a second plate 92 of a storage capacitor.
  • the shape of the second electrode plate 92 may be a rectangular shape, and an orthographic projection of the second electrode plate 92 on the silicon substrate at least partially overlaps with an orthographic projection of the first electrode plate 91 on the silicon substrate.
  • the diode plate 92 is configured as another pole plate of the storage capacitor, and the first pole plate 91 and the second pole plate 92 constitute the storage capacitor of the pixel driving circuit.
  • the area of the second electrode plate 92 may be smaller than the area of the first electrode plate 91 , and the orthographic projection of the second electrode plate 92 on the silicon substrate may be located at the orthogonal projection of the first electrode plate 91 on the silicon substrate. within the range.
  • the seventh conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror symmetrical with respect to the pixel center line A
  • the seventh conductive layer patterns of the two adjacent sub-pixels in the second direction D2 may be mirror symmetrical with respect to the pixel center line A.
  • the layer patterns can be essentially the same.
  • the seventh conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror symmetrical with respect to the pixel center line A.
  • the seventh conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror symmetrical with respect to the pixel center line A.
  • Form an eighth insulating layer pattern may include: depositing an eighth insulating film on the silicon substrate on which the foregoing pattern is formed, patterning the eighth insulating film through a patterning process, and forming a pattern covering the seventh conductive layer.
  • the eighth insulating layer is provided with multiple via holes, as shown in Figure 18.
  • the plurality of via holes in each sub-pixel may include at least: a fifty-first via hole V51 and a fifty-second via hole V52.
  • the orthographic projection of the fifty-first via hole V51 on the silicon substrate is within the range of the orthographic projection of the sixty-first connecting electrode 61 on the silicon substrate, and the orthogonal projection of the fifty-first via hole V51 on the silicon substrate is
  • the seventh insulating layer and the eighth insulating layer are etched away, exposing the surface of the sixty-first connection electrode 61, and the fifty-first via hole V51 is configured to allow the subsequently formed anode connection electrode to pass through the via hole and the sixth Eleven connection electrodes 61 are connected.
  • the orthographic projection of the fifty-second via hole V52 on the silicon substrate is within the range of the orthographic projection of the second plate 92 on the silicon substrate, and the eighth in the fifty-second via hole V52
  • the insulating layer is etched away to expose the surface of the second electrode plate 92 , and the fifty-second via hole V52 is configured so that the first power line formed later is connected to the second electrode plate 92 through the via hole.
  • Form an eighth conductive layer pattern may include: depositing an eighth conductive film on the silicon substrate on which the foregoing pattern is formed, patterning the eighth conductive film through a patterning process, and forming an eighth conductive layer on the eighth insulating layer.
  • the eighth conductive layer pattern is as shown in Figures 19A and 19B.
  • Figure 19B is a schematic diagram of the eighth conductive layer in Figure 19A.
  • the eighth conductive layer may be called a sixth metal (Metal6) layer or a second metal connection (TM2) layer.
  • the eighth conductive layer in each sub-pixel may include at least: an anode connection electrode 71 , a power supply electrode 72 , and a first power supply line 73 .
  • the shape of the anode connection electrode 71 may be a rectangular shape, the anode connection electrode 71 may be connected to the sixty-first connection electrode 61 through the fifty-first via hole V51, and the anode connection electrode 71 is configured to be connected to the subsequent formed anode connection. Since the sixty-first connection electrode 61 is connected to the fifty-second connection electrode 52 through the via hole, the fifty-second connection electrode 52 is connected to the forty-second connection electrode 42 through the via hole, and the forty-second connection electrode 42 is connected through the via hole.
  • the hole is connected to the thirty-third connection electrode 33, the thirty-third connection electrode 33 is connected to the twenty-fourth connection electrode 24 through the via hole, and the twenty-fourth connection electrode 24 is connected to the third connection electrode of the second active layer through the via hole.
  • the second area is connected to the second area of the third active layer, so that the subsequently formed anode can be connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3 (the second node N2 of the pixel driving circuit). connection, the current output by the pixel drive circuit can be supplied to the anode.
  • the shape of the power electrode 72 may be a rectangular shape, and the power electrode 72 may be connected to the second plate 92 through the fifty-second via hole V52.
  • the shape of the first power line 73 may be a line shape extending along the first direction D1, and the first power line 73 is connected to the power electrode 72 of each sub-pixel, so that the second plate 92 has the potential of the first power line 73.
  • the power electrode 72 and the first power line 73 may be an integral structure connected to each other.
  • the first and second plates 91 and 91 have the potential of the first node N1 of the pixel driving circuit.
  • 92 constitutes the storage capacitor of the MIM capacitor structure.
  • the subsequent preparation process may include processes such as forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color filter structure layer and a second encapsulation layer, which will not be described again here.
  • the structure of the display device and its preparation process in the exemplary embodiments of the present disclosure are only illustrative.
  • the corresponding structure can be changed and the patterning process can be added or reduced according to the actual situation, and the present disclosure is not limited here.
  • the first to eighth insulating layers may be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and may be a single-layer structure, or may be a multi-layer composite structure.
  • the first to sixth metal layers can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) or molybdenum (Mo), or they can be made of alloy materials composed of metals, such as aluminum-neodymium alloy. (AlNd) or molybdenum-niobium alloy (MoNb), etc.
  • the alloy material can be a single-layer structure, or it can be a multi-layer composite structure, such as a composite structure composed of Mo layer, Cu layer and Mo layer.
  • the planar shape of the via holes may be rectangular, circular, elliptical, etc., and the sizes of the multiple via holes may be the same or different, which is not limited in this disclosure.
  • FIG. 20 is an equivalent circuit diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate may include a display area AA and a frame area BK, and the frame area BK may be disposed on one side of the display area AA.
  • the display area AA may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel may include a pixel driving circuit, and the pixel driving circuit may include a first transistor T1, a second transistor T2, the third transistor T3 and the storage capacitor C, the pixel driving circuit is respectively connected with the first scanning signal line 26, the second scanning signal line 27, the data signal line 34, the reference signal line 35, the light-emitting voltage line 43, and the first power supply line 73. It is connected to the first pole of the light-emitting device XL, and the second pole of the light-emitting device XL is connected to the second power line VSS.
  • the first scanning signal line 26 , the second scanning signal line 27 , the light-emitting voltage line 43 and the first power supply line 73 may extend along the pixel row direction and be connected to pixel driving circuits in multiple sub-pixels in a pixel row.
  • the data signal line 34 and the reference signal line 35 may extend along the pixel column direction and be connected to pixel driving circuits in multiple sub-pixels in a pixel column.
  • the bezel area BK may include a gate driving circuit, a light emitting control circuit, and a bezel power supply lead.
  • the gate driving circuit may include a plurality of cascaded gate driving units (shift registers), and the gate driving circuit may be connected to the first scanning signal line 26 and the second scanning signal of each pixel row.
  • Line 27 outputs the first scanning signal and the second scanning signal to the first scanning signal line 26 and the second scanning signal line 27 respectively.
  • the light-emitting control circuit may at least include a light-emitting control transistor T4.
  • a gate electrode of the light-emitting control transistor T4 is connected to the light-emitting control line E.
  • a first electrode of the light-emitting control transistor T4 is connected to the frame power supply lead F.
  • the light-emitting control transistor T4 The second electrode of T4 is connected to the light-emitting voltage line 43 of each pixel row, and the light-emitting control transistor T4 is configured to output the light-emitting voltage to the light-emitting voltage line 43 under the control of the light-emitting control line E.
  • the frame power lead F is connected to the first power line 73 and continuously outputs a high level signal to the first power line 73 .
  • the gate driving circuit, the light emission control circuit and the frame power supply wires in the frame area can be prepared and formed simultaneously with the pixel driving circuit in the display area, and will not be described again here.
  • the present disclosure adopts minimal designs such as gate electrode overlapping positions are set at the same interval, gate electrodes are shared, drain electrodes are shared, and sub-pixels are flipped, etc. It maximizes the PPI of the display substrate and achieves the highest PPI design of Real RGB silicon-based OLED in the industry.
  • the present disclosure uses a via hole connecting the first scanning signal line and the gate electrode of the first transistor T1, a via hole connecting the second scanning signal line and the gate electrode of the third transistor T3, and a second electrode of the first transistor T1 and the third transistor T1.
  • the via holes connecting the gate electrodes of the two transistors T2 are all set in the gap area of the sub-pixel, forming a structure in which the overlapping positions of the gate electrodes in the sub-pixel are located in the same gap area.
  • the present disclosure forms a structure in which the sub-pixel is horizontally flipped relative to the pixel center line by mirroring the first transistor T1, the second transistor T2 and the third transistor T3 of two adjacent sub-pixels in the first direction with respect to the pixel center line, so that The first gate electrodes of two adjacent sub-pixels are an integral structure connected to each other, and the third gate electrodes of two adjacent sub-pixels are an integrated structure connected to each other, forming a structure shared by the gate electrodes of adjacent sub-pixels.
  • the present disclosure forms an integrated structure by arranging the second transistor T2 and the third transistor T3 along the second direction so that the second pole of the second transistor T2 and the second pole of the third transistor T3 are connected to each other to form leakage current in the sub-pixel.
  • Very common structure By adopting the MIM capacitor structure, the present disclosure not only increases the capacitance value of the storage capacitor, but also ensures the stability of the output current of the pixel drive circuit and the stability of the OLED brightness.
  • this disclosure optimizes the layout of the pixel drive circuit, optimizes the layout space, reduces the occupied area of the pixel drive circuit, maximizes the PPI of the display substrate, and achieves the highest PPI design of Real RGB silicon-based OLED in the industry , the resolution can reach 4k*4k, which can achieve higher display quality and display effect.
  • Exemplary embodiments of the present disclosure also provide a method for preparing a display substrate.
  • the display substrate includes a display area and a frame area
  • the display area includes a plurality of sub-pixels forming pixel rows and pixel columns
  • the sub-pixels include first areas sequentially arranged along the pixel row direction.
  • At least one sub-pixel includes a pixel driving circuit, a first scanning signal line and a second scanning signal line, the pixel driving circuit includes at least a first transistor, a second transistor and a third transistor, the The first scan signal line is configured to control the conduction or disconnection of the first transistor, and the second scan signal line is configured to control the conduction or disconnection of the second transistor; the first transistor at least including a first gate electrode, a first active layer, a first electrode of a first transistor, and a second electrode of the first transistor; the second transistor at least includes a second gate electrode and a second active layer; and the third The transistor at least includes a third gate electrode and a third active layer; the preparation method may include:
  • the first transistor, the second transistor, the third transistor, the first scanning signal line and the second scanning signal line are formed, the first active layer is provided in the first region, the second active layer and The third active layer is disposed in the second region, and the second active layer is disposed on one side of the third active layer in the pixel column direction; the first gate electrode is connected to the third active layer through a first gate via hole.
  • a scanning signal line is connected, the second gate electrode is connected to the second electrode of the first transistor through a second gate via hole, and the third gate electrode is connected to the second scanning signal line through a third gate via hole,
  • the first gate via hole, the second gate via hole and the third gate via hole are provided in the gap area.
  • Exemplary embodiments of the present disclosure also provide a display device, including the aforementioned display substrate.
  • the display device of the present disclosure can be used in virtual reality equipment or enhanced display equipment, etc.
  • the display device can also be used in, but is not limited to: mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators or any device with a display Functional products or components.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个子像素，子像素包括第一区(q1)、间隙区(q3)和第二区(q2)；子像素包括第一晶体管(T1)、第二晶体管(T2)和第三晶体管(T3)，第一晶体管(T1)包括第一有源层(1)和第一栅电极(11)，第二晶体管(T2)包括第二有源层(2)和第二栅电极(12)，第三晶体管(T2)包括第三有源层(3)和第三栅电极(13)；第一有源层(1)设置在第一区(q1)，第二有源层(2)和第三有源层(T3)设置在第二区(q2)，第一栅电极(11)和第三栅电极(13)与扫描信号线连接的过孔、第二栅电极(12)与第一晶体管(T1)连接的过孔均设置在间隙区(q3)。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
微型有机发光二极管(Micro Organic Light-Emitting Diode，简称Micro-OLED)是近年来发展起来的微型显示器，硅基OLED是其中的一种。硅基OLED不仅可以实现像素的有源寻址，并且可以实现在硅基衬底上制备像素驱动电路等结构，有利于减小系统体积，实现轻量化。硅基OLED采用成熟的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)集成电路工艺制备，具有体积小、高分辨率(Pixels Per Inch，简称PPI)、高刷新率等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供了一种显示基板，包括显示区域和边框区域，所述显示区域包括形成多个像素行和多个像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述第一有源层设置在所述第一区，所述第二有源层和第三有 源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一扫描信号线通过第一栅过孔与所述第一栅电极连接，所述第一晶体管的第二极通过第二栅过孔与所述第二栅电极连接，所述第二扫描信号线通过第三栅过孔与所述第三栅电极连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
在示例性实施方式中，沿着所述像素行方向，所述第一区具有第一宽度，所述第二区具有第二宽度，所述间隙区具有第三宽度，所述第三宽度小于或等于0.5*第一宽度，所述第三宽度小于或等于0.5*第二宽度。
在示例性实施方式中，所述像素行上相邻的两个子像素的第一栅电极为相互连接的一体结构，所述像素行上相邻的两个子像素的第三栅电极为相互连接的一体结构。
在示例性实施方式中，所述一体结构的第一栅电极通过两个第一栅过孔与所述第一扫描信号线连接，所述一体结构的第三栅电极通过两个第三栅过孔与所述第二扫描信号线连接。
在示例性实施方式中，所述像素行上相邻的两个子像素的所述第一晶体管、所述第二晶体管和所述第三晶体管相对于像素中心线镜像对称，所述像素中心线是位于所述像素行上相邻的两个子像素之间且沿着所述像素列方向延伸的直线。
在示例性实施方式中，至少一个子像素中，所述第一栅电极包括相互连接的第一栅主体部和第一栅连接部，所述第一栅连接部设置在所述间隙区，所述第一扫描信号线通过所述第一栅过孔与所述第一栅连接部连接。
在示例性实施方式中，至少一个子像素中，所述第二栅电极包括相互连接的第二栅主体部和第二栅连接部，所述第二栅连接部设置在所述间隙区，所述所述第一晶体管的第二极通过所述第二栅过孔与所述第二栅连接部连接。
在示例性实施方式中，至少一个子像素中，所述第三栅电极包括相互连接的第三栅主体部和第三栅连接部，所述第三栅连接部设置在所述间隙区，所述第二扫描信号线通过所述第三栅过孔与所述第三栅连接部连接。
在示例性实施方式中，至少一个子像素中，所述第一栅电极包括相互连 接的第一栅主体部和第一栅连接部，所述第一栅连接部设置所述第一栅主体部靠近所述第三栅电极的一侧，所述第三栅电极包括相互连接的第三栅主体部和第三栅连接部，所述第三栅连接部设置在所述第三栅主体部靠近所述第一栅电极的一侧，所述第一栅连接部和所述第三栅连接部在所述像素列方向上错位设置。
在示例性实施方式中，所述第一栅主体部和第一栅连接部远离所述第二晶体管一侧的边缘平齐，所述第三栅主体部和第三栅连接部靠近所述第二晶体管一侧的边缘平齐。
在示例性实施方式中，至少一个子像素中，所述第二栅电极包括相互连接的第二栅主体部和第二栅连接部，所述第二栅连接部设置在所述间隙区，所述第二栅主体部和第二栅连接部靠近所述第三晶体管一侧的边缘平齐。
在示例性实施方式中，所述第一扫描信号线和第二扫描信号线的形状为主体部分沿着所述像素行方向延伸的线形状，所述第一扫描信号线在所述显示基板的平面上的正投影与所述第一栅电极和第三栅电极在所述显示基板的平面上的正投影至少部分交叠，所述第二扫描信号线在所述显示基板的平面上的正投影与所述第一栅电极和第三栅电极在所述显示基板的平面上的正投影至少部分交叠。
在示例性实施方式中，所述第二晶体管还包括第二晶体管的第一极和第二晶体管的第二极，所述第三晶体管还包括第三晶体管的第一极和第三晶体管的第二极，所述第一源电极与数据信号线连接，所述第二晶体管的第一极与发光电压线连接，所述第三晶体管的第一极与参考信号线连接，所述第二晶体管的第二极和所述第三晶体管的第二极为相互连接的一体结构。
在示例性实施方式中，至少一个子像素中，所述像素驱动电路还包括存储电容，所述存储电容包括第一极板和第二极板，所述第一极板在所述显示基板的平面上的正投影与所述第二极板在所述显示基板的平面上的正投影至少部分交叠，所述第一极板通过连接电极与所述第一晶体管的第二极连接，所述第二极板与第一电源线连接。
在示例性实施方式中，至少一个子像素还包括接触电极，所述接触电极设置在所述第一区，所述接触电极设置在所述第一有源层所述像素列方向的 一侧。
在示例性实施方式中，至少一个子像素还包括偏置电压线，所述偏置电压线通过过孔与所述接触电极连接，所述偏置电压线在所述显示基板的平面上的正投影与所述第二栅电极在所述显示基板的平面上的正投影至少部分交叠。
在示例性实施方式中，至少一个子像素中，所述接触电极的形状为沿着所述像素列方向延伸的条形状，所述偏置电压线的形状为沿着所述像素行方向延伸的线形状，所述偏置电压线所述像素列方向的一侧或者两侧连接有偏置连接线，所述偏置连接线在所述显示基板的平面上的正投影与所述接触电极在所述显示基板的平面上的正投影至少部分交叠，所述偏置连接线通过过孔与所述接触电极连接。
在示例性实施方式中，所述偏置电压线和所述偏置连接线为相互连接的一体结构。
在示例性实施方式中，所述边框区域至少包括发光控制晶体管，所述发光控制晶体管的栅电极与发光控制线连接，所述发光控制晶体管的第一极与边框电源引线连接，所述发光控制晶体管的第二极与发光电压线连接，所述发光电压线与一个像素行中多个子像素的第二晶体管的第一极连接，所述边框电源引线与第一电源线连接。
在示例性实施方式中，垂直于所述显示基板的平面上，所述显示基板至少包括在硅基底上依次设置的第一导电层和第二导电层，所述硅基底至少包括所述第一有源层、第二有源层和第三有源层，所述第一导电层至少包括所述第一栅电极、第二栅电极和第三栅电极，所述第二导电层至少包括所述第一扫描信号线和第二扫描信号线。
在示例性实施方式中，所述显示基板还包括设置在所述第二导电层远离所述硅基底一侧的第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层，所述第三导电层至少包括数据信号线和参考信号线，所述第四导电层至少包括发光电压线，所述第六导电层至少包括存储电容的第一极板，所述第七导电层至少包括存储电容的第二极板，所述第八导电层至少包括阳极连接电极和第一电源线。
另一方面，本公开实施例提供了一种显示装置，包括前述的显示基板。
又一方面，本公开实施例提供了一种显示基板的制备方法，所述显示基板包括显示区域和边框区域，所述显示区域包括形成像素行和像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述制备方法包括：
形成所述第一晶体管、第二晶体管、第三晶体管、第一扫描信号线和第二扫描信号线，所述第一有源层设置在所述第一区，所述第二有源层和第三有源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一栅电极通过第一栅过孔与第一扫描信号线连接，所述第二栅电极通过第二栅过孔与所述第一晶体管的第二极连接，所述第三栅电极通过第三栅过孔与第二扫描信号线连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种硅基OLED显示装置的结构示意图；
图2为一种硅基OLED显示装置的平面结构示意图；
图3为一种硅基OLED显示装置的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路图；
图5为本公开示例性实施例一种显示基板的平面结构示意图；
图6为本公开实施例形成第一导电层图案后的示意图；
图7为本公开实施例形成第二绝缘层图案后的示意图；
图8A和图8B为本公开实施例形成第二导电层图案后的示意图；
图9为本公开实施例形成第三绝缘层图案后的示意图；
图10A和图10B为本公开实施例形成第三导电层图案后的示意图；
图11为本公开实施例形成第四绝缘层图案后的示意图；
图12A和图12B为本公开实施例形成第四导电层图案后的示意图；
图13为本公开实施例形成第五绝缘层图案后的示意图；
图14A和图14B为本公开实施例形成第五导电层图案后的示意图；
图15为本公开实施例形成第六绝缘层图案后的示意图；
图16A和图16B为本公开实施例形成第六导电层图案后的示意图；
图17A和图17B为本公开实施例形成第七导电层图案后的示意图；
图18为本公开实施例形成第八绝缘层图案后的示意图；
图19A和图19B为本公开实施例形成第八导电层图案后的示意图；
图20为本公开示例性实施例一种显示基板的等效电路图。
附图标记说明:
1—第一有源层；         2—第二有源层；         3—第三有源层；
4—接触电极；           11—第一栅电极；        11-1—第一栅主体部；
11-2—第一栅连接部；    12—第二栅电极；        12-1—第二栅主体部；
12-2—第二栅连接部；    13—第三栅电极；        13-1—第三栅主体部；
13-2—第三栅连接部；    21—第二十一连接电极；  22—第二十二连接电极；
23—第二十三连接电极；  24—第二十四连接电极；  26—第一扫描信号线；
27—第二扫描信号线；    28—偏置电压线；        29—偏置连接线；
31—第三十一连接电极；  32—第三十二连接电极；  33—第三十三连接电极；
34—数据信号线；        35—参考信号线；        41—第四十一连接电极；
42—第四十二连接电极；  43—发光电压线；        51—第五十一连接电极；
52—第五十二连接电极；  61—第六十一连接电极；  71—阳极连接电极；
72—电源电极；          73—第一电源线；        91—第一极板；
92—第二极板；          101—硅基底；           102—驱动电路层；
103—发光结构层；       104—第一封装层；       105—彩膜结构层；
106—第二封装层；       107—盖板层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示装置中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述， 而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为了区分晶体管除栅电极之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种硅基OLED显示装置的结构示意图。如图1所示，硅基OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。子像素阵列可以包括多个像素子PXij。每个像素子PXij可以连接到对应的数据信号线和对应的扫描信号线，i和j可以是自然数。子像素PXij可以指其中晶体管连接到第i 扫描信号线且连接到第j数据信号线的子像素。
图2为一种硅基OLED显示装置的平面结构示意图。如图2所示，显示装置可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，三个子像素均包括像素驱动电路和发光器件，子像素中的像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向显示发光器件输出相应的电流。子像素中的显示发光器件分别与所在子像素的像素驱动电路连接，显示发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色(R)光线的红色子像素，第二子像素P2可以是出射蓝色(B)光线的蓝色子像素，第三子像素P3可以是出射绿色(G)光线的绿色子像素。
在示例性实施方式中，子像素的形状可以是三角形、正方形、矩形、菱形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，三个子像素可以采用水平并列、竖直并列、品字形等方式排列，本公开在此不做限定。在其它可能的实施方式中，像素单元可以包括四个子像素，本公开在此不做限定。
图3为一种硅基OLED显示装置的剖面结构示意图，示意了一种采用白光+彩膜方式实现全彩的结构。如图3所示，硅基OLED显示装置可以包括：硅基底101，设置在硅基底101上的驱动电路层102，设置在驱动电路层102远离硅基底101一侧的发光结构层103，设置在发光结构层103远离硅基底101一侧的第一封装层104，设置在第一封装层104远离硅基底101一侧的彩膜结构层105，设置在彩膜结构层105远离硅基底101一侧的第二封装层106，以及设置在第二封装层106远离硅基底101一侧的盖板层107。在一些可能的实现方式中，硅基OLED显示装置可以包括其它膜层，本公开在此不做限定。
在示例性实施方式中，硅基底101可以为体硅基底或者绝缘层上硅(SOI，Silicon-On-Insulator)基底。驱动电路层102可以通过硅半导体工艺(例如 CMOS工艺)制备在硅基底101上，驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个晶体管作为示例。晶体管可以包括栅电极G、第一极S和第二极D，栅电极G、第一极S和第二极D可以通过钨金属填充的过孔(即钨过孔，W-via)分别与相应的连接电极连接，并可以通过连接电极与其它电学结构(如走线等)进行连接。
在示例性实施方式中，发光结构层103可以包括多个发光器件，发光器件可以至少包括阳极、有机发光层和阴极，阳极可以通过连接电极与晶体管的第二极D连接，有机发光层与阳极连接，阴极与有机发光层连接，阴极与第二电源线连接，有机发光层在阳极和阴极驱动下出射光线。在示例性实施方式中，有机发光层可以包括发光层(简称EML)，以及如下任意一种多种：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，对于出射白光的发光器件，所有子像素的有机发光层可以是连接在一起的共通层。
在示例性实施方式中，第一封装层104和第二封装层106可以采用薄膜封装(Thin Film Encapsulation，简称TFE)方式，可以保证外界水汽无法进入发光结构层，盖板层107可以采用玻璃，或者采用具可挠特性的塑胶类无色聚酰亚胺等。
在示例性实施方式中，彩膜结构层105可以包括黑矩阵(BM)和彩色滤光片(CF)，彩色滤光片分别设置在红色子像素、绿色子像素和蓝色子像素，将发光器件出射的白光过滤成红色(R)光、绿色(G)光和蓝色(B)光，黑矩阵可以位于相邻的彩色滤光片之间。
目前，硅基OLED显示装置逐渐应用与虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)近眼显示领域中，使得用户可以在虚拟现实世界中体验到真实的感受，具有超强的仿真系统，实现了人机交互。研究表明，当屏幕分辨率足够大时，人眼视网膜就无法分辨出像素点了。分辨率(Pixels Per Inch，简称PPI)是指单位面积所拥有像素的数 量，可以称为像素密度，PPI数值越高，代表显示基板能够以越高的密度显示画面，画面的细节就越丰富。因而，为了提高显示品质，大幅度提升PPI成为各个厂商的研究重点。
本公开示例性实施例提供了一种显示基板，包括显示区域和边框区域，所述显示区域包括形成多个像素行和多个像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述第一有源层设置在所述第一区，所述第二有源层和第三有源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一扫描信号线通过第一栅过孔与所述第一栅电极连接，所述第一晶体管的第二极通过第二栅过孔与所述第二栅电极连接，所述第二扫描信号线通过第三栅过孔与所述第三栅电极连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
在示例性实施方式中，沿着所述像素行方向，所述第一区具有第一宽度，所述第二区具有第二宽度，所述间隙区具有第三宽度，所述第三宽度小于或等于0.5*第一宽度，所述第三宽度小于或等于0.5*第二宽度。
在示例性实施方式中，所述像素行上相邻的两个子像素的第一栅电极为相互连接的一体结构，所述像素行上相邻的两个子像素的第三栅电极为相互连接的一体结构。
在示例性实施方式中，所述一体结构的第一栅电极通过两个第一栅过孔与所述第一扫描信号线连接，所述一体结构的第三栅电极通过两个第三栅过孔与所述第二扫描信号线连接。
在示例性实施方式中，所述像素行上相邻的两个子像素的所述第一晶体管、所述第二晶体管和所述第三晶体管相对于像素中心线镜像对称，所述像 素中心线是位于所述像素行上相邻的两个子像素之间且沿着所述像素列方向延伸的直线。
在示例性实施方式中，所述第二晶体管还包括第二晶体管的第一极和第二晶体管的第二极，所述第三晶体管还包括第三晶体管的第一极和第三晶体管的第二极，所述第一源电极与数据信号线连接，所述第二晶体管的第一极与发光电压线连接，所述第三晶体管的第一极与参考信号线连接，所述第二晶体管的第二极和所述第三晶体管的第二极为相互连接的一体结构。
本公开示例性实施例提供了一种超高PPI的显示基板，通过采用栅电极搭接位置均设置在同一间隔、栅电极共用、漏电极共用、子像素翻转等最小化设计，最大限度地提高了显示基板的PPI，实现了业内Real RGB硅基OLED最高PPI设计。
下面通过示例性实施例说明本公开显示基板的技术方案。
图4为本公开示例性实施例一种像素驱动电路的等效电路图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C等结构。如图4所示，本公开示例性实施例像素驱动电路可以是3T1C结构，包括3个晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)和1个存储电容C，像素驱动电路与7条信号线(第一扫描信号线S1、第二扫描信号线S1、数据信号线D、参考信号线VE、第一电源线VDD和发光电压线VF)连接，第一节点N1和第二节点N2是表示电路图中相关电连接的汇合点。
在示例性实施方式中，存储电容C的第一端可以与第一节点N1连接，存储电容C的第二端可以与第一电源线VDD连接。
在示例性实施方式中，第一晶体管T1的栅电极与第一扫描信号线S1连接，第一晶体管T1的第一极与数据信号线D连接，第一晶体管T1的第二极与第一节点N1连接。
在示例性实施方式中，第二晶体管T2的栅电极与第一节点N1连接，第二晶体管T2的第一极与发光电压线VF连接，第二晶体管T2的第二极与第二节点N2连接。
在示例性实施方式中，第三晶体管T3的栅电极与第二扫描信号线S2连接，第三晶体管T3的第一极与参考信号线VE连接，第三晶体管T3的第二极与第二节点N2连接。
在示例性实施方式中，发光器件XL的第一极与第二节点N2连接，发光器件XL的第二极与第二电源线VSS连接。
在示例性实施方式中，第一晶体管T1被配置为在第一扫描信号线S1的信号的控制下，接收数据信号线D传输的数据电压，将数据电压存储至存储电容C，并向第二晶体管T2的栅电极提供数据电压。第二晶体管T2被配置为在其栅电极所接收的数据信号控制下，在第二极产生相应的电流，以驱动显示发光器件XL发光。第三晶体管T3被配置为在第二扫描信号线S2的信号的控制下，接收参考信号线VE传输的参考电压，向第二节点N2提供参考电压。存储电容C被配置为存储第二晶体管T2的栅电极的电位，发光器件XL被配置为响应第二晶体管T2的第二极的电流发出相应亮度的光。
在示例性实施方式中，第一电源线VDD的信号可以为持续提供的高电平信号，发光电压线VF的信号可以为发光控制晶体管输出的电压信号，第二电源线VSS的信号可以为持续提供的低电平信号。
在一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以是P型晶体管。在另一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在又一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以包括P型晶体管和N型晶体管。例如，第一晶体管T1和第三晶体管T3可以为P型金属氧化物半导体晶体管(PMOS)，第二晶体管T2可以为N型金属氧化物半导体晶体管(NMOS)。
在示例性实施方式中，发光器件XL可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为本公开示例性实施例一种显示基板的平面结构示意图，示意了一个像素单元中三个子像素的结构。在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以至少包括硅基底、设置在硅基底上的驱动电路层、 设置在驱动电路层远离硅基底一侧的发光结构层以及设置在发光结构层远离硅基底一侧的封装层。在平行于显示基板的平面上，显示基板的驱动电路层可以包括形成多个像素行和多个像素列的多个子像素，沿着第一方向D1依次设置第一子像素P1、第二子像素P2和第三子像素P3组成一个像素单元。第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路、第一扫描信号线26和第二扫描信号线27，像素驱动电路可以至少包括第一晶体管T1、第二晶体管T2和第三晶体管T3，第一扫描信号线26被配置为控制第一晶体管T1的导通或者断开，第二扫描信号线27被配置为控制第二晶体管T2的导通或者断开。
如图5所示，在示例性实施方式中，第一晶体管T1可以包括第一有源层1、第一栅电极11、第一晶体管T1的第一极(第二十一连接电极)21和第一晶体管T1的第二极(第二十二连接电极)22。第二晶体管T2可以包括第二有源层2、第二栅电极12、第二晶体管T2的第一极(第二十三连接电极)23和第二晶体管T2的第二极(第二十四连接电极)24。第三晶体管T3可以包括第三有源层3、第三栅电极13、第三晶体管T3的第一极(第二十五连接电极)25和第三晶体管T3的第二极(第二十四连接电极)24。
在示例性实施方式中，第一子像素P1、第二子像素P2和第三子像素P3均可以包括沿着像素行方向依次设置的第一区q1、间隙区q3和第二区q2，间隙区q3可以设置在第一区q1和第二区q2之间。例如，第一子像素P1和第三子像素P3可以包括沿着第一方向D1依次设置的第一区q1、间隙区q3和第二区q2，第二子像素P2可以包括沿着第一方向D1的反方向依次设置的第一区q1、间隙区q3和第二区q2，第一子像素P1与第二子像素P2中三个区的设置位置相对于像素中心线A镜像对称，第二子像素P2与第三子像素P3中三个区的设置位置相对于像素中心线A镜像对称，像素中心线A是位于第一方向D1上相邻的两个子像素之间且沿着第二方向D2延伸的直线。
在示例性实施方式中，沿着第一方向D1，第一区q1可以具有第一宽度，第二区q2可以具有第二宽度，间隙区q3可以具有第三宽度，第三宽度可以小于或等于0.5*第一宽度，第三宽度可以小于或等于0.5*第二宽度。
在示例性实施方式中，至少一个子像素中，第一有源层1可以设置在第 一区q1，第二有源层2和第三有源层3可以设置在第二区q2，第二有源层2可以设置在第三有源层3第二方向D2的一侧，间隙区q3中没有设置有源层，间隙区q3作为第一区q1中有源层和第二区q2中有源层之间的间隙区域。这样形成了“L”形排布的第一晶体管T1、第二晶体管T2和第三晶体管T3，第一晶体管T1和第三晶体管T3可以沿着第一方向D1依次设置，第二晶体管T2和第三晶体管T3可以沿着第二方向D2依次设置。
在示例性实施方式中，至少一个子像素中，第一扫描信号线26通过第一栅过孔K1与第一晶体管T1的第一栅电极11连接，第一晶体管的第二极22通过第二栅过孔K2与第二晶体管T2的第二栅电极12连接，第二扫描信号线27通过第三栅过孔K3与所述第三晶体管T3的第三栅电极连接，第一栅过孔K1、第二栅过孔K2和第三栅过孔K3可以均设置在间隙区q3，形成子像素内栅电极搭接位置均位于同一间隙区域的结构。
在示例性实施方式中，第一晶体管T1的第一极21可以与数据信号线连接，第二晶体管T2的第一极23可以与发光电压线连接，第三晶体管T3的第一极25可以与参考信号线连接，第二晶体管T2的第二极24和第三晶体管T3的第二极24可以同层设置，通过同一次图案化工艺形成相互连接的一体结构，形成子像素内漏电极共用的结构。
在示例性实施方式中，第一方向D1上相邻两个子像素的第一晶体管T1、第二晶体管T2和第三晶体管T3可以相对于像素中心线A镜像对称，形成子像素相对于像素中心线A水平翻转的结构。
在示例性实施方式中，第一方向D1上相邻两个子像素的第一栅电极11可以同层设置，通过同一次图案化工艺形成相互连接的一体结构，第一方向D1上相邻两个子像素的第三栅电极13可以同层设置，通过同一次图案化工艺形成相互连接的一体结构，形成相邻子像素栅电极共用的结构。例如，第一子像素P1的第三栅电极13和第二子像素P2的第三栅电极13为相互连接的一体结构，第二子像素P2的第一栅电极11和第三子像素P3的第一栅电极11为相互连接的一体结构。
在示例性实施方式中，至少一个子像素中，第一晶体管T1的第一栅电极11可以包括第一栅主体部11-1和第一栅连接部11-2，第一栅连接部11-2 可以设置在第一栅主体部11-1靠近第三晶体管T3的一侧，且与第一栅主体部11-1连接，使得第一栅连接部11-2位于间隙区q3，第一扫描信号线26可以通过第一栅过孔K1与第一栅连接部11-2连接。
在示例性实施方式中，至少一个子像素中，第二晶体管T2的第二栅电极12可以包括第二栅主体部12-1和第二栅连接部12-2，第二栅连接部12-2可以设置在第二栅主体部12-1靠近第一晶体管T1的一侧，且与第二栅主体部12-1连接，使得第二栅连接部12-2位于间隙区q3，第一晶体管的第二极22通过第二栅过孔K2与第二栅连接部12-2连接。
在示例性实施方式中，至少一个子像素中，第三晶体管T3的第三栅电极13可以包括第三栅主体部13-1和第三栅连接部13-2，第三栅连接部13-2可以设置在第三栅主体部13-1靠近第一晶体管T1的一侧，且与第三栅主体部13-1连接，使得第三栅连接部13-2位于间隙区q3，第二扫描信号线27可以通过第三栅过孔K3与第三栅连接部13-2连接。
在示例性实施方式中，至少一个子像素中，第一栅连接部11-2和第三栅连接部13-2在第二方向D2上错位设置，且两者之间具有间隔。
在示例性实施方式中，第一栅主体部11-1和第一栅连接部11-2远离第二晶体管T2一侧的边缘可以平齐。
在示例性实施方式中，第三栅主体部13-1和第三栅连接部13-2靠近第二晶体管T2一侧的边缘可以平齐。
在示例性实施方式中，第一扫描信号线26和第二扫描信号线27的形状可以为主体部分沿着第一方向D1延伸的线形状，第一扫描信号线26在显示基板的平面上的正投影与第一栅电极11和第三栅电极13在显示基板的平面上的正投影至少部分交叠，第二扫描信号线27在显示基板的平面上的正投影与第一栅电极11和第三栅电极13在显示基板的平面上的正投影至少部分交叠。
在示例性实施方式中，至少一个子像素还可以包括接触电极4，接触电极4可以设置在第一区q1，接触电极4可以设置在第一有源层1第二方向D2的一侧，接触电极4被配置为被配置为对硅基底进行低压偏置，从而避免硅基底偏置效应等寄生效应引起的阈值电压变化，提高电路的稳定性。。
在示例性实施方式中，至少一个子像素还可以包括偏置电压线28，偏置电压线28在显示基板的平面上的正投影与所述第二晶体管T2的第二栅电极12在显示基板的平面上的正投影至少部分交叠。偏置电压线28可以通过过孔与接触电极4连接，实现偏置电压线28向接触电极4提供低电压。
在示例性实施方式中，至少一个子像素中，接触电极4的形状可以为主体部分沿着第二方向D2延伸的线形状，偏置电压线28的形状可以为主体部分沿着第一方向D1延伸的线形状，偏置电压线28第二方向D2的一侧或者两侧可以连接有偏置连接线29，偏置连接线29的形状可以为主体部分沿着第二方向D2延伸的条形状，偏置连接线29在显示基板的平面上的正投影与接触电极4在显示基板的平面上的正投影至少部分交叠，偏置连接线29通过多个过孔与接触电极4连接。
在示例性实施方式中，偏置电压线28和偏置连接线29可以同层设置，通过同一次图案化工艺形成相互连接的一体结构。
在示例性实施方式中，垂直于所述显示基板的平面上，显示基板的驱动电路层可以包括在硅基底上依次设置的第一导电层和第二导电层，硅基底可以至少包括第一有源层1、第二有源层2、第三有源层3和接触电极4，第一导电层可以至少包括第一栅电极11、第二栅电极12和第三栅电极13，第二导电层可以至少包括第一晶体管T1的第一极21、第一晶体管T1的第二极22、第二晶体管T2的第一极23、第二晶体管T2的第二极(也是第三晶体管T3的第二极)24、第三晶体管T3的第一极25、第一扫描信号线26、第二扫描信号线27、偏置电压线28和偏置连接线29。
在示例性实施方式中，驱动电路层还可以包括设置在第二导电层远离硅基底一侧的第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层，第三导电层可以至少包括数据信号线和参考信号线，第四导电层可以至少包括发光电压线，第五导电层可以至少包括多个连接电极，第六导电层可以至少包括存储电容的第一极板，第七导电层可以至少包括存储电容的第二极板，第八导电层可以至少包括阳极连接电极和第一电源线。
下面通过显示装置的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、 显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示装置方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以一个像素单元中的3个子像素为例，显示装置的制备过程可以包括以下步骤。
(1)形成硅基底。在示例性实施方式中，形成硅基底可以包括：提供P型硅材料的硅基底，如P型单晶硅，P型单晶硅可以作为N型晶体管的沟道区。
在示例性实施方式中，硅基底可以采用N型硅材料，作为P型晶体管的沟道区，本公开在此不做限定。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在硅基底上依次沉积第一绝缘薄膜和多晶硅薄膜，先通过图案化工艺对多晶硅薄膜进行图案化，形成覆盖硅基底的第一绝缘层以及设置在第一绝缘层上的多晶硅层图案，然后利用多晶硅层图案作为遮挡进行掺杂工艺，形成第一导电层和有源层图案，如图6所示。
在示例性实施方式中，掺杂工艺可以采用N型掺杂工艺，掺杂元素可以是硼元素等，形成的有源层图案可以至少包括第一晶体管T1的第一有源层1、第二晶体管T2的第二有源层2、第三晶体管T3的第三有源层3以及接触电极4，形成的第一导电层图案可以至少包括第一晶体管T1的第一栅电极11、 第二晶体管T2的第二栅电极12和第三晶体管T3的第三栅电极13。
在示例性实施方式中，掺杂工艺可以采用离子注入工艺，由于多晶硅层为半导体材料，因而在离子注入工艺中，一方面可以利用多晶硅层作为遮挡，使得离子注入到多晶硅层的两侧，形成多个晶体管的第一区和第二区，实现自对准，另一方面可以同时掺杂多晶硅层，使得电阻较高的多晶硅层变成电阻较低的第一导电层，形成多个晶体管的栅电极。本公开通过采用多晶硅材料作为第一导电层，可以节省工艺成本，降低工艺难度。
在示例性实施方式中，每个子像素中的第一有源层1和接触电极4可以设置在第一区q1，第二有源层2和第三有源层3可以设置在第二区q2，间隙区q3中没有设置有源层，间隙区q3作为第一区q1中有源层和第二区q2中有源层之间的间隙区域。
在示例性实施方式中，第一有源层1、第二有源层2、第三有源层3和接触电极4可以为沿着第二方向D2延伸的条形状。接触电极4可以设置在第一有源层1第二方向D2的一侧，第二有源层2可以设置在第三有源层3第二方向D2的一侧。这样，第三有源层3可以设置在第一有源层1第一方向D1的一侧或者第一方向D1的反方向的一侧，第二有源层2可以设置在接触电极4第一方向D1的一侧或者第一方向D1的反方向的一侧，第一有源层1和第三有源层3可以位于子像素第二方向D2的一侧，接触电极4和第二有源层2可以位于子像素第二方向D2的另一侧，每个子像素中的第一有源层1、第二有源层2和第三有源层3形成“L”形布局。本公开通过将第二有源层2和第三有源层3设置在子像素第一方向D1的相同侧，有利于实现第二有源层2的第二区和第三有源层3的第二区的连接，不仅可以简化结构，而且可以减小像素驱动电路的占用面积，从而实现显示产品的分辨率。
在示例性实施方式中，第一方向D1上相邻的两个子像素的有源层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的有源层图案可以基本上相同，像素中心线A是在第一方向D1上位于相邻的两个子像素之间且沿着第二方向D2延伸的直线。例如，第一子像素P1和第二子像素P2的有源层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的有源层图案可以相对于像素中心线A镜像对称。
在示例性实施方式中，每个子像素中的第一栅电极11和第三栅电极13可以沿着第一方向D1依次设置，第二栅电极12和第三栅电极13可以沿着第二方向D2依次设置，在子像素中形成“L”形布局。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第一导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第一导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第一导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第一导电层图案可以相对于像素中心线A镜像对称。
在示例性实施方式中，由于第一导电层图案的对称特性，第一方向D1上相邻的两个子像素的第一栅电极11可以为相互连接的一体结构，第一方向D1上相邻的两个子像素的第三栅电极13可以为相互连接的一体结构。例如，第一子像素P1和第二子像素P2的第三栅电极13可以为相互连接的一体结构。又如，第二子像素P2和第三子像素P3第一栅电极11可以为相互连接的一体结构。本公开通过将相邻两个子像素的第一栅电极设置成相互连接的一体结构，将相邻两个子像素的第三栅电极设置成相互连接的一体结构，可以在满足设计规则的前提下，使得像素驱动电路的排布更加紧凑，有助于提高显示装置的分辨率。
在示例性实施方式中，第一晶体管T1的第一栅电极11可以包括第一栅主体部11-1和第一栅连接部11-2。第一栅主体部11-1的形状可以为矩形状，第一栅主体部11-1与第一有源层1相重叠的区域可以作为第一有源层1的第一沟道区，第一有源层1的第一区1-1可以位于第一沟道区第二方向D2的一侧(远离接触电极4的一侧)，第一有源层1的第二区1-2可以位于第一沟道区第二方向D2的反方向的一侧(靠近接触电极4的一侧)。第一栅连接部11-2的形状可以为矩形状，可以设置在第一栅主体部11-1靠近第三晶体管T3的一侧，且与第一栅主体部11-1连接，使得第一栅连接部11-2位于间隙区q3，第一栅连接部11-2被配置为通过第一栅过孔与后续形成的第一扫描信号线连接。
在示例性实施方式中，第二晶体管T2的第二栅电极12可以包括第二栅主体部12-1和第二栅连接部12-2。第二栅主体部12-1的形状可以为矩形状， 第二栅主体部12-1与第二有源层2相重叠的区域可以作为第二有源层2的第二沟道区，第二有源层2的第一区2-1可以位于第二沟道区第二方向D2的反方向的一侧(远离第三有源层3的一侧)，第二有源层2的第二区2-2可以位于第二沟道区第二方向D2的一侧(靠近第三有源层3的一侧)。第二栅连接部12-2的形状可以为矩形状，可以设置在第二栅主体部12-1靠近接触电极4的一侧，且与第二栅主体部12-1连接，使得第二栅连接部12-2位于间隙区q3，第二栅连接部12-2被配置为通过第二栅过孔与后续形成的第一晶体管的第二极连接。
在示例性实施方式中，第三晶体管T3的第三栅电极13可以包括第三栅主体部13-1和第三栅连接部13-2。第三栅主体部13-1的形状可以为矩形状，第三栅主体部13-1与第三有源层3相重叠的区域可以作为第三有源层3的第三沟道区，第三有源层3的第一区3-1可以位于第三沟道区第二方向D2的一侧(远离第二有源层2的一侧)，第三有源层3的第二区3-2可以位于第三沟道区第二方向D2的反方向的一侧(靠近第二有源层2的一侧)。第三栅连接部13-2的形状可以为矩形状，可以设置在第三栅主体部13-1靠近第一晶体管T1的一侧，且与第三栅主体部13-1连接，使得第三栅连接部13-2位于间隙区q3，第三栅连接部13-2被配置为通过第三栅过孔与后续形成的第二扫描信号线连接。
在示例性实施方式中，由于第一栅连接部11-2、第二栅连接部12-2和第三栅连接部13-2均位于间隙区q3，且分别被配置为与后续形成的第一扫描信号线、第一晶体管的第二极和第二扫描信号线连接，使得三个栅电极的搭接位置均位于同一间隔区域内，不仅可以在满足设计规则的前提下，使得像素驱动电路的排布更加紧凑，有助于提高显示装置的分辨率，而且使得栅过孔不会影响晶体管的电学性能，提高像素驱动电路的工作可靠性。
在示例性实施方式中，位于间隙区q3的第一栅连接部11-2和第三栅连接部13-2可以在第二方向D2上错位设置，且第一栅连接部11-2和第三栅连接部13-2之间具有间隔。
在示例性实施方式中，第一栅连接部11-2可以位于间隙区q3第二方向D2的一端，第三栅连接部13-2可以位于间隙区q3第二方向D2的反方向的 一端，第一栅主体部11-1和第一栅连接部11-2远离第二晶体管T2一侧的边缘可以平齐，第三栅主体部13-1和第三栅连接部13-2靠近第二晶体管T2一侧的边缘可以平齐。在一些可能的实施方式中，第一栅连接部11-2可以位于间隙区q3第二方向D2的反方向的一端，第三栅连接部13-2可以位于间隙区q3第二方向D2的一端，第一栅主体部11-1和第一栅连接部11-2靠近第二晶体管T2一侧的边缘可以平齐，第三栅主体部13-1和第三栅连接部13-2远离第二晶体管T2一侧的边缘可以平齐。
在示例性实施方式中，接触电极4可以为N型掺杂区(N+)，接触电极4被配置为对硅基底进行低压偏置，从而避免硅基底偏置效应等寄生效应引起的阈值电压变化，提高电路的稳定性。本公开通过设置接触电极4对硅基底进行低压偏置，可以对子像素之间的器件进行电性隔离，并降低器件之间的寄生效应，可以提高电路的稳定性。
(3)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成前述图案的硅基底上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化，形成覆盖第一导电层图案的第二绝缘层，第二绝缘层上设置有多个过孔，如图7所示。
在示例性实施方式中，每个子像素中的多个过孔可以至少包括第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9和第十过孔V10。
在示例性实施方式中，第一过孔V1在硅基底上的正投影可以位于第一有源层1的第一区在硅基底上的正投影的范围之内，第一过孔V1内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层1的第一区的表面，第一过孔V1被配置为使后续形成的第二十一连接电极通过该过孔与第一有源层1的第一区连接。
在示例性实施方式中，第二过孔V2在硅基底上的正投影可以位于第一有源层1的第二区在硅基底上的正投影的范围之内，第二过孔V2内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层1的第二区的表面，第二过孔V2被配置为使后续形成的第二十二连接电极通过该过孔与第一有源层1的第二区连接。
在示例性实施方式中，第三过孔V3在硅基底上的正投影可以位于第二有源层2的第一区在硅基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层2的第一区的表面，第三过孔V3被配置为使后续形成的第二十三连接电极通过该过孔与第二有源层2的第一区连接。
在示例性实施方式中，第四过孔V4在硅基底上的正投影可以位于第二有源层2的第二区在硅基底上的正投影的范围之内，第四过孔V4内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层2的第二区的表面，第四过孔V4被配置为使后续形成的第二十四连接电极通过该过孔与第二有源层2的第二区连接。
在示例性实施方式中，第五过孔V5在硅基底上的正投影可以位于第三有源层3的第一区在硅基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层3的第一区的表面，第三过孔V3被配置为使后续形成的第二十五连接电极通过该过孔与第三有源层3的第一区连接。
在示例性实施方式中，第六过孔V6在硅基底上的正投影可以位于第三有源层3的第二区在硅基底上的正投影的范围之内，第六过孔V6内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层3的第二区的表面，第六过孔V6被配置为使后续形成的第二十四连接电极通过该过孔与第三有源层3的第二区连接。
在示例性实施方式中，第七过孔V7在硅基底上的正投影可以位于第一栅电极11的第一栅连接部11-2在硅基底上的正投影的范围之内，第七过孔V7内的第二绝缘层被刻蚀掉，暴露出第一栅连接部11-2的表面，第七过孔V7被配置为使后续形成的第一扫描信号线通过该过孔与第一栅连接部11-2连接，第七过孔V7可以作为本公开的第一栅过孔。
在示例性实施方式中，由于第一方向D1上相邻两个子像素的第一栅电极11为相互连接的一体结构，因而一体结构的第一栅电极11所在区域设置有两个第七过孔V7(第一栅过孔)，两个第七过孔V7分别位于一体结构的第一栅电极11第一方向D1的两端，使得同一个一体结构的第一栅电极11 可以通过两个第七过孔V7与后续形成的第一扫描信号线连接。
在示例性实施方式中，第八过孔V8在硅基底上的正投影可以位于第二栅电极12的第二栅连接部12-2在硅基底上的正投影的范围之内，第八过孔V8内的第二绝缘层被刻蚀掉，暴露出第二栅连接部12-2的表面，第八过孔V8被配置为使后续形成的第二十二连接电极通过该过孔与第二栅连接部12-2连接，第八过孔V8可以作为本公开的第二栅过孔。
在示例性实施方式中，第九过孔V9在硅基底上的正投影可以位于第三栅电极13的第三栅连接部13-2在硅基底上的正投影的范围之内，第九过孔V9内的第二绝缘层被刻蚀掉，暴露出第三栅连接部13-2的表面，第九过孔V9被配置为使后续形成的第二扫描信号线通过该过孔与第三栅连接部13-2连接，第九过孔V9可以作为本公开的第三栅过孔。
在示例性实施方式中，由于第一方向D1上相邻两个子像素的第三栅电极13为相互连接的一体结构，因而一体结构的第三栅电极13所在区域设置有两个第九过孔V9(第三栅过孔)，两个第九过孔V9分别位于一体结构的第三栅电极13第一方向D1的两端，使得同一个一体结构的第三栅电极13可以通过两个第九过孔V9与后续形成的第二扫描信号线连接。
在示例性实施方式中，第十过孔V10在硅基底上的正投影可以位于接触电极4在硅基底上的正投影的范围之内，第十过孔V10内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出接触电极4的表面，第十过孔V10被配置为使后续形成的参考信号线通过该过孔与接触电极4连接。
在示例性实施方式中，第八过孔V8和第十过孔V10可以为多个，以降低接触电阻并提高连接可靠性。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的硅基底上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成形成第二导电层图案，如图8A和图8B所示，图8B为图8A中第二导电层的示意图。在示例性实施方式中，第二导电层可以称为第一金属(Metal1)层。
在示例性实施方式中，每个子像素中的第二导电层图案可以至少包括：第二十一连接电极21、第二十二连接电极22、第二十三连接电极23、第二 十四连接电极24、第一扫描信号线26、第二扫描信号线27、偏置电压线28和偏置连接线29。
在示例性实施方式中，第二十一连接电极21的形状可以为矩形状，第二十一连接电极21可以通过第一过孔V1与第一有源层的第一区连接，第二十一连接电极21可以作为第一晶体管T1的第一极，第二十一连接电极21被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第二十二连接电极22的形状可以为“L”形状，第二十二连接电极22的第一端可以通过第二过孔V2与第一有源层的第二区连接，第二十二连接电极22的第二端向着第二栅电极12的方向弯折并延伸后，与通过第八过孔V8与第二栅电极12的第二栅连接部12-2连接，第二十二连接电极22可以作为第一晶体管T1的第二极，实现了第一晶体管T1的第二极与第二晶体管T2的第二栅电极12的连接。
在示例性实施方式中，第二十三连接电极23的形状可以为主体部分沿着第二方向D2延伸的条形状，第二十三连接电极23的第一端可以通过第三过孔V3与第二有源层的第一区连接，第二十三连接电极23的第二端沿着第二方向D2延伸到第二栅电极12的中部位置，第二十三连接电极23可以作为第二晶体管T2的第一极，第二十三连接电极23被配置为与后续形成的第三十二连接电极连接。
在示例性实施方式中，第二十四连接电极24的形状可以为矩形状，第二十四连接电极24的第一端可以通过第四过孔V4与第二有源层2的第二区连接，第二十四连接电极24的第二端可以通过第六过孔V6与第三有源层3的第二区连接，第二十四连接电极24可以同时作为第二晶体管T2的第二极和第三晶体管T3的第二极，即第二晶体管T2的第二极和第三晶体管T3的第二极为相互连接的一体结构，第二十四连接电极24被配置为与后续形成的第三十三连接电极连接。
在示例性实施方式中，第二十五连接电极25的形状可以为矩形状，第二十五连接电极25可以通过第五过孔V5与第三有源层3的第一区连接，第二十五连接电极25可以作为第三晶体管T3的第一极，第二十五连接电极25被配置为与后续形成的参考信号线连接。
在示例性实施方式中，第一扫描信号线26的形状可以为主体部分沿着第一方向D1延伸的线形状，第一扫描信号线26可以通过第七过孔V7与每个子像素的第一栅连接部11-2连接，因而实现了第一扫描信号线26与每个子像素的第一栅电极11的连接，第一扫描信号线26可以向每个子像素的第一晶体管T1提供控制第一晶体管T1导通或者断开的第一扫描信号。
在示例性实施方式中，由于第一方向D1上相邻两个子像素的第一栅电极11为相互连接的一体结构，一体结构的第一栅电极11所在区域设置有两个第七过孔V7(第一栅过孔)，因而第一扫描信号线26通过两个第七过孔V7与同一个一体结构的第一栅电极11连接。
在示例性实施方式中，第二扫描信号线27的形状可以为主体部分沿着第一方向D1延伸的线形状，第二扫描信号线27可以通过第九过孔V9与每个子像素的第三栅连接部13-2连接，因而实现了第二扫描信号线27与每个子像素的第三栅电极13的连接，第二扫描信号线27可以向每个子像素的第三晶体管T3提供控制第三晶体管T3导通或者断开的第二扫描信号。
在示例性实施方式中，由于第一方向D1上相邻两个子像素的第三栅电极13为相互连接的一体结构，一体结构的第三栅电极13所在区域设置有两个第九过孔V9(第三栅过孔)，因而第二扫描信号线27通过两个第九过孔V9与同一个一体结构的第三栅电极13连接。
在示例性实施方式中，第一扫描信号线26在硅基底上的正投影与第一栅电极11和第三栅电极13在硅基底上的正投影至少部分交叠，第二扫描信号线27在硅基底上的正投影与第一栅电极11和第三栅电极13在硅基底上的正投影至少部分交叠。本公开通过设置第一扫描信号线和第二扫描信号线均与第一栅电极和第三栅电极重叠，有助于减小第一扫描信号线和第二扫描信号线的占用面积，有利于减小像素驱动电路的占用面积，从而实现显示产品的分辨率。
在示例性实施方式中，每个子像素的偏置电压线28的形状可以为主体部分沿着第一方向D1延伸的线形状，偏置电压线28可以通过第十过孔V10与每个子像素的接触电极4连接，实现了偏置电压线28向接触电极4提供低电压，对硅基底进行低压偏置，实现对器件进行电隔离，降低器件之间的寄 生效应，提高像素驱动电路的稳定性。
在示例性实施方式中。在示例性实施方式中，每个子像素的偏置连接线29的形状可以为主体部分沿着第二方向D2延伸的条形状，可以设置在偏置电压线28第二方向D2的一侧或者两侧，且与偏置电压线28连接。每个子像素的偏置连接线29可以通过多个第十过孔V10与接触电极4连接，以降低接触电阻并提高连接可靠性。
在示例性实施方式中，第一扫描信号线26可以位于靠近第二十一连接电极21的一侧，第二扫描信号线27可以位于第一扫描信号线26远离第二十一连接电极21的一侧。
在示例性实施方式中，偏置电压线28可以位于第二十二连接电极22和第二十三连接电极23之间，偏置电压线28在硅基底上的正投影与第二栅电极12在硅基底上的正投影至少部分交叠。
在示例性实施方式中，偏置电压线28的宽度可以大于第一扫描信号线26的宽度，偏置电压线28的宽度可以大于第二扫描信号线27的宽度，以降低偏置电压线28的电阻，提高电源电压的均一性。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第二导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第二导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第二导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第二导电层图案可以相对于像素中心线A镜像对称。
(5)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的硅基底上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层图案的第三绝缘层，第三绝缘层上设置有多个过孔，如图9所示。
在示例性实施方式中，每个子像素中的多个过孔可以包括第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14和第十五过孔V15。
在示例性实施方式中，第十一过孔V11在硅基底上的正投影可以位于第二十一连接电极21在硅基底上的正投影的范围之内，第十一过孔V11内的 第三绝缘层被刻蚀掉，暴露出第二十一连接电极21的表面，第十一过孔V11被配置为使后续形成的数据信号线通过该过孔与第二十一连接电极21连接。
在示例性实施方式中，第十二过孔V12在硅基底上的正投影可以位于第二十二连接电极22在硅基底上的正投影的范围之内，第十二过孔V12内的第三绝缘层被刻蚀掉，暴露出第二十二连接电极22的表面，第十二过孔V12被配置为使后续形成的第三十一连接电极通过该过孔与第二十二连接电极22连接。
在示例性实施方式中，第十三过孔V13在硅基底上的正投影可以位于第二十三连接电极23在硅基底上的正投影的范围之内，第十三过孔V13内的第三绝缘层被刻蚀掉，暴露出第二十三连接电极23的表面，第十三过孔V13被配置为使后续形成的第三十二连接电极通过该过孔与第二十三连接电极23连接。
在示例性实施方式中，第十四过孔V14在硅基底上的正投影可以位于第二十四连接电极24在硅基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层被刻蚀掉，暴露出第二十四连接电极24的表面，第十四过孔V14被配置为使后续形成的第三十三连接电极通过该过孔与第二十四连接电极24连接。
在示例性实施方式中，第十五过孔V15在硅基底上的正投影可以位于第二十五连接电极25在硅基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层被刻蚀掉，暴露出第二十五连接电极25的表面，第十五过孔V15被配置为使后续形成的参考信号线通过该过孔与第二十五连接电极25连接。
在示例性实施方式中，第十一过孔V11至第十五过孔V15可以为多个，以降低接触电阻并提高连接可靠性。
(6)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的硅基底上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第三绝缘层上形成形成第三导电层图案，如图10A和图10B所示，图10B为图10A中第三导电层的示意图。在示例性实施方式中，第三导电层可以称为第二金属(Metal2)层。
在示例性实施方式中，每个子像素中的第三导电层图案可以至少包括： 第三十一连接电极31、第三十二连接电极32、第三十三连接电极33、数据信号线34和参考信号线35。
在示例性实施方式中，第三十一连接电极31的形状可以为沿着第二方向D2延伸的条形状，第三十一连接电极31第二方向D2的反方向的端部(靠近第二晶体管T2的端部)可以通过第十二过孔V12与第二十二连接电极22连接，第三十一连接电极31被配置为与后续形成的第四十一连接电极连接。
在示例性实施方式中，第三十二连接电极32的形状可以为矩形状，第三十二连接电极32可以通过第十三过孔V13与第二十三连接电极23连接，第三十二连接电极32被配置为与后续形成的发光电压线连接。
在示例性实施方式中，第三十三连接电极33的形状可以为沿着第二方向D2延伸的折线形状，第三十三连接电极33第二方向D2的端部(靠近第三晶体管T3的端部)可以通过第十四过孔V14与第二十四连接电极24连接，第三十三连接电极33被配置为与后续形成的第四十二连接电极连接。
在示例性实施方式中，数据信号线34的形状可以为沿着第二方向D2延伸的线形状，数据信号线34可以通过第十一过孔V11与第二十一连接电极21连接。由于第二十一连接电极21与第一有源层的第一区连接，因而实现了数据信号线34将数据信号写入第一晶体管T1的第一极。
在示例性实施方式中，参考信号线35的形状可以为沿着第二方向D2延伸的线形状，参考信号线35可以通过第十五过孔V15与第二十五连接电极25连接。由于第二十五连接电极25与第三有源层的第一区连接，因而实现了参考信号线35将参考信号写入第三晶体管T3的第一极。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第三导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第三导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第三导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第三导电层图案可以相对于像素中心线A镜像对称。
(7)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的硅基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层图案的第四绝缘层，第四 绝缘层上设置有多个过孔，如图11所示。
在示例性实施方式中，每个子像素中的多个过孔可以包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在硅基底上的正投影可以位于第三十一连接电极31第二方向D2的端部在硅基底上的正投影的范围之内，第二十一过孔V21内的第四绝缘层被刻蚀掉，暴露出第三十一连接电极31的表面，第二十一过孔V21被配置为使后续形成的第四十一连接电极通过该过孔与第三十一连接电极31连接。
在示例性实施方式中，第二十二过孔V22在硅基底上的正投影可以位于第三十二连接电极32在硅基底上的正投影的范围之内，第二十二过孔V22内的第四绝缘层被刻蚀掉，暴露出第三十二连接电极32的表面，第二十二过孔V22被配置为使后续形成的发光电压线通过该过孔与第三十二连接电极32连接。
在示例性实施方式中，第二十三过孔V23在硅基底上的正投影位于第三十三连接电极33第二方向D2的反方向的端部在硅基底上的正投影的范围之内，第二十三过孔V23内的第四绝缘层被刻蚀掉，暴露出第三十三连接电极33的表面，第二十三过孔V23被配置为使后续形成的第四十二连接电极通过该过孔与第三十三连接电极33连接。
(8)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的硅基底上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，在第四绝缘层上形成第四导电层图案，如图12A和图12B所示，图12B为图12A中第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第三金属(Metal3)层。
在示例性实施方式中，每个子像素中的第四导电层图案可以至少包括：第四十一连接电极41、第四十二连接电极42和发光电压线43。
在示例性实施方式中，第四十一连接电极41的形状可以为“T”形状，第四十一连接电极41可以通过第二十一过孔V21与第三十一连接电极31连接，第四十一连接电极41被配置为与后续形成的第五十一连接电极连接。
在示例性实施方式中，第四十二连接电极42的形状可以为“T”形状，第四十二连接电极42可以通过第二十三过孔V23与第三十三连接电极33连接，第四十二连接电极42被配置为与后续形成的第五十二连接电极连接。
在示例性实施方式中，发光电压线43的形状可以为主体部分沿着第一方向D1延伸的线形状，发光电压线43可以通过第二十二过孔V22与第三十二连接电极32连接。由于发光电压线43与位于边框区域的发光控制晶体管的第二极连接，被配置为输出发光电压信号，第三十二连接电极32通过过孔与第二十三连接电极23连接，第二十三连接电极23通过过孔与第二有源层的第一区连接，因而实现了发光电压线43将发光电压信号写入第二晶体管T2的第一极。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第四导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第四导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第四导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第四导电层图案可以相对于像素中心线A镜像对称。
(9)形成第五绝缘层图案。在示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的硅基底上沉积第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第四导电层图案的第五绝缘层，第五绝缘层上设置有多个过孔，如图13所示。
在示例性实施方式中，每个子像素中的多个过孔可以包括：第三十一过孔V31和第三十二过孔V32。
在示例性实施方式中，第三十一过孔V31在硅基底上的正投影位于第四十一连接电极41在硅基底上的正投影的范围之内，第三十一过孔V31内的的第五绝缘层被刻蚀掉，暴露出第四十一连接电极41的表面，第三十一过孔V31被配置为使后续形成的第五十一连接电极通过该过孔与第四十一连接电极41连接。
在示例性实施方式中，第三十二过孔V32在硅基底上的正投影位于第四十二连接电极42在硅基底上的正投影的范围之内，第三十二过孔V32内的第五绝缘层被刻蚀掉，暴露出第四十二连接电极42的表面，第三十二过孔 V32被配置为使后续形成的第五十二连接电极通过该过孔与第四十二连接电极41连接。
在示例性实施方式中，多个第三十一过孔V31和多个第三十二过孔V32可以沿着第一方向D1依次设置，以降低接触电阻并提高连接可靠性。
(10)形成第五导电层图案。在示例性实施方式中，形成第五导电层图案可以包括：在形成前述图案的硅基底上沉积第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，在第五绝缘层上形成第五导电层图案，如图14A和图14B所示，图14B为图14A中第五导电层的示意图。在示例性实施方式中，第五导电层可以称为第四金属(Metal4)层。
在示例性实施方式中，每个子像素中的第五导电层图案可以至少包括：第五十一连接电极51和第五十二连接电极52。
在示例性实施方式中，第五十一连接电极51的形状可以为沿着第一方向D1延伸的条形状，第五十一连接电极51可以通过多个第三十一过孔V31与第四十一连接电极41连接，第五十一连接电极51被配置为与后续形成的第一极板连接。
在示例性实施方式中，第五十二连接电极52的形状可以为沿着第一方向D1延伸的条形状，第五十二连接电极52可以通过多个第三十二过孔V32与第四十二连接电极42连接，第五十二连接电极52被配置为与后续形成的第六十一连接电极连接。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第五导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第五导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第五导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第五导电层图案可以相对于像素中心线A镜像对称。
(11)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的硅基底上沉积第六绝缘薄膜，通过图案化工艺对第六绝缘薄膜进行图案化，形成覆盖第五导电层图案的第六绝缘层，第六绝缘层上设置有多个过孔，如图15所示。
在示例性实施方式中，每个子像素中的多个过孔可以包括：第四十一过孔V41和第四十二过孔V42。
在示例性实施方式中，第四十一过孔V41在硅基底上的正投影位于第五十一连接电极51在硅基底上的正投影的范围之内，第四十一过孔V41内的第六绝缘层被刻蚀掉，暴露出第五十一连接电极51的表面，第四十一过孔V41被配置为使后续形成的第一极板通过该过孔与第五十一连接电极51连接。
在示例性实施方式中，第四十二过孔V42在硅基底上的正投影位于第五十二连接电极52在硅基底上的正投影的范围之内，第四十二过孔V42内的第六绝缘层被刻蚀掉，暴露出第五十二连接电极52的表面，第四十二过孔V42被配置为使后续形成的第六十一连接电极通过该过孔与第五十二连接电极52连接。
在示例性实施方式中，多个第四十一过孔V41和多个第四十二过孔V42可以沿着第一方向D1依次设置，以降低接触电阻并提高连接可靠性。
(12)形成第六导电层图案。在示例性实施方式中，形成第六导电层图案可以包括：在形成前述图案的硅基底上沉积第六导电薄膜，通过图案化工艺对第六导电薄膜进行图案化，在第六绝缘层上形成第六导电层图案，如图16A和图16B所示，图16B为图16A中第六导电层的示意图。在示例性实施方式中，第六导电层可以称为第五金属(Metal5)层。
在示例性实施方式中，每个子像素中的第六导电层图案可以至少包括：第六十一连接电极61和存储电容的第一极板91。
在示例性实施方式中，第六十一连接电极61的形状可以为矩形状，第六十一连接电极61可以通过多个第四十二过孔V42与第五十二连接电极52连接，第六十一连接电极61被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，存储电容的第一极板91的形状可以为矩形状，第一极板91可以通过多个第四十一过孔V41与第五十一连接电极51连接，第一极板91被配置为作为存储电容的一个极板。由于第五十一连接电极51通过过孔与第四十一连接电极41连接，第四十一连接电极41通过过孔与第三十一连接电极31连接，第三十一连接电极31通过过孔与第二十二连接电极 22连接，第二十二连接电极22分别通过过孔与第一有源层的第二区和第二晶体管T2的栅电极连接，因而实现了第一极板91、第一晶体管T1的第二极和第二晶体管T2的栅电极具有相同的电位(像素驱动电路的第一节点N1)。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第六导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第六导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第六导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第六导电层图案可以相对于像素中心线A镜像对称。
(13)形成第七导电层图案。在示例性实施方式中，形成第七导电层图案可以包括：在形成前述图案的硅基底上依次沉积第七绝缘薄膜和第七导电薄膜，通过图案化工艺对第七导电薄膜进行图案化，形成覆盖第六导电层图案的第七绝缘层，以及设置在第七绝缘层上的第七导电层图案，如图17A和图17B所示，图17B为图17A中第七导电层的示意图。在示例性实施方式中，第七导电层可以称为金属-绝缘体-金属(Metal-Insulator-Metal，简称MIM)层。
在示例性实施方式中，每个子像素中的第七导电层可以至少包括：存储电容的第二极板92。
在示例性实施方式中，第二极板92的形状可以为矩形状，第二极板92在硅基底上的正投影与第一极板91在硅基底上的正投影至少部分交叠，第二极板92被配置为作为存储电容的另一个极板，第一极板91和第二极板92构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板92的面积可以小于第一极板91的面积，第二极板92在硅基底上的正投影可以位于第一极板91在硅基底上的正投影的范围之内。
在示例性实施方式中，第一方向D1上相邻的两个子像素的第七导电层图案可以相对于像素中心线A镜像对称，在第二方向D2上相邻的两个子像素的第七导电层图案可以基本上相同。例如，第一子像素P1和第二子像素P2的第七导电层图案可以相对于像素中心线A镜像对称。又如，第二子像素P2和第三子像素P3的第七导电层图案可以相对于像素中心线A镜像对称。
(14)形成第八绝缘层图案。在示例性实施方式中，形成第八绝缘层图案可以包括：在形成前述图案的硅基底上沉积第八绝缘薄膜，通过图案化工艺对第八绝缘薄膜进行图案化，形成覆盖第七导电层图案的第八绝缘层，第八绝缘层上设置有多个过孔，如图18所示。
在示例性实施方式中，每个子像素中的多个过孔可以至少包括：第五十一过孔V51和第五十二过孔V52。
在示例性实施方式中，第五十一过孔V51在硅基底上的正投影位于第六十一连接电极61在硅基底上的正投影的范围之内，第五十一过孔V51内的第七绝缘层和第八绝缘层被刻蚀掉，暴露出第六十一连接电极61的表面，第五十一过孔V51被配置为使后续形成的阳极连接电极通过该过孔与第六十一连接电极61连接。
在示例性实施方式中，第五十二过孔V52在硅基底上的正投影位于第二极板92在硅基底上的正投影的范围之内，第五十二过孔V52内的第八绝缘层被刻蚀掉，暴露出第二极板92的表面，第五十二过孔V52被配置为使后续形成的第一电源线通过该过孔与第二极板92连接。
(15)形成第八导电层图案。在示例性实施方式中，形成第八导电层图案可以包括：在形成前述图案的硅基底上沉积第八导电薄膜，通过图案化工艺对第八导电薄膜进行图案化，在第八绝缘层上形成第八导电层图案，如图19A和图19B所示，图19B为图19A中第八导电层的示意图。在示例性实施方式中，第八导电层可以称为第六金属(Metal6)层或者第二金属连接(TM2)层。
在示例性实施方式中，每个子像素中的第八导电层可以至少包括：阳极连接电极71、电源电极72和第一电源线73。
在示例性实施方式中，阳极连接电极71的形状可以为矩形状，阳极连接电极71可以通过第五十一过孔V51与第六十一连接电极61连接，阳极连接电极71被配置为与后续形成的阳极连接。由于第六十一连接电极61通过过孔与第五十二连接电极52连接，第五十二连接电极52通过过孔与第四十二连接电极42连接，第四十二连接电极42通过过孔与第三十三连接电极33连接，第三十三连接电极33通过过孔与第二十四连接电极24连接，第二十 四连接电极24分别通过过孔与第二有源层的第二区和第三有源层的第二区连接，因而可以实现后续形成的阳极与第二晶体管T2的第二极和第三晶体管T3的第二极(像素驱动电路的第二节点N2)的连接，可以将像素驱动电路输出的电流提供给阳极。
在示例性实施方式中，电源电极72的形状可以为矩形状，电源电极72可以通过第五十二过孔V52与第二极板92连接。第一电源线73的形状可以为沿着第一方向D1延伸的线形状，第一电源线73与每个子像素的电源电极72连接，使得第二极板92具有第一电源线73的电位。
在示例性实施方式中，电源电极72和第一电源线73可以为相互连接的一体结构。
在示例性实施方式中，由于第二极板92具有第一电源线73的电位，第一极板91具有像素驱动电路的第一节点N1的电位，因而第一极板91和第二极板92构成MIM电容结构的存储电容。本公开通过采用MIM电容结构，单位面积的容值较高，可以满足高PPI所需的电容容量，可以提高像素驱动电路的驱动能力。
在示例性实施方式中，后续制备过程可以包括形成阳极、像素定义层、有机发光层、阴极、第一封装层、彩膜结构层和第二封装层等工艺，这里不再赘述。
本公开示例性实施例显示装置的结构及其制备过程仅仅是一种示例性说明，可以根据实际情况变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，第一绝缘层至第八绝缘层可以采用硅氧化物SiOx、硅氮化物SiNx或氮氧化硅SiON等，可以是单层结构，或者可以是多层复合结构。第一金属层至第六金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)或钼(Mo)等，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，合金材料可以是单层结构，或者可以是多层复合结构，如Mo层、Cu层和Mo层组成的复合结构等。在示例性实施方式中，过孔的平面形状可以为矩形、圆形或者椭圆等，多个过孔的尺寸可以相同，或者可以不同，本公开在此不做限定。
图20为本公开示例性实施例一种显示基板的等效电路图。如图20所示，显示基板可以包括显示区域AA和边框区域BK，边框区域BK可以设置在显示区域AA的一侧。
在示例性实施方式中，显示区域AA可以包括形成多个像素行和多个像素列的多个子像素，至少一个子像素可以包括像素驱动电路，像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C，像素驱动电路分别与第一扫描信号线26、第二扫描信号线27、数据信号线34、参考信号线35、发光电压线43、第一电源线73和发光器件XL的第一极连接，发光器件XL的第二极与第二电源线VSS连接。第一扫描信号线26、第二扫描信号线27、发光电压线43和第一电源线73可以沿着像素行方向延伸，与一个像素行中多个子像素中的像素驱动电路连接。数据信号线34和参考信号线35可以沿着像素列方向延伸，与一个像素列中多个子像素中的像素驱动电路连接。
在示例性实施方式中，边框区域BK可以包括栅极驱动电路、发光控制电路和边框电源引线。
在示例性实施方式中，栅极驱动电路可以包括多个级联的栅极驱动单元(移位寄存器)，栅极驱动电路可以与每个像素行的第一扫描信号线26和第二扫描信号线27，分别向第一扫描信号线26和第二扫描信号线27输出第一扫描信号和第二扫描信号。
在示例性实施方式中，发光控制电路可以至少包括发光控制晶体管T4，发光控制晶体管T4的栅电极与发光控制线E连接，发光控制晶体管T4的第一极与边框电源引线F连接，发光控制晶体管T4的的第二极与每个像素行的发光电压线43连接，发光控制晶体管T4被配置为在发光控制线E的控制下，向发光电压线43输出发光电压。
在示例性实施方式中，边框电源引线F与第一电源线73连接，向第一电源线73持续输出高电平信号。
在示例性实施方式中，边框区域的栅极驱动电路、发光控制电路和边框电源引线可以与显示区域的像素驱动电路同步制备形成，这里不再赘述。
通过本公开示例性实施例显示装置的结构及其制备过程可以看出，本公 开通过采用栅电极搭接位置均设置在同一间隔、栅电极共用、漏电极共用、子像素翻转等最小化设计，最大限度地提高了显示基板的PPI，实现了业内Real RGB硅基OLED最高PPI设计。本公开通过将第一扫描信号线与第一晶体管T1的栅电极连接的过孔、第二扫描信号线与第三晶体管T3的栅电极连接的过孔以及第一晶体管T1的第二极与第二晶体管T2的栅电极连接的过孔均设置在子像素的间隙区，形成子像素内栅电极搭接位置均位于同一间隙区域的结构。本公开通过将第一方向上相邻两个子像素的第一晶体管T1、第二晶体管T2和第三晶体管T3相对于像素中心线镜像对称，形成子像素相对于像素中心线水平翻转的结构，使得相邻两个子像素的第一栅电极为相互连接的一体结构，相邻两个子像素的第三栅电极为相互连接的一体结构，形成相邻子像素栅电极共用的结构。本公开通过将第二晶体管T2和第三晶体管T3沿着第二方向排布，使得第二晶体管T2的第二极和第三晶体管T3的第二极为相互连接的一体结构，形成子像素内漏电极共用的结构。本公开通过采用MIM电容结构不仅增大了存储电容的电容值，保证了像素驱动电路输出电流的稳定性，保证了OLED亮度的稳定性。本公开通过上述结构设计优化了像素驱动电路的布局，优化了布局空间，减小了像素驱动电路的占用面积，最大限度地提高了显示基板的PPI，实现了业内Real RGB硅基OLED最高PPI设计，分辨率可以达到4k*4k，可以实现较高显示品质和显示效果。
本公开示例性实施例还提供了一种显示基板的制备方法。在示例性实施方式中，所述显示基板包括显示区域和边框区域，所述显示区域包括形成像素行和像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述制备方法可以包括：
形成所述第一晶体管、第二晶体管、第三晶体管、第一扫描信号线和第 二扫描信号线，所述第一有源层设置在所述第一区，所述第二有源层和第三有源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一栅电极通过第一栅过孔与第一扫描信号线连接，所述第二栅电极通过第二栅过孔与所述第一晶体管的第二极连接，所述第三栅电极通过第三栅过孔与第二扫描信号线连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
本公开示例性实施例还提供了一种显示装置，包括前述的显示基板。本公开显示装置可以用于虚拟现实设备或增强显示设备等，显示装置还可以用于包括但不限于为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪或者任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但上述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示基板，包括显示区域和边框区域，所述显示区域包括形成多个像素行和多个像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述第一有源层设置在所述第一区，所述第二有源层和第三有源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一扫描信号线通过第一栅过孔与所述第一栅电极连接，所述第一晶体管的第二极通过第二栅过孔与所述第二栅电极连接，所述第二扫描信号线通过第三栅过孔与所述第三栅电极连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
  2. 根据权利要求1所述的显示基板，其中，沿着所述像素行方向，所述第一区具有第一宽度，所述第二区具有第二宽度，所述间隙区具有第三宽度，所述第三宽度小于或等于0.5*第一宽度，所述第三宽度小于或等于0.5*第二宽度。
  3. 根据权利要求1所述的显示基板，其中，所述像素行上相邻的两个子像素的第一栅电极为相互连接的一体结构，所述像素行上相邻的两个子像素的第三栅电极为相互连接的一体结构。
  4. 根据权利要求3所述的显示基板，其中，所述一体结构的第一栅电极通过两个第一栅过孔与所述第一扫描信号线连接，所述一体结构的第三栅电极通过两个第三栅过孔与所述第二扫描信号线连接。
  5. 根据权利要求1所述的显示基板，其中，所述像素行上相邻的两个子像素的所述第一晶体管、所述第二晶体管和所述第三晶体管相对于像素中心线镜像对称，所述像素中心线是位于所述像素行上相邻的两个子像素之间且 沿着所述像素列方向延伸的直线。
  6. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述第一栅电极包括相互连接的第一栅主体部和第一栅连接部，所述第一栅连接部设置在所述间隙区，所述第一扫描信号线通过所述第一栅过孔与所述第一栅连接部连接。
  7. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述第二栅电极包括相互连接的第二栅主体部和第二栅连接部，所述第二栅连接部设置在所述间隙区，所述所述第一晶体管的第二极通过所述第二栅过孔与所述第二栅连接部连接。
  8. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述第三栅电极包括相互连接的第三栅主体部和第三栅连接部，所述第三栅连接部设置在所述间隙区，所述第二扫描信号线通过所述第三栅过孔与所述第三栅连接部连接。
  9. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述第一栅电极包括相互连接的第一栅主体部和第一栅连接部，所述第一栅连接部设置所述第一栅主体部靠近所述第三栅电极的一侧，所述第三栅电极包括相互连接的第三栅主体部和第三栅连接部，所述第三栅连接部设置在所述第三栅主体部靠近所述第一栅电极的一侧，所述第一栅连接部和所述第三栅连接部在所述像素列方向上错位设置。
  10. 根据权利要求9所述的显示基板，其中，所述第一栅主体部和第一栅连接部远离所述第二晶体管一侧的边缘平齐，所述第三栅主体部和第三栅连接部靠近所述第二晶体管一侧的边缘平齐。
  11. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述第二栅电极包括相互连接的第二栅主体部和第二栅连接部，所述第二栅连接部设置在所述间隙区，所述第二栅主体部和第二栅连接部靠近所述第三晶体管一侧的边缘平齐。
  12. 根据权利要求1所述的显示基板，其中，所述第一扫描信号线和第二扫描信号线的形状为主体部分沿着所述像素行方向延伸的线形状，所述第一扫描信号线在所述显示基板的平面上的正投影与所述第一栅电极和第三栅 电极在所述显示基板的平面上的正投影至少部分交叠，所述第二扫描信号线在所述显示基板的平面上的正投影与所述第一栅电极和第三栅电极在所述显示基板的平面上的正投影至少部分交叠。
  13. 根据权利要求1所述的显示基板，其中，所述第二晶体管还包括第二晶体管的第一极和第二晶体管的第二极，所述第三晶体管还包括第三晶体管的第一极和第三晶体管的第二极，所述第一源电极与数据信号线连接，所述第二晶体管的第一极与发光电压线连接，所述第三晶体管的第一极与参考信号线连接，所述第二晶体管的第二极和所述第三晶体管的第二极为相互连接的一体结构。
  14. 根据权利要求1所述的显示基板，其中，至少一个子像素中，所述像素驱动电路还包括存储电容，所述存储电容包括第一极板和第二极板，所述第一极板在所述显示基板的平面上的正投影与所述第二极板在所述显示基板的平面上的正投影至少部分交叠，所述第一极板通过连接电极与所述第一晶体管的第二极连接，所述第二极板与第一电源线连接。
  15. 根据权利要求1所述的显示基板，其中，至少一个子像素还包括接触电极，所述接触电极设置在所述第一区，所述接触电极设置在所述第一有源层所述像素列方向的一侧。
  16. 根据权利要求15所述的显示基板，其中，至少一个子像素还包括偏置电压线，所述偏置电压线通过过孔与所述接触电极连接，所述偏置电压线在所述显示基板的平面上的正投影与所述第二栅电极在所述显示基板的平面上的正投影至少部分交叠。
  17. 根据权利要求16所述的显示基板，其中，至少一个子像素中，所述接触电极的形状为沿着所述像素列方向延伸的条形状，所述偏置电压线的形状为沿着所述像素行方向延伸的线形状，所述偏置电压线所述像素列方向的一侧或者两侧连接有偏置连接线，所述偏置连接线在所述显示基板的平面上的正投影与所述接触电极在所述显示基板的平面上的正投影至少部分交叠，所述偏置连接线通过过孔与所述接触电极连接。
  18. 根据权利要求17所述的显示基板，其中，所述偏置电压线和所述偏置连接线为相互连接的一体结构。
  19. 根据权利要求1所述的显示基板，其中，所述边框区域至少包括发光控制晶体管，所述发光控制晶体管的栅电极与发光控制线连接，所述发光控制晶体管的第一极与边框电源引线连接，所述发光控制晶体管的第二极与发光电压线连接，所述发光电压线与一个像素行中多个子像素的第二晶体管的第一极连接，所述边框电源引线与第一电源线连接。
  20. 根据权利要求1至19任一项所述的显示基板，其中，垂直于所述显示基板的平面上，所述显示基板至少包括在硅基底上依次设置的第一导电层和第二导电层，所述硅基底至少包括所述第一有源层、第二有源层和第三有源层，所述第一导电层至少包括所述第一栅电极、第二栅电极和第三栅电极，所述第二导电层至少包括所述第一扫描信号线和第二扫描信号线。
  21. 根据权利要求20所述的显示基板，其中，所述显示基板还包括设置在所述第二导电层远离所述硅基底一侧的第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层，所述第三导电层至少包括数据信号线和参考信号线，所述第四导电层至少包括发光电压线，所述第六导电层至少包括存储电容的第一极板，所述第七导电层至少包括存储电容的第二极板，所述第八导电层至少包括阳极连接电极和第一电源线。
  22. 一种显示装置，包括1至21任一项所述的显示基板。
  23. 一种显示基板的制备方法，所述显示基板包括显示区域和边框区域，所述显示区域包括形成像素行和像素列的多个子像素，所述子像素包括沿着像素行方向依次设置的第一区、间隙区和第二区；至少一个子像素包括像素驱动电路、第一扫描信号线和第二扫描信号线，所述像素驱动电路至少包括第一晶体管、第二晶体管和第三晶体管，所述第一扫描信号线被配置为控制所述第一晶体管的导通或者断开，所述第二扫描信号线被配置为控制所述第二晶体管的导通或者断开；所述第一晶体管至少包括第一栅电极、第一有源层和第一晶体管的第一极和第一晶体管的第二极，所述第二晶体管至少包括第二栅电极和第二有源层，所述第三晶体管至少包括第三栅电极和第三有源层；所述制备方法包括：
    形成所述第一晶体管、第二晶体管、第三晶体管、第一扫描信号线和第二扫描信号线，所述第一有源层设置在所述第一区，所述第二有源层和第三 有源层设置在所述第二区，所述第二有源层设置在所述第三有源层像素列方向的一侧；所述第一栅电极通过第一栅过孔与第一扫描信号线连接，所述第二栅电极通过第二栅过孔与所述第一晶体管的第二极连接，所述第三栅电极通过第三栅过孔与第二扫描信号线连接，所述第一栅过孔、第二栅过孔和第三栅过孔设置在所述间隙区。
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