WO2022267531A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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WO2022267531A1
WO2022267531A1 PCT/CN2022/079199 CN2022079199W WO2022267531A1 WO 2022267531 A1 WO2022267531 A1 WO 2022267531A1 CN 2022079199 W CN2022079199 W CN 2022079199W WO 2022267531 A1 WO2022267531 A1 WO 2022267531A1
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transistor
electrode
substrate
electrically connected
pole
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PCT/CN2022/079199
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English (en)
French (fr)
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赵梦
关峰
刘威
刘凤娟
史鲁斌
宁策
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京东方科技集团股份有限公司
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Priority to US18/022,924 priority Critical patent/US20230329037A1/en
Publication of WO2022267531A1 publication Critical patent/WO2022267531A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present application relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display panel.
  • OLED Organic Light-Emtting Diode, Organic Light-Emitting Diode
  • wearable devices such as smart watches, etc.
  • an LTPO backplane drive circuit that is, a backplane structure combining LTPS-TFT (low temperature polysilicon thin film transistor) and oxide-TFT (oxide thin film transistor).
  • This structure uses LTPS-TFT as the driving TFT of the OLED element, and oxide-TFT as the switching TFT. It not only utilizes the characteristics of fast response speed and large turn-on current of LTPS-TFT to provide a current source for OLED display; at the same time, it utilizes the characteristics of low leakage of oxide-TFT to reduce the power consumption of the backplane. This low-power design is more suitable for wearable devices.
  • the size of the oxide-TFT is relatively large; at the same time, the oxide-TFT is an NMOS transistor, while the LTPS-TFT is a PMOS transistor. High resolution display panel.
  • Embodiments of the present application provide a display substrate, a manufacturing method thereof, and a display panel.
  • the display panel can greatly improve resolution while ensuring low power consumption.
  • a display substrate including a substrate and a plurality of sub-pixels arranged in an array on one side of the substrate;
  • the sub-pixel includes a storage capacitor, a polysilicon transistor, and at least one oxide transistor; wherein, the storage capacitor includes a first electrode and a second electrode that are oppositely arranged, and the first electrode is arranged at a distance from the second electrode to the one side of the substrate;
  • the second electrode is arranged on the same layer as the gate of the polysilicon transistor; the oxide transistor is arranged on a side of the first electrode away from the substrate, and the first electrode is connected to at least one of the oxide transistors.
  • the active layers of the transistors overlap at least partially in a direction perpendicular to the substrate;
  • the first electrode is configured to receive a power supply signal and also serve as a bottom gate of an overlapped oxide transistor, wherein the oxide layer at least partially overlaps with the first electrode along a direction perpendicular to the substrate.
  • the physical transistor is the staggered oxide transistor.
  • the orthographic projection of the active layer of at least one oxide transistor on the substrate is located within the orthographic projection of the first electrode on the substrate.
  • the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate.
  • the display substrate further includes a power line, and the first electrode is electrically connected to the power line.
  • the power line is arranged on the same layer as the first electrode and the second electrode of the overlapping oxide transistor.
  • the polysilicon transistor is a top-gate polysilicon transistor, and the active layer of the polysilicon transistor is disposed between the substrate and the gate of the polysilicon transistor.
  • the first pole and the second pole of the polysilicon transistor are arranged in the same layer as the first pole and the second pole of the overlapping oxide transistor.
  • the sub-pixel further includes an anode, and one of the first pole and the second pole of the polysilicon transistor is electrically connected to the anode.
  • the polysilicon transistor is a P-type transistor
  • the oxide transistor is an N-type transistor.
  • the sub-pixel further includes a single-gate oxide transistor, and the active layer of the single-gate oxide transistor does not overlap with the first electrode along a direction perpendicular to the substrate.
  • the sub-pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the first transistor and the second transistor are all The oxide transistor, the third transistor is the polysilicon transistor;
  • the display substrate also includes power lines, light emission control signal lines, data signal lines, reset control signal lines, and initial signal lines; the sub-pixels also include light-emitting diodes;
  • the gate of the first transistor is electrically connected to the reset control signal line
  • the second pole is electrically connected to the initial signal line
  • the first pole of the first transistor, the first pole of the second transistor are connected to the first
  • the nodes are electrically connected
  • the gate of the third transistor and the second electrode of the storage capacitor are electrically connected to the first node, and the first electrode of the storage capacitor is electrically connected to the power line;
  • the gate of the second transistor is electrically connected to the reset control signal line, the second pole is electrically connected to the third node, the first pole of the third transistor is electrically connected to the second node, and the second pole is electrically connected to the The third node is electrically connected, the first pole of the fourth transistor is electrically connected to the second node, the second pole is electrically connected to the data signal line, and the gate is electrically connected to the reset control signal line.
  • the second pole of the fifth transistor is electrically connected to the second node, the first pole is electrically connected to the power supply line, and the gate is electrically connected to the light emission control signal line;
  • the gate of the sixth transistor is electrically connected to the light emission control signal line, the first pole is electrically connected to the third node, the second pole is electrically connected to the fourth node, the gate of the seventh transistor is electrically connected to the
  • the reset control signal line is electrically connected, the first pole is electrically connected to the fourth node, the second pole is electrically connected to the initial signal line, the anode of the light emitting diode is electrically connected to the fourth node, and the cathode is grounded;
  • the orthographic projections of the active layers of the first transistor and the second transistor on the substrate are located within the orthographic projection of the first electrode on the substrate, and the active layers of the remaining transistors The orthographic projection on the substrate does not overlap the orthographic projection of the first electrode on the substrate.
  • a display panel including the above-mentioned display substrate.
  • a method for preparing the above display substrate including:
  • the multiple sub-pixels arranged in an array on the substrate include:
  • the storage capacitor includes a first electrode and a second electrode that are oppositely arranged, and the first electrode is arranged on a side where the second electrode is far away from the substrate side; the second electrode is set on the same layer as the gate of the polysilicon transistor; the oxide transistor is set on the side of the first electrode away from the substrate, and the first electrode and at least one of the The active layer of the oxide transistor overlaps at least partially along a direction perpendicular to the substrate; the first electrode is configured to receive a power signal and also serves as a bottom gate of the overlapped oxide transistor, wherein, with the The oxide transistors whose first electrodes at least partially overlap in a direction perpendicular to the substrate are the overlapped oxide transistors.
  • forming the storage capacitor and the polysilicon transistor includes:
  • the second electrode of the storage capacitor and the gate of the polysilicon transistor are formed by one patterning process.
  • forming the polysilicon transistor and the overlapping oxide transistor includes:
  • the first pole and the second pole of the polysilicon transistor and the first pole and the second pole of the overlapping oxide transistor are formed by one patterning process.
  • Fig. 1 is the structural representation of a kind of LTPO substrate provided by the embodiment of the present application.
  • Fig. 2 is the circuit diagram of a kind of 7T1C provided by the embodiment of the present application.
  • Fig. 3 is a layout of a 7T1C adopting the structure of Fig. 1;
  • FIG. 4 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • Fig. 5 is a layout of a 7T1C adopting the structure of Fig. 4;
  • Figure 6-13 is a flowchart structure diagram for preparing the structure of Figure 13 provided by the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another display substrate provided by the embodiment of the present application.
  • FIG. 15 is a schematic diagram of a test structure of a display substrate provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of an equivalent structure of FIG. 15 .
  • plural means two or more, and “at least one” means one or more, unless otherwise specifically defined.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or None to imply that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation should therefore not be construed as limiting the application.
  • the transistor includes a gate, a source and a drain, and one of the source and the drain is called a first pole, and the other is called a second pole.
  • the LTPO substrate may include an LTPS drive tube 103, an oxide switch tube 105, and a Cst capacitor 100 as shown in FIG.
  • the gate 104 of the drive transistor 103 and the second pole 102 of the Cst capacitor 100 are arranged on the same layer, and the first pole 101 of the Cst capacitor 100 and the bottom gate 106 of the oxide switch transistor 105 are arranged on the same layer; in FIG.
  • the LTPO substrate also includes PI (polyimide) substrate 107, first GI layer 108, first ILD layer 109, second ILD layer 110, Buffer layer 111, second GI layer 112, second ILD layer 113, first PLN layer 114 , the second PLN layer 115 , the Anode layer 117 , the PDL layer 118 and the PS layer 119 , this structure can be made by using 13 Masks.
  • the LTPO substrate can use the 7T1C drive circuit shown in Figure 2, wherein the transistor T3 can use the LTPS drive tube shown in Figure 1, and the transistors T1 and T2 can use the oxide switch tube shown in Figure 1, the 7T1C drive circuit
  • the layout can be shown in Figure 3.
  • the Pitch (pitch) of the final sub-pixels is 56 ⁇ m, and the corresponding PPI (Pixels Per Inch, pixel density) is about 450.
  • the PPI can reach 630.
  • the PPI of LTPO panels needs to be further improved.
  • an embodiment of the present application provides a display substrate, including a substrate and a plurality of sub-pixels arranged in an array on one side of the substrate.
  • the sub-pixel includes a storage capacitor 2, a polysilicon transistor 1, and at least one oxide transistor 3; wherein, the storage capacitor 2 includes a first electrode 18 and a second electrode 16 that are oppositely arranged, and the first electrode 18 is arranged at the second electrode. The side of the second electrode 16 is away from the substrate 10 .
  • the second electrode 16 is set on the same layer as the gate 15 of the polysilicon transistor 1; the oxide transistor 3 is set on the side of the first electrode 18 away from the substrate 10, and the first electrode 18 is connected to at least one oxide transistor.
  • the active layer 20 of 3 at least partially overlaps along the direction perpendicular to the substrate.
  • the first electrode is configured to receive a power supply signal and is also used as a bottom gate of an overlapped oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode in a direction perpendicular to the substrate is an overlapped oxide transistor .
  • the specific structure of the driving circuit adopted by the above sub-pixels is not limited.
  • a 2T1C driving circuit, a 3T1C driving circuit or a 7T1C driving circuit may be used.
  • a 7T1C driving circuit as shown in FIG. 2 can be used.
  • a polysilicon transistor can be used as a driving transistor T3, and an oxide transistor can be used as a switching transistor T1 or T2.
  • the material of the active layer of the above-mentioned oxide transistor may be a metal oxide such as IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide, Indium Tin Zinc Oxide).
  • IGZO Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide, Indium Tin Zinc Oxide
  • the type of the above-mentioned polysilicon transistor is not limited, and it may be a top-gate polysilicon transistor, or may also be a bottom-gate polysilicon transistor.
  • FIG. 4 takes a top-gate polysilicon transistor as an example for illustration.
  • the at least partial overlap between the first electrode and the active layer of the at least one oxide transistor along the direction perpendicular to the substrate includes: the first electrode partially overlaps the active layer of the at least one oxide transistor along the direction perpendicular to the substrate, wherein When , the orthographic projection of the first electrode on the substrate may partially overlap the orthographic projection of the active layer of the at least one oxide transistor on the substrate; or, the first electrode and the active layer of the at least one oxide transistor along the Complete overlap perpendicular to the substrate direction, at this time, the orthographic projection of the active layer of the at least one oxide transistor on the substrate may be located within the orthographic projection of the first electrode on the substrate.
  • the above-mentioned overlapping oxide transistor may include a top gate, a bottom gate, a first electrode and a second electrode, wherein the first electrode of the storage capacitor is used as the bottom gate and is electrically connected to the power signal line, which can protect the channel and boost
  • the function of stability can also be used as a light-shielding layer to further protect the performance of the stacked oxide transistor.
  • the top gate and bottom gate of a double-gate transistor are connected to the same gate signal, but in this application, the top gate of the overlapped oxide transistor is connected to the gate signal, and the bottom gate (ie, the first electrode) is connected to the same gate signal.
  • Access the power signal VDD generally 4.6V DC voltage.
  • the crossover oxide transistor 200 includes a light-shielding electrode 202, an IGZO active layer 205, a gate (G) pole 206, a source (S) pole 207 and Drain (D) pole 208;
  • this test structure also comprises glass substrate 201, silicon oxide (thickness ) and silicon nitride (thickness ) buffer layer 203, GI gate insulating layer 204, PVX passivation layer 210, Resin planar layer 211 and PDL defining layer 212 which are stacked.
  • the light-shielding electrode is used as the bottom gate.
  • Table 1 shows the test results. Referring to Table 1, when the voltage of the light-shielding electrode is 5V, the threshold voltage Vth of the transistor is about -1.5V. At this time, the voltage Vgl of the off transistor is -7V, and the transistor can be turned off normally, which shows the performance of the transistor with this structure Good, with better switchability, can be used in drive circuits.
  • the first electrode and the active layer of at least one oxide transistor overlap at least partially along the direction perpendicular to the substrate, and the first electrode also serves as the bottom gate of the overlapped oxide transistor, which can By avoiding additional bottom gates of overlapping oxide transistors, the layout space is greatly saved, the pitch of sub-pixels is reduced, and the resolution is greatly improved while ensuring low power consumption.
  • the orthographic projection of the active layer of at least one oxide transistor on the substrate is located within the orthographic projection of the first electrode on the substrate.
  • the orthographic projection F2 of the active layer 20 of the oxide transistor 3 on the substrate 10 is located within the orthographic projection F1 of the first electrode 18 on the substrate 10 .
  • FIG. 4 shows an example where the orthographic projection of the active layer of an oxide transistor on the substrate is located within the orthographic projection of the first electrode on the substrate.
  • the active layer of the oxide transistor may include a semiconductor portion, and a first pole contact portion and a second pole contact portion located at both ends of the semiconductor portion.
  • the first pole contact portion It is electrically connected with the first pole, and the second pole contact part is electrically connected with the second pole.
  • the orthographic projection F3 of the second electrode 16 on the substrate 10 is located within the orthographic projection F1 of the first electrode 18 on the substrate 10, which can further save space and improve resolution. .
  • the display substrate further includes power lines 31 , and the first electrodes 18 are electrically connected to the power lines 31 .
  • the specific position of the power line is not limited here, and as an example, one layer may be set alone, or it may be set on the same layer as other structures.
  • the power line 31 and the first pole 32 and the second pole 33 of the overlapping oxide transistor are arranged on the same layer, that is, they can be simultaneously patterned in one patterning process.
  • a power supply line, a first pole and a second pole of the stacked oxide transistor are formed.
  • One patterning process refers to the process of forming the required layer structure after one exposure.
  • a patterning process includes processes such as masking, exposure, development, etching and stripping.
  • the polysilicon transistor is a top-gate polysilicon transistor, and the active layer 13 of the polysilicon transistor 1 is arranged between the substrate 10 and the gate 15 of the polysilicon transistor 1. between.
  • Transistors can be classified into two types according to the positional relationship of electrodes. One is that the gate is located below the source and drain, which is called a bottom-gate thin film transistor; the other is that the gate is located above the source and drain, and this is called a top-gate thin film transistor.
  • the same layer arrangement means that the first electrode and the second electrode of the polysilicon transistor and the first electrode and the second electrode of the overlapping oxide transistor can be formed simultaneously through one patterning process.
  • the display substrate further includes a power line 31, the power line 31, the first pole 29 and the second pole 30 of the polysilicon transistor, and the first pole 32 of the overlapped oxide transistor It is set on the same layer as the second pole 33 .
  • the sub-pixel further includes an anode 35 , one of the first pole and the second pole of the polysilicon transistor is electrically connected to the anode, so as to provide sufficient current to the light emitting diode.
  • the electrical connection between the second pole 30 and the anode 35 of the polysilicon transistor is shown as an example.
  • the anode 35 may be electrically connected to the second pole 30 of the polysilicon transistor through a via hole penetrating the first flat layer 34; or, referring to FIG.
  • the via holes in the second planar layer 40 are electrically connected to the connection electrode 41 , and the connection electrode 41 is electrically connected to the second electrode 30 of the polysilicon transistor through the via hole penetrating the first planar layer 34 .
  • the polysilicon transistor is a P-type transistor
  • the oxide transistor is an N-type transistor
  • the sub-pixel in order to improve the scalability of the driving circuit, may further include a single-gate oxide transistor, and the active layer of the single-gate oxide transistor does not intersect with the first electrode along the direction perpendicular to the substrate.
  • the sub-pixels include a plurality of transistors of different types, which can form sub-pixel driving circuits with different performances.
  • the sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor
  • the transistor T7 ; the first transistor T1 and the second transistor T2 are oxide transistors shown in FIG. 4
  • the third transistor T3 is a polysilicon transistor.
  • the polysilicon transistor may be a top-gate polysilicon transistor shown in FIG. 4 .
  • the display substrate further includes a power line ELVDD, an emission control signal line EM, a data signal line Data, a reset control signal line Scan, and an initial signal line Vinit; the sub-pixels also include a light emitting diode LED.
  • the gates of all transistors are marked as G, the first pole is marked as S, and the second pole is marked as D.
  • the gate of the first transistor T1 is electrically connected to the reset control signal line Scan
  • the second pole is electrically connected to the initial signal line Vinit
  • the first pole of the first transistor T1 the first pole of the second transistor T2 It is electrically connected to the first node N1
  • the gate of the third transistor T3 and the second electrode of the storage capacitor Cst are electrically connected to the first node N1
  • the first electrode of the storage capacitor Cst is electrically connected to the power line ELVDD.
  • the gate of the second transistor T2 is electrically connected to the reset control signal line Scan
  • the second pole is electrically connected to the third node N3
  • the first pole of the third transistor T3 is electrically connected to the second node N2
  • the second pole is electrically connected to the second node N2.
  • the second pole is electrically connected to the third node N2
  • the first pole of the fourth transistor T4 is electrically connected to the second node N2
  • the second pole is electrically connected to the data signal line Data
  • the gate is electrically connected to the reset control signal line Scan.
  • the second pole of the transistor T5 is electrically connected to the second node N2, the first pole is electrically connected to the power line ELVDD, and the gate is electrically connected to the light emission control signal line EM.
  • the gate of the sixth transistor T6 is electrically connected to the light emission control signal line EM
  • the first pole is electrically connected to the third node N3
  • the second pole is electrically connected to the fourth node N4
  • the gate of the seventh transistor T7 The electrodes are electrically connected to the reset control signal line Scan, the first electrode is electrically connected to the fourth node N4, the second electrode is electrically connected to the initial signal line Vinit, the anode of the light emitting diode LED is electrically connected to the fourth node N4, and the cathode is grounded ELVSS.
  • the orthographic projections of the active layers of the first transistor and the second transistor on the substrate are all located within the orthographic projection of the first electrode on the substrate, and the orthographic projections of the active layers of the remaining transistors on the substrate are in the same range as the first electrode.
  • the orthographic projections of the electrodes on the substrate do not overlap.
  • the first node N1 , the second node N2 , the third node N3 , and the fourth node N4 above are only for describing the circuit structure, and are not an actual circuit unit.
  • the foregoing fourth transistor, fifth transistor, sixth transistor and seventh transistor may all be polysilicon transistors or oxide transistors, which are not limited herein.
  • the above-mentioned sub-pixels use a 7T1C driving circuit, and the driving principle of the driving circuit can be obtained by referring to related technologies, and will not be repeated here.
  • the above-mentioned first electrode is not only used as one pole of the storage capacitor, but also used as the bottom gate of the first transistor and the second transistor, which can avoid additional setting of the bottom gate of the first transistor and the second transistor, thereby greatly saving layout space, Reduced sub-pixel pitch.
  • the first transistor T1 and the second transistor T2 have the same structure as the oxide transistor shown in FIG. 4, and the third transistor T3 has the same structure as the polysilicon transistor shown in FIG. 4. Referring to FIG. 5, the first transistor T1 and the second transistor T2 is overlapped with the first electrode 18; compared with FIG.
  • the first electrode 18 is not only used as one pole of the storage capacitor, but also serves as the bottom gate of the first transistor and the second transistor, which can avoid additional setting of the first transistor. and the bottom gate of the second transistor, greatly saving layout space.
  • the Pitch (pitch) of the sub-pixels shown in Figure 5 is 42 ⁇ m, and the corresponding PPI is about 600. Compared with the structure shown in Figure 3, the resolution is greatly improved while ensuring low power consumption.
  • the above display substrate may further include an isolation layer 11, a first buffer layer 12, a first gate insulating layer 14, a second gate insulating layer 17, a second buffer layer 19, a third gate
  • the insulating layer 21, the interlayer dielectric layer 23, the first flat layer 34, the pixel defining layer 36, the anode 35 and the spacer 37 may also include other structures, the embodiment of the present application only introduces the structures related to the invention point, Other structures can be obtained by referring to related technologies, and will not be repeated here.
  • the embodiment of the present application also provides a display panel, including the above-mentioned display substrate.
  • the display panel may be a flexible display panel (also known as a flexible screen), or a rigid display panel (ie, a display panel that cannot be bent), which is not limited here.
  • the display panel can be an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display panel, a Micro LED display panel or a Mini LED display panel, and any TV, digital camera, mobile phone, tablet computer, etc. that include these display panels.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the embodiment of the present application further provides a method for preparing a display substrate, including:
  • a plurality of sub-pixels arranged in an array on the substrate include:
  • the storage capacitor includes a first electrode and a second electrode oppositely arranged, and the first electrode is arranged on a side of the second electrode away from the substrate; the second electrode and The gates of the polysilicon transistors are arranged on the same layer; the oxide transistor is arranged on the side of the first electrode away from the substrate, and the first electrode and the active layer of at least one oxide transistor overlap at least partially in a direction perpendicular to the substrate; the first The electrode is configured to receive a power signal and also serves as a bottom gate of an overlapped oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode in a direction perpendicular to the substrate is an overlapped oxide transistor.
  • the first electrode at least partially overlaps the active layer of at least one oxide transistor along a direction perpendicular to the substrate, and the first electrode is also used as the bottom gate of the overlapped oxide transistor, In this way, additional bottom gates of overlapping oxide transistors can be avoided, thereby greatly saving layout space, reducing the pitch of sub-pixels, and greatly improving resolution while ensuring low power consumption.
  • the preparation method is simple and easy to realize.
  • forming storage capacitors and polysilicon transistors includes:
  • forming polysilicon transistors and overlapping oxide transistors includes:
  • the method includes:
  • S101 on the substrate 10, sequentially form an isolation layer (Barrier) 11, a first buffer layer 12, an active layer 13 of a polysilicon transistor, a first gate insulating layer 14, a gate metal layer, and a second gate as shown in FIG.
  • the above-mentioned second electrode and the gate of the polysilicon transistor are fabricated by one patterning process.
  • the aforementioned substrate may be a flexible substrate, such as a PI substrate, or the like; or may also be a rigid substrate, such as a glass substrate. If a PI substrate is used, in order to provide better performance, an additional layer of isolation film and PI film can be arranged in sequence between the substrate and the isolation layer.
  • the material of the active layer of the above-mentioned polysilicon transistor may be a low temperature polysilicon material.
  • the material of the first gate insulating layer and the second gate insulating layer may be silicon oxide or silicon nitride.
  • the material of the gate metal layer and the first electrode may be metal, such as copper, aluminum and the like.
  • one mask is required to form the active layer of the polysilicon transistor, one mask is required to form the second electrode and the gate of the polysilicon transistor, and one mask is required to form the first electrode, totaling three masks.
  • the second buffer layer is both an insulating layer and a gate insulating layer of the bottom gate (i.e., the second electrode).
  • the material and thickness can be adjusted according to the specific device characteristic requirements, and the thickness is usually selected to be of silicon oxide.
  • the material of the above active layer may be a metal oxide material such as IGZO.
  • a Mask is required to form the active layer of the oxide transistor.
  • the first via hole and the second via hole respectively penetrate the interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer and the first gate insulating layer, and the third via hole penetrates the interlayer dielectric layer.
  • layer, the third gate insulating layer and the second buffer layer the first via hole is used to electrically connect the first pole of the polysilicon transistor to the active layer of the polysilicon transistor, and the second via hole is used to connect the second pole of the polysilicon transistor to the polysilicon transistor
  • the active layer is electrically connected, and the third via hole is used to electrically connect the power signal line to the first electrode.
  • the first via hole and the second via hole are formed by etching first, then HF (hydrogen fluoride) cleaning is performed, and then the third via hole is formed; a mask is required to form the first via hole and the second via hole, and the third via hole is formed.
  • a hole requires a Mask, a total of 2 Masks.
  • the fourth via hole and the fifth via hole respectively penetrate through the third gate insulating layer and the second buffer layer, the fourth via hole is used to electrically connect the first electrode of the oxide transistor to the active layer of the oxide transistor, and the fourth via hole is used to electrically connect the first electrode of the oxide transistor to the active layer of the oxide transistor.
  • the five vias are used to electrically connect the second electrode of the oxide transistor to the active layer of the oxide transistor.
  • forming the fourth via hole and the fifth via hole requires a Mask.
  • the source-drain metal layer includes the first pole 29 and the second pole 30 of the polysilicon transistor, the power signal line ELVDD line 31, and the first pole 32 of the oxide transistor as shown in FIG. 12 and the second pole 33 .
  • the first pole and the second pole of the polysilicon transistor are electrically connected to the active layer of the polysilicon transistor through the first via hole and the second via hole respectively, and the power signal line ELVDD line is electrically connected to the first electrode through the third via hole,
  • the first pole and the second pole of the oxide transistor are electrically connected to the active layer of the oxide transistor through the fourth via hole and the fifth via hole respectively.
  • forming the fourth via hole and the fifth via hole requires a Mask.
  • the planar layer includes a sixth via hole, and the anode is electrically connected to the second electrode of the polysilicon transistor through the sixth via hole.
  • one mask is needed to form the sixth via hole, one mask is needed to form the anode, one mask is needed to form the pixel defining layer, and one mask is needed to form the spacer, 4 masks in total.
  • S101 uses 3 masks
  • S103 uses 1 mask
  • S104 uses 1 mask
  • S105 uses 2 masks
  • S106 uses 1 mask
  • S107 uses 1 mask
  • S108 uses 4 masks, 13 in total Mask.
  • the above preparation method is simple and easy to implement, and a display substrate with relatively large resolution is formed under the condition that the number of original patterning processes remains unchanged.

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Abstract

本申请提供了一种显示基板及其制备方法、显示面板，涉及显示技术领域，该显示面板能够在保证低功耗的前提下，大幅提升分辨率。显示基板包括多个子像素；子像素包括存储电容、多晶硅晶体管、至少一个氧化物晶体管；存储电容包括相对设置的第一电极和第二电极，第一电极设置在第二电极远离衬底的一侧；第二电极与多晶硅晶体管的栅极同层设置；氧化物晶体管设置在第一电极远离衬底的一侧，第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向至少部分交叠；第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，与第一电极沿垂直于衬底方向至少部分交叠的氧化物晶体管为交叠氧化物晶体管。

Description

显示基板及其制备方法、显示面板
相关申请的交叉引用
本申请要求在2021年06月23日提交中国专利局、申请号为202110700542.X、名称为“一种显示基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示面板。
背景技术
OLED(Organic Light-Emtting Diode，有机发光二极管)显示器凭借低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流，可以广泛应用于智能手机、平板电脑、电视等终端产品。
目前可穿戴设备(如智能手表等)通常采用LTPO背板驱动电路，即LTPS-TFT(低温多晶硅薄膜晶体管)与oxide-TFT(氧化物薄膜晶体管)结合的背板结构。这种结构采用LTPS-TFT作为OLED元件的驱动TFT，采用oxide-TFT作为开关TFT。既利用了LTPS-TFT响应速度快，开启电流较大的特点，为OLED显示提供电流源；同时又利用了oxide-TFT低漏电的特点，降低了背板功耗。这种低功耗的设计更加适合可穿戴设备。
但是LTPO技术中，oxide-TFT的尺寸较大；同时oxide-TFT为NMOS型晶体管，而LTPS-TFT为PMOS型晶体管，两者的驱动电压不同，从而导致LTPO背板布线紧张，最终难以形成较高分辨率的显示面板。
发明内容
本申请的实施例提供一种显示基板及其制备方法、显示面板，该显示面板能够在保证低功耗的前提下，大幅提升分辨率。
为达到上述目的，本申请的实施例采用如下技术方案：
一方面，提供了一种显示基板，包括衬底、以及位于所述衬底一侧的阵列排布的多个子像素；
所述子像素包括存储电容、多晶硅晶体管、至少一个氧化物晶体管；其中，所述存储电容包括相对设置的第一电极和第二电极，所述第一电极设置在所述第二电极远离所述衬底的一侧；
所述第二电极与所述多晶硅晶体管的栅极同层设置；所述氧化物晶体管 设置在所述第一电极远离所述衬底的一侧，所述第一电极与至少一个所述氧化物晶体管的有源层沿垂直于所述衬底方向至少部分交叠；
所述第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与所述第一电极沿垂直于所述衬底方向至少部分交叠的所述氧化物晶体管为所述交叠氧化物晶体管。
可选的，至少一个所述氧化物晶体管的有源层在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影以内。
可选的，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影以内。
可选的，所述显示基板还包括电源线，所述第一电极与所述电源线电连接。
可选的，所述电源线与所述交叠氧化物晶体管的第一极和第二极同层设置。
可选的，所述多晶硅晶体管为顶栅型多晶硅晶体管，所述多晶硅晶体管的有源层设置在所述衬底和所述多晶硅晶体管的栅极之间。
可选的，所述多晶硅晶体管的第一极和第二极，与所述交叠氧化物晶体管的第一极和第二极同层设置。
可选的，所述子像素还包括阳极，所述多晶硅晶体管的第一极和第二极两者中的一个与所述阳极电连接。
可选的，所述多晶硅晶体管为P型管，所述氧化物晶体管为N型管。
可选的，所述子像素还包括单栅氧化物晶体管，所述单栅氧化物晶体管的有源层与所述第一电极沿垂直于所述衬底方向不交叠。
可选的，所述子像素包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；所述第一晶体管和所述第二晶体管为所述氧化物晶体管，所述第三晶体管为所述多晶硅晶体管；
所述显示基板还包括电源线、发光控制信号线、数据信号线、复位控制信号线、初始信号线；所述子像素还包括发光二极管；
所述第一晶体管的栅极与所述复位控制信号线电连接、第二极与初始信号线电连接，所述第一晶体管的第一极、所述第二晶体管的第一极与第一节点电连接，所述第三晶体管的栅极、所述存储电容的所述第二电极与所述第一节点电连接，所述存储电容的所述第一电极与所述电源线电连接；
所述第二晶体管的栅极与所述复位控制信号线电连接、第二极与第三节 点电连接，所述第三晶体管的第一极与第二节点电连接、第二极与所述第三节点电连接，所述第四晶体管的第一极与所述第二节点电连接、第二极与所述数据信号线电连接、栅极与所述复位控制信号线电连接，所述第五晶体管的第二极与所述第二节点电连接、第一极与所述电源线电连接、栅极与所述发光控制信号线电连接；
所述第六晶体管的栅极与所述发光控制信号线电连接、第一极与所述第三节点电连接、第二极与第四节点电连接，所述第七晶体管的栅极与所述复位控制信号线电连接、第一极与所述第四节点电连接、第二极与初始信号线电连接，所述发光二极管的阳极与所述第四节点电连接、阴极接地；
其中，所述第一晶体管和所述第二晶体管的有源层在所述衬底上的正投影均位于所述第一电极在所述衬底上的正投影以内，其余晶体管的有源层在所述衬底上的正投影与所述第一电极在所述衬底上的正投影不交叠。
另一方面，提供了一种显示面板，包括上述的显示基板。
再一方面，提供了一种上述显示基板的制备方法，包括：
在衬底上形成阵列排布的多个子像素；
所述在衬底上形成阵列排布的多个子像素包括：
形成存储电容、多晶硅晶体管、至少一个氧化物晶体管；其中，所述存储电容包括相对设置的第一电极和第二电极，所述第一电极设置在所述第二电极远离所述衬底的一侧；所述第二电极与所述多晶硅晶体管的栅极同层设置；所述氧化物晶体管设置在所述第一电极远离所述衬底的一侧，所述第一电极与至少一个所述氧化物晶体管的有源层沿垂直于所述衬底方向至少部分交叠；所述第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与所述第一电极沿垂直于所述衬底方向至少部分交叠的所述氧化物晶体管为所述交叠氧化物晶体管。
可选的，形成所述存储电容和所述多晶硅晶体管包括：
采用一次构图工艺形成所述存储电容的所述第二电极和所述多晶硅晶体管的栅极。
可选的，形成所述多晶硅晶体管和所述交叠氧化物晶体管包括：
采用一次构图工艺形成所述多晶硅晶体管的第一极和第二极、以及所述交叠氧化物晶体管的第一极和第二极。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它 目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种LTPO基板的结构示意图；
图2为本申请实施例提供的一种7T1C的电路图；
图3为采用图1结构的一种7T1C版图；
图4为本申请实施例提供的一种显示基板的结构示意图；
图5为采用图4结构的一种7T1C版图；
图6-13为本申请实施例提供的一种制备图13结构的流程结构图；
图14为本申请实施例提供的另一种显示基板的结构示意图；
图15为本申请实施例提供的一种显示基板的测试结构示意图；
图16为图15的等效结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的实施例中，采用“第一”、“第二”、……、“第七”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本申请的实施例中，“多个”的含义是两个或两个以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
在本申请的实施例中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的实施例中，晶体管包括栅极、源极和漏极，将源极和漏极中的一个称为第一极、另一个称为第二极。
相关技术中，LTPO基板可以包括如图1所示的LTPS驱动管103、oxide开关管105和Cst电容100，其中，LTPS驱动管和oxide开关管平行放置，oxide开关管为双栅型晶体管，LTPS驱动管103的栅极104和Cst电容100的第二极102同层设置，Cst电容100的第一极101和oxide开关管105的底栅106同层设置；图1中，该LTPO基板还包括PI(聚酰亚胺)衬底107、第一GI层108、第一ILD层109、第二ILD层110、Buffer层111、第二GI层112、第二ILD层113、第一PLN层114、第二PLN层115、Anode层117、PDL层118和PS层119，该结构可以采用13道Mask(掩膜)制作。该LTPO基板可以采用如图2所示的7T1C驱动电路，其中，晶体管T3可以采用图1所示的LTPS驱动管，晶体管T1和T2可以采用图1所示的oxide开关管，该7T1C驱动电路的版图可以如图3所示，最终形成的子像素的Pitch(间距)为56μm，相应的PPI(Pixels Per Inch，像素密度)约为450。而采用LTPS技术，PPI可达到630。LTPO面板的PPI还有待于进一步提升。
基于上述，本申请实施例提供了一种显示基板，包括衬底、以及位于衬底一侧的阵列排布的多个子像素。
参考图4所示，子像素包括存储电容2、多晶硅晶体管1、至少一个氧化物晶体管3；其中，存储电容2包括相对设置的第一电极18和第二电极16，第一电极18设置在第二电极16远离衬底10的一侧。
参考图4所示，第二电极16与多晶硅晶体管1的栅极15同层设置；氧化物晶体管3设置在第一电极18远离衬底10的一侧，第一电极18与至少一个氧化物晶体管3的有源层20沿垂直于衬底方向至少部分交叠。
第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与第一电极沿垂直于衬底方向至少部分交叠的氧化物晶体管为交叠氧化物晶体管。
上述子像素采用的驱动电路的具体结构不做限定，示例的，可以采用2T1C驱动电路、3T1C驱动电路或者7T1C驱动电路等。为了获得更好地驱动性能，可以采用如图2所示的7T1C驱动电路，示例的，多晶硅晶体管可以用作驱动管T3，氧化物晶体管可以用作开关管T1或者T2等。
上述氧化物晶体管的有源层的材料可以是IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)或者ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)等金属氧化物。
上述多晶硅晶体管的类型不做限定，其可以是顶栅型多晶硅晶体管，或 者，还可以是底栅型多晶硅晶体管。图4中以顶栅型多晶硅晶体管为例进行绘示。
上述第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向至少部分交叠包括：第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向部分交叠，此时，第一电极在衬底上的正投影可以与至少一个氧化物晶体管的有源层在衬底上的正投影部分交叠；或者，第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向完全交叠，此时，至少一个氧化物晶体管的有源层在衬底上的正投影可以位于第一电极在衬底上的正投影以内。
上述交叠氧化物晶体管可以包括顶栅、底栅、第一极和第二极，其中，存储电容的第一电极用作底栅、与电源信号线电连接，能够起到保护沟道和提升稳定性的作用，同时还可以作为遮光层，进一步保护交叠氧化物晶体管的性能。
需要说明的是，一般双栅型晶体管的顶栅和底栅接入同一栅极信号，而本申请中，交叠氧化物晶体管的顶栅接入栅极信号，底栅(即第一电极)接入电源信号VDD(一般为4.6V直流电压)。以图15所示结构为例进行性能测试，参考图15所示，该交叠氧化物晶体管200包括遮光电极202、IGZO有源层205、栅(G)极206、源(S)极207和漏(D)极208；当然，该测试结构还包括玻璃衬底201、氧化硅(厚度
Figure PCTCN2022079199-appb-000001
)和氮化硅(厚度
Figure PCTCN2022079199-appb-000002
)叠层设置的缓冲层203、GI栅绝缘层204、PVX钝化层210、Resin平坦层211和PDL界定层212。其中，遮光电极用作底栅，参考图16所示，向遮光电极输入不同的直流电压，同时向栅(G)极、源(S)极和漏(D)极输入相应的电压，得到如表一所示的测试结果。参考表一，当遮光电极的电压为5V时，该晶体管的阈值电压Vth约为-1.5V，此时，关闭晶体管的电压Vgl为-7V，该晶体管可以正常关闭，说明该种结构的晶体管性能良好，具有较好地开关性，可以应用在驱动电路中。
表一
Figure PCTCN2022079199-appb-000003
本申请提供的显示基板中，第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向至少部分交叠，同时第一电极还用作交叠氧化物晶体管的底栅，这样可以避免额外设置交叠氧化物晶体管的底栅，从而大幅节省了版图空间，降低了子像素的间距，进而在保证低功耗的前提下，大幅提升了分辨率。
可选的，为了提高晶体管的性能，至少一个氧化物晶体管的有源层在衬底上的正投影位于第一电极在衬底上的正投影以内。参考图4所示，氧化物晶体管3的有源层20在衬底10上的正投影F2位于第一电极18在衬底10上的正投影F1以内。图4以一个氧化物晶体管的有源层在衬底上的正投影位于第一电极在衬底上的正投影以内为例进行绘示。
这里对于有源层的具体结构不做限定，示例的，氧化物晶体管的有源层可以包括半导体部、以及位于半导体部两端的第一极接触部和第二极接触部，第一极接触部与第一极电连接，第二极接触部与第二极电连接。
进一步可选的，参考图4所示，第二电极16在衬底10上的正投影F3位于第一电极18在衬底10上的正投影F1以内，这样可以更进一步节省空间，提高分辨率。
可选的，为了更好地向第一电极提供电源信号，参考图4所示，该显示基板还包括电源线31，第一电极18与电源线31电连接。
这里对于电源线的具体位置不做限定，示例的，可以单独设置一层，或者与其他结构同层设置。
进一步可选的，为了减少构图次数，降低生产成本，参考图4所示，电源线31与交叠氧化物晶体管的第一极32和第二极33同层设置，即可以通过一次构图工艺同时形成电源线、交叠氧化物晶体管的第一极和第二极。
上述同层设置是指采用一次构图工艺制作。一次构图工艺是指经过一次曝光形成所需要的层结构工艺。一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺。
可选的，为了降低设计难度，减少构图次数，参考图4所示，多晶硅晶体管为顶栅型多晶硅晶体管，多晶硅晶体管1的有源层13设置在衬底10和多晶硅晶体管1的栅极15之间。
根据电极的位置关系可以将晶体管分为两类。一类是栅极位于源极和漏极的下面，这类称之为底栅型薄膜晶体管；一类是栅极位于源极和漏极的上面，这类称之为顶栅型薄膜晶体管。
进一步可选的，为了减少构图次数，降低生产成本，参考图4所示，多晶硅晶体管1的第一极29和第二极30，与交叠氧化物晶体管的第一极32和第二极33同层设置，即可以通过一次构图工艺同时形成多晶硅晶体管的第一极和第二极、交叠氧化物晶体管的第一极和第二极。
需要说明的是，参考图4所示，若该显示基板还包括电源线31，则电源线31、多晶硅晶体管的第一极29和第二极30，与交叠氧化物晶体管的第一极32和第二极33同层设置。
进一步可选的，参考图4所示，子像素还包括阳极35，多晶硅晶体管的第一极和第二极两者中的一个与阳极电连接，从而向发光二极管提供足够的电流。图4中以多晶硅晶体管的第二极30与阳极35电连接为例进行绘示。需要说明的是，参考图4所示，阳极35可以通过贯通第一平坦层34的过孔与多晶硅晶体管的第二极30电连接；或者，参考图14所示，阳极35还可以通过贯通第二平坦层40的过孔与连接电极41电连接，连接电极41通过 贯通第一平坦层34的过孔与多晶硅晶体管的第二极30电连接。
在一个或者多个实施例中，为了提供更好地驱动性能，多晶硅晶体管为P型管，氧化物晶体管为N型管。
在一个或者多个实施例中，为了提高驱动电路的可扩展性，子像素还可以包括单栅氧化物晶体管，单栅氧化物晶体管的有源层与第一电极沿垂直于衬底方向不交叠，此时，子像素包括多个不同类型的晶体管，可以形成具有不同性能的子像素驱动电路。这里对于单栅氧化物晶体管的数量不做限定，具体可以根据实际要求确定。
在一个或者多个实施例中，参考图2所示，子像素包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7；第一晶体管T1和第二晶体管T2为图4所示的氧化物晶体管，第三晶体管T3为多晶硅晶体管，该多晶硅晶体管可以为图4所示的顶栅型多晶硅晶体管。
参考图2所示，显示基板还包括电源线ELVDD、发光控制信号线EM、数据信号线Data、复位控制信号线Scan、初始信号线Vinit；子像素还包括发光二极管LED。图2中，所有晶体管的栅极标记为G、第一极标记为S、第二极标记为D。
参考图2所示，第一晶体管T1的栅极与复位控制信号线Scan电连接、第二极与初始信号线Vinit电连接，第一晶体管T1的第一极、第二晶体管T2的第一极与第一节点N1电连接，第三晶体管T3的栅极、存储电容Cst的第二电极与第一节点N1电连接，存储电容Cst的第一电极与电源线ELVDD电连接。
参考图2所示，第二晶体管T2的栅极与复位控制信号线Scan电连接、第二极与第三节点N3电连接，第三晶体管T3的第一极与第二节点N2电连接、第二极与第三节点N2电连接，第四晶体管T4的第一极与第二节点N2电连接、第二极与数据信号线Data电连接、栅极与复位控制信号线Scan电连接，第五晶体管T5的第二极与第二节点N2电连接、第一极与电源线ELVDD电连接、栅极与发光控制信号线EM电连接。
参考图2所示，第六晶体管T6的栅极与发光控制信号线EM电连接、第一极与第三节点N3电连接、第二极与第四节点N4电连接，第七晶体管T7的栅极与复位控制信号线Scan电连接、第一极与第四节点N4电连接、第二极与初始信号线Vinit电连接，发光二极管LED的阳极与第四节点N4 电连接、阴极接地ELVSS。
其中，第一晶体管和第二晶体管的有源层在衬底上的正投影均位于第一电极在衬底上的正投影以内，其余晶体管的有源层在衬底上的正投影与第一电极在衬底上的正投影不交叠。
上述第一节点N1、第二节点N2、第三节点N3、第四节点N4只是为了便于描述电路结构，并不是一个实际的电路单元。
上述第四晶体管、第五晶体管、第六晶体管和第七晶体管可以均为多晶硅晶体管或者氧化物晶体管，这里不做限定。
上述子像素采用7T1C的驱动电路，该驱动电路的驱动原理可以参考相关技术获得，这里不再赘述。上述第一电极既用作存储电容的一极，又同时用作第一晶体管和第二晶体管的底栅，可以避免额外设置第一晶体管和第二晶体管的底栅，从而大幅节省了版图空间，降低了子像素的间距。第一晶体管T1和第二晶体管T2与图4所示的氧化物晶体管结构相同，第三晶体管T3与图4所示的多晶硅晶体管结构相同，参考图5所示，第一晶体管T1和第二晶体管T2与第一电极18交叠设置；相比图3，第一电极18既用作存储电容的一极，又同时用作第一晶体管和第二晶体管的底栅，可以避免额外设置第一晶体管和第二晶体管的底栅，大幅节省了版图空间。图5所示子像素的Pitch(间距)为42μm，相应的PPI约为600，相比图3所示结构，在保证低功耗的前提下，大幅提升了分辨率。
需要说明的是，参考图4所示，上述显示基板还可以包括隔离层11、第一缓冲层12、第一栅绝缘层14、第二栅绝缘层17、第二缓冲层19、第三栅绝缘层21、层间介质层23、第一平坦层34、像素界定层36、阳极35和隔垫物37，当然，还可以包括其他结构，本申请实施例仅介绍与发明点相关的结构，其余结构可以参考相关技术获得，这里不再赘述。
本申请实施例还提供了一种显示面板，包括上述的显示基板。
该显示面板可以是柔性显示面板(又称柔性屏)，也可以是刚性显示面板(即不能折弯的显示面板)，这里不做限定。该显示面板以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，还可以是Micro LED显示面板或者Mini LED显示面板，以及包括这些显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
本申请实施例又提供了一种的显示基板的制备方法，包括：
S01、在衬底上形成阵列排布的多个子像素。
S01、在衬底上形成阵列排布的多个子像素包括：
S10、形成存储电容、多晶硅晶体管、至少一个氧化物晶体管；其中，存储电容包括相对设置的第一电极和第二电极，第一电极设置在第二电极远离衬底的一侧；第二电极与多晶硅晶体管的栅极同层设置；氧化物晶体管设置在第一电极远离衬底的一侧，第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向至少部分交叠；第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与第一电极沿垂直于衬底方向至少部分交叠的氧化物晶体管为交叠氧化物晶体管。
通过上述制备方法形成的显示基板中，第一电极与至少一个氧化物晶体管的有源层沿垂直于衬底方向至少部分交叠，同时第一电极还用作交叠氧化物晶体管的底栅，这样可以避免额外设置交叠氧化物晶体管的底栅，从而大幅节省了版图空间，降低了子像素的间距，进而在保证低功耗的前提下，大幅提升了分辨率。该制备方法简单易实现。
可选的，为了减少构图次数，降低生产成本，形成存储电容和多晶硅晶体管包括：
S20、采用一次构图工艺形成存储电容的第二电极和多晶硅晶体管的栅极。
可选的，为了减少构图次数，降低生产成本，形成多晶硅晶体管和交叠氧化物晶体管包括：
S30、采用一次构图工艺形成多晶硅晶体管的第一极和第二极、以及交叠氧化物晶体管的第一极和第二极。
下面以图13所示的结构为例，说明具体的制备方法。
该方法包括：
S101、在衬底10上依次形成如图6所示的隔离层(Barrier)11、第一缓冲层12、多晶硅晶体管的有源层13、第一栅绝缘层14、栅金属层、第二栅绝缘层17、存储电容的第一电极18；其中，栅金属层包括存储电容的第二电极16和多晶硅晶体管的栅极15，第二电极16在衬底10上的正投影F3位于第一电极18在衬底10上的正投影F1以内。
上述第二电极和多晶硅晶体管的栅极采用一次构图工艺制作。上述衬底可以是柔性衬底，例如：PI衬底等；或者，还可以是刚性衬底，例如：玻璃衬底等。若采用PI衬底，为了提供更好地性能，还可以在衬底与隔离层之间再额外依次设置一层隔离膜和PI膜。
上述多晶硅晶体管的有源层材料可以是低温多晶硅材料。上述第一栅绝缘层和第二栅绝缘层的材料可以是氧化硅或者氮化硅等。上述栅金属层和第一电极的材料可以是金属，例如：铜、铝等。
S101中，形成多晶硅晶体管的有源层需要一道Mask(掩膜)，形成第二电极和多晶硅晶体管的栅极需要一道Mask，形成第一电极需要一道Mask，共计3道Mask。
S102、在第一电极18上沉积如图7所示的第二缓冲层19。
第二缓冲层既是绝缘层也是底栅(即第二电极)的栅绝缘层，可根据具体的器件特性要求调整材质和厚度，通常选择厚度为
Figure PCTCN2022079199-appb-000004
的氧化硅。
S103、在第二缓冲层19上形成如图8所示的氧化物晶体管的有源层20。
上述有源层的材料可以是IGZO等金属氧化物材料。S103中，形成氧化物晶体管的有源层需要一道Mask。
S104、形成如图9所示的第三栅绝缘层21和氧化物晶体管的栅极(即顶栅)22，其中，第三栅绝缘层21覆盖氧化物晶体管的有源层20。
S104中，形成氧化物晶体管的栅极需要一道Mask。
S105、形成如图10所示覆盖氧化物晶体管栅极的层间介质层23、以及第一过孔24、第二过孔25和第三过孔26。
其中，第一过孔和第二过孔均分别贯通层间介质层、第三栅绝缘层、第二缓冲层、第二栅绝缘层和第一栅绝缘层，第三过孔贯通层间介质层、第三栅绝缘层和第二缓冲层，第一过孔用于多晶硅晶体管的第一极与多晶硅晶体管的有源层电连接，第二过孔用于多晶硅晶体管的第二极与多晶硅晶体管的有源层电连接，第三过孔用于电源信号线与第一电极电连接。
S105中，先刻蚀形成第一过孔和第二过孔，再进行HF(氟化氢)清洗，接着再形成第三过孔；形成第一过孔和第二过孔需要一道Mask，形成第三过孔需要一道Mask，共计2道Mask。
S106、形成如图11所示的第四过孔27和第五过孔28。
其中，第四过孔和第五过孔均分别贯通第三栅绝缘层和第二缓冲层，第四过孔用于氧化物晶体管的第一极与氧化物晶体管的有源层电连接，第五过孔用于氧化物晶体管的第二极与氧化物晶体管的有源层电连接。S106中，形成第四过孔和第五过孔需要一道Mask。
S107、形成源漏金属层，其中，源漏金属层包括如图12所示的多晶硅晶体管的第一极29和第二极30、电源信号线ELVDD线31、以及氧化物晶 体管的第一极32和第二极33。
其中，多晶硅晶体管的第一极和第二极分别通过第一过孔和第二过孔与多晶硅晶体管的有源层电连接，电源信号线ELVDD线通过第三过孔与第一电极电连接，氧化物晶体管的第一极和第二极分别通过第四过孔和第五过孔与氧化物晶体管的有源层电连接。S107中，形成第四过孔和第五过孔需要一道Mask。
S108、形成如图13所示覆盖源漏金属层的第一平坦层34、阳极35、像素界定层36和隔垫物(PS)37。
其中，平坦层包括第六过孔，阳极通过第六过孔与多晶硅晶体管的第二极电连接。S108中，形成第六过孔需要一道Mask，形成阳极需要一道Mask，形成像素界定层需要一道Mask，形成隔垫物需要一道Mask，共计4道Mask。
上述制备方法中，S101采用3道Mask，S103采用1道Mask，S104采用1道Mask，S105采用2道Mask，S106采用1道Mask，S107采用1道Mask，S108采用4道Mask，总共13道Mask。
上述制备方法简单易实现，在保证原有构图工艺次数不变的情况下，形成了具有较大分辨率的显示基板。
需要说明的是，本申请实施例中涉及的显示基板的相关结构说明，可以参考前述实施例，这里不再赘述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (15)

  1. 一种显示基板，其中，包括衬底、以及位于所述衬底一侧的阵列排布的多个子像素；
    所述子像素包括存储电容、多晶硅晶体管、至少一个氧化物晶体管；其中，所述存储电容包括相对设置的第一电极和第二电极，所述第一电极设置在所述第二电极远离所述衬底的一侧；
    所述第二电极与所述多晶硅晶体管的栅极同层设置；所述氧化物晶体管设置在所述第一电极远离所述衬底的一侧，所述第一电极与至少一个所述氧化物晶体管的有源层沿垂直于所述衬底方向至少部分交叠；
    所述第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与所述第一电极沿垂直于所述衬底方向至少部分交叠的所述氧化物晶体管为所述交叠氧化物晶体管。
  2. 根据权利要求1所述的显示基板，其中，至少一个所述氧化物晶体管的有源层在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影以内。
  3. 根据权利要求2所述的显示基板，其中，所述第二电极在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影以内。
  4. 根据权利要求1所述的显示基板，其中，所述显示基板还包括电源线，所述第一电极与所述电源线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述电源线与所述交叠氧化物晶体管的第一极和第二极同层设置。
  6. 根据权利要求1所述的显示基板，其中，所述多晶硅晶体管为顶栅型多晶硅晶体管，所述多晶硅晶体管的有源层设置在所述衬底和所述多晶硅晶体管的栅极之间。
  7. 根据权利要求6所述的显示基板，其中，所述多晶硅晶体管的第一极和第二极，与所述交叠氧化物晶体管的第一极和第二极同层设置。
  8. 根据权利要求7所述的显示基板，其中，所述子像素还包括阳极，所述多晶硅晶体管的第一极和第二极两者中的一个与所述阳极电连接。
  9. 根据权利要求1所述的显示基板，其中，所述多晶硅晶体管为P型管，所述氧化物晶体管为N型管。
  10. 根据权利要求1所述的显示基板，其中，所述子像素还包括单栅氧化物晶体管，所述单栅氧化物晶体管的有源层与所述第一电极沿垂直于 所述衬底方向不交叠。
  11. 根据权利要求1所述的显示基板，其中，所述子像素还包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；所述第一晶体管和所述第二晶体管为所述氧化物晶体管，所述第三晶体管为所述多晶硅晶体管；
    所述显示基板还包括电源线、发光控制信号线、数据信号线、复位控制信号线、初始信号线；所述子像素还包括发光二极管；
    所述第一晶体管的栅极与所述复位控制信号线电连接、第二极与初始信号线电连接，所述第一晶体管的第一极、所述第二晶体管的第一极与第一节点电连接，所述第三晶体管的栅极、所述存储电容的所述第二电极与所述第一节点电连接，所述存储电容的所述第一电极与所述电源线电连接；
    所述第二晶体管的栅极与所述复位控制信号线电连接、第二极与第三节点电连接，所述第三晶体管的第一极与第二节点电连接、第二极与所述第三节点电连接，所述第四晶体管的第一极与所述第二节点电连接、第二极与所述数据信号线电连接、栅极与所述复位控制信号线电连接，所述第五晶体管的第二极与所述第二节点电连接、第一极与所述电源线电连接、栅极与所述发光控制信号线电连接；
    所述第六晶体管的栅极与所述发光控制信号线电连接、第一极与所述第三节点电连接、第二极与第四节点电连接，所述第七晶体管的栅极与所述复位控制信号线电连接、第一极与所述第四节点电连接、第二极与初始信号线电连接，所述发光二极管的阳极与所述第四节点电连接、阴极接地；
    其中，所述第一晶体管和所述第二晶体管的有源层在所述衬底上的正投影均位于所述第一电极在所述衬底上的正投影以内，其余晶体管的有源层在所述衬底上的正投影与所述第一电极在所述衬底上的正投影不交叠。
  12. 一种显示面板，其中，包括权利要求1-11任一项所述的显示基板。
  13. 一种如权利要求1-11任一项所述的显示基板的制备方法，其中，包括：
    在衬底上形成阵列排布的多个子像素；
    所述在衬底上形成阵列排布的多个子像素包括：
    形成存储电容、多晶硅晶体管、至少一个氧化物晶体管；其中，所述存储电容包括相对设置的第一电极和第二电极，所述第一电极设置在所述第二电极远离所述衬底的一侧；所述第二电极与所述多晶硅晶体管的栅极 同层设置；所述氧化物晶体管设置在所述第一电极远离所述衬底的一侧，所述第一电极与至少一个所述氧化物晶体管的有源层沿垂直于所述衬底方向至少部分交叠；所述第一电极被配置为接入电源信号、且还用作交叠氧化物晶体管的底栅，其中，与所述第一电极沿垂直于所述衬底方向至少部分交叠的所述氧化物晶体管为所述交叠氧化物晶体管。
  14. 根据权利要求13所述的方法，其中，形成所述存储电容和所述多晶硅晶体管包括：
    采用一次构图工艺形成所述存储电容的所述第二电极和所述多晶硅晶体管的栅极。
  15. 根据权利要求13所述的方法，其中，形成所述多晶硅晶体管和所述交叠氧化物晶体管包括：
    采用一次构图工艺形成所述多晶硅晶体管的第一极和第二极、以及所述交叠氧化物晶体管的第一极和第二极。
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