WO2020198975A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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Publication number
WO2020198975A1
WO2020198975A1 PCT/CN2019/080523 CN2019080523W WO2020198975A1 WO 2020198975 A1 WO2020198975 A1 WO 2020198975A1 CN 2019080523 W CN2019080523 W CN 2019080523W WO 2020198975 A1 WO2020198975 A1 WO 2020198975A1
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Prior art keywords
gate
layer
gate lead
base substrate
display substrate
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PCT/CN2019/080523
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English (en)
French (fr)
Inventor
王丽
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京东方科技集团股份有限公司
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Priority to CN201980000434.2A priority Critical patent/CN110114885B/zh
Priority to PCT/CN2019/080523 priority patent/WO2020198975A1/zh
Priority to US16/642,814 priority patent/US11264443B2/en
Publication of WO2020198975A1 publication Critical patent/WO2020198975A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display panel.
  • OLED display devices have the advantages of self-luminescence, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. They have become the key development of a new generation of display devices. One of the directions, so it has received more and more attention.
  • the pixel driving circuit of the OLED display device usually includes circuit elements such as transistors and capacitors, and the current flowing through the light-emitting diodes is controlled by these circuit elements, thereby controlling the display gray scale of the display device.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a pixel driving circuit.
  • the pixel drive circuit is on the base substrate and includes a drive transistor and a gate lead.
  • the drive transistor includes a gate.
  • the gate lead is electrically connected to the gate, wherein the gate lead is located on the Between the gate and the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a data line, the data line is located on a side of the gate away from the base substrate, and the driving transistor is configured to receive The data voltage signal provided by the data line controls the driving current flowing through the driving transistor based on the data voltage signal, and the driving current is used to drive the light emitting device to work.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a shielding layer between the layer where the gate is located and the layer where the data line is located, wherein the shielding layer and the gate are connected to each other. They are insulated and overlap each other in a direction perpendicular to the base substrate.
  • the shielding layer is a metal layer.
  • the orthographic projection of the gate lead on the base substrate and the orthographic projection of the shielding layer on the base substrate at least partially overlap.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a buffer layer, the buffer layer being on the base substrate and including a first via, wherein the gate lead is located near the buffer layer.
  • the gate On one side of the base substrate, the gate is located on a side of the buffer layer away from the base substrate, and the gate lead is connected to the gate through the first via hole.
  • the buffer layer further includes a second via hole, and the gate lead is electrically connected to a circuit element different from the driving transistor through the second via hole.
  • the circuit element includes a reset transistor, a compensation transistor, or a storage capacitor.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a second buffer layer, the second buffer layer being on the base substrate, and the gate lead is located far from the second buffer layer.
  • the side of the base substrate is located far from the second buffer layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a conductive layer located on a side of the gate lead away from the base substrate and covering at least part of the side surface of the gate lead and The surface of the gate lead away from the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a light-shielding layer, the gate lead and the light-shielding layer are in the same layer, and the light-shielding layer and the pixel driving circuit at least partially overlap.
  • the driving transistor further includes a semiconductor layer, and the gate lead is in the same layer as the semiconductor layer.
  • the semiconductor layer includes an unconducted channel region, a conductive source region, and a conductive drain region
  • the gate lead includes a conductive semiconductors.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, including: providing a base substrate, forming a pixel driving circuit on the base substrate, the pixel driving circuit including a driving transistor and a gate lead, the driving The transistor includes a gate, and the gate lead is electrically connected to the gate, wherein the gate lead is formed between the gate and the base substrate.
  • the manufacturing method provided by at least one embodiment of the present disclosure further includes: forming a data line on a side of the gate far away from the base substrate, wherein the driving transistor is formed to receive the data line on the gate.
  • the data voltage signal provided by the data line controls the driving current flowing through the driving transistor based on the data voltage signal, and the driving current is used to drive the light emitting device to work.
  • the preparation method provided by at least one embodiment of the present disclosure further includes: forming a shielding layer between the layer where the gate is located and the layer where the data line is located, wherein the shielding layer and the gate are insulated from each other And overlap each other in a direction perpendicular to the base substrate.
  • the gate lead and the light shielding layer are formed in the same layer, wherein the light shielding layer and the pixel driving circuit at least partially overlap.
  • forming the driving transistor further includes forming a semiconductor layer, wherein the gate lead and the semiconductor layer are formed in the same layer.
  • forming the gate lead and the semiconductor layer includes forming a semiconductor material layer, and the semiconductor material layer includes a channel region, a source region, a drain region and Gate lead region; doping the source region, the drain region and the gate lead region to make the source region, the drain region and the gate lead region conductive .
  • At least one embodiment of the present disclosure provides a display panel including any of the above-mentioned display substrates.
  • 1A is a circuit diagram of a pixel driving circuit of a display substrate
  • FIG. 1B is a schematic diagram showing that longitudinal crosstalk occurs on a substrate
  • Figure 1C is a curve of the relationship between the deviation of the gate voltage and the parasitic capacitance between the gate and the data line;
  • 2A is a schematic plan view of a pixel driving circuit of a display substrate
  • FIG. 2B is a schematic cross-sectional view of the pixel driving circuit in FIG. 2A along line A-A;
  • FIG. 2C is a schematic partial plan view of the pixel driving circuit in FIG. 2A;
  • 3A is a schematic cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • 3B is another schematic cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • 3C shows a schematic plan view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 4A is a schematic cross-sectional view of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 4B is another schematic cross-sectional view of another display substrate provided by some embodiments of the present disclosure.
  • 5A is a schematic cross-sectional view of still another display substrate provided by some embodiments of the present disclosure.
  • 5B is another schematic cross-sectional view of still another display substrate provided by some embodiments of the present disclosure.
  • 5C shows a schematic plan view of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 6A is a preparation flow chart of a display substrate provided by some embodiments of the present disclosure.
  • 6B-6F are schematic plan views of a display substrate provided by some embodiments of the disclosure during the manufacturing process
  • FIG. 7 is a preparation flow chart of another display substrate provided by some embodiments of the disclosure.
  • FIG. 8A is a preparation flow chart of still another display substrate provided by some embodiments of the present disclosure.
  • 8B-8E are schematic plan views of still another display substrate provided by some embodiments of the disclosure during the manufacturing process.
  • a display substrate includes a plurality of pixel units, and each pixel unit includes a light-emitting device and a pixel driving circuit for driving the light-emitting device.
  • the pixel driving circuit includes, for example, a driving transistor, a switching transistor, and a capacitor.
  • the basic pixel circuit in the display substrate is usually a 2T1C pixel circuit, that is, two TFTs (Thin-film Transistors) and a storage capacitor C are used to realize the basic function of driving the light-emitting device.
  • the threshold voltage of the driving transistor in each pixel circuit may be different due to the manufacturing process, and the threshold voltage of the driving transistor may drift due to, for example, the influence of temperature changes.
  • the industry also provides other pixel circuits with compensation functions on the basis of the above-mentioned 2T1C basic pixel circuits.
  • the compensation function can be realized by voltage compensation, current compensation or hybrid compensation.
  • the pixel circuits with compensation function can be, for example, 4T1C, 4T2C or 7T1C circuit, etc.
  • a display substrate has a 7T1C pixel driving circuit as shown in FIG. 1A, and the driving circuit controls the light-emitting state of the light-emitting device (D1) through seven transistors (T) and a storage capacitor (C1).
  • the working process of the pixel driving circuit mainly includes four stages, which are an initialization stage, a data writing and compensation stage, a reset stage and a light-emitting stage. The working process of the pixel driving circuit is briefly described below.
  • the first reset signal RST1 is input, the fourth transistor T4 is turned on, and the reset voltage VINT is applied to the control terminal of the driving transistor T1; the first light emission control signal EM1 is input, the fifth transistor T5 is turned on, and the first voltage VDD is applied to the first terminal (second node N2) of the driving transistor T1.
  • the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the reset voltage VINT can be applied to the gate of the first transistor T1, and the reset voltage VINT can make the first transistor T1 in a conductive state.
  • the scan signal GATE marked as G
  • data signal DATA marked as D
  • the second transistor T2 the driving transistor T1 and the third transistor T3 are turned on
  • the second transistor T2 transmits the data signal DATA Write to the source of the driving transistor T1 (the second node N2), and charge the gate of the driving transistor T1 (the first node N1) through the driving transistor T1 and the third transistor T3 until the gate of the driving transistor T1
  • the voltage is equal to (Vdata-Vth), where Vdata is the voltage value of the data signal DATA, and Vth is the threshold voltage of the driving transistor T1, which is stored by the storage capacitor C1, and the data voltage Vdata is written to the gate of the driving transistor T1 And it is stored by the storage capacitor C1, and the third transistor T3 performs threshold compensation on the driving transistor T1.
  • the second transistor T2 and the third transistor T3 are turned on by the scan signal GATE, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh
  • the data signal DATA charges the first node N1 (that is, the storage capacitor C1) after passing through the second transistor T2, the first transistor T1, and the third transistor T3 to charge the storage capacitor C1 in the subsequent
  • the light-emitting stage provides gray scale display data and compensates the threshold voltage of the first transistor T1 itself.
  • the second light emission control signal EM2 and the second reset signal RST2 are input, the sixth transistor T6 and the seventh transistor T7 are turned on, and the driving transistor T1, the third transistor T3 and the light emitting device are reset.
  • the sixth transistor T6 is turned on by the second light emission control signal EM2, and the seventh transistor T7 is turned on by the second reset signal RST2; at the same time, the second transistor T2, the third transistor T3, the fourth transistor T4 and the The five transistor T5 is turned off.
  • the drain of the first transistor T1 is discharged through the sixth transistor T6 and the seventh transistor T7, thereby simultaneously resetting the potentials of the third node N3 and the fourth node N4 (light emitting device D1), so that the light emitting device D1 is emitting light No light before the stage.
  • the first light emitting control signal EM1 and the second light emitting control signal EM2 are input, and the fifth transistor T5, the sixth transistor T6 and the first transistor T1 are turned on, so that the driving current is applied to the light emitting device D1 to make it emit light.
  • the anode and the cathode of the light-emitting device D1 are respectively applied with voltages, thereby emitting light under the action of the driving current flowing through the first transistor T1.
  • the light emitting device D1 is an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or the like.
  • the display substrate further includes a scan driving circuit and a data driving circuit.
  • the data driving circuit is connected to a plurality of data signal lines to provide a data signal DATA; for example, the data driving circuit can also be connected to a plurality of voltage lines and a plurality of reset voltage lines to provide voltage signals (such as VDD) and a reset voltage VINT, respectively.
  • the scan driving circuit is connected to a plurality of scan signal lines to provide a scan signal GATE; for example, the scan driving circuit can also be connected to a plurality of light emission control lines to provide a light emission control signal EM, and to a plurality of reset control lines to provide a reset signal RST.
  • FIG. 2A and 2B respectively show a plan view and a partial cross-sectional view of the above-mentioned pixel driving circuit.
  • the cross-sectional view in FIG. 2B is, for example, taken along A-A in FIG. 2A.
  • the pixel driving circuit part shown in FIG. 2B includes a gate 12 of a driving transistor, a gate lead 11 drawn through a via hole in a gate insulating layer 13, a data line 14, a metal layer 15, and the like.
  • the metal layer 15 is, for example, a part of the capacitor C1 or the wiring in the pixel driving circuit, or a metal layer structure formed by the same layer as the capacitor C1 and the wiring, and can be used as a shielding layer.
  • the gate lead 11 is, for example, used to electrically connect the gate 12 with other circuit structures, for example, in the pixel driving circuit shown in FIG. 1A, for connecting the gate 12 to the first node N1.
  • an opening needs to be formed in the metal layer 15 for the gate lead 11 to be drawn out.
  • the metal layer 15 forms an opening corresponding to the gate lead 11.
  • FIG. 2C shows a schematic plan view of the layer where the metal layer 15 is located and the functional layer below.
  • the metal layer 15 has an opening 15A to facilitate the gate lead 11 to be drawn out.
  • the inventor of the present application discovered in research that in the above pixel driving circuit, at the opening position of the metal layer 15, the gate 12 of the driving transistor and the data line 14 easily form a parasitic capacitance, so the data signal in the data line 14 jumps At this time, the parasitic capacitance easily causes errors in the driving signal applied to the gate 12 of the driving transistor, thereby affecting the light-emitting effect of the light-emitting device.
  • FIG. 1B shows a schematic diagram of a display screen of a display substrate when the data signal DATA jumps.
  • the display signal is scanned from top to bottom, the two sides of the display panel are displayed in L127 gray scale, the middle of the display panel is displayed in L0 gray scale, and then the data signal DATA starts from the signal corresponding to the L0 gray scale.
  • the jump becomes a signal corresponding to the L127 gray scale, but due to the parasitic capacitance formed between the gate 12 of the driving transistor and the data line 14, the voltage of the gate 12 of the driving transistor deviates from the initial value, causing the data signal DATA to jump
  • the display screen in the middle of the display panel cannot be accurately displayed as the L127 gray scale, but is displayed as the LX gray scale different from the L127 gray scale, thereby causing vertical display crosstalk.
  • the gate voltage of the driving transistor T1 is maintained by the storage capacitor C1.
  • the data signal DATA jumps, due to the existence of the parasitic capacitance between the gate 12 of the driving transistor T1 and the data line 14 , The gate voltage of the driving transistor T3 will also change, thereby deviating from the initial value, so that the driving current flowing through the first transistor T1 has a certain deviation, which affects the light-emitting effect of the light-emitting device D1 and causes display errors.
  • FIG. 1C shows the gate The relationship curve between the deviation of the pole voltage and the parasitic capacitance between the gate and the data line. It can be seen that when the parasitic capacitance between the gate and the data line is small or there is no parasitic capacitance, the gate voltage of the driving transistor T3 The deviation from the initial value is small or has no deviation.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a pixel driving circuit.
  • the pixel driving circuit is on the base substrate and includes a driving transistor and a gate lead.
  • the driving transistor includes a gate.
  • the gate lead is electrically connected to the gate.
  • the gate lead is located between the gate and the base substrate.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, which includes: providing a base substrate, and forming a pixel drive circuit on the base substrate.
  • the pixel drive circuit includes a drive transistor and a gate lead, and the drive transistor includes a gate and a gate.
  • the electrode lead is electrically connected to the gate, and the gate lead is formed between the gate and the base substrate.
  • FIGS. 3A and 3B show schematic diagrams of different cross-sections of the display substrate.
  • Figure 3A mainly shows the relative positional relationship of the gate, gate lead, and data line of the drive transistor of the display substrate
  • Figure 3B mainly shows the overall structure of the drive transistor of the display substrate and the gate lead and other How the circuit components are connected.
  • Fig. 3C shows a schematic plan view of the display substrate, and Fig. 3A is cut along the line B-B in Fig. 3C, for example.
  • the display substrate includes a base substrate 101 and a pixel driving circuit.
  • the embodiments of the present disclosure do not impose limitations on the pixel driving circuit.
  • it may be the above-mentioned 2T1C type pixel driving circuit, or may be 4T2C, 7T1C type, and so on.
  • the pixel driving circuit is on the base substrate 101 and includes a driving transistor and a gate lead 103.
  • the driving transistor includes a gate 102.
  • the gate lead 103 is electrically connected to the gate 102.
  • the gate lead 103 is located between the gate 102 and the base substrate 101. between.
  • the gate lead 103 is used to electrically connect the gate 102 with other circuit structures.
  • the display substrate also includes structures such as a data line 104 on the base substrate 101, and the data line 104 is located on the side of the gate 102 away from the base substrate 101.
  • the driving transistor is configured to receive and store (through a storage capacitor) the data voltage signal provided by the data line 104 at the gate 102, and control the driving current flowing through the driving transistor based on the data voltage signal, and the driving current is used to drive the light emitting device to work.
  • the gate lead 103 and the data line 104 are located on both sides of the gate 102, and the gate lead 103 is electrically connected to the gate 102 through the via hole.
  • the display substrate further includes a shielding layer 105, the shielding layer 105 is disposed between the layer where the gate 102 is located and the layer where the data line 104 is located, and the shielding layer 105 is connected to
  • the gate electrodes 102 are insulated from each other and overlap each other in a direction perpendicular to the base substrate 101. In this way, the shielding layer 105 can avoid parasitic capacitance between the gate 102 and the data line 104.
  • the extraction of the gate lead 103 will not damage the integrity of the shielding layer 105.
  • the shielding layer 105 does not need to form an opening for leading the gate lead 103. Therefore, the shielding layer 105 has a certain integrity and can achieve a good shielding effect.
  • the shielding layer 105 is a conductive layer, such as a metal layer.
  • the shielding layer 105 is an existing structure in the pixel driving circuit, for example, an electrode of the capacitor in the pixel driving circuit or a wiring layer of the pixel driving circuit, or the shielding layer 105 is connected to the capacitor of the pixel driving circuit.
  • FIG. 3C shows a schematic plan view of the display substrate.
  • the orthographic projection of the gate lead 103 on the base substrate and the orthographic projection of the shielding layer 105 on the base substrate at least partially overlap. Since the gate lead 103 is drawn from between the gate 102 and the base substrate 101, there is no opening in the shielding layer 105.
  • the shielding layer 105 when the shielding layer 105 is an electrode of the capacitor in the pixel driving circuit, the absence of an opening in the shielding layer 105 can increase the area of the capacitor electrode (that is, the area of the orthographic projection of the shielding layer 105 on the base substrate increases). Thus, the capacitance of the capacitor can be increased or the space occupied by the electrode can be reduced while maintaining the capacitance.
  • the gate 102 can also be used as another electrode of the capacitor, whereby the gate 102, the shielding layer 105 and the insulating layer between the two together form a capacitor, which can be used as a storage capacitor in the pixel driving circuit.
  • the driving transistor further includes a gate insulating layer 107, a semiconductor layer 110 and other structures.
  • the gate insulating layer 107 is located between the gate 102 and the semiconductor layer 110 to insulate the two.
  • the semiconductor layer 110 includes an unconducted channel region 110A, a conductive source region 110B, and a conductive drain region 110C.
  • the channel region 110A corresponds to the gate 102, and the source region 110B and the drain region 110C are doped regions of the semiconductor layer 110, so that the source region 110B and the drain region 110C are conductive and have good conductivity.
  • the source and drain of the drive transistor respectively.
  • the source of the driving transistor is electrically connected to other elements through the wiring 104A, for example, for transmitting data signals.
  • the display substrate further includes an interlayer insulating layer 108, and the interlayer insulating layer 108 covers the driving transistor.
  • the gate lead 103, the gate insulating layer 107, the gate 102, the interlayer insulating layer 108, and the data line 104 are sequentially stacked on the base substrate 101, whereby the gate lead 103 and the data line 104 are respectively arranged On both sides of the gate 102.
  • the display substrate further includes a buffer layer 106 disposed on the base substrate 101, and the gate lead 103 is electrically connected to the gate 102 through a via hole in the buffer layer 106.
  • the buffer layer 106 includes a first via 1061
  • the gate lead 103 is located on the side of the buffer layer 106 close to the base substrate 101, that is, the lower side of the buffer layer 106 is shown in the figure
  • the gate 102 is located on the buffer layer 106.
  • the gate lead 103 passes through the first via 1061 and the gate insulating layer 107 that communicates with the first via 1061 The hole is electrically connected to the gate 102.
  • the buffer layer 106 further includes a second via 1062, and the gate lead 103 is electrically connected to a circuit element other than the driving transistor through the second via 1062.
  • the gate lead 103 can electrically connect the gate 102 of the driving transistor to other circuit structures.
  • the wiring for electrical connection through the second via 1062 may also be a wiring or element 103A on the same layer as the gate lead 103.
  • the wiring or element 103A may be any signal wiring or functional element (for example, an electrode or a light shielding layer, etc.) on the display substrate, which is not limited in the embodiment of the present disclosure.
  • circuit elements other than drive transistors include reset transistors, compensation transistors, or storage capacitors.
  • the circuit elements different from the driving transistor T1 are the third transistor T3, the fourth transistor T4 or the storage capacitor C1, etc., which are connected to the driving transistor T1 through the gate lead (including the node N1).
  • the grid is electrically connected.
  • the reference numeral 111 shows a conductive structure such as a part of the above-mentioned circuit element or a wire connecting the above-mentioned circuit element.
  • the conductive structure 111 and the semiconductor layer 110 are provided in the same layer, so the two can be formed by the same semiconductor film layer in the manufacturing process.
  • the same semiconductor film layer is processed by a patterning process and a doping process, thereby forming a portion corresponding to the conductive structure 111 and a portion of the semiconductor layer 110, and the portion corresponding to the semiconductor layer 110 includes, for example, a channel region. , Source area and drain area.
  • heavy doping is performed at positions corresponding to the conductive structure 111, the source region and the drain region, thereby forming the conductive layer 211, the source electrode and the drain electrode with good conductivity.
  • the semiconductor film layer used to form the conductive structure 111 and the semiconductor layer 110 is a polysilicon film layer or an oxide semiconductor film layer.
  • the polysilicon film layer may include low temperature polysilicon or high temperature polysilicon
  • the oxide semiconductor film layer may include IGZO (Indium Oxide Gallium zinc), etc.
  • the heavily doped part of the semiconductor film layer has good conductivity, for example, for the polysilicon film layer, for example, doped with boron ions (B 3+ ) to achieve p-doping, or doped with phosphorus ions ( P 3- )
  • the doping method can adopt various methods such as ion implantation and thermal diffusion, which are not limited in the embodiments of the present disclosure.
  • the display substrate further includes a light shielding layer.
  • the light shielding layer is located between the base substrate 101 and the buffer layer 106 and at least partially overlaps the pixel driving circuit.
  • the light-shielding layer is disposed at the position of the dashed frame indicated by the reference number 112, which corresponds to the channel region 110A of the semiconductor layer 110, so that the light-shielding layer can prevent ambient light from irradiating the channel region 110A, thereby preventing the ambient light from affecting the driving The normal operation of the transistor.
  • the light-shielding layer and the gate lead 103 are arranged in the same layer, and both are made of a metal layer. Therefore, the light-shielding layer and the gate lead 103 can be formed by the same patterning process using the same thin film during the preparation process, which can simplify the display substrate. Preparation Process.
  • the display substrate further includes a second interlayer insulating layer 109 covering the shielding layer 105, and the trace 104A passes through the gate insulating layer 107, the interlayer insulating layer 108, and the second interlayer insulating layer 109.
  • the via is electrically connected to the source of the driving transistor, for example, for transmitting a data voltage signal, so that the driving transistor can receive the data voltage signal provided by the wiring 104A and control the driving current flowing through the driving transistor based on the data voltage signal.
  • the base substrate 101 adopts any suitable substrate such as a glass substrate, a quartz substrate, and a plastic substrate.
  • One or more of the gate 102, the gate lead 103, the data line 104, and the shielding layer 105 are formed of copper, silver, aluminum, molybdenum and other metal materials or alloy materials.
  • the buffer layer 106 is formed of organic insulating materials such as polyimide (PI), acrylate, and epoxy resin, or inorganic insulating materials (for example, silicon nitride).
  • One or more of the gate insulating layer 107, the interlayer insulating layer 108, and the second interlayer insulating layer 109 are made of organic insulating materials such as polyimide, acrylate, and epoxy, or silicon oxide, silicon nitride, and It is formed of inorganic insulating materials such as silicon oxynitride.
  • organic insulating materials such as polyimide, acrylate, and epoxy, or silicon oxide, silicon nitride, and It is formed of inorganic insulating materials such as silicon oxynitride.
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the gate lead 103 and the data line 104 can be arranged on both sides of the gate 102, for example, the gate lead 103 is arranged on Between the gate 102 and the base substrate 101, a shielding layer 105 with a certain integrity can be formed between the gate 102 and the data line 104.
  • the shielding layer 105 can prevent the formation of parasitic capacitance between the gate 102 and the data line 104 Therefore, the possible adverse effects of the parasitic capacitance are avoided, and the display quality of the display substrate is improved.
  • the gate lead of the display substrate can also be drawn in other ways, and these ways can achieve the above technical effects.
  • FIGS. 4A and 4B show schematic diagrams of different cross-sections of display substrates provided by other embodiments of the present disclosure.
  • FIG. 4A mainly shows the relative positional relationship of the gate, gate lead, and data line of the driving transistor of the display substrate
  • FIG. 4B mainly shows the overall structure and gate of the driving transistor of the display substrate.
  • the connection method of the lead wire and other circuit components For a schematic plan view of the display substrate, refer to FIG. 3C.
  • the display substrate includes a base substrate 201 and a pixel driving circuit.
  • the pixel driving circuit is on the base substrate 201 and includes a driving transistor and a gate lead 203.
  • the driving transistor includes a gate 202.
  • the gate lead 203 is electrically connected to the gate 202.
  • the gate lead 103 is located between the gate 202 and the base substrate 201. between.
  • the display substrate also includes structures such as a data line 204 on the base substrate 201, and the data line 204 is located on the side of the gate 202 away from the base substrate 201.
  • the driving transistor is configured to receive and store (through a storage capacitor) the data voltage signal provided by the data line 204 at the gate 202, and control the driving current flowing through the driving transistor based on the data voltage signal, and the driving current is used to drive the light emitting device to work.
  • the gate lead 203 and the data line 204 are located on both sides of the gate 202, and the gate lead 203 is electrically connected to the gate 202 through the via hole.
  • the display substrate further includes a shielding layer 205, a buffer layer 206, a semiconductor layer 210, a gate insulating layer 207, an interlayer insulating layer 208, and a second interlayer insulating layer. 209 and other structures.
  • the semiconductor layer 210 includes an unconducted channel region 210A, a conductive source region 210B, and a conductive drain region 210C.
  • the channel region 210A corresponds to the gate 202, and the source region 210B and the drain region 210C are doped regions of the semiconductor layer 210, so that the source region 210B and the drain region 210C are conductive, and have good conductivity.
  • the source and drain of the drive transistor respectively.
  • the source of the driving transistor is electrically connected to other components through the wiring 204A, for example, for transmitting data signals.
  • the buffer layer 206 is located on the base substrate 201, and the gate lead 203 is located on the side of the buffer layer 206 away from the base substrate 201, namely It is located on the upper side of the buffer layer 206 in the figure.
  • the gate lead 203 is electrically connected to the gate 202 through the via hole in the gate insulating layer 207.
  • the display substrate further includes a conductive layer 211.
  • the conductive layer 211 is located on the side of the gate lead 203 away from the base substrate 201 and covers at least part of the side of the gate lead 203 and the gate. The surface of the lead 203 away from the base substrate 201, so that the conductive layer 211 can be directly formed on the gate lead 203 during the preparation process.
  • the conductive layer 211 is a conductive structure such as a part of a circuit element different from the driving transistor or a wiring connecting a circuit element different from the driving transistor.
  • the gate lead 203 electrically connects the gate 102 of the driving transistor with other circuit structures.
  • circuit elements other than the driving transistor include reset transistors, compensation transistors, or storage capacitors, which are not limited in the embodiments of the present disclosure.
  • the conductive layer 211 may also cover the traces or elements 203A in the same layer as the gate lead 203.
  • the trace or element 203A can be any signal trace or functional element (such as an electrode or a light shielding layer, etc.) on the display substrate, which is not limited in the embodiment of the present disclosure.
  • the conductive layer 211 and the semiconductor layer 210 are provided in the same layer, so they can be formed using the same semiconductor film layer in the manufacturing process.
  • the specific setting method refer to the above-mentioned embodiment, which will not be repeated here.
  • the display substrate may further include a light shielding layer.
  • the light shielding layer is located between the semiconductor layer 210 and the buffer layer 206, and is at least connected to the pixel driving circuit. Partially overlapped.
  • the light-shielding layer is provided at the position of the dashed frame indicated by the reference numeral 212, which corresponds to the position of the channel region 210A of the semiconductor layer 210.
  • an insulating layer (not shown in the figure) is formed between the light-shielding layer and the semiconductor layer 210. ).
  • the light-shielding layer and the gate lead 203 are provided in the same layer, so that the light-shielding layer and the gate lead 203 can be formed by the same patterning process using the same film during the manufacturing process, thereby simplifying the manufacturing process of the display substrate.
  • the examples shown in FIGS. 4A and 4B do not have a via structure in the buffer layer 206, so one via formation process can be reduced during the manufacturing process, which can further simplify the display The preparation process of the substrate.
  • a shielding layer 205 with a certain integrity can be provided between the gate 202 and the data line 204, and the shielding layer 205 can prevent the gate 202 from the data line 204.
  • a parasitic capacitance is formed between them, so as to avoid possible adverse effects of the parasitic capacitance and improve the display quality of the display substrate.
  • the shielding layer 205 is an electrode of the capacitor in the pixel driving circuit
  • the absence of an opening in the shielding layer 205 can increase the area of the capacitor electrode, thereby increasing the capacitance of the capacitor or reducing the electrode while maintaining the capacitance. The space occupied.
  • FIG. 5A and FIG. 5B show schematic diagrams of different cross-sections of a display substrate provided by still other embodiments of the present disclosure.
  • FIG. 5A mainly shows the relative positional relationship of the gate, gate lead, and data line of the driving transistor of the display substrate
  • FIG. 5B mainly shows the overall structure and the gate of the driving transistor of the display substrate.
  • FIG. 5C shows a schematic plan view of the display substrate, and FIG. 5A is cut along the line C-C in FIG. 5C, for example.
  • the display substrate includes a base substrate 301 and a pixel driving circuit.
  • the pixel driving circuit is on the base substrate 301 and includes a driving transistor and a gate lead 303.
  • the driving transistor includes a gate 302.
  • the gate lead 303 is electrically connected to the gate 302.
  • the gate lead 303 is located between the gate 302 and the base substrate 301. between.
  • the display substrate further includes a structure such as a data line 304 on the base substrate 301, and the data line 304 is located on the side of the gate 302 away from the base substrate 301.
  • the driving transistor is configured to receive and store (via a storage capacitor) the data voltage signal provided by the data line 304 at the gate 302, and control the driving current flowing through the driving transistor based on the data voltage signal, and the driving current is used to drive the light emitting device to operate.
  • the gate lead 303 and the data line 304 are located on both sides of the gate 302, and the gate lead 303 is electrically connected to the gate 302 through the via hole.
  • the display substrate further includes a shielding layer 305, a buffer layer 306, a gate insulating layer 307, an interlayer insulating layer 308, and a second interlayer insulating layer 309.
  • a shielding layer 305 for example, as shown in FIGS. 5A and 5B, the display substrate further includes a shielding layer 305, a buffer layer 306, a gate insulating layer 307, an interlayer insulating layer 308, and a second interlayer insulating layer 309.
  • a shielding layer 305 for example, a buffer layer 306, a gate insulating layer 307, an interlayer insulating layer 308, and a second interlayer insulating layer 309.
  • the gate lead 303 and the semiconductor layer 310 are arranged in the same layer, so the same semiconductor layer can be formed by patterning and doping in the preparation process. .
  • the driving transistor includes a semiconductor layer 310, and the semiconductor 310 includes an unconducted channel region 310A, a conductive source region 310B, and a conductive drain region 310C.
  • the channel region 310A corresponds to the gate 302, and the source region 310B and the drain region 310C are doped regions, so that the source region 310B and the drain region 310C are conductive and have good conductivity, which can be used as driving transistors respectively
  • the source and drain includes a conductive semiconductor material. In the preparation process, the same semiconductor layer can be doped to form a conductive source region 310B, a drain region 310C, and a gate lead 303.
  • the channel region 310A is also a doped region, but its doping concentration is much lower than that of the source region 310B and the drain region 310C.
  • the source of the driving transistor is electrically connected to other components through the wiring 304A, for example, for transmitting data signals.
  • the same semiconductor layer is patterned and doped to form the gate lead 303 and the semiconductor layer 310 at the same time, other conductive structures 311 connected to the gate lead 303 may also be formed.
  • the conductive structure 311 It can also be obtained by doping the semiconductor layer. Therefore, the gate lead 303, the semiconductor layer 310, and the conductive structure 311 for connecting the gate lead 303 and other circuit elements can be arranged in the same layer, and can be formed by patterning and doping the same semiconductor layer. This can further simplify the preparation process.
  • the gate lead 303, the semiconductor layer 310, and the conductive structure 311 can be formed by performing a doping process on the same semiconductor layer, so the three are located in the same layer.
  • the gate lead 303 and the conductive structure 311 can be directly electrically connected through a conductive semiconductor material. Compared with the display substrate shown in FIG. 3C, there is no need to connect the gate lead 303 and the conductive structure 311.
  • a structure such as a via for connecting the conductive structure 311 and the gate lead 303 is further formed there.
  • a shielding layer 305 with a certain integrity can be provided between the gate 302 and the data line 304.
  • the shielding layer 305 can prevent the formation of parasitic capacitance between the gate 302 and the data line 304, thereby avoiding The possible adverse effects of the parasitic capacitance can improve the display quality of the display substrate.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, which includes: providing a base substrate, and forming a pixel drive circuit on the base substrate.
  • the pixel drive circuit includes a drive transistor and a gate lead, and the drive transistor includes a gate and a gate.
  • the electrode lead is electrically connected to the gate, and the gate lead is formed between the gate and the base substrate.
  • the manufacturing method of the display substrate further includes forming a data line, the data line is formed on the side of the gate away from the base substrate, and the driving transistor is configured to receive the data voltage signal provided by the data line at the gate and control based on the data voltage signal The driving current flowing through the driving transistor is used to drive the light emitting device to work.
  • the flow chart of the preparation method thereof is shown in FIG. 6A, and the preparation method at least includes steps S101-S111.
  • Step S101 Provide a base substrate.
  • the provided base substrate 101 includes various types of substrates such as a glass substrate, a quartz substrate, a plastic substrate, etc.
  • the base substrate 101 is formed with a barrier layer (not shown in the figure), for example, and the barrier layer covers the base substrate 101. It can prevent the impurities that may exist in the base substrate 101 and impurities such as water and oxygen from entering other film layers to be formed thereon, thereby avoiding the deterioration of the electrical performance of the driving transistor and the like.
  • the barrier layer is made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, for example, formed into a multilayer structure in which silicon oxide and silicon nitride are alternately stacked.
  • Step S102 forming a gate lead.
  • a gate lead 103 is first formed on the base substrate 101.
  • the gate lead 103 is formed of metal materials or alloy materials such as copper, silver, aluminum, and molybdenum.
  • a gate lead material layer is formed on the base substrate 101 by evaporation, sputtering, etc., and then a patterning process is performed on the gate lead material layer to form the gate lead 103.
  • one patterning process includes photoresist coating, exposure, development, and etching of the material layer, which are not limited in the embodiment of the present disclosure.
  • the preparation method further includes forming a light-shielding layer.
  • the gate lead 103 and the light-shielding layer are formed in the same layer, and the light-shielding layer and the pixel driving circuit at least partially overlap, for example, formed in the corresponding layer.
  • the light shielding layer can prevent ambient light from irradiating the channel region 110A.
  • the light shielding layer and the gate lead 103 are formed using the same thin film through the same patterning process, thereby simplifying the manufacturing process of the display substrate.
  • Step S103 forming a buffer layer.
  • a buffer layer 106 is formed on the gate lead 103.
  • the buffer layer 106 is formed of, for example, an organic insulating material or an inorganic insulating material, such as polyimide (PI), acrylate, epoxy, etc.
  • Organic insulating materials, or inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • a buffer material layer is formed on the gate lead 103 by coating or the like, and then a patterning process is performed on the buffer material layer to form the via 1062 of the conductive structure 111 to be formed after the connection.
  • Step S104 forming a semiconductor layer.
  • the semiconductor layer 110 of the driving transistor is formed on the buffer layer 106, and the conductor layer 110 is formed of, for example, a polysilicon semiconductor.
  • the amorphous silicon material layer is formed on the buffer layer 106 by deposition or the like, the amorphous silicon material layer is crystallized by means such as laser annealing to obtain a polysilicon material layer, and then a patterning process is performed on the polysilicon material layer to form a corresponding layer.
  • the area of the driving transistor the area includes, for example, a channel region 110A, a source region 110B, and a drain region 110C.
  • the patterning process also forms a conductive region corresponding to the conductive structure 111.
  • the source region 110B, the drain region 110C, and the conductive region are doped, such as heavily doped with impurities such as boron or phosphorus, to make the polysilicon material conductive, thereby having good conductivity, and forming the source of the driving transistor
  • the electrode and the drain electrode and the conductive structure 111 are doped.
  • the channel region 110A may also be lightly doped with impurities such as boron or phosphorus according to the characteristics of the thin film transistor to form the channel of the thin film transistor.
  • the semiconductor layer 110 and the conductive structure 111 are formed in the same layer, which can simplify the manufacturing process of the display substrate.
  • the 7T1C circuit structure shown in FIG. 1A is formed in the display substrate, which includes seven thin film transistors and one storage capacitor. At this time, in the preparation process, the seven thin film transistors can be formed in the same process. Therefore, when forming the semiconductor layer 110 of the driving transistor (T1), the semiconductor layers of other transistors T2 to T7 are also formed. The positions of the semiconductor layers of T2 to T7 are shown in FIG. 6B.
  • Step S105 forming a gate insulating layer.
  • a gate insulating layer 107 is formed on the semiconductor layer 110 and the conductive structure 111.
  • the gate insulating layer 107 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. It is formed of organic insulating materials such as polyimide (PI), acrylate, and epoxy resin.
  • PI polyimide
  • a gate insulating material layer is formed by deposition or coating on the semiconductor layer 110 and the conductive structure 111, and then the gate insulating material layer and the buffer layer 106 are patterned to form a via 1061 exposing the gate lead 103 , In order to connect the gate 102 to be formed later.
  • Step S106 forming a gate.
  • a gate 102 is formed on the gate insulating layer 107.
  • the gate 102 is made of, for example, copper, silver, aluminum, molybdenum and other metal materials or alloy materials. form.
  • a gate material layer is formed on the gate insulating layer 107 by evaporation, sputtering, or the like, and then a patterning process is performed on the gate material layer to form the gate 102.
  • the gate 102 is electrically connected to the gate lead 103 through the via 1061.
  • the gate 102 may be formed on the same layer as the wiring for transmitting the light emission control signal EM, the wiring for transmitting the reset signal RST, and the wiring for transmitting the scan signal GATE.
  • the trace for transmitting the reset signal RST covers the channel region of the semiconductor layer of the fourth transistor T4, and the trace portion covering the channel region serves as the gate of the fourth transistor T4, and the fourth transistor T4 can be used as the reset transistor.
  • the traces that transmit the scan signal GATE cover the channel regions of the semiconductor layers of the second transistor T2 and the third transistor T3, and part of the traces that cover the channel region of the second transistor T2 serve as the gate of the second transistor T2.
  • T2 can be used as a switching transistor; part of the wiring covering the channel region of the third transistor T3 is used as the gate of the third transistor T3, and the second transistor T3 can be used as a compensation transistor.
  • the wiring that transmits the emission control signal EM covers the channel regions of the semiconductor layers of the fifth transistor T5 and the sixth transistor T6, and a part of the wiring that covers the channel region of the fifth transistor T5 serves as the gate of the fifth transistor T5.
  • the transistor T5 can be used as a driving control transistor; a part of the wiring covering the channel region of the sixth transistor T6 can be used as the gate of the sixth transistor T6, and the sixth transistor T6 can be used as a light emitting control transistor.
  • the trace that transmits another scan signal GATE covers the channel region of the semiconductor layer of the seventh transistor T7, and a part of the trace that covers the channel region of the seventh transistor T7 serves as the gate of the seventh transistor T7.
  • the seventh transistor T7 can be used as Bypass transistor.
  • the gate 102 can also be used as an electrode of the storage capacitor C1, and together with another electrode formed later and an insulating layer between the two to form the storage capacitor C1.
  • Step S107 forming an interlayer insulating layer.
  • an interlayer insulating layer 108 is formed on the gate 102.
  • the interlayer insulating layer 108 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or other inorganic insulating materials, or polyimide (PI), It is made of organic insulating materials such as acrylate and epoxy resin.
  • an interlayer insulating material layer is formed on the gate 102 by deposition or coating, and a patterning process is performed on the interlayer insulating material layer to form a desired pattern.
  • Step S108 forming a shielding layer.
  • a shielding layer 105 is formed on the interlayer insulating layer 108.
  • the shielding layer 105 is made of, for example, copper, silver, aluminum, molybdenum and other metal materials or alloy materials. form.
  • a shielding material layer is formed on the interlayer insulating layer 108 by evaporation or sputtering, and then a patterning process is performed on the shielding material layer to form the shielding layer 105 at a position corresponding to the gate 102.
  • the shielding layer 105 and the gate 102 are insulated from each other and overlap each other in a direction perpendicular to the base substrate 201. As shown in FIG. 6D, no opening is formed in the shielding layer 105.
  • the shielding layer 105 is formed with the same layer as the wiring for transmitting the reset voltage VINT and the second shielding layer 1051.
  • the second shielding layer 1051 can prevent parasitic capacitance from being generated between two adjacent conductive layers, for example, can prevent parasitic capacitance from being generated between the semiconductor layer and a data line to be formed later.
  • the shielding layer 105 can be used as another electrode of the storage capacitor C1, and together with the gate 102 and the interlayer insulating layer between the two to form the storage capacitor C1. Since the shielding layer 105 does not have an opening, the area of the shielding layer 105 is larger, so that the capacitance of the storage capacitor C1 can be increased or the space occupied by the shielding layer 105 can be reduced while maintaining the capacitance.
  • Step S109 forming a second interlayer insulating layer.
  • a second interlayer insulating layer 109 is formed on the shielding layer 105.
  • the second interlayer insulating layer 109 is made of silicon oxide, silicon nitride, or oxynitride. It is formed of inorganic insulating materials such as silicon or organic insulating materials such as polyimide (PI), acrylic, and epoxy.
  • PI polyimide
  • a second interlayer insulating material layer is formed on the shielding layer 105 by deposition or coating, and a patterning process is performed on the second interlayer insulating material layer to form a desired pattern.
  • the patterning process also includes the second The interlayer insulating material layer, the gate insulating layer 107, and the interlayer insulating layer 108 are formed with a via 1081 exposing the source 110B of the driving transistor, so that the source 110B and the trace 104A to be formed later, such as a data line 104 and other connections.
  • via hole 1081 when the via hole 1081 is formed, other via holes are also formed, such as via holes exposing the source and drain of other thin film transistors to facilitate electrical connection.
  • Step S110 forming a data line.
  • a data line 104 is formed on the second interlayer insulating layer 109.
  • the data line 104 is, for example, copper, silver, aluminum, molybdenum and other metals. Material or alloy material.
  • a data line material layer is formed on the second interlayer insulating layer 109 by evaporation or sputtering, and then a patterning process is performed on the data line material layer to form the data line 104.
  • the data line 104 is formed in the same layer as the power line for transmitting the first voltage VDD and the connection electrode 1041.
  • the connecting electrode 1041 is used to electrically connect the two conductive structures, for example, electrically connecting the source and drain of the seventh thin film transistor T7 to a wiring that transmits the reset voltage VINT.
  • Step S111 forming a light emitting device and the like.
  • a flat layer, a pixel defining layer, a light-emitting device including a cathode, an anode, and a light-emitting layer between the cathode and the anode, etc.
  • spacers, encapsulation layers and other structures can be further formed.
  • the materials, patterns and their forming methods can be referred to conventional technologies, and the description of the embodiments of the present disclosure will not be repeated.
  • the light emitting device of the embodiment of the present disclosure may be an OLED or QLED or the like.
  • the display substrate shown in FIG. 3A and FIG. 3B can be formed by the above method.
  • the gate lead 103 is formed between the gate 102 and the base substrate 101, so the gate lead 103 and the data line 104 are formed on the gate.
  • a shielding layer 105 with a certain integrity can be formed between the gate 102 and the data line 104.
  • the shielding layer 105 can prevent the formation of parasitic capacitance between the gate 102 and the data line 104, thereby avoiding the parasitic
  • the possible adverse effects of capacitors can improve the display quality of the display substrate.
  • some embodiments of the present disclosure also provide a preparation method for forming the display substrate as shown in FIG. 4A and FIG. 4B.
  • the flowchart of the preparation method is shown in FIG. 7, and the preparation method at least includes steps S201-S211.
  • this method differs mainly in the formation sequence and formation structure of the buffer layer, the gate lead, and the semiconductor layer in step S202-step S204. The following will focus on the difference, and other parts of the formation method can refer to the above-mentioned embodiment.
  • Step S201 Provide a base substrate.
  • Step S202 forming a buffer layer.
  • a buffer layer 206 is formed on the base substrate 201.
  • the material and forming method of the buffer layer 206 can be referred to the above-mentioned embodiments, which will not be repeated here.
  • Step S203 forming a gate lead.
  • the gate lead 203 is formed on the buffer layer 206.
  • the material and the forming method of the gate lead 203 can refer to the above-mentioned embodiment, and will not be repeated here.
  • the gate lead 203 and the light-shielding layer are formed in the same layer, and the formation method thereof can be referred to the above-mentioned embodiment, which will not be repeated here.
  • Step S204 forming a semiconductor layer.
  • the semiconductor layer 210 is formed on the gate lead 203 and the conductive layer 211 is formed at the same time, that is, the conductive layer 211 and the semiconductor layer 210 are formed using the same semiconductor film layer.
  • a polysilicon material layer is formed on the gate lead 203, and then a patterning process is performed on the polysilicon material layer to form regions corresponding to the channel, source, and drain of the driving transistor.
  • the region includes, for example, the channel region 210A, the source The polar region 210B and the drain region 210C, and at the same time, the patterning process also forms a conductive region corresponding to the conductive layer 211.
  • the source region 210B, the drain region 210C, and the conductive region are doped, such as heavily doped with impurities such as phosphorus and boron, so that these regions have good conductivity, thereby forming the source and drain of the driving transistor. Pole and conductive layer 211.
  • the channel region 210A may be lightly doped with impurities such as boron or phosphorus according to the characteristics of the thin film transistor to form the channel of the thin film transistor.
  • the conductive layer 211 is directly formed on the gate lead 203 and covers at least part of the side surface of the gate lead 203 and the surface of the gate lead 203 away from the base substrate 201.
  • Step S205 forming a gate insulating layer.
  • a gate insulating layer 207 is formed on the semiconductor layer 210 and the conductive layer 211, and a via hole exposing the gate lead 203 is formed in the gate insulating layer 207 through a patterning process, In order to be connected to the gate 202 to be formed later.
  • Step S206 forming a gate.
  • Step S207 forming an interlayer insulating layer.
  • Step S208 forming a shielding layer.
  • Step S209 forming a second interlayer insulating layer.
  • Step S210 forming a data line.
  • Step S211 forming a light emitting device and the like.
  • some embodiments of the present disclosure also provide a preparation method for forming the display substrate as shown in FIGS. 5A and 5B.
  • the flow chart of the preparation method is shown in FIG. 8A.
  • the preparation method at least includes steps S301-S310.
  • this method differs mainly in the manner of forming the gate lead and the semiconductor layer in step S303. The following will focus on the difference, and other parts of the formation method can refer to the above-mentioned embodiment.
  • Step S301 Provide a base substrate.
  • Step S302 forming a buffer layer.
  • Step S303 forming a gate lead and a semiconductor layer.
  • the gate lead 303 and the semiconductor layer 310 of the driving transistor are formed using the same polysilicon material layer through a patterning process and a doping process.
  • forming the semiconductor layer 310 of the gate lead 303 and the driving transistor includes: forming a semiconductor material layer (for example, a polysilicon material layer), the semiconductor material layer includes a channel region 310A, a source region 310B, a drain region 310C, and a gate lead region (Area indicated by 303); doping the source region 310B, the drain region 310C and the gate lead region to make the source region 310B, the drain region 310C and the gate lead region conductive.
  • the gate lead region is first doped to form the gate lead 303, and the source region 310B and the drain region 310C are second doped to form the source and drain of the driving transistor.
  • both the first doping and the second doping are heavily doped, so that the polysilicon material layer has good conductivity.
  • the channel region 110A can also be subjected to third doping, such as light doping, to form the channel of the thin film transistor.
  • the doping is boron doping or phosphorus doping, which is not limited in the embodiments of the present disclosure.
  • the conductive structure 311 connected to the gate lead 303 can also be formed.
  • the polysilicon layer corresponding to the conductive structure 311 is also heavily doped. To have good conductivity.
  • Step S304 forming a gate insulating layer.
  • Step S305 forming a gate.
  • the gate 302 is formed at a position corresponding to the channel region 310A, and its specific formation method can refer to the above-mentioned embodiment, which will not be repeated here.
  • Step S306 forming an interlayer insulating layer.
  • Step S307 forming a shielding layer.
  • the shielding layer 305 is formed at a position corresponding to the gate 302, and its specific formation method can refer to the above-mentioned embodiment, which will not be repeated here.
  • Step S308 forming a second interlayer insulating layer.
  • Step S309 forming a data line.
  • the formation position of the data line 304 can refer to FIG. 5A, FIG. 5B and FIG. 8E, and the specific formation method of the data line 304 can refer to the above-mentioned embodiment, which will not be repeated here.
  • Step S310 forming a light emitting device and the like.
  • the manufacturing method of the display substrate provided by the embodiment of the present disclosure forms a gate lead between the gate and the base substrate, so that a shielding layer with a certain integrity can be formed between the gate and the data line, and the shielding layer can avoid A parasitic capacitance is formed between the gate and the data line, thereby avoiding possible adverse effects of the parasitic capacitance and improving the display quality of the display substrate.

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Abstract

一种显示基板及其制备方法、显示面板。该显示基板包括衬底基板(101/201/301)以及在衬底基板(101/201/301)上的像素驱动电路；像素驱动电路包括驱动晶体管和栅极引线(103/203/303)，驱动晶体管包括栅极(102/202/302)，栅极引线(103/203/303)电连接于栅极(102/202/302)，栅极引线(103/203/303)位于栅极(102/202/302)与衬底基板(101/201/301)之间。该显示基板的栅极(102/202/302)和数据线(104/204/304)之间不形成寄生电容，因此具有更优质的显示效果。

Description

显示基板及其制备方法、显示面板 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等优点，成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。OLED显示装置的像素驱动电路通常包括晶体管、电容等电路元件，并通过这些电路元件控制流过发光二极管的电流，进而控制显示装置的显示灰阶。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板和像素驱动电路。像素驱动电路在所述衬底基板上，包括驱动晶体管和栅极引线，所述驱动晶体管包括栅极，所述栅极引线电连接于所述栅极，其中，所述栅极引线位于所述栅极与所述衬底基板之间。
例如，本公开至少一实施例提供的显示基板还包括数据线，所述数据线位于所述栅极的远离所述衬底基板的一侧，所述驱动晶体管配置为在所述栅极接收由所述数据线提供的数据电压信号并基于所述数据电压信号控制流过所述驱动晶体管的驱动电流，所述驱动电流用于驱动发光器件工作。
例如，本公开至少一实施例提供的显示基板还包括屏蔽层，屏蔽层在所述栅极所在的层与所述数据线所在的层之间，其中，所述屏蔽层与所述栅极彼此绝缘且在垂直于所述衬底基板的方向上彼此重叠。
例如，本公开至少一实施例提供的显示基板中，所述屏蔽层为金属层。
例如，本公开至少一实施例提供的显示基板中，所述栅极引线在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板还包括缓冲层，所述缓冲层在所述衬底基板上且包括第一过孔，其中，所述栅极引线位于所述缓冲层的 靠近所述衬底基板的一侧，所述栅极位于所述缓冲层远离所述衬底基板的一侧，所述栅极引线通过所述第一过孔与所述栅极连接。
例如，本公开至少一实施例提供的显示基板中，所述缓冲层还包括第二过孔，所述栅极引线通过所述第二过孔与不同于所述驱动晶体管的电路元件电连接。
例如，本公开至少一实施例提供的显示基板中，所述电路元件包括复位晶体管、补偿晶体管或存储电容。
例如，本公开至少一实施例提供的显示基板还包括第二缓冲层，所述第二缓冲层在所述衬底基板上，其中，所述栅极引线位于所述第二缓冲层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板还包括导电层，所述导电层位于所述栅极引线的远离所述衬底基板的一侧，并且覆盖至少部分所述栅极引线的侧面以及所述栅极引线的远离所述衬底基板的表面。
例如，本公开至少一实施例提供的显示基板还包括遮光层，所述栅极引线与遮光层同层，且所述遮光层与所述像素驱动电路至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述驱动晶体管还包括半导体层，所述栅极引线与所述半导体层同层。
例如，本公开至少一实施例提供的显示基板中，所述半导体层包括未导体化的沟道区、导体化的源极区和导体化的漏极区，所述栅极引线包括导体化的半导体材料。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，在所述衬底基板上形成像素驱动电路，所述像素驱动电路包括驱动晶体管和栅极引线，所述驱动晶体管包括栅极，所述栅极引线电连接于所述栅极，其中，所述栅极引线形成于所述栅极与所述衬底基板之间。
例如，本公开至少一实施例提供的制备方法还包括：在所述栅极的远离所述衬底基板的一侧形成数据线，其中，所述驱动晶体管形成为在所述栅极接收由所述数据线提供的数据电压信号并基于所述数据电压信号控制流过所述驱动晶体管的驱动电流，所述驱动电流用于驱动发光器件工作。
例如，本公开至少一实施例提供的制备方法还包括：在所述栅极所在的层与所述数据线所在的层之间形成屏蔽层，其中，所述屏蔽层与所述栅极彼此绝缘且在垂直于所述衬底基板的方向上彼此重叠。
例如，本公开至少一实施例提供的制备方法中，所述栅极引线与遮光层同层形成，其中，所述遮光层与所述像素驱动电路至少部分重叠。
例如，本公开至少一实施例提供的制备方法中，形成所述驱动晶体管还包括：形成半导体层，其中，所述栅极引线与所述半导体层同层形成。
例如，本公开至少一实施例提供的制备方法中，形成所述栅极引线与所述半导体层包括：形成半导体材料层，所述半导体材料层包括沟道区、源极区、漏极区和栅极引线区；对所述源极区、所述漏极区和所述栅极引线区进行掺杂，以使所述源极区、所述漏极区和所述栅极引线区导体化。
本公开至少一实施例提供一种显示面板，包括上述任一所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的像素驱动电路的电路图；
图1B为一种显示基板发生纵向串扰的示意图；
图1C为栅极电压的偏差与栅极和数据线之间的寄生电容之间的关系曲线；
图2A为一种显示基板的像素驱动电路的平面示意图；
图2B为图2A中的像素驱动电路沿A-A线的截面示意图；
图2C为图2A中的像素驱动电路的部分平面示意图；
图3A为本公开一些实施例提供的一种显示基板的截面示意图；
图3B为本公开一些实施例提供的一种显示基板的另一截面示意图；
图3C示出了本公开一些实施例提供的一种显示基板的平面示意图；
图4A为本公开一些实施例提供的另一种显示基板的截面示意图；
图4B为本公开一些实施例提供的另一种显示基板的另一截面示意图；
图5A为本公开一些实施例提供的再一种显示基板的截面示意图；
图5B为本公开一些实施例提供的再一种显示基板的另一截面示意图；
图5C示出了本公开一些实施例提供的再一种显示基板的平面示意图；
图6A为本公开一些实施例提供的一种显示基板的制备流程图；
图6B-图6F为本公开一些实施例提供的一种显示基板在制备过程中的平面示意图；
图7为本公开一些实施例提供的另一种显示基板的制备流程图；
图8A为本公开一些实施例提供的再一种显示基板的制备流程图；
图8B-图8E为本公开一些实施例提供的再一种显示基板在制备过程中的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常来说，显示基板包括多个像素单元，每个像素单元包括发光器件以及用于驱动发光器件的像素驱动电路，像素驱动电路例如包括驱动晶体管、开关晶体管以及电容等结构。显示基板中基础的像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容C来实现驱动发光器件的基本功能。另外，各个像素电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电压进行补偿。同时在驱动晶体管处于截止状态时，由于漏电流的存在，也可能会 导致显示不良。因此，业界还在上述2T1C的基本像素电路的基础上提供了其他具有补偿功能的像素电路，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C、4T2C或7T1C电路等。
例如，一种显示基板具有如图1A所示的7T1C像素驱动电路，该驱动电路通过七个晶体管(T)和一个存储电容(C1)来控制发光器件(D1)的发光状态。该像素驱动电路的工作过程主要包括四个阶段，分别为初始化阶段、数据写入和补偿阶段、复位阶段以及发光阶段。下面对该像素驱动电路的工作过程进行简要说明。
首先，在初始化阶段，输入第一复位信号RST1，开启第四晶体管T4，将复位电压VINT施加至驱动晶体管T1的控制端；输入第一发光控制信号EM1，开启第五晶体管T5，将第一电压VDD施加至驱动晶体管T1的第一端(第二节点N2)。此时，第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7被截止。
在初始化阶段，由于第四晶体管T4导通，可以将复位电压VINT施加至第一晶体管T1的栅极，该复位电压VINT可以使第一晶体管T1处于导通状态。
在数据写入和补偿阶段，输入扫描信号GATE(标记为G)和数据信号DATA(标记为D)，开启第二晶体管T2、驱动晶体管T1和第三晶体管T3，第二晶体管T2将数据信号DATA写入至驱动晶体管T1的源极(第二节点N2)，并且经驱动晶体管T1和第三晶体管T3对于驱动晶体管T1的栅极(第一节点N1)进行充电，直至驱动晶体管T1的栅极的电压等于(Vdata-Vth)，其中Vdata为数据信号DATA的电压值，Vth为驱动晶体管T1的阈值电压，该电压由存储电容C1存储，由此数据电压Vdata被写入至驱动晶体管T1的栅极并通过存储电容C1存储，第三晶体管T3对驱动晶体管T1进行阈值补偿。此时，第二晶体管T2和第三晶体管T3被扫描信号GATE导通，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7被截止。
因此，在该数据写入和补偿阶段，数据信号DATA经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对第一节点N1进行充电(即对存储电容C1充电)，以在后续的发光阶段提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在复位阶段，输入第二发光控制信号EM2和第二复位信号RST2，开启第六晶体管T6和第七晶体管T7，对驱动晶体管T1、第三晶体管T3和发光器件进行复位。
在该复位阶段，第六晶体管T6被第二发光控制信号EM2导通，第七晶体管T7被第二复位信号RST2导通；同时，第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5被截止。此时，第一晶体管T1的漏极经过第六晶体管T6和第七晶体管T7放电，从而将第三节点N3和第四节点N4(发光器件D1)的电位同时复位，由此发光器件D1在发光阶段之前不发光。
在发光阶段，输入第一发光控制信号EM1和第二发光控制信号EM2，开启第五晶体管T5、第六晶体管T6和第一晶体管T1，从而驱动电流被施加至发光器件D1以使其发光。在发光阶段，发光器件D1的阳极和阴极分别被施加电压，从而在流经第一晶体管T1的驱动电流的作用下发光。例如，发光器件D1为有机发光二极管(OLED)、量子点发光二极管(QLED)等。
例如，该显示基板还包括扫描驱动电路和数据驱动电路。数据驱动电路与多条数据信号线连接，以提供数据信号DATA；例如，数据驱动电路还可以与多条电压线和多条复位电压线连接以分别提供电压信号(例如VDD)和复位电压VINT。扫描驱动电路与多条扫描信号线连接，以提供扫描信号GATE；例如，扫描驱动电路还可以与多条发光控制线连接以提供发光控制信号EM，以及与多条复位控制线连接以提供复位信号RST。
图2A和图2B分别示出了上述像素驱动电路的平面图和部分截面图，图2B中的截面图例如是沿图2A中的A-A剖切得到的。
例如，图2B示出的像素驱动电路部分包括驱动晶体管的栅极12、通过栅极绝缘层13中的过孔引出的栅极引线11、数据线14以及金属层15等。金属层15例如是像素驱动电路中电容C1或者走线的一部分，或者是与电容C1、走线等同层形成的金属层结构，可作为屏蔽层。栅极引线11例如用于将栅极12与其他电路结构电连接，例如在图1A示出的像素驱动电路中，用于将栅极12连接至第一节点N1。在栅极引线11引出时，金属层15中需要形成开口以便栅极引线11引出，例如在如图1A所示的截面图中，金属层15对应于栅极引线11的位置形成开口。
例如，图2C示出了金属层15所在的层及其下方的功能层的平面示意图，如图2C所示，金属层15中具有开口15A，以便于栅极引线11引出。
本申请发明人在研究中发现，在上述像素驱动电路中，在金属层15的开口位置，驱动晶体管的栅极12与数据线14容易形成寄生电容，因此在数据线14中的数据信号跳变时，该寄生电容容易导致施加给驱动晶体管的栅极12的驱动信号产生误差，从而影响发光器件的发光效果。
例如，图1B示出了一种显示基板的显示画面在数据信号DATA跳变时的示意图。如图1B所示，显示信号从上向下扫描，显示面板的两侧画面显示为L127灰阶，显示面板的中部开始显示为L0灰阶，之后数据信号DATA从对应于在L0灰阶的信号跳变为对应于L127灰阶的信号，但是由于驱动晶体管的栅极12与数据线14之间形成了寄生电容，驱动晶体管的栅极12的电压与初始值产生偏差，使得数据信号DATA跳变为对应于L127灰阶的信号之后，显示面板的中部的显示画面也不能准确地显示为L127灰阶，而是显示为不同于L127灰阶的LX灰阶，由此产生纵向显示串扰。
具体来说，在上述像素驱动电路中，驱动晶体管T1的栅极电压由存储电容C1保持，在数据信号DATA跳变时，由于驱动晶体管T1的栅极12与数据线14之间寄生电容的存在，驱动晶体管T3的栅极电压也会发生变化，从而与初始值产生偏差，使得流经第一晶体管T1的驱动电流具有一定偏差，从而影响发光器件D1的发光效果，导致显示误差。
本申请发明人在研究中发现，在数据信号DATA跳变之后，驱动晶体管T3的栅极电压与初始值产生的偏差大小与栅极和数据线之间的寄生电容相关，图1C示出了栅极电压的偏差与栅极和数据线之间的寄生电容之间的关系曲线，可见，当栅极和数据线之间的寄生电容较小或者不存在寄生电容时，驱动晶体管T3的栅极电压与初始值产生的偏差较小或者不具有偏差。
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板和像素驱动电路。像素驱动电路在衬底基板上，包括驱动晶体管和栅极引线，驱动晶体管包括栅极，栅极引线电连接于栅极，栅极引线位于栅极与衬底基板之间。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，在衬底基板上形成像素驱动电路，像素驱动电路包括驱动晶体管和栅极引线，驱动晶体管包括栅极，栅极引线电连接于栅极，栅极引线形成于栅极与衬底基板之间。
下面通过几个具体的实施例对本公开一些实施例提供的显示基板及其 制备方法进行说明。
本公开一些实施例提供一种显示基板，图3A和3B示出了该显示基板的不同截面的示意图。图3A主要示出了该显示基板的驱动晶体管的栅极、栅极引线以及数据线等结构的相对位置关系，图3B主要示出了该显示基板的驱动晶体管的整体结构以及栅极引线与其他电路元件的连接方式。图3C示出了该显示基板的平面示意图，图3A例如是沿图3C中的B-B线剖切得到的。
在图3A和3B示出的显示基板中，显示基板包括衬底基板101和像素驱动电路。本公开的实施例对于像素驱动电路的不作限制，例如可以为上述2T1C型像素驱动电路，可以为4T2C、7T1C型等。像素驱动电路在衬底基板101上，包括驱动晶体管和栅极引线103，驱动晶体管包括栅极102，栅极引线103电连接于栅极102，栅极引线103位于栅极102与衬底基板101之间。例如，栅极引线103用于将栅极102与其他电路结构电连接。
例如，显示基板还包括衬底基板101上的数据线104等结构，数据线104位于栅极102的远离衬底基板101的一侧。驱动晶体管配置为在栅极102接收并(通过存储电容)存储由数据线104提供的数据电压信号，并基于数据电压信号控制流过驱动晶体管的驱动电流，该驱动电流用于驱动发光器件工作。
由此，在上述显示基板中，在垂直于衬底基板101的方向上，栅极引线103和数据线104位于栅极102的两侧，栅极引线103通过过孔电连接于栅极102。
例如，在一些实施例中，如图3A和3B所示，显示基板还包括屏蔽层105，屏蔽层105设置在栅极102所在的层与数据线104所在的层之间，并且屏蔽层105与栅极102彼此绝缘，且在垂直于衬底基板101的方向上彼此重叠。由此，屏蔽层105可以避免栅极102与数据线104之间产生寄生电容。
在上述结构中，栅极引线103的引出不会破坏屏蔽层105的完整性，例如相比于如图1A所示的显示基板来说，屏蔽层105中无需形成引出栅极引线103的开口，从而屏蔽层105具有一定的完整性，可起到良好的屏蔽效果。
例如，在一些实施例中，屏蔽层105为导电层，例如为金属层。例如，屏蔽层105为像素驱动电路中已有的结构，例如为像素驱动电路中电容的一个电极或者为像素驱动电路的一个走线层，又或者，屏蔽层105为与像素驱 动电路的电容的一个电极同层或者与像素驱动电路的一个走线层同层的金属层。由此，像素驱动电路中已有的金属层结构即可作为屏蔽层，达到屏蔽效果；同时，该设置还可以简化显示基板的结构，从而简化其制备工艺。
例如，图3C示出了该显示基板的平面示意图。如图3C所示，栅极引线103在衬底基板上的正投影与屏蔽层105在衬底基板上的正投影至少部分重叠。由于栅极引线103从栅极102与衬底基板101之间引出，因此屏蔽层105中不具有开口。
例如，当屏蔽层105为像素驱动电路中电容的一个电极时，屏蔽层105中不具有开口可以增大电容电极的面积(即屏蔽层105在衬底基板上的正投影的面积增大)，从而可以增大电容的电容量或者在保持电容量的同时减小电极所占的空间。例如，栅极102还可以作为电容的另一电极，由此栅极102、屏蔽层105以及二者之间的绝缘层共同组成电容，该电容可作为像素驱动电路中的存储电容。
例如，如图3B所示，驱动晶体管还包括栅极绝缘层107、半导体层110等结构。例如，栅极绝缘层107位于栅极102与半导体层110之间，以将二者绝缘。半导体层110包括未导体化的沟道区110A、导体化的源极区110B和导体化的漏极区110C。沟道区110A对应于栅极102，源极区110B和漏极区110C为半导体层110的掺杂区，从而源极区110B和漏极区110C被导体化，并具有良好的导电性，可分别作为驱动晶体管的源极和漏极。例如，驱动晶体管的源极通过走线104A与其他元件电连接，例如用于传输数据信号。
例如，如图3A和3B所示，显示基板还包括层间绝缘层108，层间绝缘层108覆盖驱动晶体管。例如，栅极引线103、栅极绝缘层107、栅极102、层间绝缘层108和数据线104在衬底基板101上依次叠层设置，由此将栅极引线103和数据线104分别设置于栅极102的两侧。
例如，在一些实施例中，如图3A和3B所示，显示基板还包括设置在衬底基板101的缓冲层106，栅极引线103通过缓冲层106中的过孔与栅极102电连接。例如，缓冲层106包括第一过孔1061，栅极引线103位于缓冲层106的靠近衬底基板101的一侧，即图中示出为缓冲层106的下侧，栅极102位于缓冲层106的远离衬底基板101的一侧，即图中示出为缓冲层106的上侧，栅极引线103通过第一过孔1061和栅极绝缘层107中的与第一过 孔1061连通的过孔与栅极102电连接。
例如，如图3B所示，缓冲层106还包括第二过孔1062，栅极引线103通过第二过孔1062与不同于驱动晶体管的电路元件电连接。由此，栅极引线103可将驱动晶体管的栅极102与其他电路结构电连接。
例如，在其他示例中，通过第二过孔1062进行电连接的走线还可以为与栅极引线103同层的走线或元件103A。此时，走线或元件103A可以为显示基板上的任意信号走线或功能元件(例如电极或者遮光层等)，本公开的实施例对此不做限定。
例如，不同于驱动晶体管的电路元件包括复位晶体管、补偿晶体管或存储电容等。例如在图1A示出的像素驱动电路中，不同于驱动晶体管T1的电路元件为第三晶体管T3，第四晶体管T4或存储电容C1等，它们通过栅极引线(包括节点N1)与驱动晶体管T1的栅极电连接。此时，标号111示出为上述电路元件的一部分或者连接上述电路元件的走线等导电结构。
例如，在一些实施例中，导电结构111与半导体层110同层设置，因此在制备工艺中二者可采用同一半导体膜层形成。例如，在制备工艺中，采用构图工艺与掺杂工艺处理该同一半导体膜层，从而形成分别对应于导电结构111的部分和半导体层110的部分，对应于半导体层110的部分例如包括沟道区、源极区和漏极区。例如，在对应于导电结构111、源极区和漏极区的位置进行重掺杂，从而形成具有良好导电性的导电层211、源极和漏极。例如，用于形成导电结构111与半导体层110的半导体膜层为多晶硅膜层或氧化物半导体膜层，该多晶硅膜层可以包括低温多晶硅或高温多晶硅，氧化物半导体膜层可以包括IGZO(氧化铟镓锌)等，该半导体膜层的重掺杂的部分具有良好的导电性，例如，对于多晶硅膜层，例如掺杂硼离子(B 3+)以实现p掺杂，或者掺杂磷离子(P 3-)以实现n掺杂，掺杂方法可以采用离子注入、热扩散等多种方式，本公开的实施例对此不作限制。
例如，在一些实施例中，显示基板还包括遮光层，如图3B所示，该遮光层例如位于衬底基板101与缓冲层106之间，并且与像素驱动电路至少部分重叠。例如，遮光层设置在标号112所指示的虚线框的位置，该位置对应于半导体层110的沟道区110A，从而遮光层可以避免环境光照射到沟道区110A，而从而避免环境光影响驱动晶体管的正常工作。例如，该遮光层与栅极引线103同层设置，均采用金属层制备，从而在制备过程中该遮光层与栅 极引线103可以采用同一薄膜通过同一构图工艺形成，由此可以简化显示基板的制备工艺。
例如，如图3B所示，显示基板还包括覆盖屏蔽层105的第二层间绝缘层109，走线104A通过栅极绝缘层107、层间绝缘层108以及第二层间绝缘层109中的过孔电连接于驱动晶体管的源极，例如用于传输数据电压信号，从而驱动晶体管可接收由走线104A提供的数据电压信号并基于数据电压信号控制流过驱动晶体管的驱动电流。
例如，在上述实施例中，衬底基板101采用玻璃基板、石英基板、塑料基板等任何合适的基板。栅极102、栅极引线103、数据线104和屏蔽层105中的一种或多种采用铜、银、铝、钼等金属材料或者合金材料形成。缓冲层106采用聚酰亚胺(PI)、丙烯酸酯和环氧树脂等有机绝缘材料或无机绝缘材料(例如氮化硅等)形成。栅极绝缘层107、层间绝缘层108和第二层间绝缘层109中的一种或多种采用聚酰亚胺、丙烯酸酯和环氧树脂等有机绝缘材料或者氧化硅、氮化硅和氮氧化硅等无机绝缘材料形成。本公开的实施例对各功能层的材料不作具体限定。
在本公开的上述实施例中，衬底基板上的像素驱动电路的电路布图中，可以将栅极引线103和数据线104设置于栅极102的两侧，例如将栅极引线103设置在栅极102和衬底基板101之间，从而栅极102与数据线104之间可形成具有一定完整性的屏蔽层105，该屏蔽层105可以避免栅极102与数据线104之间形成寄生电容，从而避免该寄生电容可能产生的不良影响，提高显示基板的显示质量。
在本公开的其他实施例中，显示基板的栅极引线还可以采用其他方式引出，这些方式均可以达到上述技术效果。
例如，图4A和图4B示出了本公开另一些实施例提供的显示基板的不同截面的示意图。类似地，图4A主要示出了该显示基板的驱动晶体管的栅极、栅极引线以及数据线等结构的相对位置关系，图4B主要示出了该显示基板的驱动晶体管的整体结构以及栅极引线与其他电路元件的连接方式。该显示基板的平面示意图可参考图3C。
如图4A和图4B所示，该显示基板包括衬底基板201和像素驱动电路。像素驱动电路在衬底基板201上，包括驱动晶体管和栅极引线203，驱动晶体管包括栅极202，栅极引线203电连接于栅极202，栅极引线103位于栅 极202与衬底基板201之间。
例如，显示基板还包括衬底基板201上的数据线204等结构，数据线204位于栅极202的远离衬底基板201的一侧。驱动晶体管配置为在栅极202接收并(通过存储电容)存储由数据线204提供的数据电压信号，并基于数据电压信号控制流过驱动晶体管的驱动电流，该驱动电流用于驱动发光器件工作。
由此，在上述显示基板中，在垂直于衬底基板201的方向上，栅极引线203和数据线204位于栅极202的两侧，栅极引线203通过过孔电连接于栅极202。
例如，在一些实施例中，如图4A和4B所示，显示基板还包括屏蔽层205、缓冲层206、半导体层210、栅极绝缘层207、层间绝缘层208和第二层间绝缘层209等结构。半导体层210包括未导体化的沟道区210A和导体化的源极区210B和导体化的漏极区210C。沟道区210A对应于栅极202，源极区210B和漏极区210C为半导体层210的掺杂区，从而源极区210B和漏极区210C被导体化，并具有良好的导电性，可分别作为驱动晶体管的源极和漏极。例如，驱动晶体管的源极通过走线204A与其他元件电连接，例如用于传输数据信号。
与上述实施例不同的是，在图4A和4B示出的实施例中，缓冲层206位于衬底基板201上，栅极引线203位于缓冲层206的远离衬底基板201的一侧，即在图中位于缓冲层206的上侧。此时，栅极引线203通过栅极绝缘层207中的过孔与栅极202电连接。
此时，如图4A和4B所示，显示基板还包括导电层211，导电层211位于栅极引线203的远离衬底基板201的一侧，并且覆盖至少部分栅极引线203的侧面以及栅极引线203的远离衬底基板201的表面，从而在制备工艺中，导电层211可直接形成于栅极引线203上。例如，导电层211为不同于驱动晶体管的电路元件的一部分或者连接不同于驱动晶体管的电路元件的走线等导电结构。由此，栅极引线203将驱动晶体管的栅极102与其他电路结构电连接。例如，不同于驱动晶体管的电路元件包括复位晶体管、补偿晶体管或存储电容等，本公开的实施例对此不做限定。
例如，在其他示例中，导电层211覆盖的还可以是与栅极引线203同层的走线或元件203A。此时，走线或元件203A可以为显示基板上的任意信号 走线或功能元件(例如电极或者遮光层等)，本公开的实施例对此不做限定。
例如，导电层211和半导体层210同层设置，因此在制备工艺中二者可采用同一半导体膜层形成。具体设置方式可参见上述实施例，在此不再赘述。
例如，在图4A和图4B示出的实施例中，显示基板还可以包括遮光层，如图4B所示，该遮光层例如位于半导体层210与缓冲层206之间，并且与像素驱动电路至少部分重叠。例如，遮光层设置在标号212指示的虚线框的位置，该位置对应于半导体层210的沟道区210A的位置，例如遮光层与半导体层210之间还形成有绝缘层(图中未示出)。例如，该遮光层与栅极引线203同层设置，从而在制备过程中该遮光层与栅极引线203可以采用同一薄膜通过同一构图工艺形成，由此可以简化显示基板的制备工艺。
图4A和图4B示出的示例相对于图3A和图3B示出的示例来说，缓冲层206中不具有过孔结构，因此在制备过程中可减少一次过孔形成工艺，可进一步简化显示基板的制备工艺。
同样地，在图4A和图4B示出的显示基板中，栅极202与数据线204之间可以设置具有一定完整性的屏蔽层205，该屏蔽层205可以避免栅极202与数据线204之间形成寄生电容，从而避免该寄生电容可能产生的不良影响，提高显示基板的显示质量。另外，当屏蔽层205为像素驱动电路中电容的一个电极时，屏蔽层205中不具有开口可以增大电容电极的面积，从而可以增大电容的电容量或者在保持电容量的同时减小电极所占的空间。
例如，图5A和图5B示出了本公开再一些实施例提供的显示基板的不同截面的示意图。类似地，图5A主要示出了该显示基板的驱动晶体管的栅极、栅极引线以及数据线等结构的相对位置关系，图5B主要示出了该显示基板的驱动晶体管的整体结构以及栅极引线与其他电路元件的连接方式。图5C示出了该显示基板的平面示意图，图5A例如是沿图5C中的C-C线剖切得到的。
如图5A和图5B所示，该显示基板包括衬底基板301和像素驱动电路。像素驱动电路在衬底基板301上，包括驱动晶体管和栅极引线303，驱动晶体管包括栅极302，栅极引线303电连接于栅极302，栅极引线303位于栅极302与衬底基板301之间。
例如，显示基板还包括衬底基板301上的数据线304等结构，数据线304位于栅极302的远离衬底基板301的一侧。驱动晶体管配置为在栅极302接 收并(通过存储电容)存储由数据线304提供的数据电压信号，并基于数据电压信号控制流过驱动晶体管的驱动电流，该驱动电流用于驱动发光器件工作。
由此，在上述显示基板中，在垂直于衬底基板301的方向上，栅极引线303和数据线304位于栅极302的两侧，栅极引线303通过过孔电连接于栅极302。
例如，如图5A和5B所示，显示基板还包括屏蔽层305、缓冲层306、栅极绝缘层307、层间绝缘层308和第二层间绝缘层309等结构，具体设置可参见上述实施例，在此不再赘述。
与上述实施例不同的是，在图5A和5B示出的实施例中，栅极引线303与半导体层310同层设置，因此在制备工艺中可以通过对同一半导体层进行构图与掺杂工艺形成。
例如，如图5B所示，驱动晶体管包括半导体层310，半导体310包括未导体化的沟道区310A、导体化的源极区310B和导体化的漏极区310C。沟道区310A对应于栅极302，源极区310B和漏极区310C为掺杂区，从而源极区310B和漏极区310C被导体化，并具有良好的导电性，可分别作为驱动晶体管的源极和漏极。例如，栅极引线303包括导体化的半导体材料。在制备工艺中，可通过对同一半导体层进行掺杂工艺以形成导体化的源极区310B、漏极区310C和栅极引线303。例如，在一些示例中，沟道区310A也为掺杂区，但是其掺杂浓度远小于源极区310B和漏极区310C的掺杂浓度。例如，驱动晶体管的源极通过走线304A与其他元件电连接，例如用于传输数据信号。
在图5A和图5B的示例中，对同一半导体层进行构图与掺杂工艺形成栅极引线303与半导体层310的同时，还可以形成连接栅极引线303的其他导电结构311，该导电结构311也可以通过对半导体层进行掺杂来获得。由此，栅极引线303、半导体层310以及用于连接栅极引线303与其他电路元件的导电结构311可同层设置，可通过对同一半导体层进行构图与掺杂工艺形成。由此可进一步简化制备工艺。
在上述示例中，栅极引线303、半导体层310以及导电结构311可通过对同一半导体层进行掺杂工艺而形成，因此三者位于同一层中。如图5C所示，栅极引线303和导电结构311可通过导体化的半导体材料直接电连接， 相比于图3C示出的显示基板来说，无需在栅极引线303和导电结构311的连接处再形成用于连接导电结构311与栅极引线303的过孔等结构。
同样地，在上述显示基板中，栅极302与数据线304之间可以设置具有一定完整性的屏蔽层305，该屏蔽层305可以避免栅极302与数据线304之间形成寄生电容，从而避免该寄生电容可能产生的不良影响，提高显示基板的显示质量。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，在衬底基板上形成像素驱动电路，像素驱动电路包括驱动晶体管和栅极引线，驱动晶体管包括栅极，栅极引线电连接于栅极，栅极引线形成于栅极与衬底基板之间。
例如，显示基板的制备方法还包括形成数据线，数据线形成于栅极的远离衬底基板的一侧，驱动晶体管配置为在栅极接收由数据线提供的数据电压信号并基于数据电压信号控制流过驱动晶体管的驱动电流，驱动电流用于驱动发光器件工作。
例如，以图3A和图3B示出的显示基板为例，其制备方法的流程图如图6A所示，该制备方法至少包括步骤S101-S111。
步骤S101：提供衬底基板。
参照图3A和图3B。例如，提供的衬底基板101包括玻璃基板、石英基板、塑料基板等各种类型的基板，衬底基板101上例如形成有阻挡层(图中未示出)，该阻挡层覆盖衬底基板101，可防止衬底基板101中可能存在的杂质以及水、氧等杂质进入其上将要形成的其他膜层中，从而避免驱动晶体管等的电气性能劣化。该阻挡层例如采用氧化硅、氮化硅或者氮氧化硅等无机材料，例如形成为氧化硅和氮化硅交替堆叠的多层结构。
步骤S102：形成栅极引线。
图6B-图6F示出了显示基板在制备过程中的平面示意图。参照图3A、图3B以及图6B，在衬底基板101上首先形成栅极引线103。例如，栅极引线103采用铜、银、铝、钼等金属材料或者合金材料形成。例如，在衬底基板101上采用蒸镀、溅射等方式形成栅极引线材料层，然后对该栅极引线材料层进行构图工艺以形成栅极引线103。例如，一次构图工艺包括光刻胶的涂覆、曝光、显影，以及材料层的刻蚀等工序，本公开的实施例对此不做限定。
例如，在一些示例中，制备方法还包括形成遮光层，例如，栅极引线103与遮光层(标号112指示的位置)同层形成，该遮光层与像素驱动电路至少部分重叠，例如形成在对应于之后将要形成的半导体层110的沟道110A的位置，从而遮光层可以避免环境光等照射到沟道区110A。例如，该遮光层与栅极引线103采用同一薄膜通过同一构图工艺形成，由此简化显示基板的制备工艺。
步骤S103：形成缓冲层。
例如，栅极引线103形成后，在栅极引线103上形成缓冲层106，缓冲层106例如采用有机绝缘材料或者无机绝缘材料形成，例如聚酰亚胺(PI)、丙烯酸酯和环氧树脂等有机绝缘材料，或者氧化硅、氮化硅或者氮氧化硅等无机材料。例如，在栅极引线103上采用涂覆等方式形成缓冲材料层，然后对缓冲材料层进行构图工艺以形成连接之后将要形成的导电结构111的过孔1062等。
步骤S104：形成半导体层。
例如，缓冲层106形成后，参照图3A、图3B以及图6B，在缓冲层106上形成驱动晶体管的半导体层110，导体层110例如采用多晶硅半导体形成。例如，在缓冲层106上采用沉积等方式形成非晶硅材料层，将该非晶硅材料层通过例如激光退火等方式结晶化得到多晶硅材料层，然后对多晶硅材料层进行构图工艺，以形成对应于驱动晶体管的区域，该区域例如包括沟道区110A、源极区110B和漏极区110C，同时，该构图工艺还形成对应于导电结构111的导电区。之后，通过对源极区110B、漏极区110C以及导电区进行掺杂处理，例如重掺杂硼或磷等杂质，以使多晶硅材料导体化，从而具有良好的导电性，形成驱动晶体管的源极和漏极以及导电结构111。例如，在一些示例中，还可以根据薄膜晶体管的特征对沟道区110A轻掺杂硼或磷等杂质，以形成薄膜晶体管的沟道。此时，半导体层110与导电结构111同层形成，可简化显示基板的制备工艺。
例如，该显示基板中形成如图1A所示的7T1C电路结构，即包括七个薄膜晶体管和一个存储电容。此时，在制备工艺中，该七个薄膜晶体管可以在相同的工艺中形成，因此在形成上述驱动晶体管(T1)的半导体层110时，还形成有其他晶体管T2～T7的半导体层，其他晶体管T2～T7的半导体层的位置示出在图6B中。
步骤S105：形成栅极绝缘层。
例如，半导体层110和导电结构111形成后，在半导体层110和导电结构111上形成栅极绝缘层107，栅极绝缘层107例如采用氧化硅、氮化硅、氮氧化硅等无机绝缘材料或者聚酰亚胺(PI)、丙烯酸酯、环氧树脂等有机绝缘材料形成。例如，在半导体层110和导电结构111上采用沉积或者涂覆等方式形成栅极绝缘材料层，然后对栅极绝缘材料层以及缓冲层106进行构图工艺以形成暴露栅极引线103的过孔1061，以便于连接之后将要形成的栅极102。
步骤S106：形成栅极。
例如，参照图3A、图3B以及图6C，栅极绝缘层107形成后，在栅极绝缘层107上形成栅极102，栅极102例如采用铜、银、铝、钼等金属材料或者合金材料形成。例如，在栅极绝缘层107上采用蒸镀、溅射等方式形成栅极材料层，然后对该栅极材料层进行构图工艺以形成栅极102。栅极102通过过孔1061与栅极引线103电连接。
例如，栅极102可以与传输发光控制信号EM的走线、传输复位信号RST的走线和传输扫描信号GATE的走线等同层形成。
例如，传输复位信号RST的走线覆盖第四晶体管T4的半导体层的沟道区，该覆盖沟道区的走线部分作为第四晶体管T4的栅极，第四晶体管T4可作为复位晶体管。传输扫描信号GATE的走线覆盖第二晶体管T2和第三晶体管T3的半导体层的沟道区，覆盖第二晶体管T2的沟道区的部分走线作为第二晶体管T2的栅极，第二晶体管T2可作为开关晶体管；覆盖第三晶体管T3的沟道区的部分走线作为第三晶体管T3的栅极，第二晶体管T3可作为补偿晶体管。传输发光控制信号EM的走线覆盖第五晶体管T5和第六晶体管T6的半导体层的沟道区，覆盖第五晶体管T5的沟道区的部分走线作为第五晶体管T5的栅极，第五晶体管T5可作为驱动控制晶体管；覆盖第六晶体管T6的沟道区的部分走线作为第六晶体管T6的栅极，第六晶体管T6可作为发光控制晶体管。传输另一扫描信号GATE的走线覆盖第七晶体管T7的半导体层的沟道区，覆盖第七晶体管T7的沟道区的部分走线作为第七晶体管T7的栅极，第七晶体管T7可作为旁路晶体管。
另外，栅极102还可以作为存储电容C1的一个电极，与之后形成的另一电极以及二者之间的绝缘层共同组成存储电容C1。
步骤S107：形成层间绝缘层。
例如，栅极102形成后，在栅极102上形成层间绝缘层108，层间绝缘层108例如采用氧化硅、氮化硅、氮氧化硅等无机绝缘材料或者聚酰亚胺(PI)、丙烯酸酯、环氧树脂等有机绝缘材料形成。例如，在栅极102上采用沉积或者涂覆等方式形成层间绝缘材料层，并对层间绝缘材料层进行构图工艺以形成所需的图案。
步骤S108：形成屏蔽层。
例如，参照图3A、图3B以及图6D，层间绝缘层108形成后，在层间绝缘层108上形成屏蔽层105，屏蔽层105例如采用铜、银、铝、钼等金属材料或者合金材料形成。例如，在层间绝缘层108上采用蒸镀或者溅射等方式形成屏蔽材料层，然后对该屏蔽材料层进行构图工艺以在对应于栅极102的位置形成屏蔽层105。屏蔽层105与栅极102彼此绝缘且在垂直于衬底基板201的方向上彼此重叠。如图6D所示，屏蔽层105中没有形成开口。
例如，屏蔽层105与传输复位电压VINT的走线以及第二屏蔽层1051等同层形成。第二屏蔽层1051可以防止相邻的两个导电层之间产生寄生电容，例如可以防止半导体层与之后将要形成的数据线之间产生寄生电容等。
例如，屏蔽层105可以作为存储电容C1的另一电极，与栅极102以及二者之间的层间绝缘层一起共同构成存储电容C1。由于屏蔽层105中不具有开口，因此屏蔽层105的面积更大，从而可以增大存储电容C1的电容量或者在保持电容量的同时减小屏蔽层105所占的空间。
步骤S109：形成第二层间绝缘层。
例如，参照图3A、图3B以及图6E，屏蔽层105形成后，在屏蔽层105上形成第二层间绝缘层109，第二层间绝缘层109例如采用氧化硅、氮化硅、氮氧化硅等无机绝缘材料或者聚酰亚胺(PI)、丙烯酸酯、环氧树脂等有机绝缘材料形成。例如，在屏蔽层105上采用沉积或者涂覆等方式形成第二层间绝缘材料层，并对第二层间绝缘材料层进行构图工艺以形成所需的图案，该构图工艺还包括在第二层间绝缘材料层以及栅极绝缘层107、层间绝缘层108中形成暴露驱动晶体管的源极110B的过孔1081，以便于之后将源极110B与之后将要形成的走线104A，例如数据线104等连接。
例如，在形成过孔1081的同时，还形成有其他过孔，例如暴露其他薄膜晶体管的源漏极的过孔等，以便于电连接。
步骤S110：形成数据线。
例如，参照图3A、图3B以及图6F，第二层间绝缘层109形成后，在第二层间绝缘层109上形成数据线104，数据线104例如采用铜、银、铝、钼等金属材料或者合金材料形成。例如，在第二层间绝缘层109上采用蒸镀或者溅射等方式形成数据线材料层，然后对该数据线材料层进行构图工艺以形成数据线104。
例如，数据线104与传输第一电压VDD的电源线以及连接电极1041等同层形成。连接电极1041用于电连接两个导电结构，例如电连接第七薄膜晶体管T7的源漏极与传输复位电压VINT的走线等。
步骤S111：形成发光器件等。
例如，在上述驱动电路形成后，还可进一步形成平坦层、像素界定层、发光器件(包括阴极、阳极以及阴极和阳极之间的发光层等)、隔垫物、封装层等结构，这些结构的材料、图形以及它们的形成方式可参照常规技术，本公开的实施例不再赘述。本公开实施例的发光器件可以为OLED或QLED等。
通过上述方法可形成如图3A和图3B示出的显示基板，该方法通过将栅极引线103形成于栅极102和衬底基板101之间，因此栅极引线103和数据线104形成于栅极102的两侧，使得栅极102与数据线104之间可形成具有一定完整性的屏蔽层105，该屏蔽层105可以避免栅极102与数据线104之间形成寄生电容，从而避免该寄生电容可能产生的不良影响，提高显示基板的显示质量。
例如，本公开的一些实施例还提供了形成如图4A和图4B示出的显示基板的制备方法，该制备方法的流程图如图7所示，该制备方法至少包括步骤S201-S211。该方法与上述形成图3A和图3B的显示基板的方法相比，区别主要在于步骤S202-步骤S204中缓冲层、栅极引线以及半导体层等的形成顺序以及形成结构。下面将重点描述该区别之处，其他部分的形成方法可参照上述实施例。
步骤S201：提供衬底基板。
步骤S202：形成缓冲层。
参照图4A和图4B，在衬底基板201上形成缓冲层206。缓冲层206的材料以及形成方式可参照上述实施例，在此不再赘述。
步骤S203：形成栅极引线。
例如，缓冲层206形成后，在缓冲层206上形成栅极引线203。栅极引线203的材料以及形成方式可参照上述实施例，在此不再赘述。
例如，在一些示例中，栅极引线203与遮光层(标号212指示的位置)同层形成，其形成方式可参照上述实施例，在此不再赘述。
步骤S204：形成半导体层。
例如，在栅极引线203形成后，在栅极引线203上形成半导体层210，并同时形成导电层211，即导电层211和半导体层210采用同一半导体膜层形成。
例如，在栅极引线203上形成多晶硅材料层，然后对多晶硅材料层进行构图工艺，以形成对应于驱动晶体管的沟道、源极和漏极的区域，该区域例如包括沟道区210A、源极区210B和漏极区210C，同时，该构图工艺还形成对应于导电层211的导电区。之后，通过对源极区210B、漏极区210C以及导电区进行掺杂处理，例如重掺杂磷、硼等杂质，以使这些区域具有良好的导电性，从而形成驱动晶体管的源极和漏极以及导电层211。例如，在一些示例中，还可以根据薄膜晶体管的特征对沟道区210A轻掺杂硼或磷等杂质，以形成薄膜晶体管的沟道。由此，导电层211直接形成于栅极引线203上，并覆盖至少部分栅极引线203的侧面以及栅极引线203的远离衬底基板201的表面。
步骤S205：形成栅极绝缘层。
例如，在半导体层210和导电层211形成后，在半导体层210和导电层211上形成栅极绝缘层207，并通过构图工艺在栅极绝缘层207中形成暴露栅极引线203的过孔，以便于与之后将要形成的栅极202连接。
步骤S206：形成栅极。
步骤S207：形成层间绝缘层。
步骤S208：形成屏蔽层。
步骤S209：形成第二层间绝缘层。
步骤S210：形成数据线。
步骤S211：形成发光器件等。
上述未详细说明的步骤以及平面构图等可参照上述实施例，在此不再赘述。
例如，本公开的一些实施例还提供了形成如图5A和图5B示出的显示基板的制备方法，该制备方法的流程图如图8A所示，该制备方法至少包括步骤S301-S310。该方法与上述形成图4A和图4B的显示基板的方法相比，区别主要在于步骤S303中栅极引线和半导体层的形成方式。下面将重点描述该区别之处，其他部分的形成方法可参照上述实施例。
步骤S301：提供衬底基板。
步骤S302：形成缓冲层。
步骤S303：形成栅极引线和半导体层。
参照图5A、图5B和图8B。例如，栅极引线303与驱动晶体管的半导体层310采用同一多晶硅材料层通过构图工艺与掺杂工艺形成。
例如，形成栅极引线303与驱动晶体管的半导体层310包括：形成半导体材料层(例如多晶硅材料层)，半导体材料层包括沟道区310A、源极区310B、漏极区310C和栅极引线区(303指示的区域)；对源极区310B、漏极区310C和栅极引线区进行掺杂，以使源极区310B、漏极区310C和栅极引线区导体化。例如，对栅极引线区进行第一掺杂以形成栅极引线303，对源极区310B和漏极区310C进行第二掺杂以形成驱动晶体管的源极和漏极。
例如，第一掺杂和第二掺杂均为重掺杂，从而使多晶硅材料层具有良好的导电性。例如，还可以对沟道区110A进行第三掺杂，例如轻掺杂，以形成薄膜晶体管的沟道。例如，该掺杂为硼掺杂或磷掺杂等，本公开的实施例对此不做限定。
例如，在采用同一多晶硅材料层形成栅极引线303与半导体层310的同时，还可以形成连接栅极引线303的导电结构311，此时，对应于导电结构311的多晶硅层也进行重掺杂，以具有良好的导电性。
步骤S304：形成栅极绝缘层。
步骤S305：形成栅极。
例如，参照图5A、图5B和图8C，栅极302形成于对应于沟道区310A的位置，其具体形成方式可参照上述实施例，在此不再赘述。
步骤S306：形成层间绝缘层。
步骤S307：形成屏蔽层。
例如，参照图5A、图5B和图8D，屏蔽层305形成于对应于栅极302的位置，其具体形成方式可参照上述实施例，在此不再赘述。
步骤S308：形成第二层间绝缘层。
步骤S309：形成数据线。
例如，数据线304的形成位置可参照图5A、图5B和图8E，数据线304的具体形成方式可参照上述实施例，在此不再赘述。
步骤S310：形成发光器件等。
上述未详细说明的步骤可参照上述实施例，在此不再赘述。
本公开实施例提供的显示基板的制备方法通过将栅极引线形成在栅极和衬底基板之间，使得栅极与数据线之间可形成具有一定完整性的屏蔽层，该屏蔽层可以避免栅极与数据线之间形成寄生电容，从而避免该寄生电容可能产生的不良影响，提高显示基板的显示质量。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，
    像素驱动电路，在所述衬底基板上，包括驱动晶体管和栅极引线，所述驱动晶体管包括栅极，所述栅极引线电连接于所述栅极，
    其中，所述栅极引线位于所述栅极与所述衬底基板之间。
  2. 根据权利要求1所述的显示基板，还包括数据线，所述数据线位于所述栅极的远离所述衬底基板的一侧，
    所述驱动晶体管配置为在所述栅极接收由所述数据线提供的数据电压信号并基于所述数据电压信号控制流过所述驱动晶体管的驱动电流，所述驱动电流用于驱动发光器件工作。
  3. 根据权利要求2所述的显示基板，还包括：
    屏蔽层，在所述栅极所在的层与所述数据线所在的层之间，
    其中，所述屏蔽层与所述栅极彼此绝缘且在垂直于所述衬底基板的方向上彼此重叠。
  4. 根据权利要求3所述的显示基板，其中，所述屏蔽层为金属层。
  5. 根据权利要求3所述的显示基板，其中，所述栅极引线在所述衬底基板上的正投影与所述屏蔽层在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求3所述的显示基板，还包括：
    缓冲层，在所述衬底基板上且包括第一过孔，
    其中，所述栅极引线位于所述缓冲层的靠近所述衬底基板的一侧，所述栅极位于所述缓冲层远离所述衬底基板的一侧，所述栅极引线通过所述第一过孔与所述栅极连接。
  7. 根据权利要求6所述的显示基板，其中，所述缓冲层还包括第二过孔，所述栅极引线通过所述第二过孔与不同于所述驱动晶体管的电路元件电连接。
  8. 根据权利要求7所述的显示基板，其中，所述电路元件包括复位晶体管、补偿晶体管或存储电容。
  9. 根据权利要求3所述的显示基板，还包括：
    第二缓冲层，在所述衬底基板上，
    其中，所述栅极引线位于所述第二缓冲层的远离所述衬底基板的一侧。
  10. 根据权利要求9所述的显示基板，还包括：
    导电层，位于所述栅极引线的远离所述衬底基板的一侧，并且覆盖至少部分所述栅极引线的侧面以及所述栅极引线的远离所述衬底基板的表面。
  11. 根据权利要求3-10任一所述的显示基板，还包括遮光层，其中，所述栅极引线与遮光层同层，且所述遮光层与所述像素驱动电路至少部分重叠。
  12. 根据权利要求1所述的显示基板，其中，所述驱动晶体管还包括半导体层，所述栅极引线与所述半导体层同层。
  13. 根据权利要求12所述的显示基板，其中，所述半导体层包括未导体化的沟道区、导体化的源极区和导体化的漏极区，所述栅极引线包括导体化的半导体材料。
  14. 一种显示基板的制备方法，包括：
    提供衬底基板，
    在所述衬底基板上形成像素驱动电路，所述像素驱动电路包括驱动晶体管和栅极引线，所述驱动晶体管包括栅极，所述栅极引线电连接于所述栅极，
    其中，所述栅极引线形成于所述栅极与所述衬底基板之间。
  15. 根据权利要求14所述的制备方法，还包括：
    在所述栅极的远离所述衬底基板的一侧形成数据线，
    其中，所述驱动晶体管形成为在所述栅极接收由所述数据线提供的数据电压信号并基于所述数据电压信号控制流过所述驱动晶体管的驱动电流，所述驱动电流用于驱动发光器件工作。
  16. 根据权利要求15所述的制备方法，还包括：
    在所述栅极所在的层与所述数据线所在的层之间形成屏蔽层，
    其中，所述屏蔽层与所述栅极彼此绝缘且在垂直于所述衬底基板的方向上彼此重叠。
  17. 根据权利要求15或16所述的制备方法，其中，所述栅极引线与遮光层同层形成，其中，所述遮光层与所述像素驱动电路至少部分重叠。
  18. 根据权利要求14所述的制备方法，其中，形成所述驱动晶体管还包括：形成半导体层，
    其中，所述栅极引线与所述半导体层同层形成。
  19. 根据权利要求18所述的制备方法，其中，形成所述栅极引线与所述半导体层包括：
    形成半导体材料层，所述半导体材料层包括沟道区、源极区、漏极区和栅极引线区；
    对所述源极区、所述漏极区和所述栅极引线区进行掺杂，以使所述源极区、所述漏极区和所述栅极引线区导体化。
  20. 一种显示面板，包括权利要求1-13任一所述的显示基板。
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