WO2020094126A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2020094126A1
WO2020094126A1 PCT/CN2019/116629 CN2019116629W WO2020094126A1 WO 2020094126 A1 WO2020094126 A1 WO 2020094126A1 CN 2019116629 W CN2019116629 W CN 2019116629W WO 2020094126 A1 WO2020094126 A1 WO 2020094126A1
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WIPO (PCT)
Prior art keywords
transistor
gate
layer
electrically connected
auxiliary metal
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PCT/CN2019/116629
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English (en)
French (fr)
Inventor
龙春平
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/768,555 priority Critical patent/US11244606B2/en
Publication of WO2020094126A1 publication Critical patent/WO2020094126A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a manufacturing method thereof, and a display device including the display substrate.
  • the display substrate usually includes a plurality of pixel units, and each pixel unit is provided with a pixel circuit. By providing signals to the pixel circuits in each pixel unit, the pixel unit can be driven to emit light.
  • a display substrate including: a substrate; and a first graphics layer, a second graphics layer, and a third graphics layer provided on the substrate, wherein the third The graphics layer is disposed on the substrate, the first graphics layer is disposed on the third graphics layer, the second graphics layer is disposed on the first graphics layer, and the first graphics layer includes at least One auxiliary metal line, the second pattern layer includes at least one power line, the third pattern layer includes multiple rows and columns of second electrodes arranged in an array, and one auxiliary metal line among the at least one auxiliary metal line A row of second electrodes in the plurality of rows and columns of second electrodes is disposed opposite to and partially overlaps with at least one second electrode in the row of second electrodes to form at least one storage capacitor, and the auxiliary metal line passes through The hole is electrically connected to the at least one power line.
  • the width of the overlapping portion of the auxiliary metal line and the second electrode is larger than the width of the remaining portion of the auxiliary metal line, and the overlapping portion is used as the first electrode of the storage capacitor.
  • the auxiliary metal line has a protrusion at a position opposite to the second electrode, and the protrusion is used as the first electrode of the storage capacitor.
  • the extending direction of the at least one power line is parallel to the column direction of the second electrodes of the multiple rows and multiple columns, and the extending direction of the at least one auxiliary metal line is the second direction of the multiple rows and multiple columns
  • the row directions of the electrodes are parallel, and the extension direction of the at least one power supply line is perpendicular to the extension direction of the at least one auxiliary metal line.
  • the second graphics layer further includes a plurality of data lines
  • the third graphics layer further includes a plurality of gate lines
  • an extension direction of the at least one power supply line is different from that of the plurality of data lines
  • the extending direction is parallel
  • the extending direction of the at least one auxiliary metal line is parallel to the extending direction of the plurality of gate lines.
  • the first graphic layer further includes at least one reset signal line provided at the same layer as the at least one auxiliary metal line.
  • the first pattern layer further includes an interlayer insulating layer, which is disposed on the at least one auxiliary metal line, and each auxiliary metal line in the at least one auxiliary metal line is disposed on the The via in the interlayer insulating layer is electrically connected to the at least one power line.
  • the at least one power line and the plurality of data lines in the second graphics layer are disposed on the interlayer insulating layer.
  • the third graphic layer further includes: a second gate insulating layer, which is disposed on the second electrodes of the plurality of rows and columns and the plurality of gate lines, on which the at least An auxiliary metal wire.
  • the display substrate further includes an active layer provided on the substrate; and a first gate insulating layer provided on the active layer and the exposed substrate The plurality of rows and columns of second electrodes and the plurality of gate lines are provided.
  • the display substrate is divided into a plurality of pixel units based on a plurality of rows and columns of second electrodes arranged in an array
  • the at least one auxiliary metal line includes a plurality of auxiliary metal lines
  • the at least one The power line includes a plurality of power lines
  • the plurality of auxiliary metal lines are electrically connected to the plurality of power lines through via holes, respectively
  • the plurality of auxiliary metal lines are respectively arranged opposite to the plurality of rows of second electrodes
  • Each second electrode of the two electrodes partially overlaps to form a plurality of storage capacitors, and each pixel unit of the plurality of pixel units is provided with a pixel circuit and an organic light-emitting diode.
  • the pixel circuit includes a driving transistor, The data writing transistor, the first light-emission control transistor, the second light-emission control transistor, the reset transistor, the compensation sub-circuit and the storage capacitor, and the second electrode of the storage capacitor serves as the drive transistor of the pixel unit where the storage capacitor is located
  • the gate wherein the source of the driving transistor is electrically connected to the drain of the first light emitting control transistor, the driving transistor Is electrically connected to the source of the second light-emitting control transistor; the source of the first light-emitting control transistor is electrically connected to one of the power lines, and the The gate is electrically connected to the light emission control signal line; the drain of the second light emission control transistor is electrically connected to the anode of the organic light emitting diode, and the gate of the second light emission control transistor is electrically connected to the light emission control signal line
  • the source of the reset transistor is electrically connected to the reset signal line, the drain of the reset transistor is electrically connected to the gate of the drive transistor, and the gate of the reset transistor is
  • the compensation sub-circuit includes a first compensation transistor and a second compensation transistor, the gate of the first compensation transistor is electrically connected to the gate of the second compensation transistor, and is formed as the The control terminal of the compensation subcircuit; the source of the first compensation transistor is electrically connected to the drain of the second compensation transistor, and the drain of the first compensation transistor serves as the second end of the compensation subcircuit The drain of the driving transistor is electrically connected, and the source of the second compensation transistor is electrically connected to the gate of the driving transistor as the first end of the compensation sub-circuit.
  • the display substrate further includes a buffer layer formed on the substrate, and the active layer is formed on the buffer layer.
  • the substrate is made of polyurethane material
  • the active layer is made of polysilicon material
  • the buffer layer is made of silicon oxide and / or silicon nitride.
  • a display device including the above-described display substrate.
  • a method for manufacturing a display substrate includes a third graphics layer, a first graphics layer, and a second graphics layer disposed in sequence on a substrate.
  • the method includes : Forming the third pattern layer, comprising: forming a plurality of rows and columns of second electrodes arranged in an array on the substrate; forming a second on the bare substrate and the plurality of rows and columns of second electrodes A gate insulating layer, forming the first pattern layer, comprising: forming at least one auxiliary metal line on the second gate insulating layer, and making one auxiliary metal line of the at least one auxiliary metal line and the plurality of rows A row of second electrodes in a plurality of columns of second electrodes is oppositely arranged and partially overlaps with at least one second electrode in the row of second electrodes to form at least one storage capacitor; forming an interlayer insulation on the at least one auxiliary metal wire A layer; forming a via hole extending to the at least one auxiliary metal line in the interlayer
  • the method before forming the third pattern layer, further includes: forming an active layer on the substrate; forming a first gate on the active layer and the bare substrate An insulating layer, a plurality of rows and columns of second electrodes arranged in an array are formed on the first gate insulating layer, and forming the first pattern layer further includes: forming at least one auxiliary metal line while forming at least one auxiliary metal line A reset signal line.
  • the display substrate is divided into a plurality of pixel units based on the plurality of rows and columns of second electrodes arranged in an array, and each of the plurality of pixel units includes a pixel circuit and An organic light emitting diode
  • the pixel circuit includes a driving transistor, a data writing transistor, a first light emitting control transistor, a second light emitting control transistor, a reset transistor, a first compensation transistor, a second compensation transistor, and the storage capacitor
  • the third pattern layer further includes: forming a plurality of rows and columns of second electrodes arranged in an array on the first gate insulating layer, and forming the data writing transistor on the first gate insulating layer ,
  • the gate of the first emission control transistor, the gate of the second emission control transistor, the gate of the reset transistor, the gate of the first compensation transistor, the second compensation transistor Gate, multiple gate lines, light emission control signal lines and reset control signal lines, the second electrode of the storage capacitor is used as the gate of the driving transistor, And the gate of
  • forming the second pattern layer further includes: forming, in the interlayer insulating layer, a source region extending to the first light emission control transistor and a drain of the second light emission control transistor, respectively Electrode region, the second electrode of the storage capacitor, the source region of the data writing transistor, the source region of the second compensation transistor, the source region of the reset transistor and the reset signal line A hole; while forming the at least one power line on the interlayer insulating layer, forming the drain of the second light-emission control transistor, a plurality of data lines, and the via of the second pole of the storage capacitor The electrical connection line between the vias of the source region of the second compensation transistor and the electrical connection line between the vias of the source region of the reset transistor and the via of the reset signal line, and making the The power line electrically connected to one of the at least one auxiliary metal line among the at least one power line is electrically connected to the source region of the first light-emitting control transistor through the via in the interlayer insulating layer connection.
  • FIG. 1 is a cross-sectional view of a display substrate at an organic light emitting diode, a driving transistor, and a storage capacitor according to an embodiment of the present disclosure, and shows the connection of an auxiliary metal line and a power line;
  • FIG. 2 is a schematic diagram of a pixel circuit on a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional view of a display substrate at a light-emitting control transistor, a driving transistor, and a storage capacitor according to an embodiment of the present disclosure
  • FIG. 4 is a cross-sectional view of a display substrate at a reset transistor, a compensation transistor, and a driving transistor according to an embodiment of the present disclosure
  • 5A to 5K are schematic diagrams of structures obtained by various steps in a method of manufacturing a display substrate provided by the present disclosure according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure
  • FIG. 7 is an exemplary flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the inventor of the present disclosure has repeatedly studied and found that one reason why the display device has uneven light emission during display is as follows.
  • the pixel circuit in each pixel unit is provided with a high-level voltage signal through the power line and the power line has an internal resistance. Therefore, in the process of transmitting the high-level voltage signal, the resistance voltage drop (IR Drop) of the power line will cause The high-level voltage signals received by each pixel unit are different, so that each pixel unit emits light unevenly, reducing the display effect.
  • the present disclosure provides a display substrate including a substrate and a first graphics layer, a second graphics layer, and a third graphics layer provided on the substrate.
  • 1 is a cross-sectional view taken along line aa 'in FIG. 5K
  • the third graphic layer 13 is disposed on the substrate 100
  • the first graphic layer 11 is disposed on the third graphic layer 13
  • the second graphic layer 12 ⁇ on the first graphics layer 11.
  • the first pattern layer 11 includes at least one auxiliary metal line 210
  • the second pattern layer 12 includes at least one power line 110
  • at least one auxiliary metal line 210 is electrically connected to at least one power line 110 through a via
  • the layer 13 includes a plurality of rows and columns of second electrodes 320 arranged in an array.
  • One auxiliary metal line of at least one auxiliary metal line 210 is disposed opposite to a row of second electrodes in the second electrodes of the plurality of rows and columns and partially overlaps with at least one second electrode in the second electrode of the row to form at least one storage capacitor Cst, and the auxiliary metal line 210 is electrically connected to at least one power line 110 through a via.
  • the second electrodes 320 based on multiple rows and columns arranged in an array may divide the display substrate into a plurality of pixel units arranged in an array.
  • Each column of pixel units may correspond to one power supply line. Therefore, the number of at least one power supply line may be the same as the number of columns of pixel units. Similarly, the number of at least one auxiliary metal line may be the same as the number of rows of pixel units.
  • At least one power line 110 and at least one auxiliary metal line 210 are electrically connected to each other, which is equivalent to increasing the cross-sectional area of the power line, so that the resistance of the combined structure of the two is less than the resistance of the power line 110 itself.
  • the power supply line 110 is electrically connected to a DC power supply, and a high-level voltage is provided to the display substrate via the combined structure of the power supply line 110 and the auxiliary metal line 210. Since the resistance of the above-mentioned combined structure is smaller than the resistance of the power supply line 110, compared with the related art that only the high-level voltage is transferred through the power supply line, when the display device including the display substrate provided by the present disclosure performs display, the signal transfer process The IR drop in the resistor is smaller, so that the difference between the high-level signals received by different pixel units can be reduced, thereby improving the uniformity of the display.
  • the extension direction of at least one power line 110 is perpendicular to the extension direction of at least one auxiliary metal line 210.
  • the orthographic projections of the plurality of power lines 110 and the plurality of auxiliary metal lines 210 on the display substrate form a grid.
  • the power supply line 110 is generally electrically connected to the source of the light emission control transistor through the high-level signal terminal ELVDD.
  • the source, drain, and data lines of different transistors are usually provided on the same layer. Therefore, in order to simplify the manufacturing process and reduce the thickness of the display substrate, in some embodiments, the power line 110 Set on the same layer as the data line. That is, the second graphics layer 12 further includes multiple data lines.
  • the extension direction of at least one power line 110 is parallel to the column direction of the second electrodes in multiple rows and columns, and the extension direction of at least one auxiliary metal line 210 is The row directions of the second electrodes in the rows and columns are parallel, and the extending direction of the at least one power line 110 is perpendicular to the extending direction of the at least one auxiliary metal line 210.
  • the first pattern layer 11 further includes an interlayer insulating layer 400 disposed on at least one auxiliary metal line 210, and each auxiliary metal line in the at least one auxiliary metal line 210
  • the via holes provided in the interlayer insulating layer 400 are electrically connected to at least one power line 110 respectively.
  • At least one power line 110 and multiple data lines in the second pattern layer 12 are disposed on the interlayer insulating layer 400.
  • the third pattern layer 13 further includes a second gate insulating layer 420, which is disposed on the second electrodes 320 in multiple rows and columns and on multiple gate lines, on which at least one Auxiliary metal wire 210.
  • the display substrate further includes an active layer 500 and a first gate insulating layer 410.
  • the active layer 500 is provided on the substrate 100.
  • the first gate insulating layer 410 is disposed on the active layer 500 and the exposed substrate 100.
  • a plurality of rows and columns of second electrodes 320 and a plurality of gate lines GATE are provided on the first gate insulating layer 410.
  • the display substrate includes a plurality of pixel units, and each pixel unit includes an organic light emitting diode and a pixel circuit, and the pixel circuit is used to drive the organic light emitting diode to emit light.
  • the pixel circuit includes a driving transistor T1 and a storage capacitor Cst.
  • the driving transistor T1 is used to generate a driving current
  • the storage capacitor Cst is for storing the data voltage and the threshold voltage of the driving transistor T1.
  • the purpose of storing the threshold voltage of the driving transistor T1 is to compensate the threshold voltage of the driving transistor T1 when driving the organic light emitting diode to emit light, so as to prevent the threshold voltage of the driving transistor T1 from affecting the light emission of the organic light emitting diode.
  • the first electrode of the storage capacitor Cst is electrically connected to the power supply line 110 through the auxiliary metal line 210, and the second electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1.
  • a part of the auxiliary metal line 210 may be used as the first electrode of the storage capacitor Cst (in the embodiment shown in FIG. 5E, the auxiliary metal line 210 may be The second electrode of the storage capacitor Cst protrudes at a relative position, and the protrusion is used as the first electrode 220 of the storage capacitor Cst). That is, the portion where the auxiliary metal line 210 overlaps the second electrode is larger than the width of the remaining part of the auxiliary metal line 210.
  • the storage capacitor Cst is used to store the data voltage and the threshold voltage of the driving transistor T1. Therefore, in general, the second electrode 320 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1. In order to simplify the manufacturing process, in some embodiments, the second electrode 320 of the storage capacitor Cst may be used as the gate of the driving transistor T1, as shown in FIG. 5E. In order to facilitate manufacturing, the gates of each transistor in the display substrate and a plurality of gate lines are all located in the third pattern layer 13.
  • FIG. 2 is a schematic diagram of a pixel circuit, and the positional relationship of each transistor in the pixel circuit on the display substrate is shown in FIG. 5G.
  • the pixel circuit further includes a data writing transistor T2, a first light-emission control transistor T5, a second light-emission control transistor T6, a reset transistor T4, and a compensation sub-circuit.
  • the second electrode 320 of the storage capacitor Cst can be used as the gate of the driving transistor T1 in the pixel unit where the storage capacitor is located, and there is no need to provide the gate of the driving transistor T1.
  • the source of the driving transistor T1 is electrically connected to the drain of the first light emission control transistor T5
  • the gate of the driving transistor T1 is electrically connected to the second electrode 320 of the storage capacitor Cst
  • the drain of the driving transistor T1 It is electrically connected to the source of the second light emission control transistor T6.
  • the source of the first light-emitting control transistor T5 is electrically connected to one of the at least one power line 110 through the high-level signal terminal ELVDD, and the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EMn through the port Eln .
  • the drain of the second emission control transistor T6 is electrically connected to the anode of the organic light emitting diode OLED, and the gate of the second emission control transistor T6 is electrically connected to the emission control signal line EMn through the port Eln.
  • the source of the reset transistor T4 is electrically connected to the reset signal line VINT through the reset signal terminal ELVINT, the drain of the reset transistor T4 is electrically connected to the gate of the drive transistor T1, and the gate of the reset transistor T4 passes through the reset signal control terminal SLn-1 It is electrically connected to the reset control signal line RESET.
  • the gate of the reset transistor T4 receives an effective reset control signal, the source of the reset transistor and the drain of the reset transistor are turned on, thereby turning on the gate of the driving transistor T1 and the reset signal line VINT, and The gate of the transistor T1 and the storage capacitor Cst are reset.
  • the source of the data writing transistor T2 is electrically connected to one of the data lines DATA through the data signal writing terminal DLm, the drain of the data writing transistor T2 is electrically connected to the source of the driving transistor T1, and the data is written
  • the gate of the input transistor T2 is electrically connected to one of the gate lines GATE through the data write control signal terminal SLn.
  • the data writing transistor T2 is set such that the source of the data writing transistor T2 and the drain of the data writing transistor T2 are turned on when the gate of the data writing transistor T2 receives an effective control signal, thereby passing data
  • the data voltage written at the signal writing terminal is written to the storage capacitor Cst.
  • the first end of the compensation subcircuit is electrically connected to the gate of the driving transistor T1
  • the second end of the compensation subcircuit is electrically connected to the drain of the driving transistor T1
  • the control end of the compensation subcircuit is connected to the gate of the data writing transistor T2 Polar connection.
  • the compensation sub-circuit may electrically connect the gate and the drain of the driving transistor T1 when the control terminal of the compensation sub-circuit receives an effective control signal, so that the storage capacitor Cst stores the threshold voltage of the driving transistor T1.
  • the compensation sub-circuit may include a first compensation transistor T3 and a second compensation transistor T7.
  • the source of the first compensation transistor T3 is electrically connected to the drain of the second compensation transistor T7.
  • the drain of the first compensation transistor T3 serves as the second end of the compensation subcircuit and is electrically connected to the source of the second light emission control transistor T6.
  • the source of the second compensation transistor T7 is electrically connected to the gate of the drive transistor T1 as the first end of the compensation subcircuit.
  • the gate of the first compensation transistor T3 is electrically connected to the gate of the second compensation transistor T7 and forms a control terminal of the compensation sub-circuit.
  • the gate of the first compensation transistor T3 and the gate of the second compensation transistor T7 are electrically connected to the gate of the data writing transistor T2, that is, the same gate can be used
  • the line control data writing transistor T2, the first compensation transistor T3, and the second compensation transistor T7 are electrically connected to the gate of the data writing transistor T2, that is, the same gate can be used.
  • the gate of the driving transistor T1, the gate of the data writing transistor T2, the gate of the first emission control transistor T5, the gate of the second emission control transistor T6, the gate of the reset transistor T4, the first The gate of one compensation transistor T3 and the gate of the second compensation transistor T7 are arranged in the same layer (third pattern layer 13).
  • FIG. 3 is a cross-sectional view taken along line bb ′ in FIG. 5K.
  • 4 is a cross-sectional view taken along line cc ′ in FIG. 5K.
  • a part of the reset transistor T4, the first compensation transistor T3, and the second compensation transistor T7 are cut And a part of the driving transistor T1.
  • active layers of different transistors are all formed in the same layer.
  • the active layer of the pixel circuit is formed on the substrate.
  • a buffer layer 600 may also be provided between the substrate and the active layer 500 .
  • the specific material of the substrate is not particularly limited.
  • the substrate may be a glass substrate or a flexible substrate made of polyurethane material.
  • the buffer layer 600 may be made of silicon oxide (SiOx) or silicon nitride (SiNx).
  • each transistor in the display substrate (including the first light-emission control transistor T5, the second light-emission control transistor T6, the reset transistor T4, the drive transistor T1, the first A compensation transistor T3 and a second compensation transistor body T7) are top-gate transistors.
  • the third pattern layer 13 is located above the first gate insulating layer 410, and the first pattern layer 11 is located above the third pattern layer 13, and the second pattern layer 12 is located above the first pattern layer 11.
  • each transistor may also be a bottom-gate transistor.
  • the substrate 100 may be made of polyurethane material
  • the active layer 500 may be made of polysilicon material
  • the buffer layer 600 may be made of silicon oxide and / or silicon nitride.
  • the display substrate further includes a passivation layer 700, which is disposed on the second pattern layer 12 and has a via extending to the drain A of the second emission control transistor T6.
  • the display substrate further includes a planarization layer 800, which is disposed on the passivation layer 700 and has a via extending to the via of the passivation layer 700, that is, the via of the planarization layer 800 and the via of the passivation layer 700 are Coaxial in the direction perpendicular to the substrate.
  • the display substrate further includes a pixel electrode 900, which is disposed on the planarization layer 800, and is electrically connected to the drain A of the second light emission control transistor T6 through the via of the passivation layer 700 and the via in the planarization layer 800 .
  • the display substrate also includes an organic light emitting diode, which is disposed on the pixel electrode 900.
  • the passivation layer 700 may be made of silicon nitride.
  • the planarization layer 800 may be made of polyurethane material.
  • a display device including a display substrate, wherein the display substrate is the above-mentioned display substrate provided by the present disclosure.
  • the combined structure of the power supply line and the auxiliary metal line with a small resistance is used to provide high-level signals to each pixel unit, which can reduce the resistance of high-level signals during transmission
  • the voltage drop makes the signals received by each pixel unit closer, thereby making the brightness of each pixel unit more uniform and improving the display effect of the display device.
  • the display device may be a wearable device, or may be an electronic device such as a tablet computer, a navigator, or the like.
  • the manufacturing method of the display substrate provided by the present disclosure includes sequentially forming a third pattern layer, a first pattern layer, and a second pattern layer on a substrate, as shown in FIG. 6.
  • the forming of the third pattern layer includes steps S1 and S2, wherein in step S1, a plurality of rows and columns of second electrodes arranged in an array are formed on the substrate; in step S2, the bare substrate and the multi-row A second gate insulating layer is formed on the second electrode of the column.
  • the forming of the first pattern layer includes steps S3 and S5, wherein, in step S3, at least one auxiliary metal line is formed on the second gate insulating layer, and at least one auxiliary metal line is provided corresponding to each second electrode row At least one second electrode in the two-electrode row partially overlaps to form at least one storage capacitor; in step S4, an interlayer insulating layer is formed on at least one auxiliary metal line; in step S5, it is formed in the interlayer insulating layer Vias extending to at least one auxiliary metal wire.
  • the forming of the second pattern layer includes step S6, wherein in step S6, at least one power line is formed on the interlayer insulating layer, and at least one power line is electrically connected to at least one auxiliary metal line through the via in the interlayer insulating layer connection.
  • FIGS. 1 to 4 The manufacturing method for manufacturing the display substrate in FIGS. 1 to 4 will be described below with reference to FIGS. 5A to 5K and FIG. 7.
  • a substrate 100 is provided.
  • the substrate may be made of polyurethane material.
  • a buffer layer 600 is formed on the substrate (as shown in FIG. 5B).
  • PECVD plasma enhanced chemical vapor deposition
  • SiN silicon nitride
  • SiO2 silicon dioxide
  • an amorphous silicon layer is formed on the buffer layer 600.
  • An amorphous silicon (a-Si) layer is formed on the buffer layer 600 using PECVD or other chemical or physical vapor deposition methods.
  • the amorphous silicon layer is crystallized by a laser annealing (ELA) or solid phase crystallization (SPC) method to form a polycrystalline silicon layer.
  • ELA laser annealing
  • SPC solid phase crystallization
  • a first photoresist pattern is formed on the polysilicon layer, the first photoresist pattern is used as an etching barrier layer, and the polysilicon layer not protected by the first photoresist pattern is etched by plasma to form an active ⁇ 500 ⁇ Layer 500.
  • FIG. 5A is a plan view of a display substrate having an active layer 500 (a light-transmitting layer is not shown), and FIG. 5B is a cross-sectional view taken along line d-d 'of FIG. 5A.
  • the ion implantation process is used to dope the transistor channel in the polysilicon active layer 500 with low concentration ions to form a conductive channel required by the thin film transistor in the polysilicon active layer 500.
  • silicon dioxide or silicon dioxide and silicon nitride are deposited to obtain the first gate insulating layer 410.
  • the photoresist on the polysilicon active layer 500 is removed through a photoresist stripping process, SiO2 or SiO2 and SiN are deposited using PECVD, and a first gate insulating layer 410 is formed on the polysilicon active layer and the entire buffer layer.
  • one or more low-resistance metal material films are deposited on the first gate insulating layer 410 by a physical vapor deposition method such as magnetron sputtering, and a gate pattern layer is formed by a photolithography process, and the gate pattern layer Including the light emission control signal line EMn, the multiple gate lines GATE, the multiple reset control signal lines RESET, the gates of the transistors (not shown, including the gate of the data writing transistor T2 in FIG.
  • FIG. 5C is a top view of the second electrode 320, the light emission control signal line EMn, the plurality of gate lines GATE, and the reset control signal line RESET.
  • the second electrode 320 is used as the gate of the driving transistor T1 and allows data to be written into the transistor
  • the gate of T2, the gate of the first compensation transistor T3, and the gate of the second compensation transistor T7 are electrically connected to the same gate line GATE of the plurality of gate lines through the data write control signal terminal SLn, and the first light is emitted
  • the gates of the control transistor T5 and the second light-emission control transistor T6 are electrically connected to the light-emission control signal line EMn through corresponding light-emission control signal control terminals ELn, respectively.
  • Fig. 5D is a cross-sectional view taken along line e-e 'of Fig. 5C.
  • the gate pattern layer may be a single-layer metal thin film such as Al, Cu, Mo, Ti, or AlNd, or may be a multi-layer metal thin film such as Mo / Al / Mo or Ti / Al / Ti.
  • the gate electrode and the second electrode 320 in the gate pattern layer are used as ion implantation barrier layers to ion-dope the active layer 500 to form a low area in the polysilicon active layer region that is not blocked by the gate electrode Impedance source and drain regions. Based on the structure of the active layer 500 of FIG.
  • the source region of the driving transistor T1, the drain region of the first light-emission control transistor T5, and the drain region of the data writing transistor T2 can be in the active layer 500 is formed as one body, the drain region of the driving transistor T1, the source region of the second light emission control transistor T6 and the drain region of the first compensation transistor T3 are formed as one body in the active layer 500, and the drain of the reset transistor T4
  • the region and the source region of the first compensation transistor T3 are integrally formed in the active layer 500, and the source region of the first compensation transistor T3 and the drain region of the second compensation transistor T7 are integrally formed in the active layer 500.
  • the source region and the drain region in the active layer 500 are respectively equivalent to the source and / or drain of the corresponding transistor, and each transistor is connected through the source-drain region without providing a corresponding source and drain.
  • the second gate insulating layer 420 is formed. On the entire surface including the gate pattern layer, a SiO2 film and a SiN film are sequentially deposited using a PECVD process to form a second gate insulating layer 420.
  • a plurality of auxiliary metal lines 210 and a plurality of reset signal lines VINT are formed on the second gate insulating layer 420.
  • Each of the plurality of auxiliary metal lines 210 has a protrusion at a position opposite to the second electrode 320, and the protrusion is used as the first electrode 220 of the storage capacitor.
  • FIG. 5E shows a top view with the auxiliary metal line 210 and the reset signal line VINT
  • FIG. 5F shows a cross-sectional view taken along line f-f 'of FIG. 5E.
  • FIG. 5G is a cross-sectional view taken along line g-g 'of FIG. 5G, which shows a via extending to the first electrode 220 of the storage capacitor and a via extending to the source region of the first light emission control transistor T5.
  • a plurality of power lines 110, a plurality of data lines DATA, a drain A of the second light emission control transistor T6, a via of the second electrode 320 of the storage capacitor, and a second compensation transistor are formed on the interlayer insulating layer 400
  • One or more low-resistance metal thin films are deposited on the interlayer insulating layer 400 by a magnetron sputtering process, and a plurality of power lines 110, a plurality of data lines DATA, and a second light-emitting control transistor are formed through a mask and an etching process
  • the drain A of T6, and the power line electrically connected to one auxiliary metal line among the plurality of auxiliary metal lines 210 among the plurality of power line 110 is electrically connected to the source of the first light emitting control transistor T5 through the via
  • One of the data lines DATA is electrically connected to the source region of the data writing transistor T2 through the via
  • the second electrode 320 of the storage capacitor and the source region of the second compensation transistor T7 are electrically connected through the electrical connection line and reset
  • the source region of the transistor T4 and the reset signal line VINT are electrically connected by an electrical connection line.
  • the metal film of the electrical connection line between the via of the source region of the reset transistor T4 and the via of the reset signal line VINT may be a single-layer metal thin film of Al, Cu, Mo, Ti, or AlNd, It may also be a multilayer metal thin film such as Mo / Al / Mo or Ti / Al / Ti.
  • 5I is a plan view of the drain A having the power supply line 110, the data line DATA, and the second light emission control transistor T6, and FIG. 5J is a cross-sectional view taken along line h-h 'of FIG. 5I.
  • a layer of silicon nitride film is deposited on the entire surface including the power supply line 110, the data line DATA, and the drain A of the second light emission control transistor T6, and an anode electrode including an organic light emitting diode is formed through a mask and an etching process ⁇ ⁇ passivation layer 700.
  • the via on the passivation layer 700 extends to the drain A of the second light emission control transistor T6.
  • a rapid thermal annealing or a heat treatment furnace annealing is used to perform a hydrogenation process to repair defects inside and at the interface of the active layer 500.
  • an organic planarization layer 800 having a via hole having the same vertical axis as the anode via hole is formed over the passivation layer 700 again by a mask process to fill the device surface with a low concavity to form a flat surface. And the via hole in the planarization layer 800 extends to the via hole in the passivation layer 700.
  • magnetron sputtering is used to deposit a transparent conductive film on the organic planarization layer 800, the transparent conductive film is etched through a photolithography process, and the via hole of the organic planarization layer 800 and part of the organic planarization layer 800
  • the pixel electrode 900 in the pixel area is formed thereon, as shown in FIG. 5K.
  • a layer of photosensitive organic material similar to the organic planarization layer is coated on the exposed organic planarization layer and the pixel electrode, and a partial area of the pixel electrode is exposed through the last mask process to form the pixel definition layer 1000.
  • the pixel definition layer covers the organic planarization layer and part of the pixel electrode area.
  • the transparent conductive film may be a single-layer oxide conductive film, such as ITO or IZO, or a composite film such as ITO / Ag / ITO or IZO / Ag.
  • the display substrate provided by the present disclosure can be obtained through 8 to 9 mask processes. After the display substrate provided by the present disclosure is obtained, each functional layer of the organic light emitting diode can also be formed on the display substrate, and the display substrate is encapsulated to obtain a display panel.

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Abstract

一种显示基板及其制作方法、显示装置，所述显示基板，包括：衬底（100）；以及在所述衬底（100）上设置的第一图形层（11）、第二图形层（12）和第三图形层（13），其中，所述第三图形层（13）设置在所述衬底（100）上，所述第一图形层（11）设置在所述第三图形层（13）上，所述第二图形层（12）设置在所述第一图形层（11）上，所述第一图形层（11）包括至少一条辅助金属线（210），所述第二图形层（12）包括至少一条电源线（110），所述第三图形层（13）包括呈阵列排布的多行多列第二电极（320），所述至少一条辅助金属线（210）中的一条辅助金属线与所述多行多列第二电极（320）中的一行第二电极相对设置并与该行第二电极中的至少一个第二电极部分地重叠以形成至少一个存储电容（Cst），并且该条辅助金属线通过过孔与所述至少一条电源线（110）电连接。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2018年11月8日在中国知识产权局提交的申请号为201821835171.6、名称为“显示基板和显示装置”的中国专利申请的优先权，该中国专利申请的全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，具体地，涉及一种显示基板及其制作方法、和一种包括该显示基板的显示装置。
背景技术
显示基板通常包括多个像素单元，每个像素单元内都设置有像素电路。通过向各个像素单元中的像素电路提供信号，可以驱动像素单元发光。
发明内容
根据本公开的实施例，提供了一种显示基板，其包括：衬底；以及在所述衬底上设置的第一图形层、第二图形层和第三图形层，其中，所述第三图形层设置在所述衬底上，所述第一图形层设置在所述第三图形层上，所述第二图形层设置在所述第一图形层上，所述第一图形层包括至少一条辅助金属线，所述第二图形层包括至少一条电源线，所述第三图形层包括呈阵列排布的多行多列第二电极，所述至少一条辅助金属线中的一条辅助金属线与所述多行多列第二电极中的一行第二电极相对设置并与该行第二电极中的至少一个第二电极部分地重叠以形成至少一个存储电容，并且该条辅助金属线通过过孔与所述至少一条电源线电连接。
根据本公开的实施例，所述辅助金属线与所述第二电极的重叠 部分的宽度大于所述辅助金属线的其余部分的宽度，并将该重叠部分作为所述存储电容的第一电极。
根据本公开的实施例，所述辅助金属线在与所述第二电极的相对位置处具有突出，并将该突出作为所述存储电容的第一电极。
根据本公开的实施例，所述至少一条电源线的延伸方向与所述多行多列第二电极的列方向平行，所述至少一条辅助金属线的延伸方向与所述多行多列第二电极的行方向平行，所述至少一条电源线的延伸方向与所述至少一条辅助金属线的延伸方向垂直。
根据本公开的实施例，所述第二图形层还包括多条数据线，所述第三图形层还包括多条栅线，所述至少一条电源线的延伸方向与所述多条数据线的延伸方向平行，所述至少一条辅助金属线的延伸方向与所述多条栅线的延伸方向平行。
根据本公开的实施例，所述第一图形层还包括与所述至少一条辅助金属线同层设置的至少一条复位信号线。
根据本公开的实施例，所述第一图形层还包括层间绝缘层，其设置在所述至少一条辅助金属线上，所述至少一条辅助金属线中的每一条辅助金属线通过设置在所述层间绝缘层中的过孔与所述至少一条电源线电连接。
根据本公开的实施例，所述第二图形层中的所述至少一条电源线和所述多条数据线设置在所述层间绝缘层上。
根据本公开的实施例，所述第三图形层还包括：第二栅绝缘层，其设置在所述多行多列第二电极以及所述多条栅线上，其上设置有所述至少一条辅助金属线。
根据本公开的实施例，该显示基板还包括，有源层，其设置在所述衬底上；以及第一栅绝缘层，其设置在所述有源层和裸露的衬底上，其上设置有所述多行多列第二电极以及所述多条栅线。
根据本公开的实施例，所述显示基板基于呈阵列排布的多行多列第二电极被划分为多个像素单元，所述至少一条辅助金属线包括多条辅助金属线，所述至少一条电源线包括多条电源线，所述多条辅助金属线通过过孔分别与所述多条电源线电连接，所述多条辅助金属线 分别与多行第二电极相对设置并与相应行第二电极中的每个第二电极部分地重叠以形成多个存储电容，所述多个像素单元中的每一个像素单元内均设置有像素电路和有机发光二极管，所述像素电路包括驱动晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、复位晶体管、补偿子电路和所述存储电容，所述存储电容的第二电极作为该存储电容所在的像素单元中的驱动晶体管的栅极，其中，所述驱动晶体管的源极与所述第一发光控制晶体管的漏极电连接，所述驱动晶体管的漏极与所述第二发光控制晶体管的源极电连接；所述第一发光控制晶体管的源极与所述多条电源线中的一条电源线电连接，所述第一发光控制晶体管的栅极与发光控制信号线电连接；所述第二发光控制晶体管的漏极与所述有机发光二极管的阳极电连接，所述第二发光控制晶体管的栅极与所述发光控制信号线电连接；所述复位晶体管的源极与所述复位信号线电连接，所述复位晶体管的漏极与所述驱动晶体管的栅极电连接，所述复位晶体管的栅极与复位控制信号线电连接；所述数据写入晶体管的源极与所述多条数据线中的一条数据线电连接，所述数据写入晶体管的漏极与所述驱动晶体管的源极电连接，所述数据写入晶体管的栅极与所述多条栅线中的一条栅线电连接，所述数据写入晶体管设置为该数据写入晶体管的源极与该数据写入晶体管的漏极在该数据写入晶体管的栅极接收到有效的控制信号时导通；所述补偿子电路的第一端与所述驱动晶体管的栅极电连接，所述补偿子电路的第二端与所述驱动晶体管的漏极电连接，所述补偿子电路的控制端与所述数据写入晶体管的栅极电连接，所述补偿子电路设置为在该补偿子电路的控制端接收到有效的控制信号时将所述驱动晶体管的漏极和所述驱动晶体管的栅极电连接，以使得所述存储电容存储所述驱动晶体管的阈值电压。
根据本公开的实施例，所述补偿子电路包括第一补偿晶体管和第二补偿晶体管，所述第一补偿晶体管的栅极与所述第二补偿晶体管的栅极电连接，并形成为所述补偿子电路的控制端；所述第一补偿晶体管的源极与所述第二补偿晶体管的漏极电连接，所述第一补偿晶体管的漏极作为所述补偿子电路的第二端而与所述驱动晶体管的漏极 电连接，所述第二补偿晶体管的源极作为所述补偿子电路的第一端而与所述驱动晶体管的栅极电连接。
根据本公开的实施例，该显示基板还包括形成在所述衬底上的缓冲层，所述有源层形成在所述缓冲层上。
根据本公开的实施例，所述衬底由聚氨酯材料制成，所述有源层由多晶硅材料制成，所述缓冲层由硅的氧化物和/或硅的氮化物制成。
根据本公开的实施例，提供了一种显示装置，其包括以上所述的显示基板。
根据本公开的实施例，提供了一种用于制作显示基板的方法，所述显示基板包括在衬底上依次设置的第三图形层、第一图形层和第二图形层，所述方法包括：形成所述第三图形层，包括：在所述衬底上形成呈阵列排布的多行多列第二电极；在裸露的衬底和所述多行多列第二电极上形成第二栅绝缘层，形成所述第一图形层，包括：在所述第二栅绝缘层上形成至少一条辅助金属线，并使得所述至少一条辅助金属线中的一条辅助金属线与所述多行多列第二电极中的一行第二电极相对设置并与该行第二电极中的至少一个第二电极部分地重叠以形成至少一个存储电容；在所述至少一条辅助金属线上形成层间绝缘层；在所述层间绝缘层中形成延伸至所述至少一条辅助金属线的过孔，形成所述第二图形层，包括：在所述层间绝缘层上形成至少一条电源线，并使得所述至少一条电源线通过所述层间绝缘层中的过孔与所述至少一条辅助金属线电连接。
根据本公开的实施例，在形成所述第三图形层之前，所述方法还包括：在所述衬底上形成有源层；在所述有源层和裸露的衬底上形成第一栅绝缘层，呈阵列排布的多行多列第二电极形成在所述第一栅绝缘层上，形成所述第一图形层还包括：在形成所述至少一条辅助金属线的同时，形成至少一条复位信号线。
根据本公开的实施例，所述显示基板基于呈阵列排布的所述多行多列第二电极被划分为多个像素单元，所述多个像素单元中的每一个像素单元包括像素电路和有机发光二极管，所述像素电路包括驱动 晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、复位晶体管、第一补偿晶体管、第二补偿晶体管和所述存储电容，其中，形成所述第三图形层还包括：在所述第一栅绝缘层上形成呈阵列排布的多行多列第二电极的同时，在所述第一栅绝缘层上形成所述数据写入晶体管的栅极、所述第一发光控制晶体管的栅极、所述第二发光控制晶体管的栅极、所述复位晶体管的栅极、所述第一补偿晶体管的栅极、所述第二补偿晶体管的栅极、多条栅线、发光控制信号线以及复位控制信号线，将所述存储电容的第二电极作为所述驱动晶体管的栅极，并使得所述数据写入晶体管的栅极、所述第一补偿晶体管的栅极和所述第二补偿晶体管的栅极均与所述多条栅线中的同一条栅线电连接，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极分别与所述发光控制信号线电连接；使用各晶体管的栅极和所述多行多列第二电极作为离子注入阻挡层，以对所述有源层进行离子掺杂，从而在未被所述离子注入阻挡层阻挡的有源层区域中形成各晶体管的源极区和漏极区，其中，所述驱动晶体管的源极区、所述第一发光控制晶体管的漏极区和所述数据写入晶体管的漏极区在所述有源层中形成为一体；所述驱动晶体管的漏极区、所述第二发光控制晶体管的源极区和所述第一补偿晶体管的漏极区形成为一体；所述复位晶体管的漏极区和所述第二补偿晶体管的源极区在所述有源层中形成为一体；所述第一补偿晶体管的源极区与所述第二补偿晶体管的漏极区在所述有源层中形成为一体。
根据本公开的实施例，形成所述第二图形层还包括：在所述层间绝缘层中形成分别延伸至所述第一发光控制晶体管的源极区、所述第二发光控制晶体管的漏极区、所述存储电容的第二极、所述数据写入晶体管的源极区、所述第二补偿晶体管的源极区、所述复位晶体管的源极区和所述复位信号线的过孔；在所述层间绝缘层上形成所述至少一条电源线的同时，形成所述第二发光控制晶体管的漏极、多条数据线、所述存储电容的第二极的过孔与所述第二补偿晶体管的源极区的过孔之间的电连接线以及所述复位晶体管的源极区的过孔与所述复位信号线的过孔之间的电连接线，并使得所述至少一条电源线中的 与所述至少一条辅助金属线中的一条辅助金属线电连接的电源线通过所述层间绝缘层中的过孔而与所述第一发光控制晶体管的源极区电连接。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是根据本公开的实施例的显示基板在有机发光二极管、驱动晶体管以及存储电容处的剖视图，并示出了辅助金属线与电源线的连接；
图2是根据本公开的实施例所提供的显示基板上的像素电路的示意图；
图3是根据本公开的实施例的显示基板在发光控制晶体管、驱动晶体管、存储电容处的剖视图；
图4是根据本公开的实施例的显示基板在复位晶体管、补偿晶体管和驱动晶体管处的剖视图；
图5A至图5K是根据本公开的实施例的制造本公开所提供的显示基板的制造方法中的各个步骤获得的结构的示意图；
图6是根据本公开的实施例的制作显示基板的方法的流程图；
图7是根据本公开的实施例的制作显示基板的方法的示例流程图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
目前，显示装置在进行显示时，其上不同像素单元可能会发光不均匀，影响显示效果。因此，如何提高各个像素单元发光的均匀性成为本领域亟待解决的技术问题。
本公开的发明人反复研究发现，显示装置在显示时出现发光不均匀的一个原因如下。通过电源线向每个像素单元内的像素电路提供高电平电压信号并且电源线存在内阻，因此，在传递高电平电压信号的过程中，电源线的电阻压降(IR Drop)会导致各个像素单元接收到的高电平电压信号不同，从而使得各个像素单元发光不均匀，降低了显示效果。
有鉴于此，本公开提供了一种显示基板，所述显示基板包括衬底以及在所述衬底上设置的第一图形层、第二图形层和第三图形层。如图1所示为沿图5K中的线a-a’截取的剖视图，第三图形层13设置在衬底100上，第一图形层11设置在第三图形层13上，第二图形层12设置在第一图形层上11。所述第一图形层11包括至少一条辅助金属线210，所述第二图形层12包括至少一条电源线110，至少一条辅助金属线210通过过孔与至少一条电源线110电连接，第三图形层13包括呈阵列排布的多行多列第二电极320。
至少一条辅助金属线210的一条辅助金属线与多行多列第二电极中的一行第二电极相对设置并与该行第二电极中的至少一个第二电极部分地重叠以形成至少一个存储电容Cst，并且该条辅助金属线210通过过孔与至少一条电源线110电连接。
基于呈阵列排布的多行多列第二电极320可将显示基板划分为呈阵列排布的多个像素单元。每列像素单元可对应一条电源线，因此，至少一条电源线的条数可以与像素单元的列数相同。同理，至少一条辅助金属线的条数可以与像素单元的行数相同。
至少一条电源线110与至少一条辅助金属线210彼此电连接，等同于增加了电源线的横截面积，使得两者的组合结构的电阻小于电源线110本身的电阻。
在包括所述显示基板的显示装置进行显示时，将电源线110与直流电源电连接，并经由电源线110和辅助金属线210的组合结构向显示基板提供高电平电压。由于上述组合结构的电阻小于电源线110的电阻，因此，与仅通过电源线传递高电平电压的相关技术相比，在包括本公开所提供的显示基板的显示装置进行显示时，信号传递过程 中的电阻压降(IR Drop)更小，从而可以使得不同的像素单元所接收到的高电平信号之间的差别缩小，进而提高了显示的均匀性。
为了进一步地提高信号传递过程中的均匀性，在一些实施例中，至少一条电源线110的延伸方向与至少一条辅助金属线210的延伸方向垂直。在一个具体实施例中，多条电源线110与多条辅助金属线210在所述显示基板上的正投影形成网格。
在本公开中，当所述显示基板为有机发光二极管显示基板时，电源线110通常通过高电平信号端ELVDD而与发光控制晶体管的源极电连接。而对于像素电路而言，不同的晶体管的源极、漏极以及数据线通常设置在同一层，因此，为了简化制造工艺、并降低显示基板的厚度，在一些实施例中，可以将电源线110与数据线同层设置。即，所述第二图形层12还包括多条数据线。为了避免电源线110与数据线之间产生短路，在一些实施例中，至少一条电源线110的延伸方向与多行多列第二电极的列方向平行，至少一条辅助金属线210的延伸方向与多行多列第二电极的行方向平行，至少一条电源线110的延伸方向与至少一条辅助金属线210的延伸方向垂直。
如图1所示，在一些实施例中，第一图形层11还包括层间绝缘层400，其设置在至少一条辅助金属线210之上，至少一条辅助金属线210中的每一条辅助金属线通过设置在层间绝缘层400中的过孔分别与至少一条电源线110电连接。
如图1所示，在一些实施例中，第二图形层12中的至少一条电源线110和多条数据线设置在层间绝缘层400上。
如图1所示，在一些实施例中，第三图形层13还包括第二栅绝缘层420，其设置在多行多列第二电极320以及多条栅线上，其上设置有至少一条辅助金属线210。
如图1所示，在一些实施例中，该显示基板还包括有源层500和第一栅绝缘层410。有源层500设置在衬底100上。第一栅绝缘层410设置在有源层500和裸露的衬底100上。第一栅绝缘层410上设置有多行多列第二电极320以及多条栅线GATE。
对于包括有机发光二极管的显示基板而言，该显示基板包括多 个像素单元，每个像素单元都包括有机发光二极管和像素电路，所述像素电路用于驱动所述有机发光二极管发光。相应地，如图2所示，所述像素电路包括驱动晶体管T1和存储电容Cst。驱动晶体管T1用于产生驱动电流，而存储电容Cst则是为了存储数据电压和驱动晶体管T1的阈值电压。需要解释的是，存储驱动晶体管T1的阈值电压的目的是为了在驱动有机发光二极管发光时，对驱动晶体管T1的阈值电压进行补偿，防止驱动晶体管T1的阈值电压对有机发光二极管的发光造成影响。
为了存储驱动晶体管T1的阈值电压，存储电容Cst的第一电极通过辅助金属线210与电源线110电连接，存储电容Cst的第二电极与驱动晶体管T1的栅极电连接。为了降低所述显示基板的厚度，在一些实施例中，可以将辅助金属线210的一部分作为存储电容Cst的第一电极(在图5E中所示的实施方式中，辅助金属线210可以在与存储电容Cst的第二电极的相对位置处突出，并将该突出作为存储电容Cst的第一电极220)。即，辅助金属线210与第二电极重叠部分的部分大于辅助金属线210的其余部分的宽度。
在像素电路中，存储电容Cst用于存储数据电压以及驱动晶体管T1的阈值电压，因此，通常，存储电容Cst的第二电极320与驱动晶体管T1的栅极电连接。为了简化制造工艺，在一些实施例中，可以将存储电容Cst的第二电极320作为驱动晶体管T1的栅极，如图5E所示。为了便于制造，所述显示基板中各个晶体管的栅极以及多条栅线均位于第三图形层13中。
图2中所示的是像素电路的示意图，该像素电路中的各晶体管在显示基板上的位置关系如图5G所示。具体地，该像素电路除了包括上述的驱动晶体管T1和存储电容Cst之外，还包括数据写入晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、复位晶体管T4和补偿子电路。如上所述，存储电容Cst的第二电极320可作为该存储电容所在的像素单元中的驱动晶体管T1的栅极，则无需设置驱动晶体管T1的栅极。
如图2中所示，驱动晶体管T1的源极与第一发光控制晶体管 T5的漏极电连接，驱动晶体管T1的栅极与存储电容Cst的第二电极320电连接，驱动晶体管T1的漏极与第二发光控制晶体管T6的源极电连接。
第一发光控制晶体管T5的源极通过高电平信号端ELVDD与至少一条电源线中110的一条电源线电连接，第一发光控制晶体管T5的栅极通过端口Eln与发光控制信号线EMn电连接。
第二发光控制晶体管T6的漏极与有机发光二极管OLED的阳极电连接，第二发光控制晶体管T6的栅极通过端口Eln与所述发光控制信号线EMn电连接。
复位晶体管T4的源极通过复位信号端ELVINT而与复位信号线VINT电连接，复位晶体管T4的漏极与驱动晶体管T1的栅极电连接，复位晶体管T4的栅极通过复位信号控制端SLn-1而与复位控制信号线RESET电连接。复位晶体管T4的栅极接收到有效的复位控制信号时，该复位晶体管的源极和该复位晶体管的漏极导通，从而将驱动晶体管T1的栅极与复位信号线VINT导通，并对驱动晶体管T1的栅极和存储电容Cst进行复位。
数据写入晶体管T2的源极通过数据信号写入端DLm而与多条数据线中的一条数据线DATA电连接，数据写入晶体管T2的漏极与驱动晶体管T1的源极电连接，数据写入晶体管T2的栅极通过数据写入控制信号端SLn而与多条栅线中的一条栅线GATE电连接。数据写入晶体管T2设置为该数据写入晶体管T2的源极与该数据写入晶体管T2的漏极在该数据写入晶体管T2的栅极接收到有效的控制信号时导通，从而将通过数据信号写入端写入的数据电压写入存储电容Cst。
所述补偿子电路的第一端与驱动晶体管T1的栅极电连接，补偿子电路的第二端与驱动晶体管T1的漏极电连接，补偿子电路的控制端与数据写入晶体管T2的栅极电连接。补偿子电路可以在该补偿子电路的控制端接收到有效的控制信号时将驱动晶体管T1的栅极和漏极电连接，以便于存储电容Cst存储驱动晶体管T1的阈值电压。
在本公开中，对所述补偿子电路的具体结构不做特殊限定，如 图2中所示，所述补偿子电路可包括第一补偿晶体管T3和第二补偿晶体管T7。第一补偿晶体管T3的源极与第二补偿晶体管T7的漏极电连接，第一补偿晶体管T3的漏极作为补偿子电路的第二端而与第二发光控制晶体管T6的源极电连接。第二补偿晶体管T7的源极作为补偿子电路的第一端与驱动晶体管T1的栅极电连接。第一补偿晶体管T3的栅极与第二补偿晶体管T7的栅极电连接，并形成为补偿子电路的控制端。
在图2中所示的实施方式中，第一补偿晶体管T3的栅极以及第二补偿晶体管T7的栅极均与数据写入晶体管T2的栅极电连接，也就说，可以利用同一条栅线控制数据写入晶体管T2、第一补偿晶体管T3以及第二补偿晶体管T7。
作为一种实施方式，驱动晶体管T1的栅极、数据写入晶体管T2的栅极、第一发光控制晶体管T5的栅极、第二发光控制晶体管T6的栅极、复位晶体管T4的栅极、第一补偿晶体管T3的栅极、第二补偿晶体管T7的栅极同层(第三图形层13)设置。
如图3所示为沿图5K中的线b-b’截取的剖视图，在图3中所示的剖视图中，剖切了第一发光控制晶体管T5的一部分、存储电容Cst的一部分和第二发光控制晶体管T6的一部分。如图4所示为沿图5K中的线c-c’截取的剖视图，在图4中所示的剖视图中，剖切了复位晶体管T4的一部分、第一补偿晶体管T3和第二补偿晶体管T7的一部分和驱动晶体管T1的一部分。
为了便于制造，在所述像素电路中，不同晶体管的有源层均形成在同一层中。所述像素电路的有源层形成在衬底上，为了防止衬底表面的杂质向有源层500扩散，在一些实施例中，还可以在衬底和有源层500之间设置缓冲层600。
在本公开中，对衬底的具体材料不做特殊的限制，例如，衬底可以为玻璃衬底，也可以为由聚氨酯材料制成的柔性衬底。可以利用硅的氧化物(SiOx)或者硅的氮化物(SiNx)制成缓冲层600。
在图1、图3和图4中所示的实施方式中，所述显示基板中的各个晶体管(包括第一发光控制晶体管T5、第二发光控制晶体管T6、 复位晶体管T4、驱动晶体管T1、第一补偿晶体管T3和第二补偿晶体管体T7)为顶栅型的晶体管。所述第三图形层13位于第一栅绝缘层410上方，并且，所述第一图形层11位于所述第三图形层13上方，第二图形层12位于第一图形层11成上方。但是，本公开并不限于此，各个晶体管也可以为底栅型晶体管。
如图1所示，在一个实施例中，衬底100可由聚氨酯材料制成，有源层500可由多晶硅材料制成，缓冲层600可由硅的氧化物和/或硅的氮化物制成。
如图3所示，在一些实施例中，该显示基板还包括钝化层700，其设置在第二图形层12上并具有延伸至第二发光控制晶体管T6的漏极A的过孔。该显示基板还包括平坦化层800，其设置在钝化层700上，具有延伸至钝化层700的过孔的过孔，即平坦化层800的过孔与钝化层700的过孔在垂直衬底的方向上同轴。该显示基板还包括像素电极900，其设置在平坦化层800上，并通过钝化层700的过孔和平坦化层800中的过孔而与第二发光控制晶体管T6的漏极A电连接。该显示基板还包括有机发光二极管，其设置在像素电极900上。
钝化层700可由硅的氮化物制成。平坦化层800可由聚氨酯材料制成。
作为本公开的第二个方面，提供一种显示装置，所述显示装置包括显示基板，其中，所述显示基板为本公开所提供的上述显示基板。
如上文中所述，在所述显示基板中，利用具有较小电阻的电源线与辅助金属线的组合结构来向各个像素单元提供高电平信号，可以降低高电平信号在传输过程中的电阻压降，使得各个像素单元接收到的信号更加接近，从而使得各个像素单元的亮度更加均匀，并提高显示装置的显示效果。
在本公开中，对显示装置的具体应用不做特殊的要求，例如，所述显示装置可以是可穿戴设备，也可以是平板电脑、导航仪等电子设备。
下面介绍本公开所提供的显示基板的制造方法，其中，所述制造方法包括在衬底上依次形成第三图形层、第一图形层和第二图形 层，如图6所示。形成第三图形层包括S1和S2步骤，其中，在步骤S1中，在衬底上形成呈阵列排布的多行多列第二电极；在步骤S2中，在裸露的衬底和多行多列第二电极上形成第二栅绝缘层。形成第一图形层包括S3和S5步骤，其中，在步骤S3中，在第二栅绝缘层上形成至少一条辅助金属线，并使得至少一条辅助金属线分别对应各第二电极行设置并与第二电极行中的至少一个第二电极部分地重叠以形成至少一个存储电容；在步骤S4中，在至少一条辅助金属线上形成层间绝缘层；在步骤S5中，在层间绝缘层中形成延伸至至少一条辅助金属线的过孔。形成第二图形层包括S6步骤，其中，在步骤S6中，在层间绝缘层上形成至少一条电源线，并使得至少一条电源线通过层间绝缘层中的过孔与至少一条辅助金属线电连接。
下面结合图5A至图5K、以及图7介绍制造图1至图4中显示基板的制造方法。
在S101中，提供衬底100。衬底可由聚氨酯材料制成。
在S102中，在衬底上形成缓冲层600(如图5B所示)。通过等离子体增强化学气相沉积(PECVD)，在整个衬底100上依次沉积氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜，形成包括氮化硅和二氧化硅的缓冲层600。
在S103中，在缓冲层600上形成非晶硅层。利用PECVD或者其它化学或物理气相沉积方法在缓冲层600上形成非晶硅(a-Si)层。
在S104中，通过激光退火(ELA)或者固相结晶(SPC)方法使得非晶硅层结晶以形成多晶硅层。
在S105中，在多晶硅层上形成第一光刻胶图案，以第一光刻胶图案为刻蚀阻挡层，通过等离子体刻蚀没有被第一光刻胶图案保护的多晶硅层，形成有源层500。图5A所示为具有有源层500的显示基板的俯视图(透光层未示出)，图5B所示为沿图5A的线d-d’截取的剖视图。利用离子注入工艺对多晶硅有源层500中的晶体管沟道进行低浓度离子掺杂，以在多晶硅有源层500中形成薄膜晶体管要求的导电沟道。
在S106中，沉积二氧化硅或二氧化硅与氮化硅，以获得第一栅 绝缘层410。通过光刻胶剥离工艺去除多晶硅有源层500上的光刻胶，使用PECVD沉积SiO2或SiO2与SiN，在多晶硅有源层以及整个缓冲层上形成第一栅绝缘层410。
在S107中，通过磁控溅射等物理气相沉积方法在第一栅绝缘层410上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极图形层，该栅极图形层包括发光控制信号线EMn、多条栅线GATE、多条复位控制信号线RESET、各晶体管的栅极(未示出，包括图2中数据写入晶体管T2的栅极、第一发光控制晶体管T5的栅极、第二发光控制晶体管T6的栅极、复位晶体管的栅极、第一补偿晶体管T3的栅极、第二补偿晶体管T7的栅极)和多行多列第二电极320(同时用作驱动晶体管T1的栅极)。图5C所示为具有第二电极320、发光控制信号线EMn、多条栅线GATE、复位控制信号线RESET的俯视图，将第二电极320作为驱动晶体管T1的栅极，并使得数据写入晶体管T2的栅极、第一补偿晶体管T3的栅极和第二补偿晶体管T7的栅极均通过数据写入控制信号端SLn而与多条栅线中的同一条栅线GATE电连接，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极通过对应的发光控制信号控制端ELn而分别与发光控制信号线EMn电连接。图5D所示为沿图5C的线e-e’截取的剖面图。其中，该栅极图形层可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
在S108中，使用所述栅极图形层中的栅极和第二电极320作为离子注入阻挡层，对有源层500进行离子掺杂，在未被栅极阻挡的多晶硅有源层区域形成低阻抗的源极区和漏极区。基于图5A的有源层500的结构，通过离子掺杂，可以使得驱动晶体管T1的源极区、第一发光控制晶体管T5的漏极区和数据写入晶体管T2的漏极区在有源层500中形成为一体，驱动晶体管T1的漏极区、第二发光控制晶体管T6的源极区和第一补偿晶体管T3的漏极区在有源层500中形成为一体，复位晶体管T4的漏极区和第一补偿晶体管T3的源极区在有源层500中形成为一体，第一补偿晶体管T3的源极区与第二补偿晶体管T7的漏极区在有源层500中形成为一体。有源层500中的 源极区和漏极区分别等同于相应晶体管的源极和/或漏极，各晶体管通过源漏极区连接则无需设置对应的源漏极。
在S109中，形成第二栅绝缘层420。在包含栅极图形层的整个表面，使用PECVD工艺依次沉积SiO2薄膜和SiN薄膜以形成第二栅绝缘层420。
在S110中，在第二栅绝缘层420上形成多条辅助金属线210和多条复位信号线VINT。多条辅助金属线210中的每一条在与第二电极320的相对位置处具有突出，并将该突出作为存储电容的第一电极220。图5E所示为具有辅助金属线210和复位信号线VINT的俯视图，图5F为所示为沿图5E的线f-f’截取的剖视图。
在S111中，依次沉积二氧化硅薄膜和氮化硅薄膜形成层间绝缘层400，通过掩模和刻蚀工艺刻蚀层间绝缘层400而形成分别延伸至第一发光控制晶体管T5的源极区、第二发光控制晶体管T6的漏极区、存储电容的第一电极220和第二电极320、数据写入晶体管T2的源极区、第二补偿晶体管T7的源极区、复位晶体管T4的源极区和复位信号线VINT的过孔，如图5G所示。图5H为沿图5G的线g-g’截取的剖视图，其示出延伸至存储电容的第一电极220的过孔和延伸至第一发光控制晶体管T5的源极区的过孔。
在S112中，在层间绝缘层400上形成多条电源线110、多条数据线DATA、第二发光控制晶体管T6的漏极A、存储电容的第二电极320的过孔与第二补偿晶体管T7的源极区的过孔之间的电连接线310以及复位晶体管T4的源极区的过孔与复位信号线VINT的过孔之间的电连接线330。通过磁控溅射工艺在层间绝缘层400上沉积一种或多种低电阻的金属薄膜，通过掩模和刻蚀工艺形成多条电源线110、多条数据线DATA以及第二发光控制晶体管T6的漏极A，并使得多条电源线110中的与多条辅助金属线210中的一条辅助金属线电连接的电源线通过过孔与第一发光控制晶体管T5的源极电连接，多条数据线DATA中的一条数据线通过过孔与数据写入晶体管T2的源极区电连接，存储电容的第二电极320与第二补偿晶体管T7的源极区通过电连接线电连接，复位晶体管T4的源极区与复位信号线 VINT通过电连接线电连接。用于形成多条电源线110、多条数据线DATA、第二发光控制晶体管T6的漏极A、存储电容的第二电极320的过孔与第二补偿晶体管T7的源极区的过孔之间的电连接线以及复位晶体管T4的源极区的过孔与复位信号线VINT的过孔之间的电连接线的金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。图5I所示为具有电源线110、数据线DATA以及第二发光控制晶体管T6的漏极A的俯视图，图5J为所示为沿图5I的线h-h’截取的剖视图。
在S113中，使用快速热退火或热处理炉退火，激活有源层500中掺杂的离子，使得在栅极之下的有源层500中形成有效的导电沟道；
在S114中，在包括电源线110、数据线DATA以及第二发光控制晶体管T6的漏极A的整个表面沉积一层氮化硅薄膜，通过掩模和刻蚀工艺形成包含有机发光二极管的阳极过孔的钝化层700。该钝化层700上的过孔延伸至第二发光控制晶体管T6的漏极A。
在S115中，使用快速热退火或热处理炉退火进行氢化工艺，修复有源层500内部和界面的缺陷。
在S116中，再一次通过掩模工艺，在钝化层700之上形成具有与阳极过孔具有相同竖直轴的过孔的有机平坦化层800，以填充器件表面的低凹形成平坦表面。并且平坦化层800中的过孔延伸至钝化层700中的过孔。
在S117中，使用磁控溅射在有机平坦化层800上沉积一层透明导电薄膜，通过光刻工艺刻蚀该透明导电薄膜，在有机平坦化层800的过孔及部分有机平坦化层800之上形成像素区域的像素电极900，如图5K所示。然后在裸露的有机平坦化层及像素电极上涂覆一层与有机平坦化层类似的光敏有机材料，通过最后一道掩模工艺暴露出像素电极的部分区域，形成像素定义层1000。像素定义层覆盖有机平坦化层及部分的像素电极区域。该透明导电薄膜可以是单层的氧化物导电薄膜，如ITO或IZO等，也可以是ITO/Ag/ITO、IZO/Ag等复合薄膜。
通过8次至9次掩膜工艺即可获得本公开所提供的显示基板。得到本公开所提供的显示基板后，还可以在显示基板上形成有机发光二极管的各个功能层，并对显示基板进行封装，可以获得显示面板。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种显示基板，包括：
    衬底；以及
    在所述衬底上设置的第一图形层、第二图形层和第三图形层，
    其中，
    所述第三图形层设置在所述衬底上，所述第一图形层设置在所述第三图形层上，所述第二图形层设置在所述第一图形层上，
    所述第一图形层包括至少一条辅助金属线，所述第二图形层包括至少一条电源线，所述第三图形层包括呈阵列排布的多行多列第二电极，
    所述至少一条辅助金属线中的一条辅助金属线与所述多行多列第二电极中的一行第二电极相对设置并与该行第二电极中的至少一个第二电极部分地重叠以形成至少一个存储电容，并且该条辅助金属线通过过孔与所述至少一条电源线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述辅助金属线与所述第二电极的重叠部分的宽度大于所述辅助金属线的其余部分的宽度，并将该重叠部分作为所述存储电容的第一电极。
  3. 根据权利要求2所述的显示基板，其中，所述辅助金属线在与所述第二电极的相对位置处具有突出，并将该突出作为所述存储电容的第一电极。
  4. 根据权利要求3所述的显示基板，其中，所述至少一条电源线的延伸方向与所述多行多列第二电极的列方向平行，所述至少一条辅助金属线的延伸方向与所述多行多列第二电极的行方向平行，所述至少一条电源线的延伸方向与所述至少一条辅助金属线的延伸方向垂直。
  5. 根据权利要求1-4中任一项所述的显示基板，其中，所述第二图形层还包括多条数据线，所述第三图形层还包括多条栅线，所述至少一条电源线的延伸方向与所述多条数据线的延伸方向平行，所述至少一条辅助金属线的延伸方向与所述多条栅线的延伸方向平行。
  6. 根据权利要求5所述的显示基板，其中，所述第一图形层还包括与所述至少一条辅助金属线同层设置的至少一条复位信号线。
  7. 根据权利要求6所述的显示基板，其中，所述第一图形层还包括层间绝缘层，其设置在所述至少一条辅助金属线上，所述至少一条辅助金属线中的每一条辅助金属线通过设置在所述层间绝缘层中的过孔与所述至少一条电源线电连接。
  8. 根据权利要求7所述的显示基板，其中，所述第二图形层中的所述至少一条电源线和所述多条数据线设置在所述层间绝缘层上。
  9. 根据权利要求8所述的显示基板，其中，所述第三图形层还包括：
    第二栅绝缘层，其设置在所述多行多列第二电极以及所述多条栅线上，其上设置有所述至少一条辅助金属线。
  10. 根据权利要求9所述的显示基板，还包括，
    有源层，其设置在所述衬底上；以及
    第一栅绝缘层，其设置在所述有源层和裸露的衬底上，其上设置有所述多行多列第二电极以及所述多条栅线。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板基于呈阵列排布的多行多列第二电极被划分为多个像素单元，所述至少一条辅助金属线包括多条辅助金属线，所述至少一条电源线包括多条电源线，所述多条辅助金属线通过过孔分别与所述多条电源线电连 接，所述多条辅助金属线分别与多行第二电极相对设置并与相应行第二电极中的每个第二电极部分地重叠以形成多个存储电容，
    所述多个像素单元中的每一个像素单元内均设置有像素电路和有机发光二极管，所述像素电路包括驱动晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、复位晶体管、补偿子电路和所述存储电容，所述存储电容的第二电极作为该存储电容所在的像素单元中的驱动晶体管的栅极，其中，
    所述驱动晶体管的源极与所述第一发光控制晶体管的漏极电连接，所述驱动晶体管的漏极与所述第二发光控制晶体管的源极电连接；
    所述第一发光控制晶体管的源极与所述多条电源线中的一条电源线电连接，所述第一发光控制晶体管的栅极与发光控制信号线电连接；
    所述第二发光控制晶体管的漏极与所述有机发光二极管的阳极电连接，所述第二发光控制晶体管的栅极与所述发光控制信号线电连接；
    所述复位晶体管的源极与所述复位信号线电连接，所述复位晶体管的漏极与所述驱动晶体管的栅极电连接，所述复位晶体管的栅极与复位控制信号线电连接；
    所述数据写入晶体管的源极与所述多条数据线中的一条数据线电连接，所述数据写入晶体管的漏极与所述驱动晶体管的源极电连接，所述数据写入晶体管的栅极与所述多条栅线中的一条栅线电连接，所述数据写入晶体管设置为该数据写入晶体管的源极与该数据写入晶体管的漏极在该数据写入晶体管的栅极接收到有效的控制信号时导通；
    所述补偿子电路的第一端与所述驱动晶体管的栅极电连接，所述补偿子电路的第二端与所述驱动晶体管的漏极电连接，所述补偿子电路的控制端与所述数据写入晶体管的栅极电连接，所述补偿子电路设置为在该补偿子电路的控制端接收到有效的控制信号时将所述驱动晶体管的漏极和所述驱动晶体管的栅极电连接，以使得所述存储电 容存储所述驱动晶体管的阈值电压。
  12. 根据权利要求11所述的显示基板，其中，所述补偿子电路包括第一补偿晶体管和第二补偿晶体管，
    所述第一补偿晶体管的栅极与所述第二补偿晶体管的栅极电连接，并形成为所述补偿子电路的控制端；
    所述第一补偿晶体管的源极与所述第二补偿晶体管的漏极电连接，所述第一补偿晶体管的漏极作为所述补偿子电路的第二端而与所述驱动晶体管的漏极电连接，所述第二补偿晶体管的源极作为所述补偿子电路的第一端而与所述驱动晶体管的栅极电连接。
  13. 根据权利要求12所述的显示基板，还包括形成在所述衬底上的缓冲层，所述有源层形成在所述缓冲层上。
  14. 根据权利要求13所述的显示基板，其中，所述衬底由聚氨酯材料制成，所述有源层由多晶硅材料制成，所述缓冲层由硅的氧化物和/或硅的氮化物制成。
  15. 一种显示装置，包括权利要求1至14中任一项所述的显示基板。
  16. 一种用于制作显示基板的方法，所述显示基板包括在衬底上依次设置的第三图形层、第一图形层和第二图形层，所述方法包括：
    形成所述第三图形层，包括：
    在所述衬底上形成呈阵列排布的多行多列第二电极；
    在裸露的衬底和所述多行多列第二电极上形成第二栅绝缘层，
    形成所述第一图形层，包括：
    在所述第二栅绝缘层上形成至少一条辅助金属线，并使得所述至少一条辅助金属线中的一条辅助金属线与所述多行多列第二电极中的一行第二电极相对设置并与该行第二电极中的至少一个第二电 极部分地重叠以形成至少一个存储电容；
    在所述至少一条辅助金属线上形成层间绝缘层；
    在所述层间绝缘层中形成延伸至所述至少一条辅助金属线的过孔，
    形成所述第二图形层，包括：
    在所述层间绝缘层上形成至少一条电源线，并使得所述至少一条电源线通过所述层间绝缘层中的过孔与所述至少一条辅助金属线电连接。
  17. 根据权利要求16所述的方法，其中，
    在形成所述第三图形层之前，所述方法还包括：
    在所述衬底上形成有源层；
    在所述有源层和裸露的衬底上形成第一栅绝缘层，呈阵列排布的多行多列第二电极形成在所述第一栅绝缘层上，
    形成所述第一图形层还包括：
    在形成所述至少一条辅助金属线的同时，形成至少一条复位信号线。
  18. 根据权利要求17所述的方法，其中，所述显示基板基于呈阵列排布的所述多行多列第二电极被划分为多个像素单元，所述多个像素单元中的每一个像素单元包括像素电路和有机发光二极管，所述像素电路包括驱动晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、复位晶体管、第一补偿晶体管、第二补偿晶体管和所述存储电容，
    其中，形成所述第三图形层还包括：
    在所述第一栅绝缘层上形成呈阵列排布的多行多列第二电极的同时，在所述第一栅绝缘层上形成所述数据写入晶体管的栅极、所述第一发光控制晶体管的栅极、所述第二发光控制晶体管的栅极、所述复位晶体管的栅极、所述第一补偿晶体管的栅极、所述第二补偿晶体管的栅极、多条栅线、发光控制信号线以及复位控制信号线，将所述 存储电容的第二电极作为所述驱动晶体管的栅极，并使得所述数据写入晶体管的栅极、所述第一补偿晶体管的栅极和所述第二补偿晶体管的栅极均与所述多条栅线中的同一条栅线电连接，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极分别与所述发光控制信号线电连接；
    使用各晶体管的栅极和所述多行多列第二电极作为离子注入阻挡层，以对所述有源层进行离子掺杂，从而在未被所述离子注入阻挡层阻挡的有源层区域中形成各晶体管的源极区和漏极区，
    其中，所述驱动晶体管的源极区、所述第一发光控制晶体管的漏极区和所述数据写入晶体管的漏极区在所述有源层中形成为一体；
    所述驱动晶体管的漏极区、所述第二发光控制晶体管的源极区和所述第一补偿晶体管的漏极区形成为一体；
    所述复位晶体管的漏极区和所述第二补偿晶体管的源极区在所述有源层中形成为一体；
    所述第一补偿晶体管的源极区与所述第二补偿晶体管的漏极区在所述有源层中形成为一体。
  19. 根据权利要求18所述的方法，其中，形成所述第二图形层还包括：
    在所述层间绝缘层中形成分别延伸至所述第一发光控制晶体管的源极区、所述第二发光控制晶体管的漏极区、所述存储电容的第二极、所述数据写入晶体管的源极区、所述第二补偿晶体管的源极区、所述复位晶体管的源极区和所述复位信号线的过孔；
    在所述层间绝缘层上形成所述至少一条电源线的同时，形成所述第二发光控制晶体管的漏极、多条数据线、所述存储电容的第二极的过孔与所述第二补偿晶体管的源极区的过孔之间的电连接线以及所述复位晶体管的源极区的过孔与所述复位信号线的过孔之间的电连接线，并使得所述至少一条电源线中的与所述至少一条辅助金属线中的一条辅助金属线电连接的电源线通过所述层间绝缘层中的过孔而与所述第一发光控制晶体管的源极区电连接。
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