WO2021189484A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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WO2021189484A1
WO2021189484A1 PCT/CN2020/081856 CN2020081856W WO2021189484A1 WO 2021189484 A1 WO2021189484 A1 WO 2021189484A1 CN 2020081856 W CN2020081856 W CN 2020081856W WO 2021189484 A1 WO2021189484 A1 WO 2021189484A1
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Prior art keywords
layer
silicon
display
color
alignment mark
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PCT/CN2020/081856
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English (en)
French (fr)
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WO2021189484A9 (zh
Inventor
李云龙
卢鹏程
敖雨
朱志坚
田元兰
张大成
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京东方科技集团股份有限公司
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Priority to PCT/CN2020/081856 priority Critical patent/WO2021189484A1/zh
Priority to GB2208249.9A priority patent/GB2606871A/en
Priority to US17/260,562 priority patent/US11968879B2/en
Priority to CN202080000418.6A priority patent/CN113748534B/zh
Publication of WO2021189484A1 publication Critical patent/WO2021189484A1/zh
Publication of WO2021189484A9 publication Critical patent/WO2021189484A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/19—Tandem OLEDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • Micro-Organic Light-Emitting Diode is a micro-display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize the active addressing of pixels, but also can realize the preparation of timing control (TCON) circuits and over-current protection (OCP) circuits on a silicon-based substrate, which is beneficial to reduce the size of the system. Realize lightweight. Silicon-based OLEDs are fabricated using mature complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) integrated circuit technology. They have the advantages of small size, high resolution (PPI), high refresh rate, etc., and are widely used in virtual reality (Virtual Reality, VR) or augmented reality (Augmented Reality, AR) near the eye display field.
  • CMOS complementary metal oxide semiconductor
  • the bonding machine In the manufacturing process of the silicon-based OLED micro-display panel, in order for the bonding machine to bind accurately and stably, it is necessary to set the first alignment mark for the bonding machine to align at the corresponding position of the substrate. Since the first alignment mark is generally made of anode layer metal or reflective layer metal, not only a certain distance between the first alignment mark and other metal traces needs to be maintained, but also between the first alignment mark and other metal traces. It is easy to form a metal-insulator-metal (Metal-insulator-Metal, MIM) capacitance effect, causing defects such as electrical breakdown.
  • MIM metal-insulator-metal
  • the distance between the first alignment mark and the upper edge of the bonding pad must be greater than or equal to the preset minimum spacing, that is, the first alignment mark increases the substrate
  • the border area affects the cutting efficiency of the entire motherboard.
  • the embodiment of the present disclosure provides a display substrate, including: a silicon-based substrate and a color filter layer disposed on the silicon-based substrate; A plurality of metal traces connected to the bonding area, the color film layer includes a first alignment mark; the first alignment mark is a hollow structure; the first alignment mark is on the silicon-based substrate.
  • the projection of and the projection of the metal trace on the silicon-based substrate include overlapping areas.
  • the color film layer of the display area includes a first color unit, a second color unit, and a third color unit arranged in an array; the color film layer outside the display area includes a whole At least one of the first color unit, the second color unit, and the third color unit of the surface structure.
  • the color film layer outside the display area includes a first color unit layer and a second color unit layer that are sequentially stacked on top of the first color unit layer and the second color unit layer. It includes mutually penetrating openings to form the first alignment mark through the openings.
  • the first color unit layer is a blue filter unit layer
  • the second color unit layer is a red filter unit layer
  • the length of the first alignment mark is 50 to 150 microns
  • the width of the first alignment mark is 20 to 50 microns
  • the width of the metal trace is 50 to 150 nanometers.
  • the interval between adjacent metal traces is 30 to 50 nanometers.
  • the ratio of the area of the metal trace exposed by the first alignment mark to the area of the first alignment mark is greater than or equal to 80%.
  • the display area includes a light-emitting structure layer disposed on a silicon-based substrate, and the light-emitting structure layer includes a reflective layer, an anode layer, an organic light-emitting layer, and a cathode layer that are sequentially stacked;
  • the silicon-based substrate of the display area is provided with a driving circuit layer.
  • the driving circuit layer includes a first scan line, a first power line, a data line, a switching transistor, and a driving transistor.
  • the control electrode of the switching transistor and the first The scan line is connected, the first pole of the switch transistor is connected to the data line, the second pole of the switch transistor is connected to the control electrode of the drive transistor, and the first pole of the drive transistor is connected to the first power line.
  • the switching transistor is configured to receive the data signal transmitted by the data line under the control of the first scan signal output by the first scan line, so that the control electrode of the driving transistor receives the data signal, and the driving transistor is configured to be at its control electrode. Under the control of the received data signal, a corresponding current is generated at the second pole; the metal wiring and the driving circuit layer are arranged in the same layer.
  • the cathode ring includes a power supply electrode layer provided on a silicon-based substrate, a reflective layer provided on a side of the power supply electrode layer away from the silicon-based substrate, and a reflective layer provided on the reflective layer away from the silicon-based substrate.
  • the anode layer on the side of the power supply electrode layer and the cathode layer arranged on the side of the anode layer away from the reflective layer.
  • the bonding area includes a bonding electrode layer disposed on the silicon-based substrate and an insulating layer covering the bonding electrode layer, and the insulating layer is provided with exposed bonding electrodes. Bonding electrode vias in the layer.
  • the bonding area further includes a second alignment mark layer provided on the silicon-based substrate, and the second alignment mark layer and the bonding electrode layer are provided in the same layer. .
  • An embodiment of the present disclosure also provides a display device, including: the display substrate as described in any one of the preceding items.
  • the embodiment of the present disclosure also provides a method for manufacturing a display substrate, including: providing a display substrate mother board, wherein the display substrate mother board includes at least one display substrate area, the display substrate area includes a silicon-based substrate, and The silicon-based substrate includes a plurality of metal traces for connecting the display area and the cathode ring with the binding area respectively; a color film layer is formed on the silicon-based substrate, and the color film layer includes a first An alignment mark, the first alignment mark is a hollow structure; the projection of the first alignment mark on the silicon-based substrate and the projection of the metal trace on the silicon-based substrate include overlap Area; cutting the display substrate mother board to obtain a separate display substrate.
  • the color film layer of the display area includes a first color unit, a second color unit, and a third color unit arranged in an array; the color film layer outside the display area includes a whole At least one of the first color unit, the second color unit, and the third color unit of the surface structure.
  • FIG. 1 is a schematic diagram of a structure of a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a structure of a color film layer according to an embodiment of the disclosure
  • FIG. 3 is a schematic cross-sectional view of the display substrate shown in FIG. 1;
  • FIG. 4 is a schematic diagram of a structure of an organic light-emitting layer according to an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a circuit principle of a silicon-based substrate according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a circuit implementation of a voltage control circuit and a pixel driving circuit according to an embodiment of the disclosure
  • FIG. 7 is a schematic diagram of a display substrate after preparing a silicon-based substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a display substrate after forming a first insulating layer and a first conductive pillar according to an embodiment of the disclosure
  • FIG. 9 is a schematic diagram of a display substrate after a reflective electrode is formed on a display substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a display substrate after forming a second insulating layer and a second conductive pillar according to an embodiment of the disclosure
  • FIG. 11 is a schematic diagram of a display substrate after an anode layer is formed on a display substrate according to an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a display substrate after forming an organic light-emitting layer and a cathode according to an embodiment of the disclosure
  • FIG. 13 is a schematic diagram of a display substrate after an encapsulation layer is formed on a display substrate according to an embodiment of the disclosure
  • FIG. 14 is a schematic diagram of a display substrate after forming a color filter layer according to an embodiment of the disclosure.
  • FIG. 15 is a schematic flowchart of a manufacturing method of a display substrate according to an embodiment of the disclosure.
  • 16 Siliconed conductive pillar
  • 20 Light emitting structure layer
  • 31 Alignment
  • 100 display area
  • 101 pixel drive circuit
  • 102 light emitting device
  • 110 voltage control circuit
  • 200 dummy pixel area
  • 300 cathode ring
  • 301 Power supply electrode
  • 400 Metal wiring area
  • 401 Metal wiring
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the first alignment mark includes a first alignment mark on the metal trace and a second alignment mark on one side of the metal trace.
  • the first alignment mark is generally made of anode layer metal or reflective layer metal. Since the first alignment mark is located on the metal traces of the display area and the cathode ring, the first alignment mark and the metal traces on the lower side are very likely to form a MIM capacitance effect, causing electrical breakdown and other defects.
  • the minimum distance between the first alignment mark and the upper edge of the Bonding Pad is 0.3 mm
  • the minimum distance between the second alignment mark and the lower cutting edge of the substrate is 0.48 mm. It is also necessary to maintain a certain distance between the bit mark and the second alignment mark and other metal traces. Therefore, this method of manufacturing the first alignment mark increases the edge area of the substrate and affects the cutting efficiency of the entire motherboard.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a silicon-based substrate and a color filter layer disposed on the silicon-based substrate.
  • the color film layer includes a first alignment mark; the first alignment mark is a hollow structure; the projection of the first alignment mark on the silicon substrate and the metal wiring The projection on the silicon-based substrate contains overlapping areas.
  • Some embodiments of the present disclosure also provide a display device corresponding to the above-mentioned display substrate and a manufacturing method of the display substrate.
  • the first alignment mark is a hollow structure; the metal wiring area can be formed to reflect light at the hollow first alignment mark , In other positions, the color film layer is covered to avoid light reflection, that is, obvious grayscale changes are produced at the edge of the first alignment mark, so that the edge position of the first alignment mark can be accurately identified.
  • the first alignment mark reduces the risk of capacitor breakdown, reduces the edge area of the substrate, improves the cutting efficiency of the substrate, and the preparation process is simple and reliable.
  • FIG. 1 is a schematic diagram of the structure of the display substrate of the present disclosure.
  • the display substrate includes a silicon-based substrate 10 and a color filter layer 50 disposed on the silicon-based substrate 10.
  • the silicon-based substrate 10 contains a display area 100 and a cathode ring 300 for binding the display area 100 and the cathode ring 300 respectively.
  • a plurality of metal traces connected to the area 500, the color film layer 50 includes a first alignment mark 52; the first alignment mark 52 is a hollow structure; the projection of the first alignment mark 52 on the silicon-based substrate 10
  • the projection of the metal trace on the silicon-based substrate 10 includes an overlapping area.
  • the color film layer 50 of the display area 100 includes a first color unit, a second color unit, and a third color unit arranged in an array, wherein the first color unit ,
  • the second color unit and the third color unit may be one of a red filter (Color Filter, CF) unit, a green filter unit, and a blue filter unit, respectively.
  • the first color unit, the second color unit, and the third color unit of the display area 100 are alternately arranged in an array in the first extension direction (for example, in the row direction of FIG. 2), and the first color unit , The second color unit and the third color unit are overlapped with each other, and the overlapping position is used as a black matrix.
  • the first color unit, the second color unit, and the third color unit of the display area 100 may be patterned column by column in the second extension direction (for example, in the column direction of FIG. 2). It can also be made by patterning each pixel unit. This application does not restrict this.
  • the color filter layer outside the display area 100 includes at least one of a first color unit, a second color unit, and a third color unit in a whole-surface structure.
  • the color filter layer outside the display area 100 is the color filter layer in the peripheral area.
  • the display substrate includes a display area 100 and a peripheral area surrounding the display area 100. As shown in FIGS. 1 and 3, the peripheral area may include a dummy pixel area 200, a cathode ring 300, a metal wiring area 400, and a bonding area 500.
  • the color filter layer 50 covers the display area 100, the dummy pixel area 200, the cathode ring 300 and part of the metal wiring area 400.
  • the color film layer outside the display area 100 includes a first color unit layer and a second color unit layer that are sequentially stacked, and the first color unit layer and the second color unit layer contain each other.
  • the through hole is used to form the first alignment mark 52 through the hole.
  • the first color unit layer may be a blue filter unit layer
  • the second color unit layer may be a red filter unit layer.
  • the adhesion of the blue filter unit is relatively high. Forming the blue filter unit first can reduce the possibility of peeling of the color film layer 50 from the cathode. Since the red filter unit has low adhesion but good fluidity, in the process of forming the red filter unit, the number of bubbles on the side of the blue filter unit and the red filter unit away from the cathode can be reduced, thereby The uniformity of the film thickness of the blue filter unit and the red filter unit can be improved.
  • the length of the first alignment mark 52 may be 50 to 150 microns
  • the width of the first alignment mark 52 may be 20 to 50 microns
  • the width of the metal trace may be 50 to 150 nanometers.
  • the interval between adjacent metal traces can be 30-50 nanometers.
  • the first alignment mark 52 is a cross-shaped structure composed of a horizontal opening and a vertical opening, wherein the length of the horizontal opening and the vertical opening are both 100 micrometers, and the widths are both 30 micrometers.
  • the width of a metal trace is 100 nanometers
  • the distance between adjacent metal traces is 50 nanometers.
  • Multiple metal traces are integrated by integrated circuits. Because multiple metal traces are densely arranged, they can be placed on the color film layer 50
  • the hollowed-out first alignment mark 52 reflects light.
  • the ratio of the area of the metal trace exposed by the first alignment mark 52 to the area of the first alignment mark 52 is greater than or equal to 80%.
  • the display area 100 includes a light emitting structure layer 20 disposed on a silicon-based substrate 10, and the light emitting structure layer 20 includes a reflective layer, an anode layer, an organic light emitting layer, and a cathode layer that are sequentially stacked.
  • the light emitting structure layer 20 may further include a structure film layer such as a pixel definition layer or a flat layer.
  • the organic light emitting layer 20 may directly emit white light from a white light material.
  • the organic light emitting layer 20 may be composed of three RGB materials stacked to emit white light.
  • FIG. 4 is a schematic diagram of a structure of the organic light-emitting layer of this embodiment.
  • the structure of the organic light-emitting layer of this embodiment includes a first light-emitting sublayer 331, a first charge generation layer 332, a second light-emitting sublayer 333, and a second charge generation layer sequentially stacked between the anode and the cathode.
  • Layer 334 and the third light-emitting sub-layer 335 are examples of the structure of the organic light-emitting layer of this embodiment.
  • the first light emitting sublayer 331 is configured to emit light of the first color, and includes a first hole transport layer (HTL) 3311, a first light emitting material layer (EML) 3312, and a first electron transport layer (ETL) 3313 that are sequentially stacked.
  • the second light-emitting sublayer 333 is configured to emit light of the second color, and includes a second hole transport layer 3331, a second light-emitting material layer 3332, and a second electron transport layer 3333 that are sequentially stacked.
  • the third light-emitting sublayer 335 is configured to emit light of the third color, and includes a third hole transport layer 3351, a third light-emitting material layer 3352, and a third electron transport layer 3353 that are sequentially stacked.
  • the first charge generation layer 332 is disposed between the first light-emitting sub-layer 331 and the second light-emitting sub-layer 333, and is used to connect the two light-emitting sub-layers in series to realize the transfer of carriers.
  • the second charge generation layer 334 is disposed between the second light-emitting sub-layer 333 and the third light-emitting sub-layer 335, and is used to connect the two light-emitting sub-layers in series to realize the transfer of carriers.
  • the organic light-emitting layer of the present disclosure includes a first light-emitting material layer that emits light of a first color, a second light-emitting material layer that emits light of a second color, and a third light-emitting material layer that emits light of a third color
  • the organic light-emitting layer finally emits light
  • the light is mixed light.
  • the first luminescent material layer is a red material layer that emits red light
  • the second luminescent material layer is a green material layer that emits green light
  • the third luminescent material layer is a blue material layer that emits blue light.
  • the layer finally emits white light.
  • At least one layer of the organic light-emitting layer 33 may be provided on the entire surface, or may be separately provided for each pixel area, so that the light-emitting layer of each color in each pixel area may be stacked to emit white light.
  • the organic light-emitting layer 33 may also be arranged in arrays of light-emitting layers of three colors such as red, green, and blue respectively, and each pixel region emits red, blue, and green light separately.
  • the organic light-emitting layer shown in FIG. 4 is only an exemplary structure, and the present disclosure does not limit this.
  • the structure of the organic light-emitting layer can be designed according to actual needs.
  • a hole injection layer (HIL) and an electron injection layer (EIL) may also be provided.
  • the first electron transport layer 3313, the first charge generation layer 332, and the second hole transport layer 3331 can be eliminated, that is, the second light-emitting material layer 3332 can be directly disposed on the first light-emitting material.
  • the organic light-emitting layer may be an organic light-emitting layer that emits light of the first color and an organic light-emitting layer that emits complementary light of the first color light, and the two organic light-emitting layers are sequentially stacked relative to the silicon-based substrate. Therefore, the white light is emitted as a whole, and the present disclosure does not limit this, as long as the white light can be realized.
  • the present disclosure adopts the white light + color film method to achieve a high resolution greater than 2000, and can meet the requirements of VR/AR.
  • the silicon-based substrate 10 of the display area 100 is provided with a driving circuit layer.
  • the driving circuit layer includes a first scan line, a first power line, a data line, a switching transistor, and a driving transistor.
  • the control electrode of the switching transistor is connected to the first scan line
  • the first electrode of the switching transistor is connected to the data line
  • the second electrode of the switching transistor is connected to the control electrode of the driving transistor
  • the first electrode of the driving transistor is connected to the first power line.
  • It is configured to receive the data signal transmitted by the data line under the control of the first scan signal output by the first scan line, so that the control electrode of the driving transistor receives the data signal, and the driving transistor is configured to control the data signal received at its control electrode Down, a corresponding current is generated in the second pole.
  • the metal wiring and the driving circuit layer are arranged in the same layer.
  • the cathode ring 300 may include a power supply electrode layer provided on the silicon-based substrate 10, a reflective layer provided on the side of the power supply electrode layer away from the silicon-based substrate, and a reflective layer provided on the reflective layer away from the power supply electrode.
  • the bonding area 500 may include a bonding electrode layer disposed on the silicon-based substrate 10 and an insulating layer covering the bonding electrode layer. The via hole of the binding electrode.
  • the bonding area 500 may further include a second alignment mark layer disposed on the silicon-based substrate 10, and the second alignment mark layer and the bonding electrode layer are disposed in the same layer.
  • the display substrate also includes a second alignment mark 51.
  • the first alignment mark 52 is located on the metal wiring area and is made by hollowing out the color film layer.
  • the second alignment mark 51 is located on the metal wiring area.
  • the binding area on the side of the zone is made of a metal layer.
  • the first alignment mark 52 may be a binding mark or any other type of alignment mark.
  • the first alignment mark 52 may also be used for the first alignment mark of the cover plate alignment.
  • the shape of the orthographic projection of the first alignment mark 52 on the silicon-based substrate may be a cross, a rectangle, a trapezoid, or any other regular or irregular shape.
  • Figure 2 shows the first alignment mark in two shapes, one is a cross and the other is an irregular shape.
  • the display substrate may further include a dummy pixel area 200.
  • the dummy pixel area 200 includes a silicon-based substrate 10, a light-emitting structure layer 20 disposed on the silicon-based substrate 10, The encapsulation layer 40 disposed on the light-emitting structure layer 20 and the color film layer 50 disposed on the encapsulation layer 40.
  • One difference from the display area 100 is that the silicon-based substrate 10 of the dummy pixel area 200 does not include circuits such as pixel driving circuits, gate driving circuits, and data driving circuits.
  • the metal wiring area 400 includes a silicon-based substrate 10, a first insulating layer disposed on the silicon-based substrate 10, and a first insulating layer disposed on the first insulating layer. Two insulating layers, an encapsulation layer 40 arranged on the second insulating layer, and a color film layer 50 arranged on the encapsulation layer 40.
  • the display substrate may further include a cover plate 70 which is disposed above the color film layer 50 to realize the function of protecting the color film 50.
  • the cover plate 70 is connected to the silicon-based substrate 10 through a sealant, and the sealant is disposed between the silicon-based substrate 10 and the cover plate 70, which can provide further protection against the intrusion of water and oxygen, so that The life span of silicon-based OLED display substrates has been greatly improved.
  • the sealant may be provided on the side surface of the cover plate 70, and the surrounding sides of the cover plate 70 and the silicon-based substrate 10 are sealed by the sealant, and the sealant is away from the side of the silicon-based substrate 10.
  • the end surface is located between the surface of the cover plate 70 on the side adjacent to the silicon-based substrate 10 and the surface of the cover plate 70 on the side away from the silicon-based substrate 10, thereby not only ensuring the sealing effect, but also preventing the sealant from rising above the cover plate 70 This leads to an increase in the thickness of the display substrate.
  • the cover plate 70 is disposed in the display area 100, which can better realize the alignment and sealing, and avoid the cover plate 70 from being broken during the cutting process.
  • the display substrate may further include a protective layer 60 disposed between the color filter layer 50 and the cover plate 70, and the protective layer 60 covers the color filter layer 50.
  • the protective layer 60 may be silicon carbide (SiC) or silicon carbide nitride (SiCNx). Since SiC or SiCNx tends to have inorganic characteristics, it can protect the color film layer 50 and reduce the color film layer 50 on the one hand. The aging damage can increase the service life. On the other hand, a flat surface can be formed, which facilitates the leveling of the glue material in the subsequent bonding process, and improves the bonding quality of the cover.
  • FIG. 5 is a schematic diagram of a circuit principle of a silicon-based substrate of the present disclosure.
  • the silicon-based substrate 10 includes a plurality of display units located in the display area 100 (effective display (AA) area) and a control circuit located in the peripheral area.
  • the multiple display units in the display area 100 are arranged regularly to form multiple displays. Rows and multiple display columns, each display unit includes a pixel drive circuit 101 and a light emitting device 102 connected to the pixel drive circuit 101, and the pixel drive circuit 101 includes at least a drive transistor.
  • the control circuit includes at least a plurality of voltage control circuits 110, and each voltage control circuit 110 is connected to a plurality of pixel driving circuits 101.
  • a voltage control circuit 110 is connected to the pixel drive circuit 101 in a display row, the first pole of the drive transistor in the display row pixel drive circuit 101 is commonly connected to the voltage control circuit 110, and the second pole of each drive transistor is connected to The anode of the light emitting device 102 of the present display unit is connected, and the cathode of the light emitting device 102 is connected to the input terminal of the second power signal VSS.
  • the voltage control circuit 110 is respectively connected to the input terminal of the first power signal VDD, the input terminal of the initialization signal Vinit, the input terminal of the reset control signal RE, and the input terminal of the light emission control signal EM, and the voltage control circuit 110 is configured to respond to the reset control
  • the signal RE outputs the initialization signal Vinit to the first pole of the driving transistor, and controls the corresponding light-emitting device 102 to reset.
  • the voltage control circuit 110 is further configured to output the first power signal VDD to the first pole of the driving transistor in response to the light emission control signal EM to drive the light emitting device 102 to emit light.
  • the structure of the pixel driving circuit 101 in the display area 100 can be simplified, and the area occupied by the pixel driving circuit 101 in the display area 100 can be reduced, so that the display area 100 can be more configured.
  • More pixel driving circuits 101 and light emitting devices 102 realize high PPI display.
  • the voltage control circuit 110 outputs the initialization signal Vinit to the first pole of the driving transistor under the control of the reset control signal RE, and controls the corresponding light-emitting device 102 to reset, which can prevent the voltage applied to the light-emitting device 102 from being lowered when the previous frame emits light.
  • the effect of one frame of light can improve the afterimage phenomenon.
  • three display units of different colors constitute one pixel, and the three display units may be a red display unit, a green display unit, and a blue display unit, respectively.
  • one pixel may include 4, 5 or more display units, which can be designed and determined according to the actual application environment, which is not limited here.
  • one voltage control circuit 110 can be connected to the pixel driving circuits 101 in two adjacent display units in the same display row, or can be connected to the pixel driving circuits 101 in three or more display units in the same display row.
  • the pixel driving circuit 101 is not limited here.
  • FIG. 6 is a schematic diagram of a circuit implementation of the voltage control circuit and the pixel driving circuit of the present disclosure.
  • the light-emitting device may include an OLED.
  • the anode of the OLED is connected to the second electrode D of the driving transistor M0, and the cathode of the OLED is connected to the input terminal of the second power signal VSS.
  • the voltage of the second power signal VSS is generally negative.
  • the voltage or ground voltage V GND generally 0V
  • the voltage of the initialization signal Vinit can also be set to the ground voltage V GND .
  • the OLED may be Micro-OLED or Mini-OLED, which is beneficial for realizing high PPI display.
  • the voltage control circuit 110 is connected to two pixel driving circuits 101 in one display row.
  • the pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst.
  • the circuit 110 includes a first transistor M1 and a second transistor M2.
  • the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all metal oxide semiconductor field effect transistors (MOS) fabricated in a silicon-based substrate.
  • the control electrode of the first transistor M1 is connected to the input end of the reset control signal RE for receiving the reset control signal RE, and the first electrode of the first transistor M1 is connected to the input end of the initialization signal Vinit for receiving the initialization signal Vinit.
  • the second pole of a transistor M1 is respectively connected to the first pole S of the corresponding driving transistor M0 and the second pole of the second transistor M2.
  • the control electrode of the second transistor M2 is connected to the input end of the light emission control signal EM for receiving the light emission control signal EM, and the first electrode of the second transistor M2 is connected to the input end of the first power signal VDD for receiving the first power source
  • the signal VDD and the second pole of the second transistor M2 are respectively connected to the first pole S of the corresponding driving transistor M0 and the second pole of the first transistor M1.
  • the types of the first transistor M1 and the second transistor M2 may be different, for example, the first transistor M1 is an N-type transistor, the second transistor M2 is a P-type transistor, or the first transistor M1 is a P-type transistor.
  • the second transistor M2 is an N-type transistor.
  • the types of the first transistor M1 and the second transistor M2 can be the same, which can be designed and determined according to the actual application environment, which is not limited herein.
  • the pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst.
  • the control electrode G of the driving transistor M0, the first electrode S of the driving transistor M0 are connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2, and the second electrode D of the driving transistor M0 is connected to the anode of the OLED.
  • the control electrode of the third transistor M3 is connected to the input end of the first control electrode scanning signal S1 for receiving the first control electrode scanning signal S1, and the first electrode of the third transistor M3 is connected to the input end of the data signal DA for receiving the first control electrode scanning signal S1.
  • the second electrode of the third transistor M3 is connected to the control electrode G of the driving transistor M0.
  • the control electrode of the fourth transistor M4 is connected to the input end of the second control electrode scanning signal S2 for receiving the second control electrode scanning signal S2, and the first electrode of the fourth transistor M4 is connected to the input end of the data signal DA for receiving the second control electrode scanning signal S2.
  • the second electrode of the fourth transistor M4 is connected to the control electrode G of the driving transistor M0.
  • the first end of the storage capacitor Cst is connected to the control electrode G of the driving transistor M0, and the second end of the storage capacitor Cst is connected to the ground terminal GND.
  • the driving transistor M0 may be an N-type transistor, and the types of the third transistor M3 and the fourth transistor M4 may be different, for example, the third transistor M3 is an N-type transistor, and the fourth transistor M4 is a P-type transistor.
  • the P-type fourth transistor M4 is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected by, for example, N The influence of the threshold voltage of the third transistor M3.
  • the third transistor M3 of the N type is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected by the P type.
  • the influence of the threshold voltage of the fourth transistor M4. In this way, the voltage range input to the control electrode G of the driving transistor M0 can be increased.
  • the type of the third transistor M3 and the fourth transistor M4 may be that the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.
  • the pixel driving circuit may be a 3T1C, 5T1C, or 7T1C circuit structure, or may be a circuit structure with internal compensation or external compensation, which is not limited in the present disclosure.
  • the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • “Thin film” refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the orthographic projection range of A, or that the orthographic projection of A covers the orthographic projection of B.
  • the silicon-based substrate 10 is prepared.
  • the silicon-based substrate 10 includes a display area 100 and a peripheral area surrounding the display area.
  • the peripheral area includes a dummy pixel area 200, a cathode ring 300, a metal wiring area 400 and a bonding area 500
  • the display area 100 includes a plurality of display units.
  • the silicon-based substrate 10 of each display unit is integrated with a pixel driving circuit.
  • the bonding area 500 is arranged on one side of the display area 100.
  • the silicon-based substrate 10 of the cathode ring 300 is integrated with a power supply.
  • the silicon-based substrate 10 in the metal wiring area 400 is integrated with metal wiring
  • the silicon-based substrate 10 in the bonding area 500 is integrated with a bonding circuit, as shown in FIG.
  • FIG. 7 illustrates three display units of the display area 100: a first display unit, a second display unit, and a third display unit, which illustrates the driving transistor 11 included in the pixel driving circuit, and illustrates
  • the power supply electrode 301 of the cathode ring 300 illustrates the metal wiring 401 of the metal wiring area 400, and illustrates the bonding electrode 501 included in the bonding circuit.
  • the driving thin film transistor of the display area 100 includes an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and the drain electrode are respectively connected to the active layer through a conductive pillar, and the gate is connected to the active layer.
  • the electrode is connected to the gate electrode through a conductive pillar, and the binding electrode 501 of the binding area 500 is arranged in the same layer as the source electrode, the drain electrode and the gate connection electrode.
  • a mature CMOS integrated circuit process can be used to prepare the silicon-based substrate 10, which is not limited in the present disclosure. After the preparation is completed, the surface of the silicon-based substrate 10 exposes the source electrode, the drain electrode and the gate connection electrode of the display area 100, the power supply electrode 301 of the cathode ring 300, the metal wiring 401 of the metal wiring area 400, and the bonding area 500 ⁇ Binding electrode 501.
  • a first insulating film is deposited on the silicon-based substrate 10, and the first insulating film is patterned through a patterning process to form a pattern of the first insulating layer 12 covering the silicon-based substrate 10, and the first insulating layer of the display area 100 12 forms a plurality of first via holes, the first insulating layer 12 of the cathode ring 300 forms at least one second via hole, the first insulating layer 12 of the bonding region 300 forms at least one third via hole, and a plurality of first via holes
  • the drain electrode of each display unit is respectively exposed, the second via hole exposes the power supply electrode 301, and the third via hole exposes the binding electrode 501.
  • first conductive pillars 13 are formed in the first via hole and the second via hole on the first insulating layer 12, and the first conductive pillar 13 in the first via hole is connected to the drain electrode of the display unit where it is located.
  • the first conductive pillar 13 in the two via holes is connected to the power supply electrode 301 of the cathode ring 300, as shown in FIG. 8.
  • the first conductive pillar 13 may be made of a metal material.
  • a polishing process may also be performed.
  • the first insulating layer 12 and the first conductive pillar may be polished through a polishing process.
  • the surface of 13 is corroded and rubbed to remove part of the thickness of the first insulating layer 12 and the first conductive pillar 13 so that the first insulating layer 12 and the first conductive pillar 13 form a flat surface.
  • the first conductive pillar 13 may be metal tungsten (W), and the via filled with tungsten metal is called a tungsten via (W-via).
  • W-via metal tungsten via
  • the tungsten vias can ensure the stability of the conductive path.
  • the resulting first insulating layer 12 has a good surface flatness, which is beneficial to Reduce contact resistance.
  • the tungsten via is not only suitable for the connection between the silicon-based substrate 10 and the reflective layer, but also for the connection between the reflective layer and the anode layer, and the connection between other wiring layers.
  • the reflective electrode 14 of each display unit is used to form a microcavity structure with the cathode formed subsequently, and the strong reflection effect of the reflective electrode is used to make the light directly emitted by the organic light-emitting layer and the light reflected by the reflective electrode interact with each other. Interference improves the color gamut of the emitted light and strengthens the brightness of the emitted light.
  • the film structure of the metal wiring area 400 and the bonding area 500 is unchanged, including the first insulating layer 12 disposed on the silicon-based substrate 10, and the first insulating layer 12 is provided with exposed bonding The binding via 502 of the fixed electrode 501.
  • a second insulating film is deposited on the silicon-based substrate 10 forming the foregoing structure, and the second insulating film is patterned through a patterning process to form a pattern of the second insulating layer 15 covering the silicon-based substrate 10, and the display area 100
  • the second insulating layer 15 forms a plurality of fourth via holes
  • the second insulating layer 15 of the dummy pixel region 200 forms a plurality of fifth via holes
  • the second insulating layer 15 of the cathode ring 300 forms at least one sixth via hole.
  • the fourth via hole respectively exposes the reflective electrode 14 of each display unit
  • the plurality of fifth via holes respectively expose the reflective electrode 14 of each dummy pixel area 200
  • the sixth via hole exposes the reflective electrode 14 of the cathode ring 300.
  • a plurality of second conductive pillars 16 are formed in the fourth via hole, the fifth via hole, and the sixth via hole on the second insulating layer 15.
  • the second conductive pillar 16 in the fourth via hole is connected to the display unit
  • the reflective electrode 14 is connected
  • the second conductive pillar 16 in the fifth via hole is connected to the reflective electrode 14 of the dummy pixel area 200
  • the second conductive pillar 16 in the sixth via hole is connected to the reflective electrode 14 of the cathode ring 300, as shown in FIG. 10 shown.
  • the second conductive pillar 16 may be made of a metal material. After the second conductive pillar 16 is formed by a filling process, a polishing process may also be performed. The second insulating layer 15 and the second conductive pillar may be polished by a polishing process.
  • the surface of 16 is corroded and rubbed to remove part of the thickness of the second insulating layer 15 and the second conductive pillar 16 so that the second insulating layer 15 and the second conductive pillar 16 form a flat surface.
  • the second conductive pillar 16 may use metal tungsten (W). In this patterning process, the film structure of the binding area 500 has not changed.
  • the anode layer includes a plurality of anodes 31 arranged in the display area 100, the dummy pixel area 200 and the cathode ring 300, and the anode 31 is connected to the reflective electrode 14 through the second conductive pillar 16, as shown in FIG.
  • the anode 31 is connected to the reflective electrode 14 through the second conductive pillar 16, and the reflective electrode 14 is connected to the drain electrode of the driving thin film transistor 11 through the first conductive pillar 13, so that the electrical signal provided by the pixel driving circuit is transmitted to the anode 31 through the reflective electrode 14.
  • the reflective electrode 14 forms a conductive channel between the pixel driving circuit and the anode on the one hand, and forms a microcavity structure on the other hand, which not only facilitates the control of the light emitting device by the pixel driving circuit, but also makes the structure of the display substrate more compact, which is beneficial to the silicon-based substrate. Miniaturization of OLED display devices. In this patterning process, the film structure of the metal wiring area 400 and the bonding area 500 is unchanged.
  • the organic light-emitting layer 33 is connected to the anode 31 of the display unit where it is located, and the planar cathode 34 is connected to each display unit.
  • the organic light-emitting layer 33 is connected; a cathode 34 is formed in the cathode ring 300, and the cathode 34 of the cathode ring 300 is connected to the anode 31 through the pixel opening, as shown in FIG. 12.
  • the cathode 34 is a semi-transmissive and semi-reverse electrode, and forms a microcavity structure with the reflective electrode 14 formed above. In this patterning process, the film structure of the metal wiring area 400 and the bonding area 300 does not change.
  • the first insulating film and the second insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), and may be a single-layer structure or a multilayer composite structure.
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or can be made of metal alloy materials, such as aluminum neodymium (AlNd) or molybdenum Niobium alloy (MoNb), etc., the alloy material can be a single-layer structure or a multilayer composite structure, such as a Mo/Cu/Mo composite structure.
  • the transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO), or a composite structure of ITO/Ag/ITO, and the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate Wait.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • a composite structure of ITO/Ag/ITO and the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate Wait.
  • an encapsulation layer pattern is formed in the display area 100, the dummy pixel area 200, the cathode ring 300, and the metal wiring area 400.
  • the encapsulation layer 40 is a thin-film encapsulation structure, as shown in FIG. 13 Shown.
  • a pattern of the color film layer 50 is formed in the display area 100, the dummy pixel area 200, the cathode ring 300 and part of the metal wiring area 400, and the color film layer 50 of the display area 100 It includes a first color unit 53, a second color unit 54 and a third color unit 55 arranged at intervals or overlapping each other.
  • the color units of the display area 100 may overlap each other as a black matrix , Or set a black matrix between color cells.
  • the color film layer 50 of the dummy pixel area 200, the cathode ring 300, and a part of the metal wiring area 400 includes a first color unit 53 and a second color unit 54 that are stacked, and the metal wiring in the metal wiring area 400 corresponds to In position, the color film layer 50 is provided with an opening 52 in the shape of a first alignment mark, as shown in FIG. 14.
  • the first color cell may be a green cell G
  • the second color cell may be a red cell R
  • the third color cell may be a blue cell B.
  • the preparation process of the color filter layer 50 includes: first forming the blue unit B, then forming the red unit R, and then forming the green unit G.
  • the adhesion of the blue color film is relatively high. Forming the blue unit B first can reduce the possibility of the color film layer 50 peeling off from the cathode. Since the red cell R has low adhesion but good fluidity, in the process of forming the red cell R, the number of bubbles on the surface of the blue cell B and the red cell R away from the cathode can be reduced, thereby increasing the blue color. The uniformity of the film thickness at the position where the cell B and the red cell R overlap. Since the base material of the green unit G and the base material of the red unit R are approximately the same, the adhesion between the green unit G and the red unit R is relatively large, which can reduce the possibility of the color film layer 50 peeling off from the cathode. In some possible implementations, the color film layer 50 may include other color units, such as white or yellow.
  • the openings corresponding to the binding marks are made through the color film layer above the metal wiring area.
  • the metal traces on the side reflect light, forming a first black and white alignment mark under the charge coupled device (CCD) image sensor of the bonding machine.
  • CCD charge coupled device
  • a sealing process is used to form the cover plate 60, and the cover plate 60 and the silicon-based substrate 10 are fixed by a sealant.
  • the film structure of the binding area 300 remains unchanged. Since the silicon-based substrate 10, the cover plate 60, and the sealant together form a closed space, it provides a guarantee for blocking water and oxygen, and greatly improves the life of the silicon-based OLED display substrate. Subsequently, the formed display mother board is cut to form a separate display substrate.
  • the present disclosure can make the metal wiring area in the first hollowed-out position by arranging the hollow first alignment mark at the position where the color film layer is opposite to the metal wiring area. Reflecting light is formed at the alignment mark, and the color film layer is covered to avoid light reflection at other positions, that is, an obvious grayscale change is generated at the edge of the first alignment mark, so that the edge position of the first alignment mark can be accurately identified .
  • the first alignment mark produced in this way reduces the risk of capacitor breakdown, reduces the edge area of the substrate, improves the cutting efficiency of the substrate, and the preparation process is simple and reliable.
  • the preparation process of the present disclosure can be realized by using mature preparation equipment, with little process improvement, high compatibility, simple process flow, easy periodic maintenance of equipment, high production efficiency, low production cost, high yield rate, and convenient mass production
  • the prepared display substrate can be used in virtual reality equipment or enhanced display equipment, or in other types of display devices, and has a good application prospect.
  • the structure shown in the present disclosure and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the length of the microcavity structure of each display unit may be the same or may be different.
  • the bonding area may form a corresponding pad, which is not specifically limited in the present disclosure.
  • the present disclosure also provides a manufacturing method of the display substrate. As shown in FIG. 15, the manufacturing method includes step S1 to step S3.
  • step S1 includes: providing a display substrate mother board, wherein the display substrate mother board includes at least one display substrate area, the display substrate area includes a silicon-based substrate, and the silicon-based substrate contains a display area and a cathode ring for connecting the display area and the cathode ring to the Multiple metal traces connected to the bonding area.
  • Step S2 includes: forming a color filter layer on a silicon-based substrate, the color filter layer including a first alignment mark, the first alignment mark is a hollow structure; the projection of the first alignment mark on the silicon-based substrate and the metal The projection of the trace on the silicon-based substrate includes an overlapping area.
  • the color film layer of the display area includes a first color unit, a second color unit, and a third color unit arranged in an array, wherein the first color unit, the second color unit, and the third color unit
  • the unit may be one of a red (R) color filter unit (Color Filter, CF), a green (G) color filter unit, and a blue (B) color filter unit.
  • the color film layer outside the display area includes a first color unit layer and a second color unit layer that are sequentially stacked, and the first color unit layer and the second color unit layer include interpenetrating The opening of the hole to form the first alignment mark through the opening.
  • the first color unit may be a blue filter unit
  • the second color unit may be a red filter unit.
  • the first alignment mark may be a binding mark or any other type of alignment mark.
  • the shape of the orthographic projection of the first alignment mark on the silicon-based substrate may be a cross, a rectangle, or any other regular or irregular shape.
  • the length of the opening of the first alignment mark is 50 to 150 microns
  • the width of the opening of the first alignment mark is 20 to 50 microns
  • the width of the metal trace is 50 to 150 nanometers.
  • the spacing between metal traces is 30 to 50 nanometers.
  • the first alignment mark is a cross-shaped structure composed of a horizontal opening and a vertical opening, wherein the length of the horizontal opening and the vertical opening are both 100 micrometers, the width is 30 micrometers, and the width of a metal trace The distance between adjacent metal traces is 50 nanometers.
  • Multiple metal traces are integrated by integrated circuits. Since multiple metal traces are densely arranged, they can be placed at the first alignment mark position hollowed out on the color film layer. Form reflections.
  • Step S3 includes: cutting the display substrate mother board to obtain a separate display substrate.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be a virtual reality device, an augmented reality device, or a near-eye display device, or may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.

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Abstract

一种显示基板及其制作方法、显示装置，显示基板包括硅基衬底（10）和设置在硅基衬底（10）上的彩膜层（50），硅基衬底（10）内包含用于分别将显示区域（100）和阴极环（300）与绑定区域（500）相连接的多条金属走线（401），彩膜层（50）包括第一对位标记（52），第一对位标记（52）为镂空结构；第一对位标记（52）在硅基衬底（10）上的投影和金属走线（401）在硅基衬底（10）上的投影包含重叠区域。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
微型有机发光二极管(Micro Organic Light-Emitting Diode，Micro-OLED)是近年来发展起来的微型显示器，硅基OLED是其中一种。硅基OLED不仅可以实现像素的有源寻址，并且可以实现在硅基衬底上制备时序控制(TCON)电路、过电流保护(OCP)电路等多种功能电路，有利于减小系统体积，实现轻量化。硅基OLED采用成熟的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)集成电路工艺制备，具有体积小、高分辨率(PPI)、高刷新率等优点，广泛应用在虚拟现实(Virtual Reality，VR)或增强现实(Augmented Reality，AR)近眼显示领域中。
硅基OLED微显示面板的制作过程中，为了让绑定机台能精准稳定的绑定，需要在基板的对应位置设置供绑定机台对位的第一对位标记。由于第一对位标记一般采用阳极层金属或反射层金属制作，不仅第一对位标记与其他金属走线之间需要保持一定的间距，而且第一对位标记与其他金属走线之间还容易形成金属-绝缘层-金属(Metal-insulator-Metal，MIM)电容效应，引起电学击穿等不良。此外，应绑定机台要求，第一对位标记与绑定焊盘(Bonding Pad)的上侧边缘之间的间距需大于或等于预设的最小间距，即第一对位标记增加了基板的边缘(Border)区域，影响了整个母板的切割效率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括：硅基衬底和设置在所述硅基衬底上的彩膜层，所述硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线，所述彩膜层包括第一对位标记；所述第一对位标记为镂空结构；所述第一对位标记在所述硅基衬底上的投影和所述金属走线在所述硅基衬底上的投影包含重叠区域。
在一些可能的实现方式中，所述显示区域的彩膜层包括呈阵列排布的第一颜色单元、第二颜色单元和第三颜色单元；所述显示区域之外的彩膜层包括呈整面结构的第一颜色单元、第二颜色单元、第三颜色单元中的至少一种。
在一些可能的实现方式中，所述显示区域之外的彩膜层包括依次叠层设置的第一颜色单元层和第二颜色单元层，所述第一颜色单元层和第二颜色单元层上包含相互贯穿的开孔，以通过所述开孔形成所述第一对位标记。
在一些可能的实现方式中，所述第一颜色单元层为蓝色滤光单元层，所述第二颜色单元层为红色滤光单元层。
在一些可能的实现方式中，所述第一对位标记的长度为50至150微米，所述第一对位标记的宽度为20至50微米，所述金属走线的宽度为50至150纳米，相邻金属走线的间隔为30至50纳米。
在一些可能的实现方式中，所述第一对位标记暴露出的金属走线的面积与所述第一对位标记的面积的比值大于或等于80％。
在一些可能的实现方式中，所述显示区域包括设置在硅基衬底上的发光结构层，所述发光结构层包括依次叠层设置的反射层、阳极层、有机发光层和阴极层；所述显示区域的硅基衬底内设置有驱动电路层，所述驱动电路层包括第一扫描线、第一电源线、数据线、开关晶体管和驱动晶体管，所述开关晶体管的控制极与第一扫描线连接，所述开关晶体管的第一极与数据线连接，所述开关晶体管的第二极与驱动晶体管的控制极连接，所述驱动晶体管的第一极与第一电源线连接，所述开关晶体管被配置为在第一扫描线输出的第一扫描信号控制下，接收数据线传输的数据信号，使驱动晶体管的控制极接收所述数据信号，所述驱动晶体管被配置为在其控制极所接收的数据信号控制下，在第二极产生相应的电流；所述金属走线和所述驱动电路层同层设置。
在一些可能的实现方式中，所述阴极环包括设置在硅基衬底上的供电电极层、设置在所述供电电极层远离硅基衬底一侧的反射层、设置在所述反射层远离供电电极层一侧的阳极层以及设置在所述阳极层远离反射层一侧的阴极层。
在一些可能的实现方式中，所述绑定区域包括设置在所述硅基衬底上的绑定电极层以及覆盖绑定电极层的绝缘层，所述绝缘层上开设有暴露出绑定电极层内的绑定电极的过孔。
在一些可能的实现方式中，所述绑定区域还包括设置在所述硅基衬底上的第二对位标记层，所述第二对位标记层和所述绑定电极层同层设置。
本公开实施例还提供了一种显示装置，包括：如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制作方法，包括：提供显示基板母板，其中，所述显示基板母板包括至少一个显示基板区域，所述显示基板区域包括硅基衬底，所述硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线；在所述硅基衬底上形成彩膜层，所述彩膜层包括第一对位标记，所述第一对位标记为镂空结构；所述第一对位标记在所述硅基衬底上的投影和所述金属走线在所述硅基衬底上的投影包含重叠区域；对所述显示基板母板进行切割以得到单独的显示基板。
在一些可能的实现方式中，所述显示区域的彩膜层包括呈阵列排布的第一颜色单元、第二颜色单元和第三颜色单元；所述显示区域之外的彩膜层包括呈整面结构的第一颜色单元、第二颜色单元、第三颜色单元中的至少一种。
在阅读并理解了附图概述和本公开的实施方式后，可以明白其他方面。
附图说明
图1为本公开实施例的显示基板的一种结构示意图；
图2为本公开实施例的彩膜层的一种结构示意图；
图3为图1所示显示基板的剖面示意图；
图4为本公开实施例有机发光层一种结构的示意图；
图5为本公开实施例硅基衬底一种电路原理的示意图；
图6为本公开实施例电压控制电路和像素驱动电路一种电路实现的示意图；
图7为本公开实施例一种显示基板制备硅基衬底后的示意图；
图8为本公开实施例一种显示基板形成第一绝缘层和第一导电柱后的示意图；
图9为本公开实施例一种显示基板形成反射电极后的示意图；
图10为本公开实施例一种显示基板形成第二绝缘层和第二导电柱后的示意图；
图11为本公开实施例一种显示基板形成阳极层后的示意图；
图12为本公开实施例一种显示基板形成有机发光层和阴极后的示意图；
图13为本公开实施例一种显示基板形成封装层后的示意图；
图14为本公开实施例一种显示基板形成彩膜层后的示意图；
图15为本公开实施例显示基板的制作方法的流程示意图。
附图标记说明：
10—硅基衬底；         11—驱动薄膜晶体管；   12—第一绝缘层；
13—第一导电柱；       14—反射电极；         15—第二绝缘层；
16—第二导电柱；       20—发光结构层；       31—阳极；
32—像素定义层；       33—有机发光层；       34—阴极；
40—封装层；           50—彩膜层；           51—第二对位标记；
52—第一对位标记；     53—第一颜色单元；     54—第二颜色单元；
55—第三颜色单元；     60—保护层；           70—盖板；
100—显示区域；        101—像素驱动电路；    102—发光器件；
110—电压控制电路；    200—虚设像素区域；    300—阴极环；
301—供电电极；        400—金属走线区；      401—金属走线；
Figure PCTCN2020081856-appb-000001
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述 各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
一种硅基OLED微显示面板的制作过程中，为了让绑定机台能精准稳定的绑定，需要在基板的对应位置设置供绑定机台对位的第一对位标记。第一 对位标记包括位于金属走线之上的第一对位标记和位于金属走线一侧的第二对位标记，第一对位标记一般采用阳极层金属或反射层金属制作。由于第一对位标记位于显示区域和阴极环的金属走线之上，第一对位标记与其下侧的金属走线，极容易形成MIM电容效应，引起电学击穿等不良。此外，应绑定机台要求，第一对位标记距离Bonding Pad的上侧边缘的最小间距为0.3毫米，第二对位标记距离基板的下侧切割边缘的最小间距为0.48毫米，第一对位标记和第二对位标记与其他金属走线之间也需要保持一定的间距。因此，这种第一对位标记的制作方式会增加基板的边缘区域，影响整个母板的切割效率。
本公开至少一实施例提供一种显示基板，该显示基板包括硅基衬底和设置在硅基衬底上的彩膜层，硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线，彩膜层包括第一对位标记；所述第一对位标记为镂空结构；第一对位标记在硅基衬底上的投影和金属走线在硅基衬底上的投影包含重叠区域。
本公开一些实施例还提供对应于上述显示基板的显示装置及该显示基板的制作方法。
本公开上述实施例提供的显示基板，通过在彩膜层上设置第一对位标记，该第一对位标记为镂空结构；可以使得金属走线区在镂空的第一对位标记处形成反光，在其他位置处由于彩膜层覆盖避免反光，即在第一对位标记的边缘处产生明显的灰度变化，从而可以准确的识别到第一对位标记的边缘位置，通过该方式制作的第一对位标记，减少了电容击穿的风险，减小了基板的边缘区域，提高了基板的切割效率，且制备工艺简单可靠。
图1为本公开显示基板的结构示意图。如图1所示，显示基板包括硅基衬底10和设置在硅基衬底10上的彩膜层50，硅基衬底10内包含用于分别将显示区域100和阴极环300与绑定区域500相连接的多条金属走线，彩膜层50包括第一对位标记52；所述第一对位标记52为镂空结构；第一对位标记52在硅基衬底10上的投影和金属走线在硅基衬底10上的投影包含重叠区域。
在一种示例性实施例中，如图2所示，显示区域100的彩膜层50包括呈 阵列排布的第一颜色单元、第二颜色单元和第三颜色单元，其中，第一颜色单元、第二颜色单元和第三颜色单元可以分别为红色滤光(Color Filter，CF)单元、绿色滤光单元和蓝色滤光单元中的其中一种。在一些可能的实现方式中，显示区域100的第一颜色单元、第二颜色单元和第三颜色单元在第一延伸方向上(例如图2的行方向上)阵列交替排布，且第一颜色单元、第二颜色单元和第三颜色单元之间相互交叠设置，交叠的位置作为黑矩阵。在一些可能的实现方式中，显示区域100的第一颜色单元、第二颜色单元和第三颜色单元在第二延伸方向上(例如图2的列方向上)可以是逐列图案化制成，也可以是逐个像素单元图案化制成。本申请对此不作限制。
在一种示例性实施例中，显示区域100之外的彩膜层包括呈整面结构的第一颜色单元、第二颜色单元、第三颜色单元中的至少一种。
在该示例性实施例中，显示区域100之外的彩膜层即为外围区域的彩膜层。显示基板包括显示区域100和包围显示区域100的外围区域，如图1和图3所示，外围区域可以包括虚设像素区域200、阴极环300、金属走线区400和绑定区域500。
在一种示例性实施例中，如图1和图3所示，彩膜层50覆盖显示区域100、虚设像素区域200、阴极环300和部分金属走线区400。
在一种示例性实施例中，显示区域100之外的彩膜层包括依次叠层设置的第一颜色单元层和第二颜色单元层，第一颜色单元层和第二颜色单元层上包含相互贯穿的开孔，以通过开孔形成第一对位标记52。
在一种示例性实施例中，第一颜色单元层可以为蓝色滤光单元层，第二颜色单元层可以为红色滤光单元层。蓝色滤光单元的粘附性较大，先形成蓝色滤光单元可以减小彩膜层50从阴极上剥离的可能性。由于红色滤光单元的粘附性较小，但流动性好，因而在形成红色滤光单元的过程中，可以减少蓝色滤光单元和红色滤光单元远离阴极一侧表面的气泡数量，从而可以提高蓝色滤光单元和红色滤光单元二者膜厚的均一性。
在一种示例性实施例中，第一对位标记52的长度可以为50至150微米，第一对位标记52的宽度可以为20至50微米，金属走线的宽度可以为50至 150纳米，相邻金属走线的间隔可以为30至50纳米。示例性的，如图1所示，第一对位标记52为由横向开口和竖向开口组成的十字形结构，其中，横向开口和竖向开口的长度均为100微米，宽度均为30微米，一条金属走线的宽度为100纳米，相邻金属走线的间距为50纳米，多条金属走线通过集成电路集成在一起，由于多条金属走线密集排布，可以在彩膜层50镂空的第一对位标记52位置形成反光。
在一种示例性实施例中，第一对位标记52暴露出的金属走线的面积与第一对位标记52的面积的比值大于或等于80％。
在一种示例性实施例中，显示区域100包括设置在硅基衬底10上的发光结构层20，发光结构层20包括依次叠层设置的反射层、阳极层、有机发光层和阴极层。在一示例性实施方式中，发光结构层20还可以包括像素定义层或平坦层等结构膜层。
在一种示例性实施例中，有机发光层20可以是由白光材料直接出射白光。
在另一种示例性实施例中，有机发光层20可以是RGB三种材料叠置出射白光。图4为本实施例有机发光层一种结构的示意图。如图4所示，本实施例有机发光层的结构包括在阳极与阴极之间依次叠设的第一发光子层331、第一电荷产生层332、第二发光子层333、第二电荷产生层334和第三发光子层335。第一发光子层331设置为出射第一颜色光，包括依次叠设的第一空穴传输层(HTL)3311、第一发光材料层(EML)3312和第一电子传输层(ETL)3313。第二发光子层333设置为出射第二颜色光，包括依次叠设的第二空穴传输层3331、第二发光材料层3332和第二电子传输层3333。第三发光子层335设置为出射第三颜色光，包括依次叠设的第三空穴传输层3351、第三发光材料层3352和第三电子传输层3353。第一电荷产生层332设置在第一发光子层331与第二发光子层333之间，用于将两个发光子层串联起来，实现载流子的传递。第二电荷产生层334设置在第二发光子层333与第三发光子层335之间，用于将两个发光子层串联起来，实现载流子的传递。由于本公开有机发光层包括出射第一颜色光的第一发光材料层、出射第二颜色光的第二发光材料层和出射第三颜色光的第三发光材料层，因而有机发光层最终出射的光为混合光。例如，可以设置第一发光材料层是出射红光的红光材料层， 第二发光材料层是出射绿光的绿光材料层，第三发光材料层是出射蓝光的蓝光材料层，因而有机发光层最终出射白光。
在示例性实施方式中，有机发光层33中的至少一层可以整面设置，也可以单独按照每个像素区域设置，可以满足每个像素区域中的各颜色的发光层叠置发出白光即可。
在示例性实施方式中，有机发光层33也可以是如红、绿、蓝三种颜色的发光层分别阵列排布，每个像素区域中单独发出红光、蓝光、绿光。
在示例性实施方式中，图4所示的有机发光层仅仅是一种示例结构，本公开对此不作限制。实际实施时，可以根据实际需要设计有机发光层的结构。例如，每个发光子层中，为了能够提高电子和空穴注入发光材料层的效率，还可以设置空穴注入层(HIL)和电子注入层(EIL)。又如，为了简化有机发光层的结构，可以取消第一电子传输层3313、第一电荷产生层332和第二空穴传输层3331，即第二发光材料层3332可以直接设置在第一发光材料层3312上。
在一些可能的实现方式中，有机发光层可以采用出射第一颜色光的有机发光层和出射第一颜色光的互补光的有机发光层，该两个有机发光层相对于硅基衬底依次堆叠，从而整体上发白光，本公开对此不作限制，只要可以实现发白光即可。本公开采用白光+彩膜方式可以实现大于2000的高分辨率，能够适应VR/AR需求。
在一种示例性实施例中，显示区域100的硅基衬底10内设置有驱动电路层，驱动电路层包括第一扫描线、第一电源线、数据线、开关晶体管和驱动晶体管，开关晶体管的控制极与第一扫描线连接，开关晶体管的第一极与数据线连接，开关晶体管的第二极与驱动晶体管的控制极连接，驱动晶体管的第一极与第一电源线连接，开关晶体管被配置为在第一扫描线输出的第一扫描信号控制下，接收数据线传输的数据信号，使驱动晶体管的控制极接收数据信号，驱动晶体管被配置为在其控制极所接收的数据信号控制下，在第二极产生相应的电流。
在一种示例性实施例中，金属走线和驱动电路层同层设置。
在一种示例性实施例中，阴极环300可以包括设置在硅基衬底10上的供电电极层、设置在供电电极层远离硅基衬底一侧的反射层、设置在反射层远离供电电极层一侧的阳极层以及设置在阳极层远离反射层一侧的阴极层。
在一种示例性实施例中，绑定区域500可以包括设置在硅基衬底10上的绑定电极层以及覆盖绑定电极层的绝缘层，绝缘层上开设有暴露出绑定电极层内的绑定电极的过孔。
在一种示例性实施例中，绑定区域500还可以包括设置在硅基衬底10上的第二对位标记层，第二对位标记层和绑定电极层同层设置。
如图1所示，显示基板还包括第二对位标记51，第一对位标记52位于金属走线区之上，通过彩膜层镂空制作而成，第二对位标记51位于金属走线区一侧的绑定区域，通过金属层制作而成。
在一种示例性实施例中，第一对位标记52可以为绑定标记或其他任意类型的对位标记。例如，第一对位标记52还可以用于盖板对位的第一对位标记。
在一种示例性实施例中，第一对位标记52在硅基衬底上的正投影的形状可以为十字形、矩形、梯形或其他任意的规则或不规则的形状。图2示出了两种形状的第一对位标记，一种为十字形，一种为不规则形状。
在一种示例性实施例中，如图3所示，显示基板还可以包括虚设像素区域200，虚设像素区域200包括硅基衬底10、设置在硅基衬底10上的发光结构层20、设置在发光结构层20上的封装层40以及设置在封装层40上的彩膜层50。与显示区域100的一个不同之处是，虚设像素区域200的硅基衬底10中不包括像素驱动电路、栅极驱动电路和数据驱动电路等电路。
在一种示例性实施例中，如图3所示，金属走线区400包括硅基衬底10、设置在硅基衬底10上的第一绝缘层、设置在第一绝缘层上的第二绝缘层、设置在第二绝缘层上的封装层40以及设置在封装层40上的彩膜层50。
在一种示例性实施例中，显示基板还可以包括盖板70，盖板70设置在彩膜层50的上方，可以实现保护彩膜50的功能。在一示例性实施方式中，盖板70通过密封胶与硅基衬底10连接，密封胶设置于硅基衬底10与盖板70之间，可以为阻隔水氧入侵提供进一步的保障，使硅基OLED显示基板寿 命大幅提升。在另一示例性实施方式中，密封胶可以设置于盖板70的侧面，盖板70的四周侧面与硅基衬底10之间通过密封胶密封，密封胶远离硅基衬底10一侧的端面位于盖板70邻近硅基衬底10一侧的表面与盖板70远离硅基衬底10一侧的表面之间，由此既能够确保密封效果，又可以防止密封胶高出盖板70导致显示基板的厚度增加。在示例性实施方式中，盖板70设置在显示区域100，可以较好地实现对位和密封，避免在切割过程中导致盖板70破裂。
在一种示例性实施例中，显示基板还可以包括保护层60，保护层60设置在彩膜层50和盖板70之间，保护层60覆盖彩膜层50。在一示例性实施方式中，保护层60可以采用碳化硅(SiC)或氮碳化硅(SiCNx)，由于SiC或SiCNx倾向于具有无机特性，一方面可以保护彩膜层50，减少彩膜层50的老化损伤，增加使用寿命，另一方面可以形成平坦表面，便于后续贴合盖板工艺中胶材的流平，提高盖板贴合质量。
图5为本公开硅基衬底一种电路原理的示意图。硅基衬底10包括位于显示区域100(有效显示(AA)区)中的多个显示单元和位于外围区域中的控制电路，显示区域100中的多个显示单元规则排布，形成多个显示行和多个显示列，每个显示单元包括像素驱动电路101以及与像素驱动电路101连接的发光器件102，像素驱动电路101至少包括驱动晶体管。控制电路至少包括多个电压控制电路110，每个电压控制电路110与多个像素驱动电路101连接。例如，一个电压控制电路110与一个显示行中的像素驱动电路101连接，该显示行像素驱动电路101中驱动晶体管的第一极共同连接该电压控制电路110，每个驱动晶体管的第二极与本显示单元的发光器件102的阳极连接，发光器件102的阴极连接第二电源信号VSS的输入端。电压控制电路110分别与第一电源信号VDD的输入端、初始化信号Vinit的输入端、复位控制信号RE的输入端和发光控制信号EM的输入端连接，电压控制电路110被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光器件102复位。电压控制电路110还被配置为响应于发光控制信号EM，将第一电源信号VDD输出至驱动晶体管的第一极，以驱动发光器件102发光。通过一个显示行中的像素驱动电路101共同连接电 压控制电路110，可以简化显示区域100中像素驱动电路101的结构，降低显示区域100中像素驱动电路101的占用面积，从而使显示区域100设置更多的像素驱动电路101和发光器件102，实现高PPI显示。电压控制电路110在复位控制信号RE的控制下将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光器件102复位，可以避免上一帧发光时加载于发光器件102上的电压对下一帧发光的影响，可以改善残影现象。
在示例性实施方式中，3个不同颜色的显示单元组成1个像素，3个显示单元可以分别为红色显示单元、绿色显示单元以及蓝色显示单元。在一些可能的实现方式中，1个像素可以包括4个、5个或更多的显示单元，可以根据实际应用环境来设计确定，在此不作限定。在一些可能的实现方式中，一个电压控制电路110可以连接同一显示行中两个相邻的显示单元中的像素驱动电路101，或可以连接同一显示行中三个或更多的显示单元中的像素驱动电路101，在此不作限定。
图6为本公开电压控制电路和像素驱动电路一种电路实现的示意图。如图6所示，发光器件可以包括OLED，OLED的阳极与驱动晶体管M0的第二极D连接，OLED的阴极与第二电源信号VSS的输入端连接，第二电源信号VSS的电压一般为负电压或接地电压V GND(一般为0V)，初始化信号Vinit的电压也可以设置为接地电压V GND。在示例性实施方式中，OLED可以是Micro-OLED或Mini-OLED，有利于实现高PPI显示。
在示例性实施方式中，电压控制电路110与一显示行中的两个像素驱动电路101连接，像素驱动电路101包括驱动晶体管M0、第三晶体管M3、第四晶体管M4和存储电容Cst，电压控制电路110包括第一晶体管M1和第二晶体管M2。驱动晶体管M0、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4均是制备在硅基衬底中的金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)。
第一晶体管M1的控制极与复位控制信号RE的输入端连接，用于接收复位控制信号RE，第一晶体管M1的第一极与初始化信号Vinit的输入端连接，用于接收初始化信号Vinit，第一晶体管M1的第二极分别与对应的驱动晶体管M0的第一极S和第二晶体管M2的第二极连接。第二晶体管M2的 控制极与发光控制信号EM的输入端连接，用于接收发光控制信号EM，第二晶体管M2的第一极与第一电源信号VDD的输入端连接，用于接收第一电源信号VDD，第二晶体管M2的第二极分别与对应的驱动晶体管M0的第一极S和第一晶体管M1的第二极连接。在示例性实施方式中，第一晶体管M1与第二晶体管M2的类型可以不同，例如，第一晶体管M1为N型晶体管，第二晶体管M2为P型晶体管，或者，第一晶体管M1为P型晶体管，第二晶体管M2为N型晶体管。在一些可能的实现方式中，第一晶体管M1与第二晶体管M2的类型可以相同，可以根据实际应用环境来设计确定，在此不作限定。
像素驱动电路101包括驱动晶体管M0、第三晶体管M3、第四晶体管M4和存储电容Cst。驱动晶体管M0的控制极G，驱动晶体管M0的第一极S与第一晶体管M1的第二极和第二晶体管M2的第二极连接，驱动晶体管M0的第二极D与OLED的阳极连接。第三晶体管M3的控制极与第一控制极扫描信号S1的输入端连接，用于接收第一控制极扫描信号S1，第三晶体管M3的第一极与数据信号DA的输入端连接，用于接收数据信号DA，第三晶体管M3的第二极与驱动晶体管M0的控制极G连接。第四晶体管M4的控制极与第二控制极扫描信号S2的输入端连接，用于接收第二控制极扫描信号S2，第四晶体管M4的第一极与数据信号DA的输入端连接，用于接收数据信号DA，第四晶体管M4的第二极与驱动晶体管M0的控制极G连接。存储电容Cst的第一端与驱动晶体管M0的控制极G连接，存储电容Cst的第二端与接地端GND连接。在示例性实施方式中，驱动晶体管M0可以为N型晶体管，第三晶体管M3与第四晶体管M4的类型可以不同，例如，第三晶体管M3为N型晶体管，第四晶体管M4为P型晶体管。当数据信号DA的电压为高灰阶对应的电压时，通过P型的第四晶体管M4导通以将数据信号DA传输给驱动晶体管M0的控制极G，可以避免数据信号DA的电压受例如N型的第三晶体管M3的阈值电压的影响。当数据信号DA的电压为低灰阶对应的电压时，通过N型的第三晶体管M3导通以将数据信号DA传输给驱动晶体管M0的控制极G，可以避免数据信号DA的电压受P型的第四晶体管M4的阈值电压的影响。这样，可以提高输入到驱动晶体管M0 的控制极G上的电压范围。在一些可能的实现方式中，第三晶体管M3与第四晶体管M4的类型可以是，第三晶体管M3为P型晶体管，第四晶体管M4为N型晶体管。在一些可能的实现方式中，像素驱动电路可以是3T1C、5T1C或7T1C电路结构，或可以是具有内部补偿或外部补偿功能的电路结构，本公开对此不作限制。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。本公开中所说的“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
(1)制备硅基衬底10，硅基衬底10包括显示区域100和包围显示区域的外围区域，外围区域包括虚设像素区域200、阴极环300、金属走线区400和绑定区域500，显示区域100包括多个显示单元，每个显示单元的硅基衬底10集成有像素驱动电路，绑定区域500设置在显示区域100的一侧，阴极环300的硅基衬底10集成有供电电路，金属走线区400的硅基衬底10集成有金属走线，绑定区域500的硅基衬底10集成有绑定电路，如图7所示。作为一种示例性说明，图7中示意了显示区域100的三个显示单元：第一显示单元、第二显示单元和第三显示单元，示意了像素驱动电路所包括的驱动晶体管11，示意了阴极环300的供电电极301，示意了金属走线区400的金属走线401，示意了绑定电路所包括的绑定电极501。在一示例性实施方式中，显示区域100的驱动薄膜晶体管包括有源层、栅电极、源电极、漏电极和栅连接电极，源电极和漏电极分别通过导电柱与有源层连接，栅连接电极通过导电柱与栅电极连接，绑定区域500的绑定电极501与源电极、漏电极和栅 连接电极同层设置。制备硅基衬底10可以采用成熟的CMOS集成电路工艺，本公开对此不作限制。制备完成后，硅基衬底10的表面暴露出显示区域100的源电极、漏电极和栅连接电极，阴极环300的供电电极301、金属走线区400的金属走线401以及绑定区域500的绑定电极501。
(2)在硅基衬底10上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成覆盖硅基衬底10的第一绝缘层12图案，显示区域100的第一绝缘层12形成多个第一过孔，阴极环300的第一绝缘层12形成至少一个第二过孔，绑定区域300的第一绝缘层12形成至少一个第三过孔，多个第一过孔分别暴露出每个显示单元的漏电极，第二过孔暴露出供电电极301，第三过孔暴露出绑定电极501。随后，在第一绝缘层12上的第一过孔和第二过孔内形成多个第一导电柱13，第一过孔内的第一导电柱13与所在显示单元的漏电极连接，第二过孔内的第一导电柱13与阴极环300的供电电极301连接，如图8所示。在示例性实施方式中，第一导电柱13可以由金属材料制成，通过填充处理形成第一导电柱13后，还可以进行抛光处理，通过抛光工艺对第一绝缘层12和第一导电柱13的表面进行腐蚀和摩擦，去除第一绝缘层12和第一导电柱13的部分厚度，使第一绝缘层12和第一导电柱13形成平齐的表面。在一些可能的实现方式中，第一导电柱13可以采用金属钨(W)，由钨金属填充的过孔称为钨过孔(W-via)。在第一绝缘层12厚度较大的情况下，采用钨过孔可以保证导电通路的稳定性，由于制作钨过孔的工艺成熟，所得到的第一绝缘层12的表面平坦度好，有利于降低接触电阻。钨过孔不仅适用于硅基衬底10与反射层之间的连接，还适用于反射层与阳极层之间的连接，以及其它布线层之间的连接。
(3)在形成前述结构的硅基衬底10上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在第一绝缘层12上形成反射层图案，反射层包括设置在显示区域100、虚设像素区域200和阴极环300内的多个反射电极14，在每个显示单元内，反射电极14通过第一导电柱13与漏电极连接，在阴极环300，反射电极14通过第一导电柱13与供电电极301连接，如图9所示。在示例性实施方式中，每个显示单元的反射电极14用于与后续形成的阴极构成微腔结构，利用反射电极的强反射效应，使得有机发光层直接出射 的光线与反射电极反射的光线相互干涉，提高了出射光的色域，强化了出射光的的亮度。本次构图工艺中，金属走线区400和绑定区域500的膜层结构没有变化，包括设置在硅基衬底10上的第一绝缘层12，第一绝缘层12上开设有暴露出绑定电极501的绑定过孔502。
(4)在形成前述结构的硅基衬底10上沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成覆盖硅基衬底10的第二绝缘层15图案，显示区域100的第二绝缘层15形成多个第四过孔，虚设像素区域200的第二绝缘层15形成多个第五过孔，阴极环300的第二绝缘层15形成至少一个第六过孔，多个第四过孔分别暴露出每个显示单元的反射电极14，多个第五过孔分别暴露出每个虚设像素区域200的反射电极14，第六过孔暴露出阴极环300的反射电极14。随后，在第二绝缘层15上的第四过孔、第五过孔和第六过孔内形成多个第二导电柱16，第四过孔内的第二导电柱16与所在显示单元的反射电极14连接，第五过孔内的第二导电柱16与虚设像素区域200的反射电极14连接，第六过孔内的第二导电柱16与阴极环300的反射电极14连接，如图10所示。在示例性实施方式中，第二导电柱16可以由金属材料制成，通过填充处理形成第二导电柱16后，还可以进行抛光处理，通过抛光工艺对第二绝缘层15和第二导电柱16的表面进行腐蚀和摩擦，去除第二绝缘层15和第二导电柱16的部分厚度，使第二绝缘层15和第二导电柱16形成平齐的表面。在一些可能的实现方式中，第二导电柱16可以采用金属钨(W)。本次构图工艺中，绑定区域500的膜层结构没有变化。
(5)在形成前述结构的硅基衬底10上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在显示区域100、虚设像素区域200和阴极环300的第二绝缘层15上形成阳极层图案，阳极层包括设置在显示区域100、虚设像素区域200和阴极环300的多个阳极31，阳极31通过第二导电柱16与反射电极14连接，如图11所示。阳极31通过第二导电柱16与反射电极14连接，反射电极14通过第一导电柱13与驱动薄膜晶体管11的漏电极连接，这样像素驱动电路提供的电信号通过反射电极14传输到阳极31，反射电极14一方面形成像素驱动电路与阳极之间的导电通道，另一方面形成微腔结构，不仅有利于像素驱动电路对发光器件的控制，而且使显示基板的结构 更紧凑，有利于硅基OLED显示装置的微型化。本次构图工艺中，金属走线区400和绑定区域500的膜层结构没有变化。
(6)在形成前述结构的硅基衬底10上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，在显示区域100、虚设像素区域200和阴极环300形成像素定义层(PDL)32图案，在每个显示单元，像素定义层32开设有像素开口，像素开口暴露出阳极31的表面。随后，在显示区域100和虚设像素区域200依次形成有机发光层33和阴极34，在每个显示单元，有机发光层33与所在显示单元的阳极31连接，面状的阴极34与每个显示单元的有机发光层33连接；在阴极环300形成阴极34，阴极环300的阴极34通过像素开口与阳极31连接，如图12所示。在示例性实施方式中，阴极34为半透半反电极，与前述形成的反射电极14构成微腔结构。本次构图工艺中，金属走线区400和绑定区域300的膜层结构没有变化。
前述制备过程中，第一绝缘薄膜和第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)，可以是单层结构，或者可以是多层复合结构。第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)或钼(Mo)等，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，合金材料可以是单层结构，或者可以是多层复合结构，如Mo/Cu/Mo的复合结构。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，或ITO/Ag/ITO的复合结构，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
(7)在形成前述结构的硅基衬底10上，在显示区域100、虚设像素区域200、阴极环300和金属走线区400形成封装层图案，封装层40为薄膜封装结构，如图13所示。
(8)在形成前述结构的硅基衬底10上，在显示区域100、虚设像素区域200、阴极环300和部分金属走线区400形成彩膜层50图案，显示区域100的彩膜层50包括相互间隔设置或相互交叠设置的第一颜色单元53、第二颜色单元54和第三颜色单元55，在一种示例性实施例中，显示区域100的颜色单元可以相互交叠作为黑矩阵，或者在颜色单元之间设置黑矩阵。虚设像素区域200、阴极环300和部分金属走线区400的彩膜层50包括叠层设置的 第一颜色单元53和第二颜色单元54，且在金属走线区400的金属走线对应的位置，彩膜层50设置有第一对位标记形状的开口52，如图14所示。在示例性实施方式中，第一颜色单元可以为绿色单元G，第二颜色单元可以为红色单元R，第三颜色单元可以为蓝色单元B。在一些可能的实现方式中，彩膜层50的制备过程包括：先形成蓝色单元B，然后形成红色单元R，然后形成绿色单元G。蓝色彩膜的粘附性较大，先形成蓝色单元B可以减小彩膜层50从阴极上剥离的可能性。由于红色单元R的粘附性较小，但流动性好，因而在形成红色单元R的过程中，可以减少蓝色单元B和红色单元R远离阴极一侧表面的气泡数量，从而可以提高蓝色单元B和红色单元R二者交叠位置处膜厚的均一性。由于绿色单元G的基体材料和红色单元R的基体材料大致相同，因而绿色单元G和红色单元R之间的粘附力较大，可以减小彩膜层50从阴极上剥离的可能性。在一些可能的实现方式中，彩膜层50可以包括其它颜色单元，例如白色或黄色等。
采用本公开的方法制作的显示基板，在下层反射金属层或阳极金属层上均不需制作绑定标记，而通过金属走线区上方的彩膜层制作绑定标记对应的开口，通过开口下侧的金属走线反光，在绑定机台的电荷耦合器件(charge coupled device，CCD)图像传感器下形成黑白分明的第一对位标记。考虑彩胶材料的流动性，目前彩胶曝光之后的制作误差约为0.2微米，而绑定机台的精度要求约为1微米，因此，通过彩膜层制作的第一对位标记，完全符合绑定机台对精度的要求。
后续工艺中，采用密封工艺形成盖板60，盖板60与硅基衬底10之间通过密封胶固定。完成上述工艺后，绑定区域300的膜层结构没有变化。由于硅基衬底10、盖板60和密封胶一起形成封闭的空间，因而提供了阻隔水氧的保障，使硅基OLED显示基板的寿命大幅提升。随后，对形成的显示母板进行切割，形成单独的显示基板。
通过本公开显示基板的结构及其制备过程可以看出，本公开通过在彩膜层与金属走线区相对的位置设置镂空的第一对位标记，可以使得金属走线区在镂空的第一对位标记处形成反光，在其他位置处由于彩膜层覆盖避免反光，即在第一对位标记的边缘处产生明显的灰度变化，从而可以准确的识别到第 一对位标记的边缘位置。通过该方式制作的第一对位标记，减少了电容击穿的风险，减小了基板的边缘区域，提高了基板的切割效率，且制备工艺简单可靠。
本公开的制备工艺可以利用成熟的制备设备实现，对工艺改进较小，兼容性高，工艺流程简便，易于设备周期性维护，生产效率高，生产成本低，良品率高，便于大规模量产，所制备的显示基板可以应用在虚拟现实设备或增强显示设备中，或应用在其它类型的显示装置中，具有良好的应用前景。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，每个显示单元微腔结构的长度可以相同，或者可以不同。又如，在显示区域形成反射电极的工艺中，绑定区域可以形成相应焊盘，本公开在此不做具体的限定。
本公开还提供了一种显示基板的制作方法，如图15所示，该制作方法包括步骤S1至步骤S3。
其中，步骤S1包括：提供显示基板母板，其中，显示基板母板包括至少一个显示基板区域，显示基板区域包括硅基衬底，硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线。
步骤S2包括：在硅基衬底上形成彩膜层，彩膜层包括第一对位标记，该第一对位标记为镂空结构；第一对位标记在硅基衬底上的投影和金属走线在硅基衬底上的投影包含重叠区域。
在一种示例性实施例中，显示区域的彩膜层包括成阵列设置的第一颜色单元、第二颜色单元和第三颜色单元，其中，第一颜色单元、第二颜色单元和第三颜色单元可以分别为红(R)色滤光单元(Color Filter，CF)、绿(G)色滤光单元和蓝(B)色滤光单元中的其中一种。
在一种示例性实施例中，显示区域之外的彩膜层包括依次叠层设置的第一颜色单元层和第二颜色单元层，第一颜色单元层和第二颜色单元层上包含相互贯穿的开孔，以通过开孔形成所述第一对位标记。在一些可能的实现方式中，第一颜色单元可以为蓝色滤光单元，第二颜色单元可以为红色滤光单 元。
在一种示例性实施例中，第一对位标记可以为绑定标记或其他任意类型的对位标记。
在一种示例性实施例中，第一对位标记在硅基衬底上的正投影的形状可以为十字形、矩形或其他任意的规则或不规则的形状。
在一种示例性实施方式中，第一对位标记的开口长度为50至150微米，第一对位标记的开口宽度为20至50微米，金属走线的宽度为50至150纳米，相邻金属走线的间隔为30至50纳米。
示例性的，第一对位标记为由横向开口和竖向开口组成的十字形结构，其中，横向开口和竖向开口的长度均为100微米，宽度均为30微米，一条金属走线的宽度为100纳米，相邻金属走线的间距为50纳米，多条金属走线通过集成电路集成在一起，由于多条金属走线密集排布，可以在彩膜层镂空的第一对位标记位置形成反光。
步骤S3包括：对显示基板母板进行切割以得到单独的显示基板。
本公开还提供了一种显示装置，包括前述的显示基板。显示装置可以为虚拟现实装置、增强现实装置或近眼显示装置，或者可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪，或任何其它具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种显示基板，包括：硅基衬底和设置在所述硅基衬底上的彩膜层，所述硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线，所述彩膜层包括第一对位标记，所述第一对位标记为镂空结构；
    所述第一对位标记在所述硅基衬底上的投影和所述金属走线在所述硅基衬底上的投影包含重叠区域。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域的彩膜层包括呈阵列排布的第一颜色单元、第二颜色单元和第三颜色单元；所述显示区域之外的彩膜层包括呈整面结构的第一颜色单元、第二颜色单元、第三颜色单元中的至少一种。
  3. 根据权利要求2所述的显示基板，其中，所述显示区域之外的彩膜层包括依次叠层设置的第一颜色单元层和第二颜色单元层，所述第一颜色单元层和第二颜色单元层上包含相互贯穿的开孔，以通过所述开孔形成所述第一对位标记。
  4. 根据权利要求3所述的显示基板，其中，所述第一颜色单元层为蓝色滤光单元层，所述第二颜色单元层为红色滤光单元层。
  5. 根据权利要求1所述的显示基板，其中，所述第一对位标记的长度为50至150微米，所述第一对位标记的宽度为20至50微米，所述金属走线的宽度为50至150纳米，相邻金属走线的间隔为30至50纳米。
  6. 根据权利要求5所述的显示基板，其中，所述第一对位标记暴露出的金属走线的面积与所述第一对位标记的面积的比值大于或等于80％。
  7. 根据权利要求1所述的显示基板，其中，所述显示区域包括设置在硅基衬底上的发光结构层，所述发光结构层包括依次叠层设置的反射层、阳极层、有机发光层和阴极层；
    所述显示区域的硅基衬底内设置有驱动电路层，所述驱动电路层包括第 一扫描线、第一电源线、数据线、开关晶体管和驱动晶体管，所述开关晶体管的控制极与第一扫描线连接，所述开关晶体管的第一极与数据线连接，所述开关晶体管的第二极与驱动晶体管的控制极连接，所述驱动晶体管的第一极与第一电源线连接，所述开关晶体管被配置为在第一扫描线输出的第一扫描信号控制下，接收数据线传输的数据信号，使驱动晶体管的控制极接收所述数据信号，所述驱动晶体管被配置为在其控制极所接收的数据信号控制下，在第二极产生相应的电流；
    所述金属走线和所述驱动电路层同层设置。
  8. 根据权利要求1所述的显示基板，其中，所述阴极环包括设置在硅基衬底上的供电电极层、设置在所述供电电极层远离硅基衬底一侧的反射层、设置在所述反射层远离供电电极层一侧的阳极层以及设置在所述阳极层远离反射层一侧的阴极层。
  9. 根据权利要求1所述的显示基板，其中，所述绑定区域包括设置在所述硅基衬底上的绑定电极层以及覆盖绑定电极层的绝缘层，所述绝缘层上开设有暴露出绑定电极层内的绑定电极的过孔。
  10. 根据权利要求9所述的显示基板，其中，所述绑定区域还包括设置在所述硅基衬底上的第二对位标记层，所述第二对位标记层和所述绑定电极层同层设置。
  11. 一种显示装置，包括：如权利要求1至10任一所述的显示基板。
  12. 一种显示基板的制作方法，包括：
    提供显示基板母板，其中，所述显示基板母板包括至少一个显示基板区域，所述显示基板区域包括硅基衬底，所述硅基衬底内包含用于分别将显示区域和阴极环与绑定区域相连接的多条金属走线；
    在所述硅基衬底上形成彩膜层，所述彩膜层包括第一对位标记，所述第一对位标记为镂空结构；所述第一对位标记在所述硅基衬底上的投影和所述金属走线在所述硅基衬底上的投影包含重叠区域；
    对所述显示基板母板进行切割以得到单独的显示基板。
  13. 根据权利要求12所述的制作方法，其中，所述显示区域的彩膜层包括呈阵列排布的第一颜色单元、第二颜色单元和第三颜色单元；所述显示区域之外的彩膜层包括呈整面结构的第一颜色单元、第二颜色单元、第三颜色单元中的至少一种。
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