WO2022204918A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022204918A1
WO2022204918A1 PCT/CN2021/083843 CN2021083843W WO2022204918A1 WO 2022204918 A1 WO2022204918 A1 WO 2022204918A1 CN 2021083843 W CN2021083843 W CN 2021083843W WO 2022204918 A1 WO2022204918 A1 WO 2022204918A1
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Prior art keywords
layer
pixel opening
sub
electrode
opening area
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PCT/CN2021/083843
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English (en)
French (fr)
Inventor
张月
崔颖
孙力
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京东方科技集团股份有限公司
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Priority to DE112021001208.8T priority Critical patent/DE112021001208T5/de
Priority to PCT/CN2021/083843 priority patent/WO2022204918A1/zh
Priority to US17/634,558 priority patent/US20230363203A1/en
Priority to CN202180000636.4A priority patent/CN115485850A/zh
Publication of WO2022204918A1 publication Critical patent/WO2022204918A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/125—Deposition of organic active material using liquid deposition, e.g. spin coating using electrolytic deposition e.g. in-situ electropolymerisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • TFT thin film transistor
  • the present disclosure provides a display substrate, comprising a substrate, a driving circuit layer disposed on the substrate, and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer including transistors, the light emitting
  • the structural layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode ;
  • the pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, the height of the first retaining walls is less than the height of the second retaining walls, the first retaining walls and the second retaining walls
  • the intersection defines a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, the area of the first pixel opening area is larger than the area of the second pixel opening area, and the two pixel opening areas are
  • the second retaining walls extend along the second direction, a plurality of the second retaining walls are arranged in sequence along the first direction, and there are a plurality of edges between two adjacent second retaining walls. the first retaining walls arranged in sequence in the second direction, the first direction and the second direction intersect;
  • the second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, and the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions alternately arranged, The first bent portion extends toward the first direction, and the second extension portion extends toward the second direction.
  • the two adjacent first bending parts of the same first sub-retaining wall, the second extending part between the two adjacent first bending parts, and A second sub-retaining wall adjacent to the first sub-retaining wall and a first retaining wall between the first sub-retaining wall and the second sub-retaining wall enclose a first pixel opening area
  • first blocking wall between the sub-blocking wall and the second sub-blocking wall encloses one of the second pixel opening areas.
  • the plurality of first bending portions of the plurality of first sub-retaining walls have the same bending times and bending directions.
  • the width of the second blocking wall along the first direction is between 1/3 and 2/3 of the width of the first bending portion along the first direction.
  • the height of the first retaining wall is less than or equal to 1 ⁇ m, and the height of the second retaining wall is 1.2 ⁇ m to 1.5 ⁇ m.
  • the width of the first retaining wall is smaller than the width of the second retaining wall.
  • the material of the first retaining wall is a lyophilic material
  • the material of the second retaining wall is a lyophobic material
  • the first electrodes of all sub-pixels have the same width along the first direction, the first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction, and adjacent rows of first electrodes are arranged in a matrix along the first and second directions.
  • the distances between the first electrodes are equal, and the distance between the first electrodes in the (2n+1)th column and the first electrodes in the (2n+2)th column is greater than that in the (2n+2)th column
  • the distance between the first electrode and the first electrode in the (2n+3)th column, n is an integer greater than or equal to 0.
  • the first pixel opening area includes a light-emitting area and a non-light-emitting area
  • the second pixel opening area only includes a light-emitting area
  • the orthographic projection of the light-emitting area on the substrate is the same as that of the first electrode on the substrate.
  • the orthographic projection on the substrate coincides, and the orthographic projection of the non-light-emitting region on the substrate has no overlapping area with the orthographic projection of the first electrode on the substrate.
  • the widths of the first electrodes of adjacent sub-pixels along the first direction are different, the first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction, and all the first electrodes of adjacent rows are arranged in a matrix along the first direction and the second direction.
  • the distances between the first electrodes are equal, and the distances between the first electrodes in adjacent columns are equal.
  • the width of the second pixel opening area along the first direction is between 1/3 and 2/3 of the width of the first pixel opening area along the first direction.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate, comprising:
  • the driving circuit layer including transistors
  • a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the The organic light-emitting layer is located between the first electrode and the second electrode;
  • the pixel definition layer includes a plurality of first blocking walls and a plurality of second blocking walls, and the height of the first blocking walls is smaller than that of the second blocking walls
  • the height of the wall, the intersection of the first retaining wall and the second retaining wall defines a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, and the first pixel opening area is The area is larger than that of the second pixel opening area, and two adjacent first pixel opening areas and the second pixel opening area are separated by the first blocking wall.
  • forming a light emitting structure layer on the driving circuit layer includes:
  • a pixel definition layer pattern is formed through a halftone mask patterning process
  • the organic light-emitting layer pattern is formed by an inkjet printing process, and during inkjet printing, the organic light-emitting layer material ink is only printed to the opening area of the first pixel;
  • a second electrode pattern is formed on the organic light emitting layer.
  • forming a light emitting structure layer on the driving circuit layer includes:
  • the organic light-emitting layer pattern is formed by an inkjet printing process, and during inkjet printing, the organic light-emitting layer material ink is only printed to the opening area of the first pixel;
  • a second electrode pattern is formed on the organic light emitting layer.
  • the organic light-emitting layer pattern is formed by an inkjet printing process, including any one or more of the following:
  • the hole injection material ink flows to the second pixel opening area adjacent to the first pixel opening area, and drying to remove the
  • the hole injection layer pattern is formed by post-baking the solvent of the hole injection material ink
  • the hole transport layer pattern is formed by post-baking the solvent of the ink
  • the luminescent material ink is inkjet printed in the first pixel opening area, the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area, and the solvent of the luminescent material ink is dried and removed, and then baked to form luminescence. layer pattern.
  • the second retaining walls extend along the second direction, a plurality of the second retaining walls are arranged in sequence along the first direction, and there are a plurality of edges between two adjacent second retaining walls. the first retaining walls arranged in sequence in the second direction, the first direction and the second direction intersect;
  • the second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, and the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions alternately arranged, The first bent portion extends toward the first direction, and the second extension portion extends toward the second direction.
  • Figure 1 is a schematic diagram of the calculation principle of the highest resolution of the substrate that can be printed by the printing device
  • FIG. 2 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure
  • Fig. 3 and Fig. 4 are two kinds of sectional structure schematic diagrams of AA' area in Fig. 2;
  • Fig. 5 is two kinds of sectional structure schematic diagrams of BB' region in Fig. 2;
  • FIG. 6 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 7 is a schematic diagram after forming a driving circuit layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram after forming a first electrode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of the first electrode pattern shown in FIG. 8.
  • FIG. 10 is another schematic diagram after forming a first electrode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic plan view of the first electrode pattern shown in FIG. 10;
  • FIG. 12 is a schematic diagram after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of another exemplary embodiment of the present disclosure after forming a pixel definition layer pattern
  • FIG. 14 is a schematic plan view of the pixel definition layer pattern shown in FIG. 12 or FIG. 13;
  • FIG. 15 and FIG. 16 are schematic plan views of the first electrode and pixel definition layer patterns formed by two exemplary embodiments of the present disclosure
  • FIG. 17 is a schematic diagram of forming an organic light-emitting layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of another exemplary embodiment of the present disclosure after forming a pattern of an organic light-emitting layer
  • FIG. 19 is a schematic diagram after forming a second electrode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 20 is another schematic diagram after forming a second electrode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • the film forming method of OLED mainly includes an evaporation process or a solution process.
  • the evaporation process is relatively mature in small-scale applications, and this technology has been used in mass production.
  • the solution process OLED film forming methods mainly include inkjet printing, nozzle coating, spin coating, screen printing, etc. Among them, inkjet printing technology is considered to be a large-scale OLED due to its high material utilization rate and large-scale size. An important way to achieve mass production.
  • the printer is used to print a display substrate with a higher resolution than the highest resolution it can print itself, there is a risk of ink overflow.
  • An embodiment of the present disclosure provides a display substrate, including a substrate, a driving circuit layer disposed on the substrate, and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer including transistors, and
  • the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the organic light-emitting layer is located on the first electrode and the second electrode between;
  • the pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, the height of the first retaining walls is less than the height of the second retaining walls, and the intersection of the first retaining walls and the second retaining walls defines a plurality of pixel openings area, the pixel opening area includes a first pixel opening area and a second pixel opening area, the area of the first pixel opening area is larger than the area of the second pixel opening area, and the two adjacent first pixel opening areas and the second pixel opening area are The two pixel opening regions are separated by a first barrier wall.
  • two kinds of retaining walls with different heights are used to enclose a first pixel opening area and a second pixel opening area with different areas, and the ink is only printed to the first pixel opening area during inkjet printing.
  • the height of the first retaining wall is relatively low, and the ink in the opening area of the first pixel can flow into the opening area of the second pixel adjacent to it, thus effectively avoiding the problem of low pixel resolution in order to prevent the overflow of ink, and thus can
  • the process defects are obviously improved, the processing yield is improved, and the distance between the adjacent sub-pixel openings can be reduced to improve the resolution and display quality.
  • FIGS. 3 and 4 are schematic views of two cross-sectional structures of the AA' region of the display substrate shown in FIG. 2
  • FIG. 5 is the BB' region of the display substrate shown in FIG. 2 . Schematic diagram of the cross-sectional structure. As shown in FIGS.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 that emits light of a first color,
  • the second light-emitting unit P2 that emits light of the second color and the third light-emitting unit P3 that emits light of the third color, the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 all include pixel driving circuits and light-emitting devices.
  • the pixel driving circuits in the first light emitting unit P1, the second light emitting unit P2 and the third light emitting unit P3 are respectively connected with the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of the light-emitting unit, and the light-emitting devices are configured to respond to the current output by the pixel driving circuit of the light-emitting unit. Brightness of light.
  • the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit and white light-emitting units, which are not limited in the present disclosure.
  • the shape of the light emitting unit in the pixel unit may be a rectangle shape, a diamond shape, a pentagon shape or a hexagon shape.
  • the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally, vertically, or in a square pattern.
  • the pixel unit includes four light-emitting units, the four light-emitting units can be horizontally, vertically, or square. (Square) arrangement, which is not limited in the present disclosure.
  • FIG. 3 and FIG. 4 only illustrate the structure of three sub-pixels in the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 10 , a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10 , and The encapsulation layer 104 is disposed on the side of the light emitting structure layer 103 away from the substrate 10 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • substrate 10 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit.
  • each sub-pixel includes one transistor 101 as an example for illustration.
  • the light-emitting structure layer 103 may include a first electrode 21, a pixel definition layer, an organic light-emitting layer, and a second electrode 26.
  • the first electrode 21 is connected to the drain electrode of the transistor 101 through a via hole
  • the organic light-emitting layer is connected to the first electrode 21, and the first electrode 21 is connected to the drain electrode of the transistor 101 through a via hole.
  • the two electrodes 26 are connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the driving of the first electrode 21 and the second electrode 26 .
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the pixel definition layer includes a plurality of first retaining walls 22a and a plurality of second retaining walls 22b, the height of the first retaining walls 22a is smaller than that of the second retaining walls 22b, and the A blocking wall 22a and the second blocking wall 22b intersect to define a plurality of pixel opening areas.
  • the pixel opening areas include a first pixel opening area 221 and a second pixel opening area 222.
  • the area of the first pixel opening area 221 is larger than that of the second pixel opening area.
  • the area of the region 222 is separated from two adjacent first pixel opening regions 221 and second pixel opening regions 222 by the first blocking wall 22a.
  • the first blocking walls 22a extend along the first direction D1
  • the plurality of first blocking walls 22a are arranged in sequence along the second direction D2
  • the second blocking walls 22b are arranged along the second direction D2 extends
  • a plurality of second retaining walls 22b are arranged in sequence along the first direction D1
  • a plurality of first retaining walls 22a are arranged in sequence along the second direction D2 between two adjacent second retaining walls 22b.
  • a direction D1 and a second direction D2 intersect;
  • the second retaining wall 22b includes first sub-retaining walls 22b1 and second sub-retaining walls 22b2 arranged at intervals, and the first sub-retaining wall 22b1 has a plurality of first bending portions 22b1a and a plurality of second extending portions alternately arranged 22b1b, the first bending portion 22b1a extends in the first direction D1, the second extending portion 22b1b extends in the second direction D2, and the second sub-retaining wall 22b2 extends in the second direction D2.
  • the first direction D1 is the same as the extending direction of the gate lines
  • the second direction D2 is the same as the extending direction of the data lines.
  • the first direction D1 and the second direction D2 may be perpendicular to each other.
  • the first pixel opening areas 221 and the second pixel opening areas 222 are alternately arranged along the second direction D2, the colors of the sub-pixels in the same column of sub-pixels are the same, and the sub-pixels in the same column of sub-pixels have the same color. Adjacent sub-pixels are separated by the first blocking wall 22a.
  • the first pixel opening areas 221 and the second pixel opening areas 222 are alternately arranged along the first direction D1, the colors of adjacent sub-pixels in the same row of sub-pixels are different, and the same row of sub-pixels has different colors. Adjacent sub-pixels in the sub-pixels are separated by second blocking walls 22b.
  • the second extension between two adjacent first bending parts 22b1a of the same first sub-retaining wall 22b1 and two adjacent first bending parts 22b1a The portion 22b1b, the second sub-retaining wall 22b2 adjacent to the first sub-retaining wall 22b1, and the first sub-retaining wall 22a between the first sub-retaining wall 22b1 and the second sub-retaining wall 22b2 enclose a first pixel opening area 221 ;
  • the first blocking wall 22a between 22b1 and the second sub-blocking wall 22b2 encloses a second pixel opening area 222 .
  • the plurality of first bending portions 22b1a of the plurality of first sub-retaining walls 22b1 are bent in the same number of times and in the same direction.
  • the width of the first retaining wall 22a is smaller than the width of the second retaining wall 22b.
  • the first blocking wall 22a since the first blocking wall 22a only needs to separate the first electrodes 21 in adjacent sub-pixels, and does not need to separate the organic light-emitting layer, the first blocking wall 22a can be designed as narrow as possible.
  • the second barrier wall 22b needs to separate the organic light emitting layers of adjacent sub-pixels, therefore, the width of the second barrier wall 22b may be greater than that of the first barrier wall 22a.
  • the material of the first retaining wall 22a is a material with lyophilic properties
  • the material of the second retaining wall 22b is a material with lyophobic properties.
  • the width of the first electrode 21 exposed by the first pixel opening area 221 is greater than or equal to the width of the first electrode 21 exposed by the second pixel opening area 222 .
  • the width of the first electrode 21 exposed by the first pixel opening area 221 is equal to the width of the first electrode 21 exposed by the second pixel opening area 222 , the The light-emitting regions of the plurality of sub-pixels have the same width.
  • the first pixel opening region 221 is divided into a light-emitting region and a non-light-emitting region, and only the first electrode 21 and the corresponding transistor 101 connected to the first electrode 21 are arranged under the light-emitting region. There is no first electrode or a transistor connected to the first electrode under the non-light-emitting area. This solution can keep the sizes of the three sub-pixels consistent, and make the display edge smoother.
  • the width of the first electrode 21 exposed by the first pixel opening area 221 is greater than the width of the first electrode 21 exposed by the second pixel opening area 222 , the first pixel opening area in each pixel unit
  • the width of the light-emitting area of the sub-pixels of 221 is larger than the width of the light-emitting area of the sub-pixels of the second pixel opening area 222 .
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 6 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 6 , the pixel driving circuit has a 3T1C structure, which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
  • 3T1C structure which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is coupled to the first scan line Gn
  • the first electrode of the first transistor T1 is coupled to the data line Dn
  • the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2
  • the first transistor T1 is used for receiving the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, and the second electrode of the second transistor T2 is coupled to the second electrode of the OLED One pole, the second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is coupled to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the first electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2.
  • the three transistors T3 are used to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.
  • the first pole of the OLED is coupled to the second pole of the second transistor T2, the second pole of the OLED is coupled to the second power line VSS, and the OLED is used for responding to the current of the second pole of the second transistor T2 to emit corresponding brightness.
  • the first pole of the storage capacitor C ST is coupled to the gate electrode of the second transistor T2, the second pole of the storage capacitor C ST is coupled to the second pole of the second transistor T2, and the storage capacitor C ST is used to store the second transistor T2 the gate electrode potential.
  • the signal of the first power supply line VDD is a high-level signal continuously provided
  • the signal of the second power supply line VSS is a low-level signal.
  • the first to third transistors T1 to T3 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode) 21 , an organic light emitting layer and a second electrode (cathode) 26 .
  • OLED organic electroluminescent diode
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • a manufacturing process of a display substrate may include the following operations.
  • the driving circuit layer 102 includes a plurality of gate lines and a plurality of data lines, and the intersection of the plurality of gate lines and the plurality of data lines defines a plurality of pixel units arranged in a matrix, each pixel unit includes at least 3 sub-pixels, and each sub-pixel includes Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • one pixel unit includes three sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively.
  • the solution in this embodiment is also applicable to the case where one pixel unit includes 4 sub-pixels (a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W).
  • substrate 10 may be a flexible substrate, or may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and then forming a first flexible (PI1) layer after curing into a film; Subsequently, a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; and then an amorphous silicon film is deposited on the first barrier layer to form a barrier layer covering the first barrier layer.
  • Amorphous silicon (a-si) layer then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; then a layer is deposited on the second flexible layer A barrier film is formed to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate 10 is completed.
  • a-si Amorphous silicon
  • PI2 polyimide
  • the preparation process of the driving circuit layer 102 may include:
  • a shielding film is deposited on the substrate 10 , and the shielding film is patterned through a patterning process to form a shielding layer pattern disposed on the substrate 10 .
  • a first insulating film and a semiconductor film are sequentially deposited, and the semiconductor film is patterned by a patterning process to form a first insulating layer covering the shielding layer pattern, and a semiconductor layer pattern disposed on the first insulating layer, and the semiconductor layer pattern At least the active layer is included, and the orthographic projection of the active layer on the substrate 10 is within the range of the orthographic projection of the blocking layer on the substrate 10 .
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer disposed on the pattern of the semiconductor layer, and a second insulating layer disposed on the second insulating layer.
  • a metal layer pattern, the first metal layer pattern at least includes a gate electrode, the orthographic projection of the second insulating layer on the substrate 10 is within the range of the orthographic projection of the active layer on the substrate 10 , and the orthographic projection of the gate electrode on the substrate 10 The projection is within the range of the orthographic projection of the second insulating layer on the substrate 10 .
  • a third insulating film is deposited, and the third insulating film is patterned through a patterning process to form a third insulating layer covering the pattern of the first metal layer, and an active via pattern is opened on the third insulating layer.
  • Two active via holes are located at two ends of the active layer, and the third insulating layer in the active via holes is etched away to expose the surface of the active layer.
  • a second metal film is deposited, the second metal film is patterned by a patterning process, and a second metal layer pattern is formed on the third insulating layer, the second metal layer pattern at least includes a source electrode, a drain electrode, a source electrode and a The drain electrodes are respectively connected to the active layer through active via holes.
  • a flat film is coated, and the flat film is patterned by a patterning process to form a flat layer covering the pattern of the second metal layer, an anode via pattern is opened on the flat layer, and the flat layer in the anode via is etched away , exposing the surface of the drain electrode.
  • the pattern of the driving circuit layer 102 is prepared on the substrate 10 , as shown in FIG. 7 .
  • an active layer, a gate electrode, a source electrode, and a drain electrode constitute the transistor 101 .
  • the transistor 101 may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (Thin Film Transistor, TFT).
  • TFT Thin Film Transistor
  • the first insulating layer, the second insulating layer, and the third insulating layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • the first insulating layer is called a buffer layer
  • the second insulating layer is called a gate insulating (GI) layer
  • the third insulating layer is called an interlayer insulating (ILD) layer.
  • the flat film can be made of organic materials such as resins.
  • the first metal thin film and the second metal thin film may adopt a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or
  • the alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • the shielding film can be made of a metal material, or an opaque non-metallic material.
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • a first electrode 21 pattern is formed on the substrate on which the aforementioned pattern is formed.
  • forming the first electrode 21 pattern may include: depositing a first transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first transparent conductive film through a patterning process to form the first electrode 21 pattern , the first electrode 21 of each sub-pixel is connected to the drain electrode of the thin film transistor in the sub-pixel, as shown in FIG. 8 to FIG. 9 or FIG. 10 to FIG. 11 .
  • the width a1 of the first electrodes 21 of all sub-pixels along the first direction D1 is the same, and the first electrodes 21 of all sub-pixels along the first direction D1 and the second direction D1
  • the direction D2 is arranged in a matrix, the distance b1 between the first electrodes 21 in adjacent rows is equal, and the distance between the first electrodes 21 in the (2n+1)th column and the first electrodes 21 in the (2n+2)th column is equal.
  • the distance c1 is greater than the distance d1 between the first electrode 21 of the (2n+2)th column and the first electrode 21 of the (2n+3)th column, and n is an integer greater than or equal to 0.
  • the first transparent conductive film may use indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the widths of the first electrodes 21 of adjacent sub-pixels along the first direction D1 are different, and among the first electrodes 21 of every two adjacent sub-pixels, one The width of the electrode 21 along the first direction D1 is a2, the width of the other electrode 21 along the first direction D1 is b2, a2>b2, the first electrodes 21 of all sub-pixels are in a matrix along the first direction D1 and the second direction D2 Arrangement, the distances c2 between the first electrodes 21 in adjacent rows are equal, and the distances d2 between the first electrodes 21 in adjacent columns are equal.
  • the first electrode 21 can also use a metal with high reflectivity, such as silver Ag, gold Au, palladium Pd, platinum Pt, etc., or an alloy of these metals, or a composite layer of these metals, or The composite layer structure of indium tin oxide ITO layer and metal reflective layer is adopted, which has good electrical conductivity, high reflectivity and good morphological stability.
  • a metal with high reflectivity such as silver Ag, gold Au, palladium Pd, platinum Pt, etc., or an alloy of these metals, or a composite layer of these metals, or The composite layer structure of indium tin oxide ITO layer and metal reflective layer is adopted, which has good electrical conductivity, high reflectivity and good morphological stability.
  • a pixel definition layer pattern is formed on the substrate on which the aforementioned pattern is formed.
  • the pixel definition layer is used to define a light-emitting region in each sub-pixel, and the light-emitting region exposes the first electrode 21 , as shown in FIGS. 12 to 16 .
  • forming the pattern of the pixel definition layer includes: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and using a halftone mask to expose the pixel definition film once and then form the film including the first
  • the pixels of the retaining wall 22a and the second retaining wall 22b define the layer pattern.
  • forming the pattern of the pixel definition layer includes: coating a first pixel definition film on the substrate on which the aforementioned pattern is formed, and exposing and developing the first pixel definition film with a single-tone mask to form the first pixel definition film.
  • the pixel definition layer includes a plurality of first blocking walls 22a extending along a first direction D1 and a plurality of second blocking walls 22b extending along a second direction D2, the first direction D1 and the second direction D2
  • the intersection, the intersection of the first blocking wall 22a and the second blocking wall 22b define a plurality of pixel opening areas, and the pixel opening areas include the first pixel opening area 221 and the second pixel opening area 222, the first pixel opening area 221 and the second pixel opening area 221 and the second pixel opening area.
  • the opening regions 222 are alternately arranged along the second direction D2 , and the area of the first pixel opening region 221 is larger than that of the second pixel opening region 222 .
  • the second retaining wall 22b includes first sub-retaining walls 22b1 and second sub-retaining walls 22b2 that are arranged at intervals, wherein the first sub-retaining wall 22b1 has a plurality of first bends that are alternately arranged
  • the portion 22b1a and the plurality of second extension portions 22b1b, the first bent portion 22b1a extends in the first direction D1, and the second extension portion 22b1b extends in the second direction D2.
  • the two adjacent first bending parts 22b1a of the same first sub-retaining wall 22b1, the second extending part 22b1b between the two adjacent first bending parts 22b1a, and the second A second sub-retaining wall 22b2 adjacent to a sub-retaining wall 22b1 and the first retaining wall 22a between the first sub-retaining wall 22b1 and the second sub-retaining wall 22b2 enclose a first pixel opening area 221;
  • the first blocking wall 22a between the wall 22b1 and the second sub-blocking wall 22b2 encloses a second pixel opening area 222 .
  • the width a3 of the second blocking wall 22b along the first direction D1 is between 1/3 and 2/3 of the width b3 of the first bending portion 22b1a along the first direction D1.
  • the width d3 of the second pixel opening area 222 along the first direction D1 is between 1/3 and 2/3 of the width d4 of the first pixel opening area 221 along the first direction D1.
  • the height of the first retaining wall 22a is less than the height of the second retaining wall 22b.
  • the height of the first retaining wall 22a is less than 1 micron.
  • the height of the second retaining wall 22b is 1.2 micrometers to 1.5 micrometers.
  • the ink in the second pixel opening area 222 flows from the ink in the first pixel opening area 221. Therefore, the first block The wall 22a does not need to consider the overflow of the ink.
  • the first blocking wall 22a only needs to isolate the first electrodes 21 of the adjacent sub-pixels.
  • the width c3 of the first blocking wall 22a along the second direction D2 can be designed as much as possible. narrow, thereby increasing pixel resolution.
  • the first blocking wall 22a only needs to cover the edges of two adjacent first electrodes 21 , for example, covering the edges of the first electrodes and extending inwardly within a range of less than 3 microns, and further, may be less than 2 microns .
  • the second blocking wall 22b covers the edges of two adjacent first electrodes 21, for example, covers the edges of the first electrodes and extends inwardly within a range of less than 4 micrometers, further, may be less than 3 micrometers, further , can be smaller than 2 microns.
  • the size of the second barrier wall 22b covering the edge of the first electrode may be greater than or equal to the size of the first barrier wall 22a covering the edge of the first electrode.
  • the material of the first retaining wall 22a is a material with lyophilic properties
  • the material of the second retaining wall 22b is a material with lyophobic properties.
  • the plurality of first bending portions 22b1a of the plurality of first sub-retaining walls 22b1 have the same bending frequency and bending direction.
  • the plurality of first bending portions 22b1a of the plurality of first sub-retaining walls 22b1 are all bent to the left, to the right, and to the left
  • the bending sequence of bending, bending to the right that is, the bending times and bending directions of the plurality of first bending portions 22b1a of the plurality of first sub-retaining walls 22b1 are the same, so that the first retaining walls 22a are
  • the first pixel opening areas 221 and the second pixel opening areas 222 defined by crossing the second blocking wall 22b are alternately arranged along the first direction D1.
  • the second blocking wall 22b Since the ink is only printed to the first pixel opening area 221 when the organic light emitting layer is printed, and the ink in the second pixel opening area 222 flows from the ink in the first pixel opening area 221, the second blocking wall 22b only needs to consider For the problem of the overflow of the ink on one side, the width a3 of the second blocking wall 22b along the first direction D1 can be designed to be narrower. In addition, the first blocking wall 22a only needs to separate the first electrodes 21 in adjacent sub-pixels, and does not need to separate the organic light-emitting layer. Therefore, the width c3 of the first blocking wall 22a along the second direction D2 can be designed as much as possible narrow, thus greatly improving the pixel resolution.
  • the width a3 of the second blocking wall 22b along the first direction D1 is 5 to 30 micrometers.
  • the width a3 of the second blocking wall 22b along the first direction D1 is 5 ⁇ m to 10 ⁇ m.
  • the shapes of the first pixel opening area 221 and the second pixel opening area 222 may be a triangle, a rectangle, a polygon, a circle, an ellipse, or the like.
  • the cross-sectional shape of the first pixel opening area 221 and the second pixel opening area 222 may be a rectangle or a trapezoid or the like.
  • the organic light-emitting layer pattern is formed on the substrate on which the aforementioned pattern is formed.
  • forming the pattern of the organic light emitting layer may include: inkjet printing the hole injection material ink on the first pixel opening area 221. Since the first blocking wall 22a is a lyophilic material and has a low height, hole injection The material ink flows to the second pixel opening area 222 adjacent to the first pixel opening area 221, and the hole injection material ink is dried to remove the solvent and then baked to form a hole injection layer 23 pattern;
  • the hole transport material ink is inkjet printed on the first pixel opening area 221. Since the first retaining wall 22a is a lyophilic material and has a low height, the hole transport material ink flows to the first pixel opening area 221 adjacent to the first pixel opening area 221. The two pixel opening areas 222 are dried to remove the solvent of the hole transport material ink and then baked to form the hole transport layer 24 pattern;
  • the luminescent material ink is inkjet-printed on the first pixel opening area 221. Since the first retaining wall 22a is a lyophilic material and has a low height, the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area 221. 222 , drying to remove the solvent of the light-emitting material ink, and then baking to form a pattern of the light-emitting layer 25 , as shown in FIG. 17 to FIG. 18 .
  • the organic light-emitting layer includes the above-mentioned hole injection layer (Hole Injection Layer, HIL) 23, hole transport layer (Hole Transport Layer, HTL) 24, light-emitting layer (Emitting Layer, EML) 25
  • it can also include any one or more of the following: an electron blocking layer (Electron Block Layer, EBL), a hole blocking layer (Hole Block Layer, HBL), an electron transport layer (Electron Transport Layer, ETL) and electron injection Layer (Electron Injection Layer, EIL).
  • the electron blocking layer, the hole blocking layer, the electron transport layer and the electron injection layer may be formed by using an open mask (Open Mask) evaporation.
  • the electron blocking layer can be used as a microcavity adjustment layer of the light emitting device, and by designing the thickness of the electron blocking layer, the thickness of the organic light emitting layer between the cathode and the anode can meet the design of the microcavity length.
  • a hole transport layer, a hole blocking layer or an electron transport layer in the organic light emitting layer may be used as the microcavity adjustment layer of the light emitting device, which is not limited in the present disclosure.
  • the light emitting layer may include a host material and a dopant material doped in the host material, and the doping ratio of the guest material in the light emitting layer is 1% to 20%.
  • the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light; ”, which effectively improves the fluorescence quenching caused by the collision between the molecules of the light-emitting layer and the guest materials and the collision between the energies, and improves the luminous efficiency and device life.
  • the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage.
  • the thickness of the light emitting layer may be about 10 nm to 50 nm.
  • the hole injection layer may employ inorganic oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide , tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or p-type dopants and hole transport material dopants of strong electron withdrawing systems may be employed.
  • the thickness of the hole injection layer may be about 5 nm to 20 nm.
  • the hole transport layer may use a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methyl fluorene, spirofluorene , dibenzothiophene or furan, etc.
  • the thickness of the hole transport layer may be about 40 nm to 150 nm.
  • the hole blocking layer and the electron transport layer may employ an aromatic heterocyclic compound such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazophenanthridine derivatives and other imidazole derivatives; pyrimidines Derivatives, triazine derivatives and other azine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives and other compounds containing a nitrogen-containing six-membered ring structure (also including phosphine oxides on the heterocyclic ring) Substituent compounds) etc.
  • the thickness of the hole blocking layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.
  • the electron injection layer may adopt alkali metals or metals, such as materials such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals Wait.
  • the electron injection layer may have a thickness of about 0.5 nm to 2 nm.
  • a second electrode 26 pattern is formed on the substrate on which the aforementioned pattern is formed.
  • forming the pattern of the second electrode 26 may include: evaporating a second electrode material on the substrate formed with the aforementioned pattern to form a pattern of the second electrode 26, and the second electrode 26 is connected to the light emitting layer 25, as shown in FIG. 19 . as shown in Figure 20.
  • the second electrode 26 may be a unitary structure that communicates together.
  • the pattern of the light-emitting structure layer 103 is prepared on the driving circuit layer 102.
  • the light-emitting structure layer 103 includes the first electrode 21, the pixel definition layer, the organic light-emitting layer and the second electrode 26. The two electrodes 26 are connected.
  • a pattern of the encapsulation layer 104 is formed on the substrate on which the aforementioned pattern is formed, as shown in FIG. 3 or FIG. 4 .
  • Forming the pattern of the encapsulation layer 104 may include: first, using an open mask to deposit a first inorganic thin film by plasma-enhanced chemical vapor deposition (PECVD) to form the first encapsulation layer 401 . Subsequently, an organic material is inkjet printed on the first encapsulation layer 401 by an inkjet printing process, and after curing to form a film, a second encapsulation layer 402 is formed.
  • PECVD plasma-enhanced chemical vapor deposition
  • the first encapsulation layer 401 and the third encapsulation layer 403 may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which may be It is a single layer, a multi-layer or a composite layer.
  • the second encapsulation layer 402 can be made of resin material to form a laminated structure of inorganic material/organic material/inorganic material.
  • the organic material layer is arranged between the two inorganic material layers, which can ensure the external Water vapor cannot enter the light emitting structure layer 103 .
  • a touch structure layer may be formed on the encapsulation layer 104, and the touch structure layer may include a touch electrode layer, or a touch electrode layer and a touch insulating layer.
  • the preparation process of the display substrate may include processes such as peeling off the glass carrier, attaching the back film, cutting, etc., which are not limited in the present disclosure.
  • the exemplary embodiment of the present disclosure forms two kinds of retaining walls with different heights (and lyophilicity),
  • the first pixel opening area 221 and the second pixel opening area 222 are alternately arranged.
  • the organic light-emitting layer is printed, the ink is only printed to the first pixel opening area 221, and the ink in the first pixel opening area 221 can flow to the second pixel.
  • the pixels in the second pixel opening area 222 can be designed as narrow as possible, and since the ink in the second pixel opening area 222 flows from the first pixel opening area 221, the first pixel opening area 221
  • the first blocking wall 22a does not need to consider the overflow of ink on both sides, therefore, the first blocking wall 22a can be designed as narrow as possible, and the second blocking wall 22b only considers the overflow of ink on one side. Therefore, the second blocking wall 22b can also be designed to be narrower, so as to improve the pixel resolution, solve the problem caused by the error of the ink ejection amount among multiple nozzles, and help to improve the display quality.
  • Exemplary embodiments of the present disclosure show that the preparation method of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, convenient printing mass production, and high yield.
  • the structures and the preparation process thereof shown in the exemplary embodiments of the present disclosure are merely exemplary descriptions. In the exemplary embodiments, corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
  • the transistors in the driving circuit layer 102 may be of a top-gate structure, or may be of a bottom-gate structure, may be of a single-gate structure, or may be of a double-gate structure.
  • the driving circuit layer 102 and the light emitting structure layer 103 may also be provided with other film layer structures, electrode structures or lead structures.
  • the substrate 10 may be a glass substrate, which is not specifically limited in the present disclosure.
  • the present disclosure also provides a preparation method of a display substrate.
  • the preparation method may include:
  • the driving circuit layer including transistors
  • a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the The organic light-emitting layer is respectively connected with the first electrode and the second electrode;
  • the pixel definition layer includes a plurality of first blocking walls and a plurality of second blocking walls, and the height of the first blocking walls is smaller than that of the second blocking walls
  • the height of the wall, the intersection of the first retaining wall and the second retaining wall defines a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, and the first pixel opening area is The area is larger than that of the second pixel opening area, and at least one group of adjacent first pixel opening areas and the second pixel opening area are separated by the first blocking wall.
  • forming a light emitting structure layer on the driving circuit layer includes:
  • a pixel definition layer pattern is formed through a halftone mask patterning process
  • the organic light-emitting layer pattern is formed by an inkjet printing process, and during inkjet printing, the organic light-emitting layer material ink is only printed to the opening area of the first pixel;
  • a second electrode pattern is formed, and the second electrode is connected to the organic light emitting layer.
  • forming a light emitting structure layer on the driving circuit layer includes:
  • the organic light-emitting layer pattern is formed by an inkjet printing process, and during inkjet printing, the organic light-emitting layer material ink is only printed to the opening area of the first pixel;
  • a second electrode pattern is formed, and the second electrode is connected to the organic light emitting layer.
  • the organic light-emitting layer pattern is formed by an inkjet printing process, including any one or more of the following:
  • the hole injection material ink flows to the second pixel opening area adjacent to the first pixel opening area, and drying to remove the
  • the hole injection layer pattern is formed by post-baking the solvent of the hole injection material ink
  • the hole transport layer pattern is formed by post-baking the solvent of the ink
  • the luminescent material ink is inkjet printed in the first pixel opening area, the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area, and the solvent of the luminescent material ink is dried and removed, and then baked to form luminescence. layer pattern.
  • the first retaining walls extend in a first direction, a plurality of the first retaining walls are arranged in sequence in the second direction, and a plurality of the second retaining walls are arranged in sequence in the first direction , the first direction and the second direction intersect;
  • the second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, and the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions alternately arranged, The first bent portion extends toward the first direction, and the second extension portion extends toward the second direction.
  • a first blocking wall between a sub-blocking wall and a second sub-blocking wall defines a second pixel opening area.
  • the plurality of first bending portions of the plurality of first sub-retaining walls have the same bending times and bending directions.
  • the height of the first retaining wall is less than or equal to 1 ⁇ m, and the height of the second retaining wall is 1.2 ⁇ m to 1.5 ⁇ m.
  • the width of the first retaining wall is smaller than the width of the second retaining wall.
  • the material of the first retaining wall is a lyophilic material
  • the material of the second retaining wall is a lyophobic material
  • the width of the first electrode exposed by the first pixel opening region is greater than or equal to the width of the first electrode exposed by the two pixel opening regions.
  • the present disclosure provides a preparation method of a display substrate.
  • a first pixel opening area and a second pixel opening area with different areas are enclosed, and the ink is only printed to the first pixel opening area during inkjet printing.
  • the ink in the first pixel opening area can flow to the adjacent second pixel opening area, thereby effectively avoiding the low pixel resolution in order to prevent ink overflow. Therefore, the poor process can be significantly improved, the processing yield can be improved, and the distance between the adjacent sub-pixel openings can be reduced to improve the resolution and display quality.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • FIG. 21 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
  • the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn) and A plurality of sub-pixels Pxij.
  • the timing controller may supply grayscale values and control signals suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver driver.
  • the data driver may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample grayscale values with a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of sub-pixel rows, n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
  • the sub-pixel array may include a plurality of pixel sub-PXij. Each sub-pixel PXij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers.
  • the sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括基底、设置在基底上的驱动电路层和设置在驱动电路层远离基底一侧的发光结构层，驱动电路层包括晶体管，发光结构层包括第一电极、像素定义层、有机发光层和第二电极，第一电极与晶体管的漏电极连接，有机发光层位于第一电极和第二电极之间；像素定义层包括多个第一挡墙和多个第二挡墙，第一挡墙的高度小于第二挡墙的高度，第一挡墙和第二挡墙交叉限定出多个像素开口区域，像素开口区域包括第一像素开口区域和第二像素开口区域，第一像素开口区域的面积大于第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过第一挡墙隔开。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示基板，包括基底、设置在所述基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述驱动电路层包括晶体管，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层位于所述第一电极和第二电极之间；所述像素定义层包括多个第一挡墙和多个第二挡墙，所述第一挡墙的高度小于所述第二挡墙的高度，所述第一挡墙和第二挡墙交叉限定出多个像素开口区域，所述像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过所述第一挡墙隔开。
在示例性实施例中，所述第二挡墙沿第二方向延伸，多个所述第二挡墙沿第一方向依次排布，相邻的两个第二挡墙之间具有多个沿第二方向依次排 布的所述第一挡墙，所述第一方向和第二方向相交；
所述第二挡墙包括间隔排布的第一子挡墙和第二子挡墙，所述第一子挡墙具有交替排布的多个第一弯折部和多个第二延伸部，所述第一弯折部向所述第一方向延伸，所述第二延伸部向所述第二方向延伸。
在示例性实施例中，同一所述第一子挡墙的相邻的两个所述第一弯折部、相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙之间的第一挡墙围成一个所述第一像素开口区域；
同一所述第一子挡墙的相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙之间的第一挡墙围成一个所述第二像素开口区域。
在示例性实施例中，多个所述第一子挡墙的多个第一弯折部的弯折次数和弯折方向相同。
在示例性实施例中，所述第二挡墙沿所述第一方向的宽度为所述第一弯折部沿第一方向的宽度的1/3至2/3之间。
在示例性实施例中，所述第一挡墙的高度小于或等于1微米，所述第二挡墙的高度为1.2微米至1.5微米。
在示例性实施例中，所述第一挡墙的宽度小于所述第二挡墙的宽度。
在示例性实施例中，所述第一挡墙的材料为亲液特性材料，所述第二挡墙的材料为疏液特性材料。
在示例性实施例中，所有子像素的第一电极沿所述第一方向的宽度相同，所有子像素的第一电极沿所述第一方向和第二方向呈矩阵排布，相邻行的所述第一电极之间的距离相等，第(2n+1)列的所述第一电极与第(2n+2)列的所述第一电极之间的距离大于第(2n+2)列的所述第一电极与第(2n+3)列的所述第一电极之间的距离，n为大于或等于0的整数。
在示例性实施例中，所述第一像素开口区域包括发光区域和非发光区域，所述第二像素开口区域只包括发光区域，所述发光区域在基底上的正投影与 第一电极在基底上的正投影重合，所述非发光区域在基底上的正投影与第一电极在基底上的正投影没有交叠区域。
在示例性实施例中，相邻子像素的第一电极沿第一方向的宽度不同，所有子像素的第一电极沿所述第一方向和第二方向呈矩阵排布，相邻行的所述第一电极之间的距离相等，相邻列的所述第一电极之间的距离相等。
在示例性实施例中，所述第二像素开口区域沿所述第一方向的宽度为所述第一像素开口区域沿所述第一方向的宽度的1/3至2/3之间。
本公开还提供了一种显示装置，包括前述的显示基板。
本公开还提供了一种显示基板的制备方法，包括：
在基底上形成驱动电路层，所述驱动电路层包括晶体管；
在所述驱动电路层上形成发光结构层，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层位于所述第一电极和第二电极之间；所述像素定义层包括多个第一挡墙和多个第二挡墙，所述第一挡墙的高度小于所述第二挡墙的高度，所述第一挡墙和第二挡墙交叉限定出多个像素开口区域，所述像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过所述第一挡墙隔开。
在示例性实施例中，在所述驱动电路层上形成发光结构层，包括：
在所述驱动电路层上形成第一电极图案；
通过一次半色调掩膜构图工艺形成像素定义层图案；
通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
在所述有机发光层上形成第二电极图案。
在示例性实施例中，在所述驱动电路层上形成发光结构层，包括：
在所述驱动电路层上形成第一电极图案；
通过第一次单色调掩膜构图工艺形成像素定义层中的第一挡墙图案；
通过第二次单色调掩膜构图工艺形成像素定义层中的第二挡墙图案；
通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
在所述有机发光层上形成第二电极图案。
在示例性实施例中，通过喷墨打印工艺形成有机发光层图案，包括以下任意一项或多项：
将空穴注入材料墨水喷墨打印在所述第一像素开口区域，所述空穴注入材料墨水流到与所述第一像素开口区域相邻的所述第二像素开口区域，干燥除去所述空穴注入材料墨水的溶剂后烘烤形成空穴注入层图案；
将空穴传输材料墨水喷墨打印在所述第一像素开口区域，空穴传输材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述空穴传输材料墨水的溶剂后烘烤形成空穴传输层图案；
将发光材料墨水喷墨打印在第一像素开口区域，发光材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述发光材料墨水的溶剂后烘烤形成发光层图案。
在示例性实施例中，所述第二挡墙沿第二方向延伸，多个所述第二挡墙沿第一方向依次排布，相邻的两个第二挡墙之间具有多个沿第二方向依次排布的所述第一挡墙，所述第一方向和第二方向相交；
所述第二挡墙包括间隔排布的第一子挡墙和第二子挡墙，所述第一子挡墙具有交替排布的多个第一弯折部和多个第二延伸部，所述第一弯折部向所述第一方向延伸，所述第二延伸部向所述第二方向延伸。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开 的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为打印设备可打印的基板最高分辨率计算原理示意图；
图2为本公开示例性实施例一种显示基板的结构示意图；
图3和图4为图2中AA’区域的两种剖面结构示意图；
图5为图2中BB’区域的两种剖面结构示意图；
图6为一种像素驱动电路的等效电路示意图；
图7为本公开示例性实施例一种形成驱动电路层图案后的示意图；
图8为本公开示例性实施例一种形成第一电极图案后的示意图；
图9为图8所示第一电极图案的平面结构示意图；
图10为本公开示例性实施例另一种形成第一电极图案后的示意图；
图11为图10所示第一电极图案的平面结构示意图；
图12为本公开示例性实施例一种形成像素定义层图案后的示意图；
图13为本公开示例性实施例另一种形成像素定义层图案后的示意图；
图14为图12或图13所示像素定义层图案的平面结构示意图；
图15和图16为本公开示例性实施例两种形成的第一电极和像素定义层图案的平面示意图；
图17为本公开示例性实施例一种形成有机发光层图案后的示意图；
图18为本公开示例性实施例另一种形成有机发光层图案后的示意图；
图19为本公开示例性实施例一种形成第二电极图案后的示意图；
图20为本公开示例性实施例另一种形成第二电极图案后的示意图；
图21为本公开示例性实施例一种显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的 区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
OLED的成膜方式主要包括蒸镀制程或溶液制程。蒸镀制程在小尺寸应用较为成熟，目前该技术已经应用于量产中。而溶液制程OLED成膜方式主要有喷墨打印、喷嘴涂覆、旋涂、丝网印刷等，其中喷墨打印技术由于其材料利用率较高、可以实现大尺寸化，被认为是大尺寸OLED实现量产的重要方式。
当前高分辨率的OLED器件已成为发展的趋势，然而对于喷墨打印的OLED器件来说，分辨率受到打印机喷头尺寸的制约，如图1所示，一般而言，打印设备可打印的最高分辨率计算公式如下：
Figure PCTCN2021083843-appb-000001
如果将打印机用于打印分辨率比自身能打印的最高分辨率更高的显示基板，则会产生墨水溢流的风险。
本公开实施例提供了一种显示基板，包括基底、设置在所述基底上的驱动电路层以及设置在所述驱动电路层远离基底一侧的发光结构层，所述驱动电路层包括晶体管，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层位于所述第一电极和第二电极之间；
所述像素定义层包括多个第一挡墙和多个第二挡墙，第一挡墙的高度小于第二挡墙的高度，第一挡墙和第二挡墙交叉限定出多个像素开口区域，像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过第一挡墙隔开。
本公开实施例的显示基板，通过使用两种高度不同的挡墙，围成面积不同的第一像素开口区域和第二像素开口区域，喷墨打印时墨水只打印至第一像素开口区域，由于第一挡墙的高度较低，第一像素开口区域内的墨水可以流通至与其相邻的第二像素开口区域内，从而有效避免了为了防止墨水溢流导致像素分辨率低的问题，进而可以明显改善工艺不良，提高加工良率，且可以将相邻子像素开口之间的距离做小，提高分辨率和显示质量。
图2为本公开实施例一种显示基板的平面结构示意图，图3和图4为图2所示显示基板AA’区域的两种剖面结构示意图，图5为图2所示显示基板BB’区域的剖面结构示意图。如图2至图5所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一发光单元(子像素)P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3，第一发光单元P1、第二发光单元P2和第三发光单元P3均包括像素驱动电路和发光器件。第一发光单元P1、第二发光单元P2和第三发光单元P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相 应的电流。第一发光单元P1、第二发光单元P2和第三发光单元P3中的发光器件分别与所在发光单元的像素驱动电路连接，发光器件被配置为响应所在发光单元的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)发光单元、绿色(G)发光单元和蓝色(B)发光单元，或者可以包括红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元，本公开在此不做限定。在示例性实施方式中，像素单元中发光单元的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个发光单元时，三个发光单元可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个发光单元时，四个发光单元可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3和图4只是示意了OLED显示基板中三个子像素的结构。如图3或图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层102、设置在驱动电路层102远离基底10一侧的发光结构层103以及设置在发光结构层103远离基底10一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底10可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个晶体管101为例进行示意。发光结构层103可以包括第一电极21、像素定义层、有机发光层和第二电极26，第一电极21通过过孔与晶体管101的漏电极连接，有机发光层与第一电极21连接，第二电极26与有机发光层连接，有机发光层在第一电极21和第二电极26驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，如图2所示，像素定义层包括多个第一挡墙22a 和多个第二挡墙22b，第一挡墙22a的高度小于第二挡墙22b的高度，第一挡墙22a和第二挡墙22b交叉限定出多个像素开口区域，像素开口区域包括第一像素开口区域221和第二像素开口区域222，第一像素开口区域221的面积大于第二像素开口区域222的面积，两个相邻的第一像素开口区域221和第二像素开口区域222之间通过第一挡墙22a隔开。
在示例性实施方式中，如图2所示，第一挡墙22a沿第一方向D1延伸，多个第一挡墙22a沿第二方向D2依次排布，第二挡墙22b沿第二方向D2延伸，多个第二挡墙22b沿第一方向D1依次排布，相邻的两个第二挡墙22b之间具有多个沿第二方向D2依次排布的第一挡墙22a，第一方向D1和第二方向D2相交；
第二挡墙22b包括间隔排布的第一子挡墙22b1和第二子挡墙22b2，第一子挡墙22b1具有交替排布的多个第一弯折部22b1a和多个第二延伸部22b1b，第一弯折部22b1a向第一方向D1延伸，第二延伸部22b1b向第二方向D2延伸，第二子挡墙22b2沿第二方向D2延伸。
在示例性实施方式中，第一方向D1与栅线的延伸方向相同，第二方向D2与数据线的延伸方向相同。示例性的，第一方向D1和第二方向D2可以相互垂直。
在示例性实施方式中，如图2所示，第一像素开口区域221和第二像素开口区域222沿第二方向D2交替排列，同一列子像素中各个子像素的颜色相同，且同一列子像素中相邻的子像素之间通过第一挡墙22a隔开。
在示例性实施方式中，如图2所示，第一像素开口区域221和第二像素开口区域222沿第一方向D1交替排列，同一行子像素中相邻子像素的颜色不同，且同一行子像素中相邻的子像素之间通过第二挡墙22b隔开。
在示例性实施方式中，如图2所示，同一第一子挡墙22b1的相邻的两个第一弯折部22b1a、相邻的两个第一弯折部22b1a之间的第二延伸部22b1b、与第一子挡墙22b1相邻的第二子挡墙22b2以及第一子挡墙22b1与第二子挡墙22b2之间的第一挡墙22a围成一个第一像素开口区域221；
同一第一子挡墙22b1的相邻的两个第一弯折部22b1a之间的第二延伸部 22b1b、与第一子挡墙22b1相邻的第二子挡墙22b2以及第一子挡墙22b1与第二子挡墙22b2之间的第一挡墙22a围成一个第二像素开口区域222。
在示例性实施方式中，如图2所示，多个第一子挡墙22b1的多个第一弯折部22b1a的弯折次数和弯折方向相同。
在示例性实施方式中，如图2所示，第一挡墙22a的宽度小于第二挡墙22b的宽度。
本实施例中，由于第一挡墙22a只需要隔开相邻子像素中的第一电极21，不需要隔开有机发光层，因此，第一挡墙22a可以设计的尽量的窄。第二挡墙22b需要隔开相邻子像素的有机发光层，因此，第二挡墙22b的宽度可以大于第一挡墙22a的宽度。
在示例性实施方式中，第一挡墙22a的材料为亲液特性材料，第二挡墙22b的材料为疏液特性材料。
在示例性实施方式中，如图3和图4所示，第一像素开口区域221暴露出的第一电极21的宽度大于或等于第二像素开口区域222暴露出的第一电极21的宽度。
本实施例中，如图3所示，当第一像素开口区域221暴露出的第一电极21的宽度等于第二像素开口区域222暴露出的第一电极21的宽度时，每个像素单元中多个子像素的发光区域宽度相同，此时，第一像素开口区域221分为发光区域和非发光区域，仅发光区域下方设置有第一电极21和相应的与第一电极21连接的晶体管101，非发光区域下方没有设置第一电极或者与第一电极连接的晶体管，该方案可以保持三种子像素大小一致，使显示边缘更平滑。
如图4所示，当第一像素开口区域221暴露出的第一电极21的宽度大于第二像素开口区域222暴露出的第一电极21的宽度时，每个像素单元中第一像素开口区域221的子像素的发光区域宽度大于第二像素开口区域222的子像素的发光区域宽度。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图6为一种像素驱动电路的等效电路示意图。如图6所 示，像素驱动电路为3T1C结构，可以包括3个开关晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)、1个存储电容C ST和6个信号线(数据线Dn、第一扫描线Gn、第二扫描线Sn、补偿线Se、第一电源线VDD和第二电源线VSS)。在示例性实施方式中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极耦接于第一扫描线Gn，第一晶体管T1的第一极耦接于数据线Dn，第一晶体管T1的第二极耦接于第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描线Gn控制下，接收数据线Dn传输的数据信号，使第二晶体管T2的栅电极接收所述数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极，第二晶体管T2的第一极耦接于第一电源线VDD，第二晶体管T2的第二极耦接于OLED的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描线Sn，第三晶体管T3的第一极连接补偿线Se，第三晶体管T3的第二极耦接于第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。OLED的第一极耦接于第二晶体管T2的第二极，OLED的第二极耦接于第二电源线VSS，OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C ST的第一极与第二晶体管T2的栅电极耦接，存储电容C ST的第二极与第二晶体管T2的第二极耦接，存储电容C ST用于存储第二晶体管T2的栅电极的电位。
在示例性实施方式中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。第一晶体管T1到第三晶体管T3可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第三晶体管T3可以包括P型晶体管和N型晶体管。在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一电极(阳极)21、有机发光层和第二电极(阴极)26。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工 艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的一种制备过程可以包括如下操作。
(1)首先，在基底10上制备驱动电路层102图案，如图7所示。驱动电路层102包括多条栅线和多条数据线，多条栅线和多条数据线交叉限定出多个矩阵排布的像素单元，每个像素单元包括至少3个子像素，每个子像素包括薄膜晶体管(Thin Film Transistor，TFT)。本实施例中，一个像素单元包括3个子像素，分别为红色子像素R、绿色子像素G和蓝色子像素B。当然，本实施例方案也适用于一个像素单元包括4个子像素(红色子像素R、绿色子像素G、蓝色子像素B和白色子像素W)情形。
在示例性实施方式中，基底10可以是柔性基底，或者可以是刚性基底。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。 在示例性实施方式中，以一种叠层结构为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底10的制备。
在示例性实施方式中，驱动电路层102的制备过程可以包括：
在基底10上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，形成设置在基底10上的遮挡层图案。
随后，依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡层图案的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括有源层，有源层在基底10上的正投影位于遮挡层在基底10上的正投影的范围之内。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成设置在半导体层图案上的第二绝缘层，以及设置在第二绝缘层上的第一金属层图案，第一金属层图案至少包括栅电极，第二绝缘层在基底10上的正投影位于有源层在基底10上的正投影的范围之内，栅电极在基底10上的正投影位于第二绝缘层在基底10上的正投影的范围之内。
随后，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第一金属层图案的第三绝缘层，第三绝缘层上开设有有源过孔图案。两个有源过孔位于有源层两端所在位置，有源过孔内的第三绝缘层被刻蚀掉，暴露出有源层的表面。
随后，沉积第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，在第三绝缘层上形成第二金属层图案，第二金属层图案至少包括源电极、漏电极，源电极和漏电极分别通过有源过孔与有源层连接。
随后，涂覆平坦薄膜，通过图案化工艺对平坦薄膜进行图案化，形成覆 盖第二金属层图案的平坦层，平坦层上开设有阳极过孔图案，阳极过孔内的平坦层被刻蚀掉，暴露出漏电极的表面。
至此，在基底10上制备完成驱动电路层102图案，如图7所示。在示例性实施方式中，有源层、栅电极、源电极和漏电极组成晶体管101。在示例性实施方式中，晶体管101可以是像素驱动电路中的驱动晶体管，驱动晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)。
在示例性实施方式中，第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，第二绝缘层称为栅绝缘(GI)层，第三绝缘层称为层间绝缘(ILD)层。平坦薄膜可以采用有机材料，如树脂等。第一金属薄膜和第二金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。遮挡薄膜可以采用金属材料，或者采用不透光的非金属材料。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
(2)在形成前述图案的基底上形成第一电极21图案。在示例性实施方式中，形成第一电极21图案可以包括：在形成前述图案的基底上沉积第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成第一电极21图案，每个子像素的第一电极21与该子像素中薄膜晶体管的漏电极连接，如图8至图9或图10至图11所示。
在示例性实施方式中，如图8至图9所示，所有子像素的第一电极21沿第一方向D1的宽度a1相同，所有子像素的第一电极21沿第一方向D1和第二方向D2呈矩阵排布，相邻行的第一电极21之间的距离b1相等，第(2n+1)列的第一电极21与第(2n+2)列的第一电极21之间的距离c1大于第(2n+2)列的第一电极21与第(2n+3)列的第一电极21之间的距离d1，n为大于或等于0的整数。
在示例性实施方式中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
在示例性实施方式中，如图10至图11所示，相邻子像素的第一电极21沿第一方向D1的宽度不同，每两个相邻的子像素的第一电极21中，一个电极21沿第一方向D1的宽度为a2，另一个电极21沿第一方向D1的宽度为b2，a2>b2，所有子像素的第一电极21沿第一方向D1和第二方向D2呈矩阵排布，相邻行的第一电极21之间的距离c2相等，相邻列的第一电极21之间的距离d2相等。
在示例性实施方式中，第一电极21也可以采用具有高反射率的金属，如银Ag、金Au、钯Pd、铂Pt等，或这些金属的合金，或这些金属的复合层，还可以采用氧化铟锡ITO层和金属反射层的复合层结构，具有良好的导电性、高的反射率、良好的形态稳定性。
(3)在形成前述图案的基底上形成像素定义层图案，像素定义层用于在每个子像素限定出发光区域，发光区域露出第一电极21，如图12至图16所示。
在一种示例性实施例中，形成像素定义层图案包括：在形成前述图案的基底上涂覆一像素界定薄膜，采用半色调掩膜版对像素界定薄膜进行一次曝光显影后形成同时包含第一挡墙22a和第二挡墙22b的像素定义层图案。
在另一种示例性实施例中，形成像素定义层图案包括：在形成前述图案的基底上涂覆第一像素界定薄膜，采用单色调掩膜版对第一像素界定薄膜进行曝光显影后形成第一挡墙22a图案；在形成前述图案的基底上涂覆第二像素界定薄膜，采用单色调掩膜版对第二像素界定薄膜进行曝光显影后形成第二挡墙22b图案。
在示例性实施例中，像素定义层包括多个沿第一方向D1延伸的第一挡墙22a和多个沿第二方向D2延伸的第二挡墙22b，第一方向D1和第二方向D2相交，第一挡墙22a和第二挡墙22b交叉限定出多个像素开口区域，像素开口区域包括第一像素开口区域221和第二像素开口区域222，第一像素开口区域221和第二像素开口区域222沿第二方向D2交替排列，第一像素开 口区域221的面积大于第二像素开口区域222的面积。
在示例性实施例中，第二挡墙22b包括间隔排布的第一子挡墙22b1和第二子挡墙22b2，其中，第一子挡墙22b1具有交替排布的多个第一弯折部22b1a和多个第二延伸部22b1b，第一弯折部22b1a向第一方向D1延伸，第二延伸部22b1b向第二方向D2延伸。
在示例性实施例中，同一条第一子挡墙22b1的相邻的两个第一弯折部22b1a、相邻的两个第一弯折部22b1a之间的第二延伸部22b1b、与第一子挡墙22b1相邻的第二子挡墙22b2以及第一子挡墙22b1与第二子挡墙22b2之间的第一挡墙22a围成一个第一像素开口区域221；
同一条第一子挡墙22b1的相邻的两个第一弯折部22b1a之间的第二延伸部22b1b、与第一子挡墙22b1相邻的第二子挡墙22b2以及第一子挡墙22b1与第二子挡墙22b2之间的第一挡墙22a围成一个第二像素开口区域222。
在示例性实施例中，第二挡墙22b沿第一方向D1的宽度a3为第一弯折部22b1a沿第一方向D1的宽度b3的1/3至2/3之间。
在示例性实施例中，第二像素开口区域222沿第一方向D1的宽度d3为第一像素开口区域221沿第一方向D1的宽度d4的1/3至2/3之间。
在示例性实施例中，第一挡墙22a的高度小于第二挡墙22b的高度。
在示例性实施例中，第一挡墙22a的高度小于1微米。
在示例性实施例中，第二挡墙22b的高度为1.2微米至1.5微米。
本实施例中，由于有机发光层打印时墨水只打印至第一像素开口区域221，第二像素开口区域222内的墨水是第一像素开口区域221内的墨水流通过来的，因此，第一挡墙22a不需要考虑墨水的溢流问题，第一挡墙22a只需要隔离相邻子像素的第一电极21即可，第一挡墙22a沿第二方向D2的宽度c3可以设计的尽可能的窄，从而提高了像素分辨率。在示例性实施例中，第一挡墙22a覆盖相邻的两个第一电极21的边缘即可，例如，覆盖第一电极边缘向内部延伸小于3微米的范围，进一步的，可以小于2微米。在示例性实施例中，第二挡墙22b覆盖相邻的两个第一电极21的边缘，例如，覆盖第 一电极边缘向内部延伸小于4微米的范围，进一步的，可以小于3微米，进一步的，可以小于2微米。在示例性实施例中，第二挡墙22b覆盖第一电极边缘处的尺寸可以大于等于第一挡墙22a覆盖第一电极边缘处的尺寸。
在示例性实施例中，第一挡墙22a的材料为亲液特性材料，第二挡墙22b的材料为疏液特性材料。
在示例性实施例中，多个第一子挡墙22b1的多个第一弯折部22b1a的弯折次数和弯折方向相同。
示例性的，如图14所示，从上往下看，多个第一子挡墙22b1的多个第一弯折部22b1a均为向左侧弯折、向右侧弯折、向左侧弯折、向右侧弯折……的弯折顺序，即多个第一子挡墙22b1的多个第一弯折部22b1a的弯折次数和弯折方向相同，从而使得第一挡墙22a和第二挡墙22b交叉限定出的第一像素开口区域221和第二像素开口区域222沿第一方向D1交替排列。由于有机发光层打印时墨水只打印至第一像素开口区域221，第二像素开口区域222内的墨水是第一像素开口区域221内的墨水流通过来的，因此，第二挡墙22b只需考虑一侧墨水的溢流问题，第二挡墙22b沿第一方向D1的宽度a3可以设计的较窄一些。此外，第一挡墙22a只需要隔开相邻子像素中的第一电极21，不需要隔开有机发光层，因此，第一挡墙22a沿第二方向D2的宽度c3可以设计的尽量的窄，从而大大提高了像素分辨率。
在示例性实施例中，第二挡墙22b沿第一方向D1的宽度a3为5至30微米。示例性的，第二挡墙22b沿第一方向D1的宽度a3为5微米至10微米。
在示例性实施例中，在平行于显示基板的平面内，第一像素开口区域221和第二像素开口区域222的形状可以是三角形、矩形、多边形、圆形或椭圆形等。在垂直于显示基板的平面内，第一像素开口区域221和第二像素开口区域222的截面形状可以是矩形或者梯形等。
(4)在形成前述图案的基底上形成有机发光层图案。在示例性实施方式中，形成有机发光层图案可以包括：将空穴注入材料墨水喷墨打印在第一像素开口区域221，由于第一挡墙22a为亲液材料且高度较低，空穴注入材料 墨水流到与第一像素开口区域221相邻的第二像素开口区域222，干燥除去所述空穴注入材料墨水的溶剂后烘烤形成空穴注入层23图案；
将空穴传输材料墨水喷墨打印在第一像素开口区域221，由于第一挡墙22a为亲液材料且高度较低，空穴传输材料墨水流到与第一像素开口区域221相邻的第二像素开口区域222，干燥除去所述空穴传输材料墨水的溶剂后烘烤形成空穴传输层24图案；
将发光材料墨水喷墨打印在第一像素开口区域221，由于第一挡墙22a为亲液材料且高度较低，发光材料墨水流到与第一像素开口区域221相邻的第二像素开口区域222，干燥除去所述发光材料墨水的溶剂后烘烤形成发光层25图案，如图17至图18所示。
在示例性实施方式中，有机发光层除包括上述的空穴注入层(Hole Injection Layer，HIL)23、空穴传输层(Hole Transport Layer，HTL)24、发光层(Emitting Layer，EML)25之外，还可以包括如下任意一层或多层：、电子阻挡层(Electron Block Layer，EBL)、空穴阻挡层(Hole Block Layer，HBL)、电子传输层(Electron Transport Layer，ETL)和电子注入层(Electron Injection Layer，EIL)。在示例性实施方式中，电子阻挡层、空穴阻挡层、电子传输层和电子注入层可以采用开放式掩膜版(Open Mask)蒸镀形成。
在示例性实施方式中，电子阻挡层可以作为发光器件的微腔调节层，通过设计电子阻挡层的厚度，可以使得阴极和阳极之间有机发光层的厚度满足微腔长度的设计。在一些示例性实施方式中，可以采用有机发光层中的空穴传输层、空穴阻挡层或电子传输层作为发光器件的微腔调节层，本公开在此不做限定。
在示例性实施方式中，发光层可以包括主体(Host)材料和掺杂在主体材料中的客体(Dopant)材料，发光层客体材料的掺杂比例为1％至20％。在该掺杂比例范围内，一方面发光层主体材料可将激子能量有效转移给发光层客体材料来激发发光层客体材料发光，另一方面发光层主体材料对发光层客体材料进行了“稀释”，有效改善了发光层客体材料分子间相互碰撞、以及能量间相互碰撞引起的荧光淬灭，提高了发光效率和器件寿命。在示例性实施方式中，掺杂比例是指客体材料的质量与发光层的质量之比，即质量百分 比。在示例性实施方式中，发光层的厚度可以约为10nm至50nm。
在示例性实施方式中，空穴注入层可以采用无机的氧化物，如钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物或锰氧化物，或者可以采用强吸电子体系的p型掺杂剂和空穴传输材料的掺杂物。在示例性实施方式中，空穴注入层的厚度可以约为5nm至20nm。
在示例性实施方式中，在示例性实施方式中，空穴传输层可以采用空穴迁移率较高的材料，如芳胺类化合物，其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中，空穴传输层的厚度可以约为40nm至150nm。
在示例性实施方式中，空穴阻挡层和电子传输层可以采用芳族杂环化合物，例如苯并咪唑衍生物、咪唑并吡啶衍生物、苯并咪唑并菲啶衍生物等咪唑衍生物；嘧啶衍生物、三嗪衍生物等嗪衍生物；喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等包含含氮六元环结构的化合物(也包括在杂环上具有氧化膦系的取代基的化合物)等。在示例性实施方式中，空穴阻挡层的厚度可以约为5nm至15nm，电子传输层的厚度可以约为20nm至50nm。
在示例性实施方式中，电子注入层可以采用碱金属或者金属，例如氟化锂(LiF)、镱(Yb)、镁(Mg)或钙(Ca)等材料，或者这些碱金属或者金属的化合物等。在示例性实施方式中，电子注入层的厚度可以约为0.5nm至2nm。
(5)在形成前述图案的基底上形成第二电极26图案。在示例性实施方式中，形成第二电极26图案可以包括：在形成前述图案的基底上蒸镀第二电极材料，形成第二电极26图案，第二电极26与发光层25连接，如图19至图20所示。在示例性实施方式中，第二电极26可以是连通在一起的整体结构。
至此，在驱动电路层102上制备完成发光结构层103图案，发光结构层103包括第一电极21、像素定义层、有机发光层和第二电极26，有机发光层分别与第一电极21和第二电极26连接。
(6)在形成前述图案的基底上形成封装层104图案，如图3或图4所示。形成封装层104图案可以包括：先利用开放式掩膜板采用等离子体增强化学气相沉积(PECVD)方式沉积第一无机薄膜，形成第一封装层401。随后，利用喷墨打印工艺在第一封装层401上喷墨打印有机材料，固化成膜后，形成第二封装层402。随后，利用开放式掩膜板沉积第二无机薄膜，形成第三封装层403，第一封装层401、第二封装层402和第三封装层403组成封装层104。在示例性实施例中，第一封装层401和第三封装层403可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第二封装层402可以采用树脂材料，形成无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，制备完成封装层104后，可以在封装层104上形成触摸结构层(TSP)，触摸结构层可以包括触控电极层，或者包括触控电极层和触控绝缘层。
在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程可以包括剥离玻璃载板、贴附背膜、切割等工艺，本公开在此不作限定。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，在垂直于显示基板的平面内，本公开示例性实施例通过形成两种高度(及亲液性)不同的挡墙，围成交替排列的第一像素开口区域221和第二像素开口区域222，有机发光层打印时墨水只打印至第一像素开口区域221，第一像素开口区域221内的墨水可以流通至第二像素开口区域222内，从而可以将第二像素开口区域222内的像素设计的尽可能的窄，且由于第二像素开口区域222内的墨水是从第一像素开口区域221流通过来的，因此，第一挡墙22a不用考虑两侧墨水的溢流问题，因此，第一挡墙22a可以设计的尽可能的窄，第二挡墙22b只考虑一侧墨水的溢流问题，因此，第二挡墙22b也可以设计的较窄一些，从而提高了像素分辨率，解决了由多个喷嘴间喷墨量的误差引起的不良，有利于提高显示品质。本公开示例性实施例显示基板的制备方法具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，便于打印量产，良品率高。
本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺。例如，驱动电路层102中的晶体管可以是顶栅结构，或者可以是底栅结构，可以是单栅结构，或者可以是双栅结构。又如，驱动电路层102和发光结构层103中还可以设置其它膜层结构、电极结构或引线结构。再如，基底10可以是玻璃基底，本公开在此不做具体的限定。
本公开还提供了一种显示基板的制备方法。在示例性实施方式中，所述制备方法可以包括：
在基底上形成驱动电路层，所述驱动电路层包括晶体管；
在所述驱动电路层上形成发光结构层，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层分别与所述第一电极和第二电极连接；所述像素定义层包括多个第一挡墙和多个第二挡墙，所述第一挡墙的高度小于所述第二挡墙的高度，所述第一挡墙和第二挡墙交叉限定出多个像素开口区域，所述像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，至少一组相邻的第一像素开口区域和第二像素开口区域之间通过所述第一挡墙隔开。
在示例性实施方式中，在所述驱动电路层上形成发光结构层，包括：
在所述驱动电路层上形成第一电极图案；
通过一次半色调掩膜构图工艺形成像素定义层图案；
通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
形成第二电极图案，所述第二电极与所述有机发光层连接。
在示例性实施方式中，在所述驱动电路层上形成发光结构层，包括：
在所述驱动电路层上形成第一电极图案；
通过第一次单色调掩膜构图工艺形成像素定义层中的第一挡墙图案；
通过第二次单色调掩膜构图工艺形成像素定义层中的第二挡墙图案；
通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
形成第二电极图案，所述第二电极与所述有机发光层连接。
在示例性实施方式中，通过喷墨打印工艺形成有机发光层图案，包括以下任意一项或多项：
将空穴注入材料墨水喷墨打印在所述第一像素开口区域，所述空穴注入材料墨水流到与所述第一像素开口区域相邻的所述第二像素开口区域，干燥除去所述空穴注入材料墨水的溶剂后烘烤形成空穴注入层图案；
将空穴传输材料墨水喷墨打印在所述第一像素开口区域，空穴传输材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述空穴传输材料墨水的溶剂后烘烤形成空穴传输层图案；
将发光材料墨水喷墨打印在第一像素开口区域，发光材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述发光材料墨水的溶剂后烘烤形成发光层图案。
在示例性实施方式中，所述第一挡墙沿第一方向延伸，多个所述第一挡墙沿第二方向依次排布，多个所述第二挡墙沿第一方向依次排布，所述第一方向和第二方向相交；
所述第二挡墙包括间隔排布的第一子挡墙和第二子挡墙，所述第一子挡墙具有交替排布的多个第一弯折部和多个第二延伸部，所述第一弯折部向所述第一方向延伸，所述第二延伸部向所述第二方向延伸。
在示例性实施方式中，同一所述第一子挡墙的任意相邻的两个所述第一弯折部、相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙之间的第一挡墙围成一个所述第一像素开口区域；
同一所述第一子挡墙的任意相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙 之间的第一挡墙围成一个所述第二像素开口区域。
在示例性实施方式中，多个所述第一子挡墙的多个第一弯折部的弯折次数和弯折方向相同。
在示例性实施方式中，所述第一挡墙的高度小于或等于1微米，所述第二挡墙的高度为1.2微米至1.5微米。
在示例性实施方式中，所述第一挡墙的宽度小于所述第二挡墙的宽度。
在示例性实施方式中，所述第一挡墙的材料为亲液特性材料，所述第二挡墙的材料为疏液特性材料。
在示例性实施方式中，所述第一像素开口区域暴露出的第一电极的宽度大于或等于所述二像素开口区域暴露出的第一电极的宽度。
本公开提供了一种显示基板的制备方法，通过通过使用两种高度不同的挡墙，围成面积不同的第一像素开口区域和第二像素开口区域，喷墨打印时墨水只打印至第一像素开口区域，由于第一挡墙的高度较低，第一像素开口区域内的墨水可以流通至与其相邻的第二像素开口区域内，从而有效避免了为了防止墨水溢流导致像素分辨率低的问题，进而可以明显改善工艺不良，提高加工良率，且可以将相邻子像素开口之间的距离做小，提高分辨率和显示质量。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
图21为本公开实施例一种显示装置的结构示意图。如图21所示，OLED显示装置可以包括时序控制器、数据驱动器、扫描驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰 度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。子像素阵列可以包括多个像素子PXij。每个子像素PXij可以连接到对应的数据信号线和对应的扫描信号线，i和j可以是自然数。子像素PXij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种显示基板，包括基底、设置在所述基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述驱动电路层包括晶体管，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层位于所述第一电极和第二电极之间；
    所述像素定义层包括多个第一挡墙和多个第二挡墙，所述第一挡墙的高度小于所述第二挡墙的高度，所述第一挡墙和第二挡墙交叉限定出多个像素开口区域，所述像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过所述第一挡墙隔开。
  2. 根据权利要求1所述的显示基板，其中，所述第二挡墙沿第二方向延伸，多个所述第二挡墙沿第一方向依次排布，相邻的两个第二挡墙之间具有多个沿第二方向依次排布的所述第一挡墙，所述第一方向和第二方向相交；
    所述第二挡墙包括间隔排布的第一子挡墙和第二子挡墙，所述第一子挡墙具有交替排布的多个第一弯折部和多个第二延伸部，所述第一弯折部向所述第一方向延伸，所述第二延伸部向所述第二方向延伸。
  3. 根据权利要求2所述的显示基板，其中，同一所述第一子挡墙的相邻的两个所述第一弯折部、相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙之间的第一挡墙围成一个所述第一像素开口区域；
    同一所述第一子挡墙的相邻的两个所述第一弯折部之间的第二延伸部、与所述第一子挡墙相邻的第二子挡墙以及所述第一子挡墙与第二子挡墙之间的第一挡墙围成一个所述第二像素开口区域。
  4. 根据权利要求2所述的显示基板，其中，多个所述第一子挡墙的多个第一弯折部的弯折次数和弯折方向相同。
  5. 根据权利要求2所述的显示基板，其中，所述第二挡墙沿所述第一方向的宽度为所述第一弯折部沿第一方向的宽度的1/3至2/3之间。
  6. 根据权利要求2所述的显示基板，其中，所述第一挡墙沿所述第二方向的宽度小于所述第二挡墙沿所述第一方向的宽度。
  7. 根据权利要求2至6任一项所述的显示基板，其中，所有子像素的第一电极沿所述第一方向的宽度相同，所有子像素的第一电极沿所述第一方向和第二方向呈矩阵排布，相邻行的所述第一电极之间的距离相等，第(2n+1)列的所述第一电极与第(2n+2)列的所述第一电极之间的距离大于第(2n+2)列的所述第一电极与第(2n+3)列的所述第一电极之间的距离，n为大于或等于0的整数。
  8. 根据权利要求7所述的显示基板，其中，所述第一像素开口区域包括发光区域和非发光区域，所述第二像素开口区域只包括发光区域，所述发光区域在基底上的正投影与第一电极在基底上的正投影重合，所述非发光区域在基底上的正投影与第一电极在基底上的正投影没有交叠区域。
  9. 根据权利要求2至6任一项所述的显示基板，其中，相邻子像素的第一电极沿所述第一方向的宽度不同，所有子像素的第一电极沿所述第一方向和第二方向呈矩阵排布，相邻行的所述第一电极之间的距离相等，相邻列的所述第一电极之间的距离相等。
  10. 根据权利要求2至6任一项所述的显示基板，其中，所述第二像素开口区域沿所述第一方向的宽度为所述第一像素开口区域沿所述第一方向的宽度的1/3至2/3之间。
  11. 根据权利要求1所述的显示基板，其中，所述第一挡墙的高度小于或等于1微米，所述第二挡墙的高度为1.2微米至1.5微米。
  12. 根据权利要求1所述的显示基板，其中，所述第一挡墙的材料为亲液特性材料，所述第二挡墙的材料为疏液特性材料。
  13. 一种显示装置，包括如权利要求1至12任一项所述的显示基板。
  14. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层，所述驱动电路层包括晶体管；
    在所述驱动电路层上形成发光结构层，所述发光结构层包括第一电极、像素定义层、有机发光层和第二电极，所述第一电极与所述晶体管的漏电极连接，所述有机发光层位于所述第一电极和第二电极之间；所述像素定义层包括多个第一挡墙和多个第二挡墙，所述第一挡墙的高度小于所述第二挡墙的高度，所述第一挡墙和第二挡墙交叉限定出多个像素开口区域，所述像素开口区域包括第一像素开口区域和第二像素开口区域，所述第一像素开口区域的面积大于所述第二像素开口区域的面积，两个相邻的第一像素开口区域和第二像素开口区域之间通过所述第一挡墙隔开。
  15. 根据权利要求14所述的制备方法，其中，在所述驱动电路层上形成发光结构层，包括：
    在所述驱动电路层上形成第一电极图案；
    通过一次半色调掩膜构图工艺形成像素定义层图案；
    通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
    在所述有机发光层上形成第二电极图案。
  16. 根据权利要求14所述的制备方法，其中，在所述驱动电路层上形成发光结构层，包括：
    在所述驱动电路层上形成第一电极图案；
    通过第一次单色调掩膜构图工艺形成像素定义层中的第一挡墙图案；
    通过第二次单色调掩膜构图工艺形成像素定义层中的第二挡墙图案；
    通过喷墨打印工艺形成有机发光层图案，喷墨打印时，有机发光层材料墨水只打印至第一像素开口区域；
    在所述有机发光层上形成第二电极图案。
  17. 根据权利要求15或16任一所述的制备方法，其中，通过喷墨打印工艺形成有机发光层图案，包括以下任意一项或多项：
    将空穴注入材料墨水喷墨打印在所述第一像素开口区域，所述空穴注入材料墨水流到与所述第一像素开口区域相邻的所述第二像素开口区域，干燥除去所述空穴注入材料墨水的溶剂后烘烤形成空穴注入层图案；
    将空穴传输材料墨水喷墨打印在所述第一像素开口区域，空穴传输材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述空穴传输材料墨水的溶剂后烘烤形成空穴传输层图案；
    将发光材料墨水喷墨打印在第一像素开口区域，发光材料墨水流到与所述第一像素开口区域相邻的第二像素开口区域，干燥除去所述发光材料墨水的溶剂后烘烤形成发光层图案。
  18. 根据权利要求14所述的制备方法，其中，所述第二挡墙沿第二方向延伸，多个所述第二挡墙沿第一方向依次排布，相邻的两个第二挡墙之间具有多个沿第二方向依次排布的所述第一挡墙，所述第一方向和第二方向相交；
    所述第二挡墙包括间隔排布的第一子挡墙和第二子挡墙，所述第一子挡墙具有交替排布的多个第一弯折部和多个第二延伸部，所述第一弯折部向所述第一方向延伸，所述第二延伸部向所述第二方向延伸。
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