WO2023137709A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023137709A1
WO2023137709A1 PCT/CN2022/073243 CN2022073243W WO2023137709A1 WO 2023137709 A1 WO2023137709 A1 WO 2023137709A1 CN 2022073243 W CN2022073243 W CN 2022073243W WO 2023137709 A1 WO2023137709 A1 WO 2023137709A1
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Prior art keywords
area
layer
substrate
power supply
dam
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PCT/CN2022/073243
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English (en)
French (fr)
Inventor
周宏军
马龙
承天一
黄耀
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/073243 priority Critical patent/WO2023137709A1/zh
Priority to CN202280000049.XA priority patent/CN117322161A/zh
Publication of WO2023137709A1 publication Critical patent/WO2023137709A1/zh

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  • the present disclosure relates to but not limited to the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • Flexible Display which use OLED as a light-emitting device and are signal-controlled by Thin Film Transistor (TFT for short), have become mainstream products in the display field.
  • TFT Thin Film Transistor
  • the present disclosure further provides a display substrate, comprising: a display area and an edge area located on a side of the display area, the display substrate further comprising: a base and a power line disposed on the base and located in the edge area, the power line includes: a first power supply part and a second power supply part connected to each other, and the second power supply part is located on a side of the first power supply part away from the base;
  • the display area includes: a plurality of display units, at least one display unit includes: a pixel driving circuit and a light emitting device, the pixel driving circuit is electrically connected to the anode of the light emitting device, the power line is electrically connected to the cathode of the light emitting device,
  • the orthographic projection of the second power supply part on the substrate at least partially overlaps the orthographic projection of the first power supply part on the substrate, and the distance between the end of the second power supply part far away from the display area and the display area is greater than or equal to the distance between the end of the first power supply part far away from the display area and the display area.
  • the edge area includes a circuit area and an isolation dam area arranged in sequence along a direction away from the display area
  • the circuit area includes: a first circuit area, a second circuit area, and a third circuit area arranged in sequence along a direction away from the display area;
  • the pixel drive circuit includes: a writing transistor, a compensation transistor, a light emitting transistor, a first scanning signal line, a second scanning signal line, and a light emitting signal line; the first scanning signal line is electrically connected to the control electrode of the writing transistor, the second scanning signal line is electrically connected to the control electrode of the compensation transistor, and the light emitting signal line is electrically connected to the control electrode of the light emitting transistor; the transistor types of the writing transistor and the compensation transistor are different;
  • the display substrate further includes: a first drive circuit located in the first circuit area, a second drive circuit located in the second circuit area, and a third drive circuit located in the third circuit area and the isolation dam area;
  • the first driving circuit is electrically connected to the first scanning signal line
  • the second driving circuit is electrically connected to the second scanning signal line
  • the third driving circuit is electrically connected to the light emitting signal line
  • the first power supply unit is located in the isolation dam area, and the second power supply unit is located in the isolation dam area and the circuit area;
  • the orthographic projection of the second power supply part on the substrate at least partially overlaps the orthographic projection of the third driving circuit on the substrate, and there is no overlapping area with the orthographic projection of the second driving circuit on the substrate.
  • it further includes: a crack detection line located in the isolation dam area, the crack detection line is arranged on the same layer as the first power supply part, and is located on a side of the first power supply part away from the display area;
  • the distance between the first power supply part and the crack detection line is greater than or equal to 1 micron and less than or equal to 6 microns.
  • the distance between the first power supply unit and the third driving circuit is greater than or equal to 1 micron and less than or equal to 6 microns.
  • it further includes: a first flat layer located in the display area, the circuit area, and the isolation dam area, and a first protective layer located in the isolation dam area; the first flat layer is located between the first power supply part and the second power supply part, and is arranged on the same layer as the first protective layer;
  • the orthographic projection of the first protection layer on the substrate covers the orthographic projection of the crack detection line on the substrate, and at least partially overlaps with the orthographic projection of the first power supply part on the substrate.
  • the third drive circuit includes: a clock signal line located in the isolation dam region; the clock signal line is arranged on the same layer as the first power supply part, and is located on a side of the first power supply part close to the display area;
  • the orthographic projection of the first flat layer on the substrate covers the orthographic projection of the clock signal line on the substrate, and there is no overlapping area with the orthographic projection of the first power supply part on the substrate.
  • the second power supply part is provided with a plurality of second via holes exposing the first planar layer, and the plurality of second via holes are arranged in a matrix;
  • the orthographic projection of the plurality of second via holes on the substrate at least partially overlaps the orthographic projection of the third driving circuit on the substrate.
  • it further includes: a second flat layer located in the display area and the circuit area, and a second protection layer located in the isolation dam area;
  • the second flat layer is located on a side of the second power supply part away from the substrate, and is arranged on the same layer as the second protective layer;
  • the orthographic projection of the second protective layer on the substrate covers the orthographic projection of the first protective layer on the substrate, and the orthographic projection of the second planar layer on the substrate covers the orthographic projection of the second via hole substrate.
  • it further includes: an auxiliary power line located in an edge region; the anode is located on a side of the second planar layer away from the substrate, and is arranged on the same layer as the auxiliary power line;
  • the auxiliary power line is electrically connected to the second power supply unit
  • the orthographic projection of the auxiliary power line on the substrate at least partially overlaps the orthographic projections of the first driving circuit, the second driving circuit and the third driving circuit on the substrate.
  • the auxiliary power line is provided with a plurality of fifth via holes exposing the second planar layer, and the plurality of fifth via holes are arranged in a matrix;
  • the plurality of fifth vias are located in the first circuit area, the second circuit area and the third circuit area;
  • the orthographic projection of the fifth via hole located in the third circuit region on the substrate at least partially overlaps the orthographic projection of the second via hole on the substrate.
  • it further includes: a pixel definition layer located in the display area and an isolation layer located in the circuit area; the pixel definition layer is located on one side of the base of the anode, and is arranged on the same layer as the isolation layer;
  • the distance between the end of the isolation layer away from the display area and the display area is less than or equal to the distance between the end of the second flat layer away from the display area and the display area, and the orthographic projection of the isolation layer on the substrate covers the orthographic projection of the fifth via hole on the substrate.
  • it further includes: an organic light-emitting layer stacked on the substrate in sequence and located in the display area, and a cathode located in the display area and the circuit area;
  • the cathode is electrically connected to the auxiliary power line.
  • the isolation dam area further includes: a first isolation dam and a second isolation dam;
  • the second isolation dam is located on a side of the first isolation dam away from the display area, and is located on a side of the second protective layer close to the display area.
  • it also includes: the first dam foundation, the third dam foundation, the fifth dam foundation and the seventh dam foundation located in the isolation dam area;
  • the first dam foundation is set on the same layer as the first flat layer
  • the third dam foundation is set on the same layer as the second flat layer
  • the fifth dam foundation is set on the same layer as the pixel definition layer
  • the seventh dam foundation is located on the side of the pixel definition layer away from the base;
  • the second power supply part covers the first dam foundation
  • the third dam foundation is arranged on the second power supply part covering the first dam foundation
  • the orthographic projection of the third dam foundation on the base covers the orthographic projection of the first dam foundation on the base
  • the fifth dam foundation is arranged on the third dam foundation
  • the orthographic projection of the fifth dam foundation on the base covers the orthographic projection of the third dam foundation on the base
  • the seventh dam foundation is arranged on the fifth dam foundation
  • the orthographic projection of the fifth dam foundation on the base covers the orthographic projection of the seventh dam foundation on the base;
  • the auxiliary power line partially covers the third dam foundation
  • the first dam foundation, the second power supply portion covering the first dam foundation, the third dam foundation, the fifth dam foundation, and the seventh dam foundation form a second isolation dam.
  • it also includes: the second dam foundation, the fourth dam foundation and the sixth dam foundation located in the isolation dam area;
  • the second dam foundation is set on the same layer as the second flat layer, the fourth dam foundation is set on the same layer as the pixel definition layer, and the sixth dam foundation is set on the same layer as the seventh dam foundation;
  • the second dam foundation is arranged on the second power supply part, the fourth dam foundation is arranged on the auxiliary power line covering the second dam foundation, and the orthographic projection of the fourth dam foundation on the base covers the orthographic projection of the second dam foundation on the base, the sixth dam foundation is arranged on the fourth dam foundation, and the orthographic projection of the fourth dam foundation on the base covers the orthographic projection of the sixth dam foundation on the base;
  • the second dam foundation, the auxiliary power line covering the second dam foundation, the fourth dam foundation and the sixth dam foundation form a first isolation dam.
  • the orthographic projection of the first isolation dam on the substrate at least partially overlaps with the clock signal line.
  • the present disclosure further provides a display device, including: the above-mentioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate, which is configured to manufacture the above-mentioned display substrate, the display substrate comprising: a display area and an edge area located on a side of the display area, the method comprising:
  • a first power supply part and a second power supply part are sequentially formed on the substrate to form a power line located in the edge area, the orthographic projection of the second power supply part on the substrate at least partially overlaps the orthographic projection of the first power supply part on the substrate, and the distance between the end of the second power supply part far away from the display area and the display area is greater than or equal to the distance between the end of the first power supply part far away from the display area and the display area.
  • the sequentially forming the first power supply part and the second power supply part on the substrate includes:
  • a pixel drive circuit in the display area, a first drive circuit located in the circuit area, a second drive circuit, a third drive circuit located in the third circuit area, and a first power supply part and a crack detection line located in the isolation dam area on the substrate;
  • first planar layer located in the display area and a circuit area, a first dam foundation located in an isolation dam area, and a first protective layer on the substrate forming the first power supply portion;
  • connection electrode located in the display area and a second power supply portion located in the circuit area and the isolation dam area on the substrate forming the first planar layer
  • An organic light-emitting layer located in the display area, a cathode located in the display area and a circuit area, and sixth and seventh dams located in the isolation dam area are formed on the base for forming the pixel definition layer.
  • FIG. 1 is a schematic structural view of a display substrate
  • FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a top view of a display substrate provided by an embodiment of the present disclosure.
  • Fig. 5 is a top view of a part of the film layer of the display substrate provided by the embodiment of the present disclosure
  • Fig. 6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment
  • FIG. 7 is a schematic diagram after forming a display circuit layer
  • Fig. 8 is a sectional view along A-A direction of Fig. 7;
  • Fig. 10 is a sectional view along A-A direction of Fig. 9;
  • FIG. 11 is a schematic diagram after forming a second source-drain metal layer
  • Fig. 12 is a schematic diagram along the A-A direction of Fig. 11;
  • FIG. 13 is a schematic diagram after forming a second organic layer
  • Fig. 14 is a sectional view along A-A direction of Fig. 13;
  • 15 is a schematic diagram after forming a transparent conductive layer
  • Fig. 16 is a sectional view along A-A direction of Fig. 15;
  • 17 is a schematic diagram after forming a third organic layer
  • Figure 18 is a schematic diagram along the A-A direction of Figure 17;
  • Figure 19 is a schematic diagram after forming an organic light-emitting layer
  • Fig. 20 is a sectional view along A-A direction of Fig. 19;
  • Figure 21 is a schematic diagram after forming a cathode
  • Fig. 22 is a cross-sectional view along A-A direction of Fig. 21 .
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode.
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • a low-temperature polycrystalline oxide display product that provides low-voltage signals to the display area through the power line. Due to the certain impedance of the power line, there is a voltage drop in the voltage signal transmission, and the voltage loss of the power line reduces the display brightness uniformity of the display product and increases the power consumption of the display product, which has become an important factor affecting high-quality display.
  • FIG. 1 is a schematic structural view of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and an edge area 300 located on the other side of the display area 100 .
  • the display area 100 at least includes a plurality of display units (sub-pixels) arranged regularly.
  • the display unit in a plane perpendicular to the display substrate, may include a driving structure layer disposed on the substrate, a light emitting device disposed on the driving structure layer, and an encapsulation layer disposed on the light emitting device.
  • the driving structure layer may include a pixel driving circuit, the light emitting device is connected to the pixel driving circuit, the light emitting device is configured to emit light, and the pixel driving circuit is configured to drive the light emitting device to emit light.
  • the pixel driving circuit may include a plurality of thin film transistors (Thin Film Transistor, TFT for short) and storage capacitors, such as 3T1C, 4T1C, 5T1C, 6T1C or 7T1C, etc., which is not limited in the present disclosure.
  • TFT Thin Film Transistor
  • FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS).
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.
  • control electrode of the first transistor T1 is connected to the third scanning signal line S3, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • control electrode of the second transistor T2 is connected to the second scanning signal line S2, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 may be referred to as a compensation transistor, and when a turn-on level scan signal is applied to the second scan signal line S2, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1
  • the first electrode of the fourth transistor T4 is connected to the data signal line D
  • the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a write transistor, and when a turn-on level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • control electrode of the seventh transistor T7 is connected to the third scanning signal line S3, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device to initialize or release the accumulated charge amount in the first pole of the light emitting device.
  • the cathode of the light emitting device is connected to the second power supply line VSS.
  • the first power line VDD continuously provides a high-level signal
  • the second power line VSS continuously provides a low-level signal
  • the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 and the second transistor T2 are N-type metal oxide transistors
  • the third transistor T3 to the seventh transistor T7 are P-type low temperature polysilicon thin film transistors
  • the transistor types of the write transistor and the compensation transistor are different.
  • the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the light emitting signal line E, and the initial signal line INIT extend along a first direction
  • the second power line VSS, the first power line VDD, and the data signal line D extend along a second direction, and the first direction and the second direction intersect.
  • the light-emitting device may be an organic electroluminescence diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescence diode
  • the anode of the light emitting device is connected with the pixel driving circuit.
  • the display substrate provided by the embodiments of the present disclosure may be a low temperature polycrystalline oxide display substrate.
  • the bonding area 200 includes at least an isolation dam and a bonding circuit that connects signal lines of multiple display units to an external driving device
  • the edge area 300 includes at least an isolation dam, a gate drive circuit, and a power line for transmitting voltage signals to a plurality of display units
  • the bonding area 200 and the isolation dams of the edge area 300 form a ring structure surrounding the display area 100.
  • FIG. 3 is a schematic structural view of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 3 is an enlarged view of area C in FIG. 1 .
  • FIG. 4 is a top view of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view along the A-A direction of FIG. 4 .
  • the edge region 300 in a plane parallel to the display substrate, includes a circuit region 301 and an isolation dam region 302 arranged in sequence along a direction away from the display region 100 .
  • the circuit area 301 includes: a first circuit area 301A, a second circuit area 301B and a third circuit area 301C arranged in sequence along a direction away from the display area 100 .
  • the circuit area 301 includes at least a gate driving circuit.
  • the gate driving circuit is respectively electrically connected to the first scanning signal line, the second scanning signal line and the light emitting signal line of the pixel driving circuit 101 in the display area 100 .
  • the gate driving circuit located in the edge region 300 may include: a first driving circuit 201 , a second driving circuit 202 and a third driving circuit 203 .
  • the first driving circuit 201 is electrically connected to the first scanning signal line.
  • the second driving circuit 202 is electrically connected to the second scanning signal line.
  • the second driving circuit 202 may further include a clock signal line CLK.
  • the third driving circuit 203 is electrically connected to the light emitting signal line, and the third driving circuit 203 may further include a clock signal line ECLK.
  • the first driving circuit 201 may be an 8T2C circuit structure, or other circuit structures.
  • the second driving circuit 202 may be a 10T3C or 13T3C circuit structure, which is not limited in this disclosure.
  • the first driving circuit 201 is located in the first circuit area 301A
  • the second driving circuit 202 is located in the second circuit area 301B
  • the third driving circuit 203 is located in the third circuit area 301C and the isolation dam area 302 .
  • the isolation dam region 302 at least includes a power line 310 connected to the cathode of the light emitting device, a first isolation dam 410 , a second isolation dam 420 , a crack detection line 320 and a clock signal line ECLK of the third driving circuit 203 .
  • the power line 310 extends along a direction parallel to the edge of the display area, and is connected to the second power line VSS of the pixel driving circuit 101 in the display area 100 .
  • the power cord 310 includes: a first power supply part 310A and a second power supply part 310B connected to each other, and the second power supply part 310B is located on a side of the first power supply part 310A away from the base.
  • the orthographic projection of the second power supply part 310B on the substrate at least partially overlaps the orthographic projection of the first power supply part 310A on the substrate, and the distance between the end of the second power supply part 310B away from the display area 100 and the display area 100 is greater than or equal to the distance between the end of the first power supply part 310A far away from the display area 100 and the display area 100.
  • the first power supply portion 310A is located in the isolation dam region 302 .
  • the second power supply part 310B is located at least in the isolation dam area 302 and the third circuit area 301C.
  • the second power supply part 310B may also be located in the second circuit area 301B, wherein the orthographic projection of the second power supply part 310B on the substrate at least partially overlaps the orthographic projection of the third driving circuit 203 on the substrate, and there is no overlapping area with the orthographic projection of the second driving circuit 202 on the substrate.
  • the second driving circuit includes: a clock signal line CLK.
  • the distance between the end of the second power supply part 310B close to the display area 100 and the display area 100 is greater than the distance between the end of the clock signal line CLK away from the display area 100 and the display area 100, that is, there is no overlapping area between the orthographic projection of the second power supply part 310B on the substrate and the orthographic projection of the clock signal line CLK on the substrate.
  • the crack detection line 320 extends along a direction parallel to the edge of the display area, and is located on a side of the power line 310 away from the display area 100 .
  • the crack detection line is set to detect the presence or absence of cracks in the substrate.
  • the first isolation dam 410 and the second isolation dam 420 extend along a direction parallel to the edge of the display area, and are configured to block water vapor entering the display area 100 from the edge area 300 .
  • the distance between the first isolation dam 410 and the display area 100 is smaller than the distance between the second isolation dam 420 and the display area 100, that is, the second isolation dam 420 is arranged on the side of the first isolation dam 410 away from the display area 100.
  • the low voltage required by the light-emitting device connected to the pixel driving circuit in the display area 100 is introduced from the bonding pad of the bonding area 200, enters the edge area 300 after passing through the bonding area 200, and is delivered to the second power line VSS of each pixel driving circuit through the ring-shaped power line 310 of the edge area 300.
  • FIG. 3 schematically shows a cross-sectional structure of a display area and a peripheral area of a top-emission OLED.
  • OLED can be divided into bottom emission type, top emission type and double-sided emission type.
  • the top-emitting OLED has the advantages of high aperture ratio, high color purity, and easy realization of high resolution (Pixels Per Inch, PPI for short), and has gradually become the current mainstream structure.
  • the cathode is required to be very thin, so the voltage drop of the power line that provides low voltage for the cathode has a relatively important impact on improving the uniformity of display brightness.
  • the display substrate of the exemplary embodiment of the present disclosure includes a display area 100 and an edge area 300 , and the edge area 300 includes a circuit area 301 and an isolation dam area 302 arranged in sequence along a direction away from the display area 100 .
  • the display area 100 of the display substrate includes:
  • the active layer disposed on the first insulating layer 11, the active layer at least includes the first active layer;
  • the first gate metal layer, the third insulating layer 13, the second gate metal layer and the fourth insulating layer 14 are sequentially arranged on the second insulating layer 12, the first gate metal layer includes at least a first gate electrode; the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 are provided with via holes exposing the first active layer.
  • the first organic layer disposed on the first source-drain metal layer at least includes: a first planar layer 15 covering the first source-drain metal layer, the first planar layer 15 is provided with a first via hole exposing the first drain electrode;
  • a second organic layer is provided on the second source-drain electrode layer, and the second organic layer includes at least: a second planar layer 16 covering the connection electrode 17, on which is provided a second via hole exposing the connection electrode 17;
  • a third organic layer disposed on the transparent conductive layer at least includes: a pixel definition layer 22 disposed on the anode 21, and a fifth via hole exposing the anode 21 is disposed on the pixel definition layer 22;
  • the organic light emitting layer 24 and the cathode 25 on the pixel definition layer 22 are arranged, and the cathode 25 is connected with the organic light emitting layer 24 .
  • the edge region 300 of the display substrate includes:
  • the active layer disposed on the first insulating layer 11, the active layer at least includes a second active layer, a third active layer and a fourth active layer located in the circuit region 301;
  • a fourth insulating layer 14 covering the second gate metal layer, and a plurality of via holes exposing the second active layer, the third active layer and the fourth active layer are arranged on the fourth insulating layer 14 of the circuit region 301;
  • the via holes in the active layer are connected to the third active layer, and the fourth source electrode and the fourth drain electrode are respectively connected to the fourth active layer through the via holes exposing the fourth active layer;
  • the first organic layer arranged on the first source-drain metal layer at least includes: the first flat layer 15 located in the circuit region 301 and the isolation dam region 302, and the first dam foundation 421 and the first protective layer 431 formed in the isolation dam region 302; the first dam foundation 421 of the isolation dam region 302 is arranged on the first power supply part 310A, the first protective layer 431 is arranged on the crack detection line 320 and the first power supply part 310A, and the first protective layer 431 covers the crack
  • the detection line 320 covers the end of the first power supply part 310A away from the display area, and the first flat layer 15 covers the clock signal line ECLK;
  • the second organic layer is provided on the second source-drain electrode layer.
  • the second organic layer at least includes: the second flat layer 16 in the circuit region 301, and the second dam foundation 411, the third dam foundation 422, and the second protective layer 432 arranged in the isolation dam region 302.
  • the third dam foundation 422 is arranged on the second power supply part 310B covering the first dam foundation 421.
  • the second dam foundation 411 is arranged on the second power supply part 310B on the side of the first dam foundation 421 adjacent to the display area 100.
  • the second protective layer 432 is disposed on the first protective layer 431 and covers the end of the second power supply part 310B away from the display area, and the second flat layer 16 is provided with a fourth via hole exposing the second power supply part 310B;
  • the transparent conductive layer arranged on the second organic layer, the transparent conductive layer at least includes: the auxiliary power line 330 located on the circuit area 301 and the isolation dam area 302, and a plurality of fifth via holes are arranged on the auxiliary power line 330 located on the circuit area 301; the auxiliary power line 330 of the isolation dam area 302 covers the second dam base 411, and partially covers the third dam base 422; The auxiliary power lines 330 on one side of the display area 100 are all connected to the second power supply part 310B;
  • the third organic layer disposed on the transparent conductive layer at least includes: the isolation layer 23 located in the circuit area 301 and the fourth dam base 412 and the fifth dam base 423 located in the isolation dam area 302 , the isolation layer 23 has a seventh via hole exposing the auxiliary power line 330 , the fourth dam base 412 is arranged on the auxiliary power line 330 covering the second dam base 411 , and the fifth dam base 423 is arranged on the third dam base 422 .
  • the sixth dam foundation 413 and the seventh dam foundation 424 are arranged on the isolation dam area 302 , the sixth dam foundation 413 is located on the fourth dam foundation 412 , and the seventh dam foundation 424 is located on the fifth dam foundation 423 .
  • the sixth dam foundation 413 and the seventh dam foundation 424 can be reused as isolation columns.
  • the second dam foundation 402 , the auxiliary power line 330 covering the second dam foundation, the fourth dam foundation 412 and the sixth dam foundation 413 form a first isolation dam 410 .
  • the first dam foundation 421 , the second power supply part 310B covering the first dam foundation, the third dam foundation 422 , the fifth dam foundation 423 and the seventh dam foundation 424 form the second isolation dam 420 .
  • Fig. 6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment.
  • the display substrate provided by an exemplary embodiment may further include: an encapsulation layer 26 .
  • the encapsulation layer 26 may include: a first encapsulation layer 261 , a second encapsulation layer 262 and a third encapsulation layer 263 stacked on the substrate in sequence.
  • the encapsulation layer of the display area 100 and the circuit area 301 is a stacked structure of the first encapsulation layer/the second encapsulation layer/the third encapsulation layer
  • the encapsulation layer of the isolation dam area 302 is a lamination structure of the first encapsulation layer/the third encapsulation layer.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process" mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including coating organic materials, mask exposure and development and other treatments. Any one or more of sputtering, evaporation, and chemical vapor deposition can be used for deposition, any one or more of spray coating, spin coating, and inkjet printing can be used for coating, and any one or more of dry etching and wet etching can be used for etching, which is not limited in the present disclosure.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
  • the display substrate includes a display area 100 and an edge area 300
  • the edge area 300 includes a circuit area 301 and an isolation dam area 302 arranged in sequence along a direction away from the display area 100
  • the circuit area 301 includes: a first circuit area 301A, a second circuit area 301A and a third circuit area 301C arranged in sequence along a direction away from the display area 100
  • the display area 100 includes: a pixel driving circuit 101
  • the first circuit area 301A includes: the first driving circuit 201
  • the second circuit area 301A includes: the second driving circuit 202
  • the isolation dam area 302 and the third circuit area 301C include: the third driving circuit 203 .
  • the pixel driving circuit 101, the first driving circuit 201, the second driving circuit 202 and the third driving circuit 203 at least include: a plurality of transistors and at least one capacitor, as shown in FIG. 7 to FIG. 22 only one transistor in the pixel driving circuit, one transistor and one capacitor in the first to third driving circuits.
  • the display circuit layer pattern includes: a driving structure layer located in the display area 100 and a circuit structure layer pattern located in the peripheral area 300 .
  • the driving structure layer of the display area 100 includes the pixel driving circuit 101
  • the circuit structure layer of the peripheral area 300 includes the first driving circuit 201 located in the first circuit area 301A, the second driving circuit 202 located in the second circuit area 301B, and the third driving circuit 203 located in the third circuit area 301C, and also includes the first power supply part 310A located in the isolation dam area 302, the clock signal line ECLK and the crack detection line 320 of the third driving circuit 203, as shown in Figures 7 and 8
  • FIG. 7 is a schematic diagram after forming a display circuit layer
  • FIG. 8 is a cross-sectional view along the A-A direction of FIG. 7 .
  • the substrate 10 may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer.
  • the material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film and the like.
  • the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier (Barrier) layers, and the material of the semiconductor layer can be amorphous silicon (a-si). After this process, both the display area 100 and the peripheral area 300 include the substrate 10 .
  • the preparation process of the display circuit layer may include:
  • a first insulating film and a semiconductor film are sequentially deposited on the substrate 10, and the semiconductor film is patterned by a patterning process to form a first insulating layer 11 covering the entire substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 11.
  • the semiconductor layer pattern includes at least a first active layer located in the display area 100, a second active layer located in the first circuit region 301A, a third active layer located in the second circuit region 301B, and a fourth active layer located in the third circuit region 301C.
  • the first gate metal layer pattern includes at least the first gate electrode in the display area 100, the second gate electrode and the first capacitance electrode in the first circuit region 301A, the third gate electrode and the second capacitance electrode in the second circuit region 301B, and the fourth gate electrode and the fourth gate electrode in the third circuit region 301C. the third capacitive electrode.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 13 covering the first gate metal layer pattern and covering the entire substrate, and a second gate metal layer pattern disposed on the third insulating layer 13.
  • the second gate metal layer pattern includes at least the fourth capacitor electrode located in the first circuit region 301A, the fifth capacitor electrode located in the second circuit region 301B, and the sixth capacitor electrode located in the third circuit region 301C.
  • the orthographic projection of the first capacitive electrode on the substrate and the orthographic projection of the fourth capacitive electrode on the substrate at least partially overlap, and the first capacitive electrode and the fourth capacitive electrode constitute a capacitance in the first driving circuit.
  • the orthographic projection of the second capacitive electrode on the substrate at least partially overlaps the orthographic projection of the fifth capacitive electrode on the substrate, and the second capacitive electrode and the fifth capacitive electrode constitute a capacitance in the second driving circuit.
  • the orthographic projection of the third capacitive electrode on the substrate at least partially overlaps the orthographic projection of the sixth capacitive electrode on the substrate, and the third capacitive electrode and the sixth capacitive electrode constitute a capacitor in the third driving circuit.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 14 covering the pattern of the second gate metal layer and covering the entire substrate.
  • the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 have via holes exposing the first active layer in the display area 100, opening via holes exposing the second active layer in the first circuit area 301A, opening via holes exposing the third active layer in the second circuit area 301B, and opening via holes exposing the fourth active layer in the third circuit area 301C.
  • the first source-drain metal layer pattern at least includes: a first source electrode and a first drain electrode located in the display area 100, a second source electrode and a second drain electrode located in the first circuit region 301A, a third source electrode and a third drain electrode located in the second circuit region 301B, a fourth source electrode and a fourth drain electrode located in the third circuit region 301C, and the first power supply portion 3 formed in the isolation dam region 302 10A, the clock signal line ECLK and the crack detection line 320 of the third driving circuit.
  • the first power supply part 310A formed in the isolation dam region 302, the clock signal line ECLK of the third driving circuit, and the crack detection line 320 are arranged on the fourth insulating layer 14, the crack detection line 320 is arranged at the end of the first power supply part 310A away from the display area 100, and the clock signal line ECLK of the third driving circuit is located at the end of the first power supply part 310A close to the display area 100.
  • the first source electrode and the first drain electrode are respectively connected to the first active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, the second source electrode and the second drain electrode are respectively connected to the second active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, the third source electrode and the third drain electrode are respectively connected to the third active layer through the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14, and the fourth source electrode and the fourth drain electrode are respectively passed through the second insulating layer 12.
  • the third insulating layer 13 and the fourth insulating layer 14 are connected to the fourth active layer.
  • the display circuit layer pattern is prepared on the substrate.
  • the first active layer may include active layers of all transistors in the pixel driving circuit
  • the first gate electrode may include: gate electrodes of the active layers of all transistors in the pixel driving circuit
  • the first source electrode may include: source electrodes of all transistors in the pixel driving circuit
  • the first drain electrode may include: drain electrodes of all transistors in the pixel driving circuit.
  • the second active layer may include active layers of all transistors in the first driving circuit
  • the second gate electrode may include: gate electrodes of the active layers of all transistors in the first driving circuit
  • the second source electrode may include: source electrodes of all transistors in the first driving circuit
  • the second drain electrode may include: drain electrodes of all transistors in the first driving circuit.
  • the third active layer may include active layers of all transistors in the second driving circuit
  • the third gate electrode may include: gate electrodes of the active layers of all transistors in the second driving circuit
  • the third source electrode may include: source electrodes of all transistors in the second driving circuit
  • the third drain electrode may include: drain electrodes of all transistors in the second driving circuit.
  • the fourth active layer may include active layers of all transistors in the third driving circuit
  • the fourth gate electrode may include: gate electrodes of the active layers of all transistors in the third driving circuit
  • the fourth source electrode may include: source electrodes of all transistors in the third driving circuit
  • the fourth drain electrode may include: drain electrodes of all transistors in the third driving circuit.
  • the distance L1 between the first power supply part 310A and the third driving circuit 203 is greater than or equal to 3 microns and less than or equal to 5 microns.
  • the distance between the first power supply part 310A and the third driving circuit 203 may be 4 microns, which is not limited in this disclosure.
  • the distance L1 between the first power supply part 310A and the third driving circuit 203 may refer to the shortest distance between the first power supply part and the clock signal line ECLK of the third driving circuit.
  • the distance L2 between the first power supply part 310A and the crack detection line 320 is greater than or equal to 3 microns and less than or equal to 5 microns.
  • the distance between the first power supply part 310A and the crack detection line 320 may be 4 microns, which is not limited in this disclosure.
  • the distance L1 between the first power supply part 310A and the third driving circuit 203 and the distance L2 between the first power supply part 310A and the crack detection line 320 may be equal or unequal, which is not limited in this disclosure.
  • the thickness of the first source-drain metal layer may be about 700 nm to 1000 nm.
  • the thickness of the first source-drain metal layer may be about 860 nm.
  • the first flat film is patternized by the pattern technology to form the first organic layer pattern.
  • the first organic layer pattern includes: the first flat layer 15 of the display area 100, the circuit area 301 and the 302 isolation dam area 15 and the first dam base 421 and the first protection layer 431 in the segregated dam area, as shown in Figure 9 and 10 and 10 Show, Figure 9 is a schematic diagram after forming the first organic layer. Figure 10 is the cross-sectional view of the A-A direction of A-A.
  • the first planar layer 15 is provided with a first via hole V1 exposing the first drain electrode.
  • the orthographic projection of the first flat layer 15 on the substrate covers the orthographic projection of the clock signal line ECLK of the third driving circuit on the substrate, and there is no overlapping area with the orthographic projection of the first power supply part 310A on the substrate.
  • the shape of the first via hole V1 may be a triangle, a rectangle, a polygon, a circle, or an ellipse.
  • the shape of the first via hole V1 may be a rectangle, the length of the rectangle may be about 10 ⁇ m to 40 ⁇ m, the width of the rectangle may be about 10 ⁇ m to 40 ⁇ m, and the distance between adjacent first via holes V5 may be about 10 ⁇ m to 40 ⁇ m.
  • the surface of the first planar layer located in the isolation dam region 302 is not planar.
  • the first planar layer located in the isolation dam region 302 includes: a first sub-planar layer and a second sub-planar layer, the first sub-planar layer P1 is located on the side of the second sub-planar layer P2 away from the display region 100, and the thickness of the first sub-planar layer P1 is smaller than the thickness of the second sub-planar layer P2.
  • the orthographic projection of the second sub-planar layer P2 on the substrate covers the third driving circuit 203 .
  • the thickness of the first sub-planar layer P1 may be equal to the thickness of the first power supply part 310A, and the thickness of the second sub-planar layer P2 may be equal to the thickness of the first planar layer located in the display area 100 .
  • the first dam foundation 421 is located on the side of the first power supply part 310A away from the base, and the orthographic projection of the first power supply part 310A on the base and the orthographic projection of the first dam foundation 421 on the base at least partially overlap.
  • the length of the first dam foundation 421 along the first direction is smaller than the length of the first power supply portion 310A along the first direction, that is, the first power supply portion 310A is exposed on both the side of the first dam foundation 421 close to the display area and the side away from the display area.
  • the first protection layer 431 is located on a side of the first dam foundation 421 away from the display area 100 .
  • the orthographic projection of the first protective layer 431 on the substrate covers the orthographic projection of the crack detection line 320 on the substrate, and at least partially overlaps with the orthographic projection of the first power supply part 310A on the substrate, that is, the first protective layer 431 covers the crack detection line 320 and the end of the first power supply part 310A away from the display area 100 .
  • the length of the first dam foundation 421 along the first direction may be about 20 ⁇ m to 60 ⁇ m, and the first dam foundation 421 is configured to form the second isolation dam.
  • the cross-sectional shape of the first dam foundation 421 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • FIG. 11 is a schematic diagram after forming the second source-drain metal layer, and FIG.
  • connection electrode 17 is electrically connected to the first drain electrode through the first via hole V1.
  • the second power supply part 310B is located at least in the isolation dam area 302 and the third circuit area 301C.
  • the second power supply part 310B may also be located in the second circuit area 301B.
  • the orthographic projection of the second power supply part 310B on the substrate covers the orthographic projections of the first power supply part 310A and the third driving circuit 203 on the substrate, and partly overlaps the orthographic projection of the first protection layer 431 on the substrate.
  • the distance between the end of the second power supply part 310B away from the display area and the display area may be greater than or equal to the distance between the end of the first power supply part 310A far away from the display area and the display area.
  • FIG. 12 illustrates an example that the distance between the end of the second power supply part 310B away from the display area and the display area is equal to the distance between the end of the first power supply part 310A far away from the display area and the display area.
  • the orthographic projection of the second power supply unit 310B on the substrate there is no overlapping area between the orthographic projection of the second power supply unit 310B on the substrate and the orthographic projection of the second driving circuit 202 on the substrate.
  • the distance between the end of the second power supply part 310B close to the display area 100 and the display area 100 is greater than the distance between the clock signal line in the second driving circuit 202 and the display area 100, that is, the orthographic projection of the second power supply part 310B on the substrate does not overlap with the orthographic projection of the clock signal line in the second driving circuit 202 on the substrate, and the orthographic projection of the second power supply part 310B on the substrate does not overlap with the orthographic projection of the clock signal line in the second driving circuit 202 on the substrate, which can ensure the display effect of the display substrate. .
  • the second power supply part 310B covers the surface of the first dam foundation 421, and the second power supply part 310B is arranged on the first power supply part 310A exposed on both sides of the first dam foundation 421 to realize the connection between the second power supply part 310B and the first power supply part 310A,
  • the distance between the end of the crack detection line 320 close to the display area and the display area is greater than the distance between the end of the second power supply part 310B away from the display area and the display area, that is, the orthographic projection of the second power supply part 310B on the substrate does not overlap with the orthographic projection of the crack detection line 320 on the substrate.
  • the second power supply portion 310B is opened with a plurality of second via holes V2 exposing the first planar layer 15 .
  • the second via hole V2 is configured to release the gas in the first planar layer 15 to form a gas release channel to discharge the gas generated by the planarized film layer during the process, so as to avoid peeling of the film layer and improve the process quality.
  • the number of the second via holes V2 is multiple, and the multiple second via holes V2 are arranged in a matrix to uniformly release the gas in the first planar layer 15 .
  • the first power supply part 310A of the first source-drain metal layer and the second power supply part 310B of the second source-drain metal layer form a double-layer power supply line in the edge region 300
  • the double-layer power supply line of the parallel structure is realized by lapping in the isolation dam region 302, which reduces the resistance of the power supply line in the edge region 200, minimizes the voltage drop of the voltage signal, improves the display brightness uniformity of the display area, and improves the display quality.
  • the shape of the second via hole may be a triangle, a rectangle, a polygon, a circle, or an ellipse.
  • the shape of the second via hole may be a rectangle, the length of the rectangle may be about 10 ⁇ m to 40 ⁇ m, the width of the rectangle may be about 10 ⁇ m to 40 ⁇ m, and the distance between adjacent second via holes may be about 10 ⁇ m to 40 ⁇ m.
  • the first dam foundation 421 includes a first surface, a first proximal surface and a first distal surface. Covering the surface of the first dam foundation 421 by the second power supply part 310B may mean that the second power supply part 310B completely covers the first surface, the first near side and the first far side of the first dam foundation 401, that is, the second power supply part 310B wraps the first surface, the first near side and the first far side of the first dam foundation 401.
  • the thickness of the second source-drain metal layer may be about 700 nm to 1000 nm. In some possible implementations, the thickness of the second source-drain metal layer may be about 860 nm.
  • the second organic layer pattern includes: the second flat layer 16 located in the display area 100 and the circuit area 301, the second dam base 411 located in the isolation dam area 302, the third dam base 422 and the second protective layer 432, as shown in Figure 13 and Figure 14,
  • Figure 13 is a schematic diagram after forming the second organic layer
  • Figure 14 is a schematic diagram of Figure 13 along the A-A direction Sectional view.
  • the second planar layer 16 is provided with a third via hole V3 exposing the connection electrode 17 and a fourth via hole V4 exposing the surface of the second power supply part 310B.
  • the orthographic projection of the fourth via hole V4 on the substrate does not overlap with the orthographic projection of the second via hole V2 on the substrate.
  • the width W1 of the fourth via hole V4 along the first direction is smaller than the distance W2 between two adjacent second via holes arranged along the first direction.
  • the shapes of the third via hole V3 and the fourth via hole V4 may be triangle, rectangle, polygon, circle or ellipse.
  • the shape of the third via hole V3 and the fourth via hole V4 may be rectangular, the length of the rectangle may be about 10 ⁇ m to 40 ⁇ m, the width of the rectangle may be about 10 ⁇ m to 40 ⁇ m, and the distance between adjacent third via holes and adjacent fourth via holes may be about 10 ⁇ m to 40 ⁇ m.
  • the second flat layer 16 covers an end of the second power supply portion 310B close to the display area 100 , and the orthographic projection of the second flat layer 16 on the substrate covers the orthographic projection of the second via hole on the substrate.
  • the distance between the end of the second flat layer 16 far away from the display region 100 and the display region 100 is smaller than the distance between the end of the third driving circuit 203 far away from the display region 100 and the display region 100
  • the distance between the end of the second flat layer 16 far away from the display region 100 and the display region 100 is smaller than the distance between the end of the first flat layer 15 far away from the display region 100 and the display region 100 .
  • the second dam foundation 411 is disposed on the second power supply part 310B on the side of the first dam foundation 421 adjacent to the display area 100 .
  • the orthographic projection of the second dam foundation 411 on the substrate at least partially overlaps the orthographic projection of the clock signal line of the third driving circuit on the substrate.
  • both the side of the second dam foundation 411 adjacent to the display area 100 and the side of the second dam foundation 411 away from the display area 100 expose the second power supply part 310B.
  • the cross-sectional shape of the second dam foundation 411 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the length of the second dam foundation 411 along the first direction may be about 20 ⁇ m to 60 ⁇ m, and the second dam foundation 411 is configured to form the first isolation dam.
  • the third dam foundation 422 is disposed on the second power supply part 310B covering the first dam foundation 421 , and the orthographic projection of the third dam foundation 422 on the base covers the orthographic projection of the first dam foundation 421 on the base.
  • the cross-sectional shape of the third dam foundation 422 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the orthographic projection of the second protection layer 432 on the substrate covers the orthographic projection of the first protection layer 431 on the substrate, that is, the second protection layer 432 covers an end of the second power supply portion 310B away from the display area 100 .
  • the length of the third dam foundation 422 along the first direction may be about 20 ⁇ m to 60 ⁇ m, and the first dam foundation 421 and the third dam foundation 422 are configured to form a second isolation dam.
  • the transparent conductive layer pattern includes: the anode 21 located in the display area 100 and the auxiliary power line 330 located in the edge area 300, as shown in FIGS. 15 and 16 .
  • the anode 21 is formed on the second planar layer 16 of the display region 100 and connected to the connection electrode 17 through the third via hole V3.
  • the auxiliary power line 330 is electrically connected to the second power part 310B, wherein a part of the auxiliary power line 330 is overlapped on the second power part 310B, and another part is connected to the second power part 310B through the fourth via hole V4.
  • the orthographic projection of the auxiliary power line 330 on the base and the orthographic projection of the third dam 422 on the base at least partially overlap, and the distance between the end of the auxiliary power line 330 away from the display area 100 and the display area 100 is smaller than the distance between the end of the third dam 422 far away from the display area 100 and the display area 100, that is, the auxiliary power line 330 partially covers the third dam 422.
  • the third dam foundation 422 includes a third surface, a third proximal surface, and a third distal surface.
  • the auxiliary power line 330 partially covering the third dam foundation 422 may mean that the auxiliary power line 330 partially covers the third surface of the third dam foundation 422 and completely covers the second near side of the third dam foundation.
  • the orthographic projection of the auxiliary power line 330 on the base covers the orthographic projection of the second dam foundation 411 on the base, that is, the auxiliary power line 330 covers the second dam foundation 411 .
  • the second dam foundation 411 includes a second surface, a second proximal surface and a second distal surface.
  • the auxiliary power line 330 covering the second dam foundation 411 may refer to that the auxiliary power line 330 completely covers the second surface, the second near side and the second far side of the second dam foundation 411 . That is, the auxiliary power line 330 wraps the second surface, the second near side and the second far side of the second dam foundation 411 .
  • the orthographic projection of the auxiliary power line 330 is at least partially overlapped with the orthographic projection of the second power supply part 310B exposed on both sides of the second dam foundation 411 on the substrate, that is, the auxiliary power supply line 330 covers the second power supply part 310B exposed on both sides of the second dam foundation 411 and is electrically connected to the second power supply part 310B exposed on both sides of the second dam foundation 411. Since the auxiliary power line 330 is connected to the second power supply unit 310B, the auxiliary power line 330 is connected to the power line 310 .
  • the orthographic projection of the auxiliary power line 330 on the substrate at least partially overlaps the orthographic projections of the first driving circuit 201 , the second driving circuit 202 and the third driving circuit 203 on the substrate.
  • the auxiliary power line 330 is provided with a fifth via hole V5 exposing the second planar layer 16 , and the fifth via hole V5 is located in the first circuit area 301A, the second circuit area 301B and the third circuit area 301C.
  • the orthographic projection of the fifth via hole V5 located in the third circuit region 301C on the substrate at least partially overlaps the orthographic projection of the second via hole V2 on the substrate.
  • the fifth via hole V5 is configured to release the gas in the second planar layer 16 to form a vent channel to discharge the gas generated by the planarized film layer during the process, so as to avoid peeling of the film layer and improve process quality.
  • the shape of the fifth via hole V5 may be a triangle, a rectangle, a polygon, a circle, or an ellipse.
  • the shape of the fifth via hole V5 may be a rectangle, the length of the rectangle may be about 10 ⁇ m to 40 ⁇ m, the width of the rectangle may be about 10 ⁇ m to 40 ⁇ m, and the distance between adjacent fifth via holes V5 may be about 10 ⁇ m to 40 ⁇ m.
  • FIG. 17 is a schematic diagram after forming the third organic layer
  • FIG. 18 is a schematic diagram along the A-A direction of FIG. 17.
  • a sixth via hole V6 exposing the anode 21 is opened on the pixel definition layer 22 .
  • the shape of the sixth via hole V6 may be a triangle, a rectangle, a polygon, a circle, or an ellipse.
  • the shape of the sixth via hole V6 may be a rectangle, the length of the rectangle may be about 10 ⁇ m to 40 ⁇ m, the width of the rectangle may be about 10 ⁇ m to 40 ⁇ m, and the distance between adjacent sixth via holes V6 may be about 10 ⁇ m to 40 ⁇ m.
  • the distance between the end of the isolation layer 23 close to the display area 100 and the display area 100 is equal to the distance between the end of the pixel definition layer 22 far away from the display area 100 and the display area 100 , and the distance between the end of the isolation layer 23 far away from the display area 100 and the display area 100 is less than or equal to the distance between the end of the second flat layer 16 far away from the display area 100 and the display area 100 .
  • the distance between the end of the isolation layer 23 away from the display area and the display area is less than or equal to the distance between the end of the second flat layer far away from the display area and the display area.
  • the orthographic projection of the isolation layer 23 on the substrate covers the orthographic projection of the fifth via hole on the substrate.
  • the isolation layer 23 is opened with a plurality of seventh via holes V7 exposing the auxiliary power line 330 .
  • a plurality of seventh vias V7 can be arranged in an array, or a plurality of seventh vias can communicate with each other.
  • FIG. 17 and FIG. 18 illustrate that multiple seventh vias can communicate with each other as an example.
  • a plurality of seventh vias V7 are located in the first circuit area 301A, the second circuit area 301B and the third circuit area 301C.
  • the orthographic projection of the seventh via hole V7 located in the third circuit region 301C on the substrate at least partially overlaps the orthographic projection of the fourth via hole V4 on the substrate.
  • the fourth dam foundation 412 is disposed on the auxiliary power line 330 covering the second dam foundation 411 , and the orthographic projection of the fourth dam foundation 412 on the base covers the orthographic projection of the second dam foundation 411 on the base.
  • the length of the fourth dam foundation 412 along the first direction may be about 20 ⁇ m to 60 ⁇ m.
  • the cross-sectional shape of the fourth dam foundation 412 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the fifth dam foundation 423 is disposed on the third dam foundation 422 , and the orthographic projection of the fifth dam foundation 423 on the base covers the orthographic projection of the third dam foundation 422 on the base.
  • the thickness of the fifth dam foundation 423 along the first direction may be about 20 ⁇ m to 60 ⁇ m.
  • the cross-sectional shape of the fifth dam foundation 423 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the auxiliary power line 330 is exposed between the fourth dam foundation 412 and the fifth dam foundation 423 , and the side of the fourth dam foundation 412 close to the display area 100 exposes the auxiliary power line 330 .
  • FIG. 19 is a schematic view after forming the organic luminescent layer
  • FIG. 20 is a cross-sectional view along the A-A direction of FIG. 19 .
  • the organic light emitting layer 24 is formed in the sixth via hole V6 of the pixel defining layer of the display region 100 to realize the connection between the organic light emitting layer 24 and the anode 21 . Since the anode 21 is connected to the connection electrode 17 and the connection electrode 17 is connected to the first drain electrode, the organic light emitting layer 24 is connected to the first drain electrode.
  • the organic light-emitting layer 24 may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), an electron blocking layer (Electron Block Layer, referred to as EBL), a light emitting layer (Emitting Layer, referred to as EML), a hole blocking layer (Hole Block Layer, referred to as HBL), an electron transport layer (Electron). Transport Layer, referred to as ETL) and electron injection layer (Electron Injection Layer, referred to as EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML light emitting layer
  • HBL hole blocking layer
  • EML Hole Block Layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layer of all sub-pixels can be a common layer connected together
  • the electron injection layer of all sub-pixels can be a common layer connected together
  • the hole transport layer of all sub-pixels can be a common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels can have a small amount of overlap, or can be isolated
  • the electron blocking layers of adjacent sub-pixels can have a small amount of overlap , or can be isolated.
  • Figure 21 is a schematic diagram after forming the cathode
  • Figure 22 is a cross-sectional view along the A-A direction of Figure 21.
  • the distance between the end of the cathode 25 away from the display region 100 and the display region 100 is smaller than the distance between the side of the isolation layer 23 far away from the display region 100 and the display region 100 .
  • a part of the cathode 25 is formed on the organic light emitting layer 24 of the display area 100 , the cathode 25 is connected to the organic light emitting layer 24 , and another part of the cathode 25 is connected to the auxiliary power line 330 through the seventh via hole.
  • the cathode 25 is connected to the auxiliary power line 330 , and the auxiliary power line 330 is electrically connected to the second power supply portion 310B of the power line 310 , the cathode 25 is connected to the power line 310 .
  • the cathode can be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.
  • the sixth dam foundation 413 is arranged on the fourth dam foundation 412 , and the orthographic projection of the fourth dam foundation on the base covers the orthographic projection of the sixth dam foundation 413 on the base.
  • the thickness of the sixth dam foundation 413 along the first direction may be about 20 ⁇ m to 60 ⁇ m.
  • the cross-sectional shape of the sixth dam foundation 413 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the second dam foundation 402 , the auxiliary power line 330 covering the second dam foundation, the fourth dam foundation 411 and the sixth dam foundation 413 form the first isolation dam 410 .
  • the seventh dam foundation 424 is disposed on the fifth dam foundation 423 , and the orthographic projection of the fifth dam foundation 423 on the base covers the orthographic projection of the seventh dam foundation 424 on the base.
  • the thickness of the seventh dam foundation 424 along the first direction may be about 20 ⁇ m to 60 ⁇ m.
  • the cross-sectional shape of the seventh dam foundation 424 may be trapezoidal or rectangular.
  • the length of the surface away from the base is smaller than the length of the surface near the base, and the length of the surface away from the base may be about 20 ⁇ m to 40 ⁇ m.
  • the first dam foundation 421 , the second power supply part 310B covering the first dam foundation, the third dam foundation 422 , the fifth dam foundation 423 and the seventh dam foundation 424 form the second isolation dam 420 .
  • the distance between the first isolation dam 410 and the display area 100 is smaller than the distance between the second isolation dam 420 and the display area 100 .
  • the length of the orthographic projection of the first isolation dam 410 and the second isolation dam 420 on the substrate along the first direction may be about 20 ⁇ m to 60 ⁇ m, and the distance between the first isolation dam 410 and the second isolation dam 420 may be about 20 ⁇ m to 60 ⁇ m.
  • cross-sectional shapes of the first isolation dam 410 and the second isolation dam 420 may be trapezoidal.
  • the sixth dam foundation 413 and the seventh dam foundation 424 are integrally formed.
  • the cathode 25 may be formed before the sixth foundation 413 and the seventh foundation 424 , or may be formed after the sixth foundation 413 and the seventh foundation 424 .
  • the orthographic projection of the first isolation dam 410 on the substrate at least partially overlaps the orthographic projection of the clock signal line of the third driving circuit on the substrate.
  • the encapsulation layer 26 of the display area 100 and the circuit area 301 adopts a stacked structure of the first encapsulation layer 261, the second encapsulation layer 262 and the third encapsulation layer 263, and the encapsulation layer 26 of the isolation dam area 302 adopts a lamination structure of the first encapsulation layer 261 and the third encapsulation layer 263.
  • the first encapsulation layer can be made of inorganic materials, covering the cathode 25 in the display area 100 , covering the spacer column layer 23 in the circuit area 301 , and wrapping the first isolation dam 410 and the second isolation dam 420 in the isolation dam area 302 .
  • the second encapsulation layer can be made of organic materials, and is disposed on the display area 100 and the circuit area 301 .
  • the third encapsulation layer can be made of inorganic materials, the second encapsulation layer covering the display area 100 and the circuit area 301 , and the first encapsulation layer covering the isolation dam area 302 .
  • the packaging layer 26 of the display area 100 and the circuit area 301 adopts a laminated structure of inorganic materials/organic materials/inorganic materials
  • the organic material layer is arranged between two inorganic material layers
  • the packaging layer 26 of the isolation dam area 302 adopts a laminated structure of inorganic materials/inorganic materials.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.
  • the first insulating layer is called a buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called a gate insulating (GI) layer
  • the fourth insulating layer is called an interlayer insulating (ILD) layer.
  • the first metal film, the second metal film, the third metal film and the fourth metal film can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single layer structure, or a multilayer composite structure, such as Ti/Al/Ti, etc.
  • the transparent conductive film may include indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate, etc.
  • the active layer film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene and other materials, that is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • the exemplary embodiment of the present disclosure forms the first power part 310A of the power line 310 through the first source-drain metal layer, and forms the second power part 310B of the power line 310 through the second source-drain metal layer, so as to form a double-layer power line 310 in the edge area 300, realize the double-layer power line in parallel structure, reduce the resistance of the power line in the edge area 300, minimize the voltage drop of the voltage signal, improve the display brightness uniformity of the display area 100, and improve the display quality.
  • the distance between the first power supply part 310A and the third driving circuit 203 is greater than or equal to 1 micron and less than or equal to 6 microns.
  • the distance between the first power supply part 310A and the third driving circuit 203 may be 4 microns, which is not limited in this disclosure.
  • the distance between the first power supply part 310A and the crack detection line 320 is greater than or equal to 1 micron and less than or equal to 6 microns.
  • the distance between the first power supply part 310A and the crack detection line 320 may be 4 microns, which is not limited in this disclosure.
  • the distance between the first power supply part 310A and the third driving circuit 203 and the distance between the first power supply part 310A and the crack detection line 320 are set so that the width of the first power supply part 310A is large enough to ensure the display substrate exposure, etching and other processes and signal interference requirements, reduce the voltage drop of the power line, improve the display uniformity of the display substrate, and reduce the power consumption of the display substrate.
  • the distance between the first power supply part 310A and the third driving circuit 203 and the distance between the first power supply part 310A and the crack detection line 320 may be equal or unequal, which is not limited in this disclosure.
  • the orthographic projection of the second power supply part 310B on the substrate 10 covers the orthographic projections of the first power supply part 310A and the third driving circuit 203 on the substrate 10 .
  • the arrangement of the second power supply part 310B in the present disclosure makes the length of the second power supply part 310B along the first direction sufficiently large, reduces the voltage drop of the power line, improves the display uniformity of the display substrate, and reduces the power consumption of the display substrate.
  • the distance between the end of the second power supply part 310B close to the display area 100 and the display area 100 is greater than the distance between the clock signal line CLK in the second driving circuit 202 and the display area 100, so as to reduce the load on the clock signal line CLK in the second driving circuit 202 and ensure the normal display of the display unit in the display area 100.
  • the first protection layer 431 wraps the end of the first power supply part 310A away from the display area 100
  • the second protection layer 432 wraps the end of the second power supply part 310B away from the display area 100 , which can prevent corrosion and dark spots.
  • the second flat layer 16 covers the second power supply portion located at the edge of the second via hole, which can prevent corrosion and dark spots.
  • the distance between the end of the first isolation dam 410 close to the display area 100 and the end of the second power supply part 310B close to the display area can be relatively large, which can improve the packaging reliability of the display substrate.
  • the auxiliary power line 330 covers the first drive circuit 201, the second drive circuit 202, and the third drive circuit 203, which can reduce the voltage drop of the power line, and can also shield the external environment or signal from interfering with the first drive circuit 201, the second drive circuit 202, and the third drive circuit 203.
  • the second via hole and the fifth via hole are respectively provided on the second power supply part 310B and the auxiliary power supply line 330 to form a venting channel, which can effectively discharge the gas generated by the flat layer during the process, avoid peeling of the film layer, and improve the process quality.
  • the exemplary embodiment of the present disclosure shows that the preparation process of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield rate.
  • the structure of the substrate shown in this disclosure and its fabrication process are merely illustrative. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • An embodiment of the present disclosure also provides a method for preparing a display substrate, which is configured to manufacture a display substrate.
  • the display substrate includes: a display area and an edge area.
  • the method for preparing a display substrate provided by an embodiment of the present disclosure may include the following steps:
  • Step S1 providing a substrate.
  • Step S2 sequentially forming a first power supply portion and a second power supply portion on the substrate to form a power supply line located in an edge region.
  • the orthographic projection of the second power supply part on the substrate at least partially overlaps the orthographic projection of the first power supply part on the substrate, and the distance between the end of the second power supply part away from the display area and the display area is greater than or equal to the distance between the end of the first power supply part far away from the display area and the display area.
  • the display substrate is the display substrate provided by any one of the above-mentioned embodiments, and the realization principle and the realization effect are similar, and will not be repeated here.
  • step S2 may include the following steps:
  • a pixel drive circuit in the display area, a first drive circuit located in the circuit area, a second drive circuit, a third drive circuit located in the third circuit area, and a first power supply part and a crack detection line located in the isolation dam area on the substrate;
  • first planar layer located in the display area and a circuit area, a first dam foundation located in an isolation dam area, and a first protective layer on the substrate forming the first power supply portion;
  • connection electrode located in the display area and a second power supply portion located in the circuit area and the isolation dam area on the substrate forming the first planar layer
  • An organic light-emitting layer located in the display area, a cathode located in the display area and a circuit area, and sixth and seventh dams located in the isolation dam area are formed on the base for forming the pixel definition layer.
  • An embodiment of the present disclosure also provides a display device, including a display substrate.
  • the display substrate is the display substrate provided by any one of the above-mentioned embodiments, and the realization principle and the realization effect are similar, and will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种显示基板及其制备方法、显示装置，其中，显示基板包括：显示区域（100）和边缘区域（300）；显示基板还包括：基底（10）以及设置在基底（10）上，且位于边缘区域（300）的电源线（310），电源线（310）包括：相互连接的第一电源部（310A）和第二电源部（310B），第二电源部（310B）位于第一电源部（310A）远离基底（10）的一侧。显示区域（100）包括多个显示单元，至少一个显示单元包括：像素驱动电路和发光器件，像素驱动电路与发光器件的阳极电连接，电源线（VSS）与发光器件的阴极电连接。第二电源部（310B）在基底（10）上的正投影与第一电源部（310A）在基底（10）上的正投影至少部分重叠，且第二电源部（310B）远离显示区域（100）的一端与显示区域（100）之间的距离大于或者等于第一电源部（310A）远离显示区域（100）的一端与显示区域（100）之间的距离。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开还提供了一种显示基板，包括：显示区域和位于显示区域侧面的边缘区域，所述显示基板还包括：基底以及设置在所述基底上，且位于所述边缘区域的电源线，所述电源线包括：相互连接的第一电源部和第二电源部，所述第二电源部位于所述第一电源部远离基底的一侧；
所述显示区域包括：多个显示单元，至少一个显示单元包括：像素驱动电路和发光器件，所述像素驱动电路与所述发光器件的阳极电连接，所述电源线与发光器件的阴极电连接，
所述第二电源部在基底上的正投影与所述第一电源部在基底上的正投影至少部分重叠，且所述第二电源部远离所述显示区域的一端与显示区域之间的距离大于或者等于所述第一电源部远离所述显示区域的一端与显示区域之间的距离。
在一些可能的实现方式中，所述边缘区域包括沿着远离所述显示区域的 方向依次设置的电路区和隔离坝区，所述电路区包括：沿着远离所述显示区域的方向依次设置的第一电路区、第二电路区和第三电路区；
所述像素驱动电路包括：写入晶体管、补偿晶体管、发光晶体管，第一扫描信号线、第二扫描信号线和发光信号线；第一扫描信号线与写入晶体管的控制极电连接，第二扫描信号线与补偿晶体管的控制极电连接，发光信号线与发光晶体管的控制极电连接；所述写入晶体管和所述补偿晶体管的晶体管类型不同；
所述显示基板还包括：位于所述第一电路区的第一驱动电路，位于所述第二电路区的第二驱动电路和位于所述第三电路区和所述隔离坝区的第三驱动电路；
所述第一驱动电路与所述第一扫描信号线电连接，所述第二驱动电路与所述第二扫描信号线电连接，所述第三驱动电路与所述发光信号线电连接；
所述第一电源部位于所述隔离坝区，所述第二电源部位于所述隔离坝区和所述电路区；
所述第二电源部在基底上的正投影与所述第三驱动电路在基底上的正投影至少部分重叠，且与所述第二驱动电路在基底上的正投影不存在重叠区域。
在一些可能的实现方式中，还包括：位于所述隔离坝区的裂纹检测线，所述裂纹检测线与所述第一电源部同层设置，且位于所述第一电源部远离所述显示区域的一侧；
所述第一电源部与所述裂纹检测线之间的距离大于或者等于1微米，且小于或者等于6微米。
在一些可能的实现方式中，所述第一电源部与第三驱动电路之间的距离大于或者等于1微米，且小于或者等于6微米。
在一些可能的实现方式中，还包括：位于所述显示区域、所述电路区和所述隔离坝区的第一平坦层和位于所述隔离坝区的第一保护层；所述第一平坦层位于所述第一电源部和所述第二电源部之间，且与所述第一保护层同层设置；
所述第一保护层在基底上的正投影覆盖所述裂纹检测线在基底上的正投 影，且与所述第一电源部在基底上的正投影至少部分重叠。
在一些可能的实现方式中，所述第三驱动电路包括：位于所述隔离坝区的时钟信号线；所述时钟信号线与所述第一电源部同层设置，且位于所述第一电源部靠近所述显示区域的一侧；
所述第一平坦层在基底上的正投影覆盖所述时钟信号线在基底上的正投影，且与所述第一电源部在基底上的正投影不存在重叠区域。
在一些可能的实现方式中，所述第二电源部开设有暴露出所述第一平坦层的多个第二过孔，所述多个第二过孔呈矩阵式排布；
多个第二过孔在基底上的正投影与所述第三驱动电路在基底上的正投影至少部分重叠。
在一些可能的实现方式中，还包括：位于所述显示区域和所述电路区的第二平坦层和位于所述隔离坝区的第二保护层；
所述第二平坦层位于所述第二电源部远离所述基底的一侧，且与所述第二保护层同层设置；
所述第二保护层在基底上的正投影覆盖所述第一保护层在基底上的正投影，所述第二平坦层在基底上的正投影覆盖所述第二过孔基底上的正投影。
在一些可能的实现方式中，还包括：位于边缘区域的辅助电源线；所述阳极位于所述第二平坦层远离基底的一侧，且与所述辅助电源线同层设置；
所述辅助电源线与所述第二电源部电连接；
所述辅助电源线在基底上的正投影与所述第一驱动电路、所述第二驱动电路和所述第三驱动电路在基底上的正投影至少部分重叠。
在一些可能的实现方式中，所述辅助电源线开设有暴露出第二平坦层的多个第五过孔，所述多个第五过孔呈矩阵式排布；
所述多个第五过孔位于所述第一电路区、所述第二电路区和所述第三电路区；
位于所述第三电路区的第五过孔在基底上的正投影与第二过孔在基底上 的正投影至少部分重叠。
在一些可能的实现方式中，还包括：位于显示区域的像素定义层和位于所述电路区的隔离层；所述像素定义层位于所述阳极所述基底的一侧，且与所述隔离层同层设置；
所述隔离层远离显示区域的一端与显示区域之间的距离小于或者等于所述第二平坦层远离显示区域的一端与显示区域之间的距离，且所述隔离层在基底上的正投影覆盖第五过孔在基底上的正投影。
在一些可能的实现方式中，还包括：依次叠设在所述基底上，且位于所述显示区域的有机发光层和位于所述显示区域和所述电路区的阴极；
所述阴极与所述辅助电源线电连接。
在一些可能的实现方式中，所述隔离坝区还包括：第一隔离坝和第二隔离坝；
所述第二隔离坝位于所述第一隔离坝远离所述显示区域的一侧，且位于所述第二保护层靠近所述显示区域的一侧。
在一些可能的实现方式中，还包括：位于所述隔离坝区的第一坝基、第三坝基、第五坝基和第七坝基；
所述第一坝基与所述第一平坦层同层设置，所述第三坝基与所述第二平坦层同层设置，所述第五坝基与所述像素定义层同层设置，所述第七坝基位于所述像素定义层远离所述基底的一侧；
所述第二电源部覆盖在所述第一坝基上，所述第三坝基设置在覆盖第一坝基的第二电源部上，且所述第三坝基在基底上的正投影覆盖所述第一坝基在基底上的正投影，所述第五坝基设置在第三坝基上，且所述第五坝基在基底上的正投影覆盖第三坝基在基底上的正投影，所述第七坝基设置在第五坝基上，且第五坝基在基底上的正投影覆盖第七坝基在基底上的正投影；
所述辅助电源线部分覆盖所述第三坝基；
所述第一坝基、覆盖所述第一坝基的所述第二电源部、所述第三坝基、所述第五坝基和所述第七坝基形成第二隔离坝。
在一些可能的实现方式中，还包括：位于所述隔离坝区的第二坝基、第四坝基和第六坝基；
所述第二坝基与所述第二平坦层同层设置，所述第四坝基与所述像素定义层同层设置，所述第六坝基与所述第七坝基同层设置；
所述第二坝基设置在所述第二电源部上，所述第四坝基设置在覆盖所述第二坝基的所述辅助电源线上，且所述第四坝基在基底上的正投影覆盖所述第二坝基在基底上的正投影，所述第六坝基设置在所述第四坝基上，且所述第四坝基在基底上的正投影覆盖所述第六坝基在基底上的正投影；
所述第二坝基、覆盖所述第二坝基的所述辅助电源线、所述第四坝基和所述第六坝基形成第一隔离坝。
在一些可能的实现方式中，所述第一隔离坝在基底上的正投影与所述时钟信号线至少部分重叠。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
第三方面，本公开还提供了一种显示基板的制备方法，设置为制成上述显示基板，所述显示基板包括：显示区域和位于显示区域侧面的边缘区域，所述方法包括：
提供一基底；
在所述基底上依次形成第一电源部和第二电源部，以形成位于所述边缘区域的电源线，所述第二电源部在基底上的正投影与所述第一电源部在基底上的正投影至少部分重叠，且所述第二电源部远离所述显示区域的一端与显示区域之间的距离大于或者等于所述第一电源部远离所述显示区域的一端与显示区域之间的距离。
在一些可能的实现方式中，所述在所述基底上依次形成第一电源部和第二电源部包括：
在基底上形成显示区域的像素驱动电路、位于电路区的第一驱动电路、第二驱动电路、位于第三电路区的第三驱动电路以及位于隔离坝区的第一电源部和裂纹检测线；
在形成第一电源部的基底上形成位于显示区域和电路区的第一平坦层和位于隔离坝区的第一坝基和第一保护层；
在形成第一平坦层的基底上形成位于显示区域的连接电极和位于电路区和隔离坝区的第二电源部；
在形成第二电源部的基底上形成位于显示区域和电路区的第二平坦层、位于隔离坝区的第二坝基、第三坝基和第二保护层；
在形成第二平坦层的基底上形成位于显示区域的阳极和位于边缘区域的辅助电源线；
在形成辅助电源线的基底上形成位于显示区域的像素定义层、位于电路区的隔离层以及位于隔离坝区的第四坝基和第五坝基；
在形成像素定义层的基底上形成位于显示区域的有机发光层、位于显示区域和电路区的阴极和位于隔离坝区中的第六坝基和第七坝基。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的结构示意图；
图2为一种像素驱动电路的等效电路示意图；
图3为本公开实施例提供的显示基板的结构示意图；
图4为本公开实施例提供的显示基板的俯视图；
图5为本公开实施例提供的显示基板的部分膜层的俯视图；
图6为一种示例性实施例提供的一种显示基板的结构示意图；
图7为形成显示电路层后的示意图；
图8为图7沿A-A向的截面图；
图9为形成第一有机层后的示意图；
图10为图9沿A-A向的截面图；
图11为形成第二源漏金属层后的示意图；
图12为图11沿A-A向的示意图；
图13为形成第二有机层后的示意图；
图14为图13沿A-A向的截面图；
图15为形成透明导电层后的示意图；
图16为图15沿A-A向的截面图；
图17为形成第三有机层后的示意图；
图18为图17沿A-A向的示意图；
图19为形成有机发光层后的示意图；
图20为图19沿A-A向的截面图；
图21为形成阴极后的示意图；
图22为图21沿A-A向的截面图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
一种低温多晶氧化物显示产品中通过电源线向显示区域提供低电压信号。由于电源线存在一定的阻抗，电压信号传输存在压降，电源线的电压损失降低了显示产品的显示亮度均一性，增大了显示产品的功耗，已经成为影响高品质显示的重要因素。
图1为一种显示基板的结构示意图。如图1所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边缘区域300。
在一种示例性实施例中，显示区域100至少包括规则排列的多个显示单元(子像素)。
在一种示例性实施例中，在垂直于显示基板的平面内，显示单元可以包括设置在基底上的驱动结构层、设置在驱动结构层上的发光器件以及设置在发光器件上的封装层。其中，驱动结构层可以包括像素驱动电路，发光器件与像素驱动电路连接，发光器件配置为出射光线，像素驱动电路配置为驱动发光器件发光。
在一种示例性实施例中，像素驱动电路可以包括多个薄膜晶体管(Thin Film Transistor，简称TFT)和存储电容，如3T1C、4T1C、5T1C、6T1C或7T1C等，本公开对此不做限定。
图2为一种像素驱动电路的等效电路示意图。如图2所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、 第三扫描信号线S3、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在一种示例性实施例中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
在一种示例性实施例中，第一晶体管T1的控制极与第三扫描信号线S3连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第三扫描信号线S3时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
在一种示例性实施例中，第二晶体管T2的控制极与第二扫描信号线S2连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。第二晶体管T2可以称为补偿晶体管，当导通电平扫描信号施加到第二扫描信号线S2时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
在一种示例性实施例中，第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
在一种示例性实施例中，第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为写入晶体管，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
在一种示例性实施例中，第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶 体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
在一种示例性实施例中，第七晶体管T7的控制极与第三扫描信号线S3连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第三扫描信号线S3时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在一种示例性实施例中，发光器件的阴极与第二电源线VSS连接。
在一种示例性实施例中，第一电源线VDD持续提供高电平信号，第二电源线VSS持续提供低电平信号。
在一种示例性实施例中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一种示例性实施例中，第一晶体管T1和第二晶体管T2为N型金属氧化物晶体管，第三晶体管T3到第七晶体管T7为P型低温多晶硅薄膜晶体管
在一种示例性实施例中，写入晶体管和补偿晶体管的晶体管类型不同。
在一种示例性实施例中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线E和初始信号线INIT沿第一方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿第二方向延伸，第一方向和第二方向相交。
在一种示例性实施例中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。发光器件的阳极与像素驱动电路连接。
本公开实施例提供的显示基板可以为低温多晶氧化物显示基板。
在一种示例性实施例中，绑定区域200至少包括隔离坝和将多个显示单 元的信号线连接至外部驱动装置的绑定电路，边缘区域300至少包括隔离坝、栅极驱动电路和向多个显示单元传输电压信号的电源线，绑定区域200和边缘区域300的隔离坝形成环绕显示区域100的环形结构。
图3为本公开实施例提供的显示基板的结构示意图，图3为图1中C区域的放大图，图4为本公开实施例提供的显示基板的俯视图，图3是图4沿A-A向的截面图，图5为本公开实施例提供的显示基板的部分膜层的俯视图。如图3至图5所示，在平行于显示基板的平面内，边缘区域300包括沿着远离显示区域100的方向依次设置的电路区301和隔离坝区302。电路区301包括：沿着远离显示区域100的方向依次设置的第一电路区301A、第二电路区301B和第三电路区301C。
在一种示例性实施例中，电路区301至少包括栅极驱动电路。其中，栅极驱动电路分别与显示区域100中像素驱动电路101的第一扫描信号线、第二扫描信号线和发光信号线电连接。
在一种示例性实施例中，位于边缘区域300的栅极驱动电路可以包括：第一驱动电路201、第二驱动电路202和第三驱动电路203。
在一种示例性实施例中，第一驱动电路201与第一扫描信号线电连接。
在一种示例性实施例中，第二驱动电路202与第二扫描信号线电连接。其中，第二驱动电路202还可以包括时钟信号线CLK。
在一种示例性实施例中，第三驱动电路203与发光信号线电连接，第三驱动电路203还可包括时钟信号线ECLK。
在一种示例性实施例中，第一驱动电路201可以为8T2C电路结构，或者其他电路结构。
在一种示例性实施例中，第二驱动电路202可以为10T3C或者13T3C电路结构，本公开对此不作任何限定。
在一种示例性实施例中，第一驱动电路201位于第一电路区301A，第二驱动电路202位于第二电路区301B，第三驱动电路203位于第三电路区301C和隔离坝区302。
在一种示例性实施例中，隔离坝区302至少包括与发光器件阴极连接的 电源线310、第一隔离坝410、第二隔离坝420、裂纹检测线320和第三驱动电路203的时钟信号线ECLK。
在一种示例性实施例中，电源线310沿着平行于显示区域边缘的方向延伸，与显示区域100中像素驱动电路101的第二电源线VSS连接。
在一种示例性实施例中，电源线310包括：相互连接的第一电源部310A和第二电源部310B，第二电源部310B位于第一电源部310A远离基底的一侧。
在一种示例性实施例中，第二电源部310B在基底上的正投影与第一电源部310A在基底上的正投影至少部分重叠，且第二电源部310B远离显示区域100的一端与显示区域100之间的距离大于或者等于第一电源部310A远离显示区域100的一端与显示区域100之间的距离。
在一种示例性实施例中，第一电源部310A位于隔离坝区302。
在一种示例性实施例中，第二电源部310B至少位于隔离坝区302和第三电路区301C。第二电源部310B还可以位于第二电路区301B，其中，第二电源部310B在基底上的正投影与第三驱动电路203在基底上的正投影至少部分重叠，且与第二驱动电路202在基底上的正投影不存在重叠区域。
在一种示例性实施例中，第二驱动电路包括：时钟信号线CLK。第二电源部310B靠近显示区域100的一端与显示区域100之间的距离大于时钟信号线CLK远离显示区域100的一端与显示区域100之间的距离，即第二电源部310B在基底上的正投影与时钟信号线CLK在基底上的正投影不存在重叠区域。
在一种示例性实施例中，裂纹检测线320沿着平行于显示区域边缘的方向延伸，且位于电源线310远离显示区域100的一侧。裂纹检测线设置为检测显示基板是否存在裂纹。
在一种示例性实施例中，第一隔离坝410和第二隔离坝420沿着平行于显示区域边缘的方向延伸，配置为阻隔从边缘区域300进入显示区域100的水汽。
在一种示例性实施例中，第一隔离坝410与显示区域100之间的距离小 于第二隔离坝420与显示区域100之间的距离，即第二隔离坝420设置在第一隔离坝410远离显示区域100的一侧。
在一种示例性实施例中，显示区域100中像素驱动电路所连接的发光器件所需的低电压从绑定区域200的绑定焊盘引入，经过绑定区域200后进入边缘区域300，通过边缘区域300环形的电源线310输送给每个像素驱动电路的第二电源线VSS。
本公开中，图3示意了一种顶发射型OLED显示区域和外围区域的剖面结构。按照出光方向，OLED可以分为底发射型、顶发射型与双面发射型。与底发射型OLED相比，顶发射型OLED具有开口率高、色纯度高、容易实现高分辨率(Pixels Per Inch，简称PPI)等优点，逐渐成为目前主流结构。对于顶发射型OLED，由于出光方向在阴极一侧，为了保证良好的透光性，要求阴极很薄，因此为阴极提供低电压的电源线的压降对提高显示亮度均一性有比较重要的影响。
如图3至图6，并结合图7～图22，本公开示例性实施例显示基板包括显示区域100和边缘区域300，边缘区域300包括沿着远离显示区域100的方向依次设置的电路区301和隔离坝区302。
在一种示例性实施例中，显示基板的显示区域100包括：
基底10；
设置在基底10上的第一绝缘层11；
设置在第一绝缘层11上的有源层，有源层至少包括位于第一有源层；
覆盖有源层的第二绝缘层12；
依次设置在第二绝缘层12上的第一栅金属层、第三绝缘层13、第二栅金属层和第四绝缘层14，第一栅金属层至少包括第一栅电极；第二绝缘层12、第三绝缘层13和第四绝缘层14设置有暴露出第一有源层的过孔。
设置在第四绝缘层14上的第一源漏金属层，第一源漏金属层至少包括第一源电极和第一漏电极，第一源电极和第一漏电极分别通过暴露出第一有源层的过孔与第一有源层连接；
设置在第一源漏金属层上的第一有机层，第一有机层至少包括：覆盖第一源漏金属层的第一平坦层15，第一平坦层15设置有暴露出第一漏电极的第一过孔；
设置在第一有机层上的第二源漏电极层，第二源漏金属层至少包括设置在第一平坦层15上的连接电极17，连接电极17通过第一过孔与第一漏电极连接；
设置第二源漏电极层上的第二有机层，第二有机层至少包括：覆盖连接电极17的第二平坦层16，其上设置有暴露出连接电极17的第二过孔；
设置在第二有机层上的透明导电层，透明导电层至少包括：设置在第二平坦层16上的阳极21，阳极21通过第二过孔与连接电极17连接；
设置在透明导电层上的第三有机层，第三有机层至少包括：设置在阳极21上的像素定义层22，像素定义层22上设置有暴露出阳极21的第五过孔；
设置在第五过孔内的有机发光层24，有机发光层24与阳极22连接；
设置有机发光层24和像素定义层22上的阴极25，阴极25与有机发光层24连接。
在一种示例性实施例中，显示基板的边缘区域300包括：
基底10；
设置在基底10上的第一绝缘层11；
设置在第一绝缘层11上的有源层，有源层至少包括位于电路区301的第二有源层、第三有源层和第四有源层；
覆盖有源层的第二绝缘层12；
设置在第二绝缘层12上的第一栅金属层，第一栅金属层至少包括位于第一电路区301A的第二栅电极和第一电容电极、位于第二电路区301B的第三栅电极和第二电容电极和位于第三电路区301C的第四栅电极和第三电容电极；
覆盖第一栅金属层的第三绝缘层13；
设置在第三绝缘层13的第二栅金属层，第二栅金属层至少包括位于第一电路区301A的第四电容电极、位于第二电路区301B的五电容电极和位于第三电路区301C的第六电容电极；
覆盖第二栅金属层的第四绝缘层14，电路区301的第四绝缘层14上设置有暴露出第二有源层、第三有源层和第四有源层的多个过孔；
设置在第四绝缘层14上的第一源漏金属层，第一源漏金属层至少包括位于电路区301的第二源电极、第二漏电极、第三源电极和第三漏电极，第四源电极和第四漏电极以及位于隔离坝区302的第一电源部310A、时钟信号线ECLK和裂纹检测线320；第二源电极和第二漏电极分别通过暴露出第二有源层的过孔与第二有源层连接，第三源电极和第三漏电极分别通过暴露出第三有源层的过孔与第三有源层连接，第四源电极和第四漏电极分别通过暴露出第四有源层的过孔与第四有源层连接；
设置在第一源漏金属层上的第一有机层，第一有机层至少包括：位于电路区301和隔离坝区302的第一平坦层15，以及形成在隔离坝区302的第一坝基421和第一保护层431；隔离坝区302的第一坝基421设置在第一电源部310A上，第一保护层431设置在裂纹检测线320和第一电源部310A上，第一保护层431覆盖裂纹检测线320，且覆盖第一电源部310A远离显示区域的一端，第一平坦层15覆盖时钟信号线ECLK；
设置在第一有机层上的第二源漏电极层，第二源漏金属层至少包括位于隔离坝区302的第二电源部310B，第二电源部310B覆盖第一坝基421，第二电源部310B上设置有暴露出第一平坦层的第二过孔；
设置第二源漏电极层上的第二有机层，第二有机层至少包括：在电路区301的第二平坦层16，以及设置在隔离坝区302的第二坝基411、第三坝基422和第二保护层432，第三坝基422设置在覆盖第一坝基421的第二电源部310B上，第二坝基411设置在第一坝基421邻近显示区域100一侧的第二电源部310B上，第二保护层432设置在第一保护层431上，且覆盖第二电源部310B远离显示区域的一端，第二平坦层16开设有暴露出第二电源部310B的第四过孔；
设置在第二有机层上的透明导电层，透明导电层至少包括：位于电路区301和隔离坝区302的辅助电源线330，位于电路区301上的辅助电源线330上设置有多个第五过孔；隔离坝区302的辅助电源线330覆盖第二坝基411，且部分覆盖第三坝基422；位于第二坝基411邻近显示区域100一侧的辅助电源线330和位于第二坝基402远离显示区域100一侧的辅助电源线330均搭接在第二电源部310B上；
设置在透明导电层上的第三有机层，第三有机层至少包括：位于电路区301的隔离层23以及位于隔离坝区302的第四坝基412和第五坝基423，隔离层23开设有暴露出辅助电源线330的第七过孔，第四坝基412设置在覆盖第二坝基411的辅助电源线330上，第五坝基423设置在第三坝基422上。
设置在电路区301的阴极25，阴极25通过第七过孔与辅助电源线330电连接；
设置在隔离坝区302的第六坝基413和第七坝基424，第六坝基413位于第四坝基412上，第七坝基424位于第五坝基423上。
在一种示例性实施例中，第六坝基413和第七坝基424可以复用为隔离柱。
第二坝基402、覆盖第二坝基的辅助电源线330、第四坝基412和第六坝基413形成第一隔离坝410。
在一种示例性实施例中，第一坝基421、覆盖第一坝基的第二电源部310B、第三坝基422、第五坝基423和第七坝基424形成第二隔离坝420。
图6为一种示例性实施例提供的一种显示基板的结构示意图。如图6所示，一种示例性实施例提供的显示基板还可以包括：封装层26。封装层26可以包括：依次叠设在基底上的第一封装层261、第二封装层262和第三封装层263。显示区域100和电路区301的封装层为第一封装层/第二封装层/第三封装层的叠层结构，隔离坝区302的封装层为第一封装层/第三封装层的叠层结构。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、 显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施例中，如图7至图22所示，显示基板包括显示区域100和边缘区域300，边缘区域300包括沿着远离显示区域100的方向依次设置的电路区301和隔离坝区302。电路区301包括：沿着远离显示区域100的方向依次设置的第一电路区301A、第二电路区301A和第三电路区301C。显示区域100包括：像素驱动电路101，第一电路区301A包括：第一驱动电路201，第二电路区301A包括：第二驱动电路202，隔离坝区302和第三电路区301C包括：第三驱动电路203。像素驱动电路101、第一驱动电路201、第二驱动电路202和第三驱动电路203中至少包括：多个晶体管和至少一个电容，如图7至图22中仅示出了像素驱动电路中的一个晶体管，第一驱动电路至第三驱动电路中的一个晶体管和一个电容。
一种示例性实施例提供的显示基板的制备过程可以包括：
(1)提供一基底10，在基底10上制备显示电路层图案，显示电路层图案包括：位于显示区域100的驱动结构层和位于外围区域300的电路结构层图案。显示区域100的驱动结构层包括像素驱动电路101，外围区域300的电路结构层包括位于第一电路区301A的第一驱动电路201、位于第二电路区301B的第二驱动电路202和位于第三电路区301C的第三驱动电路203，还 包括位于隔离坝区302的第一电源部310A、第三驱动电路203的时钟信号线ECLK和裂纹检测线320，如图7和图8所示，图7为形成显示电路层后的示意图，图8为图7沿A-A向的截面图。
在一种示例性实施例中，基底10可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。本次工艺后，显示区域100和外围区域300均包括基底10。
在一种示例性实施例中，显示电路层的制备过程可以包括：
在基底10上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底10的第一绝缘层11，以及设置在第一绝缘层11上的半导体层图案，半导体层图案至少包括位于显示区域100的第一有源层，以及位于第一电路区301A的第二有源层、位于第二电路区301B的第三有源层和位于第三电路区301C的第四有源层。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案，且覆盖整个基底的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案，第一栅金属层图案至少包括位于显示区域100的第一栅电极、位于第一电路区301A的第二栅电极和第一电容电极、位于第二电路区301B的第三栅电极和第二电容电极以及位于第三电路区301C的第四栅电极和第三电容电极。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一栅金属层图案，且覆盖整个基底的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案，第二栅金属层图案至少包括位于第一电路区301A的第四电容电极、位于第二电路区301B的第五电容电极以及位于第三电路区301C的第六电容电极。
在一种示例性实施例中，第一电容电极在基底上的正投影与第四电容电 极在基底上的正投影至少部分重叠，第一电容电极和第四电容电极构成第一驱动电路中的电容。
在一种示例性实施例中，第二电容电极在基底上的正投影与第五电容电极在基底上的正投影至少部分重叠，第二电容电极和第五电容电极构成第二驱动电路中的电容。
在一种示例性实施例中，第三电容电极在基底上的正投影与第六电容电极在基底上的正投影至少部分重叠，第三电容电极和第六电容电极构成第三驱动电路中的电容。
随后，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二栅金属层图案，且覆盖整个基底的第四绝缘层14。其中，第二绝缘层12、第三绝缘层13和第四绝缘层14在显示区域100开设有暴露出第一有源层的过孔，在第一电路区301A开设有暴露出第二有源层的过孔，在第二电路区301B开设有暴露出第三有源层的过孔，在第三电路区301C开设有暴露出第四有源层的过孔。
随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层14上形成第一源漏金属层图案，第一源漏金属层图案至少包括：位于显示区域100的第一源电极和第一漏电极，位于第一电路区301A的第二源电极和第二漏电极、位于第二电路区301B的第三源电极和第三漏电极、位于第三电路区301C的第四源电极和第四漏电极以及形成在隔离坝区302的第一电源部310A、第三驱动电路的时钟信号线ECLK和裂纹检测线320。
在一种示例性实施例中，形成在隔离坝区302的第一电源部310A、第三驱动电路的时钟信号线ECLK和裂纹检测线320设置在第四绝缘层14上，裂纹检测线320设置在第一电源部310A远离显示区域100一端，第三驱动电路的时钟信号线ECLK位于第一电源部310A靠近显示区域100的一端。
在一种示例性实施例中，第一源电极和第一漏电极分别通过第二绝缘层12、第三绝缘层13和第四绝缘层14过孔与第一有源层连接，第二源电极和第二漏电极分别通过第二绝缘层12、第三绝缘层13和第四绝缘层14与第二有源层连接，第三源电极和第三漏电极分别通过第二绝缘层12、第三绝缘层 13和第四绝缘层14与第三有源层连接，第四源电极和第四漏电极分别通过第二绝缘层12、第三绝缘层13和第四绝缘层14与第四有源层连接。
至此，在基底上制备完成显示电路层图案。
在一种示例性实施例中，第一有源层可以包括像素驱动电路中的所有晶体管的有源层，第一栅电极可以包括：像素驱动电路中的所有晶体管的有源层的栅电极、第一源电极可以包括：像素驱动电路中的所有晶体管的源电极以及第一漏电极可以包括：像素驱动电路中的所有晶体管的漏电极。
在一种示例性实施例中，第二有源层可以包括第一驱动电路中的所有晶体管的有源层，第二栅电极可以包括：第一驱动电路中的所有晶体管的有源层的栅电极、第二源电极可以包括：第一驱动电路中的所有晶体管的源电极以及第二漏电极可以包括：第一驱动电路中的所有晶体管的漏电极。
在一种示例性实施例中，第三有源层可以包括第二驱动电路中的所有晶体管的有源层，第三栅电极可以包括：第二驱动电路中的所有晶体管的有源层的栅电极、第三源电极可以包括：第二驱动电路中的所有晶体管的源电极以及第三漏电极可以包括：第二驱动电路中的所有晶体管的漏电极。
在一种示例性实施例中，第四有源层可以包括第三驱动电路中的所有晶体管的有源层，第四栅电极可以包括：第三驱动电路中的所有晶体管的有源层的栅电极、第四源电极可以包括：第三驱动电路中的所有晶体管的源电极以及第四漏电极可以包括：第三驱动电路中的所有晶体管的漏电极。
在一种示例性实施例中，第一电源部310A与第三驱动电路203之间的距离L1大于或者等于3微米，且小于或者等于5微米，示例性地，第一电源部310A与第三驱动电路203之间的距离可以为4微米，本公开对此不作任何限定。
在一种示例性实施例中，第一电源部310A与第三驱动电路203之间的距离L1可以是指第一电源部与第三驱动电路的时钟信号线ECLK之间的最短距离。
在一种示例性实施例中，第一电源部310A与裂纹检测线320之间的距离L2大于或者等于3微米，且小于或者等于5微米，示例性地，第一电源 部310A与裂纹检测线320之间的距离可以为4微米，本公开对此不作任何限定。
在一种示例性实施例中，第一电源部310A与第三驱动电路203之间的距离L1和第一电源部310A与裂纹检测线320之间的距离L2可以相等，或者可以不相等，本公开对此不作任何限定。
在一种示例性实施例中，第一源漏金属层的厚度可以约为700nm至1000nm。示例性地，第一源漏金属层的厚度可以约为860nm。
(2)在形成前述图案的基底上涂覆第一有机薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成第一有机层图案，第一有机层图案包括：位于显示区域100、电路区301和隔离坝区302的第一平坦层15和位于隔离坝区302的第一坝基421和第一保护层431，如图9和图10所示，图9为形成第一有机层后的示意图，图10为图9沿A-A向的截面图。
在一种示例性实施例中，第一平坦层15开设有暴露出第一漏电极的第一过孔V1。
在一种示例性实施例中，第一平坦层15在基底上的正投影覆盖第三驱动电路的时钟信号线ECLK在基底上的正投影，且与第一电源部310A在基底上的正投影不存在重叠区域。
在一种示例性实施例中，在平行于显示基板的平面内，第一过孔V1的形状可以是三角形、矩形、多边形、圆形或椭圆形等。
在一种示例性实施例中，第一过孔V1的形状可以是矩形，矩形的长度可以约为10μm到40μm，矩形的宽度可以约为10μm到40μm，相邻第一过孔V5之间的距离可以约为10μm到40μm。
在一种示例性实施例中，位于隔离坝区302的第一平坦层的表面不平坦。其中，位于隔离坝区302的第一平坦层包括：第一子平坦层和第二子平坦层，第一子平坦层P1位于第二子平坦层P2远离显示区域100的一侧，第一子平坦层P1的厚度小于第二子平坦层P2的厚度。
在一种示例性实施例中，第二子平坦层P2在基底上的正投影覆盖第三 驱动电路203。
在一种示例性实施例中，第一子平坦层P1的厚度可以等于第一电源部310A的厚度，第二子平坦层P2的厚度可以等于位于显示区域100的第一平坦层的厚度。
在一种示例性实施例中，第一坝基421位于第一电源部310A远离基底的一侧，且第一电源部310A在基底上的正投影与第一坝基421在基底上的正投影至少部分重叠。
在一种示例性实施例中，第一坝基421沿第一方向的长度小于第一电源部310A沿第一方向的长度，即第一坝基421靠近显示区域的一侧和远离显示区域的一侧均暴露出第一电源部310A。
在一种示例性实施例中，第一保护层431位于第一坝基421远离显示区域100的一侧。
在一种示例性实施例中，第一保护层431在基底上的正投影覆盖裂纹检测线320在基底上的正投影，且与第一电源部310A在基底上的正投影至少部分重叠，即第一保护层431覆盖裂纹检测线320和第一电源部310A远离显示区域100的一端。
在一种示例性实施例中，第一坝基421沿第一方向的长度可以约为20μm到60μm，第一坝基421配置为形成第二隔离坝。
在一种示例性实施例中，在垂直于显示基板的平面内，第一坝基421的截面形状可以为梯形或者矩形。当第一坝基421的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
(3)在形成前述图案的基底上沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化，形成第二源漏金属层图案，第二源漏金属层图案至少包括位于显示区域100的连接电极17和位于电路区301和隔离坝区302的第二电源部310B，如图11和12所示，图11为形成第二源漏金属层后的示意图，图12为图11沿A-A向的示意图。
在一种示例性实施例中，连接电极17通过第一过孔V1与第一漏电极电连接。
在一种示例性实施例中，第二电源部310B至少位于隔离坝区302和第三电路区301C。
在一种示例性实施例中，第二电源部310B还可以位于第二电路区301B。
在一种示例性实施例中，第二电源部310B在基底上的正投影覆盖第一电源部310A和第三驱动电路203在基底上的正投影，且与第一保护层431在基底上的正投影部分重叠。
在一种示例性实施例中，第二电源部310B远离显示区域的一端与显示区域之间的距离可以大于或者等于第一电源部310A远离显示区域的一端与显示区域之间的距离。图12是以第二电源部310B远离显示区域的一端与显示区域之间的距离等于第一电源部310A远离显示区域的一端与显示区域之间的距离为例进行说明的。
在一种示例性实施例中，第二电源部310B在基底上的正投影与第二驱动电路202在基底上的正投影不存在重叠区域。第二电源部310B靠近显示区域100的一端与显示区域100之间的距离大于第二驱动电路202中的时钟信号线与显示区域100之间的距离，即第二电源部310B在基底上的正投影与第二驱动电路202中的时钟信号线在基底上的正投影不重叠，第二电源部310B在基底上的正投影与第二驱动电路202中的时钟信号线在基底上的正投影不重叠可以保证显示基板的显示效果。
在一种示例性实施例中，第二电源部310B覆盖第一坝基421的表面，且第二电源部310B设置在第一坝基421两侧暴露出的第一电源部310A上，实现第二电源部310B与第一电源部310A的连接，
在一种示例性实施例中，裂纹检测线320靠近显示区域的一端与显示区域之间的距离大于第二电源部310B远离显示区域的一端与显示区域之间的距离，即第二电源部310B在基底上的正投影与裂纹检测线320在基底上的正投影不重叠。
在一种示例性实施例中，第二电源部310B开设有暴露出第一平坦层15 的多个第二过孔V2。第二过孔V2设置为释放第一平坦层15中的气体，以形成放气通道，在工艺过程中排放平坦化膜层产生的气体，避免造成膜层剥离(peeling)，提高工艺质量。
在一种示例性实施例中，第二过孔V2的数量为多个，多个第二过孔V2呈矩阵式排布，可以均匀的释放第一平坦层15中的气体。
这样，第一源漏金属层的第一电源部310A和第二源漏金属层的第二电源部310B在边缘区域300形成双层电源线，通过在隔离坝区302搭接实现了并联结构的双层电源走线，减小了边缘区域200的电源走线的电阻，最大限度地减小了电压信号的压降，提高了显示区域显示亮度均一性，提高了显示品质。
在一种示例性实施例中，第二过孔的形状可以是三角形、矩形、多边形、圆形或椭圆形等。在一种示例性实施例中，第二过孔的形状可以是矩形，矩形的长度可以约为10μm到40μm，矩形的宽度可以约为10μm到40μm，相邻第二过孔之间的距离可以约为10μm到40μm。
在一种示例性实施例中，第一坝基421包括第一表面、第一近侧面和第一远侧面。第二电源部310B覆盖第一坝基421的表面可以是指第二电源部310B完全覆盖第一坝基401的第一表面、第一近侧面和第一远侧面，即第二电源部310B将第一坝基401的第一表面、第一近侧面和第一远侧面包裹起来。
在一种示例性实施例中，第二源漏金属层的厚度可以约为700nm至1000nm。在一些可能的实现方式中，第二源漏金属层的厚度可以约为860nm。
(4)在形成前述图案的基底上涂覆第二有机薄膜，通过图案化工艺对第二有机薄膜进行图案化，形成第二有机层图案，第二有机层图案包括：位于显示区域100和电路区301的第二平坦层16、位于隔离坝区302的第二坝基411、第三坝基422和第二保护层432，如图13和图14所示，图13为形成第二有机层后的示意图，图14为图13沿A-A向的截面图。
在一种示例性实施例中，第二平坦层16开设有暴露出连接电极17的第三过孔V3和暴露出第二电源部310B的表面的第四过孔V4。
在一种示例性实施例中，第四过孔V4在基底上的正投影与第二过孔V2在基底上的正投影不重叠。
在一种示例性实施例中，第四过孔V4沿第一方向的宽度W1小于沿第一方向排布的相邻两个第二过孔之间的距离W2。
在一种示例性实施例中，在平行于显示基板的平面内，第三过孔V3和第四过孔V4的形状可以是三角形、矩形、多边形、圆形或椭圆形等。
在一种示例性实施例中，第三过孔V3和第四过孔V4的形状可以是矩形，矩形的长度可以约为10μm到40μm，矩形的宽度可以约为10μm到40μm，相邻第三过孔和相邻第四过孔之间的距离可以约为10μm到40μm。
在一种示例性实施例中，第二平坦层16覆盖第二电源部310B靠近显示区域100的一端，且第二平坦层16在基底上的正投影覆盖第二过孔在基底上的正投影。
在一种示例性实施例中，第二平坦层16远离显示区域100的一端与显示区域100之间的距离小于第三驱动电路203远离显示区域100的一端与显示区域100之间的距离，且第二平坦层16远离显示区域100的一端与显示区域100之间的距离小于第一平坦层15远离显示区域100的一端与显示区域100之间的距离。
在一种示例性实施例中，第二坝基411设置在第一坝基421邻近显示区域100一侧的第二电源部310B上。
在一种示例性实施例中，第二坝基411在基底上的正投影与第三驱动电路的时钟信号线在基底上的正投影至少部分重叠。
在一种示例性实施例中，第二坝基411邻近显示区域100的一侧和第二坝基411远离显示区域100的一侧均暴露出第二电源部310B。
在一种示例性实施例中，在垂直于显示基板的平面内，第二坝基411的截面形状可以为梯形或者矩形。当第二坝基411的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第二坝基411沿第一方向的长度可以约为20μm到60μm，第二坝基411配置为形成第一隔离坝。
在一种示例性实施例中，第三坝基422设置在覆盖第一坝基421的第二电源部310B上，第三坝基422在基底上的正投影覆盖第一坝基421在基底上的正投影。
在一种示例性实施例中，在垂直于显示基板的平面内，第三坝基422的截面形状可以为梯形或者矩形。当第三坝基422的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第二保护层432在基底上的正投影覆盖第一保护层431在基底上的正投影，即第二保护层432覆盖第二电源部310B远离显示区域100的一端。
在一种示例性实施例中，第三坝基422沿第一方向的长度可以约为20μm到60μm，第一坝基421和第三坝基422配置为形成第二隔离坝。
(5)在形成前述图案的基底上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成透明导电层图案，透明导电层图案包括：位于显示区域100的阳极21和位于边缘区域300的辅助电源线330，如图15和图16所示，图15为形成透明导电层后的示意图，图16为图15沿A-A向的截面图。
在一种示例性实施例中，阳极21形成在显示区域100的第二平坦层16上，通过第三过孔V3与连接电极17连接。
在一种示例性实施例中，辅助电源线330与第二电源部310B电连接，其中，辅助电源线330的一部分搭接在第二电源部310B上，另一部分通过第四过孔V4与第二电源部310B连接。
在一种示例性实施例中，辅助电源线330在基底上的正投影与第三坝基422在基底上的正投影至少部分重叠，且辅助电源线330远离显示区域100的一端与显示区域100之间的距离小于第三坝基422远离显示区域100的一端与显示区域100之间的距离，即辅助电源线330部分覆盖第三坝基422。
在一种示例性实施例中，第三坝基422包括第三表面、第三近侧面和第三远侧面。辅助电源线330部分覆盖第三坝基422可以是指，辅助电源线330部分覆盖第三坝基422的第三表面，且完全覆盖第三坝基的第二近侧面。
在一种示例性实施例中，辅助电源线330在基底上的正投影覆盖第二坝基411在基底上的正投影，即辅助电源线330覆盖第二坝基411。
在一种示例性实施例中，第二坝基411包括第二表面、第二近侧面和第二远侧面。辅助电源线330覆盖第二坝基411可以是指，辅助电源线330完全覆盖第二坝基411的第二表面、第二近侧面和第二远侧面。即辅助电源线330将第二坝基411的第二表面、第二近侧面和第二远侧面包裹起来。
在一种示例性实施例中，辅助电源线330上的正投影与第二坝基411两侧暴露出的第二电源部310B在基底上的正投影至少部分重叠，即辅助电源线330覆盖第二坝基411两侧暴露出的第二电源部310B，且与第二坝基411两侧暴露出的第二电源部310B电连接。由于辅助电源线330与第二电源部310B连接，因而实现了辅助电源线330与电源线310的连接。
在一种示例性实施例中，辅助电源线330在基底上的正投影与第一驱动电路201、第二驱动电路202和第三驱动电路203在基底上的正投影至少部分重叠。
在一种示例性实施例中，辅助电源线330开设有暴露出第二平坦层16的第五过孔V5，第五过孔V5位于第一电路区301A、第二电路区301B和第三电路区301C。
在一种示例性实施例中，位于第三电路区301C的第五过孔V5在基底上的正投影与第二过孔V2在基底上的正投影至少部分重叠。
在一种示例性实施例中，第五过孔V5设置为释放第二平坦层16中的气体，以形成放气通道，在工艺过程中排放平坦化膜层产生的气体，避免造成膜层剥离(peeling)，提高工艺质量。
在一种示例性实施例中，第五过孔V5的数量为多个，多个第五过孔V5呈矩阵式排布，可以均匀的释放第二平坦层16中的气体。
在一种示例性实施例中，在平行于显示基板的平面内，第五过孔V5的形状可以是三角形、矩形、多边形、圆形或椭圆形等。
在一种示例性实施例中，第五过孔V5的形状可以是矩形，矩形的长度可以约为10μm到40μm，矩形的宽度可以约为10μm到40μm，相邻第五过孔V5之间的距离可以约为10μm到40μm。
(6)在形成前述图案的基底上涂覆第三有机薄膜，通过图案化工艺对第三有机薄膜进行图案化，形成第三有机层图案，第三有机层图案包括：位于显示区域100的像素定义层22、位于电路区301的隔离层23以及位于隔离坝区302的第四坝基412和第五坝基423，图17为形成第三有机层后的示意图，图18为图17沿A-A向的示意图。
在一种示例性实施例中，像素定义层22上开设有暴露出阳极21的第六过孔V6。
在一种示例性实施例中，在平行于显示基板的平面内，第六过孔V6的形状可以是三角形、矩形、多边形、圆形或椭圆形等。
在一种示例性实施例中，第六过孔V6的形状可以是矩形，矩形的长度可以约为10μm到40μm，矩形的宽度可以约为10μm到40μm，相邻第六过孔V6之间的距离可以约为10μm到40μm。
在一种示例性实施例中，隔离层23靠近显示区域100的一端与显示区域100之间的距离等于像素定义层22远离显示区域100的一端与显示区域100之间的距离，且隔离层23远离显示区域100的一端与显示区域100之间的距离小于或者等于第二平坦层16远离显示区域100的一端与显示区域100之间的距离。
在一种示例性实施例中，隔离层23远离显示区域的一端与显示区域之间的距离小于或者等于第二平坦层远离显示区域的一端与显示区域之间的距离。
在一种示例性实施例中，隔离层23在基底上的正投影覆盖第五过孔在基底上的正投影。
在一种示例性实施例中，隔离层23开设有暴露出辅助电源线330的多个 第七过孔V7。多个第七过孔V7可以阵列式排布，或者多个第七过孔可以互通，图17和图18是以多个第七过孔可以互通为例进行说明的。
在一种示例性实施例中，多个第七过孔V7位于第一电路区301A、第二电路区301B和第三电路区301C。
在一种示例性实施例中，位于第三电路区301C的第七过孔V7在基底上的正投影与第四过孔V4在基底上的正投影至少部分重叠。
在一种示例性实施例中，第四坝基412设置在覆盖第二坝基411的辅助电源线330上，且第四坝基412在基底上的正投影覆盖第二坝基411在基底上的正投影。
在一种示例性实施例中，第四坝基412沿第一方向的长度可以约为20μm到60μm。
在一种示例性实施例中，在垂直于显示基板的平面内，第四坝基412的截面形状可以为梯形或者矩形。当第四坝基412的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第五坝基423设置在第三坝基422上，且第五坝基423在基底上的正投影覆盖第三坝基422在基底上的正投影。
在一种示例性实施例中，第五坝基423沿第一方向的可以约为20μm到60μm。
在一种示例性实施例中，在垂直于显示基板的平面内，第五坝基423的截面形状可以为梯形或者矩形。当第五坝基423的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第四坝基412和第五坝基423之间暴露出辅助电源线330，且第四坝基412靠近显示区域100的一侧暴露出辅助电源线330。
(7)在形成前述图案的基底上形成有机发光层24，如图19和图20所示，图19为形成有机发光层后的示意图，图20为图19沿A-A向的截面图。
在一种示例性实施例中，有机发光层24形成在显示区域100的像素界定层的第六过孔V6内，实现有机发光层24与阳极21连接。由于阳极21与连接电极17连接，连接电极17与第一漏电极连接，因而实现了有机发光层24与第一漏电极的连接。
在一种示例性实施例中，有机发光层24可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
(8)在形成前述图案的基底上形成位于显示区域100和电路区301的阴极25和位于隔离坝区302中的第六坝基413和第七坝基424，如图21和图22所示，图21为形成阴极后的示意图，图22为图21沿A-A向的截面图。
在一种示例性实施例中，阴极25远离显示区域100的一端与显示区域100之间的距离小于隔离层23远离显示区域100的一侧与显示区域100之间的距离。
在一种示例性实施例中，阴极25的一部分形成在显示区域100的有机发光层24上，阴极25与有机发光层24连接，阴极25的另一部分通过第七过孔与辅助电源线330连接。
在一种示例性实施例中，由于阴极25与辅助电源线330连接，辅助电源线330与电源线310的第二电源部310B电连接，因而实现了阴极25与电源线310的连接。
在一种示例性实施例中，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、 铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，第六坝基413设置在第四坝基412上，且第四坝基在基底上的正投影覆盖第六坝基413在基底上的正投影。
在一种示例性实施例中，第六坝基413沿第一方向的可以约为20μm到60μm。
在一种示例性实施例中，在垂直于显示基板的平面内，第六坝基413的截面形状可以为梯形或者矩形。当第六坝基413的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第二坝基402、覆盖第二坝基的辅助电源线330、第四坝基411和第六坝基413形成第一隔离坝410。
在一种示例性实施例中，第七坝基424设置在第五坝基423上，且第五坝基423在基底上的正投影覆盖第七坝基424在基底上的正投影。
在一种示例性实施例中，第七坝基424沿第一方向的可以约为20μm到60μm。
在一种示例性实施例中，在垂直于显示基板的平面内，第七坝基424的截面形状可以为梯形或者矩形。当第七坝基424的截面形状为梯形时，远离基底一侧的表面的长度小于靠近基底一侧的表面长度，远离基底一侧的表面的长度可以约为20μm到40μm。
在一种示例性实施例中，第一坝基421、覆盖第一坝基的第二电源部310B、第三坝基422、第五坝基423和第七坝基424形成第二隔离坝420。
在一种示例性实施例中，第一隔离坝410与显示区域100之间的距离小于第二隔离坝420与显示区域100之间的距离。
在一种示例性实施例中，第一隔离坝410和第二隔离坝420在基底上正投影沿第一方向的长度可以约为20μm到60μm，第一隔离坝410与第二隔离坝420之间的距离可以约为20μm到60μm。
在一种示例性实施例中，在垂直于显示基板的平面内，第一隔离坝410和第二隔离坝420的截面形状可以为梯形。
在一种示例性实施例中，第六坝基413和第七坝基424为一体成型结构。阴极25可以形成在第六坝基413和第七坝基424之前，或者可以形成在第六坝基413和第七坝基424之后。
在一种示例性实施例中，第一隔离坝410在基底上的正投影与第三驱动电路的时钟信号线在基底上的正投影至少部分重叠。
(9)在形成前述图案的基础上形成封装层26，封装层26形成在显示区域100、电路区301和隔离坝区302，如图5所示。
在一种示例性实施例中，显示区域100和电路区301的封装层26采用第一封装层261、第二封装层262和第三封装层263的叠层结构，隔离坝区302的封装层26采用第一封装层261和第三封装层263的叠层结构。
在一种示例性实施例中，第一封装层可以采用无机材料，在显示区域100覆盖阴极25，在电路区301覆盖隔垫柱层23，在隔离坝区302包裹第一隔离坝410和第二隔离坝420。第二封装层可以采用有机材料，设置在显示区域100和电路区301。第三封装层可以采用无机材料，覆盖显示区域100和电路区301的第二封装层，以及覆盖隔离坝区302的第一封装层。即显示区域100和电路区301的封装层26采用无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间，隔离坝区302的封装层26采用无机材料/无机材料的叠层结构。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。
在一种示例性实施例中，第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕 合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。透明导电薄膜可以包括氧化铟锡(ITO)或氧化铟锌(IZO)。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
本公开示例性实施例通过第一源漏金属层形成电源线310的第一电源部310A，通过第二源漏金属层形成电源线310的第二电源部310B，以在边缘区域300形成了双层的电源线310，实现了并联结构的双层电源走线，减小了边缘区域300电源走线的电阻，最大限度地减小了电压信号的压降，提高了显示区域100显示亮度均一性，提高了显示品质。
在一种示例性实施例中，第一电源部310A与第三驱动电路203之间的距离大于或者等于1微米，且小于或者等于6微米，示例性地，第一电源部310A与第三驱动电路203之间的距离可以为4微米，本公开对此不作任何限定。
在一种示例性实施例中，第一电源部310A与裂纹检测线320之间的距离大于或者等于1微米，且小于或者等于6微米，示例性地，第一电源部310A与裂纹检测线320之间的距离可以为4微米，本公开对此不作任何限定。
本公开中，第一电源部310A与第三驱动电路203之间的距离设置与第一电源部310A与裂纹检测线320之间的距离设置使得第一电源部310A在保证显示基板曝光、刻蚀等工艺的和信号干扰要求的情况下的宽度足够大，降低了电源线的压降，可以提升显示基板的显示均一性，并降低显示基板的功耗。
本公开中，第一电源部310A与第三驱动电路203之间的距离和第一电源部310A与裂纹检测线320之间的距离可以相等，或者可以不相等，本公开对此不作任何限定。
本公开中，第二电源部310B在基底10上的正投影覆盖第一电源部310A 和第三驱动电路203在基底10上的正投影。本公开中第二电源部310B的设置方式使得第二电源部310B沿第一方向的长度足够大，降低了电源线的压降，可以提升显示基板的显示均一性，并降低显示基板的功耗。
本公开中，第二电源部310B靠近显示区域100的一端与显示区域100之间的距离大于第二驱动电路202中的时钟信号线CLK与显示区域100之间的距离，降低第二驱动电路202中的时钟信号线CLK的负载，保证显示区域100中的显示单元的正常显示。
本公开中，第一保护层431包裹第一电源部310A远离显示区域100的一端，第二保护层432包裹第二电源部310B远离显示区域100的一端，可以防止腐蚀的发生，防止暗点。
本公开中，第二平坦层16覆盖位于第二过孔边缘的第二电源部，可以防止腐蚀的发生，防止暗点。
本公开中，由于第二电源部310B以及第二平坦层的设置方式，可以使得第一隔离坝410靠近显示区域100的一端与第二电源部310B靠近显示区域的一端之间的距离较大，可以提升显示基板的封装可靠性。
本公开中，辅助电源线330覆盖第一驱动电路201、第二驱动电路202和第三驱动电路203，可以减小电源线的压降，还可以屏蔽外界环境或者信号对于第一驱动电路201、第二驱动电路202和第三驱动电路203的干扰。
本公开示例性实施例通过在第二电源部310B和辅助电源线330上分别设置第二过孔和第五过孔，形成放气通道，可以在工艺过程中有效排放平坦层产生的气体，避免造成膜层剥离，提高工艺质量。本公开示例性实施例显示基板的制备过程具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开显示基板的结构及其制备过程仅仅是一种示例性说明。在一种示例性实施例中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
本公开实施例还提供了一种显示基板的制备方法，设置为制成显示基板，显示基板包括：显示区域和边缘区域，本公开实施例提供的显示基板的制备 方法可以包括以下步骤：
步骤S1、提供一基底。
步骤S2、在基底上依次形成第一电源部和第二电源部，以形成位于边缘区域的电源线。
在一种示例性实施例中，第二电源部在基底上的正投影与第一电源部在基底上的正投影至少部分重叠，且第二电源部远离显示区域的一端与显示区域之间的距离大于或者等于第一电源部远离显示区域的一端与显示区域之间的距离。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，步骤S2可以包括以下步骤：
在基底上形成显示区域的像素驱动电路、位于电路区的第一驱动电路、第二驱动电路、位于第三电路区的第三驱动电路以及位于隔离坝区的第一电源部和裂纹检测线；
在形成第一电源部的基底上形成位于显示区域和电路区的第一平坦层和位于隔离坝区的第一坝基和第一保护层；
在形成第一平坦层的基底上形成位于显示区域的连接电极和位于电路区和隔离坝区的第二电源部；
在形成第二电源部的基底上形成位于显示区域和电路区的第二平坦层、位于隔离坝区的第二坝基、第三坝基和第二保护层；
在形成第二平坦层的基底上形成位于显示区域的阳极和位于边缘区域的辅助电源线；
在形成辅助电源线的基底上形成位于显示区域的像素定义层、位于电路区的隔离层以及位于隔离坝区的第四坝基和第五坝基；
在形成像素定义层的基底上形成位于显示区域的有机发光层、位于显示区域和电路区的阴极和位于隔离坝区中的第六坝基和第七坝基。
本公开实施例还提供了一种显示装置，包括显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种显示基板，包括：显示区域和位于所述显示区域侧面的边缘区域，所述显示基板包括：基底以及设置在所述基底上，且位于所述边缘区域的电源线，所述电源线包括：相互连接的第一电源部和第二电源部，所述第二电源部位于所述第一电源部远离所述基底的一侧；
    所述显示区域包括：多个显示单元，至少一个显示单元包括：像素驱动电路和发光器件，所述像素驱动电路与所述发光器件的阳极电连接，所述电源线与发光器件的阴极电连接，
    所述第二电源部在基底上的正投影与所述第一电源部在基底上的正投影至少部分重叠，且所述第二电源部远离所述显示区域的一端与显示区域之间的距离大于或者等于所述第一电源部远离所述显示区域的一端与显示区域之间的距离。
  2. 根据权利要求1所述的显示基板，其中，所述边缘区域包括：沿着远离所述显示区域的方向依次设置的电路区和隔离坝区，所述电路区包括：沿着远离所述显示区域的方向依次设置的第一电路区、第二电路区和第三电路区；
    所述像素驱动电路包括：写入晶体管、补偿晶体管、发光晶体管，第一扫描信号线、第二扫描信号线和发光信号线；第一扫描信号线与写入晶体管的控制极电连接，第二扫描信号线与补偿晶体管的控制极电连接，发光信号线与发光晶体管的控制极电连接；所述写入晶体管和所述补偿晶体管的晶体管类型不同；
    所述显示基板还包括：位于所述第一电路区的第一驱动电路，位于所述第二电路区的第二驱动电路和位于所述第三电路区和所述隔离坝区的第三驱动电路；
    所述第一驱动电路与所述第一扫描信号线电连接，所述第二驱动电路与所述第二扫描信号线电连接，所述第三驱动电路与所述发光信号线电连接；
    所述第一电源部位于所述隔离坝区，所述第二电源部位于所述隔离坝区和所述电路区；
    所述第二电源部在基底上的正投影与所述第三驱动电路在基底上的正投影至少部分重叠，且与所述第二驱动电路在基底上的正投影不存在重叠区域。
  3. 根据权利要求2所述的显示基板，还包括：位于所述隔离坝区的裂纹检测线，所述裂纹检测线与所述第一电源部同层设置，且位于所述第一电源部远离所述显示区域的一侧；
    所述第一电源部与所述裂纹检测线之间的距离大于或者等于1微米，且小于或者等于6微米。
  4. 根据权利要求2所述的显示基板，其中，所述第一电源部与第三驱动电路之间的距离大于或者等于1微米，且小于或者等于6微米。
  5. 根据权利要求3所述的显示基板，还包括：位于所述显示区域、所述电路区和所述隔离坝区的第一平坦层和位于所述隔离坝区的第一保护层；所述第一平坦层位于所述第一电源部和所述第二电源部之间，且与所述第一保护层同层设置；
    所述第一保护层在基底上的正投影覆盖所述裂纹检测线在基底上的正投影，且与所述第一电源部在基底上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示基板，其中，所述第三驱动电路包括：位于所述隔离坝区的时钟信号线；所述时钟信号线与所述第一电源部同层设置，且位于所述第一电源部靠近所述显示区域的一侧；
    所述第一平坦层在基底上的正投影覆盖所述时钟信号线在基底上的正投影，且与所述第一电源部在基底上的正投影不存在重叠区域。
  7. 根据权利要求5所述的显示基板，其中，所述第二电源部开设有暴露出所述第一平坦层的多个第二过孔，所述多个第二过孔呈矩阵式排布；
    多个第二过孔在基底上的正投影与所述第三驱动电路在基底上的正投影至少部分重叠。
  8. 根据权利要求7所述的显示基板，还包括：位于所述显示区域和所述电路区的第二平坦层和位于所述隔离坝区的第二保护层；
    所述第二平坦层位于所述第二电源部远离所述基底的一侧，且与所述第 二保护层同层设置；
    所述第二保护层在基底上的正投影覆盖所述第一保护层在基底上的正投影，所述第二平坦层在基底上的正投影覆盖所述第二过孔基底上的正投影。
  9. 根据权利要求8所述的显示基板，还包括：位于边缘区域的辅助电源线；所述阳极位于所述第二平坦层远离基底的一侧，且与所述辅助电源线同层设置；
    所述辅助电源线与所述第二电源部电连接；
    所述辅助电源线在基底上的正投影与所述第一驱动电路、所述第二驱动电路和所述第三驱动电路在基底上的正投影至少部分重叠。
  10. 根据权利要求9所述的显示基板，其中，所述辅助电源线开设有暴露出第二平坦层的多个第五过孔，所述多个第五过孔呈矩阵式排布；
    所述多个第五过孔位于所述第一电路区、所述第二电路区和所述第三电路区；
    位于所述第三电路区的第五过孔在基底上的正投影与第二过孔在基底上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示基板，还包括：位于显示区域的像素定义层和位于所述电路区的隔离层；所述像素定义层位于所述阳极远离所述基底的一侧，且与所述隔离层同层设置；
    所述隔离层远离显示区域的一端与显示区域之间的距离小于或者等于所述第二平坦层远离显示区域的一端与显示区域之间的距离，且所述隔离层在基底上的正投影覆盖所述第五过孔在基底上的正投影。
  12. 根据权利要求11所述的显示基板，还包括：依次叠设在所述基底上，且位于所述显示区域的有机发光层和位于所述显示区域和所述电路区的阴极；
    所述阴极与所述辅助电源线电连接。
  13. 根据权利要求12所述的显示基板，其中，所述隔离坝区还包括：第一隔离坝和第二隔离坝；
    所述第二隔离坝位于所述第一隔离坝远离所述显示区域的一侧，且位于所述第二保护层靠近所述显示区域的一侧。
  14. 根据权利要求13所述的显示基板，还包括：位于所述隔离坝区的第一坝基、第三坝基、第五坝基和第七坝基；
    所述第一坝基与所述第一平坦层同层设置，所述第三坝基与所述第二平坦层同层设置，所述第五坝基与所述像素定义层同层设置，所述第七坝基位于所述像素定义层远离所述基底的一侧；
    所述第二电源部覆盖在所述第一坝基上，所述第三坝基设置在覆盖所述第一坝基的第二电源部上，且所述第三坝基在基底上的正投影覆盖所述第一坝基在基底上的正投影，所述第五坝基设置在第三坝基上，且所述第五坝基在基底上的正投影覆盖第三坝基在基底上的正投影，所述第七坝基设置在第五坝基上，且第五坝基在基底上的正投影覆盖第七坝基在基底上的正投影；
    所述辅助电源线部分覆盖所述第三坝基；
    所述第一坝基、覆盖所述第一坝基的所述第二电源部、所述第三坝基、所述第五坝基和所述第七坝基形成第二隔离坝。
  15. 根据要求14所述的显示基板，还包括：位于所述隔离坝区的第二坝基、第四坝基和第六坝基；
    所述第二坝基与所述第二平坦层同层设置，所述第四坝基与所述像素定义层同层设置，所述第六坝基与所述第七坝基同层设置；
    所述第二坝基设置在所述第二电源部上，所述第四坝基设置在覆盖所述第二坝基的所述辅助电源线上，且所述第四坝基在基底上的正投影覆盖所述第二坝基在基底上的正投影，所述第六坝基设置在所述第四坝基上，且所述第四坝基在基底上的正投影覆盖所述第六坝基在基底上的正投影；
    所述第二坝基、覆盖所述第二坝基的所述辅助电源线、所述第四坝基和所述第六坝基形成第一隔离坝。
  16. 根据权利要求13或15所述的显示基板，其中，所述第一隔离坝在基底上的正投影与所述时钟信号线至少部分重叠。
  17. 一种显示装置，包括：如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，设置为制成如权利要求1至16任一项所述的显示基板，所述显示基板包括：显示区域和位于显示区域侧面的边缘区域，所述方法包括：
    提供一基底；
    在所述基底上依次形成第一电源部和第二电源部，以形成位于所述边缘区域的电源线，所述第二电源部在基底上的正投影与所述第一电源部在基底上的正投影至少部分重叠，且所述第二电源部远离所述显示区域的一端与显示区域之间的距离大于或者等于所述第一电源部远离所述显示区域的一端与显示区域之间的距离。
  19. 根据权利要求18所述的方法，其中，所述在所述基底上依次形成第一电源部和第二电源部包括：
    在基底上形成显示区域的像素驱动电路、位于电路区的第一驱动电路、第二驱动电路、位于第三电路区的第三驱动电路以及位于隔离坝区的第一电源部和裂纹检测线；
    在形成第一电源部的基底上形成位于显示区域和电路区的第一平坦层和位于隔离坝区的第一坝基和第一保护层；
    在形成第一平坦层的基底上形成位于显示区域的连接电极和位于电路区和隔离坝区的第二电源部；
    在形成第二电源部的基底上形成位于显示区域和电路区的第二平坦层、位于隔离坝区的第二坝基、第三坝基和第二保护层；
    在形成第二平坦层的基底上形成位于显示区域的阳极和位于边缘区域的辅助电源线；
    在形成辅助电源线的基底上形成位于显示区域的像素定义层、位于电路区的隔离层以及位于隔离坝区的第四坝基和第五坝基；
    在形成像素定义层的基底上形成位于显示区域的有机发光层、位于显示区域和电路区的阴极和位于隔离坝区中的第六坝基和第七坝基。
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