WO2022222084A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022222084A1
WO2022222084A1 PCT/CN2021/088803 CN2021088803W WO2022222084A1 WO 2022222084 A1 WO2022222084 A1 WO 2022222084A1 CN 2021088803 W CN2021088803 W CN 2021088803W WO 2022222084 A1 WO2022222084 A1 WO 2022222084A1
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Prior art keywords
layer
auxiliary electrode
substrate
electrode
anode
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PCT/CN2021/088803
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English (en)
French (fr)
Inventor
王庆贺
周斌
苏同上
张大成
汪军
刘宁
黄勇潮
成军
闫梁臣
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000858.6A priority Critical patent/CN115606333A/zh
Priority to PCT/CN2021/088803 priority patent/WO2022222084A1/zh
Priority to US17/637,817 priority patent/US20240122032A1/en
Publication of WO2022222084A1 publication Critical patent/WO2022222084A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80517—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • An embodiment of the present disclosure provides a display substrate, which includes a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light emitting structure layer including sequentially disposed along a direction away from the substrate
  • the anode, the pixel definition layer, the organic light-emitting layer and the cathode, and the auxiliary electrode and the organic light-emitting block are arranged in sequence along the direction away from the substrate
  • the pixel definition layer includes an anode opening and an electrode opening, and the anode opening exposes the anode , the electrode opening exposes the auxiliary electrode, the organic light-emitting block is separated from the organic light-emitting layer
  • the auxiliary electrode comprises a first auxiliary electrode, a second auxiliary electrode located on the side of the first auxiliary electrode away from the substrate an electrode and a third auxiliary electrode on the side of the second auxiliary electrode away from the substrate;
  • the cathode includes a first horizontal overlapping portion and a second sidewall overlapping portion, the first horizontal overlapping portion overlaps with the first auxiliary electrode, and the second sidewall overlapping portion overlaps with the second auxiliary electrode
  • the thickness of the second side wall overlapping portion in the direction parallel to the base is greater than the thickness of the first horizontal overlapping portion in the direction perpendicular to the base.
  • the second sidewall overlapping portion is connected to the first auxiliary electrode, the second sidewall overlapping portion is in contact with a surface of the third auxiliary electrode close to the substrate, and the first auxiliary electrode is in contact with the surface of the third auxiliary electrode.
  • the overlapping parts of the two side walls are connected with the first horizontal overlapping part.
  • the organic light-emitting layer is disposed on a side of the first auxiliary electrode away from the substrate, the organic light-emitting layer is separated from the second auxiliary electrode, and the cathode further includes a first auxiliary electrode.
  • the sidewall overlap portion, the first sidewall overlap portion overlaps with the side surface of the organic light-emitting layer, and the cathode is also overlapped with the side of the organic light-emitting layer away from the substrate.
  • the cathode further includes a second horizontal overlapping portion and a third overlapping portion, the second horizontal overlapping portion and the third auxiliary electrode protruding portion of the second auxiliary electrode adjacent to the second auxiliary electrode
  • the surface of the substrate side is overlapped
  • the third overlap portion is overlapped with the surface and side surface of the organic light-emitting block on the side away from the substrate and the side surface of the third auxiliary electrode
  • the second horizontal overlap portion is overlapped with the side surface of the third auxiliary electrode.
  • the third lap joint is connected.
  • the thickness of the third overlap portion in a direction perpendicular to the base is greater than the thickness of the second sidewall overlap portion in a direction parallel to the base, and the first sidewall overlap portion is parallel to the base.
  • the thickness in the direction of the base is greater than the thickness of the first horizontal overlapping portion in the direction perpendicular to the base.
  • the thickness of the second sidewall overlapping portion in the direction parallel to the substrate is 500 angstroms to 3000 angstroms, and the thickness of the first horizontal overlapping portion in the direction perpendicular to the substrate is 100 Angstroms to 1500 Angstroms.
  • the second auxiliary electrode includes a bottom surface close to the substrate and a top surface remote from the substrate, and a side surface between the top surface and the bottom surface, in a plane perpendicular to the substrate, the side surface of the second auxiliary electrode
  • the angle formed with the bottom surface of the second auxiliary electrode is less than 90°.
  • the anode includes a first anode layer, a second anode layer disposed on a side of the first anode layer away from the substrate, and a second anode layer disposed on a side of the second anode layer away from the substrate
  • the third anode layer, the orthographic projection of the second anode layer on the substrate is within the range of the orthographic projection of the first anode layer on the substrate, and the orthographic projection of the second anode layer on the substrate is located in the within the range of the orthographic projection of the third anode layer on the substrate.
  • the first anode layer and the first auxiliary electrode are arranged in the same layer and have the same material; the second anode layer and the second auxiliary electrode are arranged in the same layer and have the same material; The third anode layer and the third auxiliary electrode are arranged in the same layer and have the same material.
  • the first anode layer has a first end and a second end in the second direction
  • the second anode layer has a third end and a fourth end
  • the first The dimension of the end portion in the first direction is smaller than the dimension of the second end portion in the first direction
  • the dimension of the third end portion in the first direction is smaller than the dimension of the fourth end portion in the The dimension in the first direction
  • the auxiliary electrode is disposed between the first end portion and the third end portion, and the first direction intersects the second direction.
  • the first anode layer has a portion closer to the second pixel unit than the first end in the first direction; the second anode layer is in the first direction Having a portion closer to the first pixel unit than the third end portion, the first pixel unit and the second pixel unit are adjacent.
  • the driving circuit layer includes: a transistor and a power supply electrode disposed on a substrate, a passivation layer disposed on a side of the transistor and the power supply electrode away from the substrate, and a passivation layer disposed far away from the substrate
  • a flat layer on one side of the substrate, the flat layer has anode vias and electrode vias, the power supply electrode and the drain electrode in the transistor are arranged in the same layer
  • the passivation layer has first vias and a second via hole, the first via hole exposes the drain electrode of the transistor, the second via hole exposes the power supply electrode;
  • the anode via hole exposes the first via hole, the electrode A via hole exposes the second via hole.
  • the first auxiliary electrode is connected to the power supply electrode through the electrode via hole and the second via hole, the second auxiliary electrode is in direct contact with the first auxiliary electrode, and the first auxiliary electrode is in direct contact with the first auxiliary electrode.
  • the orthographic projection of the second auxiliary electrode on the substrate is within the range of the orthographic projection of the third auxiliary electrode on the substrate, and the orthographic projection of the second auxiliary electrode on the substrate is located in the orthographic projection of the first auxiliary electrode on the substrate within the projection range.
  • the orthographic projection of the second via hole on the substrate is located within the orthographic projection range of the electrode via hole on the substrate, and the orthographic projection of the second via hole on the substrate is located in the first
  • the three auxiliary electrodes are in the orthographic projection range on the substrate.
  • the orthographic projection of the electrode opening on the substrate is within the range of the orthographic projection of the first auxiliary electrode on the substrate.
  • a plurality of the anodes are arranged in a row along the first direction, the anode via holes corresponding to the anodes in the same row are arranged on the same straight line extending along the first direction, and at least one electrode is connected to the electrode corresponding to the electrode The vias overlap the anode vias in a second direction that intersects the first direction.
  • Embodiments of the present disclosure also provide a display device, including the display substrate described in any preceding item.
  • Embodiments of the present disclosure also provide a method for preparing a display substrate, including:
  • a light-emitting structure layer is formed on the driving circuit layer, and the light-emitting structure layer includes an anode, a pixel definition layer, an organic light-emitting layer and a cathode arranged in sequence along a direction away from the substrate, and an auxiliary electrode and an auxiliary electrode arranged in sequence along the direction away from the substrate.
  • the pixel definition layer includes an anode opening and an electrode opening, the anode opening exposes the anode, the electrode opening exposes the auxiliary electrode, the organic light-emitting block is separated from the organic light-emitting layer,
  • the auxiliary electrode includes a first auxiliary electrode, a second auxiliary electrode located on the side of the first auxiliary electrode away from the substrate, and a third auxiliary electrode located at the side of the second auxiliary electrode away from the substrate;
  • the cathode includes a first auxiliary electrode The horizontal overlap part and the second side wall overlap part, the first horizontal overlap part overlaps with the first auxiliary electrode, the second side wall overlap part overlaps with the second auxiliary electrode, the second The thickness of the sidewall overlapping portion in the direction parallel to the base is greater than the thickness of the first horizontal overlapping portion in the direction perpendicular to the base.
  • 1 is a schematic structural diagram of a display substrate
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • 5a is a schematic structural diagram of a display substrate according to an embodiment of the disclosure.
  • Fig. 5b is the enlarged structural schematic diagram of A region in Fig. 5a;
  • FIG. 6a is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the disclosure.
  • Figure 6b is a cross-sectional view taken along the A-A direction in Figure 6a;
  • FIG. 7a is a schematic diagram after forming a semiconductor layer pattern according to an embodiment of the present disclosure.
  • Figure 7b is a cross-sectional view taken along the A-A direction in Figure 7a;
  • FIG. 8a is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the disclosure.
  • Figure 8b is a cross-sectional view taken along the A-A direction in Figure 8a;
  • FIG. 9a is a schematic diagram after forming a third insulating layer pattern according to an embodiment of the present disclosure.
  • Figure 9b is a cross-sectional view taken along the A-A direction in Figure 9a;
  • FIG. 10a is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the disclosure.
  • Figure 10b is a cross-sectional view taken along the A-A direction in Figure 10a;
  • FIG. 11a is a schematic diagram after forming a first flat layer pattern according to an embodiment of the present disclosure.
  • Figure 11b is a cross-sectional view taken along the A-A direction in Figure 11a;
  • FIG. 12a is a schematic diagram after forming a first transparent conductive layer pattern according to an embodiment of the disclosure
  • Figure 12b is a cross-sectional view taken along the A-A direction in Figure 12a;
  • FIG. 13 is a schematic diagram of an embodiment of the disclosure after forming anode and auxiliary electrode patterns
  • FIG. 14 is a schematic cross-sectional view of an auxiliary electrode according to an embodiment of the present invention.
  • 15a and 15b are schematic diagrams after forming a pixel definition layer pattern according to an embodiment of the present disclosure.
  • Figure 15c is a cross-sectional view taken along the line A-A in Figures 15a and 15b;
  • FIG. 16 is a schematic diagram of forming an organic light-emitting layer pattern according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram after forming a cathode pattern according to an embodiment of the disclosure.
  • FIG. 18 is another schematic diagram of forming an anode and an auxiliary electrode pattern according to an embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array
  • the pixel array may include a plurality of scan lines (S1 to Sm), a plurality of data lines (D1 to Dn), and a plurality of sub-pixels pixel Pxij.
  • the timing controller may supply grayscale values and control signals suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver driver.
  • the data driver may generate data voltages to be supplied to the data lines D1, D2, D3, ...
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of sub-pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals with on-level pulses to the scan lines S1 to Sm.
  • the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
  • the sub-pixel array may include a plurality of pixel sub-PXij. Each pixel sub-PXij may be connected to a corresponding data line and a corresponding scan line, and i and j may be natural numbers.
  • the sub-pixel PXij may refer to a sub-pixel in which the transistor is connected to the i-th scan line and to the j-th data line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 that emits light of a first color, a second light-emitting unit P1 that emits light of a first color, and a The second light-emitting unit P2 for color light and the third light-emitting unit P3 for emitting light of the third color, the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 all include pixel driving circuits and light-emitting devices.
  • the pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 are respectively connected with the scan lines, the data lines and the light-emitting signal lines, and the pixel driving circuits are configured to control the scan lines and the light-emitting signal lines.
  • the data voltage transmitted by the data line is received, and a corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of the light-emitting unit, and the light-emitting devices are configured to respond to the current output by the pixel driving circuit of the light-emitting unit. Brightness of light.
  • the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit and white light-emitting units, which are not limited in the present disclosure.
  • the shape of the light emitting unit in the pixel unit may be a rectangle shape, a diamond shape, a pentagon shape or a hexagon shape.
  • the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally, vertically, or in a square pattern.
  • the pixel unit includes four light-emitting units, the four light-emitting units can be horizontally, vertically, or square. (Square) arrangement, which is not limited in the present disclosure.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 10, a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10, and a light emitting structure layer 103 disposed on the light emitting
  • the structure layer 103 is away from the encapsulation layer 104 on the side of the substrate 10 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • substrate 10 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit.
  • each sub-pixel includes one transistor 101 and one storage capacitor 101A as an example for illustration.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the transistor 101 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4 , the pixel driving circuit has a 3T1C structure, which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
  • 3T1C structure which may include 3 switching transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C ST and 6 signal lines (data lines Dn, the first scan line Gn, the second scan line Sn, the compensation line Se, the first power supply line VDD and the second power supply line VSS).
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is coupled to the first scan line Gn
  • the first electrode of the first transistor T1 is coupled to the data line Dn
  • the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2
  • the first transistor T1 is used for receiving the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, and the second electrode of the second transistor T2 is coupled to the second electrode of the OLED One pole, the second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is coupled to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2.
  • the three transistors T3 are used to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.
  • the first pole of the OLED is coupled to the second pole of the second transistor T2, the second pole of the OLED is coupled to the second power line VSS, and the OLED is used for responding to the current of the second pole of the second transistor T2 to emit corresponding brightness.
  • the first pole of the storage capacitor C ST is coupled to the gate electrode of the second transistor T2, the second pole of the storage capacitor C ST is coupled to the second pole of the second transistor T2, and the storage capacitor C ST is used to store the second transistor T2 the gate electrode potential.
  • the signal of the first power supply line VDD is a high-level signal continuously provided
  • the signal of the second power supply line VSS is a low-level signal.
  • the first to third transistors T1 to T3 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • OLED display substrates can be divided into three types: bottom emission OLED, top emission OLED and double-sided emission OLED.
  • Bottom-emitting OLEDs emit light from the bottom of the substrate
  • top-emitting OLEDs emit light from the top of the substrate
  • double-sided emitting OLEDs emit light from the bottom of the substrate and the top of the substrate at the same time.
  • top-emitting OLEDs have the advantages of large aperture ratio, high color purity, and easy realization of high resolution (Pixels per inch, PPI), and have received extensive attention.
  • the cathode is required to have better light transmittance and conductivity, but it is difficult to meet the light transmittance and conductivity requirements at the same time.
  • the thickness of the cathode must be larger, but the transmittance of the cathode is low at this time, and the problem of viewing angle deviation will occur.
  • the thickness of the cathode must be thinner, but at this time, the impedance of the cathode is relatively large, which will not only cause the problems of voltage rise and power consumption, but also cause uneven voltage distribution on the cathode, and brightness will appear. uneven problem.
  • an auxiliary electrode is used to reduce the impedance of the cathode, thereby reducing the cathode voltage drop.
  • the auxiliary electrode is arranged on the driving circuit layer
  • the cathode is arranged on the light emitting structure layer
  • via holes are formed in the driving circuit layer and the light emitting structure layer by laser process, so that the cathode is connected to the auxiliary electrode through the via hole. Since a large number of particles (Particles) are generated when the via hole is formed on the organic light-emitting layer by the laser process, the structure and process seriously affect the product yield.
  • the structure and process greatly reduce the production efficiency. Since the via hole formed by the laser process is small and the contact area between the cathode and the auxiliary electrode is small, the structure and process cannot effectively reduce the voltage drop of the cathode, which affects the display effect.
  • FIG. 5a is a schematic structural diagram of a display substrate according to an exemplary embodiment of the disclosure, illustrating a cross-sectional structure of a sub-pixel in the display substrate
  • FIG. 5b is an enlarged schematic structural diagram of area A in FIG. 5a.
  • the display substrate in an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 10 and a driving circuit layer 102 disposed on a side away from the substrate the light emitting structure layer 103.
  • the driving circuit layer 102 may include the second power supply line 44 and transistors and storage capacitors constituting the pixel driving circuit
  • the light emitting structure layer 103 may include the anode 50, the auxiliary electrode 60, the pixel definition layer 71, the organic light emitting layer 72 and the cathode 80, the organic light emitting Layer 72 is connected to anode 50 and cathode 80 , respectively
  • auxiliary electrode 60 is connected to second power supply line 44
  • cathode 80 is connected to auxiliary electrode 60 .
  • the auxiliary electrode 60 includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface disposed between the bottom surface and the top surface.
  • the cathode 80 is in contact with the side surface of the auxiliary electrode 60 .
  • the auxiliary electrode 60 may include a first auxiliary electrode 61, a second auxiliary electrode 62 disposed on the side of the first auxiliary electrode 61 away from the substrate, and a second auxiliary electrode 62 disposed on the side of the first auxiliary electrode 61 away from the substrate.
  • the electrode 62 is far from the third auxiliary electrode 63 on the side of the substrate.
  • the stacked first auxiliary electrode 61, the second auxiliary electrode 62 and the third auxiliary electrode 63 form an "I"-shaped structure.
  • the projections are all within the range of the orthographic projections of the first auxiliary electrode 61 and the third auxiliary electrode 63 on the substrate.
  • the light emitting structure layer 102 may include an organic light emitting block 73, and the organic light emitting block 73 and the organic light emitting layer 72 are provided in the same layer, have the same material, and are simultaneously formed by the same evaporation process.
  • the organic light-emitting blocks 73 are disposed on the side of the auxiliary electrode 60 away from the substrate, and the organic light-emitting blocks 73 are disposed apart from the organic light-emitting layer 72 .
  • the organic light-emitting block 73 is disposed on the side of the third auxiliary electrode 63 away from the substrate, and the orthographic projection of the organic light-emitting block 73 on the substrate is within the range of the orthographic projection of the third auxiliary electrode 63 on the substrate .
  • the anode 50 in a plane perpendicular to the display substrate, may include a first anode 51, a second anode 52 disposed on a side of the first anode 51 away from the substrate, and a second anode 52 disposed on a side away from the substrate
  • the third anode 53 on the side, the stacked first anode 51, the second anode 52 and the third anode 53 form an "I" shape, and the orthographic projections of the second anode 52 on the substrate are all located at the first anode 51 and the third anode 53 is within the range of the orthographic projection on the substrate.
  • the first auxiliary electrode 61 and the first anode 51 are provided in the same layer, have the same material, and are simultaneously formed through the same patterning process.
  • the second auxiliary electrode 62 and the second anode 52 are provided in the same layer, made of the same material, and formed simultaneously by the same patterning process.
  • the third auxiliary electrode 63 and the third anode 53 are provided in the same layer, made of the same material, and formed simultaneously by the same patterning process.
  • the driving circuit layer 102 may include a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, The second insulating layer 92 on the semiconductor layer, the second conductive layer provided on the second insulating layer 92, the third insulating layer 93 covering the second conductive layer, the third conductive layer provided on the third insulating layer 93, The fourth insulating layer 94 covering the third conductive layer, and the flat layer 95 provided on the fourth insulating layer 94 .
  • the first conductive layer at least includes a shielding layer
  • the semiconductor layer at least includes a first capacitor plate and active layers of a plurality of transistors
  • the second conductive layer at least includes gate electrodes of a plurality of transistors
  • the third conductive layer at least includes a second power supply line , the second capacitor plate and the first and second poles of a plurality of transistors, the second capacitor plate is connected to the shielding layer through the via hole, the second capacitor plate and the first capacitor plate form a first storage capacitor, and the shield The layer and the first capacitor plate form a second storage capacitor.
  • the fourth insulating layer 94 and the flat layer 95 are provided with an anode via hole and an electrode via hole, the anode is connected to the second capacitor plate through the anode via hole, and the auxiliary electrode is connected to the second power line through the electrode via hole.
  • the pixel definition layer 71 in the light emitting structure layer 103 is provided with a first pixel opening and a second pixel opening, the first pixel opening exposes a part of the surface of the third anode 53, and the second pixel opening exposes the first pixel opening.
  • Two auxiliary electrodes 62 and a third auxiliary electrode 63 are provided.
  • the cathode 80 in the light emitting structure layer 103 realizes the large-area contact connection between the cathode 80 and the auxiliary electrode 60 by wrapping the organic light emitting block 73 and the auxiliary electrode 60 .
  • the exposed surface of the organic light-emitting block 73 includes: The upper surface on the side away from the substrate and the side surface on the side, the exposed surfaces of the third auxiliary electrode 63 include: the third side surface on the side and the third side surface protruding from the second auxiliary electrode 62 on the side adjacent to the substrate.
  • the lower surface, the exposed surface of the second auxiliary electrode 62 includes: a second side surface located at the side portion.
  • a side surface refers to a plurality of circumferential surfaces whose normal direction is parallel or nearly parallel to the plane of the substrate.
  • the cathode 80 wrapping the organic light-emitting block 73 and the auxiliary electrode 60 means that the cathode 80 covers or partially covers the upper surface and all side surfaces of the organic light-emitting block 73 , and the cathode 80 covers or partially covers all the third side surfaces of the third auxiliary electrode 63 . And the third lower surface, the cathode 80 completely covers or partially covers all of the second side surface of the second auxiliary electrode 62 .
  • the cathode 80 includes a first horizontal overlap portion 242 and a second sidewall overlap portion 243 , the first horizontal overlap portion 242 overlaps with the first auxiliary electrode 61 , and the first horizontal overlap portion 242 overlaps with the first auxiliary electrode 61 .
  • the two sidewall overlap portions 243 overlap with the second auxiliary electrode 62 , and the thickness a of the second sidewall overlap portion 243 in the first direction is greater than the thickness b of the first horizontal overlap portion 242 in the second direction.
  • the first direction may be a direction parallel to the substrate, and the second direction may be a direction perpendicular to the substrate.
  • the embodiment of the present disclosure can enhance the "I"-shaped supporting force of the auxiliary electrode, and can increase the distance between the second sidewall overlapping portion 243 and the third lower surface of the lower side of the third auxiliary electrode 63 and the second side
  • the effective contact area between the wall overlap portion 243 and the first auxiliary electrode 61 located on the bottom surface of the electrode via K2 enables the second sidewall overlap portion 243 to have a more stable support capability and improves the stability of the support overlap , thereby improving the reliability of the auxiliary cathode.
  • the cathode 80 further includes a first sidewall overlapping portion 241 , and the thickness c of the first sidewall overlapping portion 241 in the first direction is greater than that of the first horizontal overlapping portion 242 Thickness b in the second direction.
  • the thickness a of the second sidewall lap portion 243 in the first direction is 500 angstroms (A) to 3000 angstroms.
  • the thicker the lap thickness the smaller the resistance itself, thereby reducing the resistance of the entire auxiliary electrode and improving the electrical performance.
  • the thickness a of the second sidewall overlapping portion 243 in the first direction may be 700 angstroms.
  • the thickness b of the first horizontal overlapping portion 242 is 100 angstroms to 1500 angstroms. Therefore, the resistance value of the first horizontal lap joint 242 can be made smaller and the electrical performance is better, and the thicker the first horizontal lap joint 242 is, the stronger the lap joint strength is, and the lap joint effect is less likely to fail, which is beneficial to This assists in improving the reliability of the cathode; in addition, the thicker the thickness of the first horizontal overlapping portion 242 is, the better the overlapping effect with the first sidewall overlapping portion 241 is.
  • the thickness b of the first horizontal overlapping portion 242 may be 300 angstroms.
  • the first horizontal overlapping portion 242 overlaps with the first auxiliary electrode 61 located at the bottom surface of the electrode via hole K2 , so that the first auxiliary electrode 61 is connected to the second auxiliary electrode 61 .
  • the auxiliary electrodes 62 are all overlapped with the cathode 24, which on the one hand makes the bonding performance of the first auxiliary electrode 61 and the second auxiliary electrode 62 better, and on the other hand reduces the resistance of the whole auxiliary electrode.
  • the cathode 80 further includes a second horizontal overlapping portion 244 and a third overlapping portion 245 , and the second horizontal overlapping portion 244 and the third auxiliary electrode 63 protrude from the second auxiliary electrode 63 .
  • the electrode 62 is partially overlapped with the surface on the side adjacent to the substrate
  • the third overlap portion 245 is overlapped with the surface and side surface of the organic light-emitting block 73 on the side away from the substrate and the side surface of the third auxiliary electrode 63
  • the second horizontal overlap portion 244 is overlapped with the surface.
  • the third overlapping portion 245 is connected.
  • the thickness of the third overlap portion 245 in the direction perpendicular to the base is greater than the thickness of the second sidewall overlap portion 243 in the direction parallel to the base, and the thickness of the first sidewall overlap portion 243 in the direction parallel to the base
  • the thickness of 241 in the direction parallel to the base is greater than the thickness of the first horizontal overlapping portion 242 in the direction perpendicular to the base.
  • the second auxiliary electrode 62 includes a bottom surface close to the substrate and a top surface away from the substrate, and a side surface between the top surface and the bottom surface, in a plane perpendicular to the substrate, the first The angle ⁇ formed by the side surface of the second auxiliary electrode 62 and the bottom surface of the second auxiliary electrode 62 is less than 90°.
  • the shape of the auxiliary electrode 60 may be any of a variety of: triangle, rectangle, trapezoid, polygon, circle, and ellipse.
  • the display substrate on a plane parallel to the display substrate, the display substrate includes a plurality of pixel units, and the auxiliary electrodes may be disposed between anodes of adjacent pixel units.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • the manufacturing process of the display substrate may include the following operations.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the flexible substrate may include a stack of a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and then forming a first flexible (PI1) layer after curing into a film; Subsequently, a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; and then an amorphous silicon film is deposited on the first barrier layer to form a barrier layer covering the first barrier layer.
  • Amorphous silicon (a-si) layer then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; then a layer is deposited on the second flexible layer A barrier film is formed to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the substrate.
  • PI2 polyimide
  • Barrier2 second barrier
  • a first conductive layer pattern is formed.
  • forming the first conductive layer pattern may include: depositing a first metal thin film on the substrate, patterning the first metal thin film through a patterning process, forming the first conductive layer pattern on the substrate, and the first The conductive layer pattern at least includes a shielding layer 11 , a power supply connection line 12 and a compensation connection line 13 , as shown in FIGS. 6 a and 6 b , and FIG. 6 b is a cross-sectional view of FIG. 6 a along A-A.
  • the blocking layer 11 is disposed in each sub-pixel, and may be in the shape of a rectangle provided with protrusions or grooves.
  • the power connection line 12 is arranged in a pixel unit, and extends to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 along the first direction D1 or the opposite direction of the first direction D1, and between adjacent pixel units.
  • the power supply connection lines 12 are arranged at intervals, and the power supply connection lines 12 are configured to connect the subsequently formed first power supply lines to provide a power supply signal for the pixel driving circuit of each sub-pixel of the pixel unit.
  • the compensation connection line 13 is arranged in a pixel unit and extends along the first direction D1 or the opposite direction of the first direction D1 to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3, two adjacent pixels
  • the compensation connection lines 13 of the units are connected to each other to form an integrated structure, and the compensation connection lines 13 are configured to connect the compensation lines formed subsequently to provide compensation signals for the pixel driving circuit of each sub-pixel of the pixel unit.
  • the display substrate includes a first conductive layer disposed on the substrate 10 , and the first conductive layer at least includes a shielding layer 11 .
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, and patterning the semiconductor film through a patterning process to form a pattern covering the first metal layer and the semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern of each sub-pixel may include the first active layer 21 of the first transistor T1 and the second active layer of the second transistor T2 22.
  • the third active layer 23 and the first capacitor plate 24 of the third transistor T3 are shown in FIG. 7 a and FIG. 7 b , and FIG. 7 b is a cross-sectional view taken along A-A in FIG. 7 a .
  • the first active layer 21 , the second active layer 22 and the third active layer 23 in each sub-pixel may all be in the shape of stripes extending along the second direction D2 and arranged at intervals.
  • a capacitor electrode plate 24 may be a rectangle with protrusions or grooves.
  • the first active layer 21 and the first capacitor electrode plate 24 are connected to each other as an integral structure.
  • the orthographic projection of the second active layer 22 on the substrate Within the range of the orthographic projection of the shielding layer 11 on the substrate, the orthographic projection of the first capacitor plate 24 on the substrate is within the range of the orthographic projection of the shielding layer 11 on the substrate.
  • the display substrate includes a first conductive layer disposed on the substrate 10 , a first insulating layer 91 covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer 91 .
  • the first conductive layer at least includes the shielding layer 11
  • the semiconductor layer at least includes the second active layer 22 , the third active layer 23 and the first capacitor plate 24 .
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and applying a patterning process to the second metal film and the second insulating film Patterning is performed to form a second insulating layer and a second conductive layer pattern disposed on the second insulating layer.
  • the second conductive layer pattern at least includes: a first scan line 31, a second scan line 32, a first protection electrode 33,
  • the second protective electrode 34 , the third protective electrode 35 and the second gate electrode 36 are shown in FIGS. 8 a and 8 b , and FIG. 8 b is a cross-sectional view taken along the direction A-A in FIG. 8 a .
  • the second conductive layer may be referred to as a gate metal (GATE) layer.
  • the first scan line 31 and the second scan line 32 extend along the first direction D1.
  • the area where the first scan line 31 overlaps with the first active layer 21 in each sub-pixel serves as the gate electrode of the first transistor T1 of the sub-pixel, and the second scan line 32 overlaps with the third active layer 23 in each sub-pixel.
  • the overlapping area serves as the gate electrode of the third transistor T3 of the sub-pixel where it is located.
  • the areas other than the gate electrodes in the first scan line 31 and the second scan line 32 may be arranged in a double-line structure to improve the reliability of signal transmission.
  • the first protection electrode 33, the second protection electrode 34 and the third protection electrode 35 are all strip-shaped extending along the second direction D2.
  • the first protection electrode 33 may be disposed in each pixel unit, on a side of the first sub-pixel P1 away from the second sub-pixel P2, and the first protection electrode 33 is configured to be connected to a subsequently formed first power supply line.
  • the second protection electrode 34 and the third protection electrode 35 may be arranged between the third sub-pixels P3 of two adjacent pixel units.
  • the second protection electrode 34 and the third protection electrode 35 are arranged in sequence along the first direction D1.
  • the second protection electrode 34 is configured to be connected to the compensation line formed subsequently, and the third protection electrode 35 is configured to be connected to the second power supply line formed subsequently.
  • the second gate electrode 36 is in the shape of a strip extending along the first direction D1 and may be disposed in each sub-pixel, and the orthographic projection of the second gate electrode 36 on the substrate is the same as the second active layer 22 and The first capacitor electrodes 24 all have overlapping regions.
  • the second conductive layer can be used as a shield to conduct conductorization processing on the semiconductor layer, and the semiconductor layer in the region shielded by the second conductive layer forms the first transistors T1 and the second In the channel regions of the transistor T2 and the third transistor T3, the semiconductor layers that are not shielded by the second conductive layer are conductorized, that is, the first capacitor plate 24 and the first and second regions of the three active layers are Conductive.
  • the display substrate includes a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, Two insulating layers 92 and a second conductive layer disposed on the second insulating layer 92 .
  • the first conductive layer includes at least the shielding layer 11
  • the semiconductor layer at least includes the second active layer 22 , the third active layer 23 and the first capacitor plate 24
  • the second conductive layer at least includes the second gate electrode 36 .
  • the patterns of the second insulating layer and the second conductive layer may be substantially the same, and the orthographic projection of the second conductive layer on the substrate is within the range of the orthographic projection of the second insulating layer on the substrate.
  • a third insulating layer pattern is formed.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, and patterning the third insulating film by a patterning process to form a pattern covering the first conductive layer.
  • the third insulating layer, the third insulating layer is provided with a plurality of via holes, and the plurality of via holes at least include: the first via hole V1 to the fourteenth via hole V14, as shown in FIG. 9a and FIG. 9b, and FIG. 9b is a diagram Section 9a, A-A.
  • the first via hole V1 is provided on the power connection line 12 of the first sub-pixel P1
  • the second via hole V2 is provided on the second sub-pixel P2 and the third sub-pixel respectively
  • the third insulating layer and the first insulating layer in the first via hole V1 and the second via hole V2 are etched away, exposing the surface of the power supply connection line 12 .
  • the first via hole V1 is configured to connect the first power supply line formed subsequently to the power supply connection line 12 through the via hole
  • the second via hole V2 is configured to connect the first electrode of the second transistor T2 to be formed subsequently through the via hole.
  • the power connection line 12 is connected.
  • the third via hole V3 is arranged on the compensation connection line 13 between adjacent third sub-pixels P3, the fourth via hole V4 is arranged on the compensation connection line 13 of each sub-pixel, and the third via hole V4 is arranged on the compensation connection line 13 of each sub-pixel.
  • the third insulating layer and the first insulating layer in the hole V3 and the fourth via hole V4 are etched away, exposing the surface of the compensation connection line 13 .
  • the third via hole V3 is configured to connect the compensation line formed later to the compensation connection line 13 through the via hole
  • the fourth via hole V4 is configured to connect the first electrode of the third transistor T3 to the compensation connection line formed later through the via hole. Line 1 is connected.
  • a plurality of fifth via holes V5 are disposed in the region where the first protection electrode 33 is located, and the third insulating layer in the fifth via hole V5 is etched away to expose the surface of the first protection electrode 33 .
  • the fifth via hole V5 is configured so that the first power supply line formed later is connected to the first protection electrode 33 through the via hole, and providing a plurality of fifth via holes V5 can improve the connection reliability.
  • a plurality of sixth via holes V6 are disposed in the region where the second protection electrode 34 is located, and the third insulating layer in the sixth via hole V6 is etched away, exposing the surface of the second protection electrode 34 .
  • the sixth via hole V6 is configured so that the compensation line formed subsequently is connected to the second protection electrode 34 through the via hole, and providing a plurality of sixth via holes V6 can improve the connection reliability.
  • a plurality of seventh via holes V7 are disposed in the region where the third protection electrode 35 is located, and the third insulating layer in the seventh via hole V7 is etched away to expose the surface of the third protection electrode 35 .
  • the seventh via hole V7 is configured so that the second power supply line formed later is connected to the third protection electrode 35 through the via hole, and providing a plurality of seventh via holes V7 can improve the connection reliability.
  • the eighth via hole V8 is disposed in the region where the first region of the first active layer of each sub-pixel is located, and the third insulating layer in the eighth via hole V8 is etched away, exposing the first active layer. the surface of the first region of the source layer.
  • the eighth via hole V8 is configured to connect the subsequently formed data line to the first region of the first active layer through the via hole.
  • the ninth via hole V9 is disposed in the area where the first capacitor plate 24 and the second gate electrode 36 of each sub-pixel are located, the third insulating layer in the ninth via hole V9 is etched away, and the third insulating layer is etched away.
  • the nine via holes V9 expose the surfaces of the first capacitor plate 24 and the second gate electrode 36 at the same time.
  • the ninth via hole V9 is configured so that the second electrode of the first transistor T1 (the gate electrode of the second transistor T2 ) formed later is connected to the first capacitor plate 24 and the second gate electrode 36 through the via hole at the same time.
  • the tenth via hole V10 is disposed in the region where the first region of the second active layer of each sub-pixel is located, and the third insulating layer in the tenth via hole V10 is etched away, exposing the second active layer. the surface of the first region of the source layer.
  • the tenth via hole V10 of the first sub-pixel P1 is configured so that the first power supply line formed subsequently is connected to the first region of the second active layer through the via hole, and the tenth via hole V10 of the second sub-pixel P2 and the third sub-pixel P3
  • the via hole V10 is configured so that the first electrode of the second transistor T2 formed later is connected to the first region of the second active layer through the via hole.
  • the eleventh via hole V11 is disposed in the region where the second region of the second active layer of each sub-pixel is located, and the third insulating layer in the eleventh via hole V11 is etched away, exposing the first 2.
  • the eleventh via hole V11 is configured to connect the second capacitor plate (the second electrode of the second transistor T2 and the second electrode of the third transistor T3 ) formed later to the second region of the second active layer through the via hole .
  • the twelfth via hole V12 is disposed in the region where the first region of the third active layer of each sub-pixel is located, and the third insulating layer in the twelfth via hole V12 is etched away, exposing the first region of the third active layer. The surface of the first region of the three active layers.
  • the twelfth via hole V12 is configured to connect the first electrode of the third transistor T3 formed subsequently to the first region of the third active layer through the via hole.
  • the thirteenth via hole V13 is disposed in the region where the second region of the third active layer of each sub-pixel is located, and the third insulating layer in the thirteenth via hole V13 is etched away, exposing the The surface of the second region of the three active layers.
  • the thirteenth via hole V13 is configured to connect the second capacitor plate (the second electrode of the second transistor T2 and the second electrode of the third transistor T3 ) formed subsequently to the second region of the third active layer through the via hole .
  • the fourteenth via hole V14 is disposed in the region where the shielding layer 11 of each sub-pixel is located, and the third insulating layer and the first insulating layer in the fourteenth via hole V14 are etched away, exposing the shielding layer. surface of layer 11.
  • the fourteenth via hole V14 is configured so that the second capacitor plate (the second electrode of the second transistor T2 and the second electrode of the third transistor T3) formed later is connected to the shielding layer 11 through the via hole.
  • the display substrate includes a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, Two insulating layers 92, a second conductive layer disposed on the second insulating layer 92, and a third insulating layer 93 covering the second conductive layer.
  • the first conductive layer at least includes the shielding layer 11, the semiconductor layer at least includes the second active layer 22, the third active layer 23 and the first capacitor plate 24, the second conductive layer at least includes the second gate electrode 36, and the third insulating layer.
  • a plurality of via holes are provided on the layer 93 , and the plurality of via holes at least include: a tenth via hole V10 , an eleventh via hole V11 , a thirteenth via hole V13 and a fourteenth via hole V14 .
  • a third conductive layer pattern is formed.
  • forming the third conductive layer pattern may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the third insulating layer
  • the third conductive layer on top of the device, the third conductive layer at least includes: a first power line 41, a data line 42, a compensation line 43, a second power line 44, a second capacitor plate 45, a first connection electrode 46, a second connection
  • the electrode 47 and the third connection electrode 48 are shown in Figs. 10a and 10b, and Fig. 10b is a cross-sectional view taken along the line A-A in Fig. 10a.
  • the third conductive layer may be referred to as a source-drain metal (SD) layer.
  • SD source-drain metal
  • the first power supply line 41 is disposed in each pixel unit, on the side of the first sub-pixel P1 away from the second sub-pixel P2, and the first power supply line 41 is located along the first sub-pixel P2. Extending in the two directions D2, the first power line 41 is connected to the power connection line 12 through the first via hole V1 on the one hand, connected to the first protection electrode 33 through a plurality of fifth via holes V5 on the other hand, and the tenth through hole V5 on the other hand.
  • the via hole V10 is connected to the first region of the second active layer of the first sub-pixel P1, so that the high-level signal transmitted by the first power supply line 41 is written into the first electrode of the second transistor T2.
  • the data line 42 is disposed in each sub-pixel, the data line 42 extends along the second direction D2, and is connected to the first region of the first active layer through the eighth via hole V8, so that the data line 42 transmits The data signal is written into the first transistor T1 of each sub-pixel.
  • the data line 42 in the second subpixel P2 is disposed close to the data line 42 in the third subpixel P3.
  • the compensation line 43 is disposed between the third sub-pixels P3 of two adjacent pixel units, and the compensation line 43 extends along the second direction D2.
  • the two protection electrodes 34 are connected, and on the other hand, they are connected to the compensation connection line 13 through the third via V3 , so that the compensation signal transmitted by the compensation line 43 is written into the third transistor T3 of each sub-pixel through the compensation connection line 13 .
  • the second power line 44 is disposed between the third sub-pixels P3 of two adjacent pixel units, and the second power line 44 extends along the second direction D2 through a plurality of seventh via holes V7 Connected to the third guard electrode 35 .
  • the second capacitor plate 45 is disposed in each sub-pixel, and the second capacitor plate 45 is connected to the second region of the second active layer through the eleventh via V11 on the one hand, and is connected to the second region of the second active layer through the eleventh via V11 on the other hand
  • the thirteenth via hole V13 is connected to the second region of the third active layer, and on the other hand is connected to the blocking layer 11 through the fourteenth via hole V14.
  • the orthographic projection of the second capacitor plate 45 on the substrate and the orthographic projection of the first capacitor plate 24 on the substrate have an overlapping area, and the second capacitor plate 45 and the first capacitor plate 24 are formed the first storage capacitor.
  • the shielding layer 11 and the first capacitor plate 24 form a second storage capacitor, and each sub-pixel is formed with a first storage capacitor in parallel and the second storage capacitor, effectively increasing the capacity of each sub-pixel storage capacitor.
  • the second capacitor plate 45 may simultaneously serve as the second electrode of the second transistor T2 and the second electrode of the third transistor T3, so that the second capacitor plate 45 and the second electrode of the second transistor T2 and the second pole of the third transistor T3 has the same potential.
  • the first connection electrode 46 is disposed in each sub-pixel, and the first connection electrode 46 is simultaneously connected to the first capacitor plate 24 and the second gate electrode 36 through the ninth via V9.
  • the first connection electrode 46 may serve as the second electrode of the first transistor T1, so that the gate electrode of the second transistor T2, the second electrode of the first transistor T1 and the first capacitor plate 24 have the same potential.
  • the second connection electrode 47 is provided in each sub-pixel, and the second connection electrode 47 is connected to the compensation connection line 13 through the fourth via hole V4 on the one hand, and is connected to the compensation connection line 13 through the twelfth via hole V12 on the other hand.
  • the third active layer is connected to the first region.
  • the second connection electrode 47 may serve as the first electrode of the third transistor T3 , so that the compensation signal transmitted by the compensation line 43 is written into the third transistor T3 of each sub-pixel through the compensation connection line 13 .
  • the third connection electrode 48 is provided in the second sub-pixel P2 and the third sub-pixel P3 of each pixel unit, and the third connection electrode 48 is connected to the power supply connection line 12 through the second via hole V2 on the one hand. On the other hand, it is connected to the first region of the second active layer through the tenth via hole V10.
  • the third connection electrode 48 can be used as the first electrode of the second transistor T2, so that the high-level signal transmitted by the first power supply line 41 is written into the first electrode of the second transistor T2 through the power supply connection line 12 .
  • the display substrate includes a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, Two insulating layers 92 , a second conductive layer disposed on the second insulating layer 92 , a third insulating layer 93 covering the second conductive layer, and a third conductive layer disposed on the third insulating layer 93 .
  • the first conductive layer at least includes the shielding layer 11, the semiconductor layer at least includes the second active layer 22, the third active layer 23 and the first capacitor plate 24, the second conductive layer at least includes the second gate electrode 36, and the third insulating layer.
  • Layer 93 is provided with a plurality of via holes, the plurality of via holes at least include: a tenth via hole V10, an eleventh via hole V11, a thirteenth via hole V13 and a fourteenth via hole V14, and the third conductive layer at least includes The compensation line 43, the second power line 44, the second capacitor plate 45 and the third connection electrode 48, the third connection electrode 48 is connected to the second active layer 22 through the tenth via V10, and the second capacitor plate 45 passes through the The eleventh via hole V11 , the thirteenth via hole V13 and the fourteenth via hole V14 are respectively connected to the second active layer 22 , the third active layer 23 and the blocking layer 11 .
  • Forming the fourth insulating layer and the first flat layer pattern may include: on the substrate on which the foregoing patterns are formed, firstly depositing a fourth insulating film, then coating the flattening film, and performing a patterning process on the flattening film and the flattening film.
  • the fourth insulating film is patterned to form a fourth insulating layer covering the third conductive layer and a flat layer disposed on the fourth insulating layer.
  • the fourth insulating layer and the flat layer are provided with anode vias K1 and electrode vias K2
  • the pattern is shown in Figs. 11a and 11b, and Fig. 11b is a cross-sectional view taken along the line A-A in Fig. 11a.
  • the anode via K1 is provided in each sub-pixel, and the flat layer and the fourth insulating layer in the anode via K1 are removed, exposing the surface of the second capacitor plate 45 .
  • the electrode via hole K2 is disposed between the third sub-pixels P3 of two adjacent pixel units, and the flat layer and the fourth insulating layer in the electrode via hole K2 are removed to expose the surface of the second power line 44 .
  • the anode via hole K1 and the electrode via hole K2 may each include a large hole disposed on the flat layer 95 and a small hole disposed on the fourth insulating layer 94 , and the small hole is disposed in the large hole.
  • the display substrate includes a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, Two insulating layers 92, a second conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the second conductive layer, a third conductive layer disposed on the third insulating layer 93, covering the third insulating layer
  • the fourth insulating layer 94 and the flat layer 95 are provided with anode vias K1 and electrode vias K2 , the anode vias K1 expose the second capacitor plate 45 , and the electrode vias K2 expose the second power lines 44 .
  • the driving circuit layer pattern is prepared on the substrate.
  • the driving circuit layer of each sub-pixel at least includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer layer
  • the second insulating layer is called the gate insulating (GI) layer
  • the third insulating layer is called the interlayer insulating (ILD) layer
  • the fourth insulating layer is called the passivation (PVX) layer.
  • the flat film can be made of organic materials such as resins.
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the semiconductor film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Various materials such as thiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Various materials such as thiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a first transparent conductive layer pattern is formed.
  • forming the first transparent conductive layer pattern may include: depositing a first transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first transparent conductive film through a patterning process to form the first transparent conductive film Layer pattern, the first transparent conductive layer pattern includes at least a first anode 51 and a first auxiliary electrode 61, as shown in FIG. 12a and FIG. 12b, FIG. 12b is a cross-sectional view of FIG.
  • the first anode 51 is disposed on the flat layer, and is connected to the second capacitor plate through the anode via K1.
  • the first auxiliary electrode 61 is disposed on the flat layer, and is connected to the second power line 44 through the electrode via hole K2.
  • the first transparent conductive film may use indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the shape of the first auxiliary electrode may be any one of the following: triangle, rectangle, trapezoid, polygon, circle and ellipse, triangle, rectangle, trapezoid .
  • the edge of the polygon may be a straight line or a curved line, and the corner of the first auxiliary electrode may be set as an arc-shaped chamfer, which is not limited in the present disclosure.
  • the display substrate may include a plurality of pixel units, and the plurality of pixel units are arranged in sequence along the first direction D1 and the second direction D2 respectively, and the first auxiliary electrode 61 may be arranged Between two adjacent pixel units in the first direction D1, a plurality of sub-pixels in the two pixel units share one auxiliary electrode.
  • the first pixel unit may include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3 arranged in sequence along the first direction D1, the second sub-pixel P2
  • the pixel unit may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the opposite direction of the first direction D1, that is, in the first direction D1, the third sub-pixel of the two pixel units P3 is adjacent.
  • the first auxiliary electrode 61 may be disposed between two adjacent third sub-pixels P3.
  • the shape of the first anode in the first sub-pixel P1 and the second sub-pixel P2 in the two pixel units may be a rectangle, which is similar to the shape of the sub-pixel where it is located.
  • the first anode of the third sub-pixel P3 in the first pixel unit (left side) has a first end and a second end, the first end being in the first
  • the dimension in the direction D1 is smaller than the dimension of the second end in the first direction D1.
  • the distance between the second end portion and the second pixel unit is smaller than the distance between the first end portion and the second pixel unit.
  • the first anode of the third sub-pixel P3 in the second pixel unit (right side) has a third end and a fourth end, the third end being in the first
  • the dimension in the direction D1 is smaller than the dimension of the fourth end in the first direction D1.
  • the distance between the fourth end portion and the first pixel unit is smaller than the distance between the third end portion and the first pixel unit.
  • the first auxiliary electrode 61 is disposed between the first end portion and the third end portion.
  • the shape of the first anode in the third sub-pixel P3 in the two pixel units may be a rectangle with a groove K, the rectangle is similar to the shape of the third sub-pixel P3, and the groove K is arranged on the first anode 51 close to the first auxiliary electrode. 61 side.
  • the third sub-pixel P3 of the first pixel unit (left) includes a first anode having a first groove
  • the third sub-pixel P3 of the second pixel unit (right) includes The first anode of the second groove
  • the first auxiliary electrode is disposed between the first anode with the first groove and the first anode with the second groove.
  • the first groove is provided on the side of the first anode close to the second pixel unit, and the second pixel unit (right side)
  • the second groove is arranged on the side of the first anode close to the first pixel unit, so that an accommodation area is formed between the adjacent third sub-pixels P3 in the two pixel units, and the first auxiliary The electrode 61 is arranged in the accommodating area.
  • the display substrate includes a first conductive layer disposed on the substrate 10, a first insulating layer 91 covering the first conductive layer, a semiconductor layer disposed on the first insulating layer 91, Two insulating layers 92, a second conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the second conductive layer, a third conductive layer disposed on the third insulating layer 93, covering the third insulating layer
  • Anode and auxiliary electrode patterns are formed.
  • forming the anode and auxiliary electrode patterns may include: sequentially depositing a fourth metal thin film and a second transparent conductive thin film on the substrate on which the aforementioned patterns are formed, and performing a patterning process on the fourth metal thin film and the second transparent conductive thin film The film is patterned to form patterns of the second anode 52 , the third anode 53 , the second auxiliary electrode 62 and the third auxiliary electrode 63 .
  • the third anode 53 is arranged on the side of the second anode 52 away from the substrate and connected to the second anode 52
  • the second auxiliary electrode 62 is arranged at the side of the first auxiliary electrode 61 away from the substrate and connected to the first auxiliary electrode 61
  • the third auxiliary electrode 63 is disposed on the side of the second auxiliary electrode 62 away from the substrate and is connected with the second auxiliary electrode 62 .
  • the stacked first anode 51 , the second anode 52 and the third anode 53 form the anode 50
  • the stacked first auxiliary electrode 61 , the second auxiliary electrode 62 and the third auxiliary electrode 63 form the auxiliary electrode 60 , as shown in FIG. 13 . Show.
  • the shapes of the second anode 52 and the third anode 53 are similar to the shape of the first anode 51, and the orthographic projection of the second anode 52 on the substrate may be located at the first anode 52 Within the range of the orthographic projection of the anode 51 on the substrate, the orthographic projection of the second anode 52 on the substrate may be within the range of the orthographic projection of the third anode 53 on the substrate.
  • the shapes of the second auxiliary electrode 62 and the third auxiliary electrode 63 are similar to the shape of the first auxiliary electrode 61 , and the orthographic projection of the second auxiliary electrode 62 on the substrate may be located on the first auxiliary electrode 61 Within the range of the orthographic projection on the substrate, the orthographic projection of the second auxiliary electrode 62 on the substrate may be located within the range of the orthographic projection of the third auxiliary electrode 63 on the substrate.
  • FIG. 14 is a schematic cross-sectional view of an auxiliary electrode according to an exemplary embodiment of the present invention, and is an enlarged view of the auxiliary electrode in FIG. 13 .
  • the first auxiliary electrode 61 located on the side (lower side) of the second auxiliary electrode 62 adjacent to the substrate has an edge protruding from the contour of the second auxiliary electrode 62, forming a "
  • the third auxiliary electrode 63 located on the side (upper side) of the second auxiliary electrode 62 away from the substrate has an edge protruding from the contour of the second auxiliary electrode 62, and the first auxiliary electrode 61 and the third auxiliary electrode 63 form a
  • the "eaves" structure makes the stacked first auxiliary electrode 61, the second auxiliary electrode 62 and the third auxiliary electrode 63 form an "I" shape.
  • the first anode 51 located on the side (lower side) of the second anode 52 adjacent to the substrate has an edge that protrudes from the contour of the second anode 52, forming a "roof” structure, located away from the second anode 52
  • the third anode 53 on the substrate side (upper side) has an edge protruding from the contour of the second anode 52, forming an "eaves” structure, so that the stacked first anode 51, the second anode 52 and the third anode 53 constitute a "roof” structure.
  • Work" font is
  • the first etching solution and the second etching solution may be used for etching respectively, and the auxiliary electrode and the anode may be formed by drilling.
  • the "work" shape structure In an exemplary embodiment, the first etching solution may be an etching solution for etching transparent conductive materials (ITO etching solution), and the second etching solution may be an etching solution for etching metal materials (Metal etching solution) ).
  • the etching process may include: firstly etching the second transparent layer not covered by the photoresist by using an ITO etching solution
  • the conductive thin film exposes the fourth metal thin film in the area not covered by the photoresist to form patterns of the third anode 53 and the third auxiliary electrode 63 .
  • the exposed fourth metal thin film is etched with Metal etching solution to form patterns of the second anode 52 and the second auxiliary electrode 62 .
  • the sides of the second anode 52 and the second auxiliary electrode 62 are etched into pits. Both the first anode 51 under the second anode 52 and the third anode 53 over the second anode 52 protrude from the second anode 52 by a distance, and the first auxiliary electrode 61 under the second auxiliary electrode 62 and the second auxiliary electrode 62 above The third auxiliary electrode 63 protrudes from the second auxiliary electrode 62 for a certain distance to form an "I"-shaped structure.
  • the formed auxiliary electrode has a plurality of exposed surfaces, and the exposed surfaces respectively include: the first auxiliary electrode 61 protrudes from the second auxiliary electrode 62 partially away from the substrate; The first upper surface 611 of the side, the second side surface 621 of the side of the second auxiliary electrode 62, the third upper surface 631 of the upper side of the third auxiliary electrode 63 (the side away from the substrate), the side of the third auxiliary electrode 63
  • the third side surface 632 of the third auxiliary electrode 63, the third lower surface 633 of the lower side of the third auxiliary electrode 63 (the side adjacent to the substrate), the third lower surface 633 refers to the part of the third auxiliary electrode 63 protruding from the second auxiliary electrode 62 adjacent to the substrate. side surface.
  • the aforementioned side surfaces refer to a plurality of circumferential surfaces whose normal direction is parallel or nearly parallel to the plane of the substrate.
  • the fourth metal thin film material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or the aforementioned metals
  • the second transparent conductive material can be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • a pixel definition layer pattern is formed.
  • forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition (PDL) layer 71 pattern,
  • the pixel defining layer 71 is provided with a first pixel opening K3 and a second pixel opening K4, the pixel defining layer 71 in the first pixel opening K3 is removed, exposing a part of the surface of the third anode 53 in the anode, and the second pixel opening K4
  • the inner pixel definition layer 71 is removed, exposing the entire surface of the second auxiliary electrode 62 and the third auxiliary electrode 63 in the auxiliary electrode, as shown in Figure 15a, Figure 15b and Figure 15c,
  • Figure 15a shows the pixel in the pixel definition layer
  • FIG. 15b is a schematic diagram of the position of the pixel opening in the pixel definition layer
  • the orthographic projection of the first pixel opening K3 on the substrate is located within the range of the orthographic projection of the third anode 53 on the substrate, and the orthographic projection of the second pixel opening K4 on the substrate is located in the first auxiliary electrode
  • the orthographic projection of the second auxiliary electrode 62 and the third auxiliary electrode 63 on the substrate is within the range of the orthographic projection of the second pixel opening K4 on the substrate.
  • the second pixel opening K4 exposing the entire surface of the second auxiliary electrode 62 and the third auxiliary electrode 63 means that the second pixel opening has a second lower opening on the side adjacent to the substrate and a second upper opening on the side away from the substrate.
  • the orthographic projections of the second auxiliary electrode 62 and the third auxiliary electrode 63 on the substrate are located within the range of the orthographic projection of the second lower opening on the substrate.
  • the pixel definition layer may employ polyimide, acrylic, polyethylene terephthalate, or the like.
  • the shape of the first pixel opening K3 may be an ellipse
  • the shape of the second pixel opening K4 may be a rectangle.
  • the cross-sectional shapes of the first pixel opening K3 and the second pixel opening K4 may be a rectangle or a trapezoid or the like.
  • forming the pattern of the organic light-emitting layer may include: evaporating an organic light-emitting material on the substrate formed with the aforementioned pattern to form patterns of the organic light-emitting layer 72 and the organic light-emitting block 73, and the organic light-emitting layer 72 is disposed on the third auxiliary electrode In areas other than 63, the organic light-emitting layer 72 is connected to the third anode 53 in the anode 50 through the first pixel opening K3.
  • the organic light-emitting block 73 is disposed on the surface of the third auxiliary electrode 63 away from the substrate.
  • the organic light-emitting block 73 is connected to the organic light-emitting block 73.
  • the light emitting layers 72 are arranged in isolation, as shown in FIG. 16 .
  • the third auxiliary electrode 63 protrudes from the second auxiliary electrode 62 by a distance, and thus the organic light-emitting material is disconnected at the side edge of the third auxiliary electrode 63, at
  • the organic light emitting block 73 is formed on the second upper surface 631 of the third auxiliary electrode 63 , and the organic light emitting layer 72 is formed outside the third auxiliary electrode 63 , so that the organic light emitting layer 72 and the organic light emitting block 73 are isolated from each other.
  • the orthographic projection of the organic light emitting blocks 73 on the substrate may be approximately equal to the orthographic projection of the third auxiliary electrode 63 on the substrate.
  • the organic light-emitting layer is cut off by the auxiliary electrode of the "I"-shaped structure to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block on the outgoing light, improves the quality of the outgoing light, and is conducive to improving the display quality.
  • the organic light-emitting layer 72 is connected to the third anode 53 through the first pixel opening K3, thus realizing the connection between the organic light-emitting layer 72 and the anode 50.
  • the organic light emitting layer 72 located in the area of the second pixel opening K4 partially covers the sidewall of the second pixel opening K4, and the other part covers part of the bottom surface of the second pixel opening K4, and a slope is formed on the bottom surface of the second pixel opening K4.
  • the organic light emitting layer 72 on the bottom surface of the second pixel opening K4 is spaced from the second auxiliary electrode 62 at a certain distance, and the first auxiliary electrode 61 is exposed in the area between the organic light emitting layer 72 and the second auxiliary electrode 62 .
  • the organic light-emitting layer may include an emitting layer (Emitting Layer, referred to as EML), and any one or more of the following: a hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer (HTL), Electron Block Layer (EBL), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer, referred to as EIL).
  • EML emitting layer
  • EML emitting Layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • HBL Hole Block Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (Fine Metal Mask, FMM for short) or an open mask (Open Mask), or by using an inkjet process.
  • FMM fine metal mask
  • Open Mask open mask
  • the organic light-emitting layer may be prepared by the following preparation method. First, the hole injection layer and the hole transport layer are sequentially evaporated by using an open mask, and a common layer of the hole injection layer and the hole transport layer is formed on the display substrate. Subsequently, an electron blocking layer and a red light-emitting layer were evaporated on the red sub-pixels using a fine metal mask, an electron blocking layer and a green light-emitting layer were evaporated on the green sub-pixels, and an electron blocking layer and a blue light-emitting layer were evaporated on the blue sub-pixels.
  • the electron blocking layer and the light-emitting layer of adjacent sub-pixels may overlap slightly (for example, the overlapping portion occupies less than 10% of the area of the respective light-emitting layer patterns), or may be isolated.
  • the hole blocking layer, the electron transport layer and the electron injection layer are sequentially evaporated using an open mask to form a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.
  • the electron blocking layer can be used as a microcavity adjustment layer of the light emitting device, and by designing the thickness of the electron blocking layer, the thickness of the organic light emitting layer between the cathode and the anode can meet the design of the microcavity length.
  • a hole transport layer, a hole blocking layer or an electron transport layer in the organic light emitting layer may be used as the microcavity adjustment layer of the light emitting device, which is not limited in the present disclosure.
  • the light emitting layer may include a host material and a dopant material doped in the host material, and the doping ratio of the guest material in the light emitting layer is 1% to 20%.
  • the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light; ”, which effectively improves the fluorescence quenching caused by the collision between the molecules of the light-emitting layer and the guest materials and the collision between the energies, and improves the luminous efficiency and device life.
  • the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage.
  • the host material and the guest material can be co-evaporated through a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the evaporation rate of the guest material can be controlled during the evaporation process. to control the doping ratio, or to control the doping ratio by controlling the evaporation rate ratio of the host material and the guest material.
  • the thickness of the light emitting layer may be about 10 nm to 50 nm.
  • the hole injection layer may employ inorganic oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide , tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or p-type dopants and hole transport material dopants of strong electron withdrawing systems may be employed.
  • the thickness of the hole injection layer may be about 5 nm to 20 nm.
  • the hole transport layer may use a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methyl fluorene, spirofluorene , dibenzothiophene or furan, etc.
  • the thickness of the hole transport layer may be about 40 nm to 150 nm.
  • the hole blocking layer and the electron transport layer may employ an aromatic heterocyclic compound such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazophenanthridine derivatives and other imidazole derivatives; pyrimidines Derivatives, triazine derivatives and other azine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives and other compounds containing a nitrogen-containing six-membered ring structure (also including phosphine oxides on the heterocyclic ring) Substituent compounds) etc.
  • the thickness of the hole blocking layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.
  • the electron injection layer may adopt alkali metals or metals, such as materials such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals Wait.
  • the electron injection layer may have a thickness of about 0.5 nm to 2 nm.
  • a cathode pattern is formed.
  • forming the cathode pattern may include: evaporating a cathode material on the substrate on which the aforementioned pattern is formed, forming a cathode 80 pattern, the cathode 80 being connected to the organic light-emitting layer 72 , and wrapping the organic light-emitting block 73 and the auxiliary electrode 60 by wrapping the organic light-emitting block 73 and the auxiliary electrode 60 .
  • a large-area contact connection with the auxiliary electrode 60 is realized in the manner shown in 17.
  • cathode 80 may be a unitary structure that communicates together. In areas other than the auxiliary electrode 60 , the cathode 80 is disposed on the organic light-emitting layer 72 . In the area where the auxiliary electrode 60 is located, the cathode 80 is disposed on the exposed surface of the organic light emitting block 73 on the one hand, and on the exposed surface of the auxiliary electrode on the other hand, forming a structure wrapping the auxiliary electrode 60 and the organic light emitting block 73 .
  • a part of the cathode 80 covers or partially covers the surface of the organic light-emitting block 73 on the side away from the substrate, and another part of the cathode 80 covers or partially covers or partially covers the surface of the organic light-emitting block 73 . side surface.
  • the organic light-emitting block 73 covers or partially covers the surface of the third auxiliary electrode 63 on the side away from the substrate, a part of the cathode 80 covers or partially covers the second side surface 632 of the third auxiliary electrode 63, and another part of the cathode 80 covers or partially covers the second side surface 632 of the third auxiliary electrode 63. Covers or partially covers the second lower surface 633 of the lower side of the third auxiliary electrode 63 , that is, the cathode 80 covers or partially covers the lower surface of the part of the third auxiliary electrode 63 protruding from the second auxiliary electrode 62 .
  • the cathode 80 and the third auxiliary electrode 63 are connected through the third side surface 632 and the third lower surface 633, the potentials of the cathode 80 on the upper side of the organic light-emitting block 73 and the third auxiliary electrode 63 on the lower side of the organic light-emitting block 73 are equal, That is, the potentials on the upper and lower sides of the organic light-emitting block 73 are equal, which ensures that the organic light-emitting block 73 does not emit light and avoids the flickering phenomenon caused by the light-emitting of the organic light-emitting block 73 .
  • the cathode 80 covers or partially covers the second side surface 621 of the side portion of the second auxiliary electrode 62 .
  • the cathode 80 covers or partially covers the exposed first auxiliary electrode 61 between the organic light emitting layer 72 and the second auxiliary electrode 62 .
  • the exemplary embodiment of the present disclosure effectively increases the contact area between the cathode and the auxiliary electrode through the contact connection between the cathode and the side surface of the second auxiliary electrode, effectively reduces the resistance at the contact interface, and improves the display effect.
  • the light-emitting structure layer pattern is prepared on the driving circuit layer.
  • the light-emitting structure layer includes an anode, an auxiliary electrode, a pixel definition layer, an organic light-emitting layer and a cathode.
  • the organic light-emitting layer is connected to the anode and the cathode respectively, and the cathode is connected to the auxiliary electrode.
  • the electrodes are connected to the second power line.
  • the preparation process of the display substrate may include forming an encapsulation layer pattern, and forming the encapsulation layer pattern may include: firstly depositing a first inorganic thin film by using an open mask by plasma-enhanced chemical vapor deposition (PECVD), A first encapsulation layer is formed. Subsequently, an organic material is inkjet printed on the first encapsulation layer by an inkjet printing process, and after curing to form a film, a second encapsulation layer is formed.
  • PECVD plasma-enhanced chemical vapor deposition
  • a second inorganic thin film is deposited by using an open mask to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single Layer, multi-layer or composite layer
  • the second encapsulation layer can be made of resin material to form a laminated structure of inorganic material/organic material/inorganic material
  • the organic material layer is arranged between the two inorganic material layers, which can ensure that the outside water vapor cannot enter Light emitting structure layer.
  • a touch structure layer may be formed on the encapsulation layer, and the touch structure layer may include a touch electrode layer, or a touch electrode layer and a touch insulating layer.
  • the preparation process of the display substrate may include processes such as peeling off the glass carrier, attaching the back film, cutting, etc., which are not limited in the present disclosure.
  • the exemplary embodiment of the present disclosure makes the The light-emitting layer is disconnected at the edge of the auxiliary electrode, so that the organic light-emitting block above the auxiliary electrode is isolated, which can avoid the interference of the organic light-emitting block on the outgoing light, improve the quality of the outgoing light, and help improve the display quality.
  • the third auxiliary electrode in the auxiliary electrodes is arranged to protrude from the second auxiliary electrode, and the cathode is connected to the third auxiliary electrode, so that both sides of the organic light-emitting block are realized.
  • the potentials of the OLEDs are the same, which ensures that the organic light-emitting block does not emit light, and avoids the flickering phenomenon caused by the light-emitting of the organic light-emitting block.
  • the exemplary embodiment of the present disclosure effectively increases the contact area between the cathode and the auxiliary electrode, effectively reduces the resistance at the contact interface, and improves the display effect by arranging the side contact connection between the cathode and the auxiliary electrode. Since the manufacturing method of the substrate according to the exemplary embodiment of the present disclosure does not adopt the laser drilling process, not only the production time of a single product is shortened, but also no particles are generated during the preparation process, thereby improving the production efficiency and product yield. Exemplary embodiments of the present disclosure show that the preparation method of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
  • the display substrate may be fabricated using another fabrication method.
  • Another manufacturing process of the display substrate may include the following operations.
  • Patterns of the first transparent conductive layer and the fourth metal layer are formed.
  • forming the patterns of the first transparent conductive layer and the fourth metal layer may include: sequentially depositing the first transparent conductive film and the fourth metal thin film on the substrate on which the aforementioned patterns are formed, and making the first transparent conductive film and the fourth metal film transparent through a patterning process The conductive thin film and the fourth metal thin film are patterned to form patterns of the first transparent conductive layer and the fourth metal layer.
  • the first conductive layer pattern includes at least a first anode 51 and a first auxiliary electrode 61 .
  • the first anode 51 is connected to the second capacitor plate 45 through the anode via hole, and the first auxiliary electrode 61 is connected to the second power line 44 through the electrode via hole.
  • the fourth metal layer includes at least a second anode 52 and a second auxiliary electrode 62, the second anode 52 is arranged on the side of the first anode 51 away from the substrate and is connected to the first anode 51, and the second auxiliary electrode 62 is arranged on the first auxiliary electrode 51.
  • the side of the electrode 61 away from the substrate is connected to the first auxiliary electrode 61, as shown in FIG. 18 .
  • the first transparent conductive thin film and the fourth metal thin film may be patterned using a patterning process of a halftone or gray tone mask.
  • the patterning may include: coating a layer of positive photoresist on the fourth metal film, exposing the photoresist with a halftone or gray tone mask, so that the photoresist forms a fully exposed area and a partially exposed area. areas and unexposed areas.
  • a development process is then performed, the photoresist in the unexposed area is retained, the photoresist has a first thickness, and the photoresist in the partially exposed area is removed, and the photoresist has a second thickness, and the second thickness is smaller than the first thickness , all the photoresist in the fully exposed area is removed, exposing the surface of the fourth metal film.
  • a first etching process is performed to etch away the first transparent conductive film and the fourth metal film in the fully exposed area to form patterns of the first anode 51 and the first auxiliary electrode 61 .
  • an ashing process is performed to remove the photoresist of the second thickness in the partially exposed area to expose the surface of the fourth metal thin film.
  • a second etching process is performed to etch away the fourth metal thin film in the partially exposed area to form patterns of the second anode 52 and the second auxiliary electrode 62 .
  • forming the third anode and third auxiliary electrode patterns may include: depositing a second transparent conductive film on the substrate on which the aforementioned patterns are formed, and patterning the second transparent conductive film through a patterning process to form a second transparent conductive film.
  • the third anode 53 is arranged on the side of the second anode 52 away from the substrate and is connected to the second anode 52.
  • the third auxiliary electrode 63 is arranged at a side of the second auxiliary electrode 62 away from the substrate. side and connected to the second auxiliary electrode 62 .
  • the stacked first anode 51 , the second anode 52 and the third anode 53 form the anode 50
  • the stacked first auxiliary electrode 61 , the second auxiliary electrode 62 and the third auxiliary electrode 63 form the auxiliary electrode 60 , as shown in FIG. 13 . Show.
  • the first etching solution and the second etching solution may be used to respectively perform etching, and the “I” shape of the auxiliary electrode and the anode may be formed by drilling.
  • the "work" shape structure may be an etching solution for etching transparent conductive materials (ITO etching solution), and the second etching solution may be an etching solution for etching metal materials (Metal etching solution) ).
  • the etching process may include: firstly etching the second transparent conductive film with an ITO etching solution to form patterns of the third anode 53 and the third auxiliary electrode 63 .
  • the etching was continued with Metal etching solution. Since the rate of etching the second anode 52 and the second auxiliary electrode 62 by the Metal etching solution is greater than the rate of etching the third anode 53 and the third auxiliary electrode 63, the side surfaces of the second anode 52 and the second auxiliary electrode 62 are etched etched into pits.
  • the first anode 51 below the second anode 52 and the third anode 53 above the second anode 52 both protrude from the second anode 52 by a certain distance, forming an "I"-shaped structure.
  • the first auxiliary electrode 61 below the second auxiliary electrode 62 and the third auxiliary electrode 63 above the second auxiliary electrode 62 protrude from the second auxiliary electrode 62 by a distance to form an "I"-shaped structure.
  • the display substrate prepared by the foregoing preparation process may include: a substrate 10 ; a first conductive layer disposed on the substrate 10 , the first conductive layer at least includes a blocking layer 11 ; The first insulating layer 91; the semiconductor layer arranged on the first insulating layer 91, the semiconductor layer at least includes the first capacitor plate 24 and the active layers of the plurality of transistors; the second insulating layer 92 arranged on the semiconductor layer; A second conductive layer on the second insulating layer 92, the second conductive layer at least includes gate electrodes of a plurality of transistors; a third insulating layer 93 covering the second conductive layer; a third conductive layer disposed on the third insulating layer 93 layer, the third conductive layer at least includes a second power line 44, a second capacitor plate 45 and the first and second poles of a plurality of transistors, the second capacitor plate 45 is connected to the shielding layer 11 through a via hole, the second The capacitor plate 45 and
  • the transistors in the driver circuit layer may be of a top-gate structure.
  • other film layer structures, electrode structures or lead structures may also be provided in the driving circuit layer and the light emitting structure layer.
  • the substrate may be a glass substrate, which is not specifically limited in this disclosure.
  • the present disclosure also provides a preparation method of a display substrate.
  • the preparation method may include:
  • a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes an anode, an organic light-emitting layer, an organic light-emitting block, a cathode and an auxiliary electrode, the organic light-emitting layer is respectively connected with the anode and the cathode, and the auxiliary
  • the electrode includes a bottom surface on a side close to the substrate, a top surface on a side away from the substrate, and a side surface disposed between the bottom surface and the top surface, the cathode is in contact with the side surface of the auxiliary electrode, and the organic light-emitting The block is disposed on a side of the top surface of the auxiliary electrode away from the substrate, and the organic light-emitting block is disposed in isolation from the organic light-emitting layer.
  • the present disclosure provides a preparation method of a display substrate.
  • the organic light-emitting layer is disconnected at the edge of the auxiliary electrode and isolated from the organic light-emitting block located above the auxiliary electrode, The interference of the organic light-emitting blocks on the outgoing light can be avoided, the quality of the outgoing light is improved, and the display quality is improved.
  • the potentials on both sides of the organic light-emitting block are realized to be the same, which ensures that the organic light-emitting block does not emit light and avoids The flickering phenomenon caused by the light emission of organic light-emitting blocks.
  • the exemplary embodiment of the present disclosure effectively increases the contact area between the cathode and the auxiliary electrode, effectively reduces the resistance at the contact interface, and improves the display effect by arranging the side contact connection between the cathode and the auxiliary electrode.
  • the preparation method of the present disclosure does not adopt the laser drilling process, not only the production time of a single product is shortened, but also no particles are generated during the preparation process, thereby improving the production efficiency and product yield.
  • Exemplary embodiments of the present disclosure show that the preparation method of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括叠设在基底上的驱动电路层和发光结构层，发光结构层包括沿远离基底的方向依次设置的阳极、像素定义层、有机发光层和阴极，以及沿远离基底的方向依次设置的辅助电极和有机发光块，像素定义层包括阳极开口和电极开口，阳极开口暴露出阳极，电极开口暴露出辅助电极，有机发光块与有机发光层分离，辅助电极包括沿远离基底的方向依次设置的第一辅助电极、第二辅助电极和第三辅助电极；阴极包括第一水平搭接部和第二侧壁搭接部，第一水平搭接部与第一辅助电极搭接，第二侧壁搭接部与第二辅助电极搭接，第二侧壁搭接部在平行于基底方向的厚度大于第一水平搭接部在垂直于基底方向的厚度。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述发光结构层包括沿远离基底的方向依次设置的阳极、像素定义层、有机发光层和阴极，以及沿远离基底的方向依次设置的辅助电极和有机发光块，所述像素定义层包括阳极开口和电极开口，所述阳极开口暴露出所述阳极，所述电极开口暴露出所述辅助电极，所述有机发光块与所述有机发光层分离，所述辅助电极包括第一辅助电极、位于所述第一辅助电极远离基底一侧的第二辅助电极以及位于所述第二辅助电极远离基底一侧的第三辅助电极；
所述阴极包括第一水平搭接部和第二侧壁搭接部，所述第一水平搭接部与第一辅助电极搭接，所述第二侧壁搭接部与第二辅助电极搭接，所述第二侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底方向的厚度。
在示例性实施例中，所述第二侧壁搭接部与所述第一辅助电极连接，所述第二侧壁搭接部与所述第三辅助电极靠近基底的表面接触，所述第二侧壁搭接部与第一水平搭接部连接。
在示例性实施例中，在所述第一辅助电极远离所述基底的一侧设置有所述有机发光层，所述有机发光层与所述第二辅助电极分离，所述阴极还包括第一侧壁搭接部，所述第一侧壁搭接部与所述有机发光层的侧面搭接，所述阴极还与所述有机发光层远离基底的一侧搭接。
在示例性实施例中，所述阴极还包括第二水平搭接部和第三搭接部，所述第二水平搭接部与所述第三辅助电极凸出第二辅助电极部分邻近所述基底一侧的表面搭接，所述第三搭接部与所述有机发光块远离基底一侧的表面和侧面以及所述第三辅助电极的侧面搭接，所述第二水平搭接部与第三搭接部连接。
在示例性实施例中，所述第三搭接部在垂直于基底方向的厚度大于所述第二侧壁搭接部在平行于基底方向的厚度，所述第一侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底方向的厚度。
在示例性实施例中，所述第二侧壁搭接部在平行于基底方向上的厚度为500埃米至3000埃米，所述第一水平搭接部在垂直于基底方向上的厚度为100埃米至1500埃米。
在示例性实施例中，第二辅助电极包括靠近基底的底面和远离基底的顶面，以及在顶面和底面之间的侧面，在垂直于基底的平面内，所述第二辅助电极的侧面与所述第二辅助电极的底面形成的角度小于90°。
在示例性实施例中，所述阳极包括第一阳极层、设置在所述第一阳极层远离所述基底一侧的第二阳极层以及设置在所述第二阳极层远离所述基底一侧的第三阳极层，所述第二阳极层在基底上的正投影位于所述第一阳极层在基底上的正投影的范围之内，所述第二阳极层在基底上的正投影位于所述第三阳极层在基底上的正投影的范围之内。
在示例性实施例中，所述第一阳极层与所述第一辅助电极同层设置，且材料相同；所述第二阳极层与所述第二辅助电极同层设置，且材料相同；所 述第三阳极层与所述第三辅助电极同层设置，且材料相同。
在示例性实施例中，所述第一阳极层在第二方向上具有第一端部和第二端部，所述第二阳极层具有第三端部和第四端部，所述第一端部在第一方向上的尺寸小于所述第二端部在所述第一方向上的尺寸，所述第三端部在所述第一方向上的尺寸小于所述第四端部在所述第一方向上的尺寸，所述辅助电极设置在所述第一端部和第三端部之间，所述第一方向与第二方向相交。
在示例性实施例中，所述第一阳极层在所述第一方向上具有比所述第一端部更靠近第二像素单元的部分；所述第二阳极层在所述第一方向上具有比所述第三端部更靠近第一像素单元的部分，所述第一像素单元和所述第二像素单元相邻。
在示例性实施例中，所述驱动电路层包括：设置在基底上的晶体管和电源电极、设置在所述晶体管和电源电极远离基底的一侧的钝化层，设置在所述钝化层远离基底的一侧的平坦层，所述平坦层上具有阳极过孔和电极过孔，所述电源电极与所述晶体管中的漏电极同层设置；所述钝化层上具有第一过孔和第二过孔，所述第一过孔暴露出所述晶体管的漏电极，所述第二过孔暴露出所述电源电极；所述阳极过孔暴露出所述第一过孔，所述电极过孔暴露出所述第二过孔。
在示例性实施例中，所述第一辅助电极通过所述电极过孔和第二过孔与所述电源电极连接，所述第二辅助电极与所述第一辅助电极直接接触，所述第二辅助电极在基底上的正投影位于所述第三辅助电极在基底上的正投影的范围内，所述第二辅助电极在基底上的正投影位于所述第一辅助电极在基底上的正投影范围内。
在示例性实施例中，所述第二过孔在基底上的正投影位于所述电极过孔在基底上的正投影范围内，所述第二过孔在基底上的正投影位于所述第三辅助电极在基底上的正投影范围内。
在示例性实施例中，所述电极开口在基底上的正投影位于所述第一辅助电极在基底上的正投影的范围之内。
在示例性实施例中，多个所述阳极沿第一方向排列成行，同一行的所述 阳极对应的阳极过孔设置在沿第一方向延伸的同一条直线上，至少一个连接电极对应的电极过孔在第二方向与所述阳极过孔交叠，所述第二方向与第一方向相交。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，包括：
在基底上形成驱动电路层；
在所述驱动电路层上形成发光结构层，所述发光结构层包括沿远离基底的方向依次设置的阳极、像素定义层、有机发光层和阴极，以及沿远离基底的方向依次设置的辅助电极和有机发光块，所述像素定义层包括阳极开口和电极开口，所述阳极开口暴露出所述阳极，所述电极开口暴露出所述辅助电极，所述有机发光块与所述有机发光层分离，所述辅助电极包括第一辅助电极、位于所述第一辅助电极远离基底一侧的第二辅助电极以及位于所述第二辅助电极远离基底一侧的第三辅助电极；所述阴极包括第一水平搭接部和第二侧壁搭接部，所述第一水平搭接部与第一辅助电极搭接，所述第二侧壁搭接部与第二辅助电极搭接，所述第二侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底方向的厚度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5a为本公开实施例一种显示基板的结构示意图；
图5b为图5a中A区域的放大结构示意图；
图6a为本公开实施例一种形成第一导电层图案后的示意图；
图6b为图6a中A-A向的剖视图；
图7a为本公开实施例一种形成半导体层图案后的示意图；
图7b为图7a中A-A向的剖视图；
图8a为本公开实施例一种形成第二导电层图案后的示意图；
图8b为图8a中A-A向的剖视图；
图9a为本公开实施例一种形成第三绝缘层图案后的示意图；
图9b为图9a中A-A向的剖视图；
图10a为本公开实施例一种形成第三导电层图案后的示意图；
图10b为图10a中A-A向的剖视图；
图11a为本公开实施例一种形成第一平坦层图案后的示意图；
图11b为图11a中A-A向的剖视图；
图12a为本公开实施例一种形成第一透明导电层图案后的示意图；
图12b为图12a中A-A向的剖视图；
图13为本公开实施例一种形成阳极和辅助电极图案后的示意图；
图14为本发明实施例辅助电极的剖面示意图；
图15a和图15b为本公开实施例一种形成像素定义层图案后的示意图；
图15c为图15a和图15b中A-A向的剖视图；
图16为本公开实施例一种形成有机发光层图案后的示意图；
图17为本公开实施例一种形成阴极图案后的示意图；
图18为本公开实施例另一种形成阳极和辅助电极图案的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据驱动器、扫描驱动器和像素阵列，像素阵列可以包括多个扫描线(S1到Sm)、多个数据线(D1到Dn)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器。数据驱动器可以利用从时序控制器接收 的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。子像素阵列可以包括多个像素子PXij。每个像素子PXij可以连接到对应的数据线和对应的扫描线，i和j可以是自然数。子像素PXij可以指其中晶体管连接到第i扫描线且连接到第j数据线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一发光单元(子像素)P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3，第一发光单元P1、第二发光单元P2和第三发光单元P3均包括像素驱动电路和发光器件。第一发光单元P1、第二发光单元P2和第三发光单元P3中的像素驱动电路分别与扫描线、数据线和发光信号线连接，像素驱动电路被配置为在扫描线和发光信号线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。第一发光单元P1、第二发光单元P2和第三发光单元P3中的发光器件分别与所在发光单元的像素驱动电路连接，发光器件被配置为响应所在发光单元的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)发光单元、绿色(G)发光单元和蓝色(B)发光单元，或者可以包括红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元，本公开在此不做限定。在示例性实施方式中，像素单元中发光单元的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个发光单元时，三个发光单元可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个发光单元时，四个发光单元可以 采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层102、设置在驱动电路层102远离基底10一侧的发光结构层103以及设置在发光结构层103远离基底10一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底10可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个晶体管101和一个存储电容101A为例进行示意。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与晶体管101的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路为3T1C结构，可以包括3个开关晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)、1个存储电容C ST和6个信号线(数据线Dn、第一扫描线Gn、第二扫描线Sn、补偿线Se、第一电源线VDD和第二电源线VSS)。在示例性实施方式中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极耦接于第一扫描线Gn，第一晶体管T1的第一极耦接于数据线Dn，第一晶体管T1的第二极耦接于第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描线Gn控制下，接收数据线Dn传输的数据信号，使第二晶体管 T2的栅电极接收所述数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极，第二晶体管T2的第一极耦接于第一电源线VDD，第二晶体管T2的第二极耦接于OLED的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描线Sn，第三晶体管T3的第一极连接补偿线Se，第三晶体管T3的第二极耦接于第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。OLED的第一极耦接于第二晶体管T2的第二极，OLED的第二极耦接于第二电源线VSS，OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C ST的第一极与第二晶体管T2的栅电极耦接，存储电容C ST的第二极与第二晶体管T2的第二极耦接，存储电容C ST用于存储第二晶体管T2的栅电极的电位。
在示例性实施方式中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。第一晶体管T1到第三晶体管T3可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第三晶体管T3可以包括P型晶体管和N型晶体管。在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
按照出光方向，OLED显示基板可以分为三种：底发射OLED、顶发射OLED与双面发射OLED。底发射OLED是光从基板底部方向出射，顶发射OLED是光从基板顶部方向出射，双面发射OLED是光同时从基板底部方向和基板顶部方向出射。与底发射OLED相比，顶发射OLED具有开口率大、色纯度高、容易实现高分辨率(Pixels per inch，PPI)等优点，受到了人们的广泛重视。
对于顶发射OLED，由于出光方向在阴极(Cathode)一侧，因此要求阴极具有较好的透光性和导电性，但同时满足透光性和导电性要求则存在较大的难度。例如，为了满足导电性要求，必然要求阴极的厚度较大，但此时阴极的透过率较低，会出现视角色偏问题。为了满足透光性要求，必然要求阴 极的厚度较薄，但此时阴极的阻抗较大，不仅会导致电压上升、功耗增大的问题，而且导致阴极上各处电压分布不均匀，出现亮度不均匀的问题。
一种顶发射OLED显示基板中，为了减小阴极电压降，采用设置辅助电极(Auxiliary electrode)来降低阴极的阻抗，进而减小阴极电压降。该显示基板中，辅助电极设置在驱动电路层上，阴极设置在发光结构层上，通过激光工艺在驱动电路层和发光结构层形成过孔，使阴极通过该过孔与辅助电极连接。由于激光工艺在有机发光层上形成过孔时会产生大量的颗粒(Particle)，因而该结构和工艺严重影响了产品良率。由于采用激光工艺增加了单件产品生产时间(Tact time)，因而该结构和工艺大大降低了生产效率。由于激光工艺形成的过孔较小，阴极和辅助电极的接触面积较小，因而该结构和工艺未能有效减小阴极电压降，影响了显示效果。
图5a为本公开示例性实施例一种显示基板的结构示意图，示意了显示基板中一个子像素的剖面结构，图5b为图5a中A区域的放大结构示意图。如图5a和图5b所示，在示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括设置在基底10上的驱动电路层102和设置在驱动电路层102远离基底一侧的发光结构层103。驱动电路层102可以包括第二电源线44和构成像素驱动电路的晶体管和存储电容，发光结构层103可以包括阳极50、辅助电极60、像素定义层71、有机发光层72和阴极80，有机发光层72分别与阳极50和阴极80连接，辅助电极60与第二电源线44连接，阴极80与辅助电极60连接。辅助电极60包括靠近基底一侧的底面、远离基底一侧的顶面以及设置在底面与顶面之间的侧面，阴极80与辅助电极60的侧面接触。
在示例性实施方式中，在垂直于显示基板的平面内，辅助电极60可以包括第一辅助电极61、设置在第一辅助电极61远离基底一侧的第二辅助电极62和设置在第二辅助电极62远离基底一侧的第三辅助电极63，叠设的第一辅助电极61、第二辅助电极62和第三辅助电极63形成“工”字形结构，第二辅助电极62在基底上的正投影均位于第一辅助电极61和第三辅助电极63在基底上的正投影的范围之内。
在示例性实施方式中，发光结构层102可以包括有机发光块73，有机发 光块73和有机发光层72同层设置，材料相同，且通过同一次蒸镀工艺同时形成。在示例性实施方式中，有机发光块73设置在辅助电极60远离基底的一侧，有机发光块73与有机发光层72隔离设置。
在示例性实施方式中，有机发光块73设置在第三辅助电极63远离基底的一侧，有机发光块73在基底上的正投影位于第三辅助电极63在基底上的正投影的范围之内。
在示例性实施方式中，在垂直于显示基板的平面内，阳极50可以包括第一阳极51、设置在第一阳极51远离基底一侧的第二阳极52以及设置在第二阳极52远离基底一侧的第三阳极53，叠设的第一阳极51、第二阳极52和第三阳极53构成“工”字形，第二阳极52在基底上的正投影均位于第一阳极51和第三阳极53在基底上的正投影的范围之内。
在示例性实施方式中，第一辅助电极61与第一阳极51同层设置，材料相同，且通过同一次图案化工艺同时形成。
在示例性实施方式中，第二辅助电极62与第二阳极52同层设置，材料相同，且通过同一次图案化工艺同时形成。
在示例性实施方式中，第三辅助电极63与第三阳极53同层设置，材料相同，且通过同一次图案化工艺同时形成。
在示例性实施方式中，驱动电路层102可以包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体层，设置在半导体层上的第二绝缘层92，设置在第二绝缘层92上的第二导电层，覆盖第二导电层的第三绝缘层93，设置在第三绝缘层93上的第三导电层，覆盖第三导电层的第四绝缘层94，设置在第四绝缘层94上的平坦层95。第一导电层至少包括遮挡层，半导体层至少包括第一电容极板和多个晶体管的有源层，第二导电层至少包括多个晶体管的栅电极，第三导电层至少包括第二电源线、第二电容极板和多个晶体管的第一极和第二极，第二电容极板通过过孔与遮挡层连接，第二电容极板和第一电容极板形成第一存储电容，遮挡层和第一电容极板形成第二存储电容。第四绝缘层94和平坦层95上设置有阳极过孔和电极过孔，阳极通过该阳极过孔与第二电容极板连接 辅助电极通过电极过孔与第二电源线连接。
在示例性实施方式中，发光结构层103中的像素定义层71设置有第一像素开口和第二像素开口，第一像素开口暴露出第三阳极53的部分表面，第二像素开口暴露出第二辅助电极62和第三辅助电极63。
在示例性实施方式中，发光结构层103中的阴极80通过包裹有机发光块73和辅助电极60的方式实现阴极80与辅助电极60的大面积接触连接。
在示例性实施方式中，对于远着远离基底方向叠设的第一辅助电极61、第二辅助电极62、第三辅助电极63和有机发光块73，有机发光块73暴露出的表面包括：位于远离基底一侧的上表面和位于侧部的侧表面，第三辅助电极63暴露出的表面包括：位于侧部的第三侧表面和凸出第二辅助电极62部分邻近基底一侧的第三下表面，第二辅助电极62暴露出的表面包括：位于侧部的第二侧表面。在示例性实施方式中，侧表面是指法线方向与基底平面平行或接近平行的、周向的多个表面。阴极80包裹有机发光块73和辅助电极60是指：阴极80覆盖或部分覆盖有机发光块73的上表面和所有的侧表面，阴极80覆盖或部分覆盖第三辅助电极63所有的第三侧表面和第三下表面，阴极80完全覆盖或部分覆盖第二辅助电极62所有的第二侧表面。
在示例性实施方式中，如图5b所示，阴极80包括第一水平搭接部242和第二侧壁搭接部243，第一水平搭接部242与第一辅助电极61搭接，第二侧壁搭接部243与第二辅助电极62搭接，第二侧壁搭接部243在第一方向上的厚度a大于第一水平搭接部242在第二方向上的厚度b。本公开实施例中，第一方向可以为平行于基底的方向，第二方向可以为垂直于基底的方向。由此，本公开实施例可以增强辅助电极的“工”字形支撑力，并可以增大第二侧壁搭接部243与第三辅助电极63下侧的第三下表面之间以及第二侧壁搭接部243与位于电极过孔K2的底面位置的第一辅助电极61之间的有效接触面积，使得第二侧壁搭接部243具有更稳定的支撑能力，提高支撑搭接的稳定性，进而提升辅助阴极的信赖性。
在示例性实施方式中，如图5b所示，阴极80还包括第一侧壁搭接部241，第一侧壁搭接部241在第一方向上的厚度c大于第一水平搭接部242 在第二方向上的厚度b。
在示例性实施方式中，如图5b所示，第二侧壁搭接部243在第一方向上的厚度a为500埃米(A)至3000埃米。第二侧壁搭接部243在第一方向上的厚度a越大，第二侧壁搭接部243与第三辅助电极63下侧的第三下表面以及位于电极过孔K2的底面位置的第一辅助电极61之间的接触面积越大，它们之间形成的粘结力越强，那么辅助电极形成的力学支撑与连接稳定性也越强；此外，第二侧壁搭接部243的搭接厚度越厚，自身的电阻越小，进而可以减小整个辅助电极的电阻，提高电学性能。
示例性的，如图5b所示，第二侧壁搭接部243在第一方向上的厚度a可以为700埃米。
在示例性实施方式中，如图5b所示，第一水平搭接部242的厚度b为100埃米至1500埃米。由此，可以使得第一水平搭接部242的阻值较小，电学性能较好，且第一水平搭接部242越厚，搭接的强度越强，搭接效果更不易失效，有利于辅助阴极信赖性的提升；另外，第一水平搭接部242厚度越厚，与第一侧壁搭接部241的搭接效果也越好。
示例性的，如图5b所示，第一水平搭接部242的厚度b可以为300埃米。
在示例性实施方式中，如图5b所示，第一水平搭接部242与位于电极过孔K2的底面位置的第一辅助电极61搭接，由此，使得第一辅助电极61与第二辅助电极62均与阴极24相搭接，一方面使得第一辅助电极61与第二辅助电极62的粘结性能更好，另一方面也减小了整个辅助电极的电阻。
在示例性实施方式中，如图5b所示，阴极80还包括第二水平搭接部244和第三搭接部245，第二水平搭接部244与第三辅助电极63凸出第二辅助电极62部分邻近基底一侧的表面搭接，第三搭接部245与有机发光块73远离基底一侧的表面和侧面以及第三辅助电极63的侧面搭接，第二水平搭接部244与第三搭接部245连接。
在示例性实施方式中，如图5b所示，第三搭接部245在垂直于基底方向的厚度大于第二侧壁搭接部243在平行于基底方向的厚度，第一侧壁搭接部241在平行于基底方向的厚度大于第一水平搭接部242在垂直于基底方向的 厚度。
在示例性实施方式中，如图5b所示，第二辅助电极62包括靠近基底的底面和远离基底的顶面，以及在顶面和底面之间的侧面，在垂直于基底的平面内，第二辅助电极62的侧面与第二辅助电极62的底面形成的角度γ小于90°。
在示例性实施方式中，在平行于显示基板的平面内，辅助电极60的形状可以是如下任意一种多种：三角形、矩形、梯形、多边形、圆形和椭圆形。
在示例性实施方式中，在平行于显示基板的平面上，所述显示基板包括多个像素单元，辅助电极可以设置在相邻的像素单元的阳极之间。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以显示基板的两个像素单元(6个子像素)为例，显示基板的制备过程可以包括如下操作。
(1)提供基底。在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料 层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以一种叠层结构为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在基底上沉积第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，在基底上形成第一导电层图案，第一导电层图案至少包括：遮挡层11、电源连接线12和补偿连接线13，如图6a和图6b所示，图6b为图6a中A-A向的剖视图。
在示例性实施例中，遮挡层11设置在每个子像素中，可以为设置有凸起或凹槽的矩形状。电源连接线12设置在一个像素单元中，沿第一方向D1或第一方向D1的反方向延伸到第一子像素P1、第二子像素P2和第三子像素P3，相邻像素单元之间的电源连接线12间隔设置，电源连接线12配置为连接后续形成的第一电源线，为所在像素单元的每个子像素的像素驱动电路提供电源信号。补偿连接线13设置在一个像素单元中，沿第一方向D1延伸或第一方向D1的反方向延伸到第一子像素P1、第二子像素P2和第三子像素P3，相邻两个像素单元的补偿连接线13相互连接，形成一体结构，补偿连接线13配置为连接后续形成的补偿线，为所在像素单元的每个子像素的像素驱动电路提供补偿信号。
如图6b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，第一导电层至少包括遮挡层11。
(3)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖第一金属层图案的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，每个子像素的半导体层图案可以包括第一晶体管T1的第一有源层21、第二晶体管T2的第二有源层22、第三晶体管T3的第三有源层23和第一电容极板24，如图7a和图7b所示，图7b为图7a中A-A向的剖视图。
在示例性实施例中，每个子像素中的第一有源层21、第二有源层22和第三有源层23可以均为沿第二方向D2延伸的条形状，且间隔设置，第一电容极板24可以为设置有凸起或凹槽的矩形状，第一有源层21和第一电容极板24为相互连接的一体结构，第二有源层22在基底上的正投影位于遮挡层11在基底上的正投影的范围之内，第一电容极板24在基底上的正投影位于遮挡层11在基底上的正投影的范围之内。
如图6b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，以及设置在第一绝缘层91上的半导体层。第一导电层至少包括遮挡层11，半导体层至少包括第二有源层22、第三有源层23和第一电容极板24。
(4)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜和第二绝缘薄膜进行图案化，形成第二绝缘层以及设置在第二绝缘层上的第二导电层图案，第二导电层图案至少包括：第一扫描线31、第二扫描线32、第一保护电极33、第二保护电极34、第三保护电极35和第二栅电极36，如图8a和图8b所示，图8b为图8a中A-A向的剖视图。在示例性实施例中，第二导电层可以称为栅金属(GATE)层。
在示例性实施例中，第一扫描线31和第二扫描线32沿第一方向D1延伸。第一扫描线31与每个子像素中第一有源层21相重叠的区域作为所在子像素的第一晶体管T1的栅电极，第二扫描线32与每个子像素中第三有源层23相重叠的区域作为所在子像素的第三晶体管T3的栅电极。在示例性实施 例中，第一扫描线31和第二扫描线32中作为栅电极的以外区域可以设置成双线结构，以提高信号传输的可靠性。
在示例性实施例中，第一保护电极33、第二保护电极34和第三保护电极35均为沿第二方向D2延伸的条形。第一保护电极33可以设置在每个像素单元中，位于第一子像素P1远离第二子像素P2的一侧，第一保护电极33配置为与后续形成的第一电源线连接。第二保护电极34和第三保护电极35可以设置在相邻两个像素单元的第三子像素P3之间，第二保护电极34和第三保护电极35沿着第一方向D1依次设置，第二保护电极34配置为与后续形成的补偿线连接，第三保护电极35配置为与后续形成的第二电源线连接。
在示例性实施例中，第二栅电极36为沿第一方向D1延伸的条形，可以设置在每个子像素中，第二栅电极36在基底上的正投影与第二有源层22和第一电容电极24均存在重叠区域。
在示例性实施例中，形成第二导电层图案后，可以利用第二导电层作为遮挡，对半导体层进行导体化处理，被第二导电层遮挡区域的半导体层形成第一晶体管T1、第二晶体管T2和第三晶体管T3的沟道区域，未被第二导电层遮挡区域的半导体层被导体化，即第一电容极板24和三个有源层的第一区和第二区均被导体化。
如图8b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体层，第二绝缘层92以及设置在第二绝缘层92上的第二导电层。第一导电层至少包括遮挡层11，半导体层至少包括第二有源层22、第三有源层23和第一电容极板24，第二导电层至少包括第二栅电极36。在示例性实施例中，第二绝缘层和第二导电层的图案可以基本上相同，且第二导电层在基底上的正投影位于第二绝缘层在基底上的正投影的范围之内。
(5)形成第三绝缘层图案。在示例性实施例中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，第三绝缘层上设置有多个过孔，多个过孔至少包括：第一过孔V1至第十四过孔V14， 如图9a和图9b所示，图9b为图9a中A-A向的剖视图。
如图9a所示，在示例性实施例中，第一过孔V1设置在第一子像素P1的电源连接线12上，第二过孔V2分别设置在第二子像素P2和第三子像素P3的电源连接线12上，第一过孔V1和第二过孔V2内的第三绝缘层和第一绝缘层被刻蚀掉，暴露出电源连接线12的表面。第一过孔V1配置为使后续形成的第一电源线通过该过孔与电源连接线12连接，第二过孔V2配置为使后续形成的第二晶体管T2的第一极通过该过孔与电源连接线12连接。
在示例性实施例中，第三过孔V3设置在相邻第三子像素P3之间的补偿连接线13上，第四过孔V4设置在每个子像素的补偿连接线13上，第三过孔V3和第四过孔V4内的第三绝缘层和第一绝缘层被刻蚀掉，暴露出补偿连接线13的表面。第三过孔V3配置为使后续形成的补偿线通过该过孔与补偿连接线13连接，第四过孔V4配置为使后续形成的第三晶体管T3的第一极通过该过孔与补偿连接线1连接。
在示例性实施例中，多个第五过孔V5设置在第一保护电极33所在区域，第五过孔V5内的第三绝缘层被刻蚀掉，暴露出第一保护电极33的表面。第五过孔V5配置为使后续形成的第一电源线通过该过孔与第一保护电极33连接，设置多个第五过孔V5可以提高连接可靠性。
在示例性实施例中，多个第六过孔V6设置在第二保护电极34所在区域，第六过孔V6内的第三绝缘层被刻蚀掉，暴露出第二保护电极34的表面。第六过孔V6配置为使后续形成的补偿线通过该过孔与第二保护电极34连接，设置多个第六过孔V6可以提高连接可靠性。
在示例性实施例中，多个第七过孔V7设置在第三保护电极35所在区域，第七过孔V7内的第三绝缘层被刻蚀掉，暴露出第三保护电极35的表面。第七过孔V7配置为使后续形成的第二电源线通过该过孔与第三保护电极35连接，设置多个第七过孔V7可以提高连接可靠性。
在示例性实施例中，第八过孔V8设置在每个子像素的第一有源层第一区所在区域，第八过孔V8内的第三绝缘层被刻蚀掉，暴露出第一有源层第一区的表面。第八过孔V8配置为使后续形成的数据线通过该过孔与第一有源层第一区连接。
在示例性实施例中，第九过孔V9设置在每个子像素的第一电容极板24和第二栅电极36所在区域，第九过孔V9内的第三绝缘层被刻蚀掉，第九过孔V9同时暴露出第一电容极板24和第二栅电极36的表面。第九过孔V9配置为使后续形成的第一晶体管T1的第二极(第二晶体管T2的栅电极)通过该过孔同时与第一电容极板24和第二栅电极36连接。
在示例性实施例中，第十过孔V10设置在每个子像素的第二有源层第一区所在区域，第十过孔V10内的第三绝缘层被刻蚀掉，暴露出第二有源层第一区的表面。第一子像素P1的第十过孔V10配置为使后续形成的第一电源线通过该过孔与第二有源层第一区连接，第二子像素P2和第三子像素P3的第十过孔V10配置为使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层第一区连接。
在示例性实施例中，第十一过孔V11设置在每个子像素的第二有源层第二区所在区域，第十一过孔V11内的第三绝缘层被刻蚀掉，暴露出第二有源层第二区的表面。第十一过孔V11配置为使后续形成的第二电容极板(第二晶体管T2的第二极和第三晶体管T3的第二极)通过该过孔与第二有源层第二区连接。
在示例性实施例中，第十二过孔V12设置在每个子像素的第三有源层第一区所在区域，第十二过孔V12内的第三绝缘层被刻蚀掉，暴露出第三有源层第一区的表面。第十二过孔V12配置为使后续形成的第三晶体管T3的第一极通过该过孔与第三有源层第一区连接。
在示例性实施例中，第十三过孔V13设置在每个子像素的第三有源层第二区所在区域，第十三过孔V13内的第三绝缘层被刻蚀掉，暴露出第三有源层第二区的表面。第十三过孔V13配置为使后续形成的第二电容极板(第二晶体管T2的第二极和第三晶体管T3的第二极)通过该过孔与第三有源层第二区连接。
在示例性实施例中，第十四过孔V14设置在每个子像素的遮挡层11所在区域，第十四过孔V14内的第三绝缘层和第一绝缘层被刻蚀掉，暴露出遮挡层11的表面。第十四过孔V14配置为使后续形成的第二电容极板(第二晶体管T2的第二极和第三晶体管T3的第二极)通过该过孔与遮挡层11连 接。
如图9b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体层，第二绝缘层92，设置在第二绝缘层92上的第二导电层，以及覆盖第二导电层的第三绝缘层93。第一导电层至少包括遮挡层11，半导体层至少包括第二有源层22、第三有源层23和第一电容极板24，第二导电层至少包括第二栅电极36，第三绝缘层93上设置有多个过孔，多个过孔至少包括：第十过孔V10、第十一过孔V11、第十三过孔V13和第十四过孔V14。
(6)形成第三导电层图案。在示例性实施例中，形成第三导电层图案可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据线42、补偿线43、第二电源线44、第二电容极板45、第一连接电极46、第二连接电极47和第三连接电极48，如图10a和图10b所示，图10b为图10a中A-A向的剖视图。在示例性实施例中，第三导电层可以称为源漏金属(SD)层。
如图10a所示，在示例性实施例中，第一电源线41设置在每个像素单元中，位于第一子像素P1远离第二子像素P2的一侧，第一电源线41沿着第二方向D2延伸，第一电源线41一方面通过第一过孔V1与电源连接线12连接，另一方面通过多个第五过孔V5与第一保护电极33连接，又一方面通过第十过孔V10与第一子像素P1的第二有源层第一区连接，使第一电源线41传输的高电平信号写入第二晶体管T2的第一极。
在示例性实施例中，数据线42设置在每个子像素中，数据线42沿着第二方向D2延伸，通过第八过孔V8与第一有源层第一区连接，使数据线42传输的数据信号写入每个子像素的第一晶体管T1。在示例性实施例中，第二子像素P2中的数据线42与第三子像素P3中的数据线42靠近设置。
在示例性实施例中，补偿线43设置在相邻两个像素单元的第三子像素P3之间，补偿线43沿着第二方向D2延伸，一方面通过多个第六过孔V6与第二保护电极34连接，另一方面通过第三过孔V3与补偿连接线13连接，使补偿线43传输的补偿信号通过补偿连接线13写入每个子像素的第三晶体 管T3。
在示例性实施例中，第二电源线44设置在相邻两个像素单元的第三子像素P3之间，第二电源线44沿着第二方向D2延伸，通过多个第七过孔V7与第三保护电极35连接。
在示例性实施例中，第二电容极板45设置在每个子像素中，第二电容极板45一方面通过第十一过孔V11与第二有源层第二区连接，另一方面通过第十三过孔V13与第三有源层第二区连接，又一方面通过第十四过孔V14与遮挡层11连接。在示例性实施例中，第二电容极板45在基底上的正投影与第一电容极板24在基底上的正投影存在重叠区域，第二电容极板45与第一电容极板24构成第一存储电容。由于第二电容极板45与遮挡层11连接，两者具有相同的电位，因而使得遮挡层11与第一电容极板24形成第二存储电容，每个子像素中形成有并联的第一存储电容和第二存储电容，有效增加了每个子像素存储电容的容量。在示例性实施例中，第二电容极板45可以同时作为第二晶体管T2的第二极和第三晶体管T3的第二极，使第二电容极板45、第二晶体管T2的第二极和第三晶体管T3的第二极具有相同的电位。
在示例性实施例中，第一连接电极46设置在每个子像素中，第一连接电极46通过第九过孔V9同时与第一电容极板24和第二栅电极36连接。在示例性实施例中，第一连接电极46可以作为第一晶体管T1的第二极，使第二晶体管T2的栅电极、第一晶体管T1的第二极和第一电容极板24具有相同的电位。
在示例性实施例中，第二连接电极47设置在每个子像素中，第二连接电极47一方面通过第四过孔V4与补偿连接线13连接，另一方面通过第十二过孔V12与第三有源层第一区连接。在示例性实施例中，第二连接电极47可以作为第三晶体管T3的第一极，使补偿线43传输的补偿信号通过补偿连接线13写入每个子像素的第三晶体管T3。
在示例性实施例中，第三连接电极48设置在每个像素单元的第二子像素P2和第三子像素P3中，第三连接电极48一方面通过第二过孔V2与电源连接线12连接，另一方面通过第十过孔V10与第二有源层第一区连接。在示例性实施例中，第三连接电极48可以作为第二晶体管T2的第一极，使第一 电源线41传输的高电平信号通过电源连接线12写入第二晶体管T2的第一极。
如图10b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体层，第二绝缘层92，设置在第二绝缘层92上的第二导电层，覆盖第二导电层的第三绝缘层93，以及设置在第三绝缘层93上的第三导电层。第一导电层至少包括遮挡层11，半导体层至少包括第二有源层22、第三有源层23和第一电容极板24，第二导电层至少包括第二栅电极36，第三绝缘层93上设置有多个过孔，多个过孔至少包括：第十过孔V10、第十一过孔V11、第十三过孔V13和第十四过孔V14，第三导电层至少包括补偿线43、第二电源线44、第二电容极板45和第三连接电极48，第三连接电极48通过第十过孔V10与第二有源层22连接，第二电容极板45通过第十一过孔V11、第十三过孔V13和第十四过孔V14分别与第二有源层22、第三有源层23和遮挡层11连接。
(6)形成第四绝缘层和第一平坦层图案。在示例性实施例中，形成第四绝缘层和第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第四绝缘薄膜，然后涂覆平坦薄膜，通过图案化工艺对平坦薄膜和第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层以及设置在第四绝缘层上的平坦层，第四绝缘层和平坦层上开设有阳极过孔K1和电极过孔K2图案，如图11a和图11b所示，图11b为图11a中A-A向的剖视图。
如图11a所示，在示例性实施例中，阳极过孔K1设置在每个子像素中，阳极过孔K1内的平坦层和第四绝缘层被去掉，暴露出第二电容极板45的表面。电极过孔K2设置在相邻两个像素单元的第三子像素P3之间，电极过孔K2内的平坦层和第四绝缘层被去掉，暴露出第二电源线44的表面。
在示例性实施例中，阳极过孔K1和电极过孔K2均可以包括设置在平坦层95上的大孔和设置在第四绝缘层94上的小孔，小孔设置在大孔内。
如图11b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体 层，第二绝缘层92，设置在第二绝缘层92上的第二导电层，覆盖第二导电层的第三绝缘层93，设置在第三绝缘层93上的第三导电层，覆盖第三绝缘层93的第四绝缘层94，以及覆盖第四绝缘层94的平坦层95。第四绝缘层94和平坦层95上设置有阳极过孔K1和电极过孔K2，阳极过孔K1暴露出第二电容极板45，电极过孔K2暴露出第二电源线44。
至此，在基底上制备完成驱动电路层图案。在示例性实施方式中，每个子像素的驱动电路层至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，第二绝缘层称为栅绝缘(GI)层，第三绝缘层称为层间绝缘(ILD)层，第四绝缘层称为钝化(PVX)层。平坦薄膜可以采用有机材料，如树脂等。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
(7)形成第一透明导电层图案。在示例性实施方式中，形成第一透明导电层图案可以包括：在形成前述图案的基底上沉积第一透明导电薄膜，通过图案化工艺对第一透明导电薄膜进行图案化，形成第一透明导电层图案，第一透明导电层图案至少包括第一阳极51和第一辅助电极61，如图12a和图12b所示，图12b为图12a中A-A向的剖视图。
在示例性实施方式中，第一阳极51设置在平坦层上，通过阳极过孔K1与第二电容极板连接。第一辅助电极61设置在平坦层上，通过电极过孔K2与第二电源线44连接。
在示例性实施方式中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
在示例性实施方式中，在平行于显示基板的平面上，第一辅助电极的形状可以是如下任意一种多种：三角形、矩形、梯形、多边形、圆形和椭圆形，三角形、矩形、梯形、多边形的边缘可以是直线，或者可以是曲线，第一辅助电极的角部可以设置成弧形倒角，本公开在此不做限定。
在示例性实施方式中，在平行于显示基板的平面上，显示基板可以包括多个像素单元，多个像素单元分别沿第一方向D1和第二方向D2依次设置，第一辅助电极61可以设置在第一方向D1上相邻的两个像素单元之间，使得两个像素单元中的多个子像素共用一个辅助电极。
在示例性实施方式中，相邻的两个像素单元中，第一像素单元可以包括沿第一方向D1依次设置的第一子像素P1、第二子像素P2和第三子像素P3，第二像素单元可以包括沿第一方向D1的反方向依次设置的第一子像素P1、第二子像素P2和第三子像素P3，即在第一方向D1上，两个像素单元的第三子像素P3相邻。在示例性实施方式中，第一辅助电极61可以设置在相邻的两个第三子像素P3之间。
在示例性实施方式中，两个像素单元中第一子像素P1和第二子像素P2中第一阳极的形状可以是矩形，与所在子像素形状相近。
在示例性实施方式中，在第二方向D2上，第一像素单元(左侧)中第三子像素P3的第一阳极具有第一端部和第二端部，第一端部在第一方向D1上的尺寸小于第二端部在第一方向D1上的尺寸。在第一方向D1上，第二端部与第二像素单元的距离小于第一端部与第二像素单元的距离。
在示例性实施方式中，在第二方向D2上，第二像素单元(右侧)中第三子像素P3的第一阳极具有第三端部和第四端部，第三端部在第一方向D1上的尺寸小于第四端部在第一方向D1上的尺寸。在第一方向D1上，第四端部与第一像素单元的距离小于第三端部与第一像素单元的距离。
在示例性实施方式中，第一辅助电极61设置在第一端部和第三端部之间。
两个像素单元中第三子像素P3中第一阳极的形状可以是具有凹槽K的矩形，矩形与第三子像素P3的形状相近，凹槽K设置在第一阳极51靠近第一辅助电极61的一侧。
在示例性实施方式中，第一像素单元(左侧)的第三子像素P3中包括具有第一凹槽的第一阳极，第二像素单元(右侧)的第三子像素P3中包括具有第二凹槽的第一阳极，第一辅助电极设置在具有第一凹槽的第一阳极与具有第二凹槽的第一阳极之间。
在示例性实施方式中，第一像素单元(左侧)的第三子像素P3中，第一凹槽设置在第一阳极靠近第二像素单元的一侧，第二像素单元(右侧)的第三子像素P3中，第二凹槽设置在第一阳极靠近第一像素单元的一侧，使两个像素单元中相邻的第三子像素P3之间形成一个容置区域，第一辅助电极61设置在该容置区域内。
如图12b所示，本次工艺后，显示基板包括设置在基底10上的第一导电层，覆盖第一导电层的第一绝缘层91，设置在第一绝缘层91上的半导体层，第二绝缘层92，设置在第二绝缘层92上的第二导电层，覆盖第二导电层的第三绝缘层93，设置在第三绝缘层93上的第三导电层，覆盖第三绝缘层93的第四绝缘层94，覆盖第四绝缘层94的平坦层95，以及设置在平坦层95上的第一透明导电层，第一透明导电层至少包括第一阳极51和第一辅助电极61，第一阳极51通过阳极过孔K1与第二电容极板45连接，第一辅助电极61通过电极过孔K2与第二电源线44连接。
(8)形成阳极和辅助电极图案。在示例性实施方式中，形成阳极和辅助电极图案可以包括：在形成前述图案的基底上依次沉积第四金属薄膜和第二透明导电薄膜，通过图案化工艺对第四金属薄膜和第二透明导电薄膜进行图案化，形成第二阳极52、第三阳极53、第二辅助电极62和第三辅助电极63图案，第二阳极52设置在第一阳极51远离基底的一侧并与第一阳极51连接，第三阳极53设置在第二阳极52远离基底的一侧并与第二阳极52连接，第二辅助电极62设置在第一辅助电极61远离基底的一侧并与第一辅助电极61连接，第三辅助电极63设置在第二辅助电极62远离基底的一侧并与第二辅助电极62连接。叠设的第一阳极51、第二阳极52和第三阳极53组成阳极 50，叠设的第一辅助电极61、第二辅助电极62和第三辅助电极63组成辅助电极60，如图13所示。
在示例性实施方式中，在平行于显示基板的平面内，第二阳极52和第三阳极53的形状与第一阳极51的形状相似，第二阳极52在基底上的正投影可以位于第一阳极51在基底上的正投影的范围之内，第二阳极52在基底上的正投影可以位于第三阳极53在基底上的正投影的范围之内。在平行于显示基板的平面内，第二辅助电极62和第三辅助电极63的形状与第一辅助电极61的形状相似，第二辅助电极62在基底上的正投影可以位于第一辅助电极61在基底上的正投影的范围之内，第二辅助电极62在基底上的正投影可以位于第三辅助电极63在基底上的正投影的范围之内。
图14为本发明示例性实施例辅助电极的剖面示意图，为图13中辅助电极的放大图。如图14所示，在垂直于显示基板的平面内，位于第二辅助电极62邻近基底一侧(下侧)的第一辅助电极61具有凸出第二辅助电极62轮廓的边缘，形成一个“屋座”结构，位于第二辅助电极62远离基底一侧(上侧)的第三辅助电极63具有凸出第二辅助电极62轮廓的边缘，第一辅助电极61和第三辅助电极63形成一个“屋檐”结构，使得叠设的第一辅助电极61、第二辅助电极62和第三辅助电极63构成“工”字形。
在示例性实施方式中，位于第二阳极52邻近基底一侧(下侧)的第一阳极51具有凸出第二阳极52轮廓的边缘，形成一个“屋座”结构，位于第二阳极52远离基底一侧(上侧)的第三阳极53具有凸出第二阳极52轮廓的边缘，形成一个“屋檐”结构，使得叠设的第一阳极51、第二阳极52和第三阳极53构成“工”字形。
在示例性实施方式中，对第四金属薄膜和第二透明导电薄膜进行图案化过程中，可以采用第一刻蚀液和第二刻蚀液分别进行刻蚀，利用钻刻形成辅助电极和阳极的“工”字形结构。在示例性实施方式中，第一刻蚀液可以采用刻蚀透明导电材料的刻蚀液(ITO刻蚀液)，第二刻蚀液可以采用刻蚀金属材料的刻蚀液(Metal刻蚀液)。在示例性实施方式中，经过光刻胶的掩膜、曝光和显影，形成光刻胶图案后，刻蚀过程可以包括：先采用ITO刻蚀液刻蚀未被光刻胶覆盖的第二透明导电薄膜，使未被光刻胶覆盖的区域暴露出第 四金属薄膜，形成第三阳极53和第三辅助电极63图案。随后采用Metal刻蚀液刻蚀暴露出的第四金属薄膜，形成第二阳极52和第二辅助电极62图案。由于Metal刻蚀液刻蚀第四金属薄膜的速率大于刻蚀第一透明导电薄膜和第二透明导电薄膜的速率，因而将第二阳极52和第二辅助电极62的侧面刻蚀成凹坑。第二阳极52下方的第一阳极51和第二阳极52上方的第三阳极53均凸出第二阳极52一段距离，第二辅助电极62下方的第一辅助电极61和第二辅助电极62上方的第三辅助电极63凸出第二辅助电极62一段距离，形成“工”字形结构。
如图14所示，在垂直于显示基板的平面上，所形成的辅助电极具有多个暴露的表面，这些暴露的表面分别包括：第一辅助电极61凸出第二辅助电极62部分远离基底一侧的表面第一上表面611，第二辅助电极62侧部的第二侧表面621，第三辅助电极63上侧(远离基底一侧)的第三上表面631，第三辅助电极63侧部的第三侧表面632，第三辅助电极63下侧(邻近基底一侧)的第三下表面633，第三下表面633是指第三辅助电极63凸出第二辅助电极62部分邻近基底一侧的表面。在示例性实施方式中，前述的侧表面是指法线方向与基底平面平行或接近平行的、周向的多个表面，例如，在平行于基底的平面内，矩形状第二辅助电极62的第二侧表面621包括周向的四个表面。
在示例性实施方式中，第四金属薄膜材料可以包括银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，第二透明导电材料可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
(9)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义(PDL)层71图案，像素定义层71上开设有第一像素开口K3和第二像素开口K4，第一像素开口K3内的像素定义层71被去掉，暴露出阳极中第三阳极53的部分表面，第二像素开口K4内的像素定义层71被去掉，暴露出辅助电极中的第二辅助电极62和第三辅助电极63的全部表面，如图15a、图15b和图15c所示，图15a为像素定义层中像素开口形状的示意图，图15b为像素定义层中像素开口位置的示意图，像素定义层设置为透明，图15c为图15a和图15b中A-A向的剖视图。
在示例性实施方式中，第一像素开口K3在基底上的正投影位于第三阳极53在基底上的正投影的范围之内，第二像素开口K4在基底上的正投影位于第一辅助电极61在基底上的正投影的范围之内，第二辅助电极62和第三辅助电极63在基底上的正投影位于第二像素开口K4在基底上的正投影的范围之内。第二像素开口K4暴露出第二辅助电极62和第三辅助电极63的全部表面是指，第二像素开口具有邻近基底一侧的第二下开口和远离基底一侧的第二上开口，第二辅助电极62和第三辅助电极63在基底上的正投影位于第二下开口在基底上的正投影的范围之内。
在示例性实施方式中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。在平行于显示基板的平面内，第一像素开口K3的形状可以是椭圆形，第二像素开口K4的形状可以是矩形。在垂直于显示基板的平面内，第一像素开口K3和第二像素开口K4的截面形状可以是矩形或者梯形等。
(10)形成有机发光层图案。在示例性实施方式中，形成有机发光层图案可以包括：在形成前述图案的基底上蒸镀有机发光材料，形成有机发光层72和有机发光块73图案，有机发光层72设置在第三辅助电极63以外的区域，有机发光层72通过第一像素开口K3与阳极50中第三阳极53连接，有机发光块73设置在第三辅助电极63远离基底一侧的表面上，有机发光块73与有机发光层72隔离设置，如图16所示。
在示例性实施方式中，由于辅助电极的“工”字形结构，第三辅助电极63凸出第二辅助电极62一段距离，因而有机发光材料在第三辅助电极63的侧面边缘处断开，在第三辅助电极63的第二上表面631上形成有机发光块73，在第三辅助电极63以外区域形成有机发光层72，实现了有机发光层72与有机发光块73的相互隔离。在示例性实施方式中，有机发光块73在基底上的正投影可以约等于第三辅助电极63在基底上的正投影。通过“工”字形结构的辅助电极隔断有机发光层，形成孤立并隔离的有机发光块，有效避免了有机发光块对出射光的干扰，提高了出射光的品质，有利于提高显示品质。
在示例性实施方式中，有机发光层72通过第一像素开口K3与第三阳极53连接，因而实现了有机发光层72与阳极50的连接。位于第二像素开口 K4区域的有机发光层72，一部分覆盖第二像素开口K4的侧壁，另一部分覆盖第二像素开口K4的部分底面，并在第二像素开口K4的底面上形成斜坡。在示例性实施方式中，位于第二像素开口K4底面上的有机发光层72与第二辅助电极62相距一定距离，有机发光层72与第二辅助电极62之间区域暴露出第一辅助电极61。
在示例性实施方式中，有机发光层可以包括发光层(Emitting Layer，简称EML)，以及如下任意一层或多层：空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，有机发光层可以采用精细金属掩模版(Fine Metal Mask，简称FMM)或者开放式掩膜版(Open Mask)蒸镀形成，或者采用喷墨工艺形成。
在示例性实施方式中，可以采用如下制备方法制备有机发光层。先采用开放式掩膜版依次蒸镀空穴注入层和空穴传输层，在显示基板上形成空穴注入层和空穴传输层的共通层。随后，采用精细金属掩模版在红色子像素蒸镀电子阻挡层和红色发光层，在绿色子像素蒸镀电子阻挡层和绿色发光层，在蓝色子像素蒸镀电子阻挡层和蓝色发光层，相邻子像素的电子阻挡层和发光层可以有少量的交叠(例如，交叠部分占各自发光层图案的面积小于10％)，或者可以是隔离的。随后，采用开放式掩膜版依次蒸镀空穴阻挡层、电子传输层和电子注入层，在显示基板上形成空穴阻挡层、电子传输层和电子注入层的共通层。
在示例性实施方式中，电子阻挡层可以作为发光器件的微腔调节层，通过设计电子阻挡层的厚度，可以使得阴极和阳极之间有机发光层的厚度满足微腔长度的设计。在一些示例性实施方式中，可以采用有机发光层中的空穴传输层、空穴阻挡层或电子传输层作为发光器件的微腔调节层，本公开在此不做限定。
在示例性实施方式中，发光层可以包括主体(Host)材料和掺杂在主体材料中的客体(Dopant)材料，发光层客体材料的掺杂比例为1％至20％。 在该掺杂比例范围内，一方面发光层主体材料可将激子能量有效转移给发光层客体材料来激发发光层客体材料发光，另一方面发光层主体材料对发光层客体材料进行了“稀释”，有效改善了发光层客体材料分子间相互碰撞、以及能量间相互碰撞引起的荧光淬灭，提高了发光效率和器件寿命。在示例性实施方式中，掺杂比例是指客体材料的质量与发光层的质量之比，即质量百分比。在示例性实施方式中，可以通过多源蒸镀工艺共同蒸镀主体材料和客体材料，使主体材料和客体材料均匀分散在发光层中，可以在蒸镀过程中通过控制客体材料的蒸镀速率来调控掺杂比例，或者通过控制主体材料和客体材料的蒸镀速率比来调控掺杂比例。在示例性实施方式中，发光层的厚度可以约为10nm至50nm。
在示例性实施方式中，空穴注入层可以采用无机的氧化物，如钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物或锰氧化物，或者可以采用强吸电子体系的p型掺杂剂和空穴传输材料的掺杂物。在示例性实施方式中，空穴注入层的厚度可以约为5nm至20nm。
在示例性实施方式中，在示例性实施方式中，空穴传输层可以采用空穴迁移率较高的材料，如芳胺类化合物，其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中，空穴传输层的厚度可以约为40nm至150nm。
在示例性实施方式中，空穴阻挡层和电子传输层可以采用芳族杂环化合物，例如苯并咪唑衍生物、咪唑并吡啶衍生物、苯并咪唑并菲啶衍生物等咪唑衍生物；嘧啶衍生物、三嗪衍生物等嗪衍生物；喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等包含含氮六元环结构的化合物(也包括在杂环上具有氧化膦系的取代基的化合物)等。在示例性实施方式中，空穴阻挡层的厚度可以约为5nm至15nm，电子传输层的厚度可以约为20nm至50nm。
在示例性实施方式中，电子注入层可以采用碱金属或者金属，例如氟化锂(LiF)、镱(Yb)、镁(Mg)或钙(Ca)等材料，或者这些碱金属或者金属的化合物等。在示例性实施方式中，电子注入层的厚度可以约为0.5nm至2nm。
(11)形成阴极图案。在示例性实施方式中，形成阴极图案可以包括：在形成前述图案的基底上蒸镀阴极材料，形成阴极80图案，阴极80与有机发光层72连接，并通过包裹有机发光块73和辅助电极60的方式实现与辅助电极60的大面积接触连接，如17所示。
在示例性实施方式中，阴极80可以是连通在一起的整体结构。在辅助电极60以外区域，阴极80设置在有机发光层72上。在辅助电极60所在区域，阴极80一方面设置在有机发光块73暴露的表面上，另一方面设置在辅助电极暴露的表面上，形成包裹辅助电极60和有机发光块73的结构。
如图14和图17所示，对于有机发光块73，一部分阴极80覆盖或部分覆盖有机发光块73远离基底一侧的表面上，另一部分阴极80覆盖或部分覆盖或部分覆盖有机发光块73的侧表面。对于第三辅助电极63，有机发光块73覆盖或部分覆盖第三辅助电极63远离基底一侧的表面，一部分阴极80覆盖或部分覆盖第三辅助电极63的第二侧表面632，另一部分阴极80覆盖或部分覆盖第三辅助电极63下侧的第二下表面633，即阴极80覆盖或部分覆盖第三辅助电极63凸出第二辅助电极62部分的下表面。这样，不仅实现了阴极80与第三辅助电极63的连接，而且实现了对有机发光块73的包裹。由于阴极80与第三辅助电极63通过第三侧表面632和第三下表面633连接，因而有机发光块73上侧的阴极80与有机发光块73下侧的第三辅助电极63的电位相等，即有机发光块73上下两侧的电位相等，保证了有机发光块73不会发光，避免了因有机发光块73发光导致的闪烁现象。对于第二辅助电极62，阴极80覆盖或部分覆盖在第二辅助电极62侧部的第二侧表面621。对于第一辅助电极61，阴极80覆盖或部分覆盖有机发光层72与第二辅助电极62之间暴露出的第一辅助电极61。
本公开示例性实施例通过阴极与第二辅助电极的侧表面接触连接，有效增加了阴极与辅助电极的接触面积，有效降低了接触界面处的电阻，提高了显示效果。
至此，在驱动电路层上制备完成发光结构层图案，发光结构层包括阳极、辅助电极、像素定义层、有机发光层和阴极，有机发光层分别与阳极和阴极连接，阴极与辅助电极连接，辅助电极与第二电源线连接。
在示例性实施方式中，显示基板的制备过程可以包括形成封装层图案，形成封装层图案可以包括：先利用开放式掩膜板采用等离子体增强化学气相沉积(PECVD)方式沉积第一无机薄膜，形成第一封装层。随后，利用喷墨打印工艺在第一封装层上喷墨打印有机材料，固化成膜后，形成第二封装层。随后，利用开放式掩膜板沉积第二无机薄膜，形成第三封装层，第一封装层、第二封装层和第三封装层组成封装层。在示例性实施例中，第一封装层和第三封装层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第二封装层可以采用树脂材料，形成无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，制备完成封装层后，可以在封装层上形成触摸结构层(TSP)，触摸结构层可以包括触控电极层，或者包括触控电极层和触控绝缘层。
在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程可以包括剥离玻璃载板、贴附背膜、切割等工艺，本公开在此不作限定。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，在垂直于显示基板的平面内，本公开示例性实施例通过将辅助电极的剖面形状设置成“工”字形，将有机发光层在辅助电极的边缘处断开，使得辅助电极上方的有机发光块隔离，可以避免有机发光块对出射光的干扰，提高了出射光的品质，有利于提高显示品质。在垂直于显示基板的平面内，本公开示例性实施例通过将辅助电极中第三辅助电极设置成凸出于第二辅助电极，且阴极与第三辅助电极连接，实现了有机发光块两侧的电位相同，保证了有机发光块不会发光，避免了因有机发光块发光导致的闪烁现象。本公开示例性实施例通过设置阴极与辅助电极的侧面接触连接，有效增加了阴极与辅助电极的接触面积，有效降低了接触界面处的电阻，提高了显示效果。由于本公开示例性实施例显示基板的制备方法没有采用激光开孔工艺，不仅缩短了单件产品生产时间，而且制备过程不会产生颗粒，因而提高了生产效率和产品良率。本公开示例性实施例显示基板的制备方法具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在示例性实施方式中，显示基板可以采用另一种制备方法制备。显示基板的另一种制备过程可以包括如下操作。
(21)制备基底和驱动电路层的过程与前述实施例中制备基底和驱动电路层的过程相同，这里不再赘述。
(22)形成第一透明导电层和第四金属层图案。在示例性实施方式中，形成第一透明导电层和第四金属层图案可以包括：在形成前述图案的基底上依次沉积第一透明导电薄膜和第四金属薄膜，通过图案化工艺对第一透明导电薄膜和第四金属薄膜进行图案化，形成第一透明导电层和第四金属层图案。在示例性实施方式中，第一导电层图案至少包括第一阳极51和第一辅助电极61。第一阳极51通过阳极过孔与第二电容极板45连接，第一辅助电极61通过电极过孔与第二电源线44连接。第四金属层至少包括第二阳极52和第二辅助电极62，第二阳极52设置在第一阳极51远离基底的一侧并与第一阳极51连接，第二辅助电极62设置在第一辅助电极61远离基底的一侧并与第一辅助电极61连接，如图18所示。
在示例性实施方式中，可以采用半色调或灰色调掩膜板的图案化工艺对第一透明导电薄膜和第四金属薄膜进行图案化。例如，图案化可以包括：在第四金属薄膜上涂覆一层正性光刻胶，利用半色调或灰色调掩膜板对光刻胶进行曝光，使光刻胶形成完全曝光区域、部分曝光区域和未曝光区域。随后进行显影处理，未曝光区域的光刻胶被保留，光刻胶具有第一厚度，部分曝光区域部分厚度的光刻胶被去除，光刻胶具有第二厚度，第二厚度小于第一厚度，完全曝光区域的全部光刻胶被去除，暴露出第四金属薄膜的表面。随后进行第一次刻蚀处理，刻蚀掉完全曝光区域的第一透明导电薄膜和第四金属薄膜，形成第一阳极51和第一辅助电极61图案。随后进行灰化处理，去除部分曝光区域第二厚度的光刻胶，暴露出第四金属薄膜的表面。随后进行第二次刻蚀处理，刻蚀掉部分曝光区域的第四金属薄膜，形成第二阳极52和第二辅助电极62图案。
(23)形成第三阳极和第三辅助电极图案。在示例性实施方式中，形成第三阳极和第三辅助电极图案可以包括：在形成前述图案的基底上沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行图案化，形成第三 阳极53和第三辅助电极63图案，第三阳极53设置在第二阳极52远离基底的一侧并与第二阳极52连接，第三辅助电极63设置在第二辅助电极62远离基底的一侧并与第二辅助电极62连接。叠设的第一阳极51、第二阳极52和第三阳极53组成阳极50，叠设的第一辅助电极61、第二辅助电极62和第三辅助电极63组成辅助电极60，如图13所示。
在示例性实施方式中，对第二透明导电薄膜进行图案化过程中，可以采用第一刻蚀液和第二刻蚀液分别进行刻蚀，利用钻刻形成辅助电极的“工”字形和阳极的“工”字形结构。在示例性实施方式中，第一刻蚀液可以采用刻蚀透明导电材料的刻蚀液(ITO刻蚀液)，第二刻蚀液可以采用刻蚀金属材料的刻蚀液(Metal刻蚀液)。在示例性实施方式中，刻蚀过程可以包括：先采用ITO刻蚀液刻蚀第二透明导电薄膜，形成第三阳极53和第三辅助电极63图案。随后采用Metal刻蚀液继续刻蚀。由于Metal刻蚀液刻蚀第二阳极52和第二辅助电极62的速率大于刻蚀第三阳极53和第三辅助电极63的速率，因而将第二阳极52和第二辅助电极62的侧面刻蚀成凹坑。第二阳极52下方的第一阳极51和第二阳极52上方的第三阳极53均凸出第二阳极52一段距离，形成“工”字形结构。第二辅助电极62下方的第一辅助电极61和第二辅助电极62上方的第三辅助电极63凸出第二辅助电极62一段距离，形成“工”字形结构。
(24)形成像素定义层、有机发光层、阴极等过程与前述实施例相同，这里不再赘述。
如图5～图18所示，通过前述制备过程制备的显示基板可以包括：基底10；设置在基底10上的第一导电层，第一导电层至少包括遮挡层11；覆盖第一导电层的第一绝缘层91；设置在第一绝缘层91上的半导体层，半导体层至少包括第一电容极板24和多个晶体管的有源层；设置在半导体层上的第二绝缘层92；设置在第二绝缘层92上的第二导电层，第二导电层至少包括多个晶体管的栅电极；覆盖第二导电层的第三绝缘层93；设置在第三绝缘层93上的第三导电层，第三导电层至少包括第二电源线44、第二电容极板45和多个晶体管的第一极和第二极，第二电容极板45通过过孔与遮挡层11连接，第二电容极板45和第一电容极板24形成第一存储电容，遮挡层11 和第一电容极板24形成第二存储电容；覆盖第三导电层的第四绝缘层94；设置在第四绝缘层94上的平坦层95；设置在平坦层95上的阳极50和辅助电极60，阳极50包括叠设并形成“工”字形结构的第一阳极51、第二阳极52和第三阳极53，辅助电极60包括叠设并形成“工”字形结构的第一辅助电极61、第二辅助电极62和第三辅助电极63；设置在平坦层95上的像素定义层71，其上开设有第一像素开口和第二像素开口，第一像素开口暴露出第三阳极53，第二像素开口暴露出第二辅助电极62和第三辅助电极63；设置在像素定义层71上的有机发光层72和设置在第三辅助电极63上的有机发光块73，有机发光层72通过第一像素开口与第三阳极53连接，有机发光块73与有机发光层72隔离设置；设置在有机发光层72上的阴极80，阴极80与有机发光层72连接，并通过包裹有机发光块73和辅助电极40的方式实现与辅助电极40的大面积接触连接；设置在阴极80上的封装层，封装层包括叠设的第一封装层、第二封装层和第三封装层。
本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺。例如，驱动电路层中的晶体管可以是顶栅结构。又如，驱动电路层和发光结构层中还可以设置其它膜层结构、电极结构或引线结构。再如，基底可以是玻璃基底，本公开在此不做具体的限定。
本公开还提供了一种显示基板的制备方法。在示例性实施方式中，所述制备方法可以包括：
在基底上形成驱动电路层；
在所述驱动电路层上形成发光结构层，所述发光结构层包括阳极、有机发光层、有机发光块、阴极和辅助电极，所述有机发光层分别与所述阳极和阴极连接，所述辅助电极包括靠近所述基底一侧的底面、远离所述基底一侧的顶面以及设置在所述底面与顶面之间的侧面，所述阴极与所述辅助电极的侧面接触，所述有机发光块设置在所述辅助电极的顶面远离所述基底的一侧，所述有机发光块与所述有机发光层隔离设置。
本公开提供了一种显示基板的制备方法，通过将辅助电极的剖面形状设置成“工”字形，使有机发光层在辅助电极的边缘处断开，与位于辅助电极上 方的有机发光块隔离，可以避免有机发光块对出射光的干扰，提高了出射光的品质，有利于提高显示品质。通过将辅助电极中第三辅助电极设置成凸出于第二辅助电极，且阴极与第三辅助电极连接，实现了有机发光块两侧的电位相同，保证了有机发光块不会发光，避免了因有机发光块发光导致的闪烁现象。本公开示例性实施例通过设置阴极与辅助电极的侧面接触连接，有效增加了阴极与辅助电极的接触面积，有效降低了接触界面处的电阻，提高了显示效果。由于本公开制备方法没有采用激光开孔工艺，不仅缩短了单件产品生产时间，而且制备过程不会产生颗粒，因而提高了生产效率和产品良率。本公开示例性实施例显示基板的制备方法具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种显示基板，包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述发光结构层包括沿远离基底的方向依次设置的阳极、像素定义层、有机发光层和阴极，以及沿远离基底的方向依次设置的辅助电极和有机发光块，所述像素定义层包括阳极开口和电极开口，所述阳极开口暴露出所述阳极，所述电极开口暴露出所述辅助电极，所述有机发光块与所述有机发光层分离，所述辅助电极包括第一辅助电极、位于所述第一辅助电极远离基底一侧的第二辅助电极以及位于所述第二辅助电极远离基底一侧的第三辅助电极；
    所述阴极包括第一水平搭接部和第二侧壁搭接部，所述第一水平搭接部与第一辅助电极搭接，所述第二侧壁搭接部与第二辅助电极搭接，所述第二侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底方向的厚度。
  2. 根据权利要求1所述的显示基板，其中，所述第二侧壁搭接部与所述第一辅助电极连接，所述第二侧壁搭接部与所述第三辅助电极靠近基底的表面接触，所述第二侧壁搭接部与第一水平搭接部连接。
  3. 根据权利要求1所述的显示基板，其中，在所述第一辅助电极远离所述基底的一侧设置有所述有机发光层，所述有机发光层与所述第二辅助电极分离，所述阴极还包括第一侧壁搭接部，所述第一侧壁搭接部与所述有机发光层的侧面搭接，所述阴极还与所述有机发光层远离基底的一侧搭接。
  4. 根据权利要求3所述的显示基板，其中，所述阴极还包括第二水平搭接部和第三搭接部，所述第二水平搭接部与所述第三辅助电极凸出第二辅助电极部分邻近所述基底一侧的表面搭接，所述第三搭接部与所述有机发光块远离基底一侧的表面和侧面以及所述第三辅助电极的侧面搭接，所述第二水平搭接部与第三搭接部连接。
  5. 根据权利要求4所述的显示基板，其中，所述第三搭接部在垂直于基底方向的厚度大于所述第二侧壁搭接部在平行于基底方向的厚度，所述第一侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底 方向的厚度。
  6. 根据权利要求2所述的显示基板，其中，所述第二侧壁搭接部在平行于基底方向上的厚度为500埃米至3000埃米，所述第一水平搭接部在垂直于基底方向上的厚度为100埃米至1500埃米。
  7. 根据权利要求1所述的显示基板，其中，第二辅助电极包括靠近基底的底面和远离基底的顶面，以及在顶面和底面之间的侧面，在垂直于基底的平面内，所述第二辅助电极的侧面与所述第二辅助电极的底面形成的角度小于90°。
  8. 根据权利要求1所述的显示基板，其中，所述阳极包括第一阳极层、设置在所述第一阳极层远离所述基底一侧的第二阳极层以及设置在所述第二阳极层远离所述基底一侧的第三阳极层，所述第二阳极层在基底上的正投影位于所述第一阳极层在基底上的正投影的范围之内，所述第二阳极层在基底上的正投影位于所述第三阳极层在基底上的正投影的范围之内。
  9. 根据权利要求8所述的显示基板，其中，所述第一阳极层与所述第一辅助电极同层设置，且材料相同；所述第二阳极层与所述第二辅助电极同层设置，且材料相同；所述第三阳极层与所述第三辅助电极同层设置，且材料相同。
  10. 根据权利要求8所述的显示基板，其中，所述第一阳极层在第二方向上具有第一端部和第二端部，所述第二阳极层具有第三端部和第四端部，所述第一端部在第一方向上的尺寸小于所述第二端部在所述第一方向上的尺寸，所述第三端部在所述第一方向上的尺寸小于所述第四端部在所述第一方向上的尺寸，所述辅助电极设置在所述第一端部和第三端部之间，所述第一方向与第二方向相交。
  11. 根据权利要求10所述的显示基板，其中，所述第一阳极层在所述第一方向上具有比所述第一端部更靠近第二像素单元的部分；所述第二阳极层在所述第一方向上具有比所述第三端部更靠近第一像素单元的部分，所述第一像素单元和所述第二像素单元相邻。
  12. 根据权利要求1至11任一项所述的显示基板，其中，所述驱动电路 层包括：设置在基底上的晶体管和电源电极、设置在所述晶体管和电源电极远离基底的一侧的钝化层，设置在所述钝化层远离基底的一侧的平坦层，所述平坦层上具有阳极过孔和电极过孔，所述电源电极与所述晶体管中的漏电极同层设置；所述钝化层上具有第一过孔和第二过孔，所述第一过孔暴露出所述晶体管的漏电极，所述第二过孔暴露出所述电源电极；所述阳极过孔暴露出所述第一过孔，所述电极过孔暴露出所述第二过孔。
  13. 根据权利要求12所述的显示基板，其中，所述第一辅助电极通过所述电极过孔和第二过孔与所述电源电极连接，所述第二辅助电极与所述第一辅助电极直接接触，所述第二辅助电极在基底上的正投影位于所述第三辅助电极在基底上的正投影的范围内，所述第二辅助电极在基底上的正投影位于所述第一辅助电极在基底上的正投影范围内。
  14. 根据权利要求12所述的显示基板，其中，所述第二过孔在基底上的正投影位于所述电极过孔在基底上的正投影范围内，所述第二过孔在基底上的正投影位于所述第三辅助电极在基底上的正投影范围内。
  15. 根据权利要求1所述的显示基板，其中，所述电极开口在基底上的正投影位于所述第一辅助电极在基底上的正投影的范围之内。
  16. 根据权利要求1所述的显示基板，其中，多个所述阳极沿第一方向排列成行，同一行的所述阳极对应的阳极过孔设置在沿第一方向延伸的同一条直线上，至少一个连接电极对应的电极过孔在第二方向与所述阳极过孔交叠，所述第二方向与第一方向相交。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层；
    在所述驱动电路层上形成发光结构层，所述发光结构层包括沿远离基底的方向依次设置的阳极、像素定义层、有机发光层和阴极，以及沿远离基底的方向依次设置的辅助电极和有机发光块，所述像素定义层包括阳极开口和电极开口，所述阳极开口暴露出所述阳极，所述电极开口暴露出所述辅助电极，所述有机发光块与所述有机发光层分离，所述辅助电极包括第一辅助电 极、位于所述第一辅助电极远离基底一侧的第二辅助电极以及位于所述第二辅助电极远离基底一侧的第三辅助电极；所述阴极包括第一水平搭接部和第二侧壁搭接部，所述第一水平搭接部与第一辅助电极搭接，所述第二侧壁搭接部与第二辅助电极搭接，所述第二侧壁搭接部在平行于基底方向的厚度大于所述第一水平搭接部在垂直于基底方向的厚度。
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