WO2023137766A1 - 显示面板、显示模组及显示装置 - Google Patents

显示面板、显示模组及显示装置 Download PDF

Info

Publication number
WO2023137766A1
WO2023137766A1 PCT/CN2022/073590 CN2022073590W WO2023137766A1 WO 2023137766 A1 WO2023137766 A1 WO 2023137766A1 CN 2022073590 W CN2022073590 W CN 2022073590W WO 2023137766 A1 WO2023137766 A1 WO 2023137766A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
electrically connected
initial signal
display panel
transistor
Prior art date
Application number
PCT/CN2022/073590
Other languages
English (en)
French (fr)
Inventor
肖邦清
杜丽丽
杨妮
王明慧
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000058.9A priority Critical patent/CN117280889A/zh
Priority to PCT/CN2022/073590 priority patent/WO2023137766A1/zh
Publication of WO2023137766A1 publication Critical patent/WO2023137766A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display panel, a display module and a display device.
  • Full Display with Camera (FDC for short) with a camera has been gradually applied to display products due to its advantages of a larger screen-to-body ratio.
  • optical components such as a camera are usually placed in the under-screen area of the display panel, which greatly increases the screen-to-body ratio.
  • a display panel which has a main display area and an auxiliary display area; the display panel includes: a plurality of pixel circuits located in the main display area; the plurality of pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits; a plurality of light emitting devices, including a plurality of first light emitting devices located in the main display area and a plurality of second light emitting devices located in the auxiliary display area; the plurality of first pixel circuits are respectively electrically connected to the plurality of first light emitting devices, and the plurality of second pixel circuits are respectively electrically connected to the plurality of second light emitting devices; The circuit is electrically connected to the first initial signal line and the first light emitting device, and is configured to transmit the first initial signal transmitted by the first initial signal line to the first light emitting device, and reset the first light emitting device; the first reset transistor of the second pixel circuit is electrically connected to the second initial signal line and the second light emitting device,
  • the display panel further includes: a plurality of connection lines.
  • a second pixel circuit is electrically connected to a second light-emitting device through a connection line; the material of the plurality of connection lines includes light-permeable conductive material.
  • the difference between the voltage value of the second initial signal and the voltage value of the first initial signal is positively correlated with the length of the connecting line.
  • the display panel includes: a plurality of light emitting device columns arranged in sequence along the first direction; the light emitting device column includes a plurality of first light emitting devices located in the main display area and a plurality of second light emitting devices located in the auxiliary display area arranged in sequence along the second direction; the display panel further includes: a plurality of data lines extending along the second direction; the first direction intersects the second direction; Wire connection.
  • the part of the data line electrically connected to the plurality of second pixel circuits is located in the main display area.
  • a plurality of second pixel circuits electrically connected to a plurality of second light-emitting devices in the light-emitting device column are arranged in sequence along the second direction, and are located on one side of the auxiliary display area along the first direction;
  • the data lines include: a first sub-data line and a second sub-data line extending along the second direction and located on opposite sides of the auxiliary display area along the second direction, and a third sub-data line extending along the second direction and located on one side of the auxiliary display area along the first direction.
  • the first sub-data line and the second sub-data line are electrically connected to the plurality of first pixel circuits
  • the third sub-data line is electrically connected to the plurality of second pixel circuits.
  • the display panel includes: a substrate, and a first source-drain conductive layer and a second source-drain-gate conductive layer sequentially stacked on one side of the substrate.
  • the first sub-data line, the second sub-data line, and the third sub-data line are located in the second source-drain conductive layer, and the first transition line and the second transition line are located in the first source-drain conductive layer.
  • the pixel circuit further includes: a compensation transistor; the compensation transistor includes: an active pattern and a gate pattern stacked in sequence; the active pattern includes a first semiconductor portion, a conductor portion, and a second semiconductor portion connected in sequence, and the gate pattern includes a first sub-gate and a second sub-gate; A connected shielding block; the shielding block and the conductor part are partly arranged facing each other.
  • the shielding block is integrated with the third initial signal line.
  • the first initial signal line, the second initial signal line and the third initial signal line are arranged on the same layer.
  • the plurality of pixel circuits are arranged in rows.
  • the third initial signal line is closer to the compensation transistor electrically connected to the third initial signal line than the first initial signal line and the second initial signal line.
  • the pixel circuit further includes a second reset transistor; the first pole of the second reset transistor is electrically connected to the third initial signal line, and the second pole of the second reset transistor is electrically connected to the second pole of the compensation transistor; the display panel further includes: a reset signal line electrically connected to the control electrode of the second reset transistor; the second reset transistor is configured to transmit the third initial signal transmitted by the third initial signal line to the second pole of the compensation transistor under the control of the reset signal transmitted by the reset signal line; wherein the reset signal line is on the substrate.
  • the orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second initial signal line on the substrate; or, it is located between the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the third initial signal line on the substrate.
  • the display panel further includes: a substrate, and a first gate conductive layer and a second gate conductive layer sequentially stacked on one side of the substrate; the reset signal line is located in the first gate conductive layer; the first initial signal line, the second initial signal line, and the third initial signal line are located in the second gate conductive layer.
  • the plurality of pixel circuits are arranged in multiple rows and multiple columns; the pixel circuit further includes: a storage capacitor; the storage capacitor includes a first plate and a second plate arranged in layers; wherein, the second plates of at least two storage capacitors in the same row of pixel circuits are connected to each other and form an integrated structure.
  • the display panel further includes: a plurality of voltage signal lines extending along the second direction; one voltage signal line is electrically connected to the second plate of the storage capacitor of a column of pixel circuits.
  • the display panel further includes: a substrate, and a second gate conductive layer and a second source-drain conductive layer sequentially stacked on one side of the substrate.
  • the second electrode plate is located on the second gate conductive layer, and the plurality of voltage signal lines are located on the second source-drain conductive layer.
  • the pixel circuit further includes: a compensation transistor, and a transfer portion connecting the second pole of the compensation transistor and the first plate of the storage capacitor;
  • the display panel further includes: a first source-drain conductive layer located between the second gate conductive layer and the second source-drain conductive layer; the transfer portion is located in the first source-drain conductive layer; the orthographic projection of the transfer portion on the substrate is within the range of the orthographic projection of the voltage signal line on the substrate.
  • the display panel further includes: a first gate conductive layer disposed on the side of the second gate conductive layer away from the second source-drain conductive layer, and a first flat layer disposed between the second gate conductive layer and the second source-drain conductive layer;
  • the pixel circuit further includes: a first light emission control transistor and a second light emission control transistor; a first via hole and a second via hole are disposed on the first flat layer; the first pole of the first light emission control transistor is electrically connected to the voltage signal line through the first via hole, and the second pole of the second light emission control transistor is connected to the voltage signal line through the second via hole
  • the light emitting device is electrically connected;
  • the display panel further includes: an enabling signal line electrically connected to the control electrode of the first light emitting control transistor and the control electrode of the second light emitting control transistor; the enabling signal line is located in the first gate conductive layer; the orthographic projection of the first via hole and the second via hole on the substrate is located within the range of the orthographic projection of the
  • the display panel further includes: a plurality of scanning signal lines and a plurality of reset signal lines extending along the first direction; the pixel circuit further includes: a driving transistor, a compensation transistor, a first reset transistor, a second reset transistor, and a switch transistor.
  • the control electrode of the compensation transistor is electrically connected to the scanning signal line, the second electrode of the compensation transistor is electrically connected to the first node; the control electrode of the second reset transistor is electrically connected to the reset signal line, the first electrode of the second reset transistor is electrically connected to the third initial signal line, the second electrode of the second reset transistor is electrically connected to the first node; the second electrode of the first light emission control transistor is electrically connected to the second node;
  • the control electrode of the switching transistor is electrically connected to the scanning signal line, the first electrode of the switching transistor is electrically connected to the second node, the second electrode of the switching transistor is electrically connected to the data line; the first electrode of the second light emission control transistor is electrically connected to the third node, the first plate of the storage capacitor is electrically connected to the first node; the control electrode of the first reset transistor is electrically connected to the scanning signal line, the first electrode of the first reset transistor of the first pixel circuit is electrically connected to the first initial signal line, and the second electrode of the first reset transistor of the first
  • a display module comprising: the display panel according to any one of the above embodiments; a cover plate located on a light-emitting side of the display panel; and a protective layer located on a non-light-emitting side of the display panel.
  • a display device comprising: the display module described in the above embodiments; and an optical element located on the non-light-emitting side of the display panel of the display module, the optical element located in the auxiliary display area of the display panel.
  • FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure
  • Fig. 2 is a structural diagram of a display module according to some embodiments of the present disclosure.
  • Fig. 3a is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • Fig. 3b is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • Fig. 4a is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • Fig. 4b is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • Fig. 5 is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • FIG. 7 is an equivalent structural diagram of a first pixel circuit according to some embodiments of the present disclosure.
  • FIG. 8 is an equivalent structural diagram of a second pixel circuit according to some embodiments of the present disclosure.
  • Fig. 9 is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 10a is a top view of other film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 10b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 11a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 11b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 12a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 12b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 13a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 13b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 14a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 14b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 14c is a cross-sectional view of the top view shown in Fig. 14b along F-F' direction;
  • Figure 14d is a cross-sectional view along the G-G' direction of the top view shown in Figure 14b;
  • Fig. 15a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 15b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Figure 15c is a cross-sectional view of the top view shown in Figure 15b along the H-H' direction;
  • Figure 15d is a cross-sectional view of the top view shown in Figure 15b along the K-K' direction;
  • Figure 15e is a cross-sectional view of the top view shown in Figure 15b along the M-M' direction;
  • Fig. 16a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 16b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 17a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 17b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 18a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 18b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 19a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 19b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 20a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 20b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 21a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 21b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 22a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 22b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 23a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 23b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 24a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 24b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 25a is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 25b is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Figure 25c is a cross-sectional view along the N-N' direction of the top view shown in Figure 25b;
  • Figure 25d is a cross-sectional view of the top view shown in Figure 25b along the Q-Q' direction;
  • Fig. 26 is a top view of some film layers in a display panel according to some embodiments of the present disclosure.
  • Fig. 27a is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • Fig. 27b is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used. For example, the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined that " or “if [the stated condition or event] is detected” is optionally interpreted to mean “when it is determined that " or “in response to determining ! or “when [the stated condition or event] is detected” or “in response to detection of [the stated condition or event]”.
  • perpendicular and “equal” include both the stated situation and situations that approximate the stated situation within the range of acceptable deviation as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).
  • perpendicular includes absolute vertical and approximate vertical, wherein the acceptable deviation range of approximate vertical may also be within 5°, for example.
  • equal includes absolute equality and approximate equality, where the difference between the two that may be equal is less than or equal to 5% of either within acceptable tolerances for approximate equality, for example.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the circuit structure may be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short), or other switching devices with the same characteristics.
  • thin film transistors are used as examples for illustration.
  • the control pole of each transistor used is the gate
  • the first pole of the transistor is one of the source and the drain
  • the second pole of the transistor is the other of the source and the drain. Since the source and the drain of the transistor may be symmetrical in structure, there may be no difference in structure between the source and the drain, that is, there may be no difference in structure between the first pole and the second pole of the transistor in the embodiments of the present disclosure.
  • the transistor when the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain;
  • the transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.
  • nodes such as the first node and the second node do not represent actual components, but represent confluence points of relevant electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to confluence points of relevant electrical connections in the circuit diagram.
  • the transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or part of them may be N-type transistors and the other part may be P-type transistors.
  • active level refers to a level capable of turning on a transistor. Wherein, the P-type transistor can be turned on under the control of a low-level signal, and the N-type transistor can be turned on under the control of a high-level signal.
  • Some embodiments of the present disclosure provide a display panel 100 , a display module 1000 and a display device 2000 , and the display panel 100 , the display module 1000 and the display device 2000 will be introduced respectively below.
  • the display device 2000 may be any display device that displays images, whether moving (eg, video) or stationary (eg, still images), whether text or text. More specifically, it is contemplated that the display device of the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers, and/or displays, displays for camera views (e.g., Displays for rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (for example, displays for images of a piece of jewelry), etc.
  • PDAs personal data assistants
  • GPS receivers/navigators cameras
  • MP4 video players video cameras
  • the display device 2000 includes: a display module 1000 .
  • the above display module 1000 may be: an Organic Light Emitting Diode (OLED for short) display module, a Quantum Dot Light Emitting Diodes (QLED for short) display module, a Micro Light Emitting Diodes (Micro LED for short) display module or a Mini Light Emitting Diodes (Mini LED for short) display module, etc.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro LED for short
  • Mini LED for short Mini Light Emitting Diodes
  • the display device 2000 further includes a frame, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit, integrated circuit
  • Some embodiments of the present disclosure will be schematically described below by taking the above-mentioned display module 1000 as an OLED display module as an example.
  • the display module 1000 includes: a display panel 100 .
  • the display panel 100 has a main display area A1 and an auxiliary display area A2 .
  • the main display area A1 may surround the auxiliary display area A2.
  • the auxiliary display area A2 may be located in the middle of the main display area A1 .
  • the auxiliary display area A2 may be located on one side of the main display area A1 .
  • both the part of the above-mentioned display panel 100 located in the main display area A1 and the part located in the auxiliary display area A2 can be used for displaying images.
  • the light transmittance of the portion of the display panel 100 located in the auxiliary display area A2 is greater than the light transmittance of the portion of the display panel 100 located in the main display area A1.
  • External light can pass through the part of the display panel 100 located in the auxiliary display area A2 from one side of the display panel 100 and enter the other side of the display panel 100 .
  • the display module 1000 further includes: a cover plate on the light-emitting side of the display panel 100 ; and a protective layer on the non-light-emitting side of the display panel 100 .
  • the light-emitting side of the display panel 100 is the side where the display panel 100 displays images
  • the non-light-emitting side of the display panel 100 refers to the side opposite to the light-emitting side of the display panel 100 .
  • the material of the above-mentioned cover plate may be transparent glass or transparent organic material.
  • the transparent organic material includes PI (Polyimide, polyimide) and the like. In this way, it is possible to avoid reducing the light extraction efficiency of the display panel 100 , and further avoid affecting the image display of the display panel 100 .
  • the material of the above protective layer may be a transparent organic material.
  • the transparent organic material includes PET (Polyethylene Terephthalate, polyethylene terephthalate) and the like.
  • the protection layer can not only support the display panel 100, but also prevent the display panel 100 from being polluted and/or scratched by the outside world.
  • the display module 1000 further includes: a polarizer located between the display panel 100 and the cover plate.
  • a polarizer is arranged between the display panel 100 and the cover plate. After external light passes through the cover plate and the polarizer and enters the display panel 100 and is reflected by the internal structure of the display panel 100, the reflected external light can be blocked by the above polarizer, thereby preventing the reflected external light from exiting the light-emitting side of the display panel 100, thereby improving the display quality of the display panel 100.
  • the display device 2000 further includes: an optical element 200 on the non-light-emitting side of the display panel 100 of the display module 1000 , and the optical element 200 is located in the auxiliary display area A2 of the display panel 100 .
  • the above-mentioned optical element 200 is located in the auxiliary display area A2. In this way, the external light can pass through the part of the display panel 100 located in the auxiliary display area A2, enter the optical element 200, and be collected by the optical element 200, so that the optical element 200 can work normally.
  • the above-mentioned optical element 200 may be a camera, a fingerprint recognition sensor, an infrared sensor, and the like.
  • the present disclosure takes the optical element 200 as a camera as an example.
  • the camera when the camera is working, external light may pass through the part of the display panel 100 located in the auxiliary display area A2. In this way, the camera can collect the light to realize the function of taking pictures.
  • the above-mentioned auxiliary display area A2 may present a black picture
  • the main display area A1 presents a picture of the user's selfie, clearly showing the position of the camera.
  • the main display area A1 and the auxiliary display area A2 present a self-portrait picture of the user as a whole, without showing the location of the camera.
  • the part of the display panel 100 located in the main display area A1 can display, so that the display panel 100 and the display module 1000 as a whole can display images.
  • the optical element 200 in the auxiliary display area A2, it can not only ensure that the optical element 200 can work normally, but also increase the display area of the display panel 100, the display module 1000 and the display device 2000, and increase the screen ratio.
  • the display panel 100 includes: a plurality of pixel circuits 10 and light emitting devices 20 .
  • the aforementioned plurality of pixel circuits 10 and the plurality of light emitting devices 20 may be electrically connected in one-to-one correspondence.
  • one pixel circuit 10 may be electrically connected to multiple light emitting devices 20 , or multiple pixel circuits 10 may be electrically connected to one light emitting device 20 .
  • the present disclosure will schematically illustrate the structure of the display panel 100 by taking the electrical connection between one pixel circuit 10 and one light emitting device 20 as an example.
  • each light emitting device 10 can emit light under the driving action of the corresponding pixel circuit 20 , and the light emitted by multiple light emitting devices 10 cooperates with each other, so that the display panel 100 realizes the display function.
  • the light-emitting device 20 may include an anode, a light-emitting functional layer, a cathode, and the like that are sequentially stacked.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light emitting functional layer may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • an electric field can be formed between the anode and the cathode, and the electric field can drive different carriers (that is, holes and electrons) to recombine in the light-emitting layer, so that the light-emitting device 20 emits light.
  • the plurality of pixel circuits 10 includes a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 .
  • the above-mentioned plurality of light emitting devices 20 includes a first light emitting device 21 and a second light emitting device 22 .
  • the first pixel circuit 11 is electrically connected to the first light emitting device 21 , and the first light emitting device 21 emits light under the driving action of the corresponding first pixel circuit 11 .
  • the second pixel circuit 12 is electrically connected to the second light emitting device 22 , and the second light emitting device 22 emits light under the driving action of the corresponding second pixel circuit 12 .
  • the plurality of first pixel circuits 11 and the plurality of second pixel circuits 12 are located in the main display area A1
  • the first light emitting devices 21 electrically connected to the first pixel circuits 11 are located in the main display area A1
  • the second light emitting devices 12 electrically connected to the second pixel circuits 12 are located in the auxiliary display area A2.
  • the material forming the pixel circuit 10 includes metal material to ensure good transmission of electrical signals in the pixel circuit 10 .
  • the light transmittance of metal materials is low, and the blocking effect on light is better.
  • the present disclosure adopts the above arrangement method, and a plurality of pixel circuits 10 including a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 are arranged in the main display area A1, thereby reducing the structure capable of blocking light in the auxiliary display area A2, and external light can also be emitted from the side of the display panel 100 located in the auxiliary display area A2 (for example, the light-emitting side), through the gap between any two adjacent second light-emitting devices 12, and exit from the other side of the display panel 100 located in the auxiliary display area A2 (for example, the non-light-emitting side).
  • the portion of the display panel 100 located in the auxiliary display area A2 has higher transmittance.
  • the external light can pass through the part of the display panel 100 located in the auxiliary display area A2 and enter the optical element 200, which is collected by the optical element 200 and enables the optical element 200 to work normally.
  • the structures of the first light emitting device 21 and the first light emitting device 22 may be the same or different.
  • the first light-emitting device 21 and the first light-emitting device 22 have the same structure, which is beneficial to reduce the manufacturing difficulty of the display panel 100 and simplify the manufacturing process of the display panel 100 .
  • the structure of the pixel circuit 10 may include various types, and the setting may be selected according to actual needs.
  • the structure of the first pixel circuit 21 or the second pixel circuit 22 may include structures such as "2T1C", “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a transistor
  • the number before “T” represents the number of transistors
  • C represents a storage capacitor
  • the number before “C” represents the number of storage capacitors.
  • the structure and working process of the above-mentioned first pixel circuit 11 and the second pixel circuit 12 may be the same or different.
  • the structure and working process of the first pixel circuit 11 and the second pixel circuit 12 are the same.
  • 7 is an equivalent circuit diagram of the first pixel circuit 11
  • FIG. 8 is an equivalent circuit diagram of the second pixel circuit 12 .
  • the structure and working process of the pixel circuit 10 will be schematically described by taking the structure of the first pixel circuit 11 as “7T1C” in the pixel circuit 10 as an example. It should be noted that there may be other electrical connection relationships between the seven transistors and one storage capacitor included in the pixel circuit 10 , and are not limited to the electrical connection relationship shown in this example.
  • the display panel 100 further includes a first initial signal line Vinit1 for transmitting a first initial signal, a third initial signal line Vinit3 for transmitting a third initial signal, a scan signal line Scan for transmitting a scan signal, a reset signal line Reset for transmitting a reset signal, an enable signal line EM for transmitting an enable signal, a data line Data for transmitting a data signal, and a voltage signal line VDD for transmitting a voltage signal.
  • the first pixel circuit 11 includes: a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a switch transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst.
  • the control electrode of the second reset transistor T7 is electrically connected to the reset signal line Reset
  • the first electrode of the second reset transistor T7 is electrically connected to the third initial signal line Vinit3
  • the second electrode of the second reset transistor T7 is electrically connected to the first node N1 (that is, electrically connected to the second electrode of the compensation transistor T2).
  • the second reset transistor T7 is configured to be turned on under the control of the reset signal transmitted by the reset signal line Reset, transmit the third initial signal received from the third initial signal line Vinit3 to the first node N1, and reset the first node N1.
  • the control electrode of the first reset transistor T1 is electrically connected to the scanning signal line Scan
  • the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1
  • the second electrode of the first reset transistor T1 is electrically connected to the fourth node N4.
  • the first reset transistor T1 is configured to be turned on under the control of the scan signal transmitted by the scan signal line Scan, transmit the first initial signal received from the first initial signal line Vinit1 to the fourth node N4, and reset the fourth node N4.
  • the control electrode of the switching transistor T4 is electrically connected to the scan signal line Scan
  • the first electrode of the switching transistor T4 is electrically connected to the data line Data
  • the second electrode of the switching transistor T4 is electrically connected to the second node N2.
  • the switching transistor T4 is configured to be turned on under the control of the scanning signal transmitted by the scanning signal line Scan, and transmit the data signal transmitted by the data line Data to the second node N2.
  • the control electrode of the driving transistor T3 is electrically connected to the first node N1
  • the first electrode of the driving transistor T3 is electrically connected to the second node N2
  • the second electrode of the driving transistor T3 is electrically connected to the third node N3 .
  • the driving transistor T3 is configured to be turned on under the control of the voltage of the first node N1, and to transmit a signal (for example, a data signal) from the second node N2 to the third node N3.
  • the control electrode of the compensation transistor T2 is electrically connected to the scan signal line Scan
  • the first electrode of the compensation transistor T2 is electrically connected to the third node N3
  • the second electrode of the compensation transistor T2 is electrically connected to the first node N1 .
  • the compensation transistor T2 is configured to be turned on under the control of the scanning signal transmitted by the scanning signal line Scan, and transmit the signal (for example, a data signal) from the third node N3 to the first node N1 .
  • the control electrode of the first light emission control transistor T5 is electrically connected to the enable signal line EM
  • the first electrode of the first light emission control transistor T5 is electrically connected to the voltage signal line VDD
  • the second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.
  • the first light emission control transistor T5 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the voltage signal received from the voltage signal line VDD to the second node N2.
  • the control electrode of the second light emission control transistor T6 is electrically connected to the enable signal line EM
  • the first electrode of the second light emission control transistor T6 is electrically connected to the third node N3
  • the second electrode of the second light emission control transistor T6 is electrically connected to the fourth node N4.
  • the second light emission control transistor T6 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the voltage signal from the third node N3 to the fourth node N4.
  • the first pole of the storage capacitor Cst is electrically connected to the first node N1
  • the second pole of the storage capacitor Cst is electrically connected to the voltage signal line VDD.
  • the working process of the first pixel circuit 11 includes a reset phase, a data writing and compensation phase, and a light emitting phase which are performed in sequence.
  • the second reset transistor T7 is turned on to transmit the third initial signal V3 to the first node N1 to reset the first node N1. Since the first node N1 is electrically connected to the storage capacitor Cst, the control electrode of the driving transistor T3, and the second electrode of the compensation transistor T2, when the first node N1 is reset, the storage capacitor Cst, the control electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 can be reset. Wherein, the driving transistor T3 may be turned on under the control of the third initial signal.
  • the first reset transistor T1 , the switch transistor T4 and the compensation transistor T2 are simultaneously turned on under the control of the scan signal.
  • the first reset transistor T1 transmits the first start signal to the fourth node N4. Since the fourth node N4 is electrically connected to the anode of the first light emitting device 21 , when the fourth node N4 is reset, the anode of the first light emitting device 21 can be reset.
  • the switching transistor T4 transmits the data signal to the second node N2, the driving transistor T3 is turned on under the control of the first node N1, and transmits the data signal from the second node N2 to the third node N3.
  • the compensation transistor T2 transmits the data signal from the third node N3 to the first node N1 to charge the driving transistor T3 until the driving transistor T3 is in a cut-off state, and the threshold voltage compensation of the driving transistor T3 is completed.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are simultaneously turned on under the control of the enable signal.
  • the first light emission control transistor T5 transmits the voltage signal to the second node N2.
  • the driving transistor T3 transmits the voltage signal from the second node N2 to the third node N3.
  • the second light emission control transistor T6 transmits the voltage signal from the third node N3 to the fourth node N4.
  • the first light emitting device 21 emits light under the action of the voltage signal from the fourth node N4 and the common voltage from the common voltage line VSS.
  • the first pole of the first reset transistor T1 of the first pixel circuit 11 and the first pole of the first reset transistor T1 of the second pixel circuit 12 are both electrically connected to the first initial signal line Vinit1 .
  • the first initial signal received by the first reset transistor T1 of the first pixel circuit 11 and the first initial signal received by the first reset transistor T1 of the second pixel circuit 12 are the same signal, that is, the voltage values of the first initial signal received by both are the same. Since the first light-emitting device 21 and the first pixel circuit 11 are both located in the main display area A1, the distance between them is relatively small. Correspondingly, the distance between the first light-emitting device 21 and the fourth node N4 in the first pixel circuit 11 is relatively small.
  • the loss of voltage value is relatively small.
  • the second light-emitting device 22 is located in the auxiliary display area A2, and the second pixel circuit 12 electrically connected to it is located in the main display area A1. The distance between the second pixel circuit 12 and the second light-emitting device 22 is relatively large.
  • the distance between the fourth node N4 in the second pixel circuit 12 and the second light-emitting device 22 is relatively large, so that after the first initial signal provided by the first initial signal line is transmitted to the second light-emitting device 22 through the fourth node N4 in the second pixel circuit 12, the loss of voltage value is relatively large.
  • the auxiliary display area A2 and the main display area A1 When the preset brightness of the first light-emitting device 21 and the second light-emitting device 22 are the same, it is easy to cause the auxiliary display area A2 and the main display area A1 to have different luminances, resulting in different display effects between the main display area A1 and the auxiliary display area A2, resulting in uneven display on the display panel 100.
  • the display panel 100 includes: a plurality of first initial signal lines Vinit1 and a plurality of second initial signal lines Vinit2 .
  • the plurality of first initial signal lines Vinit1 and the plurality of second initial signal lines Vinit2 may extend along the first direction X, for example.
  • the first pixel circuit 11 is electrically connected to the first initial signal line Vinit1 and the first light emitting device 11 , configured to be electrically connected to the first initial signal line Vinit1 and the first light emitting device 21 , and configured to transmit the first initial signal transmitted by the first initial signal line Vinit1 to the first light emitting device 21 to reset the first light emitting device 21 .
  • the second pixel circuit 12 is electrically connected to the second initial signal line Vinit2 and the second light emitting device 22, is configured to be electrically connected to the second initial signal line Vinit2 and the second light emitting device 22, and is configured to transmit the second initial signal transmitted by the second initial signal line Vinit2 to the second light emitting device 22 to reset the second light emitting device 22.
  • the first reset transistor T1 (for example, the first pole of the first reset transistor) in the first pixel circuit 11 is electrically connected to the first initial signal line Vinit1 .
  • the first reset transistor T1 (such as the first pole of the first reset transistor) in the second pixel circuit 12 is electrically connected to the second initial signal line Vinit2
  • the first reset transistor T1 (such as the second pole of the first reset transistor) in the second pixel circuit 12 is electrically connected to the second light emitting device 22
  • the first reset transistor T1 in the second pixel circuit 12 is configured to transmit the second initial signal transmitted by the second initial signal line Vinit2 to the second light emitting device 22.
  • the anode of the second light emitting device 22 can be reset by using the second initial signal.
  • connection relationship of other transistors and storage capacitors in the second pixel circuit 12, and the working process of the second pixel circuit 12 can refer to the description of the first pixel circuit 11 in the above examples, and will not be repeated here.
  • the voltage value V2 of the second initial signal is greater than the voltage value V1 of the first initial signal.
  • the anode of the first light emitting device 21 is reset under the action of the first initial signal transmitted by the first initial signal line Vinit1, after the first initial signal is transmitted to the first light emitting device 21, the loss value of V1 is ⁇ V1.
  • the anode of the second light emitting device 22 is reset under the action of the second initial signal transmitted by the second initial signal line Vinit2, after the second initial signal is transmitted to the second light emitting device 22, the loss value of V2 is ⁇ V2.
  • the second pixel circuit 12 Since the second light-emitting device 22 is located in the auxiliary display area A2, and the second pixel circuit 12 electrically connected to it is located in the main display area A1, the second pixel circuit 12 is far away from the second light-emitting device 22, so that the loss value ⁇ V2 of the second initial signal voltage value is greater than the loss value ⁇ V1 of the first initial signal voltage value, that is, ⁇ V2> ⁇ V1, and the present disclosure sets V2>V1, so that the voltage value V2- ⁇ V2 of the signal received by the second light-emitting device 22 is the same as the voltage value of the signal received by the first light-emitting device 21 V1- ⁇ V1 is equal or close to equal, so that the reset effect on the first light emitting device 21 is the same or substantially the same as the reset effect on the second light emitting device 22 .
  • the voltage of the anode of the second light-emitting device 22 can reach or approach the preset light-emitting voltage, so that the light-emitting brightness of the second light-emitting device 22 can reach the preset brightness.
  • the preset luminance of the first light emitting device 21 and the second light emitting device 22 are the same, the actual luminance of the first light emitting device 21 and the second light emitting device 22 can be the same or substantially the same. This is beneficial to make the display effects of the main display area A1 and the auxiliary display area A2 consistent or close to the same, thereby improving the display quality of the display panel 100 .
  • the first pixel circuit 11 is electrically connected to the first light emitting device 21 located in the main display area A1
  • the second pixel circuit 12 is electrically connected to the second light emitting device 22 located in the auxiliary display area A2
  • the first initial signal line Vinit1 and the second initial signal line Vinit2 are provided
  • the first initial signal line Vinit1 is electrically connected to the first pixel circuit 11 to provide the first initial signal for the first pixel circuit 11, so that the first light emitting device 21 can be activated by the first initial signal.
  • the reset effect of the first initial signal on the first light-emitting device 21 and the reset effect of the second initial signal on the second light-emitting device 22 are substantially the same, and furthermore, in the light-emitting stage, the anode of the second light-emitting device 22 can reach or approach the preset light-emitting voltage, so that the actual luminous brightness of the second light-emitting device 22 reaches or approaches the preset luminous brightness, thereby ensuring that the display effects of the main display area A1 and the auxiliary display area A2 are the same or approach the same, providing a display panel 1 00 display quality.
  • the above display panel 100 further includes: a plurality of connecting wires 30 .
  • a second pixel circuit 12 is electrically connected to a first light-emitting device 22 through a connection line 30, and the driving voltage provided by the second pixel circuit 12 can be transmitted to the corresponding second light-emitting device 22 through the corresponding connection line 30, so as to drive the corresponding second light-emitting device 22 to emit light.
  • the second initial signal transmitted by the first reset transistor T1 of the second pixel circuit 12 can also be transmitted to the corresponding second light emitting device 22 through the corresponding connection line 30 to reset the corresponding second light emitting device 22 .
  • the material of the plurality of connecting wires 30 includes a light-transmitting conductive material.
  • the above-mentioned light-transmitting conductive material may be ITO (Indium Tin Oxide, indium tin oxide) and other materials.
  • the above-mentioned light-permeable conductive material has a high light transmittance, and the use of the above-mentioned light-transmittable conductive material to form the connecting line can make the connecting line 30 have a high light transmittance, and the loss of the light itself after the light passes through the connecting line 30 is small, thereby ensuring that the amount of light passing through the part of the display panel located in the auxiliary display area and incident on the optical element 200 is relatively sufficient, thereby ensuring that the optical element 200 can work normally.
  • the second pixel circuit 12 and the second light-emitting device 22 can be connected in a manner of "near to close, far to far". That is to say, in FIG. 4b, among the second pixel circuits 12 and second light-emitting devices 22 located on opposite sides of the boundary line between the main display area A1 and the auxiliary display area A2, the second pixel circuit 12 closest to the boundary line is electrically connected to the second light-emitting device 22 closest to the boundary line. At this time, the length of the connection line 30 connecting the two is the shortest. The second pixel circuit 12 closest to the boundary line is electrically connected to the second light-emitting device 22 closest to the boundary line.
  • connection line 30 connecting the two is the second shortest, ...
  • the second pixel circuit 12 farthest from the boundary line is electrically connected to the second light-emitting device 22 farthest from the boundary line.
  • the length of the connection line 30 connecting the two is the longest.
  • the second pixel circuit 12 closest to the boundary line is electrically connected to the second light-emitting device 22 farthest from the boundary line.
  • the second pixel circuit 12 closest to the boundary line is electrically connected to the second light emitting device 22 farthest from the boundary line, ..., the second pixel circuit 12 farthest from the boundary line is electrically connected to the second light emitting device 22 closest to the boundary line.
  • the lengths of the above-mentioned plurality of connection lines are, for example, the same.
  • the difference ⁇ V between the voltage value V2 of the second initial signal and the voltage value V1 of the first initial signal is positively correlated with the length of the connection line 30 . That is, the longer the connecting line 30 is, the larger the difference ⁇ V between the voltage value V2 of the second initial signal and the voltage value V1 of the first initial signal is, and correspondingly, the voltage value V2 of the second initial signal is larger.
  • connection line 30 itself has resistance. After the connection line 30 is provided between the second pixel circuit 12 and the second light emitting device 22, a resistance is formed between the two, and the resistance is shown as R 30 between the fourth node N4 and the second light emitting device in FIG. 8 .
  • the loss value ⁇ V1 of the voltage value V1 of the first initial signal is negligible relative to ⁇ V2.
  • the difference ⁇ V between the voltage value V2 of the second initial signal and the voltage value V1 of the first initial signal is ⁇ V2.
  • the second initial signal with a smaller voltage value can be set when the length of the connecting line 30 is small, and the second initial signal with a larger voltage value can be set when the length of the connecting line 30 is large.
  • the voltage value (that is, V2- ⁇ V2) of the second initial signal actually received by the second light-emitting device 22 is the same or substantially the same as the value of V1, so that the reset effect of the second initial signal on the second light-emitting device 22 is the same or roughly the same as the reset effect of the first initial signal on the first light-emitting device 21, so that in the light-emitting stage, the anode voltage of the second light-emitting device 22 can reach or approach the preset light-emitting voltage, so that the actual luminous brightness of the second light-emitting device 22 reaches or approaches the preset luminous brightness, reducing the main display area A1 and the auxiliary display area A 2, so that the display quality of the display panel 100 can be improved.
  • the display panel 100 includes: a substrate 101 , a pixel circuit layer 102 , a plurality of connection layers 103 , and a light emitting device layer 104 which are stacked in sequence.
  • the above-mentioned substrate 101 may be a flexible substrate or a rigid substrate.
  • the material of the substrate 101 may be a material with high elasticity such as dimethylsiloxane, PI (Polyimide, polyimide), PET (Polyethylene terephthalate, polyethylene terephthalate).
  • PI Polyimide, polyimide
  • PET Polyethylene terephthalate, polyethylene terephthalate
  • the material of the substrate 101 may be glass or the like.
  • the plurality of pixel circuits 10 included in the display panel 100 may be located in the above-mentioned pixel circuit layer, the plurality of light-emitting devices 20 included in the display panel 100 may be located in the above-mentioned light-emitting device layer, and the plurality of connection lines included in the display panel 100 may be located in the above-mentioned multiple connection layers.
  • the pixel circuit layer 102 the connection layer 103 and the light emitting device layer 104 will be introduced respectively below with reference to the accompanying drawings.
  • the pixel circuit layer 102 includes: a semiconductor layer Poly, a first gate conductive layer Gate1, a second gate conductive layer Gate2, an interlayer dielectric layer ILD, a first source-drain conductive layer SD1, a first planar layer PLN1, and a second source-drain conductive layer SD2, which are sequentially stacked on one side of the substrate 101.
  • a first gate insulating layer GI1 may be disposed between the semiconductor layer Poly and the first gate conducting layer Gate1
  • a second gate insulating layer GI2 may be disposed between the first gate conducting layer Gate1 and the second gate conducting layer Gate2.
  • the first gate insulating layer GI1 , the second gate insulating layer GI2 , the interlayer dielectric layer ILD and the first planar layer PLN1 can all isolate the conductive layers on their respective opposite sides, so as to prevent the conductive layers on their respective opposite sides from forming a short circuit.
  • FIG. 9 schematically shows a top view structure of the semiconductor layer Poly.
  • FIG. 10 a schematically shows a top view structure of the first gate conductive layer Gate1 .
  • FIG. 10 b schematically shows a top view structure after the semiconductor layer Poly and the first gate conductive layer Gate1 are sequentially stacked.
  • Fig. 11a schematically shows the top view structure of the second gate conductive layer Gate2.
  • FIG. 11 b schematically shows a top view structure after the semiconductor layer Poly, the first gate conductive layer Gate1 , and the second gate conductive layer Gate2 are sequentially stacked.
  • FIG. 12a schematically shows the top view structure of the interlayer dielectric layer ILD.
  • FIG. 12 b schematically shows a top view structure after the semiconductor layer Poly, the first gate conductive layer Gate1 , the second gate conductive layer Gate2 , and the interlayer dielectric layer ILD are sequentially stacked.
  • Fig. 13a schematically shows the top view structure of the first source-drain conductive layer SD1.
  • Fig. 13b schematically shows a top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, and the first source-drain conductive layer SD1 stacked in sequence.
  • Fig. 14a schematically shows the top view structure of the first planar layer PLN1.
  • FIG. 14b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, and the first flat layer PNL sequentially stacked.
  • Fig. 15a schematically shows the top view structure of the second source-drain conductive layer SD2.
  • Fig. 15b schematically shows the top view structure after the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PLN1, and the second source-drain conductive layer SD2 are sequentially stacked.
  • the material of the semiconductor layer Poly may include amorphous silicon, single crystal silicon, polycrystalline silicon or metal oxide semiconductor materials.
  • the materials of the first gate conductive layer Gate1 , the second gate conductive layer Gate2 , the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 are all conductive materials.
  • the materials of the first gate conductive layer Gate1 and the second gate conductive layer Gate2 may be the same, and the materials of the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 may be the same, for example.
  • the material of the first gate conductive layer Gate1, the second gate conductive layer Gate2, the first source-drain conductive layer SD1 or the second source-drain conductive layer SD2 may be a metal material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium) and the like.
  • the orthographic projection of the semiconductor layer Poly on the substrate overlaps with the orthographic projection of the first gate conductive layer Gate1 on the substrate.
  • the first gate conductive layer Gate1 can be used as a mask to perform doping treatment on the semiconductor layer Poly, so that the part of the semiconductor layer Poly covered by the first gate conductive layer Gate1 constitutes the active pattern of each transistor, so that the part of the semiconductor layer Poly not covered by the first gate conductive layer Gate1 constitutes a conductor, and the conductor can constitute the first electrode or the second electrode of each transistor.
  • the overlapping portion of the first gate conductive layer Gate1 and the semiconductor layer Poly constitutes a gate pattern (that is, a control electrode) of each transistor.
  • the relative positional relationship between transistors and storage capacitors included in the pixel circuit 10 is shown in FIG. 15b.
  • the compensation transistor T2 and the switch transistor T4 are arranged in a row, and the first light emission control transistor T5 and the second light emission control transistor T6 are arranged in a row.
  • the switch transistor T4 and the first light emission control transistor T5 are arranged in the same column, and the compensation transistor T2, the second light emission control transistor T6 and the first reset transistor T1 are arranged in the same column and arranged in sequence.
  • the driving transistor T3 is located between the compensation transistor T2 and the switching transistor T4; along the second direction Y, the driving transistor T3 is also located between the switching transistor T4 and the first light emission control transistor T5.
  • the second reset transistor T7 is located between the compensation transistor T2 and the switch transistor T4; along the second direction Y, the second reset transistor T7 is also located on the side of the switch transistor T4 away from the first light emission control transistor T5.
  • the location of the storage capacitor Cst is the same as that of the driving transistor T3, and the storage capacitor Cst is located on the side of the driving transistor T3 away from the substrate 101 .
  • the compensation transistor T2 in the above pixel circuit 10 includes: an active pattern p2 and a gate pattern g2 which are sequentially stacked.
  • the above-mentioned active pattern t2 may be located on the semiconductor layer Poly of the display panel 100 , and the gate pattern g2 may be located on the first gate conductive layer Gate1 of the display panel 100 .
  • the active pattern p2 includes a first semiconductor part p21 , a conductor part p22 and a second semiconductor part p23 connected in sequence.
  • the active pattern p2 includes various shapes, which can be selected and set according to actual needs.
  • the active pattern p2 is linear.
  • the first semiconductor part p21 , the conductor part p22 and the second semiconductor part p23 are arranged in sequence along the first direction X, or arranged in sequence along the second direction Y.
  • the active pattern p2 is in the shape of a broken line.
  • the first semiconductor part p21 may extend along the first direction X
  • the second semiconductor part p23 may extend along the second direction Y
  • the conductor part p22 may be in the shape of a broken line
  • one end of the conductor part p22 is connected to the first semiconductor part p21
  • the other end of the conductor part p22 is connected to the second semiconductor part p23. This is beneficial to reduce the occupied area of the active pattern p2 in the first direction X or the second direction Y.
  • the first direction X intersects the second direction Y.
  • the included angle between the first direction X and the second direction Y may be 85°, 90° or 95° and so on.
  • the included angle between the first direction X and the second direction Y is 90° as an example for illustration.
  • the gate pattern g2 includes a first sub-gate g21 and a second sub-gate g22 connected.
  • the first semiconductor portion p21 is partially opposed to the first sub-gate g21
  • the second semiconductor portion p23 is partially opposed to the second sub-gate g22 .
  • the configuration of the gate pattern g2 corresponds to the shape of the active pattern p2.
  • the first sub-gate g21 and the second sub-gate g22 may extend in the same direction, and the extending direction intersects the arrangement direction of the first semiconductor part p21, the conductor part p22 and the second semiconductor part p23 in the active pattern p2.
  • the first sub-gate g21 and the second sub-gate g22 may extend along different directions.
  • the first sub-gate g21 may extend along the second direction Y
  • the second sub-gate g22 may extend along the first direction X.
  • the intersection pattern of the first sub-gate g21 and the second sub-gate g22 is in the shape of a broken line, and the orthographic projection of the intersection pattern on the substrate does not overlap with the orthographic projection of the conductor part p22 on the substrate, and the corner of the intersection pattern is opposite to the corner of the conductor part p22.
  • the part of the first semiconductor part p21 and the first sub-gate g21 is arranged facing each other, which means that the orthographic projection of the first sub-gate g21 on the substrate 101 overlaps with the part of the orthographic projection of the first semiconductor part p21 on the substrate 101, and the boundary of the orthographic projection of the first sub-gate g21 on the substrate 101 intersects the boundary part of the orthographic projection of the first semiconductor part p21 on the substrate 101.
  • the second semiconductor portion p23 and the second sub-gate g22 are partially oppositely arranged, which means that the orthographic projection of the second sub-gate g22 on the substrate 101 coincides with the portion of the orthographic projection of the second semiconductor portion p23 on the substrate 101, and the boundary of the orthographic projection of the second sub-gate g22 on the substrate 101 intersects the boundary portion of the orthographic projection of the second semiconductor portion p23 on the substrate 101.
  • the compensation transistor T2 is a double-gate transistor.
  • Using a double-gate transistor as the compensation transistor T2 can improve the anti-leakage performance of the pixel circuit 10, reduce the leakage current of the first node N1 through the compensation transistor T2 or prevent the leakage of the first node N1 through the compensation transistor T2, so that in the light-emitting stage, the voltage stability of the first node N1 can be ensured, and the normal light emission of the light-emitting device 20 can be ensured.
  • the display panel 100 further includes: a shielding block B electrically connected to the third initial signal line Vinit3 .
  • the shielding block B and the conductor part p22' are arranged to face each other.
  • the orthographic projection of the conductor part p22 on the substrate 101 coincides with the orthographic projection of the shielding block B on the substrate 101, and the boundary of the orthographic projection of the conductor part p22 on the substrate 101 intersects the boundary of the orthographic projection of the shielding block B on the substrate 101.
  • the material of the shielding block B is a metal material, and an insulating layer is arranged between the shielding block B and the conductor part p22 at intervals. At this time, the shield block B and the conductor part p22 may constitute a capacitor.
  • the shielding block B Since the third initial signal transmitted by the third initial signal line Vinit3 is a constant voltage signal, and the shielding block B is electrically connected to the third initial signal line Vinit3, the shielding block B also has the above constant voltage signal. Since the voltage difference across the capacitor remains substantially constant, the voltage on the conductor portion p22 is substantially constant.
  • this can improve the holding effect of the capacitor formed by the shielding block B and the conductor part p22 on the potential on the conductor part p22, so that the voltage at the conductor part p22 on the compensation transistor T2 remains relatively stable relative to the voltages of the first pole and the second pole of the compensation transistor T2, thereby significantly reducing the risk of leakage current and ensuring high reliability of the pixel circuit 10 during operation.
  • the shielding block B is integrated with the third initial signal line Vinit3.
  • integrated structure means that two connected patterns are arranged on the same layer, and the two patterns are continuous and not separated. That is, in this disclosure, the shielding block B and the third initial signal line Vinit3 are located in the same film layer (for example, both are located in the second gate conductive layer Gate2), and the shielding block B and the third initial signal line Vinit3 are electrically connected to each other, and the two are continuous and not separated.
  • the first initial signal line Vinit1 , the second initial signal line Vinit2 and the third initial signal line Vinit3 are arranged on the same layer.
  • the "same layer” mentioned in this disclosure refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the first initial signal line Vinit1 , the second initial signal line Vinit2 and the third initial signal line Vinit3 can be fabricated simultaneously, which is beneficial to simplify the manufacturing process of the display panel 100 .
  • the plurality of pixel circuits 10 included in the display panel 100 may be arranged in multiple rows. Wherein, the plurality of pixel circuits 10 included in each row of pixel circuits 10 may be arranged sequentially along the first direction X. The number of pixel circuits included in any two adjacent rows of pixel circuits 10 may be the same or different.
  • a first initial signal line Vinit1 , a second initial signal line Vinit2 and a third initial signal line Vinit3 may be arranged between any two adjacent rows of pixel circuits 10 .
  • the number of the first initial signal line Vinit1 may be at least one
  • the number of the second initial signal line Vinit2 may be at least one
  • the number of the third initial signal line Vinit3 may be at least one.
  • a first initial signal line Vinit1 may be arranged between any two adjacent rows of pixel circuits 10 .
  • a second initial signal line Vinit2 may be arranged between any two adjacent rows of pixel circuits 10 .
  • a third initial signal line Vinit3 may be arranged between any two adjacent rows of pixel circuits 10 .
  • the first initial signal line Vinit1 , the second initial signal line Vinit2 and the third initial signal line Vinit3 arranged between any two adjacent rows of pixel circuits 10 extend along the first direction X and are arranged in sequence along the second direction Y.
  • the order in which the first initial signal line Vinit1 , the second initial signal line Vinit2 and the third initial signal line Vinit3 are arranged along the second direction Y may include various types.
  • the third initial signal line Vinit3 is closer to the compensation transistor T2 electrically connected to the third initial signal line Vinit3 than the first initial signal line Vinit1 and the second initial signal line Vinit2 .
  • One of the first initial signal line Vinit1 and the second initial signal line Vinit2 is closer to the third initial signal line Vinit3 .
  • the third initial signal line Vinit3 and the shielding block B electrically connected thereto can form an integral structure, which simplifies the film layer complexity of the display panel 100 .
  • a reset signal line Reset electrically connected to the control electrode of the compensation transistor T2 may also be provided between any two adjacent rows of pixel circuits 10 .
  • the reset signal line Reset extends along the first direction X, for example.
  • the reset signal line Reset and the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 arranged between any two adjacent rows of pixel circuits 10 can be arranged in various ways.
  • the orthographic projection of the reset signal line Reset on the substrate 101 is located between the orthographic projection of the first initial signal line Vinit1 on the substrate 101 and the orthographic projection of the second initial signal line Vinit2 on the substrate 101 .
  • the orthographic projection of the reset signal line Reset on the substrate 101 is located between the orthographic projection of the second initial signal line Vinit2 on the substrate 101 and the orthographic projection of the third initial signal line Vinit3 on the substrate 101 .
  • the arrangement space of the first initial signal line Vinit1, the second initial signal line Vinit2, the third initial signal line Vinit3 and the reset signal line Reset of the display panel 100 can be optimized, and the third initial signal line Vinit3 can be prevented from being electrically connected to the corresponding shielding block B by crossing the reset signal line Reset, so as to ensure that the third initial signal line Vinit3 and the shielding block B electrically connected to it are in an integrated structure, and can also prevent the reset signal transmitted by the reset signal line Reset from affecting the electrical signal on the shielding block B , to ensure a good shielding effect of the shielding block B on the compensation transistor T2 and to ensure the normal light emission of the light emitting device 20 .
  • the reset signal line Reset is located on the first gate conductive layer Gate1 .
  • the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 are located on the second gate conductive layer Gate2 .
  • the pixel circuit 10 shown in FIG. 14d is, for example, the nth row of pixel circuits.
  • the control electrode of the first reset transistor T1 of the nth row of pixel circuits may be electrically connected to the nth reset signal line Reset(n).
  • the display panel 100 further includes a first layer replacement block HC1 located in the first source-drain conductive layer SD1.
  • the first electrode of the first reset transistor T1 of the second pixel circuit 12 is electrically connected to the nth second initial signal line Vinit2(n) through the first layer changing block HC1.
  • One end of the first layer changing block HC1 can be electrically connected to the first pole of the first reset transistor T1 located in the semiconductor layer Poly (the first pole is located in the conductor in the semiconductor layer Poly) through the via holes passing through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 in sequence, and the other end of the first layer changing block HC1 can be electrically connected to the nth second initial signal line Vinit2(n) located in the second gate conductive layer Gate2 through the via holes penetrating through the interlayer dielectric layer ILD.
  • the display panel 100 further includes a second layer change block HC2 located on the first source-drain conductive layer SD1.
  • the first pole of the first reset transistor T1 of the first pixel circuit 10 is electrically connected to the nth first initial signal line Vinit1(n) through the second layer changing block HC2 .
  • One end of the second layer changing block HC2 can be electrically connected to the first pole of the first reset transistor T1 located in the semiconductor layer Poly (the first pole is located in the conductor in the semiconductor layer Poly) through the via hole passing through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 in sequence, and the other end of the first layer changing block HC1 can be electrically connected to the nth first initial signal line Vinit1(n) located in the second gate conductive layer Gate2 through the via hole penetrating through the interlayer dielectric layer ILD.
  • the second plates C2 of at least two storage capacitors Cst are connected to each other, forming an integrated structure.
  • the second plates C2 of at least two storage capacitors Cst are located in the same film layer of the display panel 100 (for example, both are located in the second gate conductive layer Gate2), and the second plates C2 of at least two storage capacitors Cst are continuous and not separated.
  • the second plates C2 of two, three, five or even more adjacent storage capacitors Cst are connected to each other, forming an integrated structure.
  • the plurality of pixel circuits 10 included in the display panel 100 may be arranged in multiple columns. Wherein, the plurality of pixel circuits included in each column of pixel circuits may be arranged in sequence along the second direction Y. The number of pixel circuits included in any two adjacent columns of pixel circuits may be the same or different.
  • FIG. 15 b there may be multiple voltage signal lines VDD electrically connected to the pixel circuit, and the multiple voltage signal lines VDD extend along the second direction Y and are arranged in sequence along the first direction X.
  • One voltage signal line VDD is, for example, electrically connected to the second plate C2 of the storage capacitor Cst of one column of pixel circuits 10 .
  • the voltage signals transmitted by the plurality of voltage signal lines VDD are constant voltage signals.
  • one voltage signal line VDD may also be electrically connected to the second plate C2 of the storage capacitor Cst of 10 storage capacitors Cst in two, three or more columns of pixel circuits, for example.
  • one voltage signal line VDD can be used to simultaneously provide voltage signals to the second plates C2 of multiple storage capacitors Cst, thereby improving the transmission effect of voltage signals.
  • the second plates C2 of at least two storage capacitors Cst are connected to each other to form an integrated structure, so that at least part or even all of the second plates C2 of the storage capacitors Cst and the voltage signal lines VDD electrically connected thereto form a grid structure.
  • This not only helps to reduce the voltage drop in the voltage signal line VDD, improves the stability and uniformity of the voltage value received by the second plate C2 of the storage capacitor Cst, ensures the stability of the electrical signal of the two plates of the storage capacitor Cst, but also helps reduce the probability of abnormalities in the display panel 100. Even if a part of the voltage signal line VDD appears to be disconnected, it can still ensure that the corresponding second plate of the storage capacitor Cst can receive a voltage signal from the second plate of the storage capacitor Cst that is integral with it.
  • the second plate of the storage capacitor Cst and the voltage signal line VDD are located on different layers.
  • the second plate of the storage capacitor Cst is located in the second gate conductive layer Gate2 , and a plurality of voltage signal lines VDD are located in the second source-drain conductive layer SD2 .
  • the display panel further includes a third layer change block HC3 located on the first source-drain conductive layer.
  • the voltage signal line VDD may contact the third layer changing block HC3 through the via hole penetrating through the first planar layer PLN1 to form an electrical connection.
  • One end of the third layer replacement block HC3 may be in contact with the second plate C2 of the storage capacitor Cst through a via hole penetrating through the interlayer dielectric layer ILD to form an electrical connection. In this way, the second plate of the storage capacitor Cst can be electrically connected to the voltage signal line VDD through the third layer changing block HC3.
  • the other end of the third layer replacement block HC3 can be in contact with the first electrode of the first light emission control transistor T5 through the via hole passing through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer in order to form an electrical connection.
  • the first electrode of the first light emission control transistor T5 can be electrically connected to the voltage signal line VDD through the third layer changing block HC3 .
  • the pixel circuit 10 further includes: a transition part Z connecting the second pole of the compensation transistor T2 and the first plate C1 of the storage capacitor Cst.
  • the transfer portion Z is located on the first source-drain conductive layer SD1.
  • the second plate C2 of the storage capacitor Cst has an opening, and the orthographic projection of the opening on the substrate is within the range of the orthographic projection of the first plate C1 of the storage capacitor Cst on the substrate 101 . That is, the opening in the second plate C2 exposes a part of the first plate C1 .
  • one end of the transition part Z can be in contact with the second pole d2 of the compensation transistor T2 to form an electrical connection through a via hole that sequentially passes through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1.
  • the other end of the transfer portion Z can be in contact with the first plate C1 of the storage capacitor Cst to form an electrical connection through a via hole that sequentially passes through the interlayer dielectric layer ILD and the second gate insulating layer GI2 and is located in the opening.
  • the transition part Z is disposed on the first source-drain conductive layer SD1, and the transition part Z can be used to form a bridge between the second pole of the compensation transistor T2 and the first plate C1 of the storage capacitor Cst, avoiding the short circuit with the scanning signal line due to the direct electrical connection between the two, reducing the difficulty of wiring, and improving the accuracy of electrical connection.
  • the orthographic projection of the transition portion Z on the substrate 101 is within the range of the orthographic projection of the voltage signal line VDD on the substrate 101 .
  • the orthographic projection area of the transfer portion Z on the substrate 101 is smaller than the orthographic projection area of the voltage signal line VDD on the substrate 101 .
  • the boundary of the orthographic projection of the transition part Z on the substrate 101 partially coincides with the boundary of the orthographic projection of the voltage signal line VDD on the substrate 101, or there is a certain distance between the boundary of the orthographic projection of the transition part Z on the substrate 101 and the boundary of the orthographic projection of the voltage signal line VDD on the substrate 101.
  • the voltage signal line VDD can completely cover the transition part Z, and shield the transition part Z. In this way, the overlapping of the first node N1 and the fourth node N4 can be avoided, thereby avoiding the formation of parasitic capacitance between the film layer on the side of the voltage signal line VDD away from the substrate (such as the anode layer AND or the connection layer of the light emitting device 20, etc.)
  • a first via hole H1 and a second via hole H2 are disposed on the first planar layer PLN1.
  • the first via hole H1 and the second via hole H2 also extend toward the substrate, and pass through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer in sequence.
  • the first via hole H1 will expose the first pole s5 of the first light emission control transistor T5
  • the second via hole H2 will expose the second pole d6 of the second light emission control transistor T6.
  • the first pole s5 of the first light emission control transistor T5 can be electrically connected to the voltage signal line VDD through the first via hole H1
  • the second pole d6 of the second light emission control transistor T6 can be electrically connected to the light emitting device 20 through the second via hole H2.
  • the first flat layer PLN1 is generally made of transparent materials, therefore, FIG. 14a only shows the positions of the via holes on the PLN1.
  • a third via hole H3 is further disposed on the first planar layer PLN1.
  • the first pole of the switching transistor T4 is electrically connected to the data line Data through the third via hole H3.
  • the control electrodes of the first light emission control transistor T5 and the second light emission control transistor T6 are electrically connected to the enable signal line EM, and are located in the first gate conductive layer Gate1.
  • the orthographic projections of the first via hole H1 and the second via hole H2 corresponding to the first light emission control transistor T5 and the second light emission control transistor T6 on the substrate 101 are within the range of the orthographic projection of the enable signal line EM on the substrate 101 .
  • the arrangement of the first via hole H1 and the second via hole H2 on the first flat layer PLN1 can be made orderly, which is convenient for manufacture.
  • the above arrangement method can also make the space occupied by the display panel 100 in the second direction Y smaller, saving space and facilitating the arrangement design of other film layers (such as the first connection layer ITO1, the second connection layer ITO2, the third connection layer ITO3, the anode layer AND, etc. mentioned below) in the second direction Y.
  • the number of connection layers in the display panel 100 may be at least two.
  • the number of connection layers may be two, three, four or more.
  • the multiple connection lines 30 included in the display panel 100 may be located in the above-mentioned multiple connection layers 103 , and each connection layer 103 includes at least one connection line 30 .
  • each connection layer 103 may further include at least one connection part 1031 . Between the connection part 1031 and the connection line 30 located in the same connection layer, they are arranged independently of each other.
  • connection layers may be three.
  • the three connection layers 103 include: a first connection layer CO1 , a second connection layer CO2 , and a third connection layer CO3 arranged on the side of the second source-drain conductive layer SD2 away from the substrate and stacked in sequence along the direction away from the substrate.
  • a second planar layer PLN2 is provided between the second source-drain conductive layer SD2 and the first connection layer CO1
  • a third planar layer PLN3 is provided between the first connection layer CO1 and the second connection layer CO2
  • a fourth planar layer PLN4 is provided between the second connection layer CO2 and the third connection layer CO3.
  • a fifth flat layer PLN5 is disposed between the third connection layer CO3 and the light emitting device layer.
  • Fig. 16a schematically shows the top view structure of the second flat layer PLN2.
  • Figure 16b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first planar layer PNL1, the second source-drain conductive layer SD2, and the second planar layer PNL2.
  • Fig. 17a schematically shows the top view structure of the first connection layer CO1.
  • FIG. 17b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, and the first connection layer CO1.
  • Fig. 18a illustrates the top view structure of the third planar layer PLN3.
  • Figure 18b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first planar layer PNL1, the second source-drain conductive layer SD2, the second planar layer PNL2, the first connection layer CO1, and the third planar layer PNL3.
  • FIG. 19a schematically shows the top view structure of the second connection layer CO2.
  • FIG. 19b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, the first connection layer CO1, the third flat layer PNL3, and the second connection layer CO2.
  • Fig. 20a illustrates the top view structure of the fourth planar layer PLN4.
  • FIG. 20b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first planar layer PNL1, the second source-drain conductive layer SD2, the second planar layer PNL2, the first connection layer CO1, the third planar layer PNL3, the second connection layer CO2, and the fourth planar layer PNL4.
  • FIG. 21a schematically shows the top view structure of the third connection layer CO3.
  • 21b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, the first connection layer CO1, the third flat layer PNL3, the second connection layer CO2, the fourth flat layer PNL4, and the third connection layer CO3.
  • FIG. 22a schematically shows the top view structure of the fifth planar layer PLN5.
  • 22b schematically shows a top view structure in which the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, the first connection layer CO1, the third flat layer PNL3, the second connection layer CO2, the fourth flat layer PNL4, the third connection layer CO3, and the fifth flat layer PNL5 are sequentially stacked.
  • Fig. 23a schematically shows the top view structure of the anode layer AND.
  • 23b schematically shows the top view structure of the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first planar layer PNL1, the second source-drain conductive layer SD2, the second planar layer PNL2, the first connection layer CO1, the third planar layer PNL3, the second connection layer CO2, the fourth planar layer PNL4, the third connection layer CO3, the fifth planar layer PNL5, and the anode layer AND.
  • the second electrode of the second light emission control transistor T6 of the first pixel circuit 11 can be electrically connected to the anode of the anode layer AND of the first light emitting device 21 through the connection portion 1031 located in the second source-drain conductive layer SD2, the connection portion 1031 located in the first connection layer CO1, the connection portion 1031 located in the second connection layer CO2 and the connection portion 1031 located in the third connection layer CO3 in sequence.
  • the anode layer AND of the first light emitting device 21 can be electrically connected to the connection portion 1031 located in the third connection layer CO3 through the via hole penetrating the fifth flat layer PLN5
  • the connection portion 1031 located in the third connection layer CO3 can be electrically connected to the connection portion 1031 located in the second connection layer CO2 through the via hole penetrating the fourth flat layer PLN4
  • the connection portion 1031 located in the second connection layer CO2 can be electrically connected to the connection portion 1031 located in the first connection layer CO1 through the via hole penetrating the third flat layer PLN3.
  • connection part 1031 located in the first connection layer CO1 can be electrically connected to the connection part 1031 located in the second source-drain conductive layer SD2 through the via hole penetrating the second planar layer PLN2, and the connection part 1031 located in the second source-drain conductive layer SD2 can be electrically connected to the second electrode of the second light emission control transistor T6 of the first pixel circuit through the via hole penetrating the first planar layer PLN1.
  • the second electrode of the second light emission control transistor T6 of a part of the second pixel circuit 12 can be electrically connected to one end of the connection line 30 located in the first connection layer CO1 through the connection part 1031 located in the second source-drain conductive layer SD2, and the other end of the connection line 30 can be electrically connected to the anode of the anode layer AND of the second light emitting device 22 through the connection part 1031 located in the second connection layer CO2 and the connection part 1031 located in the third connection layer CO3 in sequence.
  • the second electrode of the second light emission control transistor T6 of a part of the second pixel circuit 12 can be electrically connected to one end of the connection line 30 located in the second connection layer CO2 through the connection portion 1031 located in the second source-drain conductive layer SD2 and the connection portion 1031 located in the first connection layer CO1 in sequence, and the other end of the connection line 30 can be electrically connected to the anode of the anode layer AND of the second light emitting device 22 through the connection portion 1031 located in the third connection layer CO3.
  • the second electrode of the second light emission control transistor T6 of another part of the second pixel circuit 12 can be electrically connected to one end of the connection line 30 located in the third connection layer CO3 through the connection portion 1031 located in the second source-drain conductive layer SD2, the connection portion 1031 located in the first connection layer CO1, and the connection portion 1031 located in the second connection layer CO2 in sequence, and the other end of the connection line 30 can be electrically connected to the anode of the anode layer AND of the second light emitting device 22.
  • the setting manner of the via holes of each flat layer may be the same as that in the above example, and details are not repeated here.
  • the above-mentioned light emitting device layer of the display panel 100 may further include: a pixel defining layer PDL disposed on the side of the anode layer AND away from the substrate.
  • FIG. 24a schematically shows the top view structure of the pixel defining layer PDL.
  • Figure 24b schematically shows the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, the first connection layer CO1, the third flat layer PNL3, the second connection layer CO2, the fourth flat layer PNL4, the third connection layer CO3, the fifth flat layer PNL5, the anode layer AND, and the pixel definition layer PDL. overhead structure.
  • Fig. 25a schematically shows the top view structure of the light emitting layer EL.
  • Figure 25b schematically shows the semiconductor layer Poly, the first gate conductive layer Gate1, the second gate conductive layer Gate2, the interlayer dielectric layer ILD, the first source-drain conductive layer SD1, the first flat layer PNL1, the second source-drain conductive layer SD2, the second flat layer PNL2, the first connection layer CO1, the third flat layer PNL3, the second connection layer CO2, the fourth flat layer PNL4, the third connection layer CO3, the fifth flat layer PNL5, the anode layer AND, the pixel defining layer PDL, and the light-emitting layer EL in sequence
  • the pixel defining layer PDL is used to define the size of the light-emitting area of the light-emitting layer EL, and the anode layer AND is in direct or indirect contact with the light-emitting layer EL to provide an anode voltage for the light-emitting layer EL.
  • a plurality of pixel circuits 10 are arranged in multiple rows and multiple columns.
  • each row of pixel circuits may include a plurality of pixel circuits 10 , and the plurality of pixel circuits 10 are arranged in sequence along the first direction X.
  • Each column of pixel circuits may include a plurality of pixel circuits 10 , and the plurality of pixel circuits 10 are arranged in sequence along the second direction Y.
  • the number of pixel circuits 10 included in any two adjacent rows of pixel circuits 10 may be the same or different.
  • the number of pixel circuits 10 included in any two adjacent columns of pixel circuits 10 may be the same or different.
  • the first pixel circuits 11 and the second pixel circuits 12 are arranged in different columns. That is, the same column of pixel circuits only includes the first pixel circuit, or only includes the second pixel circuit.
  • the control electrodes of the first reset transistor T1 , the compensation transistor T2 and the switch transistor T4 of each pixel circuit 10 may be electrically connected to the same scanning signal line Scan.
  • the first electrodes of the second reset transistors T7 of each pixel circuit 10 may be electrically connected to the same third initial signal line Vinit3 .
  • the control electrode of the second reset transistor T7 of each pixel circuit 10 may be electrically connected to the same reset signal line Reset.
  • the multiple light emitting devices 20 on the display panel 100 are arranged in an array.
  • the plurality of light emitting devices 20 are arranged in multiple rows and multiple columns. Multiple light emitting devices 20 included in the same row of light emitting devices 20 are arranged sequentially along the first direction X, and multiple light emitting devices 20 included in the same column of light emitting devices 20 are arranged sequentially along the second direction Y.
  • the numbers of the plurality of light emitting devices 20 included in any two adjacent rows of light emitting devices 20 may be the same or different.
  • the number of multiple light emitting devices 20 included in any two adjacent columns of light emitting devices 20 may be the same or different.
  • the multiple first light emitting devices 21 among the above multiple light emitting devices 20 may be arranged in multiple rows and multiple columns.
  • the multiple second light emitting devices 22 in the above multiple light emitting devices 20 may be arranged in multiple rows and multiple columns.
  • the display panel 100 includes: a plurality of light emitting device columns 23 arranged in sequence along the first direction X.
  • Each light emitting device column 23 includes a plurality of first light emitting devices 21 located in the main display area A1 and a plurality of second light emitting devices 22 located in the auxiliary display area A2 arranged in sequence along the second direction Y.
  • only the first light emitting device 21 may be included, or only the second light emitting device 22 may be included, or both the first light emitting device 21 and the second light emitting device 22 may be included.
  • the same row of light emitting devices including the first light emitting device 21 and the second light emitting device 22 is referred to as a row of light emitting devices.
  • the data lines Data included in the display panel 100 extend along the second direction Y.
  • the overall extension direction of each data line Data among the plurality of data lines Data may be along the second direction Y, and the overall shape of each data line Data may be or approximately a straight line shape, or may be or approximately a curved shape, which is not limited in the present disclosure.
  • the multiple first pixel circuits 11 electrically connected to the multiple first light emitting devices 21 in the light emitting device column 23, and the multiple second pixel circuits 12 electrically connected to the multiple second light emitting devices 22 in the light emitting device column 23 are electrically connected to the same data line Data.
  • multiple first pixel circuits 11 electrically connected to multiple first light emitting devices 21 in the light emitting device column 23, and multiple second pixel circuits 12 electrically connected to multiple second light emitting devices 22 in the light emitting device column 23 can simultaneously receive data signals from the same data line Data.
  • the column driving method can be used to respectively provide data signals for the pixel circuits 10 electrically connected to the light emitting devices 20 in the same column, which is beneficial to simplify the driving method of the display panel 100 and ensure the display uniformity of the display panel 100.
  • the part electrically connected to the plurality of second pixel circuits 22 is located in the main display area A1.
  • the light transmittance of the data line Data is small, and has a strong blocking effect on light.
  • the present disclosure adopts the above-mentioned setting method, which can avoid setting the data line Data in the auxiliary display area A2, and further prevent the part of the data line Data electrically connected to the second pixel circuit 12 from blocking external light. This is beneficial to enable the optical element 200 located in the auxiliary display area A2 to collect more light and ensure that the optical element 200 can work normally.
  • the plurality of second pixel circuits 12 electrically connected to the plurality of second light emitting devices 22 in the light emitting device row 23 are arranged in sequence along the second direction Y, and are located on one side of the auxiliary display area A2 along the first direction X.
  • the plurality of second pixel circuits 12 electrically connected to the plurality of second light emitting devices 22 in the row 23 of light emitting devices may be independently arranged in a row. That is, among the plurality of pixel circuits 10 included in the display panel 100 , a column of pixel circuits 10 only includes a plurality of first pixel circuits 11 or only includes a plurality of second pixel circuits 12 .
  • the data line Data electrically connected to the light-emitting device column 23 includes: a first sub-data line 411 and a second sub-data line 412 extending along the second direction Y and respectively located on opposite sides of the auxiliary display area A1 along the second direction Y; a third sub-data line 413 extending along the second direction Y and located on one side of the auxiliary display area A2 along the first direction X;
  • the second transition line 422 extends along the first direction X and connects the second sub-data line 412 and the third sub-data line 413 .
  • the first sub-data line 411 and the second sub-data line 412 are electrically connected to the plurality of first pixel circuits 11
  • the third sub-data line 413 is electrically connected to the plurality of second pixel circuits 12 .
  • the third sub-data line 413 and the plurality of second pixel circuits 12 electrically connected thereto are located on the same side of the auxiliary display area A1.
  • the arrangement of the data lines Data electrically connected to the light emitting device rows 23 can be made orderly, and it can also be ensured that the first light emitting device 21 and the second light emitting device 22 in each light emitting device row 23 can receive the data signal provided by the same data line Data, so that it can be ensured that there is no difference between the display picture in the auxiliary display area A2 and the display picture in the main display area A1, and the display uniformity of the display panel 100 can be ensured.
  • the first sub-data line 411, the second sub-data line 412, and the third sub-data line 413 are located in the second source-drain conductive layer SD2, and the first transition line 421 and the second transition line 422 are located in the first source-drain conductive layer SD1.
  • the materials of the second source-drain conductive layer SD2 and the first source-drain conductive layer SD1 are the same, the materials of the first sub-data line 411, the second sub-data line 412, and the third sub-data line 413 can be made to be the same as those of the first transition line 421 and the second transition line 422, so as to avoid greatly increasing the resistance of the data line Data electrically connected to the light emitting device column 23, and reduce the loss of the data signal transmitted by the data line Data.
  • first sub-data line 411 By arranging the first sub-data line 411, the second sub-data line 412, and the third sub-data line 413 on different layers from the first transfer line 421 and the second transfer line 422, it is beneficial to increase the wiring space and reduce the routing difficulty of the data line Data.
  • a portion of the main display area A1 is compressed.
  • the main display area A1 includes a normal area and a compressed area.
  • the second pixel circuit 12 is located in the compressed area, a part of the first pixel circuits 11 among the plurality of first pixel circuits 11 is located in the normal area, and the other part of the first pixel circuits 11 is located in the compressed area, and in the compressed area, along the first direction X, at least one first pixel circuit 11 is arranged between two adjacent second pixel circuits 12.
  • the width of the column area where the first pixel circuit 11 or the second pixel circuit 12 is located in the compressed area is smaller than the width of the column area where the first pixel circuit 11 is located in the normal area.
  • the width of the column area where the first pixel circuit 11 is located refers to the size of the area occupied by the pixel circuit column where the first pixel circuit 11 is located in the first direction X.
  • the width of the column area where the second pixel circuit 12 is located refers to the size of the area occupied by the pixel circuit column where the second pixel circuit 12 is located in the first direction X.
  • the width of the column area where the first pixel circuit 11 or the second pixel circuit 12 in the compressed area is located is smaller than the width of the column area where the second pixel circuit 12 is located in the normal area, which means that the width of the column area where the first pixel circuit 11 or the second pixel circuit 12 is located in the compressed area is compressed, while the width of the column area where the second pixel circuit 12 is located in the normal area is not compressed.
  • the main display area A2 is set in overall compression. That is, in the first direction X, the width of the column area where the first pixel circuit 11 or the second pixel circuit 12 is located is compressed.
  • the display panel 100 further includes: a peripheral area F and wires disposed in the area of the peripheral area F of the display panel 100 .
  • the above peripheral area F may be located at the periphery of the display area A.
  • the above routing may include: a first initial signal bus Z1 , a second initial signal bus Z2 , and a third initial signal bus Z3 .
  • the first initial signal bus Z1 is electrically connected to the first initial signal line Vinit1 through the first bridge line q1
  • the second initial signal bus Z2 is electrically connected to the second initial signal line Vinit2 through the second bridge line q2
  • the third initial signal bus Z3 is electrically connected to the third initial signal line Vinit3 through the third bridge line q3.
  • the first initial signal bus Z1 , the second initial signal bus Z2 , and the third initial signal bus Z3 are all located in the second source-drain conductive layer SD2 of the display panel 100 .
  • the first bridge line q1 , the second bridge line q2 , and the third bridge line q3 are all located on the first source-drain conductive layer SD1 of the display panel 100 .
  • the orthographic projections of the first initial signal bus Z1, the second initial signal bus Z2, and the third initial signal bus Z3 on the substrate do not overlap, and the orthographic projections of the first bridge line q1, the second bridge line q2, and the third bridge line q3 on the substrate do not overlap.
  • first initial signal bus Z1, the second initial signal bus Z2, and the third initial signal bus Z3 may be respectively located on different layers, and the first bridge line q1, the second bridge line q2, and the third bridge line q3 may also be respectively located on different layers.
  • the orthographic projections of the first initial signal bus Z1, the second initial signal bus Z2, and the third initial signal bus Z3 on the substrate may overlap, for example, and the orthographic projections of the first bridge line q1, the second bridge line q2, and the third bridge line q3 on the substrate may overlap, for example.
  • first initial signal buses Z1 there may be two first initial signal buses Z1, and the two first initial signal buses Z1 may be respectively located at opposite ends of the first initial signal line Vinit1.
  • first initial signal buses Z1 There may be two second initial signal buses Z2, and the two second initial signal buses Z2 may be respectively located at opposite ends of the second initial signal line Vinit2.
  • second initial signal buses Z2 There may be two second initial signal buses Z2, and the two second initial signal buses Z2 may be respectively located at opposite ends of the second initial signal line Vinit2.
  • the layout of the pixel circuit 10 changes, the layout of the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 in the display panel 100 will also change accordingly.
  • FIG. 27 a shows the layout of the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 in the display panel 100 in the case of partial compression setting.
  • FIG. 27 b shows the layout of the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 in the display panel 100 in the case of overall compression setting.
  • the second pixel circuits 12 may be located only on opposite sides of the auxiliary display area A2 in the first direction X, for example.
  • the above-mentioned second initial signal line Vinit2 is only located in the area where the second pixel circuits 12 are disposed, and is electrically connected to the corresponding second pixel circuits 12 . In the remaining areas, only the first initial signal line Vinit1 and the third initial signal line Vinit3 are provided.
  • the plurality of pixel circuits in the display panel 100 further includes a plurality of virtual second pixel circuits.
  • the plurality of dummy second pixel circuits are respectively located in the column areas where the corresponding second pixel circuits 12 are located.
  • the fourth node N4 of the plurality of dummy second pixel circuits is suspended and not electrically connected to the second light emitting device 22 .
  • the first initial signal line Vinit1 , the second initial signal line Vinit2 , and the third initial signal line Vinit3 may be arranged periodically along the second direction Y sequentially.
  • a part of the second initial signal line Vinit2 is electrically connected to the corresponding second pixel circuit
  • another part of the second initial signal line Vinit2 is electrically connected to the dummy second pixel circuit.
  • the distribution density of the second light emitting devices 22 is less than or equal to the distribution density of the first light emitting devices 21 . This is beneficial to ensure that the portion of the display panel 100 located in the auxiliary display area A2 has a higher light transmittance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板（100），包括：位于主显示区（A1）的多个第一像素电路（11）、多个第二像素电路（12）、多个第一发光器件（21），位于辅助显示区（A2）的多个第二发光器件（22）；多个第一像素电路（11）分别与多个第一发光器件（21）电连接，多个第二像素电路（12）分别与多个第二发光器件（22）电连接；以及，多条第一初始信号线（Vinit1）和多条第二初始信号线（Vinit2）。第一像素电路（11）与第一初始信号线（Vinit1）及第一发光器件（21）电连接，且被配置为，将第一初始信号线（Vinit1）所传输的第一初始信号传输至第一发光器件（21），对第一发光器件（21）进行复位；第二像素电路（12）与第二初始信号线（Vinit2）及第二发光器件（22）电连接，且被配置为，将第二初始信号线（Vinit2）所传输的第二初始信号传输至第二发光器件（22），对第二发光器件（22）进行复位；其中，第二初始信号的电压值（V2）大于第一初始信号的电压值（V1）。

Description

显示面板、显示模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示模组及显示装置。
背景技术
随着显示技术的发展，具有摄像头的全面屏(Full Display with Camera，简称FDC)以其具有较大的屏占比的优点，已逐步应用于显示产品中。全面屏显示装置通常将摄像头等光学元件放置于显示面板的屏下区域，极大地提高了屏占比。
发明内容
一方面，提供一种显示面板，具有主显示区和辅助显示区；所述显示面板包括：位于所述主显示区的多个像素电路；所述多个像素电路包括多个第一像素电路和多个第二像素电路；多个发光器件，包括位于所述主显示区的多个第一发光器件和位于所述辅助显示区的多个第二发光器件；所述多个第一像素电路分别与所述多个第一发光器件电连接，所述多个第二像素电路分别与所述多个第二发光器件电连接；以及，多条第一初始信号线和多条第二初始信号线；第一像素电路，与第一初始信号线及第一发光器件电连接，且被配置为，将所述第一初始信号线所传输的第一初始信号传输至所述第一发光器件，对所述第一发光器件进行复位；第二像素电路的第一复位晶体管，与第二初始信号线及第二发光器件电连接，且被配置为，将所述第二初始信号线所传输的第二初始信号传输至所述第二发光器件，对所述第二发光器件进行复位；其中，所述第二初始信号的电压值大于所述第一初始信号的电压值。
在一些实施例中，所述显示面板，还包括：多条连接线。一个第二像素电路通过一条连接线与一个第二发光器件电连接；所述多条连接线的材料包括可透光的导电材料。
在一些实施例中，所述第二初始信号的电压值与所述第一初始信号的电压值之差，与连接线的长度，呈正相关。
在一些实施例中，所述显示面板包括：沿第一方向依次排列的多个发光器件列；发光器件列包括沿第二方向依次设置的、位于所述主显示区的多个第一发光器件和位于辅助显示区的多个第二发光器件；所述显示面板还包括：沿所述第二方向延伸的多条数据线；所述第一方向与所述第二方向相交；与所述发光器件列中多个第一发光器件电连接的多个第一像素电路，及与所述发光器件列中多个第二发光器件电连接的多个第二像素电路，与同一条数据线电连接。
在一些实施例中，所述数据线中与所述多个第二像素电路电连接的部分，位于所述主显示区。
在一些实施例中，与所述发光器件列中多个第二发光器件电连接的多个第二像素电路，沿所述第二方向依次排列，且位于所述辅助显示区沿所述第一方向的一侧；所述数据线包括：沿第二方向延伸、且分别位于所述辅助显示区沿所述第二方向的相对两侧的第一子数据线和第二子数据线，沿所述第二方向延伸、且位于所述辅助显示区沿所述第一方向的一侧的第三子数据线，沿所述第一方向延伸、且连接所述第一子数据线和所述第三子数据线的第一转接线，及沿所述第一方向延伸、且连接所述第二子数据线和所述第三子数据线的第二转接线；所述第一子数据线和所述第二子数据线与所述多个第一像素电路电连接，所述第三子数据线与所述多个第二像素电路电连接。
在一些实施例中，所述显示面板包括：衬底，以及依次层叠设置在所述衬底一侧的第一源漏导电层和第二源漏栅导电层。所述第一子数据线、所述第二子数据线、所述第三子数据线位于所述第二源漏导电层，所述第一转接线、所述第二转接线位于所述第一源漏导电层。
在一些实施例中，所述像素电路还包括：补偿晶体管；所述补偿晶体管包括：依次层叠设置的有源图案及栅极图案；所述有源图案包括依次连接的第一半导体部、导体部和第二半导体部，所述栅极图案包括相连接的第一子栅极和第二子栅极；所述第一半导体部和所述第一子栅极部分正对设置，所述第二半导体部和所述第二子栅极部分正对设置；其中，所述显示面板还包括：与所述像素电路电连接的第三初始信号线，及与所述第三初始信号线电连接的屏蔽块；所述屏蔽块与所述导体部，部分正对设置。
在一些实施例中，所述屏蔽块与所述第三初始信号线为一体结构。
在一些实施例中，所述第一初始信号线、所述第二初始信号线和所述第三初始信号线同层设置。所述多个像素电路排列为多行。位于相邻两行像素电路之间的第一初始信号线、第二初始信号线和第三初始信号线中，所述第三初始信号线，相比于所述第一初始信号线和所述第二初始信号线更靠近与所述第三初始信号线电连接的补偿晶体管。
在一些实施例中，所述像素电路还包括第二复位晶体管；所述第二复位晶体管的第一极与所述第三初始信号线电连接，所述第二复位晶体管的第二极与所述补偿晶体管的第二极电连接；所述显示面板还包括：与所述第二复位晶体管的控制极电连接的复位信号线；所述第二复位晶体管被配置为，在所述复位信号线所传输的复位信号的控制下，将所述第三初始信号线所传输的第三初始信号传输至所述补偿晶体管的第二极；其中，所述复位信号线在所述衬底上的正投影，位于所述第一初始信号线在所述衬底上的正投影及所述第二初始信号线在所述衬底上的正投影之间；或者，位于所述第二初始信号线在所述衬底上的正投影及第三初始信号线在所述衬底上的正投影之间。
在一些实施例中，所述显示面板还包括：衬底，以及依次层叠设置在所述衬底一侧的第一栅导电层和第二栅导电层；所述复位信号线位于所述第一栅导电层；所述第一初始信号线、所述第二初始信号线、所述第三初始信号线位于所述第二栅导电层。
在一些实施例中，所述多个像素电路排列为多行多列；所述像素电路还包括：存储电容器；所述存储电容器包括层叠设置的第一极板及第二极板；其中，同一行像素电路中的至少两个存储电容器的第二极板相互连接，呈一体结构。
在一些实施例中，所述显示面板还包括：沿第二方向延伸的多条电压信号线；一条电压信号线与一列像素电路的存储电容器的第二极板电连接。
在一些实施例中，所述显示面板还包括：衬底，以及依次层叠设置在所述衬底一侧的第二栅导电层和第二源漏导电层。所述第二极板位于所述第二栅导电层，所述多条电压信号线位于所述第二源漏导电层。
在一些实施例中，所述像素电路还包括：补偿晶体管，及连接所述补偿晶体管的第二极与所述存储电容器的第一极板的转接部；所述显示面板还包括：位于所述第二栅导电层与所述第二源漏导电层之间的第一源漏导电层；所述转接部位于所述第一源漏导电层；所述转接部在所述衬底上的正投影位于所述电压信号线在所述衬底上的正投影范围之内。
在一些实施例中，所述显示面板还包括：设置在所述第二栅导电层远离所述第二源漏导电层一侧的第一栅导电层，及设置在所述第二栅导电层和所述第二源漏导电层之间的第 一平坦层；所述像素电路还包括：第一发光控制晶体管和第二发光控制晶体管；所述第一平坦层上设置有第一过孔和第二过孔；所述第一发光控制晶体管的第一极通过所述第一过孔与所述电压信号线电连接，所述第二发光控制晶体管的第二极通过所述第二过孔与发光器件电连接；所述显示面板还包括：与第一发光控制晶体管的控制极和第二发光控制晶体管的控制极电连接的使能信号线；所述使能信号线位于所述第一栅导电层；所述第一过孔及所述第二过孔在所述衬底上的正投影，位于所述使能信号线在所述衬底上的正投影范围之内。
在一些实施例中，所述显示面板还包括：沿所述第一方向延伸的多条扫描信号线以及多条复位信号线；所述像素电路还包括：驱动晶体管、补偿晶体管、第一复位晶体管、第二复位晶体管、开关晶体管。所述补偿晶体管的控制极与所述扫描信号线电连接，所述补偿晶体管的第二极与第一节点电连接；所述第二复位晶体管的控制极与复位信号线电连接，所述第二复位晶体管的第一极与第三初始信号线电连接，所述第二复位晶体管的第二极与所述第一节点电连接；所述第一发光控制晶体管的第二极与第二节点电连接；所述驱动晶体管的控制极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，驱动晶体管的第二极与第三节点电连接；所述开关晶体管的控制极与所述扫描信号线电连接，所述开关晶体管的第一极与所述第二节点电连接，所述开关晶体管的第二极与所述数据线电连接；所述第二发光控制晶体管的第一极与所述第三节点电连接，所述存储电容器的第一极板与所述第一节点电连接；所述第一复位晶体管的控制极与扫描信号线电连接，所述第一像素电路的第一复位晶体管的第一极与所述第一初始信号线电连接，所述第一像素电路的第一复位晶体管的第二极与所述第一像素电路的第四节点电连接，所述第二像素电路的第一复位晶体管的第一极与所述第二初始信号线电连接，所述第二像素电路的第一复位晶体管的第二极与所述第二像素电路的第四节点电连接。
另一方面，提供一种显示模组，包括：上述任一实施例所述的显示面板；位于所述显示面板的出光侧的盖板；以及，位于所述显示面板的非出光侧的保护层。
又一方面，提供一种显示装置，所述显示装置包括：上述实施例所述的显示模组；以及，位于所述显示模组的显示面板中非出光侧的光学元件，所述光学元件位于所述显示面板的辅助显示区。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸等的限制。
图1为根据本公开的一些实施例的一种显示装置的结构图；
图2为根据本公开的一些实施例的一种显示模组的结构图；
图3a为根据本公开的一些实施例的一种显示面板的结构图；
图3b为根据本公开的一些实施例的另一种显示面板的结构图；
图4a为根据本公开的一些实施例的又一种显示面板的结构图；
图4b为根据本公开的一些实施例的又一种显示面板的结构图；
图5为根据本公开的一些实施例的又一种显示面板的结构图；
图6为根据本公开的一些实施例的又一种显示面板的结构图；
图7为根据本公开的一些实施例的一种第一像素电路的等效结构图；
图8为根据本公开的一些实施例的一种第二像素电路的等效结构图；
图9为根据本公开的一些实施例的一种显示面板中一些膜层的俯视图；
图10a为根据本公开的一些实施例的一种显示面板中另一些膜层的俯视图；
图10b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图11a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图11b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图12a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图12b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图13a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图13b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图14a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图14b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图14c为图14b所示俯视图沿F-F’向的一种剖视图；
图14d为图14b所示俯视图沿G-G’向的一种剖视图；
图15a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图15b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图15c为图15b所示俯视图沿H-H’向的一种剖视图；
图15d为图15b所示俯视图沿K-K’向的一种剖视图；
图15e为图15b所示俯视图沿M-M’向的一种剖视图；
图16a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图16b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图17a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图17b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图18a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图18b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图19a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图19b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图20a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图20b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图21a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图21b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图22a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图22b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图23a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图23b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图24a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图24b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图25a为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图25b为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图25c为图25b所示俯视图沿N-N’向的一种剖视图；
图25d为图25b所示俯视图沿Q-Q’向的一种剖视图；
图26为根据本公开的一些实施例的一种显示面板中又一些膜层的俯视图；
图27a为根据本公开的一些实施例的又一种显示面板的结构图；
图27b为根据本公开的一些实施例的又一种显示面板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相 近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如像素电路)中，电路结构所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，所采用的各晶体管的控制极为栅极，晶体管的第一极为源极和漏极中一者，晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的实施例中提供的电路结构所包括的晶体管，可以均为N型晶体管，或者可以均为P型晶体管，或者一部分为N型晶体管，另一部分为P型晶体管。在本公开中，“有效电平”指的是，能够使得晶体管导通的电平。其中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，以本公开的实施例中提供的电路结构所包括的晶体管均为P型晶体管为例，进行示意性说明。
本公开的一些实施例提供了一种显示面板100、显示模组1000及显示装置2000，以下对显示面板100、显示模组1000及显示装置2000分别进行介绍。
本公开的一些实施例提供一种显示装置2000，如图1所示。该显示装置2000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机 视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些实施例中，如图1所示，上述显示装置2000包括：显示模组1000。
示例性的，上述显示模组1000可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示模组、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示模组、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示模组或迷你发光二极管(Mini Light Emitting Diodes，简称Mini LED)显示模组等，本公开对此不做具体限定。
示例性的，显示装置2000还包括框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
下面以上述显示模组1000为OLED显示模组为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2所示，显示模组1000包括：显示面板100。
在一些示例中，如图2、图3a和图3b所示，显示面板100具有主显示区A1和辅助显示区A2。
示例性的，如图3a和图3b所示，主显示区A1可以围绕辅助显示区A2。
示例性的，如图3a所示，沿第一方向X，辅助显示区A2可以位于主显示区A1的中部。或者，如图3b所示，沿第一方向X，辅助显示区A2可以位于主显示区A1的一侧。
示例性的，上述显示面板100位于主显示区A1的部分和位于辅助显示区A2的部分均可以用来进行画面显示。
示例性的，显示面板100位于辅助显示区A2的部分的透光率，大于显示面板100位于主显示区A1的部分的透光率。外界光线可以从显示面板100的一侧，穿过显示面板100位于辅助显示区A2的部分，入射至显示面板100的另一侧。
在一些实施例中，显示模组1000还包括：位于显示面板100的出光侧的盖板；以及，位于所述显示面板100的非出光侧的保护层。
示例性的，显示面板100的出光侧为显示面板100显示画面的一侧，显示面板100的非出光侧指的是，与显示面板100出光侧相背的一侧。
示例性，上述盖板的材料可以为透明的玻璃，也可以为透明的有机材料。例如该透明的有机材料包括PI(Polyimide，聚酰亚胺)等。这样可以避免降低显示面板100的出光效率，进而避免影响显示面板100的画面显示。
示例性的，上述保护层的材料可以为透明的有机材料。例如该透明的有机材料包括PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)等。该保护层不仅可以对显示面板100进行支撑，还可以防止显示面板100受到外界的污染和/或刮伤等。
在一些示例中，显示模组1000还包括：位于显示面板100和盖板之间的偏光片。
示例性的，外界光线入射至显示面板100内部后，容易被显示面板100的内部结构反射并从显示面板100的出光侧出射，影响显示面板100的显示质量。
本公开通过在显示面板100和盖板之间设置偏光片，在外界光线穿过盖板及偏光片入射至显示面板100内部、并被显示面板100的内部结构反射后，可以利用上述偏光片对反射后的外界光线进行阻挡，从而避免该反射后的外界光线从显示面板100的出光侧出射，进而可以提高显示面板100的显示质量。
示例性的，显示装置2000还包括：显示模组1000的显示面板100中非出光侧的光学元件200，光学元件200位于显示面板100的辅助显示区A2。
在一些示例中，上述光学元件200位于辅助显示区A2。这样外界光线便可以穿过显示面板100位于辅助显示区A2的部分，入射至光学元件200，被光学元件200采集，进而使得光学元件200能够正常工作。
示例性的，上述光学元件200可以为摄像头、指纹识别传感器以及红外传感器等。
本公开以光学元件200为摄像头为例。
示例性的，在摄像头进行工作的过程中，外界光线可以穿过显示面板100位于辅助显示区A2的部分。这样摄像头便可以采集该光线，实现拍照的功能。例如，在摄像头工作(例如用户自拍)的情况下，上述辅助显示区A2可以呈现黑色画面，主显示区A1呈现用户自拍的画面，较为明确的显示出摄像头所在位置。或者，主显示区A1和辅助显示区A2整体呈现用户自拍的画面，未显示出摄像头所在位置。
示例性的，在摄像头未进行工作的情况下，显示面板100位于主显示区A1的部分能够进行显示，使得显示面板100及显示模组1000整体能够显示图像。
本公开通过对显示面板100的位于辅助显示区A2的部分的透光率进行设置，并将光学元件200设置在辅助显示区A2，既可以确保光学元件200能够正常工作，又能够提高显示面板100、显示模组1000及显示装置2000的显示面积，提高屏占比。
示例性的，如图4a所示，显示面板100包括：多个像素电路10和发光器件20。
例如，上述多个像素电路10和多个发光器件20可以一一对应电连接。又如，在本公开中，一个像素电路10可以与多个发光器件20电连接，或者，多个像素电路10可以与一个发光器件20电连接。
下面，本公开以一个像素电路10与一个发光器件20电连接为例，对显示面板100的结构进行示意性说明。
示例性的，显示面板100中，各发光器件10可以在相应的像素电路20的驱动作用下发出光，多个发光器件10发出的光相互配合，从而使得显示面板100实现显示功能。
例如，发光器件20可以包括依次层叠设置的阳极、发光功能层、阴极等。其中，发光功能层可以包括发光层。可选地，发光功能层还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层中的至少一者。
通过给发光器件20的阴极施加公共电压，并利用相应的像素电路10给发光器件20的阳极施加驱动电压，便可以在阳极和阴极之间形成电场，该电场可以驱动不同的载流子(也即空穴和电子)在发光层中复合，从而使得发光器件20发光。
在一些示例中，上述多个像素电路10包括多个第一像素电路11和多个第二像素电路12。上述多个发光器件20包括第一发光器件21和第二发光器件22。其中，第一像素电路11与第一发光器件21电连接，第一发光器件21在相应的第一像素电路11的驱动作用下发出光。第二像素电路12与第二发光器件22电连接，第二发光器件22在相应的第二像素电路12的驱动作用下发出光。
示例性的，上述多个第一像素电路11和多个第二像素电路12位于主显示区A1，与第一像素电路11电连接的第一发光器件21位于主显示区A1，与第二像素电路12电连接的第二发光器件12位于辅助显示区A2。
可以理解的是，形成像素电路10的材料包括金属材料，以确保像素电路10中电信号 的良好传输。金属材料的透光率较低，对光线的遮挡效果较好。本公开采用上述设置方式，将包括多个第一像素电路11和多个第二像素电路12的多个像素电路10设置在主显示区A1，也就减少了辅助显示区A2中能够对光线进行遮挡的结构，外界光线也便能够从显示面板100位于辅助显示区A2的部分的一侧(例如出光侧)，穿过任意相邻两个第二发光器件12之间的间隙，从显示面板100位于辅助显示区A2的部分的另一侧(例如非出光侧)出射，使得显示面板100位于辅助显示区A2的部分具有较高的透过率。
这样在将显示面板100应用至显示模组1000中，并在显示面板100的非出光侧、且在辅助显示区A2设置光学元件200的情况下，外界光线便可以透过显示面板100位于辅助显示区A2的部分入射至光学元件200，被光学元件200采集，并使得光学元件200能够正常工作。
示例性的，上述第一发光器件21和第一发光器件22的结构可以相同，也可以不同。例如，在本公开中，第一发光器件21和第一发光器件22的结构相同，这样有利于降低显示面板100的制备难度，简化显示面板100的制备工艺。
示例性的，像素电路10的结构可以包括多种，可以根据实际需要选择设置。例如，第一像素电路21或第二像素电路22的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
示例性的，上述第一像素电路11的结构和第二像素电路12的结构及工作过程可以相同，也可以不同。例如。上述第一像素电路11的结构和第二像素电路12的结构及工作过程相同。其中，图7为第一像素电路11的等效电路图，图8为第二像素电路12的等效电路图。
下面结合图7，以像素电路10中第一像素电路11的结构为“7T1C”的结构为例，对像素电路10的结构及工作过程进行示意性说明。需要说明的是，像素电路10所包括的七个晶体管和一个存储电容器之间，还可以具有其他的电连接关系，并不局限于本示例中所示的电连接关系。
可以理解的是，在像素电路10工作的过程中，需要信号线为其提供相应的电信号。因此，示例性的，显示面板100还包括用于传输第一初始信号的第一初始信号线Vinit1、用于传输第三初始信号的第三初始信号线Vinit3、用于传输扫描信号的扫描信号线Scan、用于传输复位信号的复位信号线Reset、用于传输使能信号的使能信号线EM、用于传输数据信号的数据线Data、用于传输电压信号的电压信号线VDD。
示例性的，如图7所示，第一像素电路11包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、开关晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7和存储电容器Cst。
示例性的，如图7所示，第二复位晶体管T7的控制极与复位信号线Reset电连接，第二复位晶体管T7的第一极与第三初始信号线Vinit3电连接，第二复位晶体管T7的第二极与第一节点N1电连接(也即与补偿晶体管T2的第二极电连接)。其中，第二复位晶体管T7被配置为，在复位信号线Reset所传输的复位信号的控制下导通，将从第三初始信号线Vinit3接收的第三初始信号传输至第一节点N1，对第一节点N1进行复位。
示例性的，如图7所示，第一复位晶体管T1的控制极与扫描信号线Scan电连接，第一复位晶体管T1的第一极与第一初始信号线Vinit1电连接，第一复位晶体管T1的第二极 与第四节点N4电连接。其中，第一复位晶体管T1被配置为，在扫描信号线Scan所传输的扫描信号的控制下导通，将从第一初始信号线Vinit1处接收的第一初始信号传输至第四节点N4，对第四节点N4进行复位。
示例性的，如图7所示，开关晶体管T4的控制极与扫描信号线Scan电连接，开关晶体管T4的第一极与数据线Data电连接，开关晶体管T4的第二极与第二节点N2电连接。其中，开关晶体管T4被配置为，在扫描信号线Scan所传输的扫描信号的控制下导通，将数据线Data所传输的数据信号传输至第二节点N2。
示例性的，如图7所示，驱动晶体管T3的控制极与第一节点N1电连接，驱动晶体管T3的第一极与第二节点N2电连接，驱动晶体管T3的第二极与第三节点N3电连接。其中，驱动晶体管T3被配置为，在第一节点N1的电压的控制下导通，将来自第二节点N2的信号(例如为数据信号)传输至第三节点N3。
示例性的，如图7所示，补偿晶体管T2的控制极与扫描信号线Scan电连接，补偿晶体管T2的第一极与第三节点N3电连接，补偿晶体管T2的第二极与第一节点N1电连接。其中，补偿晶体管T2被配置为，在扫描信号线Scan所传输的扫描信号的控制下导通，将来自第三节点N3的信号(例如为数据信号)传输至第一节点N1。
示例性的，如图7所示，第一发光控制晶体管T5的控制极与使能信号线EM电连接，第一发光控制晶体管T5的第一极与电压信号线VDD电连接，第一发光控制晶体管T5的第二极与第二节点N2电连接。其中，第一发光控制晶体管T5被配置为，在使能信号线EM所传输的使能信号的控制下导通，将从电压信号线VDD接收的电压信号传输至第二节点N2。
示例性的，如图7所示，第二发光控制晶体管T6的控制极与使能信号线EM电连接，第二发光控制晶体管T6的第一极与第三节点N3电连接，第二发光控制晶体管T6的第二极与第四节点N4电连接。其中，第二发光控制晶体管T6被配置为，在使能信号线EM所传输的使能信号的控制下导通，将来自第三节点N3的电压信号传输至第四节点N4。
示例性的，如图7所示，存储电容器Cst的第一极与第一节点N1电连接，存储电容器Cst的第二极与电压信号线VDD电连接。
示例性的，第一像素电路11的工作过程包括依次进行的复位阶段、数据写入及补偿阶段、发光阶段。
例如，在复位阶段，在复位信号的控制下，第二复位晶体管T7导通，将第三初始信号V3传输至第一节点N1，对第一节点N1进行复位。由于第一节点N1与存储电容器Cst、驱动晶体管T3的控制极及补偿晶体管T2的第二极电连接，因此，在对第一节点N1复位时，便可以对存储电容器Cst、驱动晶体管T3的控制极及补偿晶体管T2的第二极进行复位。其中，驱动晶体管T3可以在第三初始信号的控制下导通。
例如，在数据写入及补偿阶段，第一复位晶体管T1、开关晶体管T4和补偿晶体管T2，在扫描信号的控制下同时导通。第一复位晶体管T1将第一始信号传输至第四节点N4。由于第四节点N4与第一发光器件21的阳极电连接，因此，在对第四节点N4进行复位时，便可以对第一发光器件21的阳极进行复位。开关晶体管T4将数据信号传输至第二节点N2，驱动晶体管T3在第一节点N1的控制下导通，将来自第二节点N2的数据信号传输至第三节点N3。补偿晶体管T2将来自第三节点N3的数据信号传输至第一节点N1，对驱动晶体管T3进行充电，直至驱动晶体管T3处于截止状态，完成对驱动晶体管T3的阈值电 压的补偿。
例如，在发光阶段，第一发光控制晶体管T5和第二发光控制晶体管T6在使能信号的控制下同时导通。第一发光控制晶体管T5将电压信号传输至第二节点N2。驱动晶体管T3将来自第二节点N2的电压信号传输至第三节点N3。第二发光控制晶体管T6将来自第三节点N3的电压信号传输至第四节点N4。
第一发光器件21在来自第四节点N4的电压信号和来自公共电压线VSS的公共电压的作用下，发光。
在一种实现方式中，第一像素电路11的第一复位晶体管T1的第一极，及第二像素电路12的第一复位晶体管T1的第一极均与第一初始信号线Vinit1电连接。第一像素电路11的第一复位晶体管T1所接收的第一初始信号，与第二像素电路12的第一复位晶体管T1所接收的第一初始信号，为相同的信号，也即，两者所接收的第一初始信号的电压值相同。由于第一发光器件21与第一像素电路11均位于主显示区A1，两者相隔距离较小，相应的，第一发光器件21与第一像素电路11中的第四节点N4相隔距离较小，第一初始信号线Vinit1提供的第一初始信号经第一像素电路11的第四节点N4传输至第一发光器件21后，电压值的损耗较小。而第二发光器件22位于辅助显示区A2，与其电连接的第二像素电路12位于主显示区A1，第二像素电路12与第二发光器件22相隔距离较大，相应的，第二像素电路12中的第四节点N4与第二发光器件22相隔距离较大，使得第一初始信号线提供的第一初始信号经第二像素电路12中的第四节点N4传输至第二发光器件22后，电压值的损耗较大。这样导致第二发光器件22实际接收的第一初始信号的电压值与预设接收的第一初始信号的电压值之间具有偏差，导致对第二发光器件22的阳极的复位效果不好，进而在发光阶段，容易使得第二发光器件22的阳极无法达到预设电压，进而导致第二发光器件22的发光亮度无法达到预设亮度。在第一发光器件21与第二发光器件22的预设亮度相同的情况下，容易造成辅助显示区A2与主显示区A1的发光亮度不同，造成主显示区A1和辅助显示区A2显示效果不同，导致显示面板100产生显示不均匀现象。
基于此，本公开的一些实施例所提供的显示面板100中，如图4a所示，显示面板100包括：多条第一初始信号线Vinit1和多条第二初始信号线Vinit2。该多条第一初始信号线Vinit1和多条第二初始信号线Vinit2例如可以沿第一方向X延伸。
在一些示例中，第一像素电路11，与第一初始信号线Vinit1及第一发光器件11电连接，被配置为，与第一初始信号线Vinit1及第一发光器件21电连接，且被配置为，将第一初始信号线Vinit1所传输的第一初始信号传输至第一发光器件21，对第一发光器件21进行复位。第二像素电路12，与第二初始信号线Vinit2及第二发光器件22电连接，被配置为，与第二初始信号线Vinit2及第二发光器件22电连接，且被配置为，将第二初始信号线Vinit2所传输的第二初始信号传输至第二发光器件22，对第二发光器件22进行复位。
示例性的，第一像素电路11中的第一复位晶体管T1(例如第一复位晶体管的第一极)与第一初始信号线Vinit1电连接。第二像素电路12中的第一复位晶体管T1(例如第一复位晶体管的第一极)与第二初始信号线Vinit2电连接，第二像素电路12中的第一复位晶体管T1(例如第一复位晶体管的第二极)与第二发光器件22电连接，第二像素电路12中的第一复位晶体管T1被配置为，将第二初始信号线Vinit2所传输的第二初始信号传输至第二发光器件22。例如可以利用第二初始信号对第二发光器件22的阳极进行复位。
示例性的，第二像素电路12中其他晶体管和存储电容器的连接关系，及第二像素电路 12的工作过程，可以参照上述一些示例中对第一像素电路11的说明，此处不再赘述。
在一些示例中，第二初始信号的电压值V2大于第一初始信号的电压值V1。
示例性的，第一发光器件21的阳极在第一初始信号线Vinit1所传输的第一初始信号的作用下复位，在第一初始信号传输至第一发光器件21后，V1的损耗值为△V1。第二发光器件22的阳极在第二初始信号线Vinit2所传输的第二初始信号的作用下复位，在第二初始信号传输至第二发光器件22后，V2的损耗值为△V2。由于第二发光器件22位于辅助显示区A2，与其电连接的第二像素电路12位于主显示区A1，第二像素电路12与第二发光器件22相隔距离较远，使得第二初始信号电压值的损耗值△V2大于第一初始信号电压值的损耗值△V1，即△V2＞△V1，而本公开设置V2＞V1，使得第二发光器件22收到的信号的电压值V2-△V2，与第一发光器件21接收到的信号的电压值V1-△V1相等或趋近于相等，进而使得对第一发光器件21的复位效果和对第二发光器件22的复位效果相同或大致相同。这样一来，在发光阶段，可以使得第二发光器件22的阳极的电压达到或接近预设发光电压，使得第二发光器件22的发光亮度可以达到预设亮度。在第一发光器件21和第二发光器件22的预设发光亮度相同的情况下，可以使得第一发光器件21和第二发光器件22的实际发光亮度能够相同或大致相同。这样有利于使得主显示区A1和辅助显示区A2显示效果一致或趋近于一致，进而可以提供显示面板100的显示品质。
本公开的一些实施例提供的显示面板100，通过将第一像素电路11与位于主显示区A1的第一发光器件21电连接，将第二像素电路12与位于辅助显示区A2的第二发光器件22电连接，并设置位于第一初始信号线Vinit1和第二初始信号线Vinit2，将第一初始信号线Vinit1与第一像素电路11电连接，为第一像素电路11提供第一初始信号，使得第一发光器件21能够在第一初始信号的作用下复位；并将第二初始信号线Vinit2与第二像素电路12电连接，为第二像素电路12提供第二初始信号，使得第二发光器件22在第二初始信号的作用下复位。本公开通过设置第二初始信号的电压值V2大于第一初始信号的电压值V1，可以使得第一初始信号对第一发光器件21的复位效果和第二初始信号对第二发光器件22的复位效果相同大致相同，进而在发光阶段中，可以使得第二发光器件22的阳极能够达到或接近预设发光电压，使得第二发光器件22的实际发光亮度达到或趋近于预设发光亮度，进而可以保证主显示区A1和辅助显示区A2显示效果相同或趋近于相同，提供显示面板100的显示品质。
在一些示例中，上述显示面板100还包括：多条连接线30。
示例性的，一个第二像素电路12与一个第一发光器件22通过一条连接线30电连接，第二像素电路12提供的驱动电压，可以经相应的连接线30传输至相应的第二发光器件22，以驱动该相应的第二发光器件22发光。第二像素电路12的第一复位晶体管T1所传输的第二初始信号，也可以经相应的连接线30传输至相应的第二发光器件22，对相应的第二发光器件22进行复位。
示例性的，上述多条连接线30的材料包括可透光的导电材料。
例如，上述可透光的导电材料可以为ITO(Indium Tin Oxide，氧化铟锡)等材料。
上述可透光的导电材料具有较高的透光率，采用上述可透光的导电材料形成连接线，可以使得连接线30具有较高的透光率，在光线透过连接线30后光线自身的损耗较少，进而可以保证穿过显示面板位于辅助显示区的部分、并入射至光学元件200的光线量较为充足，进而可以保证光学元件200能够正常工作。
示例性的，第二像素电路12、第一发光器件22、连接线30之间的电连接的方式有多种，本公开对此不做限制。
例如，如图4b所示，第二像素电路12与第二发光器件22可以采用“近接近，远接远”的方式进行连接，也就是说，图4b中，位于主显示区A1与辅助显示区A2的分界线相对两侧的第二像素电路12和第二发光器件22中，距离该分界线最近的第二像素电路12与距离该分界线最近的第二发光器件22相互电连接，此时，连接两者的连接线30的长度最短。距离该分界线第二近的第二像素电路12与距离该分界线第二近的第二发光器件22相互电连接，此时，连接两者的连接线30的长度为第二短，……，距离该分界线最远的第二像素电路12与距离该分界线最远的第二发光器件22相互电连接，此时，连接两者的连接线30的长度最长。
又如，如图4a所示，位于主显示区A1与辅助显示区A2的分界线相对两侧的第二像素电路12和第二发光器件22中，距离该分界线最近的第二像素电路12与距离该分界线最远的第二发光器件22相互电连接。距离该分界线第二近的第二像素电路12与距离该分界线第二远的第二发光器件22相互电连接，……，距离该分界线最远的第二像素电路12与距离该分界线最近的第二发光器件22相互电连接。上述多条连接线的长度例如相同。
在一些示例中，第二初始信号的电压值V2与第一初始信号的电压值V1之差△V，与连接线30的长度，呈正相关。也即，连接线30的长度越长，第二初始信号的电压值V2与第一初始信号的电压值V1之差△V越大，相应的，第二初始信号的电压值V2越大。
可以理解的是，连接线30自身具有电阻。在第二像素电路12和第二发光器件22之间设置连接线30后，会在两者之间形成电阻，该电阻如图8中第四节点N4与第二发光器件之间的R 30所示。
示例性的，第二像素电路12与第二发光器件22间隔的距离越长，连接两者的连接线30的长度越长，相应的，该连接线30的电阻R 30越大。第二初始信号在经该连接线30传输至第二发光器件22的传输的过程中，所产生的损耗△V2越大。例如第一初始信号的电压值V1的损耗值△V1相对于△V2可以忽略不计，此时，第二初始信号的电压值V2与第一初始信号的电压值V1之差△V，则为△V2。因此，通过设置第二初始信号的电压值V2与第一初始信号的电压值V1之差△V，与连接线30的长度呈正相关，便可以在连接线30的长度较小时，设置具有较小电压值的第二初始信号，在连接线30的长度较大时，设置具有较大电压值的第二初始信号。这样可以使得第二发光器件22实际接收的第二初始信号的电压值(也即V2-△V2)与V1的值相同或大致相同，进而使得第二初始信号对第二发光器件22的复位效果与第一初始信号对第一发光器件21的复位效果相同或大致相同，使得在发光阶段，第二发光器件22的阳极电压可以达到或趋近于预设发光电压，使得第二发光器件22的实际发光亮度达到或趋近于预设发光亮度，减小主显示区A1和辅助显示区A2的显示差异，从而可以提供显示面板100的显示品质。
在一些实施例中，如图25c所示，显示面板100包括：依次层叠设置的衬底101、像素电路层102、多个连接层103、发光器件层104。
在一些示例中，上述衬底101可以为柔性衬底，也可以为刚性衬底。
示例性的，在衬底101为柔性衬底的情况下，衬底101的材料可以为二甲基硅氧烷、PI(Polyimide，聚酰亚胺)、PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)等具有高弹性的材料。
示例性的，在衬底101为刚性衬底的情况下，衬底101的材料可以为玻璃等。
示例性的，显示面板100所包括的多个像素电路10可以位于上述像素电路层，显示面板100所包括的多个发光器件20可以位于上述发光器件层，显示面板100所包括的多条连接线可以位于上述多个连接层。
下面结合附图，分别对像素电路层102、连接层103和发光器件层104进行介绍。
在一些实施例中，像素电路层102包括：依次层叠设置在衬底101一侧的半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PLN1和第二源漏导电层SD2。其中，半导体层Poly和第一栅导电层Gate1之间可以设置有第一栅绝缘层GI1，第一栅导电层Gate1和第二栅导电层Gate2之间可以设置有第二栅绝缘层GI2。
示例性，第一栅绝缘层GI1、第二栅绝缘层GI2、层间介质层ILD及第一平坦层PLN1，均可以对位于各自相对两侧的导电层进行隔离，避免位于各自相对两侧的导电层形成短接。
其中，图9示意出了半导体层Poly的俯视结构。图10a示意出了第一栅导电层Gate1的俯视结构。图10b示意出了半导体层Poly与第一栅导电层Gate1依次层叠设置后的俯视结构。图11a示意出了第二栅导电层Gate2的俯视结构。图11b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2依次层叠设置后的俯视结构。图12a示意出了层间介质层ILD的俯视结构。图12b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD依次层叠设置后的俯视结构。图13a示意出了第一源漏导电层SD1的俯视结构。图13b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1依次层叠设置后的俯视结构。图14a示意出了第一平坦层PLN1的俯视结构。图14b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL依次层叠设置后的俯视结构。图15a示意出了第二源漏导电层SD2的俯视结构。图15b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PLN1、第二源漏导电层SD2依次层叠设置后的俯视结构。
示例性的，半导体层Poly的材料可以包括非晶硅、单晶硅、多晶硅或金属氧化物半导体材料。
示例性的，第一栅导电层Gate1、第二栅导电层Gate2、第一源漏导电层SD1和第二源漏导电层SD2的材料均为可导电材料。第一栅导电层Gate1和第二栅导电层Gate2的材料例如可以相同，第一源漏导电层SD1和第二源漏导电层SD2的材料例如可以相同。
例如，第一栅导电层Gate1、第二栅导电层Gate2、第一源漏导电层SD1或第二源漏导电层SD2的材料可以为金属材料，该金属材料例如为Al(铝)、Ag(银)、Cu(铜)、Cr(铬)等。
需要说明的是，半导体层Poly在衬底上的正投影，与第一栅导电层Gate1在衬底上的正投影具有交叠。其中，在半导体层Poly远离衬底的一侧形成第一栅导电层Gate1后，可以第一栅导电层Gate1为掩膜，对半导体层Poly进行掺杂处理，使得半导体层Poly中被第一栅导电层Gate1覆盖的部分，构成各晶体管的有源图案，使得半导体层Poly中未被第一栅导电层Gate1覆盖的部分，构成导体，该导体可以构成各晶体管的第一极或第二极。第一栅导电层Gate1与半导体层Poly交叠的部分，构成各晶体管的栅极图案(也即控制极)。
示例性的，像素电路10所包括的各晶体管及存储电容器之间的相对位置关系如图15b所示。沿第一方向X，补偿晶体管T2和开关晶体管T4同行设置，第一发光控制晶体管T5和第二发光控制晶体管T6同行设置。沿第二方向Y，开关晶体管T4和第一发光控制晶体管T5同列设置，补偿晶体管T2、第二发光控制晶体管T6和第一复位晶体管T1同列设置、且依次排列。沿第一方向X，驱动晶体管T3位于补偿晶体管T2和开关晶体管T4之间；沿第二方向Y，驱动晶体管T3还位于开关晶体管T4和第一发光控制晶体管T5之间。沿第一方向X，第二复位晶体管T7位于补偿晶体管T2和开关晶体管T4之间；沿第二方向Y，第二复位晶体管T7还位于开关晶体管T4远离第一发光控制晶体管T5的一侧。其中，存储电容器Cst的位置，与驱动晶体管T3的位置相同，且存储电容器Cst位于驱动晶体管T3远离衬底101的一侧。
在一些实施例中，如图9、图10a、图10b及图14c所示，上述像素电路10中的补偿晶体管T2包括：依次层叠设置的有源图案p2及栅极图案g2。
示例性的，上述有源图案t2可以位于显示面板100的半导体层Poly，栅极图案g2可以位于显示面板100的第一栅导电层Gate1。
在一些示例中，如图9所示，有源图案p2包括依次连接的第一半导体部p21、导体部p22和第二半导体部p23。
示例性的，有源图案p2的形状包括多种，可以根据实际需要选择设置。
例如，有源图案p2呈直线状。可选地，第一半导体部p21、导体部p22和第二半导体部p23，沿第一方向X依次排列，或者，沿第二方向Y依次排列。
又如，有源图案p2呈折线状。可选地，第一半导体部p21可以沿第一方向X延伸，第二半导体部p23可以沿第二方向Y延伸，导体部p22可以呈折线状，导体部p22的一端连接第一半导体部p21，导体部p22的另一端连接第二半导体部p23。这样有利于减小有源图案p2在第一方向X或第二方向Y上的占据面积。
示例性的，第一方向X与第二方向Y相交。例如，第一方向X与第二方向Y的夹角可以为85°、90°或95°等。
本公开中以第一方向X与第二方向Y的夹角为90°为例进行说明。
在一些示例中，如图10a所示，栅极图案g2包括相连接的第一子栅极g21和第二子栅极g22。第一半导体部p21和第一子栅极g21部分正对设置，第二半导体部p23和第二子栅极g22部分正对设置。
示例性的，栅极图案g2的设置方式，与有源图案p2的形状相对应。
例如，在有源图案p2呈直线状的情况下，第一子栅极g21和第二子栅极g22可以沿同一方向延伸，且该延伸方向与有源图案p2中第一半导体部p21、导体部p22和第二半导体部p23的排列方向相交。
又如，如图10a所示，在有源图案p2呈折线状的情况下，第一子栅极g21和第二子栅极g22可以沿不同的方向延伸。可选地，第一子栅极g21可以沿第二方向Y延伸，第二子栅极g22可以沿第一方向X延伸。在第一子栅极g21和第二子栅极g22的延伸方向上，第一子栅极g21和第二子栅极g22的交汇图形呈折线状，且该交汇图形在衬底上的正投影与导体部p22在衬底上的正投影无交叠，交汇图形的拐角与导体部p22的拐角相对。
需要说明的是，第一半导体部p21和第一子栅极g21部分正对设置，指的是，第一子栅极g21在衬底101上的正投影与第一半导体部p21衬底101上的正投影部分重合，第一 子栅极g21在衬底101上的正投影的边界与第一半导体部p21衬底101上的正投影的边界部分相交叉。第二半导体部p23和第二子栅极g22部分正对设置，指的是，第二子栅极g22在衬底101上的正投影与第二半导体部p23在衬底101上的正投影部分重合，第二子栅极g22在衬底101上的正投影的边界与第二半导体部p23在衬底101上的正投影的边界部分相交叉。
示例性的，上述补偿晶体管T2为双栅晶体管。采用双栅晶体管作为补偿晶体管T2，可以提高像素电路10的防漏电性能，减小第一节点N1通过补偿晶体管T2的漏电流或者避免第一节点N1通过补偿晶体管T2漏电，从而在发光阶段，可以确保第一节点N1的电压的稳定性，保证发光器件20的正常发光。
在一些示例中，如图11a、图11b及图14c所示，显示面板100还包括：与第三初始信号线Vinit3电连接的屏蔽块B。屏蔽块B与导体部p22，部分正对设置。
示例性的，导体部p22在衬底101上的正投影，与屏蔽块B在衬底101上的正投影部分重合，导体部p22在衬底101上的正投影的边界与屏蔽块B在衬底101上的正投影的边界部分相交叉。
示例性的，屏蔽块B的材料为金属材料，且屏蔽块B和导体部p22之间间隔设置有绝缘层。此时，屏蔽块B和导体部p22可以构成一电容器。
由于第三初始信号线Vinit3传输的第三初始信号为恒压信号，且屏蔽块B与第三初始信号线Vinit3电连接，因此，屏蔽块B上也具有上述恒压信号。由于电容器两端的压差基本保持不变，因此，导体部p22上的电压基本为恒定的电压。
通过将屏蔽块B对补偿晶体管T2的导体部p22进行遮挡，这样可以提高上述屏蔽块B与导体部p22构成的电容器对导体部p22上电位的保持作用，使得补偿晶体管T2上导体部p22处的电压相对于补偿晶体管T2的第一极和第二极的电压保持相对稳定，从而可以显著降低形成漏电流的风险，保证像素电路10工作时具有较高的可靠性。
在一些示例中，屏蔽块B与第三初始信号线Vinit3为一体结构。
示例性的，“一体结构”指的是，相连接的两个图案同层设置，且该两个图案是连续的，未分隔开。也即，本公开中，屏蔽块B与第三初始信号线Vinit3位于同一膜层(例如均位于第二栅导电层Gate2)，且屏蔽块B与第三初始信号线Vinit3相互电连接，两者连续、未分隔开。
这样不仅可以简化显示面板100的制作工艺，还可以减小屏蔽块B与第三初始信号线Vinit3所占据区域在第二方向Y上的尺寸，减小屏蔽块B与第三初始信号线Vinit3所占据的面积，为其他膜层的布局提供较大的空间，有效的利用显示面板100的设计空间。
在一些示例中，第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3同层设置。
本公开中所提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以同时制作第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3，有利于简化显示面板100的制作工艺。
在一些示例中，显示面板100所包括的多个像素电路10可以排列为多行。其中，每行 像素电路10所包括的多个像素电路10可以沿第一方向X依次排列。任意相邻两行像素电路10所包括的像素电路的数量可以相同，也可以不同。
示例性的，任意相邻两行像素电路10之间，可以设置有第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3。第一初始信号线Vinit1的数量可以为至少一条，第二初始信号线Vinit2的数量可以为至少一条，第三初始信号线Vinit3的数量可以为至少一条。
例如，如图14b所示，任意相邻两行像素电路10之间，可以设置一条第一初始信号线Vinit1、一条第二初始信号线Vinit2和一条第三初始信号线Vinit3。
示例性的，任意相邻两行像素电路10之间所设置的第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3，沿第一方向X延伸，且沿第二方向Y依次排列。其中，该第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3，沿第二方向Y排列的顺序，可以包括多种。
示例性的，第三初始信号线Vinit3，相比于第一初始信号线Vinit1和第二初始信号线Vinit2更靠近与该第三初始信号线Vinit3电连接的补偿晶体管T2。第一初始信号线Vinit1和第二初始信号线Vinit2中的一者，更靠近第三初始信号线Vinit3。
这样可以使得第三初始信号线Vinit3及与其电连接的屏蔽块B呈一体结构，简化显示面板100的膜层复杂度。
在一些示例中，如图14b所示，任意相邻两行像素电路10之间，还可以设置有与补偿晶体管T2的控制极电连接的复位信号线Reset。复位信号线Reset例如沿第一方向X延伸。
上述复位信号线Reset，和设置在任意相邻两行像素电路10之间的第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3之间，具有多种设置方式。
示例性的，复位信号线Reset在衬底101上的正投影，位于第一初始信号线Vinit1在衬底101上的正投影及第二初始信号线Vinit2在衬底101上的正投影之间。
示例性的，如图11b所示，复位信号线Reset在衬底101上的正投影，位于第二初始信号线Vinit2在衬底101上的正投影及第三初始信号线Vinit3在衬底101上的正投影之间。
采用上述设置方式，可以优化显示面板100的第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3及复位信号线Reset的排布空间，避免第三初始信号线Vinit3跨过复位信号线Reset与相应的屏蔽块B实现电连接，从而既可以确保第三初始信号线Vinit3及与其电连接的屏蔽块B呈一体结构，还可以避免复位信号线Reset所传输的复位信号对屏蔽块B上的电信号产生影响，确保屏蔽块B对补偿晶体管T2的良好遮挡作用，保证发光器件20的正常发光。
在一些示例中，如图11a及图11b所示，复位信号线Reset位于第一栅导电层Gate1。第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3位于第二栅导电层Gate2。
采用上述设置方式，可以避免复位信号线Reset与第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3之间产生信号干扰，从而保证复位信号线Reset、第一初始信号线Vinit1、第二初始信号线Vinit2和第三初始信号线Vinit3传输的电信号的准确性。此外，采用上述设置方式，还可以增大布线空间。
示例性的，图14d中所示的像素电路10例如为第n行像素电路。该第n行像素电路的第一复位晶体管T1的控制极，可以与第n条复位信号线Reset(n)电连接。
示例性的，如图14d所示，显示面板100还包括位于第一源漏导电层SD1的第一换层块HC1。第二像素电路12的第一复位晶体管T1第一极通过第一换层块HC1实现与第n条第二初始信号线Vinit2(n)的电连接。第一换层块HC1的一端可以通过依次贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔，与第一复位晶体管T1位于半导体层Poly的第一极(该第一极位于半导体层Poly中的导体)电连接，第一换层块HC1的另一端可以通过贯穿层间介质层ILD的过孔，与位于第二栅导电层Gate2的第n条第二初始信号线Vinit2(n)电连接。
示例性的，显示面板100还包括位于第一源漏导电层SD1的第二换层块HC2。第一像素电路10的第一复位晶体管T1第一极通过第二换层块HC2实现与第n条第一初始信号线Vinit1(n)的电连接。第二换层块HC2的一端可以通过依次贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔，与第一复位晶体管T1位于半导体层Poly的第一极(该第一极位于半导体层Poly中的导体)电连接，第一换层块HC1的另一端可以通过贯穿层间介质层ILD的过孔，与位于第二栅导电层Gate2的第n条第一初始信号线Vinit1(n)电连接。
在一些示例中，如图11a所示，同一行像素电路10的多个像素电路中，至少两个存储电容器Cst的第二极板C2相互连接，呈一体结构。
也即，同一行像素电路10的多个像素电路10中，至少两个存储电容器Cst的第二极板C2位于显示面板100的同一膜层(例如均位于第二栅导电层Gate2)，至少两个存储电容器Cst的第二极板C2之间是连续的，未分隔开。
示例性的，同一行像素电路10的多个像素电路中，相邻的两个、三个、五个甚至更多个(例如上述多个像素电路的)存储电容器Cst的第二极板C2相互连接，呈一体结构。
通过采用上述设置方式设置位于同一行的存储电容器Cst的第二极板C2，不仅可以简化显示面板100的制作工艺，还可以提高上述第二极板C2的排列规则程度。
在一些示例中，如图6所示，显示面板100所包括的多个像素电路10可以排列为多列。其中，每列像素电路所包括的多个像素电路可以沿第二方向Y依次排列。任意相邻两列像素电路所包括的像素电路的数量可以相同，也可以不同。
示例性的，如图15b所示，与像素电路电连接的电压信号线VDD的数量可以为多条，该多条电压信号线VDD沿第二方向Y延伸，并沿第一方向X依次排列。一条电压信号线VDD例如与一列像素电路10的存储电容器Cst的第二极板C2电连接。
例如，多条电压信号线VDD所传输的电压信号为恒压信号。
可选地，一条电压信号线VDD例如还可以与两列、三列或更多列像素电路的10存储电容器Cst的第二极板C2电连接。
采用上述设置方式，可以利用一条电压信号线VDD同时为多个存储电容器Cst的第二极板C2提供电压信号，提高电压信号的传输效果。
由于同一行像素电路10的多个像素电路10中，至少两个存储电容器Cst的第二极板C2相互连接呈一体结构，这样可以使得至少部分甚至所有的存储电容器Cst的第二极板C2及与其电连接的电压信号线VDD构成网格状结构。这样不仅有利于减小电压信号线VDD中的压降，提高存储电容器Cst的第二极板C2接收到的电压值的稳定性、均一性， 保证存储电容器Cst两极板的电信号的稳定性，还有利于降低显示面板100出现异常的概率，即使部分电压信号线VDD出现断路现象，仍可以确保相应的存储电容器Cst的第二极板能够从与其呈一体结构的存储电容器Cst的第二极板处接收电压信号。
在一些示例中，存储电容器Cst的第二极板和电压信号线VDD位于不同层。
示例性的，如图11a及图15b所示，存储电容器Cst的第二极板位于第二栅导电层Gate2，多条电压信号线VDD位于第二源漏导电层SD2。
这样不仅可以增大布线空间，还有利于降低存储电容器Cst的第二极板和电压信号线VDD的布线难度。
示例性的，如图7、图8及图15c所示，显示面板还包括位于第一源漏导电层的第三换层块HC3。电压信号线VDD可以通过贯穿第一平坦层PLN1的过孔，与第三换层块HC3接触，形成电连接。第三换层块HC3的一端可以通过贯穿层间介质层ILD的过孔与存储电容器Cst的第二极板C2接触，形成电连接。这样存储电容器Cst的第二极板便可以通过第三换层块HC3实现与电压信号线VDD的电连接。第三换层块HC3的另一端可以通过依次贯穿层间介质层、第二栅绝缘层和第一栅绝缘层的过孔，与第一发光控制晶体管T5的第一极接触，形成电连接。这样第一发光控制晶体管T5的第一极便可以通过第三换层块HC3实现与电压信号线VDD的电连接。
在一些示例中，如图13a、图15a及图15b所示，像素电路10还包括：连接补偿晶体管T2的第二极与存储电容器Cst的第一极板C1的转接部Z。转接部Z位于第一源漏导电层SD1。
示例性的，如图11a所示，存储电容器Cst的第二极板C2具有开口，该开口在衬底上的正投影，位于存储电容器Cst的第一极板C1在衬底101上的正投影范围内。也即，第二极板C2中的开口会暴露存第一极板C1的一部分。
例如，如图15d所示，转接部Z的一端，可以通过依次贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔，与补偿晶体管T2的第二极d2接触、形成电连接。转接部Z的另一端，可以通过依次贯穿层间介质层ILD和第二栅绝缘层GI2、且位于上述开口内的过孔，与存储电容器Cst的第一极板C1接触、形成电连接。
示例性的，将转接部Z设置在第一源漏导电层SD1，可以利用转接部Z在补偿晶体管T2的第二极与存储电容器Cst的第一极板C1之间形成桥接，避免因两者直接电连接而与扫描信号线形成短接，降低布线难度，提高电连接的准确性。
示例性的，转接部Z在衬底101上的正投影位于电压信号线VDD在衬底101上的正投影范围之内。
也即，转接部Z在衬底101上的正投影面积，小于电压信号线VDD在衬底101上的正投影面积。转接部Z在衬底101上的正投影的边界与电压信号线VDD在衬底101上的正投影的边界部分重合，或者，转接部Z在衬底101上的正投影的边界与电压信号线VDD在衬底101上的正投影的边界均有一定的间距。
采用上述设置方式，可以使得电压信号线VDD完全覆盖转接部Z，对转接部Z进行遮挡屏蔽。这样可以避免第一节点N1和第四节点N4产生交叠，进而可以避免位于电压信号线VDD远离衬底一侧的膜层(例如发光器件20的阳极层AND或连接层等)与转接部Z之间形成寄生电容，进而对转接部Z传输的信号及上述膜层传输的信号形成干扰。
在一些示例中，如图14a、图14b、图15a及图15e所示，第一平坦层PLN1上设置有 第一过孔H1和第二过孔H2。
示例性的，上述第一过孔H1和第二过孔H2还会向衬底延伸，并依次贯穿层间介质层、第二栅绝缘层和第一栅绝缘层。其中，第一过孔H1会暴露第一发光控制晶体管T5的第一极s5，第二过孔H2会暴露第二发光控制晶体管T6的第二极d6。
例如，第一发光控制晶体管T5的第一极s5可以通过第一过孔H1与电压信号线VDD电连接，第二发光控制晶体管T6的第二极d6通过第二过孔H2与发光器件20电连接。
例如，第一平坦层PLN1一般采用透明材料制作而成，因此，图14a仅示出了PLN1上过孔的位置。
示例性的，第一平坦层PLN1上还设置有第三过孔H3。开关晶体管T4的第一极通过第三过孔H3与数据线Data电连接。
示例性的，与同一像素电路中，第一发光控制晶体管T5和第二发光控制晶体管T6的控制极电连接使能信号线EM，位于第一栅导电层Gate1。且与该第一发光控制晶体管T5和第二发光控制晶体管T6相对应的第一过孔H1及第二过孔H2在衬底101上的正投影，位于该使能信号线EM在衬底101上的正投影范围之内。
采用上述设置方式，可以使得第一平坦层PLN1上的第一过孔H1及第二过孔H2排列规整，便于制作，此外，上述设置方式也可以使得显示面板100在第二方向Y上占据的空间较小，节省空间，有利于其他膜层(例如下文中提到的第一连接层ITO1、第二连接层ITO2、第三连接层ITO3、阳极层AND等)在第二方向Y上的排布设计。
在一些实施例中，如图16a～图21b所示，显示面板100中多个连接层的数量，可以为至少两个。例如，连接层的数量可以为两个、三个、四个或者更多个。
示例性的，显示面板100所包括的多条连接线30可以位于上述多个连接层103，每个连接层103包括至少一条连接线30。
在一些示例中，每个连接层103还可以包括至少一个连接部1031。位于同一层连接层的连接部1031及连接线30之间，相互独立设置。
在一些示例中，如图25c所示，连接层的数量可以为三个。该三个连接层103包括：设置在第二源漏导电层SD2远离衬底的一侧、且沿远离衬底的方向依次层叠的第一连接层CO1、第二连接层CO2、第三连接层CO3。
示例性的，第二源漏导电层SD2与第一连接层CO1之间设置有第二平坦层PLN2，第一连接层CO1与第二连接层CO2之间设置有第三平坦层PLN3，第二连接层CO2与第三连接层CO3之间设置有第四平坦层PLN4。第三连接层CO3与发光器件层之间设置有第五平坦层PLN5。
其中，图16a示意出了第二平坦层PLN2的俯视结构。图16b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2依次层叠设置后的俯视结构。图17a示意出了第一连接层CO1的俯视结构。图17b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1依次层叠设置后的俯视结构。图18a示意出了第三平坦层PLN3的俯视结构。图18b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3依 次层叠设置后的俯视结构。图19a示意出了第二连接层CO2的俯视结构。图19b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2依次层叠设置后的俯视结构。图20a示意出了第四平坦层PLN4的俯视结构。图20b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4依次层叠设置后的俯视结构。图21a示意出了第三连接层CO3的俯视结构。图21b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4、第三连接层CO3依次层叠设置后的俯视结构。
示例性的，如图16a～图21b所示，为了方便看出图中各膜层位置及形貌特征，上述第二平坦层PLN2、第三平坦层PLN3、第四平坦层PLN4、第五平坦层PLN5仅在图中示意出了过孔的位置。
另外，图22a示意出了第五平坦层PLN5的俯视结构。图22b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4、第三连接层CO3、第五平坦层PNL5依次层叠设置的俯视结构。图23a示意出了阳极层AND的俯视结构。图23b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4、第三连接层CO3、第五平坦层PNL5、阳极层AND依次层叠设置后的俯视结构。
示例性的，第一像素电路11的第二发光控制晶体管T6的第二极，可以依次通过位于第二源漏导电层SD2的连接部1031、位于第一连接层CO1的连接部1031、位于第二连接层CO2的连接部1031以及位于第三连接层CO3的连接部1031，与第一发光器件21的阳极层AND的阳极电连接。其中，第一发光器件21的阳极层AND可以通过贯穿第五平坦层PLN5的过孔与位于第三连接层CO3的连接部1031电连接，位于第三连接层CO3的连接部1031可以通过贯穿第四平坦层PLN4的过孔与位于第二连接层CO2的连接部1031电连接，位于第二连接层CO2的连接部1031可以通过贯穿第三平坦层PLN3的过孔与位于第一连接层CO1的连接部1031电连接，位于第一连接层CO1的连接部1031可以通过贯穿第二平坦层PLN2的过孔与位于第二源漏导电层SD2的连接部1031电连接，位于第二源漏导电层SD2的连接部1031可以通过贯穿第一平坦层PLN1的过孔与第一像素电路的第二发光控制晶体管T6的第二极电连接。
示例性的，一部分第二像素电路12的第二发光控制晶体管T6的第二极，可以通过位于第二源漏导电层SD2的连接部1031与位于第一连接层CO1的连接线30的一端电连接，该连接线30的另一端可以依次通过位于第二连接层CO2的连接部1031以及位于第三连接层CO3的连接部1031，与第二发光器件22的阳极层AND的阳极电连接。
一部分第二像素电路12的第二发光控制晶体管T6的第二极，可以依次通过位于第二 源漏导电层SD2的连接部1031、位于第一连接层CO1的连接部1031，与位于第二连接层CO2的连接线30的一端电连接，该连接线30的另一端可以通过位于第三连接层CO3的连接部1031，与第二发光器件22的阳极层AND的阳极电连接。
另一部分第二像素电路12的第二发光控制晶体管T6的第二极，可以依次通过位于第二源漏导电层SD2的连接部1031、位于第一连接层CO1的连接部1031、位于第二连接层CO2的连接部1031，与位于第三连接层CO3的连接线30的一端电连接，该连接线30的另一端可以与第二发光器件22的阳极层AND的阳极电连接。
在本示例中，各平坦层的过孔的设置方式可以与上述示例中的设置方式相同，此处不再赘述。
在一些实施例中，如图24a～图25d所示，显示面板100的上述发光器件层还可以包括：设置在阳极层AND远离衬底一侧的像素界定层PDL。
其中，图24a示意出了像素界定层PDL的俯视结构。图24b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4、第三连接层CO3、第五平坦层PNL5、阳极层AND、像素界定层PDL依次层叠设置后的俯视结构。图25a示意出了发光层EL的俯视结构。图25b示意出了半导体层Poly、第一栅导电层Gate1、第二栅导电层Gate2、层间介质层ILD、第一源漏导电层SD1、第一平坦层PNL1、第二源漏导电层SD2、第二平坦层PNL2、第一连接层CO1、第三平坦层PNL3、第二连接层CO2、第四平坦层PNL4、第三连接层CO3、第五平坦层PNL5、阳极层AND、像素界定层PDL、发光层EL依次层叠设置后的俯视结构。
示例性的，像素界定层PDL用于界定发光层EL发光面积的大小，阳极层AND与发光层EL直接接触或间接接触，为发光层EL提供阳极电压。
在一些实施例中，如图6所示，多个像素电路10排列为多行多列。例如，每行像素电路可以包括多个像素电路10，该多个像素电路10沿第一方向X依次排列。每列像素电路可以包括多个像素电路10，该多个像素电路10沿第二方向Y依次排列。其中，任意相邻两行像素电路10所包括的像素电路10的数量，可以相同，也可以不同。任意相邻两列像素电路10所包括的像素电路10的数量，可以相同，也可以不同。
在一些示例中，如图6所示，像素电路中，第一像素电路11和第二像素电路12所排列的列不同。也即，同一列像素电路仅包括第一像素电路，或仅包括第二像素电路。
在一些示例中，同一行像素电路10中，各像素电路10的第一复位晶体管T1、补偿晶体管T2及开关晶体管T4的控制极，可以与同一条扫描信号线Scan电连接。同一行像素电路10中，各像素电路10的第二复位晶体管T7的第一极，可以与同一条第三初始信号线Vinit3电连接。同一行像素电路10中，各像素电路10的第二复位晶体管T7的控制极，可以与同一条复位信号线Reset电连接。
在一些实施例中，显示面板100上的多个发光器件20呈阵列排布。例如，该多个发光器件20排列为多行多列。同一行发光器件20所包括的多个发光器件20沿第一方向X依次排列，同一列发光器件20所包括的多个发光器件20沿第二方向Y依次排列。
示例性的，任意相邻两行发光器件20所包括的多个发光器件20的数量可以相同，也可以不同。任意相邻两列发光器件20所包括的多个发光器件20的数量可以相同，也可以 不同。
示例性的，上述多个发光器件20中的多个第一发光器件21，可以排列为多行多列。
示例性的，上述多个发光器件20中的多个第二发光器件22，可以排列为多行多列。
在一些实施例中，如图5所示，显示面板100包括：沿第一方向X依次排列的多个发光器件列23。各发光器件列23包括沿第二方向Y依次设置的、位于主显示区A1的多个第一发光器件21和位于辅助显示区A2的多个第二发光器件22。
同一列发光器件20中，可以仅包括第一发光器件21，也可以仅包括第二发光器件22，也可以同时包括第一发光器件21和第二发光器件22。
示例性的，本公开将同时包括第一发光器件21和第二发光器件22的同一列发光器件，称为发光器件列。
在一些示例中，显示面板100所包括的数据线Data沿第二方向Y延伸。
示例性的，多条数据线Data中的每条数据线Data的整体延伸方向可以沿第二方向Y，每条数据线Data的整体形状可以为或大致为直线形状，也可以为或大致为曲线形状，本公开对此不做限制。
在一些示例中，如图5所示，与发光器件列23中多个第一发光器件21电连接的多个第一像素电路11，及与发光器件列23中多个第二发光器件22电连接的多个第二像素电路12，与同一条数据线Data电连接。
通过上述设置方式，可以使得与发光器件列23中多个第一发光器件21电连接的多个第一像素电路11，及与发光器件列23中多个第二发光器件22电连接的多个第二像素电路12，同时接收来自同一条数据线Data的数据信号。这样在对显示面板100中的多个像素电路10进行驱动以使得显示面板100进行显示的过程中，可以采用列驱动的方式分别为与同一列发光器件20电连接的像素电路10提供数据信号，有利于简化显示面板100的驱动方式，保证显示面板100的显示均一性。
在一些示例中，与发光器件列电连接的数据线Data中，与多个第二像素电路22电连接的部分，位于主显示区A1。
可以理解的是，数据线Data的透光率较小，对光线的阻挡作用较强。
本公开采用上述设置方式，可以避免在辅助显示区A2设置数据线Data，进而可以避免数据线Data中与第二像素电路12电连接的部分对外界光线的阻挡。这样有利于使得位于辅助显示区A2的光学元件200可以采集较多的光线，确保光学元件200能够正常的工作。
在一些示例中，如图5所示，与发光器件列23中多个第二发光器件22电连接的多个第二像素电路12，沿第二方向Y依次排列，且位于辅助显示区A2沿第一方向X的一侧。
示例性的，与发光器件列23中多个第二发光器件22电连接的多个第二像素电路12可以独立地排列为一列。也即，显示面板100所包括的多个像素电路10中，一列像素电路10仅包括多个第一像素电路11或仅包括多个第二像素电路12。
在一些示例中，如图5所示，与发光器件列23电连接的数据线Data，包括：沿第二方向Y延伸、且分别位于辅助显示区A1沿第二方向Y的相对两侧的第一子数据线411和第二子数据线412，沿第二方向Y延伸、且位于辅助显示区A2沿第一方向X的一侧的第三子数据线413，沿第一方向X延伸、且连接第一子数据线411和第三子数据线413的第一转接线421，及沿第一方向X延伸、且连接第二子数据线412和第三子数据线413的第 二转接线422。第一子数据线411和第二子数据线412与多个第一像素电路11电连接，第三子数据线413与多个第二像素电路12电连接。
示例性的，第三子数据线413及与其电连接的多个第二像素电路12位于辅助显示区A1的同一侧。
采用上述设置方式，既可以使得与发光器件列23电连接的数据线Data排列规整，也可以保证各发光器件列23中的第一发光器件21和第二发光器件22可以接收同一条数据线Data提供的数据信号，从而可以确保位于辅助显示区A2的显示画面与位于主显示区A1的显示画面无差异，保证显示面板100的显示均一性。
在一些示例中，如图26所示，第一子数据线411、第二子数据线412、第三子数据线413位于第二源漏导电层SD2，第一转接线421、第二转接线422位于第一源漏导电层SD1。
示例性的，在第二源漏导电层SD2和第一源漏导电层SD1的材料相同的情况下，可以使得第一子数据线411、第二子数据线412、第三子数据线413的材料，与第一转接线421、第二转接线422的材料相同，这样可以避免大大增加与发光器件列23电连接的数据线Data的电阻，减小该数据线Data对其所传输的数据信号的损耗。
通过将第一子数据线411、第二子数据线412、第三子数据线413，与第一转接线421、第二转接线422设置在不同层，有利于增大布线空间，降低数据线Data的走线难度。
需要说明的是，在本公开中，像素电路10的布局方式有多种，本公开对此不做限制。
在一些示例中，主显示区A1的部分压缩设置。
示例性的，主显示区A1包括常规区域和压缩区域。第二像素电路12位于压缩区域，上述多个第一像素电路11中的一部分第一像素电路11位于常规区域，另一部分第一像素电路11位于压缩区域，且在压缩区域，沿第一方向X，相邻两个第二像素电路12之间设置有至少一个第一像素电路11。其中，位于压缩区域的第一像素电路11或第二像素电路12所在的列区域的宽度，小于位于常规区域的第一像素电路11所在的列区域的宽度。
示例性的，第一像素电路11所在的列区域的宽度，指的是，第一像素电路11所在的像素电路列，所占据的区域在第一方向X上的尺寸。第二像素电路12所在的列区域的宽度，指的是，第二像素电路12所在的像素电路列，所占据的区域在第一方向X上的尺寸。
位于压缩区域的第一像素电路11或第二像素电路12所在的列区域的宽度，小于位于常规区域的第二像素电路12所在的列区域的宽度，也就意味着，位于压缩区域的第一像素电路11或第二像素电路12所在的列区域的宽度被压缩，而位于常规区域的第二像素电路12所在的列区域的宽度未被压缩。
通过将位于压缩区域的第一像素电路11或第二像素电路12所在的列区域的宽度压缩，可以在压缩区域中挪出空间，用于放置第二像素电路12。
在另一些示例中，如图4b所示，主显示区A2整体压缩设置。也即，在第一方向X上，第一像素电路11或第二像素电路12所在的列区域的宽度，均进行了压缩。
这样有利于进一步增大第二像素电路12的可放置空间，便于在主显示区A1放置更多的第二像素电路12。
在一些实施例中，显示面板100还包括：周边区F以及设置在显示面板100位于周边区F区域的走线。
示例性的，上述周边区F可以位于显示区A的周边。上述走线可以包括：第一初始信号总线Z1、第二初始信号总线Z2、第三初始信号总线Z3。第一初始信号总线Z1与第一 初始信号线Vinit1通过第一桥接线q1电连接，第二初始信号总线Z2与第二初始信号线Vinit2通过第二桥接线q2电连接，第三初始信号总线Z3与第三初始信号线Vinit3通过第三桥接线q3电连接。
示例性的，第一初始信号总线Z1、第二初始信号总线Z2、第三初始信号总线Z3均位于显示面板100的第二源漏导电层SD2。第一桥接线q1、第二桥接线q2、第三桥接线q3均位于显示面板100的第一源漏导电层SD1。此时，第一初始信号总线Z1、第二初始信号总线Z2、第三初始信号总线Z3在衬底上的正投影无交叠，第一桥接线q1、第二桥接线q2、第三桥接线q3在衬底上的正投影无交叠。
可以理解的是，第一初始信号总线Z1、第二初始信号总线Z2、第三初始信号总线Z3可以分别位于不同层，第一桥接线q1、第二桥接线q2、第三桥接线q3也可以分别位于不同层。在此情况下，第一初始信号总线Z1、第二初始信号总线Z2、第三初始信号总线Z3在衬底上的正投影例如可以重叠，第一桥接线q1、第二桥接线q2、第三桥接线q3在衬底上的正投影例如可以重叠。
示例性的，上述第一初始信号总线Z1的数量可以为两条，该两条第一初始信号总线Z1可以分别位于第一初始信号线Vinit1的相对两端。上述第二初始信号总线Z2的数量可以为两条，该两条第二初始信号总线Z2可以分别位于第二初始信号线Vinit2的相对两端。上述第三初始信号总线Z3的数量可以为两条，该两条第三初始信号总线Z3可以分别位于第三初始信号线Vinit3的相对两端。
在一些示例中，随着像素电路10的布局方式的变化，显示面板100中第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3的布局方式也会随之变化。
示例性的，图27a所示为，在部分压缩设置的情况下，显示面板100中，第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3的布局方式。图27b所示为，在整体压缩设置的情况下，显示面板100中，第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3的布局方式。
在一些示例中，在部分压缩设置的情况下，第二像素电路12例如可以仅位于辅助显示区A2在第一方向X上的相对两侧。
示例性的，如图27a所示，上述第二初始信号线Vinit2仅位于设置有第二像素电路12的区域内，并与相应的第二像素电路12电连接。其余的区域则仅设置第一初始信号线Vinit1和第三初始信号线Vinit3。
在另一些示例中，在整体压缩设置的情况下，显示面板100中的多个像素电路，还包括多个虚拟第二像素电路。该多个虚拟第二像素电路分别位于相应的第二像素电路12所在的列区域。其中，该多个虚拟第二像素电路的第四节点N4悬浮设置，未与第二发光器件22电连接。
示例性的，如图27b所示，上述第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3，可以沿第二方向Y依次周期性设置。其中，一部分第二初始信号线Vinit2与相应的第二像素电路电连接，另一部分第二初始信号线Vinit2与虚拟第二像素电路电连接。
在一些示例中，第二发光器件22的分布密度，小于或等于第一发光器件21的分布密度。这样有利于确保显示面板100位于辅助显示区A2的部分具有较高的透光率。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此， 任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，具有主显示区和辅助显示区；所述显示面板包括：
    位于所述主显示区的多个像素电路；所述多个像素电路包括多个第一像素电路和多个第二像素电路；
    多个发光器件，包括位于所述主显示区的多个第一发光器件和位于所述辅助显示区的多个第二发光器件；所述多个第一像素电路分别与所述多个第一发光器件电连接，所述多个第二像素电路分别与所述多个第二发光器件电连接；以及，
    多条第一初始信号线和多条第二初始信号线；
    第一像素电路，与第一初始信号线及第一发光器件电连接，且被配置为，将所述第一初始信号线所传输的第一初始信号传输至所述第一发光器件，对所述第一发光器件进行复位；第二像素电路，与第二初始信号线及第二发光器件电连接，且被配置为，将所述第二初始信号线所传输的第二初始信号传输至所述第二发光器件，对所述第二发光器件进行复位；
    其中，所述第二初始信号的电压值大于所述第一初始信号的电压值。
  2. 根据权利要求1所述的显示面板，还包括：多条连接线；
    一个第二像素电路通过一条连接线与一个第二发光器件电连接；
    所述多条连接线的材料包括可透光的导电材料。
  3. 根据权利要求2所述的显示面板，其中，所述第二初始信号的电压值与所述第一初始信号的电压值之差，与连接线的长度，呈正相关。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述显示面板包括：沿第一方向依次排列的多个发光器件列；发光器件列包括沿第二方向依次设置的、位于所述主显示区的多个第一发光器件和位于所述辅助显示区的多个第二发光器件；
    所述显示面板还包括：沿所述第二方向延伸的多条数据线；
    所述第一方向与所述第二方向相交；
    与所述发光器件列中多个第一发光器件电连接的多个第一像素电路，及与所述发光器件列中多个第二发光器件电连接的多个第二像素电路，与同一条数据线电连接。
  5. 根据权利要求4所述的显示面板，其中，所述数据线中与所述多个第二像素电路电连接的部分，位于所述主显示区。
  6. 根据权利要求5所述的显示面板，其中，与所述发光器件列中多个第二发光器件电连接的多个第二像素电路，沿所述第二方向依次排列，且位于所述辅助显示区沿所述第一方向的一侧；
    所述数据线包括：沿所述第二方向延伸、且分别位于所述辅助显示区沿所述第二方向的相对两侧的第一子数据线和第二子数据线，沿所述第二方向延伸、且位于所述辅助显示区沿所述第一方向的一侧的第三子数据线，沿所述第一方向延伸、且连接所述第一子数据线和所述第三子数据线的第一转接线，及沿所述第一方向延伸、且连接所述第二子数据线和所述第三子数据线的第二转接线；
    所述第一子数据线和所述第二子数据线与所述多个第一像素电路电连接，所述第三子数据线与所述多个第二像素电路电连接。
  7. 根据权利要求6所述的显示面板，其中，
    所述显示面板包括：衬底，以及依次层叠设置在所述衬底一侧的第一源漏导电层和第二源漏栅导电层；
    所述第一子数据线、所述第二子数据线、所述第三子数据线位于所述第二源漏导电层，所述第一转接线、所述第二转接线位于所述第一源漏导电层。
  8. 根据权利要求1～7中任一项所述的显示面板，其中，所述像素电路还包括：补偿晶体管；
    所述补偿晶体管包括：依次层叠设置的有源图案及栅极图案；所述有源图案包括依次连接的第一半导体部、导体部和第二半导体部，所述栅极图案包括相连接的第一子栅极和第二子栅极；所述第一半导体部和所述第一子栅极部分正对设置，所述第二半导体部和所述第二子栅极部分正对设置；
    其中，所述显示面板还包括：与所述像素电路电连接的第三初始信号线，及与所述第三初始信号线电连接的屏蔽块；
    所述屏蔽块与所述导体部，部分正对设置。
  9. 根据权利要求8所述的显示面板，其中，所述屏蔽块与所述第三初始信号线为一体结构。
  10. 根据权利要求8或9所述的显示面板，其中，所述第一初始信号线、所述第二初始信号线和所述第三初始信号线同层设置；
    所述多个像素电路排列为多行；
    位于相邻两行像素电路之间的第一初始信号线、第二初始信号线和第三初始信号线中，所述第三初始信号线，相比于所述第一初始信号线和所述第二初始信号线更靠近与所述第三初始信号线电连接的补偿晶体管。
  11. 根据权利要求10所述的显示面板，所述像素电路还包括第二复位晶体管；所述第二复位晶体管的第一极与所述第三初始信号线电连接，所述第二复位晶体管的第二极与所述补偿晶体管的第二极电连接；
    所述显示面板还包括：与所述第二复位晶体管的控制极电连接的复位信号线；所述第二复位晶体管被配置为，在所述复位信号线所传输的复位信号的控制下，将所述第三初始信号线所传输的第三初始信号传输至所述补偿晶体管的第二极；
    其中，所述复位信号线在衬底上的正投影，位于所述第一初始信号线在所述衬底上的正投影及所述第二初始信号线在所述衬底上的正投影之间；或者，位于所述第二初始信号线在所述衬底上的正投影及第三初始信号线在所述衬底上的正投影之间。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板还包括：衬底，以及依次层叠设置在所述衬底一侧的第一栅导电层和第二栅导电层；
    所述复位信号线位于所述第一栅导电层；
    所述第一初始信号线、所述第二初始信号线、所述第三初始信号线位于所述第二栅导电层。
  13. 根据权利要求1～12中任一项所述的显示面板，其中，所述多个像素电路排列为多行多列；
    所述像素电路还包括：存储电容器；
    所述存储电容器包括层叠设置的第一极板及第二极板；
    其中，同一行像素电路中的至少两个存储电容器的第二极板相互连接，呈一体结构。
  14. 根据权利要求13所述的显示面板，还包括：沿第二方向延伸的多条电压信号线；
    一条电压信号线与一列像素电路的存储电容器的第二极板电连接。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括：衬底，以及依次层叠设置在所述衬底一侧的第二栅导电层和第二源漏导电层；
    所述第二极板位于所述第二栅导电层，所述多条电压信号线位于所述第二源漏导电层。
  16. 根据权利要求15所述的显示面板，其中，所述像素电路还包括：补偿晶体管，及连接所述补偿晶体管的第二极与所述存储电容器的第一极板的转接部；
    所述显示面板还包括：位于所述第二栅导电层与所述第二源漏导电层之间的第一源漏导电层；
    所述转接部位于所述第一源漏导电层；
    所述转接部在所述衬底上的正投影位于所述电压信号线在所述衬底上的正投影范围之内。
  17. 根据权利要求15或16所述的显示面板，其中，所述显示面板还包括：设置在所述第二栅导电层远离所述第二源漏导电层一侧的第一栅导电层，及设置在所述第二栅导电层和所述第二源漏导电层之间的第一平坦层；
    所述像素电路还包括：第一发光控制晶体管和第二发光控制晶体管；
    所述第一平坦层上设置有第一过孔和第二过孔；所述第一发光控制晶体管的第一极通过所述第一过孔与所述电压信号线电连接，所述第二发光控制晶体管的第二极通过所述第二过孔与发光器件电连接；
    所述显示面板还包括：与第一发光控制晶体管的控制极和第二发光控制晶体管的控制极电连接的使能信号线；所述使能信号线位于所述第一栅导电层；
    所述第一过孔及所述第二过孔在所述衬底上的正投影，位于所述使能信号线在所述衬底上的正投影范围之内。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：沿第一方向延伸的多条扫描信号线以及多条复位信号线；
    所述像素电路还包括：驱动晶体管、补偿晶体管、第一复位晶体管、第二复位晶体管、开关晶体管；
    补偿晶体管的控制极与所述扫描信号线电连接，所述补偿晶体管的第二极与第一节点电连接；
    所述第二复位晶体管的控制极与复位信号线电连接，所述第二复位晶体管的第一极与第三初始信号线电连接，所述第二复位晶体管的第二极与所述第一节点电连接；
    所述第一发光控制晶体管的第二极与第二节点电连接；
    所述驱动晶体管的控制极与第三节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，驱动晶体管的第二极与所述第一节点电连接；
    所述开关晶体管的控制极与所述扫描信号线电连接，所述开关晶体管的第一极与数据线电连接，所述开关晶体管的第二极与所述第二节点电连接；
    所述第二发光控制晶体管的第一极与所述第三节点电连接，
    所述存储电容器的第一极板与所述第一节点电连接；
    所述第一复位晶体管的控制极与扫描信号线电连接，所述第一像素电路的第一复位晶体管的第一极与所述第一初始信号线电连接，所述第一像素电路的第一复位晶体管的第二极与所述第一像素电路的第四节点电连接，所述第二像素电路的第一复位晶体管的第一极与所述第二初始信号线电连接，所述第二像素电路的第一复位晶体管的第二极与所述第二 像素电路的第四节点电连接。
  19. 一种显示模组，包括：
    如权利要求1～18中任一项所述的显示面板；
    位于所述显示面板的出光侧的盖板；以及，
    位于所述显示面板的非出光侧的保护层。
  20. 一种显示装置，包括：如权利要求19所述的显示模组；以及，
    位于所述显示模组的显示面板中非出光侧的光学元件，所述光学元件位于所述显示面板的辅助显示区。
PCT/CN2022/073590 2022-01-24 2022-01-24 显示面板、显示模组及显示装置 WO2023137766A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280000058.9A CN117280889A (zh) 2022-01-24 2022-01-24 显示面板、显示模组及显示装置
PCT/CN2022/073590 WO2023137766A1 (zh) 2022-01-24 2022-01-24 显示面板、显示模组及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/073590 WO2023137766A1 (zh) 2022-01-24 2022-01-24 显示面板、显示模组及显示装置

Publications (1)

Publication Number Publication Date
WO2023137766A1 true WO2023137766A1 (zh) 2023-07-27

Family

ID=87347544

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/073590 WO2023137766A1 (zh) 2022-01-24 2022-01-24 显示面板、显示模组及显示装置

Country Status (2)

Country Link
CN (1) CN117280889A (zh)
WO (1) WO2023137766A1 (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111668278A (zh) * 2020-06-29 2020-09-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN112038381A (zh) * 2020-09-10 2020-12-04 武汉天马微电子有限公司 显示面板及显示装置
CN112563303A (zh) * 2019-09-25 2021-03-26 上海和辉光电有限公司 一种显示面板及显示装置
CN112909056A (zh) * 2021-01-26 2021-06-04 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN113035131A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置
CN113035129A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置
CN113380196A (zh) * 2020-03-10 2021-09-10 三星显示有限公司 显示装置及驱动显示装置的方法
CN113540175A (zh) * 2020-04-22 2021-10-22 三星显示有限公司 显示装置
CN113674693A (zh) * 2021-08-16 2021-11-19 成都京东方光电科技有限公司 显示基板和显示装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563303A (zh) * 2019-09-25 2021-03-26 上海和辉光电有限公司 一种显示面板及显示装置
CN113035131A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置
CN113035129A (zh) * 2019-12-24 2021-06-25 乐金显示有限公司 有机发光显示装置
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN113380196A (zh) * 2020-03-10 2021-09-10 三星显示有限公司 显示装置及驱动显示装置的方法
CN113540175A (zh) * 2020-04-22 2021-10-22 三星显示有限公司 显示装置
CN111668278A (zh) * 2020-06-29 2020-09-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN112038381A (zh) * 2020-09-10 2020-12-04 武汉天马微电子有限公司 显示面板及显示装置
CN112909056A (zh) * 2021-01-26 2021-06-04 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN113674693A (zh) * 2021-08-16 2021-11-19 成都京东方光电科技有限公司 显示基板和显示装置

Also Published As

Publication number Publication date
CN117280889A (zh) 2023-12-22

Similar Documents

Publication Publication Date Title
US10916613B1 (en) Array substrate and OLED display device
US20220343862A1 (en) Display substrate and display device
US10297620B2 (en) Display device
WO2021226817A1 (zh) 显示基板及显示装置
US20230098206A1 (en) Display panel and method for driving the same, and display apparatus
CN110824797A (zh) 透明显示面板、显示面板及其显示装置
CN115669275A (zh) 显示面板和显示装置
US20240040880A1 (en) Display panel and display device
US20240172509A1 (en) Display panel and display device
WO2022094839A1 (zh) 显示基板及其检测方法、制备方法、显示装置
CN112038380A (zh) 显示基板及显示装置
WO2023137766A1 (zh) 显示面板、显示模组及显示装置
US20240147785A1 (en) Display Substrate and Preparation Method Therefor, and Display Apparatus
CN115020461A (zh) 显示基板及显示装置
CN115226415A (zh) 显示面板和显示装置
WO2023000215A1 (zh) 显示基板及显示装置
CN219042435U (zh) 显示面板及显示装置
WO2023230811A1 (zh) 显示基板以及显示装置
US20240164156A1 (en) Display Substrate, Preparation Method thereof, and Display Apparatus
WO2023165016A1 (zh) 显示面板及显示装置
EP4300273A1 (en) Display device
WO2023173424A1 (zh) 显示基板及显示装置
EP4274403A1 (en) Display substrate and display apparatus
US20240038163A1 (en) Display Substrate and Preparation Method thereof, and Display Apparatus
WO2023142071A1 (zh) 阵列基板、显示面板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280000058.9

Country of ref document: CN