WO2023230811A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2023230811A1
WO2023230811A1 PCT/CN2022/096141 CN2022096141W WO2023230811A1 WO 2023230811 A1 WO2023230811 A1 WO 2023230811A1 CN 2022096141 W CN2022096141 W CN 2022096141W WO 2023230811 A1 WO2023230811 A1 WO 2023230811A1
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Prior art keywords
sub
pixel
light
pixels
layer
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PCT/CN2022/096141
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English (en)
French (fr)
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WO2023230811A9 (zh
Inventor
鲍建东
王云浩
侯鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001603.6A priority Critical patent/CN117501832A/zh
Priority to PCT/CN2022/096141 priority patent/WO2023230811A1/zh
Publication of WO2023230811A1 publication Critical patent/WO2023230811A1/zh
Publication of WO2023230811A9 publication Critical patent/WO2023230811A9/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • OLED display devices have a series of advantages such as self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost, and have become a new generation of display devices.
  • the arrangement manner of each structure and the positional relationship between each structure are important factors that affect the display effect of the display device.
  • At least one embodiment of the present disclosure provides a display substrate, which has a plurality of sub-pixels and includes a base substrate, a pixel driving circuit layer, a pixel defining layer and a spacer layer.
  • the pixel driving circuit layer is disposed on the base substrate, and the pixel defining layer is disposed on a side of the pixel driving circuit layer away from the base substrate, and includes a plurality of sub-pixel openings, wherein the plurality of sub-pixels are Each includes a pixel driving circuit disposed in the pixel driving circuit layer and a light emitting device at least partially disposed in the sub-pixel opening, and a spacer layer is disposed on the pixel defining layer away from the base substrate.
  • One side includes a plurality of spacers, wherein the light transmittance of the plurality of spacers is less than 5%.
  • the light transmittance of the pixel defining layer in parts other than the plurality of sub-pixel openings is less than 5%.
  • the spacer layer and the pixel defining layer are made of the same material.
  • the minimum distance between the plurality of spacers and the plurality of sub-pixel openings is L, and 1 micrometer ⁇ L ⁇ 8 micrometers.
  • the spacers have a planar shape of a rectangle.
  • the length and width of the rectangle range from 13 microns to 19 microns, and in a direction perpendicular to the base substrate, the plurality of spacers The height is 0.5 micron-2.0 micron.
  • the pixel driving circuit layer has a plurality of pixel driving circuits and a plurality of scanning signal lines that provide scanning signals for the plurality of pixel driving circuits and a plurality of scanning signal lines for the plurality of pixels.
  • the driving circuit provides a plurality of reset control signal lines of reset control signals.
  • at least some of the plurality of spacers are respectively located on one reset control signal line and with the one reset control signal line. Between the control signal lines and the nearest scan signal line.
  • the pixel driving circuit layer has a plurality of pixel driving circuits and a plurality of scanning signal lines that provide scanning signals for the plurality of pixel driving circuits and a plurality of scanning signal lines for the plurality of pixels.
  • the driving circuit provides a plurality of reset control signal lines of reset control signals.
  • at least some of the plurality of spacers are respectively connected to one reset control signal line and one to the reset control signal line. At least one of the scan signal lines closest to the control signal line overlaps.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a black matrix layer disposed on a side of the light-emitting device away from the base substrate, wherein the black matrix layer includes a plurality of first light-transmitting openings,
  • the orthographic projections of the plurality of sub-pixel openings on the substrate are respectively located inside the orthographic projections of the plurality of first light-transmitting openings on the substrate, and the plurality of sub-pixel openings are located on the substrate.
  • the distance between the boundaries of the orthographic projection on the base substrate and the boundaries of the orthogonal projection of the plurality of first light-transmitting openings on the base substrate is 1.0 micrometers to 6.5 micrometers.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of color filters, wherein the plurality of color filters are respectively at least partially disposed in the plurality of first light-transmitting openings; for a first A light-transmitting opening and a color filter at least partially disposed in the first light-transmitting opening, the orthographic projection of the first light-transmitting opening on the base substrate is located at the color filter Slice inside the orthographic projection on the base substrate.
  • the black matrix layer further includes a plurality of second light-transmitting openings, and the plurality of second light-transmitting openings are respectively provided in the plurality of first light-transmitting openings. between two adjacent first light-transmitting openings.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a light-shielding layer disposed on the base substrate, wherein the pixel driving circuit layer is disposed on a side of the light-shielding layer away from the base substrate.
  • the light-shielding layer includes a plurality of third light-transmitting openings, and the orthographic projections of at least part of the plurality of third light-transmitting openings on the substrate are respectively aligned with the positions of the plurality of second light-transmitting openings.
  • the orthographic projections on the substrate at least partially overlap.
  • the orthographic projections of the plurality of third light-transmitting openings on the substrate substrate are respectively located on the positions of the plurality of second light-transmitting openings on the substrate substrate. in the orthographic projection on.
  • the boundaries of orthographic projections of at least part of the plurality of third light-transmitting openings on the substrate substrate are respectively aligned with the boundaries of the plurality of second light-transmitting openings.
  • the distance between the boundaries of the orthographic projection on the base substrate is 0.5 microns to 1.5 microns.
  • the plurality of sub-pixels include first sub-pixels, second sub-pixels and third sub-pixels, and at least part of the plurality of second light-transmitting openings are located in the same phase. between the first light-transmitting openings corresponding to the adjacent first sub-pixel and the third sub-pixel, and the distance between the first light-transmitting opening corresponding to the first sub-pixel is different from the first light-transmitting opening corresponding to the third sub-pixel distance.
  • the first sub-pixels and the third sub-pixels are arranged in multiple rows and multiple columns, and multiple first sub-pixels and multiple third sub-pixels located in the same column
  • the pixels are alternately arranged, and a second light-transmitting opening is provided between the first light-transmitting openings corresponding to the adjacent first sub-pixels and third sub-pixels in the same column.
  • a first sub-pixel, two second sub-pixels and a third sub-pixel form a repeating unit, and multiple repeating units are arranged in an array.
  • the plurality of second sub-pixels are arranged in multiple rows and multiple columns, and the one second light-transmitting opening is also provided between the first light-transmitting openings corresponding to the adjacent second sub-pixels in the row direction.
  • the orthographic projection of each of the plurality of spacers on the base substrate is respectively located at the sub-pixel of the second sub-pixel adjacent in the column direction.
  • the openings are between orthographic projections on the base substrate, and are respectively located between orthographic projections of the sub-pixel openings of the first sub-pixel and the third sub-pixel adjacent in the row direction on the base substrate.
  • the orthographic projection of each of the plurality of spacers on the base substrate is in direct contact with the adjacent first sub-pixel and third sub-pixel.
  • the shortest distance of the orthographic projection of the sub-pixel opening of the first sub-pixel on the substrate is greater than the sub-pixel opening of the third sub-pixel in the adjacent first sub-pixel and the third sub-pixel on the substrate. The shortest distance of the orthographic projection on.
  • the orthographic projection of each of the plurality of spacers on the base substrate is aligned with the sub-pixel opening of the adjacent second sub-pixel on the substrate.
  • the shortest distance of the orthographic projection on the base substrate is essentially the same.
  • the first sub-pixel is a red sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a blue sub-pixel.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer disposed on a side of the light-emitting device away from the base substrate and an encapsulation layer disposed on a side of the encapsulation layer away from the base substrate.
  • Touch layer wherein the black matrix layer is disposed on a side of the encapsulation layer away from the base substrate, and the black matrix layer is disposed on a side of the touch layer away from the base substrate.
  • the touch layer includes a plurality of touch traces, the orthographic projection of the plurality of touch traces on the base substrate and the orthogonal projection of the plurality of second light-transmitting openings on the base substrate Orthographic projections do not overlap.
  • the first sub-pixels and the third sub-pixels are arranged in multiple rows and multiple columns, and multiple first sub-pixels and multiple third sub-pixels located in the same column
  • the pixels are alternately arranged, wherein at least some of the plurality of touch traces have gaps between adjacent first sub-pixels and third sub-pixels located in the same column.
  • At least some of the plurality of touch traces are close to the third sub-pixel in adjacent first sub-pixels and third sub-pixels located in the same column.
  • One side of the pixel or a side close to the first sub-pixel has a gap; or at least part of the plurality of touch traces are close to each other in adjacent first sub-pixels and third sub-pixels located in the same column.
  • One side of the third sub-pixel and a side close to the first sub-pixel have gaps.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • Figure 1A is a partial cross-sectional schematic diagram of a display substrate
  • Figure 1B is a graph showing the color separation test results of the display substrate in Figure 1A;
  • Figure 2 is a partial cross-sectional schematic view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a partial plan view of a black matrix layer and a spacer layer in a display substrate according to at least one embodiment of the present disclosure
  • Figure 4 is a graph showing color separation test results of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a partial plan view of a black matrix layer, a spacer layer, and a first color filter stack in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 6 is a partial cross-sectional schematic diagram of a black matrix layer, a spacer layer, and a color filter stack in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7 is a partial plan view of a stack of a black matrix layer, a spacer layer, a first color filter, and a second color filter in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 8 is a partial plan view of a stack of a black matrix layer, a spacer layer, a first color filter, a second color filter and a third color filter in a display substrate according to at least one embodiment of the present disclosure
  • Figure 9 is another partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic plan view of a stack of second light-transmitting openings and third light-transmitting openings in a display substrate according to at least one embodiment of the present disclosure
  • Figure 11 is a partial plan view of a stack of a black matrix layer, a touch layer, a first color filter, a second color filter and a third color filter in a display substrate according to at least one embodiment of the present disclosure
  • Figure 12 is an equivalent circuit schematic diagram of an 8T1C pixel driving circuit provided by at least one embodiment of the present disclosure
  • Figure 13 is a working timing diagram of a pixel driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 14-25 are schematic plan views of various layers in a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 1A shows a schematic cross-sectional view of a display panel.
  • the display panel includes a light-emitting device EM and a pixel drive circuit for driving the light-emitting device.
  • the pixel drive circuit includes a thin film transistor TFT and a storage capacitor.
  • the pixel A pixel definition layer PDL is provided above the driving circuit to define the light-emitting area of the light-emitting device EM.
  • a spacer PS is provided above the pixel definition layer PDL, for example, to support a mask and other structures during the preparation process of the display panel.
  • the pixel definition layer PDL and the spacer PS are usually made of organic insulating materials such as polyimide.
  • the display panel further includes a color filter CF, and the light emitted by the light-emitting device EM is emitted through the color filter to form purer monochromatic light.
  • external ambient light may enter the display panel through the color filter CF and be reflected by some structures in the display panel, such as the pixel definition layer PDL and the spacer PS.
  • the chamfered part (the part of the circular dotted frame in the figure) reflects, and the reflected light will continue to emit from the color filter CF, affecting the normal display of the display panel, and making the dark state effect of the display panel poor, and the visual performance is reflected color separation phenomenon.
  • Figure 1B shows the actual measurement results of color separation of the display panel in Figure 1A.
  • color separation testing equipment was used to test 6 points in 72 directions (one step every 5°), a total of 432 The fitting color separation of the points produces a cloud image as shown in Figure 1B.
  • the display panel is in a dark state, when a light source shines on the screen, as shown in Figure 1B, from dark to light Color description: The more serious the color separation is, the color separation phenomenon will seriously affect the display effect of the display panel.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate has a plurality of sub-pixels and includes a substrate substrate, a pixel driving circuit layer, a pixel defining layer and a spacer layer.
  • the pixel driving circuit layer is disposed on the substrate.
  • the pixel definition layer is disposed on a side of the pixel driving circuit layer away from the base substrate, and includes a plurality of sub-pixel openings, wherein each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer;
  • a light-emitting device at least partially disposed in the sub-pixel opening, the spacer layer is disposed on a side of the pixel definition layer away from the base substrate, and includes a plurality of spacers, wherein the light transmittance of the plurality of spacers is less than 5 %.
  • the spacer is basically opaque and absorbs light. Therefore, external ambient light will not be reflected and emitted in the display panel. Therefore, the display panel will basically not produce color separation. and other undesirable phenomena, with better display effect.
  • FIG. 2 shows a partial cross-sectional view of the display panel
  • FIG. 3 shows a plan view of a partial structure of the display panel.
  • the display substrate has a plurality of sub-pixels and includes a base substrate 110 , a pixel driving circuit layer 120 , a pixel definition layer PDL and a spacer layer 140 .
  • the pixel driving circuit layer 120 is provided on the base substrate 110 and includes a plurality of pixel driving circuits.
  • Each pixel driving circuit includes a thin film transistor TFT and a storage capacitor (not shown) and other structures.
  • a thin film transistor TFT includes an active layer 121 , a gate electrode 122 , a first electrode 123 and a second electrode 124 and other structures.
  • the pixel definition layer PDL is disposed on a side of the pixel driving circuit layer 120 away from the base substrate 110 and includes a plurality of sub-pixel openings 130 .
  • Each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer 120 and a light emitting device EM at least partially disposed in the sub-pixel opening 130 .
  • the light-emitting device EM includes a first electrode 141, a light-emitting material layer 142, and a second electrode 143.
  • the first electrode 141 serves as an anode and is electrically connected to the source and drain electrodes 123 of the thin film transistor TFT.
  • the luminescent material layer 142 includes an organic luminescent material and is configured to emit monochromatic light or white light.
  • the second electrode 143 serves as a cathode, for example, formed as a surface electrode, that is, the second electrodes 143 of multiple sub-pixels are continuously arranged in a surface shape to cover the base substrate 110 as a whole; or, in some embodiments, when the display substrate requires At the position where the light transmittance is increased, the second electrode 143 may have a pattern facing the first electrode 141, that is, the second electrode 143 is patterned to increase the light transmittance of the display substrate at this position.
  • the spacer layer 140 is disposed on a side of the pixel definition layer PDL away from the base substrate 110 and includes a plurality of spacers PS.
  • the light transmittance of the plurality of spacers PS is less than 5%, for example, less than 2%.
  • the plurality of spacers PS may support devices such as masks during the preparation process of the display substrate.
  • the plurality of spacers PS can be formed of a black opaque material, such as a black opaque material formed by doping a black dye in a resin material.
  • a black opaque material such as a black opaque material formed by doping a black dye in a resin material. This material has a good light absorption effect. , so when the external ambient light shines on the spacer PS, the external ambient light will not be reflected but absorbed, so the color separation phenomenon can be weakened or even eliminated.
  • the light transmittance of the pixel defining layer PDL in portions other than the plurality of sub-pixel openings 130 is less than 5%, such as less than 2%.
  • the material of the pixel definition layer PDL can be the same as the material of the plurality of spacers PS, so that the half-tone mask can be used in the preparation process to be formed in the same patterning process, or the two can also be made of the same or different materials. materials are formed separately.
  • Figure 4 shows the actual measurement results of color separation of the display panel provided by the embodiment of the present disclosure.
  • the color separation phenomenon displayed from dark to light colors is much different than that in Figure 1B. It is weakened and even difficult to detect with the naked eye, which can greatly improve the display effect of the display panel.
  • the color separation effect can achieve lab ⁇ 4 ( The a-axis represents the relative colors of red and green, +a represents red, -a represents green, the b-axis represents the relative colors of yellow and blue, +b represents yellow, and -b represents blue), which can greatly improve the use of display substrates under outdoor sunlight. Effect.
  • the minimum distance between the spacers PS and the sub-pixel openings 130 is L, and 1 micron ⁇ L ⁇ 8 microns.
  • L is 2 microns, 4 microns, 6 microns or 8 microns. wait. Therefore, the plurality of spacers PS are separated from the plurality of sub-pixel openings 130 by a certain distance.
  • the side walls of the sub-pixel openings 130 usually have a certain tilt angle, if the distance between the plurality of spacers PS and the plurality of sub-pixel openings 130 is If the distance is too close, the spacer PS may be formed on the sidewall of the sub-pixel opening 130, thereby reducing the height of the spacer PS relative to the base substrate 110, making it difficult to achieve a sufficient spacer effect.
  • the planar shape of at least some of the spacers PS among the plurality of spacers PS is rectangular.
  • the length L1 and width W1 of the rectangle range from 13 microns to 19 microns.
  • the length L1 can be 15 microns, 17 microns, or 19 microns
  • the width W1 can be 13 microns, 15 microns, or 17 microns.
  • at least part of the planar shape of the spacer PS can also be a square. In this case, the side length of the square can be 12 microns, 15 microns, 17 microns or 19 microns, etc.
  • the planar shape of at least some of the spacers PS among the plurality of spacers PS may also be circular.
  • the diameter of the circle may be 13 microns to 19 microns, such as 15 microns or 17 microns, etc.; or, in some embodiments, the plurality of spacers PS may include main spacers and auxiliary spacers, and the planar shapes of the main spacers and auxiliary spacers may be circular.
  • the sum of the circular diameters of the main spacer and the auxiliary spacer may be 13 microns to 19 microns, such as 15 microns or 17 microns.
  • the height H of the spacers PS is 0.5 micrometers to 2.0 micrometers, such as 1.0 micrometers or 1.5 micrometers. microns, etc., to fully realize the spacer function.
  • the display substrate further includes a black matrix layer BM disposed on a side of the light-emitting device EM away from the substrate substrate 110 .
  • the black matrix layer BM includes a plurality of first light-transmitting openings BM1 .
  • FIG. 5 shows A schematic planar arrangement of the first light-transmitting openings BM1 is shown in FIG. 5 .
  • the orthographic projections of the plurality of sub-pixel openings 130 on the base substrate 110 are respectively located at the orthogonal positions of the plurality of first light-transmitting openings BM1 on the base substrate 110 . Projection inside.
  • the distance L2 between the boundaries of the orthographic projections of the plurality of sub-pixel openings 130 on the base substrate 110 and the boundaries of the orthogonal projections of the plurality of first light-transmitting openings BM1 on the base substrate 110 is 1.0 micrometers to 6.5 micrometers, for example 3 microns to 6 microns, such as 3.5 microns, 4 microns, 4.5 microns, 5 microns or 5.5 microns, etc. That is, the first light-transmitting opening BM1 is expanded by 1.0 microns to 6.5 microns relative to the corresponding sub-pixel opening 130, so that the light emitted by the light-emitting device EM can fully emit through the first light-transmitting opening BM1.
  • the display substrate further includes a plurality of color filters CF, and the plurality of color filters CF are respectively at least partially disposed in a plurality of first light-transmitting openings BM1; for a A first light-transmitting opening BM1 and a color filter CF at least partially disposed in the first light-transmitting opening BM1.
  • the orthographic projection of the first light-transmitting opening BM1 on the substrate 110 is located on the color filter CF.
  • the light sheet CF is inside the orthographic projection on the base substrate 110 , that is, the installation range of the color filter CF is larger than the installation range of the first light-transmitting opening BM1 .
  • the plurality of sub-pixels include a first sub-pixel R, a second sub-pixel G and a third sub-pixel B
  • the plurality of color filters CF include a first color filter for the first sub-pixel R.
  • the first sub-pixel is a red sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a blue sub-pixel
  • the first color filter RCF is a red filter film
  • the second color filter GCF is a green filter
  • the third color filter BCF is a blue filter
  • the first sub-pixel R can also be a green sub-pixel or a blue sub-pixel
  • the second sub-pixel G can also be a red sub-pixel or a blue sub-pixel
  • the third sub-pixel B can also be It is a red sub-pixel or a green sub-pixel.
  • a color filter of a corresponding color is set on each sub-pixel.
  • the display substrate may further include a color filter layer disposed on a side of the black matrix layer BM away from the base substrate, and the color filter layer has a grid-like structure.
  • the color filter layer includes a first color filter layer (such as a red filter layer), a second color filter layer (such as a green filter layer), and a third color filter layer (such as a blue filter layer). At least one.
  • the first color filter layer is hollowed out at the second light-transmitting opening BM2 corresponding to the second sub-pixel G and the third sub-pixel B, for example, the first color filter RCF is filled in the hollowed out part;
  • the second color filter layer The layer is hollowed out at the second light-transmitting opening BM2 corresponding to the first sub-pixel R and the third sub-pixel B, for example, the hollowed-out place is filled with the second color filter GCF;
  • the third color filter layer is formed at the first sub-pixel R and the third sub-pixel B.
  • the second light-transmitting opening BM2 corresponding to the second sub-pixel G is hollowed out, and for example, the hollowed out space is filled with a third color filter BCF. This can further reduce the reflectivity of light in the display substrate.
  • FIG. 5 shows a schematic planar arrangement of a plurality of first color filters RCF.
  • the setting range of the first color filter RCF is larger than the setting range of the first light-transmitting opening BM1 corresponding to the first sub-pixel R.
  • FIG. 6 shows a partial cross-sectional view of the first light-transmitting opening BM1, the first color filter RCF, and the sub-pixel opening 130. As shown in FIGS.
  • the setting range of the first light-transmitting opening BM1 is greater than
  • the setting range of the sub-pixel opening 130 and the setting range of the first color filter RCF are greater than the setting range of the first light-transmitting opening BM1
  • the boundary of the orthographic projection of the sub-pixel opening 130 on the base substrate 110 and the first light-transmitting opening are
  • the distance L2 of the boundary of the orthographic projection of the opening BM1 on the base substrate 110 is 1.0 micrometers to 6.5 micrometers, for example, 3 micrometers to 6 micrometers.
  • the width of the spacer PS may be smaller than the width of the non-transparent area of the black matrix layer BM.
  • the width of the spacer PS may also be larger than the width of the black matrix layer BM.
  • the width of the non-transparent area is such that even if light irradiates the spacer PS, the spacer PS will not reflect the light and cause color separation. This can improve the design freedom of the black matrix layer BM.
  • FIG. 7 shows a situation in which a second color filter GCF is provided based on FIG. 5
  • FIG. 8 shows a situation in which a third color filter BCF is provided based on FIG. 7
  • the setting range of the first light-transmitting opening BM1 is larger than the setting range of the sub-pixel opening 130
  • the setting range of the third color filter BCF is larger than the setting range of the first light-transmitting opening BM1, and the boundary between the orthographic projection of the sub-pixel opening 130 on the base substrate 110 and the first light-transmitting opening BM1 on the base substrate 110
  • the distance L2 of the orthographic projection boundary is 1.0 micron-6.5 micron, for example, 3 micron-6 micron.
  • the black matrix layer BM further includes a plurality of second light-transmitting openings BM2 , and the plurality of second light-transmitting openings BM2 are respectively disposed on the plurality of first light-transmitting openings BM2 . Between two adjacent first light-transmitting openings BM1 in the light-transmitting openings BM1.
  • the plurality of second light-transmitting openings BM2 can transmit, for example, signal light used for fingerprint recognition or signal light required by cameras, distance sensors, infrared sensors and other devices.
  • the display substrate further includes a light-shielding layer S disposed on the base substrate 110 , and the pixel driving circuit layer 120 is disposed on a side of the light-shielding layer S away from the base substrate 110 .
  • the light-shielding layer S includes a plurality of third light-transmitting openings S1.
  • the orthographic projections of at least part of the plurality of third light-transmitting openings S1 on the base substrate 110 are respectively on the base substrate 110 and the plurality of second light-transmitting openings BM2 on the base substrate 110. orthographic projections at least partially overlap.
  • the third light-transmitting opening S1 and the second light-transmitting opening BM2 form a hole to transmit signal light for fingerprint recognition, for example.
  • an image can be disposed on the side of the base substrate 110 away from the light-emitting device EM.
  • the sensor can receive the signal light passing through the second light-transmitting opening BM2 and the third light-transmitting opening S1 to perform texture collection and recognition functions.
  • the material of the light-shielding layer 110 can be metal materials such as copper and aluminum or alloy materials; or the light-shielding layer 110 can also be a black opaque layer formed by doping a black dye in a resin material.
  • the light-shielding layer S can transmit the signal light used for fingerprint recognition at the first light-transmitting opening S1, and block the light emitted by the light-emitting device EM of the display substrate and non-signal light such as ambient light at other positions. to prevent non-signal light from irradiating the image sensor arranged on the non-display side of the display substrate, thereby improving the recognition speed and accuracy of the image sensor.
  • the pixel driving circuit layer includes multiple metal layers, such as the metal layers where the gate electrode 122, the first electrode 123, the second electrode 124, etc. are located.
  • the circuit patterns composed of these metal layers are formed on the base substrate.
  • the orthographic projection on 110 does not overlap with the orthographic projection of the plurality of first light-transmitting openings S1 on the base substrate 110, nor does it overlap with the orthographic projection of the third light-transmitting opening BM2 on the base substrate 110 to avoid The circuit pattern affects the transmission of signal light.
  • FIG. 10 shows a schematic diagram of the orthographic projection of a third light-transmitting opening S1 and the corresponding second light-transmitting opening BM2 on the substrate 110.
  • a plurality of third light-transmitting openings S1 are on
  • the orthographic projections on the base substrate 110 are respectively located within the orthographic projections of the plurality of second light-transmitting openings BM2 on the base substrate 110 .
  • the boundaries of the orthographic projections of at least part of the plurality of third light-transmitting openings S1 on the substrate 110 are respectively connected with the boundaries of the plurality of second light-transmitting openings BM2 on the substrate.
  • the distance L3 of the orthographic projection boundary on the substrate 110 is 0.5 microns to 1.5 microns, such as 0.8 microns, 1.0 microns, 1.2 microns or 1.5 microns, etc., so that the signal light can fully pass through the second light-transmitting opening BM2 and the third light-transmitting opening.
  • S1 reaches the image sensor.
  • At least part of the plurality of second light-transmitting openings BM2 is located between the first light-transmitting openings BM1 corresponding to the adjacent first sub-pixel R and the third sub-pixel B. space, and the distance of the first light-transmitting opening BM1 corresponding to the first sub-pixel R is different from the distance of the first light-transmitting opening BM1 corresponding to the third sub-pixel B, for example, the distance of the first light-transmitting opening BM1 corresponding to the third sub-pixel B The distance between the light openings BM1 is closer.
  • the first sub-pixel R and the third sub-pixel B are arranged in multiple rows and multiple columns, and multiple first sub-pixels R and multiple third sub-pixels located in the same column B are arranged alternately, and a second light-transmitting opening BM2 is provided between the first light-transmitting openings BM1 corresponding to the adjacent first sub-pixels R and third sub-pixels B in the same column.
  • a first sub-pixel R, two second sub-pixels G and a third sub-pixel B form a repeating unit, and multiple repeating units are arranged in an array.
  • the plurality of second sub-pixels G in the repeating unit are arranged in multiple rows and multiple columns, and the second light-transmitting openings BM2 are also provided between the first light-transmitting openings BM1 corresponding to the adjacent second sub-pixels R in the row direction.
  • the settings of the second light-transmitting opening BM2 and the third light-transmitting opening S1 will not affect the original circuit settings on the display substrate, and the original circuit settings will not affect the signal light sequentially passing through the second light-transmitting openings.
  • BM2 and the third light-transmitting opening S1 reach the image sensor.
  • the orthographic projection of each of the plurality of spacers PS on the base substrate 110 is respectively located on the base substrate 110 of the sub-pixel opening 130 of the second sub-pixel G adjacent in the column direction. between the orthographic projections, and are respectively located between the orthographic projections of the sub-pixel openings 130 of the first sub-pixel R and the third sub-pixel B adjacent in the row direction on the base substrate 110 .
  • the orthographic projection of each of the plurality of spacers PS on the base substrate 110 is related to the sub-pixel opening of the first sub-pixel R among the adjacent first sub-pixels R and third sub-pixels B.
  • the shortest distance L11 of the orthographic projection of the sub-pixel opening 130 on the substrate substrate 110 is greater than the orthogonal distance L11 of the sub-pixel opening 130 of the third sub-pixel B among the adjacent first sub-pixel R and the third sub-pixel B on the substrate substrate 110 .
  • the shortest projected distance L12 that is, the spacer PS provided between the adjacent first sub-pixel R and the third sub-pixel B is closer to the third sub-pixel than the sub-pixel opening 130 of the first sub-pixel R. Subpixel opening 130 of B.
  • the orthographic projection of each of the plurality of spacers PS on the base substrate 110 and the sub-pixel opening 130 of the adjacent second sub-pixel G are on the base substrate 110
  • the shortest distance L13 of the front projection is basically the same, that is, the distance between the spacer PS provided between adjacent second sub-pixels G and the sub-pixel opening 130 of the adjacent second sub-pixel G is basically the same.
  • the plurality of spacers PS and the third light-transmitting openings S1 are periodically arranged in the display substrate without affecting each other.
  • a first sub-pixel R, two second sub-pixels G and a third sub-pixel B form a repeating unit, and each repeating unit is provided with two corresponding third sub-pixels.
  • each third light-transmitting opening S1 is provided with a second light-transmitting opening BM2, or, in some embodiments, one third light-transmitting opening S1 is provided for every two or more third light-transmitting openings S1.
  • a second light-transmitting opening BM2 is provided correspondingly, that is, one third light-transmitting opening S1 of every two or more third light-transmitting openings S1 corresponds to a second light-transmitting opening BM2 to form a set hole, while the other The third light-transmitting opening S1 is blocked by the black matrix layer BM and is not used to form the hole.
  • one spacer PS is provided corresponding to each repeating unit, or, in other embodiments, one spacer PS can be provided corresponding to two or more repeating units. PS, the embodiments of the present disclosure do not limit this.
  • the display substrate further includes an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate substrate 110 , and the black matrix layer BM is disposed far away from the encapsulation layer EN.
  • the encapsulation layer EN may be a composite encapsulation layer, including a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer (not shown in the figure) sequentially disposed on the light-emitting device EM to improve the encapsulation effect.
  • color filters for multiple sub-pixels may be disposed in a composite encapsulation layer, such as between two adjacent sub-encapsulation layers in the composite encapsulation layer.
  • the composite encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer and a third inorganic encapsulation layer that are sequentially disposed on the light emitting device EM.
  • the color filter It may be provided between the second inorganic encapsulation layer and the third inorganic encapsulation layer.
  • the display substrate further includes a touch layer FM disposed on a side of the encapsulation layer EN away from the base substrate 110 , and the black matrix layer BM is disposed far away from the touch layer FM.
  • the touch layer FM is disposed on a side of the encapsulation layer EN away from the base substrate 110 .
  • FIG. 11 shows a schematic plan view of the touch layer FM.
  • the touch layer FM includes a plurality of touch traces TL, and the plurality of touch traces TL are on the base substrate 110
  • the orthographic projection of the plurality of second light-transmitting openings BM2 on the base substrate 110 does not overlap.
  • the orthographic projection of the plurality of touch traces TL on the base substrate 110 does not overlap with the orthographic projection of the plurality of first light-transmitting openings BM1 on the base substrate 110 .
  • the plurality of touch traces TL are blocked by the black matrix layer BM to prevent light from irradiating the touch traces TL and affecting the signal transmission performance of the touch traces TL.
  • a plurality of touch traces TL are connected with the first color filter RCF, the second color filter GCF and At least two of the third color filters BCF have different distances.
  • the distance between the touch trace TL and the third color filter BCF is greater than the distance from the first color filter RCF. Since the shape and arrangement of the third color filter BCF are irregular, the distance between the touch trace TL and the third color filter BCF is set larger in this direction to avoid the touch trace TL and the third color filter BCF.
  • the third color filter BCF overlaps in this direction, or the overlap size is too large.
  • the first sub-pixel R and the third sub-pixel B are arranged in multiple rows and multiple columns, and multiple first sub-pixels R and multiple third sub-pixels located in the same column B are arranged alternately.
  • at least some of the plurality of touch traces TL have gaps NT1/NT2/NT3 between adjacent first sub-pixels R and third sub-pixels B located in the same column.
  • At least part of the plurality of touch traces TL is on one side or close to the third sub-pixel B among the adjacent first sub-pixels R and third sub-pixels B located in the same column. There is a gap NT1 on one side of the first sub-pixel R. At this time, at least part of the plurality of touch traces TL has a gap between the adjacent first sub-pixel R and the third sub-pixel B located in the same column. ; Alternatively, at least part of the plurality of touch traces TL is on one side of the adjacent first sub-pixel R and the third sub-pixel B located in the same column close to the third sub-pixel B and close to the first sub-pixel R. have gaps NT2/NT3 on both sides. At this time, at least part of the plurality of touch traces TL has two gaps between adjacent first sub-pixels R and third sub-pixels B located in the same column.
  • At least part of the plurality of touch traces TL is close to the third sub-pixel in the adjacent first sub-pixel R and the third sub-pixel B located in the Nth column.
  • One side of the pixel B or a side close to the first sub-pixel R has a notch NT1, and at least some of the plurality of touch traces TL are located between the adjacent first sub-pixel R and the N+1th column.
  • both the side close to the third sub-pixel B and the side close to the first sub-pixel R have notches NT2/NT3.
  • the display substrate may also include other structures such as a cover plate.
  • other structures such as a cover plate.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • Figure 12 is an equivalent circuit schematic diagram of an 8T1C pixel driving circuit.
  • the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 storage capacitor C and multiple signal lines (such as data signal line Data, first scanning signal line Gate , the second scanning signal line GateN, the reset control signal line Reset, the first initial signal line INIT1, the second initial signal line INIT2, the first power line VDD, the second power line VSS and the light emission control signal line EM, etc.).
  • the gate of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the second initial signal line INIT2, and the second electrode of the first transistor T1 is connected to the fifth node N5.
  • the gate of the second transistor T2 is connected to the first scanning signal line Gate, the first electrode of the second transistor T2 is connected to the fifth node N5, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the first scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the gate electrode of the fifth transistor T5 is connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first node of the light-emitting device). pole) connection.
  • the gate of the seventh transistor T7 is connected to the first scanning signal line Gate or the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the seventh transistor T7 is connected to the fourth Node N4 is connected.
  • the gate electrode of the eighth transistor T8 is connected to the second scanning signal line GateN, the first electrode of the eighth transistor T8 is connected to the fifth node N5, and the second electrode of the eighth transistor T8 is connected to the first node N1.
  • the first terminal of the storage capacitor C is connected to the first power line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.
  • the first to seventh transistors T1 to T7 may be N-type thin film transistors, and the eighth transistor T8 may be a P-type thin film transistor; or, the first to seventh transistors T1 to T7 may be P-type thin film transistors. , the eighth transistor T8 may be an N-type thin film transistor.
  • the first to seventh transistors T1 to T7 may be Low Temperature Polysilicon (LTPS) thin film transistors (TFT), and the eighth transistor T8 may be Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide). Gallium Zinc Oxide, IGZO) thin film transistor.
  • LTPS Low Temperature Polysilicon
  • TFT Low Temperature Polysilicon
  • IGZO Indium Gallium Zinc Oxide
  • the indium gallium zinc oxide thin film transistor generates less leakage current than the low temperature polysilicon thin film transistor. Therefore, setting the eighth transistor T8 as an indium gallium zinc oxide thin film transistor can significantly reduce the leakage current. to improve the low-frequency and low-brightness flicker problems of the display panel.
  • the first transistor T1 and the second transistor T2 do not need to be configured as indium gallium zinc oxide thin film transistors. Since the size of the low-temperature polysilicon thin film transistor is generally smaller than the indium gallium zinc oxide thin film transistor, the pixel driving method of the embodiment of the present disclosure The space occupied by the circuit will be relatively small, which will help improve the resolution of the display panel.
  • the above-mentioned pixel driving circuit provided by the embodiment of the present disclosure combines the good switching characteristics of LTPS-TFT and the low leakage characteristics of Oxide-TFT, and can realize low-frequency driving (1Hz ⁇ 60Hz) and greatly reduce the power consumption of the display screen.
  • the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS continuously provides a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the signal of the first scanning signal line Gate is the scanning signal in the pixel driving circuit of this display row
  • the signal of the reset control signal line Reset is the scanning signal of the pixel driving circuit of the previous display row. That is, for the nth display row, the first scanning signal The signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1).
  • the signal of the reset control signal line Reset of this display row is the same as the signal of the first scanning signal line Gate in the pixel driving circuit of the previous display row.
  • the signals can be the same signal to reduce the signal lines of the display panel and achieve a narrow frame of the display panel.
  • the first scanning signal line Gate, the second scanning signal line GateN, the reset control signal line Reset, the emission control signal line EM, the first initial signal line INIT1 and the second initial signal line INIT2 all extend in the horizontal direction.
  • the second power line VSS, the first power line VDD and the data signal line DATA all extend in the vertical direction.
  • At least part of the first initial signal line INIT1, the second initial signal line INIT2, the second power line VSS, and the first power line VDD may be a mesh structure, that is, including both horizontal and vertical extensions. extended part.
  • FIG 13 is a working timing diagram of a pixel driving circuit.
  • the following describes exemplary embodiments of the present disclosure through the working process of the pixel driving circuit illustrated in Figure 12.
  • the pixel driving circuit in Figure 12 includes 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C.
  • the embodiment takes as an example that the first to seventh transistors T1 to T7 are P-type transistors, the eighth transistor T8 is an N-type transistor, and the gate of the seventh transistor T7 is connected to the first scanning signal line Gate.
  • the working process of the pixel driving circuit may be as follows.
  • the first stage t1 is called the reset stage.
  • the signals of the first scanning signal line Gate, the reset control signal line Reset, the second scanning signal line GateN and the light-emitting control signal line EM are all high-level signals.
  • the reset control signal line Reset The signal is a low level signal.
  • the high level signal of the emission control signal line EM turns off the fifth transistor T5 and the sixth transistor T6, the high level signal of the second scanning signal line GateN turns on the eighth transistor T8, and the low level of the reset control signal line Reset
  • the signal causes the first transistor T1 to be turned on. Therefore, the voltage of the first node N1 is reset to the second initial voltage Vinit2 provided by the second initial signal line INIT2. Then the electrical position of the reset control signal line Reset is high, and the first transistor T1 is turned off. . Since the fifth transistor T5 and the sixth transistor T6 are turned off, the light-emitting device EL does not emit light at this stage.
  • the second stage t2 is called the data writing stage.
  • the signal of the first scanning signal line Gate is a low-level signal.
  • the fourth transistor T4, the second transistor T2 and the seventh transistor T7 are turned on, and the data signal line Data outputs the data voltage.
  • the voltage of the fourth node N4 is reset to the first initial voltage Vinit1 provided by the first initial voltage line INIT1, completing the initialization.
  • the third transistor T3 is turned on.
  • the fourth transistor T4 and the second transistor T2 are turned on so that the data voltage output by the data signal line Data passes through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the turned-on third node N3, and the turned-on third transistor T3.
  • the second transistor T2, the fifth node N5 and the eighth transistor T8 are provided to the first node N1, and charge the sum of the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 into the storage capacitor C.
  • the storage capacitor C The voltage at the second end (first node N1) is Vdata+Vth, Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.
  • the signal of the light-emitting control signal line EM is a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off to ensure that the light-emitting device EL does not emit light.
  • the third stage t3 is called the light-emitting stage.
  • the signals of the first scanning signal line Gate and the reset control signal line Reset are high-level signals, and the signals of the light-emitting control signal line EM and the second scanning signal line GateN are both low-level signals. .
  • the high-level signal of the reset control signal line Reset turns off the seventh transistor T7
  • the low-level signal of the light-emitting control signal line EM turns on the fifth transistor T5 and the sixth transistor T6, and the power output from the first power line VDD
  • the voltage provides a driving voltage to the first pole (ie, the fourth node N4) of the light-emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting device EL to emit light.
  • the driving current flowing through the third transistor T3 (ie, the third transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata+Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the light-emitting device EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.
  • the current I flowing through the light-emitting device EL has nothing to do with the threshold voltage Vth of the third transistor T3. This eliminates the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensures the uniformity of brightness.
  • the pixel driving circuit eliminates the residual positive charge of the light-emitting device EL after the last light emission, realizes compensation for the gate voltage of the third transistor, and avoids the threshold voltage drift of the third transistor from driving the light-emitting device EL.
  • the influence of current improves the uniformity of the display image and the display quality of the display panel.
  • the pixel driving circuit of the embodiment of the present disclosure can reset the light-emitting device EL by initializing the fourth node N4 to the signal of the first initial signal line INIT1 and by initializing the fifth node N5 to the signal of the second initial signal line INIT2.
  • the voltage and the reset voltage of the first node N1 are adjusted separately to achieve better display effects and improve problems such as low-frequency flickering.
  • FIGS. 14-25 show schematic plan views of various layers of a display substrate provided by at least one embodiment of the present disclosure being stacked in sequence.
  • FIG. 14 shows a schematic plan view of the light-shielding layer, which includes a plurality of first light-transmitting openings (third openings) S1.
  • FIG. 15 shows a schematic plan view of a first semiconductor layer stacked behind a light-shielding layer.
  • the first semiconductor layer includes active layers of a plurality of thin film transistors.
  • the first semiconductor layer may be made of silicon material, which includes amorphous silicon and polycrystalline silicon; in some embodiments, the first semiconductor layer may be made of amorphous silicon a-Si, and polysilicon is formed through crystallization or laser annealing.
  • the first semiconductor layer may include a first active layer 10 of the first transistor T1, a second active layer 20 of the second transistor T2, a third active layer 30 of the third transistor T3, a fourth The fourth active layer 40 of the transistor T4, the fifth active layer 50 of the fifth transistor T5, the sixth active layer 60 of the sixth transistor T6, and the seventh active layer 70 of the seventh transistor T7.
  • the first active layer 10 , the second active layer 20 , the third active layer 30 , the fourth active layer 40 , the fifth active layer 50 , the sixth active layer 60 and the seventh active layer 70 are interconnected. Connected one-piece structure.
  • the shape of the third active layer 30 may be in the shape of a "ji"
  • the first active layer 10 , the second active layer 20 , the fourth active layer 40 , the fifth active layer 50 , and the The sixth active layer 60 and the seventh active layer 70 may be in a "1" shape.
  • the first semiconductor layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the channel region of the third active layer 30 extends along the row direction, and the first active layer 10 , the second active layer 20 , the fourth active layer 40 , the fifth active layer 50 , and the third active layer 30 extend along the row direction.
  • the channel regions of the sixth active layer 60 and the seventh active layer 70 extend in the column direction.
  • the orthographic projection of the third light-transmitting opening S1 on the base substrate 110 is adjacent to the orthographic projection of the sixth active layer 60 and the seventh active layer 70 on the base substrate 110 .
  • the second light-transmitting opening S1 The orthographic projection of the opening BM2 on the base substrate 110 is adjacent to the orthographic projections of the sixth active layer 60 and the seventh active layer 70 on the base substrate 110 .
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor may all be LTPS thin film transistor.
  • p-Si polycrystalline silicon
  • FIG. 16 shows a schematic plan view of a first conductive layer stack behind a first semiconductor layer.
  • the first conductive layer may include: a first scanning signal line Gate_P, a reset control signal line Reset_P, a light emission control signal line EM_P, and a first plate Ce1 of the storage capacitor C.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first scanning signal line Gate_P, the reset control signal line Reset_P and the light emitting control signal line EM_P all extend along the first direction X.
  • the reset control signal line Reset_P is located on the side of the first scanning signal line Gate_P away from the emission control signal line EM_P, and the first plate Ce1 of the storage capacitor is disposed between the first scanning signal line Gate_P and the emission control signal line EM_P between.
  • the pixel driving circuit layer (such as the above-mentioned first conductive layer) includes a first signal line (such as a light emission control signal line EM_P in some embodiments) and a second signal line (such as in some embodiments) arranged in parallel and periodically arranged. In the embodiment, it is the reset control line Reset_P).
  • the first signal line and the second signal line are configured to provide different electrical signals to multiple sub-pixels.
  • the orthographic projections of the multiple third light-transmitting openings S1 on the substrate substrate 110 are respectively located at The orthographic projection of a first signal line (for example, the light emission control signal line EM_P) on the substrate 110 and a second signal line (for example, the reset control line Reset_P) closest to the first signal line are on the substrate 110 . between the orthographic projections on the substrate 110.
  • the orthographic projections of the plurality of second light-transmitting openings BM2 on the substrate 110 are respectively located between the orthographic projections of a first signal line (for example, the light-emitting control signal line EM_P) on the substrate 110 and the first signal line EM_P.
  • a second signal line (for example, a reset control line Reset_P) that is closest to a signal line is between orthographic projections on the base substrate 110 .
  • the plurality of sub-pixels include a first row of sub-pixels RO1 and a second row of sub-pixels RO2 adjacent to the first row of sub-pixels RO1 and located below the first row of sub-pixels RO1.
  • the pixel driving circuit of the first row of sub-pixels RO1 is shared.
  • the pixel driving circuit of the second row of sub-pixels RO2 shares one light-emitting control signal line EM_P and one reset control line Reset_P.
  • the pixel driving circuit of the first row of sub-pixels RO1 shares one A row of third light-transmitting openings is included between the orthographic projection of the emission control signal line EM_P on the substrate substrate 110 and the orthographic projection of the reset control line Reset_P shared by the pixel driving circuit of the second row sub-pixel RO2 on the substrate substrate 110 Orthographic projection of S1 on the base substrate 110 .
  • the orthographic projection of the light-emitting control signal line EM_P common to the pixel driving circuits of the first row of sub-pixels RO1 on the base substrate 110 and the common reset control line Reset_P of the pixel driving circuit of the second row of sub-pixels RO1 are on the base substrate 110 .
  • the orthographic projections on the substrate 110 include a row of orthographic projections of the second light-transmitting openings BM2 on the base substrate 110 .
  • the first plate Ce1 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate Ce1 on the base substrate 110 is consistent with the third active terminal of the third transistor T3. There is an overlapping area in the orthographic projection of layer 30 on base substrate 110 .
  • the first plate Ce1 also serves as the gate of the third transistor T3.
  • the area where the reset control signal line Reset_P overlaps with the first active layer of the first transistor T1 serves as the gate electrode of the first transistor T1
  • the first scanning signal line Gate_P overlaps with the second active layer of the second transistor T2.
  • the area where the source layers overlap serves as the gate electrode of the second transistor T2
  • the area where the first scanning signal line Gate_P overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4
  • the emission control signal line EM_P The area overlapping the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5.
  • the area overlapping the emission control signal line EM_P and the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. gate.
  • the reset control signal line Reset_P in the sub-pixels of the next row of each row of sub-pixels (the same signal as the first scanning signal line Gate_P in the sub-pixels of this row) is connected to the seventh active terminal of the seventh transistor T7 in the sub-pixels of this row.
  • the area where the layers overlap serves as the gate electrode of the seventh transistor T7.
  • FIG. 17 shows a schematic plan view of a second conductive layer stack behind the first conductive layer.
  • the second conductive layer includes: the second plate Ce2 of the storage capacitor C and the first branch GateN_B1 of the second scanning signal line GateN.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first branch GateN_B1 of the second scanning signal line GateN extends along the first direction X.
  • the second plate Ce2 of the storage capacitor is located between the first branch GateN_B1 of the second scanning signal line GateN and the light emission control signal line EM_P.
  • the outline of the second electrode plate Ce2 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate Ce2 on the base substrate 110 is aligned with the first electrode plate Ce1 on the substrate.
  • the orthographic projections on the base substrate 110 have overlapping areas.
  • the second electrode plate Ce2 is provided with an opening H, and the opening H may be located in the middle of the second electrode plate Ce2.
  • the opening H may be a regular hexagon, so that the second electrode plate Ce2 forms a ring structure.
  • the opening H exposes the third insulating layer covering the first electrode plate Ce1, and the orthographic projection of the first electrode plate Ce1 on the base substrate 110 includes the orthographic projection of the opening H on the base substrate 110.
  • the opening H is configured to accommodate a subsequently formed fourth via hole.
  • the fourth via hole is located in the opening H and exposes the first plate Ce1, so that the second electrode of the subsequently formed eighth transistor T8 is connected to the second electrode of the eighth transistor T8.
  • the first plate Ce1 is connected.
  • FIG. 18 shows a schematic plan view of a second semiconductor layer stack behind a second conductive layer.
  • the second semiconductor layer of each sub-pixel may include an eighth active layer 80 of an eighth transistor T8.
  • the eighth active layer 80 extends along the second direction Y, and the eighth active layer 80 may be shaped like a dumbbell.
  • the second semiconductor layers of any two adjacent columns of sub-pixels have a mirror-symmetric structure.
  • the second semiconductor layer may be made of oxide, that is, the eighth transistor is an oxide thin film transistor.
  • FIG. 19 shows a schematic plan view of a third conductive layer stack behind the second conductive layer.
  • the third conductive layer includes: a second branch GateN_B2 of the second scanning signal line GateN and a second initial signal line INIT2.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the second branch GateN_B2 of the second scanning signal line GateN extends along the first direction X, and the second branch GateN_B2 of the second scanning signal line GateN is close to the second branch Gate_B2 of the first scanning signal line Gate. In some embodiments, a region where the second branch GateN_B2 of the second scanning signal line GateN overlaps the eighth active layer 80 serves as the gate of the eighth transistor.
  • the orthographic projection of the second branch GateN_B2 of the second scanning signal line on the base substrate 110 overlaps with the orthographic projection of the first branch GateN_B1 of the second scanning signal line on the base substrate 110 .
  • the first branch GateN_B1 of the second scanning signal line and the second branch GateN_B2 of the second scanning signal line may be connected through signal lines in the peripheral area.
  • the second initial signal line INIT2 extends along the first direction
  • the orthographic projection of the third light-transmitting opening S1 on the base substrate 110 is also located directly on the base substrate 110 of the light-emitting control signal line EM_P and a second initial signal line INIT2 nearest to the light-emitting control signal line EM_P. between projections.
  • the orthographic projection of the second light-transmitting opening BM2 on the base substrate 110 is also located on the light-emitting control signal line EM_P and a second initial signal line INIT2 closest to the light-emitting control signal line EM_P on the base substrate 110 between the orthographic projections on.
  • FIG. 20 shows a planar distribution diagram of a plurality of via holes in the insulating layer formed on the third conductive layer.
  • a plurality of via holes are provided in the insulating layer.
  • the plurality of via holes include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole Hole V5, sixth via hole V6, seventh via hole V7, eighth via hole V8, ninth via hole V9, tenth via hole V10 and eleventh via hole V11.
  • the first via hole V1 exposes the surface of the second region of the eighth active layer 80 .
  • the second via hole exposes the surface of the first region of the eighth active layer 80 .
  • the third via V3 exposes the surface of the first region of the second active layer.
  • the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor T2 to the second active layer through the via hole.
  • the fourth via hole V4 is located within the opening H of the second electrode plate Ce2, and the orthographic projection of the fourth via hole V4 on the base substrate 110 is within the range of the orthographic projection of the opening H on the base substrate 110.
  • the hole V4 exposes the surface of the first electrode plate Ce1.
  • the fourth via hole V4 is configured to connect the subsequently formed third connection electrode 43 to the first electrode plate Ce1 through the via hole.
  • the fifth via V5 exposes the surface of the first region of the fifth active layer.
  • the fifth via hole V5 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the fifth active layer through the via hole.
  • the sixth via hole V6 is located in the area where the second electrode plate Ce2 is located, and the orthographic projection of the sixth via hole V6 on the base substrate 110 is within the range of the orthographic projection of the second electrode plate Ce2 on the base substrate 110.
  • the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the via hole V6 are etched away, exposing the surface of the second electrode plate Ce2.
  • the sixth via hole V6 is configured so that the fifth connection electrode 45 formed later is connected to the second electrode plate Ce2 through the via hole.
  • the seventh via hole V7 exposes the surface of the first region of the first active layer.
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via hole.
  • the eighth via hole V8 exposes the surface of the first region of the seventh active layer.
  • the eighth via hole V8 is configured to allow the subsequently formed first initial signal line to be connected to the seventh active layer through the via hole.
  • the ninth via hole V9 exposes the surface of the second area of the sixth active layer.
  • the ninth via hole V9 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the sixth active layer through the via hole. Seven active layer connections.
  • the tenth via hole V10 exposes the surface of the first region of the fourth active layer.
  • the tenth via hole V10 is configured so that the second connection electrode 42 formed later is connected to the fourth active layer through the via hole.
  • the eleventh via hole V11 exposes the surface of the second initial signal line INIT2.
  • the eleventh via hole V11 is configured so that the sixth connection electrode 46 formed later is connected to the second initial signal line INIT2 through the via hole.
  • Figure 21 shows a schematic plan view of the fourth conductive layer stack behind the third conductive layer.
  • the fourth conductive layer includes: a first initial signal line INIT1, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45 and a third connection electrode.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 source-drain metal
  • the fourth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first initial signal line INIT1 extends along the first direction X, and the first initial signal line INIT1 is connected to the first region of the seventh active layer through the eighth via V8, so that the seventh transistor T7 The first pole has the same potential as the first initial signal line INIT1.
  • one end of the first connection electrode 41 is connected to the first region of the second active layer (also the second region of the first active layer) through the third via hole V3, and the other end passes through the second via hole V3.
  • V2 is connected to the first area of the eighth active layer.
  • the first connection electrode 41 may serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor, and the second electrode of the first transistor.
  • the second connection electrode 42 is connected to the first region of the fourth active layer through the tenth via hole V10 on the one hand, and is connected to the subsequently formed data signal through the subsequently formed thirteenth via hole V13 on the other hand. Line Data connection.
  • the second connection electrode 42 may serve as the first electrode of the fourth transistor T4.
  • one end of the third connection electrode 43 is connected to the second region of the eighth active layer through the first via hole V1, and the other end thereof is connected to the first plate Ce1 through the fourth via hole V4.
  • the third connection electrode 43 may serve as the second electrode of the eighth transistor T8.
  • the fourth connection electrode 44 passes through the ninth via V9 and the second region of the sixth active layer (also the second region of the seventh active layer) on the one hand, and on the other hand passes through the subsequently formed
  • the twelfth via hole V12 is connected to the first electrode connection electrode formed later.
  • the fourth connection electrode 44 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the fifth connection electrode 45 (power connection electrode) is connected to the second plate Ce2 through the sixth via hole V6 on the one hand, and is connected to the third electrode of the fifth active layer through the fifth via hole V5 on the other hand.
  • One area connection, the fifth connection electrode 45 is configured to be connected to the subsequently formed first power line VDD through the subsequently formed fourteenth via hole V14.
  • one end of the sixth connection electrode 46 is connected to the first region of the first active layer through the seventh via hole V7, and the other end is connected to the second initial signal line through the eleventh via hole V11, so that the third The first pole of a transistor T1 and the second initial signal line INIT2 have the same potential.
  • Figure 22 shows a schematic plan view of the first planarization layer stack behind the fourth conductive layer and the fifth conductive layer stack behind the first planarization layer.
  • the first planarization layer 97 includes: a twelfth via hole V12, a thirteenth via hole V13, and a fourteenth via hole V14;
  • the fifth conductive layer includes: a data signal line Data, the first power supply line VDD and the first electrode connection electrode 51 .
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the fifth conductive layers of any two adjacent columns of sub-pixels may not have a mirror-symmetric structure, and a second opening or a second second opening below the third opening may be added as needed.
  • the area of the source-drain metal layer is used to increase the flatness of the first electrode (anode) formed on the upper layer, so that the entire sub-pixel is located on a plane, thereby reducing color shift and improving display quality.
  • the first power lines VDD in two adjacent columns of sub-pixels may be an integral structure connected to each other.
  • the anode formed on the upper layer can be made flatter.
  • the driving circuit layer includes third signal lines (such as the above-mentioned first power supply line VDD) that are arranged parallel to each other and arranged periodically.
  • the third signal lines extend along the second direction Y and are connected to the first signal line and the second signal line respectively. intersect, the third signal line is configured to provide power signals to multiple sub-pixels.
  • the third signal line includes a hollow portion OD, and the orthographic projection of the third light-transmitting opening S1 on the base substrate 110 is located at the hollow portion OD. within the orthographic projection on the base substrate 110 .
  • the orthographic projection of the second light-transmitting opening BM2 on the base substrate 110 is located within the orthographic projection of the hollow portion OD1 on the base substrate 110 .
  • the first electrode connection electrode 51 may be in a rectangular shape, and the first electrode connection electrode 51 is connected to the fourth connection electrode 44 through the twelfth via hole V12.
  • the first power line VDD is connected to the fifth connection electrode 45 through the fourteenth via hole V14.
  • the data signal line Data extends along the second direction Y, and the data signal line Data is connected to the second connection electrode 42 through the thirteenth via hole V13, because the second connection electrode 42 is connected to the second connection electrode 42 through the tenth via hole V10.
  • the first area of the fourth active layer is connected, thus realizing the connection between the data signal line and the first pole of the fourth transistor, so that the data signal transmitted by the data signal line Data can be written into the fourth transistor.
  • FIG. 23 shows a schematic plan view of the second planarization layer stack behind the fifth conductive layer.
  • the second planarization layer 98 includes a fifteenth via V15.
  • the fifteenth via hole V15 is located in the area where the first electrode connecting electrode 51 is located, and the second flat layer in the fifteenth via hole V15 is removed to expose the surface of the first electrode connecting electrode 51.
  • the five via holes V15 are configured to allow a subsequently formed first electrode (eg, an anode) to be connected to the first electrode connecting electrode 51 through the via holes.
  • Figure 24 shows a schematic plan view of the first electrode layer.
  • the first electrode layer includes first electrodes 141 of a plurality of sub-pixels.
  • Each first electrode 141 includes a main body part 141A and a connection part 141B.
  • the main body part 141A is exposed by the sub-pixel opening 130 , and the connection part 141B passes through respectively.
  • the fifteenth via hole V15 is connected to the first electrode 51 .
  • the pixel driving circuit can drive The light-emitting device emits light.
  • FIG. 25 shows a schematic plan view of the pixel definition layer PDL.
  • the pixel definition layer PDL includes a plurality of sub-pixel openings 130.
  • the shape of the plurality of sub-pixel openings 130 is consistent with the shape of the main body portion 141A of the first electrode 141.
  • the substrate is the same and has a size slightly smaller than that of the main body 141A to fully expose the main body 141A.
  • the pixel driving circuit layer has multiple pixel driving circuits and multiple scanning signal lines Gate (for example, taking Gate_P as an example) that provide scanning signals for the multiple pixel driving circuits and multiple pixels.
  • the driving circuit provides a plurality of reset control signal lines Reset (for example, taking Reset_P as an example) of the reset control signal.
  • Reset for example, taking Reset_P as an example
  • Reset_P Reset_P
  • a scanning signal line Gate for example, Gate_P
  • the multiple spacers PS are respectively in contact with one reset control signal.
  • the line Reset (for example, Reset_P) and at least one of the scanning signal lines Gate (for example, Gate_P) closest to the reset control signal line overlap, for example, as shown in the figure, it overlaps with the scanning signal line Gate (for example, Gate_P), In other embodiments, it may also overlap with the reset control signal line Reset (for example, Reset_P), or overlap with the above two at the same time. At this time, at least part of the structure of the spacer PS is located between the reset control signal line Reset (for example, Reset_P) and the scanning signal line Gate closest to the reset control signal line.
  • the substrate substrate 110 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polyether One or more of styrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the materials of the first inorganic material layer and the second inorganic material layer can be Silicon nitride (SiNx) or silicon oxide (SiOx) is used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti). ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti).
  • Mo molybdenum
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • the insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multi-layer or composite layer.
  • the planarization layer can be made of organic materials, and the multiple traces TL of the touch layer FM can be made of metal oxide materials such as indium tin oxide ITO or indium zinc oxide IZO.
  • the first semiconductor layer may be polysilicon (p-Si), and the second semiconductor layer (SML2) may be oxide.
  • the stacked structure of the display substrate provided by the embodiments of the present disclosure is only an illustrative description. In some embodiments, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. The embodiments of the present disclosure are not limited here. .
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

Abstract

一种显示基板以及显示装置，该显示基板具有多个子像素，且包括衬底基板(110)、像素驱动电路层(120)、像素界定层(PDL)和隔垫物层(140)，像素驱动电路层(120)设置在衬底基板(110)上，像素界定层(PDL)设置在像素驱动电路层(120)的远离衬底基板(110)的一侧，包括多个子像素开口(130)，其中，多个子像素中的每个包括设置在像素驱动电路层(120)中的像素驱动电路以及至少部分设置在子像素开口(130)中的发光器件(EM)，隔垫物层(140)设置在像素界定层(PDL)的远离衬底基板(110)的一侧，包括多个隔垫物(PS)，其中，多个隔垫物(PS)的透光率小于5％。该显示基板基本不会产生色分离等不良现象，具有更好的显示效果。

Description

显示基板以及显示装置 技术领域
本公开的实施例涉及一种显示基板以及显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。在OLED显示装置中，各个结构的设置方式以及各个结构之间的位置关系是影响显示装置的显示效果的重要因素。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有多个子像素，且包括衬底基板、像素驱动电路层、像素界定层以及隔垫物层。像素驱动电路层设置在所述衬底基板上，像素界定层设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括多个子像素开口，其中，所述多个子像素中的每个包括设置在所述像素驱动电路层中的像素驱动电路以及至少部分设置在所述子像素开口中的发光器件，隔垫物层设置在所述像素界定层的远离所述衬底基板的一侧，包括多个隔垫物，其中，所述多个隔垫物的透光率小于5％。
例如，本公开至少一实施例提供的显示基板中，所述像素界定层在除所述多个子像素开口以外的部分的透光率小于5％。
例如，本公开至少一实施例提供的显示基板中，所述隔垫物层与所述像素界定层的材料相同。
例如，本公开至少一实施例提供的显示基板中，所述多个隔垫物与所述多个子像素开口的最小距离为L，且1微米＜L＜8微米。
例如，本公开至少一实施例提供的显示基板中，所述多个隔垫物中至少部分隔垫物的平面形状为矩形。
例如，本公开至少一实施例提供的显示基板中，所述矩形的长和宽的尺 寸范围为13微米-19微米，在垂直于所述衬底基板的方向上，所述多个隔垫物的高度为0.5微米-2.0微米。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路层多个像素驱动电路以及为所述多个像素驱动电路提供扫描信号的多条扫描信号线以及为所述多个像素驱动电路提供复位控制信号的多条复位控制信号线，在平行于所述衬底基板的方向上，所述多个隔垫物中的至少部分分别位于一条复位控制信号线以及与所述一条复位控制信号线最近的一条扫描信号线之间。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路层多个像素驱动电路以及为所述多个像素驱动电路提供扫描信号的多条扫描信号线以及为所述多个像素驱动电路提供复位控制信号的多条复位控制信号线，在垂直于所述衬底基板的方向上，所述多个隔垫物中的至少部分分别与一条复位控制信号线以及与所述一条复位控制信号线最近的一条扫描信号线中的至少一个交叠。
例如，本公开至少一实施例提供的显示基板还包括设置在所述发光器件的远离所述衬底基板一侧的黑矩阵层，其中，所述黑矩阵层包括多个第一透光开口，所述多个子像素开口在所述衬底基板上的正投影分别位于所述多个第一透光开口在所述衬底基板上的正投影内部，且所述多个子像素开口在所述衬底基板上的正投影的边界分别与所述多个第一透光开口在所述衬底基板上的正投影的边界的距离为1.0微米-6.5微米。
例如，本公开至少一实施例提供的显示基板还包括多个彩色滤光片，其中，所述多个彩色滤光片分别至少部分设置在所述多个第一透光开口中；对于一个第一透光开口以及至少部分设置在所述一个第一透光开口中的一个彩色滤光片，所述一个第一透光开口在所述衬底基板上的正投影位于所述一个彩色滤光片在所述衬底基板上的正投影内部。
例如，本公开至少一实施例提供的显示基板中，所述黑矩阵层还包括多个第二透光开口，所述多个第二透光开口分别设置在所述多个第一透光开口中相邻的两个第一透光开口之间。
例如，本公开至少一实施例提供的显示基板还包括设置在所述衬底基板上的遮光层，其中，所述像素驱动电路层设置在所述遮光层的远离所述衬底基板的一侧，所述遮光层包括多个第三透光开口，所述多个第三透光开口中 的至少部分在所述衬底基板上的正投影分别与所述多个第二透光开口在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第三透光开口在所述衬底基板上的正投影分别位于所述多个第二透光开口在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述多个第三透光开口中的至少部分在所述衬底基板上的正投影的边界分别与所述多个第二透光开口在所述衬底基板上的正投影的边界的距离为0.5微米-1.5微米。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括第一子像素、第二子像素和第三子像素，所述多个第二透光开口中的至少部分位于相邻的第一子像素和第三子像素对应的第一透光开口之间，且与第一子像素对应的第一透光开口的距离不同于与第三子像素对应的第一透光开口的距离。
例如，本公开至少一实施例提供的显示基板中，所述第一子像素和所述第三子像素排列为多行多列，位于同一列的多个第一子像素和多个第三子像素交替排列，且位于同一列的相邻的第一子像素和第三子像素对应的第一透光开口之间设置一个第二透光开口。
例如，本公开至少一实施例提供的显示基板中，一个第一子像素、两个第二子像素和一个第三子像素组成一个重复单元，多个重复单元阵列排布，多个重复单元中的多个第二子像素排列为多行多列，所述一个第二透光开口还设置在行方向上相邻的第二子像素对应的第一透光开口之间。
例如，本公开至少一实施例提供的显示基板中，所述多个隔垫物的每个在所述衬底基板上的正投影分别位于在列方向上相邻的第二子像素的子像素开口在所述衬底基板上的正投影之间，且分别位于在行方向上相邻的第一子像素和第三子像素的子像素开口在衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述多个隔垫物的每个在所述衬底基板上的正投影与所述相邻的第一子像素和第三子像素中的第一子像素的子像素开口在衬底基板上的正投影的最短距离大于与所述相邻的第一子像素和第三子像素中的第三子像素的子像素开口在衬底基板上的正投影的最短距离。
例如，本公开至少一实施例提供的显示基板中，所述多个隔垫物的每个 在所述衬底基板上的正投影与所述相邻的第二子像素的子像素开口在衬底基板上的正投影的最短距离基本相同。
例如，本公开至少一实施例提供的显示基板中，所述第一子像素为红色子像素，所述第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
例如，本公开至少一实施例提供的显示基板还包括设置在所述发光器件的远离所述衬底基板一侧的封装层以及设置在所述封装层的远离所述衬底基板的一侧的触控层，其中，所述黑矩阵层设置在所述封装层的远离所述衬底基板的一侧，所述黑矩阵层设置在所述触控层的远离所述衬底基板的一侧，所述触控层包括多条触控走线，所述多条触控走线在所述衬底基板上的正投影与所述多个第二透光开口在所述衬底基板上的正投影不交叠。
例如，本公开至少一实施例提供的显示基板中，所述第一子像素和所述第三子像素排列为多行多列，位于同一列的多个第一子像素和多个第三子像素交替排列，其中，所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素之间具有缺口。
例如，本公开至少一实施例提供的显示基板中，所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素中靠近所述第三子像素的一侧或者靠近所述第一子像素的一侧具有缺口；或者所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素中靠近所述第三子像素的一侧以及靠近所述第一子像素的一侧均具有缺口。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的部分截面示意图；
图1B为图1A中的显示基板的色分离测试结果图；
图2为本公开至少一实施例提供的显示基板的部分截面示意图；
图3为本公开至少一实施例提供的显示基板中黑矩阵层与隔垫物层叠层的部分平面示意图；
图4为本公开至少一实施例提供的显示基板的色分离测试结果图；
图5为本公开至少一实施例提供的显示基板中黑矩阵层与隔垫物层、第一颜色滤光片叠层的部分平面示意图；
图6为本公开至少一实施例提供的显示基板中黑矩阵层与隔垫物层、彩色滤光片叠层的部分截面示意图；
图7为本公开至少一实施例提供的显示基板中黑矩阵层与隔垫物层、第一颜色滤光片和第二颜色滤光片叠层的部分平面示意图；
图8为本公开至少一实施例提供的显示基板中黑矩阵层与隔垫物层、第一颜色滤光片、第二颜色滤光片和第三颜色滤光片叠层的部分平面示意图；
图9为本公开至少一实施例提供的显示基板的另一部分截面示意图；
图10为本公开至少一实施例提供的显示基板中第二透光开口与第三透光开口叠层的平面示意图；
图11为本公开至少一实施例提供的显示基板中黑矩阵层与触控层、第一颜色滤光片、第二颜色滤光片和第三颜色滤光片叠层的部分平面示意图；
图12为本公开至少一实施例提供的一种8T1C像素驱动电路的等效电路示意图；
图13为本公开至少一实施例提供的为一种像素驱动电路的工作时序图；以及
图14-图25为本公开至少一实施例提供的显示基板中各个层的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件 或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1A示出了一种显示面板的截面示意图，如图1A所示，显示面板包括发光器件EM以及驱动发光器件的像素驱动电路等结构，像素驱动电路包括薄膜晶体管TFT和存储电容等结构，像素驱动电路上方设置有像素界定层PDL，用于界定发光器件EM的发光区域，像素界定层PDL上方设置有隔垫物PS，例如用于在显示面板的制备过程中支撑掩模版等结构。像素界定层PDL和隔垫物PS通常采用聚酰亚胺等有机绝缘材料制作。
在一些实施例中，显示面板还包括彩色滤光片CF，发光器件EM发出的光通过彩色滤光片出射，以形成更纯的单色光。在一些情况下，例如强光下，外界环境光还可能通过彩色滤光片CF射入到显示面板中，并被显示面板中的一些结构反射，例如在像素界定层PDL和隔垫物PS的倒角部分(图中圆形虚线框的部分)反射，反射光会继续从彩色滤光片CF出射，影响显示面板的正常显示，且使显示面板的暗态效果不佳，视觉表现为反射色分离现象。
例如，图1B示出了图1A中显示面板的色分离实测结果图，在测试过程中，采用色分离测试设备，测试72个方向(每5°一个台阶)的6个点位，总共432个点位的拟合的色分离情况，制作出如图1B所示的云图，在显示面板处于暗态情况下，当有光源照射到屏幕上的时候，如图1B所示，从深色到浅色说明，颜色分离越严重，该色分离现象会严重影响显示面板的显示效果。
本公开至少一实施例提供一种显示基板以及显示装置，该显示基板具有多个子像素，且包括衬底基板、像素驱动电路层、像素界定层和隔垫物层，像素驱动电路层设置在衬底基板上，像素界定层设置在像素驱动电路层的远离衬底基板的一侧，包括多个子像素开口，其中，多个子像素中的每个包括设置在像素驱动电路层中的像素驱动电路以及至少部分设置在子像素开口中的发光器件，隔垫物层设置在像素界定层的远离衬底基板的一侧，包括多个隔垫物，其中，多个隔垫物的透光率小于5％。
本公开实施例提供的上述显示基板中，隔垫物基本不透光，且会吸收光，因此外界环境光不会在显示面板内被反射并出射，因此，该显示面板基本不会产生色分离等不良现象，具有更好的显示效果。
下面通过几个具体的实施例对本公开实施例提供的显示基板以及显示装置进行说明。
本公开至少一实施例提供一种显示基板，图2示出了该显示面板的部分截面示意图，图3示出了显示面板的部分结构的平面示意图。如图2和图3所示，该显示基板具有多个子像素，且包括衬底基板110、像素驱动电路层120、像素界定层PDL以及隔垫物层140。
像素驱动电路层120设置在衬底基板110上，包括多个像素驱动电路，每个像素驱动电路包括薄膜晶体管TFT和存储电容(未示出)等结构，例如可以形成为3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C等结构，稍后详述。例如，如图2所示，薄膜晶体管TFT包括有源层121、栅极122、第一极123和第二极124等结构。
像素界定层PDL设置在像素驱动电路层120的远离衬底基板110的一侧，包括多个子像素开口130。多个子像素中的每个包括设置在像素驱动电路层120中的像素驱动电路以及至少部分设置在子像素开口130中的发光器件EM。
例如，如图2所示，发光器件EM包括第一电极141、发光材料层142以及第二电极143。例如，第一电极141作为阳极，与薄膜晶体管TFT的源漏电极123电连接。发光材料层142包括有机发光材料，配置为发出单色光或者白光。第二电极143作为阴极，例如形成为面电极，也即，多个子像素的第二电极143连续设置为面状，以整体覆盖衬底基板110；或者，在一些实施例中，在显示基板需要提高透光率的位置，第二电极143可以具有与第一电极141正对的图案，也即第二电极143图案化，以提高显示基板在该位置的透光率。
隔垫物层140设置在像素界定层PDL的远离衬底基板110的一侧，包括多个隔垫物PS，多个隔垫物PS的透光率小于5％，例如小于2％。多个隔垫物PS可以在显示基板的制备过程中支撑例如掩模板等装置。
例如，在一些实施例中，多个隔垫物PS可以采用黑色不透光材料形成，例如在树脂材料中掺杂黑色染料形成的黑色不透光材料，该材料对光有很好 的吸收效果，因此在外界环境光照射在隔垫物PS上，外界环境光不会被反射而是被吸收，因此可以减弱色分离现象甚至消除色分离现象。
例如，在一些实施例中，像素界定层PDL在除多个子像素开口130以外的部分的透光率小于5％，例如小于2％。例如，像素界定层PDL的材料可以与多个隔垫物PS的材料相同，由此在制备工艺中可以采用半色调掩模板在相同的构图工艺中形成，或者，二者也可以采用相同或者不同的材料分别形成。
由此，当有外界环境光照射在像素界定层PDL上，外界环境光也不会被像素界定层PDL反射，因此可以进一步减弱色分离现象甚至消除色分离现象。
例如，图4示出了本公开实施例提供的显示面板的色分离实测结果图，如图4所示，从深色到浅色所展现的颜色分离现象相比于图1B有很大程度的减弱，甚至不容易被肉眼发现，由此可以极大的提高显示面板的显示效果。例如，相对于CIE1976Lab坐标系，色分离效果可实现lab＜4的效果(
Figure PCTCN2022096141-appb-000001
a轴代表红绿相对色，+a代表红色，-a代表绿色，b轴代表黄蓝相对色，+b代表黄色，-b代表蓝色)，从而可以较大改善户外阳光下显示基板的使用效果。
例如，在一些实施例中，多个隔垫物PS与多个子像素开口130的最小距离为L，且1微米＜L＜8微米，例如，L为2微米、4微米、6微米或者8微米等。由此，多个隔垫物PS与多个子像素开口130相隔一定的距离，由于子像素开口130的侧壁通常具有一定的倾斜角度，若多个隔垫物PS与多个子像素开口130的距离过近，隔垫物PS可能形成在子像素开口130的侧壁上，从而降低了隔垫物PS相对于衬底基板110的高度，难以实现充分的隔垫作用。
例如，在一些实施例中，如图3所示，多个隔垫物PS中至少部分隔垫物PS的平面形状为矩形。例如，矩形的长L1和宽W1的尺寸范围为13微米-19微米，例如，长L1可以为15微米、17微米或者19微米等，宽W1可以为13微米、15微米或者17微米等，在一些实施例中，至少部分隔垫物PS的平面形状也可以为正方形，此时，正方形的边长可以为12微米、15微米、17微米或者19微米等。
例如，在另一些实施例中，多个隔垫物PS中至少部分隔垫物PS的平面 形状也可以为圆形，此时，圆形的直径可以为13微米-19微米，例如15微米或者17微米等；或者，在再一些实施例中，多个隔垫物PS可以包括主隔垫物和副隔垫物，主隔垫物和副隔垫物的平面形状均可以为圆形，此时，主隔垫物和副隔垫物的圆形的直径之和可以为13微米-19微米，例如15微米或者17微米等。
例如，如图1所示，在垂直于衬底基板110的方向上，也即图中的竖直方向上，多个隔垫物PS的高度H为0.5微米-2.0微米，例如1.0微米或者1.5微米等，以充分实现隔垫作用。
例如，如图2所示，显示基板还包括设置在发光器件EM的远离衬底基板110一侧的黑矩阵层BM，黑矩阵层BM包括多个第一透光开口BM1，图5示出了第一透光开口BM1的平面排布示意图，如图5所示，多个子像素开口130在衬底基板110上的正投影分别位于多个第一透光开口BM1在衬底基板110上的正投影内部。例如，多个子像素开口130在衬底基板110上的正投影的边界分别与多个第一透光开口BM1在衬底基板110上的正投影的边界的距离L2为1.0微米-6.5微米，例如3微米-6微米，例如3.5微米、4微米、4.5微米、5微米或者5.5微米等。也即，第一透光开口BM1相对于对应的子像素开口130外扩1.0微米-6.5微米，以使发光器件EM发出的光可以充分通过第一透光开口BM1出射。
例如，在一些实施例中，如图2所示，显示基板还包括多个彩色滤光片CF，多个彩色滤光片CF分别至少部分设置在多个第一透光开口BM1中；对于一个第一透光开口BM1以及至少部分设置在该一个第一透光开口BM1中的一个彩色滤光片CF，该一个第一透光开口BM1在衬底基板110上的正投影位于该一个彩色滤光片CF在衬底基板110上的正投影内部，也即，彩色滤光片CF的设置范围大于第一透光开口BM1的设置范围。
例如，在一些实施例中，多个子像素包括第一子像素R、第二子像素G和第三子像素B，多个彩色滤光片CF包括用于第一子像素R的第一颜色滤光片RCF、用于第二子像素G的第二颜色滤光片GCF和用于第三子像素B第三颜色滤光片BCF。
例如，在一些实施例中，第一子像素为红色子像素，第二子像素为绿色子像素，第三子像素为蓝色子像素；相应地，第一颜色滤光片RCF为红色滤光片，第二颜色滤光片GCF为绿色滤光片，第三颜色滤光片BCF为蓝色 滤光片。
或者，在另一些实施例中，第一子像素R也可以为绿色子像素或者蓝色子像素，第二子像素G也可以为红色子像素或者蓝色子像素，第三子像素B也可以为红色子像素或者绿色子像素。此时，各个子像素上设置相应颜色的彩色滤光片。
例如，在另一些实施例中，显示基板还可以包括设置在黑矩阵层BM的远离衬底基板一侧的彩色滤光层，彩色滤光层具有网格状结构。例如，彩色滤光层包括第一颜色滤光层(例如红色滤光层)、第二颜色滤光层(例如绿色滤光层)以及第三颜色滤光层(例如蓝色滤光层)中至少之一。此时，第一颜色滤光层在第二子像素G以及第三子像素B对应的第二透光开口BM2处镂空，例如在镂空处填充第一颜色滤光片RCF；第二颜色滤光层在第一子像素R以及第三子像素B对应的第二透光开口BM2处镂空，例如在镂空处填充第二颜色滤光片GCF；第三颜色滤光层在第一子像素R以及第二子像素G对应的第二透光开口BM2处镂空，例如在镂空处填充第三颜色滤光片BCF。由此可以进一步降低光在显示基板中的反射率。
例如，图5示出了多个第一颜色滤光片RCF的平面排布示意图。如图15所示，第一颜色滤光片RCF的设置范围大于第一子像素R对应的第一透光开口BM1的设置范围。例如，图6示出了第一透光开口BM1、第一颜色滤光片RCF以及子像素开口130的部分截面示意图，如图5和图6所示，第一透光开口BM1的设置范围大于子像素开口130的设置范围，第一颜色滤光片RCF的设置范围大于第一透光开口BM1的设置范围，且子像素开口130在衬底基板110上的正投影的边界与第一透光开口BM1在衬底基板110上的正投影的边界的距离L2为1.0微米-6.5微米，例如3微米-6微米。
例如，如图6所示，隔垫物PS的设置宽度可以小于黑矩阵层BM的非透光区域的设置宽度，在其他实施例中，隔垫物PS的设置宽度也可以大于黑矩阵层BM的非透光区域的设置宽度，此时，即使有光照射到隔垫物PS，隔垫物PS也不会反射光而造成色分离现象，由此可以提高黑矩阵层BM的设计自由度。
例如，图7示出了在图5的基础上设置了第二颜色滤光片GCF的情形，图8示出了在图7的基础上设置了第三颜色滤光片BCF的情形。如图7和图8所示，在第二子像素和第三子像素中，也均是第一透光开口BM1的设 置范围大于子像素开口130的设置范围，第二颜色滤光片GCF/第三颜色滤光片BCF的设置范围大于第一透光开口BM1的设置范围，且子像素开口130在衬底基板110上的正投影的边界与第一透光开口BM1在衬底基板110上的正投影的边界的距离L2为1.0微米-6.5微米，例如3微米-6微米。
例如，在一些实施例中，如图5、图7和图8所示，黑矩阵层BM还包括多个第二透光开口BM2，多个第二透光开口BM2分别设置在多个第一透光开口BM1中相邻的两个第一透光开口BM1之间。多个第二透光开口BM2可以透过例如用于指纹识别的信号光或者摄像头、距离传感器、红外传感器等器件所需的信号光等。
例如，在一些实施例中，如图9所示，显示基板还包括设置在衬底基板110上的遮光层S，像素驱动电路层120设置在遮光层S的远离衬底基板110的一侧。遮光层S包括多个第三透光开口S1，多个第三透光开口S1中的至少部分在衬底基板110上的正投影分别与多个第二透光开口BM2在衬底基板110上的正投影至少部分交叠。
由此，第三透光开口S1与第二透光开口BM2形成套孔，以透过例如用于指纹识别的信号光，此时，衬底基板110的远离发光器件EM的一侧可以设置图像传感器，该图像可以接收通过第二透光开口BM2和第三透光开口S1的信号光来进行纹路采集与识别功能。
例如，在一些实施例中，遮光层110的材料可以为铜、铝等金属材料或者合金材料；或者，遮光层110也可以为采用树脂材料中掺杂黑色染料形成的黑色不透光层。
本公开的实施例中，遮光层S可以在第一透光开口S1处透过用于指纹识别的信号光，并且在其他位置遮挡显示基板的发光器件EM发出的光以及环境光等非信号光，以避免非信号光照射到设置在显示基板非显示侧的图像传感器，由此可以提升图像传感器的识别速度和准确性。
例如，在一些实施例中，像素驱动电路层包括多个金属层，例如上述栅极122、第一极123、第二极124等所在的金属层，这些金属层构成的电路图案在衬底基板110上的正投影与多个第一透光开口S1在衬底基板110上的正投影不交叠，也与第三透光开口BM2在衬底基板110上的正投影不交叠，以避免电路图案影响信号光的传输。
例如，图10示出了一个第三透光开口S1与对应的第二透光开口BM2 在衬底基板110上的正投影的示意图，如图10所示，多个第三透光开口S1在衬底基板110上的正投影分别位于多个第二透光开口BM2在衬底基板110上的正投影内。
例如，如图10所示，在一些实施例中，多个第三透光开口S1中的至少部分在衬底基板110上的正投影的边界分别与多个第二透光开口BM2在衬底基板110上的正投影的边界的距离L3为0.5微米-1.5微米，例如0.8微米、1.0微米、1.2微米或者1.5微米等，从而信号光可以充分通过第二透光开口BM2和第三透光开口S1达到图像传感器。
例如，在一些实施例中，如图7所示，多个第二透光开口BM2中的至少部分位于相邻的第一子像素R和第三子像素B对应的第一透光开口BM1之间，且与第一子像素R对应的第一透光开口BM1的距离不同于与第三子像素B对应的第一透光开口BM1的距离，例如与第三子像素B对应的第一透光开口BM1的距离更近。
例如，在一些实施例中，如图7所示，第一子像素R和第三子像素B排列为多行多列，位于同一列的多个第一子像素R和多个第三子像素B交替排列，且位于同一列的相邻的第一子像素R和第三子像素B对应的第一透光开口BM1之间设置一个第二透光开口BM2。
例如，在一些实施例中，如图7所示，一个第一子像素R、两个第二子像素G和一个第三子像素B组成一个重复单元，多个重复单元阵列排布，多个重复单元中的多个第二子像素G排列为多行多列，第二透光开口BM2还设置在行方向上相邻的第二子像素R对应的第一透光开口BM1之间。
通过上述排布，第二透光开口BM2和第三透光开口S1的设置不会影响显示基板上原有的电路设置，并且原有的电路设置也不会影响信号光依次通过第二透光开口BM2和第三透光开口S1达到图像传感器。
例如，参考图5，多个隔垫物PS的每个在衬底基板110上的正投影分别位于在列方向上相邻的第二子像素G的子像素开口130在衬底基板110上的正投影之间，且分别位于在行方向上相邻的第一子像素R和第三子像素B的子像素开口130在衬底基板110上的正投影之间。
例如，参考图3，多个隔垫物PS的每个在衬底基板110上的正投影与相邻的第一子像素R和第三子像素B中的第一子像素R的子像素开口130在衬底基板110上的正投影的最短距离L11大于与相邻的第一子像素R和第 三子像素B中的第三子像素B的子像素开口130在衬底基板110上的正投影的最短距离L12，也即相邻的第一子像素R和第三子像素B之间设置的隔垫物PS相比于第一子像素R的子像素开口130，更靠近第三子像素B的子像素开口130。
例如，在一些实施例中，参考图3，多个隔垫物PS的每个在衬底基板110上的正投影与相邻的第二子像素G的子像素开口130在衬底基板110上的正投影的最短距离L13基本相同，也即相邻的第二子像素G之间设置的隔垫物PS与该相邻的第二子像素G的子像素开口130的距离基本相同。
由此，多个隔垫物PS与第三透光开口S1在显示基板中周期排布，互不影响。
例如，在一些实施例中，如图8所示，一个第一子像素R、两个第二子像素G和一个第三子像素B组成一个重复单元，每个重复单元对应设置两个第三透光开口S1。例如，每个第三透光开口S1对应设置一个第二透光开口BM2，或者，在一些实施例中，每两个或者更多个第三透光开口S1中的一个第三透光开口S1对应设置一个第二透光开口BM2，也即每两个或者更多个第三透光开口S1中的一个第三透光开口S1对应与一个第二透光开口BM2以形成套孔，而其他第三透光开口S1被黑矩阵层BM遮挡，不用于形成套孔。
例如，在一些实施例中，如图8所示，每个重复单元对应设置一个隔垫物PS，或者，在其他实施例中，也可以两个或更多个重复单元对应设置一个隔垫物PS，本公开的实施例对此不做限定。
例如，在一些实施例中，如图2和图9所示，显示基板还包括设置在发光器件EM的远离衬底基板110一侧的封装层EN，黑矩阵层BM设置在封装层EN的远离衬底基板110的一侧。例如，封装层EN可以为复合封装层，包括依次设置在发光器件EM上的第一无机封装层、第一有机封装层和第二无机封装层(图中未示出)，以提高封装效果。
例如，在一些实施例中，用于多个子像素的彩色滤光片可以设置在复合封装层中，例如复合封装层中相邻的两个子封装层之间。例如，在一个示例中，复合封装层包括依次设置在发光器件EM上的第一无机封装层、第一有机封装层、第二无机封装层和第三无机封装层，此时，彩色滤光片可以设置在第二无机封装层和第三无机封装层之间。
例如，在一些实施例中，如图9所示，显示基板还包括设置在封装层EN的远离衬底基板110的一侧的触控层FM，黑矩阵层BM设置在触控层FM的远离衬底基板110的一侧。
例如，图11示出了触控层FM的平面示意图，如图9和图11所示，触控层FM包括多条触控走线TL，多条触控走线TL在衬底基板110上的正投影与多个第二透光开口BM2在衬底基板110上的正投影不交叠。例如，多条触控走线TL在衬底基板110上的正投影与多个第一透光开口BM1在衬底基板110上的正投影也不交叠。由此，多条触控走线TL被黑矩阵层BM遮挡，以避免光照射到触控走线TL而影响触控走线TL的信号传输性能等。
例如，在一些实施例中，如图11所示，在平行于衬底基板110的同一方向上，多条触控走线TL与第一颜色滤光片RCF、第二颜色滤光片GCF和第三颜色滤光片BCF中至少两个的距离不同。例如，在虚线框位置处，在图11中的水平方向上，触控走线TL与第三颜色滤光片BCF的距离大于与第一颜色滤光片RCF的距离。由于第三颜色滤光片BCF的形状、排布不规则，因此在该方向上将触控走线TL与第三颜色滤光片BCF的距离设置的较大，可以避免触控走线TL与第三颜色滤光片BCF在该方向上交叠，或者交叠尺寸过大。
例如，在一些实施例中，如图11所示，第一子像素R和第三子像素B排列为多行多列，位于同一列的多个第一子像素R和多个第三子像素B交替排列，例如，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有缺口NT1/NT2/NT3。
例如，如图11所示，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧或者靠近第一子像素R的一侧具有缺口NT1，此时，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有一个缺口；或者，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧以及靠近第一子像素R的一侧均具有缺口NT2/NT3，此时，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有两个缺口。
例如，在一些实施例中，如图11所示，多条触控走线TL中的至少部分在位于第N列的相邻的第一子像素R和第三子像素B中靠近第三子像素B 的一侧或者靠近第一子像素R的一侧均具有缺口NT1，并且多条触控走线TL中的至少部分在位于第N+1列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧以及靠近第一子像素R的一侧均具有缺口NT2/NT3。此时，每相邻的两列第一子像素R和第三子像素B中，其中的一列中相邻的第一子像素R和第三子像素B之间具有一个缺口，另一列中相邻的第一子像素R和第三子像素B之间具有两个缺口。
例如，显示基板还可以包括盖板等其他结构，具体可以参考相关技术，这里不再赘述。
例如，在本公开的各个实施例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C结构。例如，图12为一种8T1C像素驱动电路的等效电路示意图。如图12所示，该像素驱动电路可以包括8个晶体管(第一晶体管T1到第八晶体管T8)、1个存储电容C和多个信号线(例如数据信号线Data、第一扫描信号线Gate、第二扫描信号线GateN、复位控制信号线Reset、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD、第二电源线VSS和发光控制信号线EM等)。
例如，第一晶体管T1的栅极与复位控制信号线Reset连接，第一晶体管T1的第一极与第二初始信号线INIT2连接，第一晶体管T1的第二极与第五节点N5连接。第二晶体管T2的栅极与第一扫描信号线Gate连接，第二晶体管T2的第一极与第五节点N5连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的栅极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅极与第一扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的栅极与发光控制信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅极与发光控制信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4(即发光器件的第一极)连接。第七晶体管T7的栅极与第一扫描信号线Gate或者复位控制信号线Reset连接，第七晶体管T7的第一极与第一初始信号线INIT1连接，第七晶体管T7的第二极与第四节点N4连接。第八晶体管T8的栅极与第二扫描信号线GateN连接，第八晶体管T8的第一极与第五节点N5连接，第 八晶体管T8的第二极与第一节点N1连接。存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些实施例中，第一晶体管T1到第七晶体管T7可以是N型薄膜晶体管，第八晶体管T8可以是P型薄膜晶体管；或者，第一晶体管T1到第七晶体管T7可以是P型薄膜晶体管，第八晶体管T8可以是N型薄膜晶体管。
在一些实施例中，第一晶体管T1到第七晶体管T7可以是低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)，第八晶体管T8可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管。
在上述实施例中，铟镓锌氧化物薄膜晶体管与低温多晶硅薄膜晶体管相比，产生的漏电流更少，因此，将第八晶体管T8设置为铟镓锌氧化物薄膜晶体管，可以显著减少漏电流的产生，从而改善显示面板的低频、低亮度闪烁的问题。此外，第一晶体管T1和第二晶体管T2无需设置为铟镓锌氧化物薄膜晶体管，由于低温多晶硅薄膜晶体管的尺寸一般都要小于铟镓锌氧化物薄膜晶体管，因此，本公开实施例的像素驱动电路的占用空间会比较小，利于提高显示面板的分辨率。
本公开实施例提供的上述像素驱动电路，集合了LTPS-TFT的良好开关特性和Oxide-TFT的低漏电特性，可以实现低频驱动(1Hz～60Hz)，大幅降低显示屏功耗。
在一些实施例中，发光器件的第二电极与第二电源线VSS连接，第二电源线VSS的信号为持续提供低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线Gate的信号为本显示行像素驱动电路中的扫描信号，复位控制信号线Reset的信号为上一显示行像素驱动电路中的扫描信号，即对于第n显示行，第一扫描信号线Gate为Gate(n)，复位控制信号线Reset为Gate(n-1)，本显示行的复位控制信号线Reset的信号与上一显示行像素驱动电路中的第一扫描信号线Gate的信号可以为同一信号，以减少显示面板的信号线，实现显示面板的窄边框。
在一些实施例中，第一扫描信号线Gate、第二扫描信号线GateN、复位控制信号线Reset、发光控制信号线EM、第一初始信号线INIT1和第二初始信号线INIT2均沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线DATA均沿竖直方向延伸。
在一些实施例中，第一初始信号线INIT1，第二初始信号线INIT2，第二电源线VSS、第一电源线VDD的至少部分可以为网状结构，即同时包含水平方向延伸和竖直方向延伸的部分。
图13为一种像素驱动电路的工作时序图。下面通过图12示例的像素驱动电路的工作过程说明本公开示例性实施例，图12中的像素驱动电路包括8个晶体管(第一晶体管T1到第八晶体管T8)和1个存储电容C，本实施例以第一晶体管T1到第七晶体管T7为P型晶体管，第八晶体管T8为N型晶体管，第七晶体管T7的栅极连接第一扫描信号线Gate为例进行说明。
例如，在一些实施例中，像素驱动电路的工作过程可以如下几个阶段。
第一阶段t1，称为复位阶段，第一扫描信号线Gate、复位控制信号线Reset、第二扫描信号线GateN和发光控制信号线EM的信号均为高电平信号，复位控制信号线Reset的信号为低电平信号。发光控制信号线EM的高电平信号使得第五晶体管T5和第六晶体管T6关闭，第二扫描信号线GateN的高电平信号使得第八晶体管T8导通，复位控制信号线Reset的低电平信号使得第一晶体管T1导通，因此，第一节点N1的电压被复位为第二初始信号线INIT2提供的第二初始电压Vinit2，然后复位控制信号线Reset的电位置高，第一晶体管T1关闭。由于第五晶体管T5和第六晶体管T6关闭，此阶段发光器件EL不发光。
第二阶段t2，称为数据写入阶段，第一扫描信号线Gate的信号为低电平信号，第四晶体管T4、第二晶体管T2和第七晶体管T7导通，数据信号线Data输出数据电压，第四节点N4的电压被复位为第一初始电压线INIT1提供的第一初始电压Vinit1，完成初始化。此阶段由于第一节点N1为低电平，因此第三晶体管T3导通。第四晶体管T4和第二晶体管T2导通使得数据信号线Data输出的数据电压经过导通的第四晶体管T4、第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2、第五节点N5和第八晶体管T8提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管T3的阈值电压之和充入存储电容C，存储电容C的第二端(第一节点N1)的电压为Vdata+Vth，Vdata为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。发光控制信号线EM的信号为高电平信号，第五晶体管T5和第六晶体管T6关闭，确保发光器件EL不发光。
第三阶段t3，称为发光阶段，第一扫描信号线Gate和复位控制信号线 Reset的信号为高电平信号，发光控制信号线EM和第二扫描信号线GateN的信号均为低电平信号。复位控制信号线Reset的高电平信号，使第七晶体管T7关闭，发光控制信号线EM的低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL的第一极(即第四节点N4)提供驱动电压，驱动发光器件EL发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(即第三晶体管)的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata+Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdata+Vth-Vdd)-Vth] 2＝K*[(Vdata-Vdd)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线Data输出的数据电压，Vdd为第一电源端VDD输出的电源电压。
由上述公式可以看出，流经发光器件EL的电流I与第三晶体管T3的阈值电压Vth无关，消除了第三晶体管T3的阈值电压Vth对电流I的影响，保证了亮度的均一性。
基于上述工作时序，该像素驱动电路消除了发光器件EL在上次发光后残余的正电荷，实现了对第三晶体管栅极电压的补偿，避免了第三晶体管的阈值电压漂移对发光器件EL驱动电流的影响，提高了显示图像的均匀性和显示面板的显示品质。
本公开实施例的像素驱动电路，通过将第四节点N4初始化为第一初始信号线INIT1的信号，通过将第五节点N5初始化为第二初始信号线INIT2的信号，能够对发光器件EL的复位电压和第一节点N1的复位电压分别进行调整，从而实现更佳的显示效果，改善低频闪烁等问题。
例如，图14-图25示出了本公开至少一实施例提供的显示基板的各个层依次叠层的平面示意图。
例如，图14示出了遮光层的平面示意图，遮光层包括多个第一透光开口(第三开口)S1。
图15示出了第一半导体层叠层在遮光层后的平面示意图，第一半导体层包括多个薄膜晶体管的有源层。第一半导体层可以采用硅材料，硅材料包 括非晶硅和多晶硅；在一些实施例中，第一半导体层可以采用非晶硅a-Si，经过结晶化或激光退火等方式形成多晶硅。
图15中虚线框示出的范围为一个子像素的像素驱动电路的设置范围。如图15所示，第一半导体层可以包括第一晶体管T1的第一有源层10、第二晶体管T2的第二有源层20、第三晶体管T3的第三有源层30、第四晶体管T4的第四有源层40、第五晶体管T5的第五有源层50、第六晶体管T6的第六有源层60和第七晶体管T7的第七有源层70。第一有源层10、第二有源层20、第三有源层30、第四有源层40、第五有源层50、第六有源层60和第七有源层70为相互连接的一体结构。
在一些实施例中，第三有源层30的形状可以呈“几”字形，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的形状可以呈“1”字形。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第一半导体层为镜像对称结构。
在一些实施例中，第三有源层30的沟道区沿行方向延伸，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的沟道区沿列方向延伸。
例如，第三透光开口S1在衬底基板110上的正投影与第六有源层60和第七有源层70在衬底基板110上的正投影相邻，相应地，第二透光开口BM2在衬底基板110上的正投影与第六有源层60和第七有源层70在衬底基板110上的正投影相邻。
在一些实施例中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管可以均为LTPS薄膜晶体管。
例如，图16示出了第一导电层叠层在第一半导体层后的平面示意图。在一些实施例中，如图16所示，第一导电层可以包括：第一扫描信号线Gate_P、复位控制信号线Reset_P、发光控制信号线EM_P和储存电容C的第一极板Ce1。在一些实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第一导电层为镜像对称结构。
在一些实施例中，第一扫描信号线Gate_P、复位控制信号线Reset_P和发光控制信号线EM_P均沿第一方向X延伸。在每个子像素内，复位控制信号线Reset_P位于第一扫描信号线Gate_P远离发光控制信号线EM_P的一侧，存储电容的第一极板Ce1设置在第一扫描信号线Gate_P和发光控制信号线EM_P之间。
例如，像素驱动电路层(例如上述第一导电层)包括相互平行设置且周期排布的第一信号线(例如在一些实施例中为发光控制信号线EM_P)和第二信号线(例如在一些实施例中为复位控制线Reset_P)，第一信号线和第二信号线配置为向多个子像素提供不同的电信号，多个第三透光开口S1在衬底基板110上的正投影分别位于一条第一信号线(例如为发光控制信号线EM_P)在衬底基板110上的正投影和与该一条第一信号线距离最近的一条第二信号线(例如为复位控制线Reset_P)在衬底基板110上的正投影之间。相应地，多个第二透光开口BM2在衬底基板110上的正投影分别位于一条第一信号线(例如为发光控制信号线EM_P)在衬底基板110上的正投影和与该一条第一信号线距离最近的一条第二信号线(例如为复位控制线Reset_P)在衬底基板110上的正投影之间。
例如，多个子像素包括第一行子像素RO1和与第一行子像素RO1相邻且位于第一行子像素RO1下级的第二行子像素RO2，第一行子像素RO1的像素驱动电路共用一条发光控制信号线EM_P和一条复位控制线Reset_P，第二行子像素RO2的像素驱动电路共用一条发光控制信号线EM_P和一条复位控制线Reset_P，其中，第一行子像素RO1的像素驱动电路共用的发光控制信号线EM_P在衬底基板110上的正投影和第二行子像素RO2的像素驱动电路共用的复位控制线Reset_P在衬底基板110上的正投影之间包括一行第三透光开口S1在衬底基板110上的正投影。相应地，第一行子像素RO1的像素驱动电路共用的发光控制信号线EM_P在衬底基板110上的正投影和第二行子像素RO1的像素驱动电路共用的复位控制线Reset_P在衬底基板110上的正投影之间包括一行第二透光开口BM2在衬底基板110上的正投影。
在一些实施例中，第一极板Ce1可以为矩形状，矩形状的角部可以设置倒角，第一极板Ce1在衬底基板110上的正投影与第三晶体管T3的第三有源层30在衬底基板110上的正投影存在重叠区域。在一些实施例中，第一 极板Ce1同时作为第三晶体管T3的栅极。
在一些实施例中，复位控制信号线Reset_P与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1的栅极，第一扫描信号线Gate_P与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2的栅极，第一扫描信号线Gate_P与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅极，发光控制信号线EM_P与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅极，发光控制信号线EM_P与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅极。每行子像素的下一行子像素中的复位控制信号线Reset_P(与本行子像素中的第一扫描信号线Gate_P的信号相同)与本行子像素中的第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅极。
例如，图17示出了第二导电层叠层在第一导电层后的平面示意图。如图17所示，第二导电层包括：存储电容C的第二极板Ce2和第二扫描信号线GateN的第一分支GateN_B1。在一些实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第二导电层为镜像对称结构。
在一些实施例中，第二扫描信号线GateN的第一分支GateN_B1沿第一方向X延伸。在每个子像素内，存储电容的第二极板Ce2位于第二扫描信号线GateN的第一分支GateN_B1和发光控制信号线EM_P之间。
在一些实施例中，第二极板Ce2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板Ce2在衬底基板110上的正投影与第一极板Ce1在衬底基板110上的正投影存在重叠区域。第二极板Ce2上设置有开口H，开口H可以位于第二极板Ce2的中部。开口H可以为正六边形，使第二极板Ce2形成环形结构。开口H暴露出覆盖第一极板Ce1的第三绝缘层，且第一极板Ce1在衬底基板110上的正投影包含开口H在衬底基板110上的正投影。在一些实施例中，开口H配置为容置后续形成的第四过孔，第四过孔位于开口H内并暴露出第一极板Ce1，使后续形成的第八晶体管T8的第二极与第一极板Ce1连接。
例如，图18示出了第二半导体层叠层在第二导电层后的平面示意图。在一些实施例中，如图18所示，每个子像素的第二半导体层可以包括第八 晶体管T8的第八有源层80。在一些实施例中，第八有源层80沿第二方向Y延伸，第八有源层80的形状可以呈哑铃形。
在第二方向Y上，任意相邻两列子像素的第二半导体层为镜像对称结构。
在一些实施例中，第二半导体层可以采用氧化物，即第八晶体管为氧化物薄膜晶体管。
例如，图19示出了第三导电层叠层在第二导电层后的平面示意图。如图19所示，第三导电层包括：第二扫描信号线GateN的第二分支GateN_B2和第二初始信号线INIT2。在一些实施例中，第三导电层可以称为第三栅金属(GATE3)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第三导电层为镜像对称结构。
在一些实施例中，第二扫描信号线GateN的第二分支GateN_B2沿第一方向X延伸，第二扫描信号线GateN的第二分支GateN_B2与第一扫描信号线Gate的第二分支Gate_B2靠近。在一些实施例中，第二扫描信号线GateN的第二分支GateN_B2与第八有源层80重叠的区域作为第八晶体管的栅极。
在一些实施例中，第二扫描信号线的第二分支GateN_B2在衬底基板110上的正投影与第二扫描信号线的第一分支GateN_B1在衬底基板110上的正投影交叠。在一些实施例中，第二扫描信号线的第一分支GateN_B1与第二扫描信号线的第二分支GateN_B2可以在周边区域通过信号线连接。
在一些实施例中，第二初始信号线INIT2沿第一方向X延伸，在每行子像素内，第二初始信号线INIT2设置在复位控制信号线Reset_P远离第一扫描信号线Gate_P的一侧。
例如，第三透光开口S1在衬底基板110上的正投影还位于发光控制信号线EM_P以及与该发光控制信号线EM_P最近邻的一条第二初始信号线INIT2在衬底基板110上的正投影之间。相应地，第二透光开口BM2在衬底基板110上的正投影还还位于在发光控制信号线EM_P以及与该发光控制信号线EM_P最近邻的一条第二初始信号线INIT2在衬底基板110上的正投影之间。
例如，图20示出了第三导电层上形成的绝缘层中的多个过孔的平面分布图。如图20所示，该绝缘层中设置有多个过孔，多个过孔包括：第一过 孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
例如，第一过孔V1暴露出第八有源层80的第二区的表面。第二过孔暴露出第八有源层80的第一区的表面。第三过孔V3暴露出第二有源层的第一区的表面。第三过孔V3配置为使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
第四过孔V4位于第二极板Ce2的开口H内，第四过孔V4在衬底基板110上的正投影位于开口H在衬底基板110上的正投影的范围之内，第四过孔V4暴露出第一极板Ce1的表面。第四过孔V4配置为使后续形成的第三连接电极43与通过该过孔与第一极板Ce1连接。
第五过孔V5暴露出第五有源层的第一区的表面。第五过孔V5配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层连接。
第六过孔V6位于第二极板Ce2所在区域，第六过孔V6在衬底基板110上的正投影位于第二极板Ce2在衬底基板110上的正投影的范围之内，第六过孔V6内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板Ce2的表面。第六过孔V6配置为使后续形成的第五连接电极45通过该过孔与第二极板Ce2连接。
第七过孔V7暴露出第一有源层的第一区的表面。第七过孔V7配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。第八过孔V8暴露出第七有源层的第一区的表面。第八过孔V8配置为使后续形成的第一初始信号线通过该过孔与第七有源层连接。第九过孔V9暴露出第六有源层的第二区的表面。第九过孔V9配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
第十过孔V10暴露出第四有源层的第一区的表面。第十过孔V10配置为使后续形成的第二连接电极42通过该过孔与第四有源层连接。第十一过孔V11暴露出第二初始信号线INIT2的表面。第十一过孔V11配置为使后续形成的第六连接电极46通过该过孔与第二初始信号线INIT2连接。
图21示出了第四导电层叠层在第三导电层后的平面示意图。如图21所示，第四导电层包括：第一初始信号线INIT1、第一连接电极41、第二连接 电极42、第三连接电极43、第四连接电极44、第五连接电极45和第六连接电极46。在一些实施例中，第四导电层可以称为第一源漏金属(SD1)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第四导电层为镜像对称结构。
在一些实施例中，第一初始信号线INIT1沿着第一方向X延伸，第一初始信号线INIT1通过第八过孔V8与第七有源层的第一区连接，使第七晶体管T7的第一极与第一初始信号线INIT1具有相同的电位。
在一些实施例中，第一连接电极41的一端通过第三过孔V3与第二有源层的第一区(也是第一有源层的第二区)连接，另一端通过第二过孔V2与第八有源层的第一区连接。在一些实施例中，第一连接电极41可以作为第八晶体管T8的第一极、第二晶体管的第一极和第一晶体管的第二极。
在一些实施例中，第二连接电极42一方面通过第十过孔V10与第四有源层的第一区连接，另一方面通过后续形成的第十三过孔V13与后续形成的数据信号线Data连接。在一些实施例中，第二连接电极42可以作为第四晶体管T4的第一极。
在一些实施例中，第三连接电极43的一端通过第一过孔V1与第八有源层的第二区连接，其另一端通过第四过孔V4与第一极板Ce1连接。在一些实施例中，第三连接电极43可以作为第八晶体管T8的第二极。
在一些实施例中，第四连接电极44一方面通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)，另一方面，通过后续形成的第十二过孔V12与后续形成的第一电极连接电极连接。在一些实施例中，第四连接电极44可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极。
在一些实施例中，第五连接电极45(电源连接电极)，一方面通过第六过孔V6与第二极板Ce2连接，另一方面通过第五过孔V5与第五有源层的第一区连接，第五连接电极45配置为通过后续形成的第十四过孔V14与后续形成的第一电源线VDD连接。
在一些实施例中，第六连接电极46的一端通过第七过孔V7与第一有源层的第一区连接，另一端通过第十一过孔V11与第二初始信号线连接，使第一晶体管T1的第一极与第二初始信号线INIT2具有相同的电位。
图22示出了第一平坦化层叠层在第四导电层以及第五导电层叠层在第 一平坦化层后的平面示意图。在一些实施例中，如图22所示，第一平坦化层97包括：第十二过孔V12、第十三过孔V13和第十四过孔V14，第五导电层包括：数据信号线Data、第一电源线VDD和第一电极连接电极51。在一些实施例中，第五导电层可以称为第二源漏金属(SD2)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第五导电层为镜像对称结构。在另一些示例性实施方式中，在第二方向Y上，任意相邻两列子像素的第五导电层也可以不为镜像对称结构，可以根据需要增加第二开口或第三开口下方的第二源漏金属层的面积，以增加上层形成的第一电极(阳极)的平坦度，使得子像素整体位于一个平面上，从而可以降低色偏，提高显示质量。
在一些实施例中，如图22所示，在一个重复单元内，相邻两列子像素中的第一电源线VDD可以为相互连接的一体结构。通过使相邻两列子像素中的第一电源线VDD形成相互连接的一体结构，可以使上层形成的阳极更加平坦。
例如，驱动电路层包括相互平行设置且周期排布的第三信号线(例如上述第一电源线VDD)，第三信号线沿第二方向Y延伸，分别与第一信号线和第二信号线相交，第三信号线配置为向多个子像素提供电源信号，如图18所示，第三信号线包括镂空部OD，第三透光开口S1在衬底基板110上的正投影位于镂空部OD在衬底基板110上的正投影内。相应地，第二透光开口BM2在衬底基板110上的正投影位于镂空部OD1在衬底基板110上的正投影内。
在一些实施例中，第一电极连接电极51可以为矩形状，第一电极连接电极51通过第十二过孔V12与第四连接电极44连接。
在一些实施例中，第一电源线VDD通过第十四过孔V14与第五连接电极45连接。
在一些实施例中，数据信号线Data沿着第二方向Y延伸，数据信号线Data通过第十三过孔V13与第二连接电极42连接，由于第二连接电极42通过第十过孔V10与第四有源层的第一区连接，因而实现了数据信号线与第四晶体管的第一极的连接，使数据信号线Data传输的数据信号可以写入第四晶体管。
例如，图23示出了第二平坦化层叠层在第五导电层后的平面示意图。 在一些实施例中，如图23所示，第二平坦层98包括第十五过孔V15。
在一些实施例中，第十五过孔V15位于第一电极连接电极51所在区域，第十五过孔V15内的第二平坦层被去掉，暴露出第一电极连接电极51的表面，第十五过孔V15配置为使后续形成的第一电极(例如阳极)通过该过孔与第一电极连接电极51连接。
例如，为清楚示出，图24示出了第一电极层的平面示意图。如图24所示，第一电极层包括多个子像素的第一电极141，每个第一电极141包括主体部141A和连接部141B，主体部141A被子像素开口130暴露，连接部141B通分别过第十五过孔V15与第一电极连接电极51。
由于第一电极连接电极51通过第十二过孔V12与第四连接电极44连接，第四连接电极44还通过第九过孔V9与第六有源层连接，因而实现了像素驱动电路可以驱动发光器件发光。
例如，图25示出了像素界定层PDL的平面示意图，如图25所示，像素界定层PDL包括多个子像素开口130，多个子像素开口130的形状与第一电极141的主体部141A的形状基板相同，且尺寸略小于主体部141A的尺寸，以充分暴露主体部141A。
例如，像素界定层PDL上方的隔垫物层140、触控层FM、黑矩阵层BM以及彩色滤光片的结构以及位置关系可以参见图3、图5、图7-图9以及图11等，这里不再赘述。
例如，在一些实施例中，参考图23，像素驱动电路层多个像素驱动电路以及为多个像素驱动电路提供扫描信号的多条扫描信号线Gate(例如以Gate_P作为示例)以及为多个像素驱动电路提供复位控制信号的多条复位控制信号线Reset(例如以Reset_P作为示例)，在平行于衬底基板的方向上，多个隔垫物PS中的至少部分分别位于一条复位控制信号线Reset(例如Reset_P)以及与该一条复位控制信号线Reset最近的一条扫描信号线Gate(例如Gate_P)之间；例如，上述复位控制信号线Reset以及与上述复位控制信号线Reset最近的扫描信号线Gate用于为同一行像素驱动电路提供电信号。
或者，在另一些实施例中，由于隔垫物PS的尺寸较大或者对位差异等，在垂直于衬底基板的方向上，多个隔垫物PS中的至少部分分别与一条复位控制信号线Reset(例如Reset_P)以及与该一条复位控制信号线最近的一条 扫描信号线Gate(例如Gate_P)中的至少一个交叠，例如图中示出为与扫描信号线Gate(例如Gate_P)交叠，在其他实施例中也可以与复位控制信号线Reset(例如Reset_P)交叠，或者与上述二者同时交叠。此时，隔垫物PS的至少部分结构位于上述一条复位控制信号线Reset(例如Reset_P)以及与该一条复位控制信号线最近的一条扫描信号线Gate之间。
在本公开的实施例中，衬底基板110可以是柔性基板，或者可以是刚性基板。刚性基板可以为但不限于玻璃、石英中的一种或多种，柔性基板可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些实施例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
例如，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。平坦化层可以采用有机材料，触控层FM的多条走线TL可以采用氧化铟锡ITO或氧化铟锌IZO等金属氧化物材料。第一半导体层可以采用多晶硅(p-Si)，第二半导体层(SML2)可以采用氧化物。
本公开实施例提供的显示基板的叠层结构仅仅是一种示例性说明，在一些实施例中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开的实施例在此不做限定。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，具有多个子像素，且包括：
    衬底基板，
    像素驱动电路层，设置在所述衬底基板上，
    像素界定层，设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括多个子像素开口，其中，所述多个子像素中的每个包括设置在所述像素驱动电路层中的像素驱动电路以及至少部分设置在所述子像素开口中的发光器件，以及
    隔垫物层，设置在所述像素界定层的远离所述衬底基板的一侧，包括多个隔垫物，其中，所述多个隔垫物的透光率小于5％。
  2. 根据权利要求1所述的显示基板，其中，所述像素界定层在除所述多个子像素开口以外的部分的透光率小于5％。
  3. 根据权利要求1或2所述的显示基板，其中，所述隔垫物层与所述像素界定层的材料相同。
  4. 根据权利要求1-3任一所述的显示基板，其中，所述多个隔垫物与所述多个子像素开口的最小距离为L，且1微米＜L＜8微米。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述多个隔垫物中至少部分隔垫物的平面形状为矩形。
  6. 根据权利要求5所述的显示基板，其中，所述矩形的长和宽的尺寸范围为13微米-19微米，
    在垂直于所述衬底基板的方向上，所述多个隔垫物的高度为0.5微米-2.0微米。
  7. 根据权利要求1-6任一所述的显示基板，其中，所述像素驱动电路层多个像素驱动电路以及为所述多个像素驱动电路提供扫描信号的多条扫描信号线以及为所述多个像素驱动电路提供复位控制信号的多条复位控制信号线，
    在平行于所述衬底基板的方向上，所述多个隔垫物中的至少部分分别位于一条复位控制信号线以及与所述一条复位控制信号线最近的一条扫描信号线之间。
  8. 根据权利要求7所述的显示基板，其中，所述像素驱动电路层多个 像素驱动电路以及为所述多个像素驱动电路提供扫描信号的多条扫描信号线以及为所述多个像素驱动电路提供复位控制信号的多条复位控制信号线，
    在垂直于所述衬底基板的方向上，所述多个隔垫物中的至少部分分别与一条复位控制信号线以及与所述一条复位控制信号线最近的一条扫描信号线中的至少一个交叠。
  9. 根据权利要求1-8任一所述的显示基板，还包括设置在所述发光器件的远离所述衬底基板一侧的黑矩阵层，其中，所述黑矩阵层包括多个第一透光开口，
    所述多个子像素开口在所述衬底基板上的正投影分别位于所述多个第一透光开口在所述衬底基板上的正投影内部，且所述多个子像素开口在所述衬底基板上的正投影的边界分别与所述多个第一透光开口在所述衬底基板上的正投影的边界的距离为1.0微米-6.5微米。
  10. 根据权利要求9所述的显示基板，还包括多个彩色滤光片，其中，所述多个彩色滤光片分别至少部分设置在所述多个第一透光开口中；
    对于一个第一透光开口以及至少部分设置在所述一个第一透光开口中的一个彩色滤光片，所述一个第一透光开口在所述衬底基板上的正投影位于所述一个彩色滤光片在所述衬底基板上的正投影内部。
  11. 根据权利要求10所述的显示基板，其中，所述黑矩阵层还包括多个第二透光开口，所述多个第二透光开口分别设置在所述多个第一透光开口中相邻的两个第一透光开口之间。
  12. 根据权利要求11所述的显示基板，还包括设置在所述衬底基板上的遮光层，其中，所述像素驱动电路层设置在所述遮光层的远离所述衬底基板的一侧，所述遮光层包括多个第三透光开口，
    所述多个第三透光开口中的至少部分在所述衬底基板上的正投影分别与所述多个第二透光开口在所述衬底基板上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，所述多个第三透光开口在所述衬底基板上的正投影分别位于所述多个第二透光开口在所述衬底基板上的正投影内。
  14. 根据权利要求13所述的显示基板，其中，所述多个第三透光开口中的至少部分在所述衬底基板上的正投影的边界分别与所述多个第二透光开口在所述衬底基板上的正投影的边界的距离为0.5微米-1.5微米。
  15. 根据权利要求12-14任一所述的显示基板，其中，所述多个子像素包括第一子像素、第二子像素和第三子像素，
    所述多个第二透光开口中的至少部分位于相邻的第一子像素和第三子像素对应的第一透光开口之间，且与第一子像素对应的第一透光开口的距离不同于与第三子像素对应的第一透光开口的距离。
  16. 根据权利要求15所述的显示基板，其中，所述第一子像素和所述第三子像素排列为多行多列，
    位于同一列的多个第一子像素和多个第三子像素交替排列，且位于同一列的相邻的第一子像素和第三子像素对应的第一透光开口之间设置一个第二透光开口。
  17. 根据权利要求16所述的显示基板，其中，一个第一子像素、两个第二子像素和一个第三子像素组成一个重复单元，多个重复单元阵列排布，
    多个重复单元中的多个第二子像素排列为多行多列，所述一个第二透光开口还设置在行方向上相邻的第二子像素对应的第一透光开口之间。
  18. 根据权利要求17所述的显示基板，其中，所述多个隔垫物的每个在所述衬底基板上的正投影分别位于在列方向上相邻的第二子像素的子像素开口在所述衬底基板上的正投影之间，且分别位于在行方向上相邻的第一子像素和第三子像素的子像素开口在衬底基板上的正投影之间。
  19. 根据权利要求18所述的显示基板，其中，所述多个隔垫物的每个在所述衬底基板上的正投影与所述相邻的第一子像素和第三子像素中的第一子像素的子像素开口在衬底基板上的正投影的最短距离大于与所述相邻的第一子像素和第三子像素中的第三子像素的子像素开口在衬底基板上的正投影的最短距离。
  20. 根据权利要求19所述的显示基板，其中，所述多个隔垫物的每个在所述衬底基板上的正投影与所述相邻的第二子像素的子像素开口在衬底基板上的正投影的最短距离基本相同。
  21. 根据权利要求15-20任一所述的显示基板，其中，所述第一子像素为红色子像素，所述第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
  22. 根据权利要求11-21任一所述的显示基板，还包括设置在所述发光器件的远离所述衬底基板一侧的封装层以及设置在所述封装层的远离所述 衬底基板的一侧的触控层，
    其中，所述黑矩阵层设置在所述封装层的远离所述衬底基板的一侧，所述黑矩阵层设置在所述触控层的远离所述衬底基板的一侧，所述触控层包括多条触控走线，
    所述多条触控走线在所述衬底基板上的正投影与所述多个第二透光开口在所述衬底基板上的正投影不交叠。
  23. 根据权利要求22所述的显示基板，其中，所述第一子像素和所述第三子像素排列为多行多列，
    位于同一列的多个第一子像素和多个第三子像素交替排列，其中，所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素之间具有缺口。
  24. 根据权利要求23所述的显示基板，其中，所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素中靠近所述第三子像素的一侧或者靠近所述第一子像素的一侧具有缺口；或者
    所述多条触控走线中的至少部分在位于同一列的相邻的第一子像素和第三子像素中靠近所述第三子像素的一侧以及靠近所述第一子像素的一侧均具有缺口。
  25. 一种显示装置，包括权利要求1-24任一所述的显示基板。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150261050A1 (en) * 2014-03-14 2015-09-17 Innolux Corporation Display device
CN110504275A (zh) * 2018-05-17 2019-11-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置
CN110993661A (zh) * 2019-12-02 2020-04-10 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN112420956A (zh) * 2020-11-18 2021-02-26 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN112864205A (zh) * 2021-01-18 2021-05-28 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置
WO2021102988A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113690271A (zh) * 2020-05-18 2021-11-23 京东方科技集团股份有限公司 显示基板及显示装置
CN113707697A (zh) * 2021-08-27 2021-11-26 京东方科技集团股份有限公司 一种显示面板和显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150261050A1 (en) * 2014-03-14 2015-09-17 Innolux Corporation Display device
CN110504275A (zh) * 2018-05-17 2019-11-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置
WO2021102988A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN110993661A (zh) * 2019-12-02 2020-04-10 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN113690271A (zh) * 2020-05-18 2021-11-23 京东方科技集团股份有限公司 显示基板及显示装置
CN112420956A (zh) * 2020-11-18 2021-02-26 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN112864205A (zh) * 2021-01-18 2021-05-28 京东方科技集团股份有限公司 一种显示基板、显示面板及显示装置
CN113707697A (zh) * 2021-08-27 2021-11-26 京东方科技集团股份有限公司 一种显示面板和显示装置

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