WO2024020864A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024020864A1
WO2024020864A1 PCT/CN2022/108280 CN2022108280W WO2024020864A1 WO 2024020864 A1 WO2024020864 A1 WO 2024020864A1 CN 2022108280 W CN2022108280 W CN 2022108280W WO 2024020864 A1 WO2024020864 A1 WO 2024020864A1
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Prior art keywords
light
substrate
pixel
sub
color filter
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PCT/CN2022/108280
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English (en)
French (fr)
Inventor
胡耀
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/108280 priority Critical patent/WO2024020864A1/zh
Publication of WO2024020864A1 publication Critical patent/WO2024020864A1/zh

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  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED organic light-emitting diode
  • COE technology Color Filter On Encapsulation
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a driving substrate, a plurality of light-emitting elements, a color filter layer, a first light-transmitting opening, an optical glue layer and a cover plate; the plurality of light-emitting elements are located on the driving substrate; and the color filter layer is located away from the multiple light-emitting elements away from the driving substrate.
  • One side and includes a plurality of color filters and a black matrix located between adjacent color filters; the first light-transmitting opening is located in the black matrix; the optical adhesive layer is located on the side of the color filter layer away from the driving substrate ;
  • the cover plate is located on the side of the optical glue layer away from the optical glue layer.
  • Multiple light-emitting elements and multiple color filters are arranged in one-to-one correspondence.
  • One light-emitting element and the corresponding color filter are arranged in a direction perpendicular to the driving substrate.
  • the distance is the vertical distance a, and the distance in the direction parallel to the driving substrate between the edges of the first light-transmitting opening adjacent to the corresponding color filter is the lateral distance b.
  • the display substrate can limit the emission angle of stray light, and cause the stray light to be refracted at the interface between the display substrate and the air, thereby making the stray light emission angle larger, thereby preventing stray light from affecting normal display.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a driving substrate; a plurality of light-emitting elements located on the driving substrate; and a color film layer located on a side of the multiple light-emitting elements away from the driving substrate, And it includes a plurality of color filters and a black matrix located between the adjacent color filters; a first light-transmitting opening located in the black matrix; an optical glue layer located away from the color filter layer One side of the driving substrate; and a cover plate, located on the side of the optical adhesive layer away from the color filter layer, the plurality of light-emitting elements and the plurality of color filters are arranged in one-to-one correspondence, one The distance between the light-emitting element and the corresponding color filter in a direction perpendicular to the driving substrate is a vertical distance a, and the edge of the first light-transmitting opening adjacent to the corresponding color filter is parallel to the The distance in the direction of the driving substrate is the lateral distance b, and the vertical distance a and
  • n1 is the refractive index of the cover plate
  • n2 is the refractive index of air
  • the vertical distance a and the lateral distance b satisfy the following formula:
  • the vertical distance a and the lateral distance b satisfy the following formula:
  • the refractive index of the cover plate is less than or equal to 1.55.
  • the plurality of light-emitting elements include a first light-emitting element, a second light-emitting element and a third light-emitting element
  • the plurality of color filters include a first light filter. , a second filter and a third filter
  • the first filter is configured to allow light of the first color to pass through
  • the second filter is configured to allow light of the second color to pass through
  • the third filter is configured to allow light of a third color to pass through
  • the first light-emitting element is arranged corresponding to the first filter
  • the second light-emitting element and the second filter The third light-emitting element and the third optical filter are arranged correspondingly.
  • the distance between one of the first light-emitting elements and the corresponding first color filter in a direction perpendicular to the driving substrate is a first vertical distance a1
  • the distance between the edge of the first light-transmitting opening adjacent to the corresponding first color filter in the direction parallel to the driving substrate is the first lateral distance b1
  • one second light-emitting element The distance from the corresponding second color filter in the direction perpendicular to the driving substrate is a second vertical distance a2
  • the first light-transmitting layer adjacent to the corresponding second color filter The distance between the edge of the opening in the direction parallel to the driving substrate is the second lateral distance b2, and one of the third light-emitting elements and the corresponding third color filter is in the direction perpendicular to the driving substrate.
  • the distance is the third vertical distance a3, and the distance in the direction parallel to the driving substrate between the edge of the first light-transmitting opening adjacent to the corresponding third color filter is the third lateral distance b3 , the first lateral distance b1, the second lateral distance b2 and the third lateral distance b3 are different from each other.
  • a1, b1, a2, b2, a3 and b3 satisfy the following formula:
  • the size of the first light-transmitting opening between the first color filter and the second color filter is larger than that of the first color filter.
  • the size of the first light-transmitting opening between the light sheet and the third color filter is larger than that of the first color filter.
  • the size of the first light-transmitting opening between the first color filter and the second color filter is larger than that of the second color filter.
  • the size of the first light-transmitting opening between the light sheet and the third color filter is larger than that of the second color filter.
  • a1, b1, a2, b2, a3 and b3 satisfy the following formula:
  • the first light-emitting element is configured to emit light of a first color
  • the second light-emitting element is configured to emit light of a second color
  • the third light-emitting element is configured to emit light of a second color.
  • the light-emitting element is configured to emit light of a third color.
  • the first color is red
  • the second color is green
  • the third color is blue
  • each of the light-emitting elements includes an anode, an organic light-emitting layer, and a cathode.
  • a display substrate provided by an embodiment of the present disclosure further includes: an optical sensor located on a side of the driving substrate away from the light-emitting element.
  • the optical sensor includes at least one of an optical fingerprint recognition sensor, a facial recognition sensor, an infrared sensor and a distance sensor.
  • the display substrate includes a display area and a non-display area surrounding the display area, and the display area includes a fingerprint recognition area and a non-display area located outside the fingerprint recognition area.
  • the first light-transmitting opening is located in the fingerprint recognition area.
  • the driving substrate includes: a base substrate; a light-shielding layer provided on the base substrate and including a plurality of second light-transmitting openings; and a pixel driving circuit layer, Disposed on a side of the light shielding layer away from the base substrate; and a pixel definition layer, disposed on a side of the pixel driving circuit layer away from the base substrate, including a plurality of sub-pixel openings, the pixel
  • the driving circuit layer includes a plurality of pixel driving circuits.
  • the plurality of pixel driving circuits are electrically connected to the plurality of light-emitting elements and configured to drive the plurality of light-emitting elements to emit light.
  • the plurality of light-emitting elements are arranged on Among the plurality of sub-pixel openings, and forming a plurality of sub-pixels with the plurality of pixel driving circuits; the orthographic projection of at least part of the plurality of second light-transmitting openings on the base substrate is consistent with the third An orthographic projection of a light-transmitting opening overlaps on the base substrate.
  • the orthographic projection of the plurality of second light-transmitting openings on the base substrate is located at the orthographic projection of the plurality of sub-pixel openings on the base substrate. Between them, orthographic projections of the plurality of sub-pixel openings on the base substrate respectively overlap with orthographic projections of the plurality of color filters on the base substrate.
  • the orthographic projection of at least part of the plurality of second light-transmitting openings on the substrate is located at the position of the first light-transmitting opening on the substrate. Within the orthographic projection on the substrate.
  • the pixel driving circuit layer further includes first signal lines and second signal lines arranged parallel to each other and periodically arranged. Two signal lines are configured to provide different electrical signals to the plurality of pixel driving circuits, and the orthographic projection of each second light-transmitting opening on the substrate is located between the adjacent first signal line and the The second signal line is between orthographic projections on the base substrate.
  • the first signal line is a light emission control signal line
  • the second signal line is a reset control line
  • the driving circuit layer includes third signal lines arranged parallel to each other and periodically arranged, and the third signal lines are respectively connected with the first signal line and the The second signal lines intersect, the third signal lines are configured to provide power signals to the plurality of pixel driving circuits, the third signal lines include hollow portions, and each of the second light-transmitting openings is in the substrate substrate The orthographic projection on the hollow portion is located within the orthographic projection of the hollow portion on the base substrate.
  • the orthographic projection of the first light-transmitting opening on the substrate substrate is consistent with the projection of the first signal line and the second signal line on the substrate.
  • the orthographic projections on the substrate do not overlap, and the orthographic projection of the first light-transmitting opening on the substrate is located within the orthographic projection of the hollow portion on the substrate.
  • a display substrate provided by an embodiment of the present disclosure further includes a spacer layer disposed on a side of the pixel definition layer away from the base substrate, and the spacer layer includes a plurality of spacers.
  • the light transmittance of the material of the spacer layer is less than 5%.
  • At least one embodiment of the present disclosure also provides a display device, which includes the above-mentioned display substrate.
  • Figure 1 is a schematic cross-sectional view of a display substrate
  • Figure 2 is a schematic cross-sectional view of another display substrate
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • Figure 6 is a partial cross-sectional schematic view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a partial plan view of a light-shielding layer in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 8 is a partial plan view of a stack of light shielding layers and color filter layers in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 9 is a partial plan view of a light shielding layer, a color filter layer and a color filter stack in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 10 is a schematic plan view of a stack of first light-transmitting openings and second light-transmitting openings in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 11 is a schematic planar arrangement of multiple spacers in a spacer layer in a display substrate according to at least one embodiment of the present disclosure
  • Figure 12 is a schematic plan view of a color filter layer and a touch layer stack in a display substrate according to at least one embodiment of the present disclosure
  • Figure 13 is a schematic plan view of a spacer layer and a color filter layer stacked in a display substrate according to at least one embodiment of the present disclosure
  • Figure 14 is an equivalent circuit schematic diagram of an 8T1C pixel driving circuit provided by at least one embodiment of the present disclosure
  • Figure 15 is a working timing diagram of a pixel driving circuit provided by at least one embodiment of the present disclosure.
  • 16-27 are schematic plan views of various layers in a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 28 is a schematic diagram of the stacking of a first light-transmitting opening and a color filter according to an embodiment of the present disclosure
  • Figure 29 is a schematic stacking diagram of a light shielding layer, a first electrode and a sub-pixel opening according to an embodiment of the present disclosure.
  • FIG. 30 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • COE technology Color Filter On Encapsulation replaces polarizers by setting color filters on the encapsulation layer.
  • color filters can be used to further improve sub-pixels of different colors. The purity of the light emitted thereby improves the display color gamut.
  • the polarizer can be eliminated, thereby reducing the loss of light, thereby reducing the power consumption of the display device and increasing the standby time of the display device.
  • the fingerprint recognition function is one of the important functions of the display device. Since there is a black matrix at the edge of the color filter, its light transmittance is very low (less than 10-5 %) and cannot meet the requirements of optical fingerprint recognition technology.
  • a first light-transmitting opening can be provided on the black matrix, so that the light reflected by the fingerprint can pass through the first light-transmitting opening and enter the corresponding optical fingerprint sensor, thereby realizing optical fingerprint recognition.
  • Figures 1 and 2 are schematic cross-sectional views of a display substrate.
  • the display substrate 10 includes a driving substrate 11, a light-emitting element 12, a color filter 13 and a black matrix 14; the light-emitting element 12 and the color filter 13 are arranged correspondingly, so that the light-emitting element 12 emits light Most of the light can pass through the color filters 13 and emerge; the black matrix 14 is disposed between adjacent color filters 13 .
  • the display substrate 10 also includes a first light-transmitting opening 15 and an optical fingerprint sensor 20 ; the first light-transmitting opening 15 is located in the black matrix 14 , and the optical fingerprint sensor 20 is located on the side of the driving substrate 11 away from the light-emitting element 12 . At this time, the first light-transmitting opening 15 is also located between adjacent color filters 13 .
  • the light emitted by the display substrate 10 can be illuminated on the finger 50 , and the light reflected by the finger 50 can be injected into the optical fingerprint sensor 20 through the first light-transmitting opening 15 ; the optical fingerprint sensor 20 can detect the finger. imaging to achieve fingerprint recognition.
  • FIG. 2 when the display substrate 10 performs display, due to the existence of the first light-transmitting opening 15 , part of the light emitted by the light-emitting element 12 can be emitted through the first light-transmitting opening 15 , forming stray light and affecting normal operation. show.
  • the display substrate includes a driving substrate, a plurality of light-emitting elements, a color filter layer, a first light-transmitting opening, an optical glue layer and a cover plate; the plurality of light-emitting elements are located on the driving substrate; and the color filter layer is located away from the multiple light-emitting elements away from the driving substrate.
  • One side includes a plurality of color filters and a black matrix located between adjacent color filters; the first light-transmitting opening is located in the black matrix; the optical adhesive layer is located on the side of the color filter layer away from the driving substrate ; The cover plate is located on the side of the optical glue layer away from the optical glue layer.
  • Multiple light-emitting elements and multiple color filters are arranged in one-to-one correspondence.
  • One light-emitting element and the corresponding color filter are arranged in a direction perpendicular to the driving substrate.
  • the distance is the vertical distance a
  • the distance between the edge of the first light-transmitting opening adjacent to the corresponding color filter in the direction parallel to the driving substrate is the lateral distance b.
  • the vertical distance a and the lateral distance b satisfy the following formula:
  • n1 is the refractive index of the cover plate
  • n2 is the refractive index of air.
  • the display substrate by controlling the vertical distance between the light-emitting element and the corresponding color filter in a direction perpendicular to the driving substrate and the distance between the first light-transmitting opening adjacent to the corresponding color filter The distance between the edges in the direction parallel to the driving substrate, the display substrate can limit the emission angle of stray light, and cause the stray light to be refracted at the interface between the display substrate and the air, thereby making the emission angle of the stray light larger, thereby enabling Avoid stray light affecting normal display.
  • FIG. 3 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a driving substrate 110, a plurality of light-emitting elements 120, a color filter layer 130, a first light-transmitting opening 140, an optical glue layer 150 and a cover plate 160;
  • the plurality of light-emitting elements 120 are located on the driving substrate 110;
  • the color film layer 130 is located on the side of the plurality of light-emitting elements 120 away from the driving substrate 110, and includes a plurality of color filters 132 and a black matrix 135 located between adjacent color filters 132;
  • the light opening 140 is located in the black matrix 135; for example, the first light-transmitting opening 140 penetrates the black matrix 135, so that light can pass through the black matrix 125 through the first light-transmitting opening 140.
  • the optical adhesive layer 150 is located on the side of the color filter layer 130 away from the driving substrate 110 ;
  • the cover plate 160 is located
  • a plurality of light-emitting elements 120 and a plurality of color filters 132 are arranged in one-to-one correspondence, so that most of the light emitted by the light-emitting elements 120 can be emitted through the corresponding color filters 132 .
  • the distance between one light-emitting element 120 and the corresponding color filter 132 in the direction perpendicular to the driving substrate 110 is the vertical distance a.
  • the edge of the first light-transmitting opening 140 adjacent to the corresponding color filter 132 is parallel to The distance in the direction of the driving substrate 110 is the lateral distance b, and the vertical distance a and the lateral distance b satisfy the following formula:
  • n1 is the refractive index of the cover plate
  • n2 is the refractive index of air.
  • the display substrate provided by the embodiment of the present disclosure, by controlling the vertical distance between the light-emitting element and the corresponding color filter in a direction perpendicular to the driving substrate and the distance between the first light-transmitting opening adjacent to the corresponding color filter
  • the distance between the edges in a direction parallel to the driving substrate allows the display substrate to limit the exit angle of stray light and cause the stray light to be refracted at the interface between the display substrate and the air, thereby making the stray light exit angle larger.
  • the user cannot see stray light within a larger viewing angle range (for example, 120 degrees), thereby preventing stray light from affecting normal display.
  • the display substrate can utilize color filters.
  • the film is used to further improve the purity of the light emitted by sub-pixels of different colors (one sub-pixel may include a light-emitting element and a corresponding color filter), thereby improving the display color gamut.
  • the display substrate can also use the color film layer to achieve anti-reflective effect, thereby eliminating the need for polarizers and reducing light loss, thereby reducing power consumption and extending standby time.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100 includes a driving substrate 110 , a plurality of light-emitting elements 120 , a color filter layer 130 , a first light-transmitting opening 140 , an optical glue layer 150 and a cover plate 160 .
  • the plurality of light-emitting elements 120 are located on the driving substrate 110; the color filter layer 130 is located on the side of the plurality of light-emitting elements 120 away from the driving substrate 110, and includes a plurality of color filters 132 and is located between adjacent color filters 132
  • the black matrix 135; the first light-transmitting opening 140 is located in the black matrix 135; for example, the first light-transmitting opening 140 penetrates the black matrix 135, so that light can pass through the black matrix 125 through the first light-transmitting opening 140.
  • the optical adhesive layer 150 is located on the side of the color filter layer 130 away from the driving substrate 110 ; the cover plate 160 is located on the side of the optical adhesive layer 150 away from the color filter layer 130 .
  • the plurality of light-emitting elements 120 and the plurality of color filters 132 are arranged in one-to-one correspondence, so that most of the light emitted by the light-emitting elements 120 can be emitted through the corresponding color filters 132 .
  • the distance between one light-emitting element 120 and the corresponding color filter 132 in the direction perpendicular to the driving substrate 110 is the vertical distance a
  • the edge of the first light-transmitting opening 140 adjacent to the corresponding color filter 132 The distance in the direction parallel to the driving substrate 110 is the lateral distance b
  • the vertical distance a and the lateral distance b satisfy the following formula:
  • the display substrate by controlling the vertical distance between the light-emitting element and the corresponding color filter in a direction perpendicular to the driving substrate and the edge of the first light-transmitting opening adjacent to the corresponding color filter, The distance in the direction parallel to the driving substrate, the display substrate can limit the emission angle of stray light, and cause the stray light to undergo total reflection at the interface between the display substrate and the air, so that the stray light cannot emit, thus avoiding the influence of stray light normal display.
  • the above vertical distance a and lateral distance b satisfy the following formula:
  • the display substrate by controlling the vertical distance between the light-emitting element and the corresponding color filter in a direction perpendicular to the driving substrate and the edge of the first light-transmitting opening adjacent to the corresponding color filter, The distance in the direction parallel to the driving substrate, the display substrate can limit the emission angle of stray light, and cause the stray light to undergo total reflection at the interface between the display substrate and the air, so that the stray light cannot emit, thus avoiding the influence of stray light normal display.
  • the driving substrate 110 may include a rigid substrate such as a glass substrate, a quartz substrate, a plastic substrate, or the like, or a flexible substrate such as a polyimide substrate.
  • the driving substrate may be a silicon-based semiconductor substrate.
  • the driving substrate 110 may also include structures such as pixel driving circuits, data lines, and power lines for driving the light-emitting elements 120 to emit light. These structures can be referred to the general design, and the embodiments of the present disclosure will not be described again here.
  • the display substrate 100 may further include an encapsulation layer 170 , which is located on a side of the plurality of light-emitting elements 120 away from the driving substrate 110 ; at this time, the color filter layer 130 is disposed on The encapsulation layer 170 is away from the side of the driving substrate.
  • the display substrate forms a flat surface through the encapsulation layer, thereby facilitating the formation of the above-mentioned color filter layer 130 and improving the alignment accuracy between the color filter 132 and the corresponding light-emitting element 120 .
  • the refractive index of cover 160 is less than or equal to 1.55. Therefore, when a user attaches a protective film to the surface of a display device using the display substrate, since the refractive index of the cover plate is less than or equal to 1.55, the display substrate can prevent stray light from being refracted at the interface between the cover plate and the protective film. The rear exit angle becomes smaller.
  • the plurality of light-emitting elements 120 includes a first light-emitting element 130A, a second light-emitting element 120B, and a third light-emitting element 120C
  • the plurality of color filters 132 includes a first light-emitting element 130A, a second light-emitting element 120B, and a third light-emitting element 120C.
  • the third filter 132C is configured to allow the light of the third color to pass through
  • the first light-emitting element 120A is provided correspondingly to the first filter 132A
  • the second light-emitting element 120B is provided correspondingly to the second filter 132B
  • the third light-emitting element 120C is provided correspondingly to the third optical filter 132C. Therefore, the display substrate can use the first color filter to further improve the purity of the light emitted by the first light-emitting element, the second color filter to further improve the purity of the light emitted by the second light-emitting element, and the third color filter.
  • the light sheet is used to further improve the purity of the light emitted by the third light-emitting element. Therefore, the display substrate can improve the display color gamut.
  • the first light-emitting element 130A is configured to emit light of a first color
  • the second light-emitting element 120B is configured to emit light of a second color
  • the third light-emitting element 120C is configured to emit light of a third color.
  • embodiments of the present disclosure include but are not limited thereto.
  • the first light-emitting element, the second light-emitting element and the third light-emitting element can also emit white light.
  • the first color is red
  • the second color is green
  • the third color is blue.
  • embodiments of the present disclosure include, but are not limited to, this.
  • the distance between one first light-emitting element 120A and the corresponding first color filter 132A in the direction perpendicular to the driving substrate 110 is the first vertical distance a1, and the corresponding The distance between the edges of the adjacent first light-transmitting openings 140 of the first color filter 132A in the direction parallel to the driving substrate is the first lateral distance b1; a second light-emitting element 120B and a corresponding second color filter
  • the distance of the piece 132B in the direction perpendicular to the driving substrate 110 is the second vertical distance a2
  • the edge of the first light-transmitting opening 140 adjacent to the corresponding second color filter 132B is in the direction parallel to the driving substrate 110
  • the distance is the second lateral distance b2;
  • the distance between a third light-emitting element 120C and the corresponding third color filter 132C in the direction perpendicular to the driving substrate 110 is the third vertical distance a3, and the distance between a third light-emitting element
  • the distance between the edges of the adjacent first light-transmitting openings 140 of the light sheet 132C in the direction parallel to the driving substrate 110 is the third lateral distance b3; the first lateral distance b1, the second lateral distance b2 and the third lateral distance b3 are mutually exclusive. Are not the same.
  • the refractive index of the light of different colors on the cover plate will also have certain differences.
  • the display substrate can allow sub-pixels of different colors to adopt different lateral distances, so that the space on the display substrate can be used more rationally.
  • the display substrate can first ensure that the green stray light has a larger exit angle or total reflection occurs at the interface between the cover and the air.
  • first vertical distance a1, first lateral distance b1, second vertical distance a2, second lateral distance b2, third vertical distance a3 and third lateral distance b3 satisfy the following formula:
  • the display substrate can be as reasonable as possible while ensuring that stray light of various colors does not affect the normal display. Make optimal use of the area on the display substrate.
  • the first lateral distance b1 of the edge of the first light-transmitting opening adjacent to the first light-emitting element and the corresponding first color filter in the direction parallel to the driving substrate can be set smaller, and the corresponding The size of the first light-transmitting opening adjacent to the first color filter, thereby increasing the area of the first light-transmitting opening on the premise of ensuring that stray light of various colors does not affect the normal display, thereby increasing the number of optical fingerprint recognition sensors The amount of light entering thereby improves the performance of fingerprint recognition.
  • the size of the first light-transmitting opening 140 between the first color filter 132A and the second color filter 132B is larger than that of the first color filter 132A and the second color filter 132B.
  • the size of the first light-transmitting opening between the first color filter and the second color filter is larger than that of the second color filter.
  • the size of the first light-transmitting opening between the light sheet and the third color filter Since the above-mentioned first lateral distance b1 and second lateral distance b2 can be set smaller than the third lateral distance b3, the size of the first light-transmitting opening between the first color filter and the second color filter can be It is larger than the size of the first light-transmitting opening between the second color filter and the third color filter.
  • first vertical distance a1, first lateral distance b1, second vertical distance a2, second lateral distance b2, third vertical distance a3 and third lateral distance b3 satisfy the following formula:
  • each light-emitting element 120 includes an anode 121, an organic light-emitting layer 122, and a cathode 123. Therefore, the light-emitting element 120 can be an organic light-emitting element. It should be noted that each light-emitting element may also include an auxiliary functional layer for assisting light emission, such as an electron transport layer, a hole transport layer, etc.
  • the display substrate 100 may further include an optical sensor 180 ; the optical sensor 180 is located on a side of the driving substrate 110 away from the light-emitting element 120 .
  • the optical sensor can implement various functions such as fingerprint recognition, facial recognition, distance sensing, etc. through the light incident from the first light-transmitting opening.
  • the above-mentioned optical sensor may include at least one of an optical fingerprint recognition sensor, a facial recognition sensor, an infrared sensor, and a distance sensor.
  • the light reflected by the finger or fingerprint can be injected into the optical fingerprint recognition sensor through the first light-transmitting opening, thereby realizing the fingerprint recognition function.
  • the orthographic projection of the first light-transmitting opening 140 on the driving substrate 110 falls within the orthographic projection of the optical fingerprint recognition sensor 180 on the driving substrate 110 .
  • FIG. 5 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a display area 101 and a non-display area 102 surrounding the display area 101; the display area 101 includes a fingerprint recognition area 101A and a normal display area 101B located outside the fingerprint recognition area 101A; the first transparent The light opening 140 is located in the fingerprint recognition area 101 .
  • FIG. 6 is a partial cross-sectional schematic view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a partial plan view of a light-shielding layer in a display substrate according to an embodiment of the present disclosure. As shown in FIGS.
  • the driving substrate 110 includes a base substrate 111 , a light-shielding layer S, a pixel driving circuit layer 112 and a pixel definition layer PDL;
  • the light-shielding layer S is provided on the base substrate 111 and includes a plurality of second The light-transmitting opening S1;
  • the pixel driving circuit layer 112 is disposed on the side of the light-shielding layer S away from the base substrate 111;
  • the pixel definition layer PDL is disposed on the side of the pixel driving circuit layer 112 away from the base substrate 111 and includes a plurality of sub-pixel openings 113 .
  • the pixel driving circuit layer 112 includes a plurality of pixel driving circuits 1120.
  • the plurality of pixel driving circuits 1120 are electrically connected to the plurality of light-emitting elements 120 and are configured to drive the plurality of light-emitting elements 120 to emit light.
  • the plurality of light-emitting elements 120 are arranged on multiple in the sub-pixel opening 113, and form a plurality of sub-pixels 200 with the plurality of pixel driving circuits 1120; the orthographic projection of at least part of the plurality of second light-transmitting openings S1 on the substrate 110 is in conjunction with the first light-transmitting opening 140.
  • the orthographic projections on the base substrate 110 overlap.
  • each pixel driving circuit 1120 includes a thin film transistor TFT and a storage capacitor (not shown) and other structures, and may be formed into a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, which will be described in detail later.
  • the thin film transistor TFT includes an active layer 112A, a gate electrode 112G, a first electrode 112D, a second electrode 112S and other structures.
  • the light-emitting element 120 includes a first electrode 121, a light-emitting material layer 122 and a second electrode 123.
  • the first electrode 121 serves as an anode and is electrically connected to the first electrode 112D of the thin film transistor TFT.
  • the luminescent material layer 122 includes an organic luminescent material and is configured to emit monochromatic light or white light.
  • the second electrode 123 serves as a cathode, for example, formed as a surface electrode, that is, the second electrodes 123 of multiple sub-pixels are continuously arranged in a surface shape to cover the base substrate 111 as a whole; or, in some embodiments, when the display substrate requires At the position where the light transmittance is increased, the second electrode 123 may have a pattern facing the first electrode 121, that is, the second electrode 123 is patterned to increase the light transmittance of the display substrate at this position.
  • the orthographic projections of the plurality of second light-transmitting openings S1 on the substrate 111 are respectively located between the orthographic projections of adjacent sub-pixel openings 113 among the plurality of sub-pixel openings 113 on the substrate 111 .
  • the orthographic projection of at least part of the plurality of second light-transmitting openings S1 on the base substrate 110 overlaps with the orthographic projection of the first light-transmitting opening 140 on the base substrate 110 .
  • the material of the light-shielding layer S can be a metal material such as copper or aluminum or an alloy material.
  • the light-shielding layer S can also be a light-shielding layer formed by adding black dye to a resin material to fully achieve the light-shielding effect. .
  • the light-shielding layer S can transmit the signal light used for fingerprint recognition at the second light-transmitting opening S1, and block the light emitted by the light-emitting element 120 of the display substrate and non-signal light such as ambient light at other positions. to prevent non-signal light from irradiating the optical sensor arranged on the non-display side of the display substrate, thereby improving the recognition speed and accuracy of the optical sensor.
  • the display substrate further includes a black matrix 135 disposed on a side of the light-emitting element 120 away from the base substrate 111 .
  • FIG. 8 is a partial plan view of a light shielding layer and a black matrix stack in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 9 is a partial plan view of a light shielding layer, a black matrix and a color filter in a display substrate according to at least one embodiment of the present disclosure. Partial plan view of stack-up.
  • FIG. 8 shows a schematic diagram of the black matrix 135 of the display substrate laminated on the light shielding layer S
  • FIG. 9 shows a schematic diagram of the black matrix 135 of the display substrate, the pixel definition layer PDL and the color filter 132 laminated.
  • the orthographic projections of the plurality of sub-pixel openings 113 on the base substrate 111 respectively at least partially overlap with the orthographic projections of the plurality of color filters 132 on the base substrate 111 , for example,
  • the orthographic projections of the plurality of sub-pixel openings 113 on the base substrate 111 are respectively located inside the orthographic projections of the plurality of color filters 132 on the base substrate 111 .
  • the distance b(b1) between the orthographic projection of the sub-pixel opening 113 on the base substrate 111 and the orthographic projection of the color filter 132 on the base substrate 111 is 1 micron-6.5 micron, for example 1 micron to 5 micron, such as 1 micron to 3.5 micron, such as 1 micron to 2 micron, such as 1.0 micron, 1.2 micron, 1.5 micron, 1.7 micron or 2.0 micron, etc.
  • the plurality of first light-transmitting openings 140 are respectively disposed between adjacent color filters 132 in the plurality of color filters 132 , and the plurality of second light-transmitting openings S1
  • the orthographic projections of at least part of the second light-transmitting openings S1 on the base substrate 111 respectively overlap at least partially with the orthographic projections of the plurality of first light-transmitting openings 140 on the base substrate 111 .
  • the second light-transmitting opening S1 and the first light-transmitting opening 140 form a hole to transmit signal light for fingerprint recognition, for example.
  • the side of the base substrate 111 away from the light-emitting element 120 can be provided with an optical Sensor 180 (or camera, distance sensor, infrared sensor, etc.), the optical sensor 180 can receive the signal light passing through the first light-transmitting opening 140 and the second light-transmitting opening S1 to perform texture collection and recognition functions.
  • the pixel driving circuit layer includes multiple metal layers, such as the metal layers where the gate electrode 112G, the first electrode 112D, the second electrode 112S, etc. are located.
  • the circuit pattern composed of these metal layers is formed on the base substrate.
  • the orthographic projection on 111 does not overlap with the orthographic projection of the plurality of second light-transmitting openings S1 on the base substrate 111, nor does it overlap with the orthographic projection of the first light-transmitting openings 140 on the base substrate 111 to avoid The circuit pattern affects the transmission of signal light.
  • the orthographic projections of at least part of the second light-transmitting openings S1 among the plurality of second light-transmitting openings S1 on the base substrate 111 are respectively located on the base substrate 111 of the plurality of first light-transmitting openings 140 .
  • FIG. 10 shows a schematic diagram of a stack of a second light-transmitting opening S1 and a corresponding first light-transmitting opening 140.
  • at least part of the plurality of second light-transmitting openings S1 is on the substrate 111.
  • the distance L3 between the orthogonal projection boundary on the substrate 111 and the orthographic projection boundary of the plurality of first light-transmitting openings 140 on the base substrate 111 is 0.5 microns to 1.5 microns, such as 0.8 microns, 1.0 microns, 1.2 microns or 1.5 microns, etc. .
  • the plurality of sub-pixels includes a first sub-pixel R, a second sub-pixel G and a third sub-pixel B
  • the plurality of color filters 132 includes a first sub-pixel R, a second sub-pixel G and a third sub-pixel B.
  • the orthographic projection of the sub-pixel opening 113 of the first sub-pixel R on the base substrate 111 is located within the orthographic projection of the first filter 132A on the base substrate 111 , so that the light emitted by the light-emitting element of the first sub-pixel R can be It exits through the first filter 132A.
  • the orthographic projection of the sub-pixel opening 113 of the second sub-pixel G on the base substrate 111 is located within the orthographic projection of the second filter 132B on the base substrate 111, so that the light emitted by the light-emitting element of the second sub-pixel G can be It exits through the second filter 132B.
  • the orthographic projection of the sub-pixel opening 113 of the third sub-pixel B on the base substrate 111 is located within the orthographic projection of the third filter 132C on the base substrate 111, so that the light emitted by the light-emitting element of the third sub-pixel B can be It exits through the third optical filter 132C.
  • At least part of the plurality of first light-transmitting openings 140 is located between the color filters 132 corresponding to the adjacent first sub-pixel R and the third sub-pixel B, and is connected to the first sub-pixel R.
  • the minimum distance of the color filter 132 corresponding to the pixel R is the first distance D1
  • the minimum distance of the color filter 132 corresponding to the third sub-pixel B is the second distance D2.
  • the first distance D1 is different from the second distance D2. .
  • the first distance D1 is smaller than the second distance D2, that is, the first light-transmitting opening 140 located between the adjacent first sub-pixel R and the third sub-pixel B is closer to the third sub-pixel B.
  • the first sub-pixels R and the third sub-pixels B are arranged in multiple rows and multiple columns, and the multiple first sub-pixels R and the multiple third sub-pixels B located in the same column are alternately arranged and located in A first light-transmitting opening 140 is provided between the color filters 132 corresponding to the adjacent first sub-pixel R and the third sub-pixel B in the same column, that is, the first light-transmitting opening 140 is provided adjacent to each other in the column direction. between the color filter 132 of the first sub-pixel R and the third sub-pixel B.
  • FIG. 9 also shows an enlarged schematic diagram of the sub-pixel opening 113 corresponding to the third sub-pixel B, the color filter 132, the third filter 132C and the adjacent first light-transmitting opening 140.
  • the structure shown in the boxed area is basically the same as that of the enlarged portion.
  • the orthographic projection of the sub-pixel opening 113 on the base substrate 111 is located at the position of the third filter 132C on the base substrate.
  • the distance b+d on the side of 140 is smaller than the distance b1+e on the side away from the first light-transmitting opening 140, that is, the third optical filter 132C is shifted away from the first light-transmitting opening 140 to avoid During the preparation process, the third optical filter 132C covers the first light-transmitting opening 140 due to alignment errors.
  • the orthographic projection of the sub-pixel opening 113 on the base substrate 111 is located at the position of the color filter 132 on the base substrate. 111, and the boundary of the orthographic projection of the sub-pixel opening 113 on the substrate 111 and the boundary of the orthographic projection of the color filter 132 on the substrate 111 are on the side close to the first light-transmitting opening 140
  • the distance b is smaller than the distance b1 on the side away from the first light-transmitting opening 140 , that is, the color filter 132 is also shifted in a direction away from the first light-transmitting opening 140 .
  • b is 0.5 micron-1.5 micron, such as 1.0 micron, b1 is 1.0 micron-2.0 micron, such as 1.5 micron; or b is 1.2 micron, b1 is 1.7 micron, etc.
  • the boundary of the orthographic projection of the color filter 132 on the base substrate 111 is the same as the first light-transmitting opening 140 .
  • the distance a between the boundary of the orthographic projection of the light-transmitting opening 140 on the substrate 111 is greater than or equal to 4 microns. If the distance between the color filter 132 and the first light-transmitting opening 140 is too small, on the one hand, there will be light emitted by the light-emitting element 120 Leakage into the first light-transmitting opening 140 causes interference.
  • the color filter layer is easily opened at the color filter 132 and the first light-transmitting opening 140 , making it difficult to form separate color filters 132 and 140 .
  • the first light-transmitting opening 140 is easily opened at the color filter 132 and the first light-transmitting opening 140 , making it difficult to form separate color filters 132 and 140 .
  • the boundary of the orthographic projection of the third filter 132C on the substrate 111 is equal to
  • the distance c of the boundary of the orthographic projection of the first light-transmitting opening 140 on the substrate 111 is greater than or equal to 0, for example, greater than 0.5 microns, so that the third optical filter 132C does not cover the first light-transmitting opening 140 to avoid damaging the third light-transmitting opening 140 .
  • the signal light transmitted through the light-transmitting opening 140 causes interference.
  • the third filter 132C is on the substrate.
  • the distance d between the boundary of the orthographic projection on the substrate 111 and the boundary of the orthographic projection of the color filter 132 on the substrate 111 is greater than or equal to 2 microns, that is, the third filter 132C exceeds the color filter 132 by more than or equal to 2 microns.
  • the distance of microns is to increase the contact area between the third filter 132C and the black matrix 135 and prevent the third filter 132C from peeling off the color filter 132 .
  • the distance between the boundary of the orthographic projection of the third filter 132C on the base substrate 111 and the boundary of the orthographic projection of the color filter 132 on the base substrate 111 e is greater than or equal to 3 microns, which is greater than d above. Therefore, during the preparation process, once the third filter 132C is peeled off from the color filter 132 due to a small d value, the third filter 132C can be moved as a whole to increase the d value to improve the peeling phenomenon. and ensure that production can continue.
  • the orthographic projection of the sub-pixel opening 113 on the substrate 111 is located on the substrate 111 of the first filter 132A.
  • the orthographic projection on the base substrate 111 is inside, and the boundary of the orthographic projection of the sub-pixel opening 113 on the base substrate 111 and the orthographic projection of the first filter 132A on the base substrate 111 are close to the first light-transmitting opening.
  • the distance f on the side of the first light-transmitting opening 140 is substantially equal to the distance g on the side away from the first light-transmitting opening 140 .
  • a first sub-pixel R, two second sub-pixels G and a third sub-pixel B form a repeating unit, and multiple repeating units are arranged in an array.
  • the second sub-pixels G are arranged in multiple rows and multiple columns, and the first light-transmitting openings 140 are also disposed between the color filters 132 corresponding to the adjacent second sub-pixels G in the row direction.
  • the distance between the first light-transmitting opening 140 and the color filter 132 corresponding to the adjacent second sub-pixel G in the row direction is substantially the same.
  • the first sub-pixel R is a red sub-pixel
  • the second sub-pixel G is a green sub-pixel
  • the third sub-pixel B is a blue sub-pixel
  • the first filter 132A is a red filter
  • the second filter 132B is a green filter
  • the third filter 132C is a blue filter.
  • the first sub-pixel R can also be a green sub-pixel or a blue sub-pixel
  • the second sub-pixel G can also be a red sub-pixel or a blue sub-pixel
  • the third sub-pixel B can also be It is a red sub-pixel or a green sub-pixel.
  • a color filter of a corresponding color is set on each sub-pixel.
  • each repeating unit (for example, as shown in the quadrilateral dotted box in Figure 9) is provided with two second light-transmitting openings S1 and two first light-transmitting openings. 140;
  • the orthographic projections of the two second light-transmitting openings S1 on the base substrate 111 should be respectively located within the orthographic projections of the two first light-transmitting openings 140 on the base substrate 111.
  • two second light-transmitting openings S1 are provided for each repeating unit, and one first light-transmitting opening 140 is provided for each repeating unit or multiple repeating units. In this case, multiple second light-transmitting openings S1 are provided.
  • the orthographic projections of some of the second light-transmitting openings S1 in the light-transmitting openings S1 on the base substrate 111 should be respectively located within the orthographic projections of the plurality of first light-transmitting openings 140 on the base substrate 111 .
  • some of the second light-transmitting openings S1 and the first light-transmitting openings 140 form nested holes for transmitting signal light, while other second light-transmitting openings S1 are not used for transmitting signal light.
  • the position of the first light-transmitting openings 140 can be relatively flexibly set.
  • the The third filter 132C corresponding to the three sub-pixels B may not be offset as shown in FIG. 9 .
  • the display substrate further includes a spacer layer 190 disposed on a side of the pixel definition layer PDL away from the base substrate 111 , and the spacer layer 190 includes a plurality of spacers PS.
  • the plurality of spacers PS may support devices such as masks during the preparation process of the display substrate.
  • Figure 11 shows a schematic planar arrangement of multiple spacers.
  • the orthographic projections of the plurality of spacers PS on the base substrate 111 are respectively located at the sub-pixel openings 113 of the second sub-pixel G adjacent in the column direction on the base substrate. 111, and are respectively located between the orthographic projections of the sub-pixel openings 113 of the first sub-pixel R and the third sub-pixel G adjacent in the row direction on the substrate 111.
  • the minimum distance between the spacers PS and the sub-pixel openings 113 is L, and 1 micron ⁇ L ⁇ 8 microns.
  • L is 2 microns, 4 microns, 6 microns or 8 microns. wait. Therefore, the plurality of spacers PS are separated from the plurality of sub-pixel openings 113 by a certain distance.
  • the side walls of the sub-pixel openings 113 usually have a certain inclination angle, if the distance between the plurality of spacers PS and the plurality of sub-pixel openings 113 is If the distance is too close, the spacer PS may be formed on the side wall of the sub-pixel opening 113, thereby reducing the height of the spacer PS relative to the base substrate 111, making it difficult to achieve a sufficient spacer effect.
  • the spacers PS among the plurality of spacers PS have a planar shape that is rectangular.
  • the length L1 and width W1 of the rectangle range from 13 microns to 19 microns.
  • the length L1 can be 15 microns, 17 microns, or 19 microns
  • the width W1 can be 13 microns, 15 microns, or 17 microns.
  • at least part of the planar shape of the spacer PS can also be a square. In this case, the side length of the square can be 12 microns, 15 microns, 17 microns or 19 microns, etc.
  • the planar shape of at least some of the spacers PS among the plurality of spacers PS may also be circular.
  • the diameter of the circle may be 13 microns to 19 microns, such as 15 microns or 17 microns, etc.; or, in some embodiments, the plurality of spacers PS may include main spacers and auxiliary spacers, and the planar shapes of the main spacers and auxiliary spacers may be circular.
  • the sum of the circular diameters of the main spacer and the auxiliary spacer may be 13 microns to 19 microns, such as 15 microns or 17 microns.
  • the height of the spacers PS is 0.5 microns to 2.0 microns, such as 1.0 microns or 1.5 microns. etc. to fully realize the spacer function.
  • the orthographic projection of each of the plurality of spacers PS on the base substrate 111 is aligned with the sub-pixel of the first sub-pixel R in the adjacent first sub-pixel R and the third sub-pixel B.
  • the shortest distance L11 of the orthographic projection of the pixel opening 113 on the base substrate 111 is greater than the sub-pixel opening 113 on the base substrate 111 of the third sub-pixel B among the adjacent red sub-pixel R and the blue sub-pixel B.
  • the shortest distance L12 of the orthographic projection that is, the spacer PS provided between the adjacent first sub-pixel R and the third sub-pixel B is closer to the third sub-pixel than the sub-pixel opening 113 of the first sub-pixel R.
  • Sub-pixel opening 113 of pixel B is
  • the orthographic projection of each of the plurality of spacers PS on the base substrate 111 and the sub-pixel opening 113 of the adjacent second sub-pixel G are on the base substrate.
  • the shortest distance L13 of the orthographic projection on 111 is basically the same, that is, the distance between the spacer PS provided between adjacent second sub-pixels G and the sub-pixel opening 113 of the adjacent second sub-pixel G is basically the same.
  • the material of spacer layer 190 has a light transmittance of less than 5%, such as less than 2%.
  • the plurality of spacers PS can be made of black opaque material, such as a black opaque material formed by doping a black dye in a resin material. This material has a good absorption effect on light, so it is not exposed to external ambient light. When illuminated on the spacer PS, the external ambient light will not be reflected but absorbed, so the color separation phenomenon can be weakened or even eliminated.
  • the material of the pixel defining layer PDL has a light transmittance of less than 5%, such as less than 2%.
  • the material of the pixel definition layer PDL can be the same as the material of the plurality of spacers PS, so that the half-tone mask can be used in the preparation process to be formed in the same patterning process, or the two can also be made of the same or different materials. materials are formed separately.
  • the display substrate further includes an encapsulation layer 170 disposed on a side of the light-emitting element 120 away from the base substrate 111 , and a black matrix 135 is disposed on a side of the encapsulation layer 170 away from the base substrate 111 .
  • the encapsulation layer 170 may be a composite encapsulation layer, including a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer (not shown in the figure) sequentially disposed on the light emitting element 120 to improve the encapsulation effect.
  • color filters for multiple sub-pixels may be disposed in a composite encapsulation layer, such as between two adjacent sub-encapsulation layers in the composite encapsulation layer.
  • the composite encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer that are sequentially disposed on the light-emitting element 120.
  • the color filter may be disposed on the first inorganic encapsulation layer. between the encapsulation layer and the second inorganic encapsulation layer.
  • the display substrate further includes a touch layer FM disposed on a side of the encapsulation layer 170 away from the substrate substrate 111 , and the black matrix 135 is disposed on a side of the touch layer FM away from the substrate. one side of the base substrate 111 .
  • FIG. 12 shows a schematic plan view of the touch layer FM.
  • the touch layer FM includes a plurality of touch traces TL, and the orthographic projection of the plurality of touch traces TL on the substrate 111 It does not overlap with the orthographic projection of the plurality of second light-transmitting openings S1 on the base substrate 111 .
  • the orthographic projection of the plurality of touch traces TL on the base substrate 111 does not overlap with the orthographic projection of the plurality of color filters 132 on the base substrate 111 .
  • the second light-transmitting opening S1 and the color filter 132 avoid affecting the transmission of the signal light and the light emitted by the light-emitting element 120 .
  • the plurality of touch traces TL are connected to at least one of the first filter 132A, the second filter 132B, and the third filter 132C.
  • the distance between the two is different.
  • the distance between the touch trace TL and the third optical filter 132C is greater than the distance from the first optical filter 132A. Since the shape and arrangement of the third optical filter 132C are irregular, the distance between the touch trace TL and the third optical filter 132C is set larger in this direction to avoid the touch trace TL and the third optical filter 132C.
  • the filters 132C overlap in this direction, or the overlapping size is too large.
  • the first sub-pixel R and the third sub-pixel B are arranged in multiple rows and multiple columns, and multiple first sub-pixels R and multiple third sub-pixels located in the same column B are arranged alternately.
  • the plurality of touch traces TL have gaps NT1/NT2/NT3 between adjacent first sub-pixels R and third sub-pixels B located in the same column. Therefore, it is possible to avoid the touch trace TL from blocking the plurality of first light-transmitting openings 140 .
  • At least some of the plurality of touch traces TL are on one side or close to the third sub-pixel B among the adjacent first sub-pixels R and third sub-pixels B located in the same column. There is a gap NT1 on one side of the first sub-pixel R. At this time, at least part of the plurality of touch traces TL has a gap between the adjacent first sub-pixel R and the third sub-pixel B located in the same column. ; Alternatively, at least part of the plurality of touch traces TL is on one side of the adjacent first sub-pixel R and the third sub-pixel B located in the same column close to the third sub-pixel B and close to the first sub-pixel R. have gaps NT2/NT3 on both sides.
  • At least part of the plurality of touch traces TL is close to the third sub-pixel in the adjacent first sub-pixel R and the third sub-pixel B located in the Nth column.
  • One side of the pixel B or a side close to the first sub-pixel R has a notch NT1, and at least some of the plurality of touch traces TL are located between the adjacent first sub-pixel R and the N+1th column.
  • both the side close to the third sub-pixel B and the side close to the first sub-pixel R have notches NT2/NT3.
  • the display substrate may also include other structures such as a cover plate.
  • other structures such as a cover plate.
  • FIG. 13 is a schematic plan view of a spacer layer and a color filter layer in a display substrate according to an embodiment of the present disclosure.
  • the display substrate has a plurality of sub-pixels.
  • the plurality of sub-pixels include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B; the first sub-pixel R and the third sub-pixel B are arranged along rows.
  • the first pixel rows are alternately arranged upward to form multiple rows of first pixels, and the first sub-pixels R and the third sub-pixels B located in the same column in the multiple first pixel rows are alternately arranged, and the second sub-pixels G are arranged side by side along the row direction to form multiple rows of first pixels.
  • the display substrate includes a base substrate 111, a pixel driving circuit layer 112, a pixel defining layer PDL and a black matrix 135.
  • the pixel driving circuit layer 112 is disposed on the base substrate 111, and the pixel defining layer PDL is disposed on the pixel driving circuit layer.
  • a side of 112 away from the base substrate 111 includes a plurality of sub-pixel openings 113 for a plurality of sub-pixels, wherein each of the plurality of sub-pixels 130 includes a pixel driving circuit disposed in the pixel driving circuit layer 112 and at least part of The light-emitting element 120 is disposed in the sub-pixel opening 113 .
  • FIG. 13 shows a schematic plan view of a stack of black matrix 135 and spacer layer 190 .
  • the adjacent third The connection line C1 between the centers O1 and O2 of the color filter 132 corresponding to one sub-pixel R and the third sub-pixel B passes through the one first light-transmitting opening 140 .
  • the distance h1 between the center O3 of the first light-transmitting opening 140 and the center O1 of the color filter 132 corresponding to the first sub-pixel R is different from the distance h1 of the color filter corresponding to the third sub-pixel B.
  • the distance h2 between the center O1 of the light sheet 132, for example, h1 is greater than h2, that is, the first light-transmitting opening 140 is closer to the color filter corresponding to the third sub-pixel B than the color filter 132 corresponding to the first sub-pixel R.
  • a plurality of first light-transmitting openings 140 are respectively disposed between the color filters 132 corresponding to adjacent second sub-pixels G in the row direction.
  • the adjacent first sub-pixel G For example, as shown in FIG. 13 , for a first light-transmitting opening 140 and a color filter 132 corresponding to a second sub-pixel G adjacent to the first light-transmitting opening 140 , the adjacent first sub-pixel G The line C2 connecting the centers O4 and O5 of the corresponding color filter 132 passes through the first light-transmitting opening 140 .
  • the distances h3 and h4 between the center O6 of the first light-transmitting opening 140 and the centers O4 and O5 of the color filter 132 corresponding to the adjacent second sub-pixel G are substantially the same.
  • the plurality of color filters 132 includes a first filter 132A, a second filter 132B, and a third filter 132C.
  • the orthographic projection of the sub-pixel opening 113 of the first sub-pixel R on the base substrate 111 is located within the orthographic projection of the first filter 132A on the base substrate 111 , so that the light emitted by the light-emitting element of the first sub-pixel R can be It exits through the first filter 132A.
  • the orthographic projection of the sub-pixel opening 113 of the second sub-pixel G on the base substrate 111 is located within the orthographic projection of the second filter 132B on the base substrate 111, so that the light emitted by the light-emitting element of the second sub-pixel G can be It exits through the second filter 132B.
  • the orthographic projection of the sub-pixel opening 113 of the third sub-pixel B on the base substrate 111 is located within the orthographic projection of the third filter 132C on the base substrate 111, so that the light emitted by the light-emitting element of the third sub-pixel B can be It exits through the third optical filter 132C.
  • the boundary of the orthographic projection of the sub-pixel opening 113 on the base substrate 111 and the third filter 132C are on
  • the distance b+d of the orthographic projection boundary on the base substrate 111 on the side close to the first light-transmitting opening 140 is smaller than the distance b1+e on the side away from the first light-transmitting opening 140 .
  • the first subpixel R is a red subpixel
  • the second subpixel G is a green subpixel
  • the third subpixel B is a blue subpixel.
  • the display substrate further includes a light-shielding layer S.
  • the light-shielding layer S is disposed between the substrate substrate 111 and the pixel driving circuit layer 112 and includes a plurality of second light-transmitting openings S1 , and a plurality of second light-transmitting openings S1 .
  • the orthographic projections of at least part of the light openings S1 on the base substrate 111 are respectively located within the orthographic projections of the plurality of first light-transmitting openings 140 on the base substrate 111 .
  • a first sub-pixel R, two second sub-pixels G and a third sub-pixel B form a repeating unit, multiple repeating units are arranged in an array, and each of the multiple repeating units is provided with two corresponding second sub-pixels.
  • a first light-transmitting opening 140 is provided for each second light-transmitting opening S1, or in other embodiments, a first light-transmitting opening 140 is provided for every two or more second light-transmitting openings S1.
  • the display substrate may also include other structures, such as a spacer layer, an encapsulation layer, a touch layer, etc.
  • other structures such as a spacer layer, an encapsulation layer, a touch layer, etc.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • Figure 14 is an equivalent circuit schematic diagram of an 8T1C pixel driving circuit.
  • the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 storage capacitor C and multiple signal lines (such as data signal line Data, first scanning signal line Gate , the second scanning signal line GateN, the reset control signal line Reset, the first initial signal line INIT1, the second initial signal line INIT2, the first power line VDD, the second power line VSS and the light emission control signal line EM, etc.).
  • the gate of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the second initial signal line INIT2, and the second electrode of the first transistor T1 is connected to the fifth node N5.
  • the gate of the second transistor T2 is connected to the first scanning signal line Gate, the first electrode of the second transistor T2 is connected to the fifth node N5, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the first scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting control signal line EM, and the first electrode of the fifth transistor T5 is connected to the first power supply line.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first node of the light-emitting element). pole) connection.
  • the gate of the seventh transistor T7 is connected to the first scanning signal line Gate or the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the seventh transistor T7 is connected to the fourth Node N4 is connected.
  • the gate electrode of the eighth transistor T8 is connected to the second scanning signal line GateN, the first electrode of the eighth transistor T8 is connected to the fifth node N5, and the second electrode of the eighth transistor T8 is connected to the first node N1.
  • the first terminal of the storage capacitor C is connected to the first power line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.
  • the first to seventh transistors T1 to T7 may be N-type thin film transistors, and the eighth transistor T8 may be a P-type thin film transistor; or, the first to seventh transistors T1 to T7 may be P-type thin film transistors. , the eighth transistor T8 may be an N-type thin film transistor.
  • the first to seventh transistors T1 to T7 may be Low Temperature Polysilicon (LTPS) thin film transistors (TFT), and the eighth transistor T8 may be Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide). Gallium Zinc Oxide, IGZO) thin film transistor.
  • LTPS Low Temperature Polysilicon
  • TFT Low Temperature Polysilicon
  • IGZO Indium Gallium Zinc Oxide
  • the indium gallium zinc oxide thin film transistor generates less leakage current than the low temperature polysilicon thin film transistor. Therefore, setting the eighth transistor T8 as an indium gallium zinc oxide thin film transistor can significantly reduce the leakage current. to improve the low-frequency and low-brightness flicker problems of the display panel.
  • the first transistor T1 and the second transistor T2 do not need to be configured as indium gallium zinc oxide thin film transistors. Since the size of the low-temperature polysilicon thin film transistor is generally smaller than the indium gallium zinc oxide thin film transistor, the pixel driving method of the embodiment of the present disclosure The space occupied by the circuit will be relatively small, which will help improve the resolution of the display panel.
  • the above-mentioned pixel driving circuit provided by the embodiment of the present disclosure combines the good switching characteristics of LTPS-TFT and the low leakage characteristics of Oxide-TFT, and can realize low-frequency driving (1Hz ⁇ 60Hz) and greatly reduce the power consumption of the display screen.
  • the second electrode of the light-emitting element is connected to the second power line VSS, the signal of the second power line VSS continuously provides a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the signal of the first scanning signal line Gate is the scanning signal in the pixel driving circuit of this display row
  • the signal of the reset control signal line Reset is the scanning signal of the pixel driving circuit of the previous display row. That is, for the nth display row, the first scanning The signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1).
  • the signal of the reset control signal line Reset of this display row is the same as the signal of the first scanning signal line Gate in the pixel driving circuit of the previous display row.
  • the signals can be the same signal to reduce the signal lines of the display panel and achieve a narrow frame of the display panel.
  • the first scanning signal line Gate, the second scanning signal line GateN, the reset control signal line Reset, the emission control signal line EM, the first initial signal line INIT1 and the second initial signal line INIT2 all extend in the horizontal direction.
  • the second power line VSS, the first power line VDD and the data signal line DATA all extend in the vertical direction.
  • At least part of the first initial signal line INIT1, the second initial signal line INIT2, the second power line VSS, and the first power line VDD may be a mesh structure, that is, including both horizontal and vertical extensions. extended part.
  • FIG 15 is a working timing diagram of a pixel driving circuit.
  • the following describes exemplary embodiments of the present disclosure through the working process of the pixel driving circuit illustrated in Figure 14.
  • the pixel driving circuit in Figure 14 includes 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C.
  • the embodiment takes as an example that the first to seventh transistors T1 to T7 are P-type transistors, the eighth transistor T8 is an N-type transistor, and the gate of the seventh transistor T7 is connected to the first scanning signal line Gate.
  • the working process of the pixel driving circuit may be as follows.
  • the first stage t1 is called the reset stage.
  • the signals of the first scanning signal line Gate, the reset control signal line Reset, the second scanning signal line GateN and the light-emitting control signal line EM are all high-level signals.
  • the reset control signal line Reset The signal is a low level signal.
  • the high level signal of the emission control signal line EM turns off the fifth transistor T5 and the sixth transistor T6, the high level signal of the second scanning signal line GateN turns on the eighth transistor T8, and the low level of the reset control signal line Reset
  • the signal causes the first transistor T1 to be turned on. Therefore, the voltage of the first node N1 is reset to the second initial voltage Vinit2 provided by the second initial signal line INIT2. Then the electrical position of the reset control signal line Reset is high, and the first transistor T1 is turned off. . Since the fifth transistor T5 and the sixth transistor T6 are turned off, the light-emitting element EL does not emit light at this stage.
  • the second stage t2 is called the data writing stage.
  • the signal of the first scanning signal line Gate is a low-level signal.
  • the fourth transistor T4, the second transistor T2 and the seventh transistor T7 are turned on, and the data signal line Data outputs the data voltage.
  • the voltage of the fourth node N4 is reset to the first initial voltage Vinit1 provided by the first initial voltage line INIT1, completing the initialization.
  • the third transistor T3 is turned on.
  • the fourth transistor T4 and the second transistor T2 are turned on so that the data voltage output by the data signal line Data passes through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the turned-on third node N3, and the turned-on third transistor T3.
  • the second transistor T2, the fifth node N5 and the eighth transistor T8 are provided to the first node N1, and charge the sum of the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 into the storage capacitor C.
  • the storage capacitor C The voltage at the second end (first node N1) is Vdata+Vth, Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.
  • the signal of the light-emitting control signal line EM is a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off to ensure that the light-emitting element EL does not emit light.
  • the third stage t3 is called the light-emitting stage.
  • the signals of the first scanning signal line Gate and the reset control signal line Reset are high-level signals, and the signals of the light-emitting control signal line EM and the second scanning signal line GateN are both low-level signals. .
  • the high-level signal of the reset control signal line Reset turns off the seventh transistor T7
  • the low-level signal of the light-emitting control signal line EM turns on the fifth transistor T5 and the sixth transistor T6, and the power output from the first power line VDD
  • the voltage provides a driving voltage to the first electrode (ie, the fourth node N4) of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 (ie, the third transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata+Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.
  • the current I flowing through the light-emitting element EL has nothing to do with the threshold voltage Vth of the third transistor T3. This eliminates the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensures the uniformity of brightness.
  • the pixel driving circuit eliminates the residual positive charge of the light-emitting element EL after the last light emission, realizes compensation for the gate voltage of the third transistor, and avoids the threshold voltage drift of the third transistor from driving the light-emitting element EL.
  • the influence of current improves the uniformity of the display image and the display quality of the display panel.
  • the pixel driving circuit of the embodiment of the present disclosure can reset the light-emitting element EL by initializing the fourth node N4 to the signal of the first initial signal line INIT1 and by initializing the fifth node N5 to the signal of the second initial signal line INIT2.
  • the voltage and the reset voltage of the first node N1 are adjusted separately to achieve better display effects and improve problems such as low-frequency flickering.
  • 16-27 illustrate schematic plan views of various layers of a display substrate provided by at least one embodiment of the present disclosure being stacked in sequence.
  • FIG. 16 shows a schematic plan view of the light-shielding layer, and the light-shielding layer includes a plurality of second light-transmitting openings S1.
  • FIG. 17 shows a schematic plan view of a first semiconductor layer stacked behind a light-shielding layer.
  • the first semiconductor layer includes active layers of a plurality of thin film transistors.
  • the first semiconductor layer may be made of silicon material, including amorphous silicon and polycrystalline silicon; in some embodiments, the first semiconductor layer may be made of amorphous silicon a-Si, and polysilicon is formed through crystallization or laser annealing.
  • the first semiconductor layer may include a first active layer 10 of the first transistor T1, a second active layer 20 of the second transistor T2, a third active layer 30 of the third transistor T3, a fourth The fourth active layer 40 of the transistor T4, the fifth active layer 50 of the fifth transistor T5, the sixth active layer 60 of the sixth transistor T6, and the seventh active layer 70 of the seventh transistor T7.
  • the first active layer 10 , the second active layer 20 , the third active layer 30 , the fourth active layer 40 , the fifth active layer 50 , the sixth active layer 60 and the seventh active layer 70 are interconnected. Connected one-piece structure.
  • the shape of the third active layer 30 may be in the shape of a "ji"
  • the first active layer 10 , the second active layer 20 , the fourth active layer 40 , the fifth active layer 50 , and the The sixth active layer 60 and the seventh active layer 70 may be in a "1" shape.
  • the first semiconductor layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the channel region of the third active layer 30 extends along the row direction, and the first active layer 10 , the second active layer 20 , the fourth active layer 40 , the fifth active layer 50 , and the third active layer 30 extend along the row direction.
  • the channel regions of the sixth active layer 60 and the seventh active layer 70 extend in the column direction.
  • the orthographic projection of the second light-transmitting opening S1 on the base substrate 111 is adjacent to the orthographic projection of the sixth active layer 60 and the seventh active layer 70 on the base substrate 111 .
  • the first light-transmitting opening S1 The orthographic projection of the opening 140 on the base substrate 111 is adjacent to the orthographic projections of the sixth active layer 60 and the seventh active layer 70 on the base substrate 111 .
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor may all be LTPS thin film transistor.
  • p-Si polycrystalline silicon
  • FIG. 18 shows a schematic plan view of a first conductive layer stack behind a first semiconductor layer.
  • the first conductive layer may include: a first scanning signal line Gate_P, a reset control signal line Reset_P, a light emission control signal line EM_P, and a first plate Ce1 of the storage capacitor C.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first scanning signal line Gate_P, the reset control signal line Reset_P and the light emitting control signal line EM_P all extend along the first direction X.
  • the reset control signal line Reset_P is located on the side of the first scanning signal line Gate_P away from the emission control signal line EM_P, and the first plate Ce1 of the storage capacitor is disposed between the first scanning signal line Gate_P and the emission control signal line EM_P between.
  • the pixel driving circuit layer (such as the above-mentioned first conductive layer) includes a first signal line (such as a light emission control signal line EM_P in some embodiments) and a second signal line (such as in some embodiments) arranged in parallel and periodically arranged. In the embodiment, it is the reset control line Reset_P).
  • the first signal line and the second signal line are configured to provide different electrical signals to multiple sub-pixels.
  • the orthographic projections of the multiple second light-transmitting openings S1 on the substrate substrate 111 are respectively located at The orthographic projection of a first signal line (for example, the light emission control signal line EM_P) on the substrate 111 and a second signal line (for example, the reset control line Reset_P) closest to the first signal line are on the substrate 111 between the orthographic projections on the substrate 111.
  • the orthographic projections of the plurality of first light-transmitting openings 140 on the substrate 111 are respectively located between the orthographic projection of a first signal line (for example, the light-emitting control signal line EM_P) on the substrate 111 and the first signal line EM_P.
  • a second signal line (for example, a reset control line Reset_P) that is closest to a signal line is between orthographic projections on the base substrate 111 .
  • the plurality of sub-pixels include a first row of sub-pixels RO1 and a second row of sub-pixels RO2 adjacent to the first row of sub-pixels RO1 and located below the first row of sub-pixels RO1.
  • the pixel driving circuit of the first row of sub-pixels RO1 is shared.
  • the pixel driving circuit of the second row of sub-pixels RO2 shares one light-emitting control signal line EM_P and one reset control line Reset_P.
  • the pixel driving circuit of the first row of sub-pixels RO1 shares one A row of second light-transmitting openings is included between the orthographic projection of the emission control signal line EM_P on the substrate substrate 111 and the orthographic projection of the reset control line Reset_P shared by the pixel driving circuit of the second row sub-pixel RO2 on the substrate substrate 111 Orthographic projection of S1 on the base substrate 111.
  • the orthographic projection of the light-emitting control signal line EM_P common to the pixel driving circuits of the first row sub-pixel RO1 on the substrate 111 and the reset control line Reset_P common to the pixel driving circuit of the second row sub-pixel RO1 are projected on the substrate 111 .
  • the orthographic projections on the substrate 111 include a row of orthographic projections of the first light-transmitting openings 140 on the base substrate 111 .
  • the first plate Ce1 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate Ce1 on the base substrate 111 is consistent with the third active terminal of the third transistor T3. There is an overlapping area in the orthographic projection of layer 30 on base substrate 111 .
  • the first plate Ce1 also serves as the gate of the third transistor T3.
  • the area where the reset control signal line Reset_P overlaps with the first active layer of the first transistor T1 serves as the gate electrode of the first transistor T1
  • the first scanning signal line Gate_P overlaps with the second active layer of the second transistor T2.
  • the area where the source layers overlap serves as the gate electrode of the second transistor T2
  • the area where the first scanning signal line Gate_P overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4
  • the emission control signal line EM_P The area overlapping the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5.
  • the area overlapping the emission control signal line EM_P and the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. gate.
  • the reset control signal line Reset_P in the sub-pixels of the next row of each row of sub-pixels (the same signal as the first scanning signal line Gate_P in the sub-pixels of this row) is connected to the seventh active terminal of the seventh transistor T7 in the sub-pixels of this row.
  • the area where the layers overlap serves as the gate electrode of the seventh transistor T7.
  • FIG. 19 shows a schematic plan view of a second conductive layer stack behind the first conductive layer.
  • the second conductive layer includes: the second plate Ce2 of the storage capacitor C and the first branch GateN_B1 of the second scanning signal line GateN.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first branch GateN_B1 of the second scanning signal line GateN extends along the first direction X.
  • the second plate Ce2 of the storage capacitor is located between the first branch GateN_B1 of the second scanning signal line GateN and the light emission control signal line EM_P.
  • the outline of the second electrode plate Ce2 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate Ce2 on the base substrate 111 is aligned with the first electrode plate Ce1 on the substrate.
  • the orthographic projections on the base substrate 111 have overlapping areas.
  • the second electrode plate Ce2 is provided with an opening H, and the opening H may be located in the middle of the second electrode plate Ce2.
  • the opening H may be a regular hexagon, so that the second electrode plate Ce2 forms a ring structure.
  • the opening H exposes the third insulating layer covering the first electrode plate Ce1, and the orthographic projection of the first electrode plate Ce1 on the base substrate 111 includes the orthographic projection of the opening H on the base substrate 111.
  • the opening H is configured to accommodate a subsequently formed fourth via hole.
  • the fourth via hole is located in the opening H and exposes the first plate Ce1, so that the second electrode of the subsequently formed eighth transistor T8 is connected to the second electrode of the eighth transistor T8.
  • the first plate Ce1 is connected.
  • FIG. 20 shows a schematic plan view of the second semiconductor layer stack behind the second conductive layer.
  • the second semiconductor layer of each sub-pixel may include an eighth active layer 80 of the eighth transistor T8.
  • the eighth active layer 80 extends along the second direction Y, and the eighth active layer 80 may be shaped like a dumbbell.
  • the second semiconductor layers of any two adjacent columns of sub-pixels have a mirror-symmetric structure.
  • the second semiconductor layer may be made of oxide, that is, the eighth transistor is an oxide thin film transistor.
  • FIG. 21 shows a schematic plan view of a third conductive layer stack behind the second conductive layer.
  • the third conductive layer includes: a second branch GateN_B2 of the second scanning signal line GateN and a second initial signal line INIT2.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the second branch GateN_B2 of the second scanning signal line GateN extends along the first direction X, and the second branch GateN_B2 of the second scanning signal line GateN is close to the second branch Gate_B2 of the first scanning signal line Gate. In some embodiments, a region where the second branch GateN_B2 of the second scanning signal line GateN overlaps the eighth active layer 80 serves as the gate of the eighth transistor.
  • the orthographic projection of the second branch GateN_B2 of the second scanning signal line on the base substrate 111 overlaps with the orthographic projection of the first branch GateN_B1 of the second scanning signal line on the base substrate 111 .
  • the first branch GateN_B1 of the second scanning signal line and the second branch GateN_B2 of the second scanning signal line may be connected through signal lines in the peripheral area.
  • the second initial signal line INIT2 extends along the first direction
  • the orthographic projection of the second light-transmitting opening S1 on the base substrate 111 is also located directly on the base substrate 111 of the light-emitting control signal line EM_P and a second initial signal line INIT2 closest to the light-emitting control signal line EM_P. between projections.
  • the orthographic projection of the first light-transmitting opening 140 on the base substrate 111 is also located on the light-emitting control signal line EM_P and a second initial signal line INIT2 closest to the light-emitting control signal line EM_P on the base substrate 111 between the orthographic projections on.
  • FIG. 22 shows a planar distribution diagram of a plurality of via holes in the insulating layer formed on the third conductive layer.
  • a plurality of via holes are provided in the insulating layer.
  • the plurality of via holes include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V4, and a third via hole V3.
  • the first via hole V1 exposes the surface of the second region of the eighth active layer 80 .
  • the second via hole exposes the surface of the first region of the eighth active layer 80 .
  • the third via V3 exposes the surface of the first region of the second active layer.
  • the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor T2 to the second active layer through the via hole.
  • the fourth via hole V4 is located within the opening H of the second electrode plate Ce2, and the orthographic projection of the fourth via hole V4 on the base substrate 111 is within the range of the orthographic projection of the opening H on the base substrate 111.
  • the hole V4 exposes the surface of the first electrode plate Ce1.
  • the fourth via hole V4 is configured to connect the subsequently formed third connection electrode 43 to the first electrode plate Ce1 through the via hole.
  • the fifth via V5 exposes the surface of the first region of the fifth active layer.
  • the fifth via hole V5 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the fifth active layer through the via hole.
  • the sixth via hole V6 is located in the area where the second electrode plate Ce2 is located, and the orthographic projection of the sixth via hole V6 on the base substrate 111 is within the range of the orthographic projection of the second electrode plate Ce2 on the base substrate 111.
  • the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the via hole V6 are etched away, exposing the surface of the second electrode plate Ce2.
  • the sixth via hole V6 is configured so that the fifth connection electrode 45 formed later is connected to the second electrode plate Ce2 through the via hole.
  • the seventh via hole V7 exposes the surface of the first region of the first active layer.
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via hole.
  • the eighth via hole V8 exposes the surface of the first region of the seventh active layer.
  • the eighth via hole V8 is configured to allow the subsequently formed first initial signal line to be connected to the seventh active layer through the via hole.
  • the ninth via hole V9 exposes the surface of the second area of the sixth active layer.
  • the ninth via hole V9 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the sixth active layer through the via hole. Seven active layer connections.
  • the tenth via hole V10 exposes the surface of the first region of the fourth active layer.
  • the tenth via hole V10 is configured so that the second connection electrode 42 formed later is connected to the fourth active layer through the via hole.
  • the eleventh via hole V11 exposes the surface of the second initial signal line INIT2.
  • the eleventh via hole V11 is configured so that the sixth connection electrode 46 formed later is connected to the second initial signal line INIT2 through the via hole.
  • Figure 23 shows a schematic plan view of the fourth conductive layer stack behind the third conductive layer.
  • the fourth conductive layer includes: a first initial signal line INIT1, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45 and a third connection electrode.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 source-drain metal
  • the fourth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first initial signal line INIT1 extends along the first direction X, and the first initial signal line INIT1 is connected to the first region of the seventh active layer through the eighth via V8, so that the seventh transistor T7 The first pole has the same potential as the first initial signal line INIT1.
  • one end of the first connection electrode 41 is connected to the first region of the second active layer (also the second region of the first active layer) through the third via hole V3, and the other end passes through the second via hole V3.
  • V2 is connected to the first area of the eighth active layer.
  • the first connection electrode 41 may serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor, and the second electrode of the first transistor.
  • the second connection electrode 42 is connected to the first region of the fourth active layer through the tenth via hole V10 on the one hand, and is connected to the subsequently formed data signal through the subsequently formed thirteenth via hole V13 on the other hand. Line Data connection.
  • the second connection electrode 42 may serve as the first electrode of the fourth transistor T4.
  • one end of the third connection electrode 43 is connected to the second region of the eighth active layer through the first via hole V1, and the other end thereof is connected to the first plate Ce1 through the fourth via hole V4.
  • the third connection electrode 43 may serve as the second electrode of the eighth transistor T8.
  • the fourth connection electrode 44 passes through the ninth via V9 and the second region of the sixth active layer (also the second region of the seventh active layer) on the one hand, and on the other hand passes through the subsequently formed
  • the twelfth via hole V12 is connected to the first electrode connection electrode formed later.
  • the fourth connection electrode 44 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the fifth connection electrode 45 (power connection electrode) is connected to the second plate Ce2 through the sixth via hole V6 on the one hand, and is connected to the third electrode of the fifth active layer through the fifth via hole V5 on the other hand.
  • One area connection, the fifth connection electrode 45 is configured to be connected to the subsequently formed first power line VDD through the subsequently formed fourteenth via hole V14.
  • one end of the sixth connection electrode 46 is connected to the first region of the first active layer through the seventh via hole V7, and the other end is connected to the second initial signal line through the eleventh via hole V11, so that the third The first pole of a transistor T1 and the second initial signal line INIT2 have the same potential.
  • the first planarization layer 97 includes: a twelfth via hole V12, a thirteenth via hole V13, and a fourteenth via hole V14;
  • the fifth conductive layer includes: a data signal line Data, the first power supply line VDD and the first electrode connection electrode 51 .
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fifth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the fifth conductive layers of any two adjacent columns of sub-pixels may not have a mirror symmetrical structure, and the first light-transmitting opening or the second light-transmitting opening may be added as needed.
  • the area of the second source-drain metal layer below is used to increase the flatness of the first electrode (anode) formed on the upper layer, so that the entire sub-pixel is located on a plane, thereby reducing color shift and improving display quality.
  • the first power lines VDD in two adjacent columns of sub-pixels may be an integral structure connected to each other.
  • the anode formed on the upper layer can be made flatter.
  • the driving circuit layer includes third signal lines (such as the above-mentioned first power supply line VDD) that are arranged parallel to each other and arranged periodically.
  • the third signal lines extend along the second direction Y and are connected to the first signal line and the second signal line respectively. intersect, the third signal line is configured to provide power signals to multiple sub-pixels.
  • the third signal line includes a hollow portion OD, and the orthographic projection of the second light-transmitting opening S1 on the substrate substrate 111 is located in the hollow portion OD. within the orthographic projection on the base substrate 111.
  • the orthographic projection of the first light-transmitting opening 140 on the base substrate 111 is located within the orthographic projection of the hollow portion OD1 on the base substrate 111 .
  • the first electrode connection electrode 51 may be in a rectangular shape, and the first electrode connection electrode 51 is connected to the fourth connection electrode 44 through the twelfth via hole V12.
  • the first power line VDD is connected to the fifth connection electrode 45 through the fourteenth via hole V14.
  • the data signal line Data extends along the second direction Y, and the data signal line Data is connected to the second connection electrode 42 through the thirteenth via hole V13, because the second connection electrode 42 is connected to the second connection electrode 42 through the tenth via hole V10.
  • the first area of the fourth active layer is connected, thus realizing the connection between the data signal line and the first pole of the fourth transistor, so that the data signal transmitted by the data signal line Data can be written into the fourth transistor.
  • FIG. 25 shows a schematic plan view of the second planarization layer stack behind the fifth conductive layer.
  • the second planarization layer 98 includes a fifteenth via V15.
  • the fifteenth via hole V15 is located in the area where the first electrode connecting electrode 51 is located, and the second flat layer in the fifteenth via hole V15 is removed to expose the surface of the first electrode connecting electrode 51.
  • the five via holes V15 are configured to allow a subsequently formed first electrode (eg, an anode) to be connected to the first electrode connecting electrode 51 through the via holes.
  • Figure 26 shows a schematic plan view of the first electrode layer.
  • the first electrode layer includes first electrodes 121 of a plurality of sub-pixels.
  • Each first electrode 121 includes a main body part 121A and a connection part 121B.
  • the main body part 121A is exposed by the sub-pixel opening 113 , and the connection part 121B passes through respectively.
  • the fifteenth via hole V15 is connected to the first electrode 51 .
  • the pixel driving circuit can drive The light-emitting element emits light.
  • FIG. 27 shows a schematic plan view of the pixel definition layer PDL.
  • the pixel definition layer PDL includes a plurality of sub-pixel openings 113.
  • the shape of the plurality of sub-pixel openings 113 is consistent with the shape of the main body portion 121A of the first electrode 121.
  • the substrate is the same and has a size slightly smaller than that of the main body 121A to fully expose the main body 121A.
  • the base substrate 111 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polyether One or more of styrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the materials of the first inorganic material layer and the second inorganic material layer can be Silicon nitride (SiNx) or silicon oxide (SiOx) is used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti). ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti).
  • Mo molybdenum
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • the insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multi-layer or composite layer.
  • the planarization layer can be made of organic materials, and the multiple traces TL of the touch layer FM can be made of metal oxide materials such as indium tin oxide ITO or indium zinc oxide IZO.
  • the first semiconductor layer may be polysilicon (p-Si), and the second semiconductor layer (SML2) may be oxide.
  • the stacked structure of the display substrate provided by the embodiments of the present disclosure is only an illustrative description. In some embodiments, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. The embodiments of the present disclosure are not limited here. .
  • Figure 28 is a schematic diagram of the stacking of a first light-transmitting opening and a color filter according to an embodiment of the present disclosure; as shown in Figure 28, the orthographic projection of the first light-transmitting opening 140 on the substrate 110 is covered by the first The color filter 132A, the second color filter 132B and the third color filter 132C are surrounded by orthographic projections on the base substrate 110 .
  • the shape of the orthographic projection of the first light-transmitting opening 140 on the substrate 110 is circular; of course, embodiments of the present disclosure include but are not limited to this, the first light-transmitting opening 140 is formed on the substrate 110
  • the shape of the orthographic projection can also be other shapes, such as a rectangle.
  • the shape of the orthographic projection of the first color filter 132A on the base substrate 110 is a hexagon; the shape of the orthogonal projection of the second color filter 132B on the base substrate 110 is Hexagon; the orthogonal projection shape of the third color filter 132C on the base substrate 110 is a right-angled symmetrical pentagon.
  • the embodiments of the present disclosure include but are not limited to this, and the shapes of the orthographic projections of these color filters on the base substrate can also be other shapes.
  • Figure 29 is a schematic diagram of the stacking of a light-shielding layer, a first electrode and a sub-pixel opening according to an embodiment of the present disclosure; as shown in Figure 29, the shape of the orthographic projection of the second light-transmitting opening S1 on the base substrate 110 can be It is in the shape of a long strip, and both ends of the long strip include protrusions respectively.
  • FIG. 30 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 300 includes the above-mentioned display substrate 100 . Therefore, the display device can avoid stray light from affecting normal display, and also has a higher color gamut and a longer standby time.
  • the display device can be any product or component with a display function, such as a smartphone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.
  • a display function such as a smartphone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

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Abstract

一种显示基板和显示装置。在显示基板（100）中，多个发光元件（120）位于驱动基板（110）上；彩膜层（130）位于多个发光元件（120）远离驱动基板（110）的一侧，且包括多个彩色滤光片（132）和位于相邻的彩色滤光片（132）之间的黑矩阵（135）；第一透光开口（140）位于黑矩阵（135）之中；光学胶层（150）位于彩膜层（130）远离驱动基板（110）的一侧；盖板（160）位于光学胶层（150）远离彩膜层（130）的一侧，多个发光元件（120）与多个彩色滤光片（132）一一对应设置，一个发光元件（120）与对应的彩色滤光片（132）在垂直于驱动基板（110）的方向上的距离为垂直距离a，与对应的彩色滤光片（132）相邻的第一透光开口（140）的边缘在平行于驱动基板（110）的方向上的距离为横向距离b，垂直距离a和横向距离b满足以下公式： (I)n1为盖板的折射率，n2为空气的折射率。该显示基板（100）可避免杂散光影响显示。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，人们对于显示装置的显示品质的要求也越来越高。由于具有色域广、响应速度快、可柔性显示、可弯曲以及高对比度等优点，有机发光二极管(OLED)显示装置的应用范围越来越广泛。
另一方面，消费者对显示色域追求，对高待机时长要求，使得COE技术(Color Filter On Encapsulation)在有机发光二极管显示装置上的应用成为了研究热点。
发明内容
本公开实施例提供一种显示基板和显示装置。该显示基板包括驱动基板、多个发光元件、彩膜层、第一透光开口、光学胶层和盖板；多个发光元件位于驱动基板上；彩膜层位于多个发光元件远离驱动基板的一侧，且包括多个彩色滤光片和位于相邻的彩色滤光片之间的黑矩阵；第一透光开口位于黑矩阵之中；光学胶层位于彩膜层远离驱动基板的一侧；盖板位于光学胶层远离光学胶层的一侧，多个发光元件与多个彩色滤光片一一对应设置，一个发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的距离为垂直距离a，与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离为横向距离b。通过控制发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的垂直距离和与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离满足一定的关系，该显示基板可限制杂散光的出射角度，并使得杂散光在显示基板与空气的界面处发生折射，从而使得杂散光的出光角度较大，从而可避免杂散光影响正常显示。
本公开至少一个实施例提供一种显示基板，其包括：驱动基板；多个发光元件，位于所述驱动基板上；彩膜层，位于所述多个发光元件远离所述驱动基板的一侧，且包括多个彩色滤光片和位于相邻的所述彩色滤光片之间的黑矩阵；第一透光开口，位于所述黑矩阵之中；光学胶层，位于所述彩膜层远离所 述驱动基板的一侧；以及盖板，位于所述光学胶层远离所述彩膜层的一侧，所述多个发光元件与所述多个彩色滤光片一一对应设置，一个所述发光元件与对应的所述彩色滤光片在垂直于驱动基板的方向上的距离为垂直距离a，与对应的彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为横向距离b，所述垂直距离a和所述横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000001
其中，n1为所述盖板的折射率，n2为空气的折射率。
例如，在本公开一实施例提供的显示基板中，所述垂直距离a和所述横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000002
例如，在本公开一实施例提供的显示基板中，所述垂直距离a和所述横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000003
例如，在本公开一实施例提供的显示基板中，所述盖板的折射率小于等于1.55。
例如，在本公开一实施例提供的显示基板中，所述多个发光元件包括第一发光元件、第二发光元件和第三发光元件，所述多个彩色滤光片包括第一滤光片、第二滤光片和第三滤光片，所述第一滤光片被配置为允许第一颜色的光透过，所述第二滤光片被配置为允许第二颜色的光透过，所述第三滤光片被配置为允许第三颜色的光透过，所述第一发光元件与所述第一滤光片对应设置，所述第二发光元件与所述第二滤光片对应设置，所述第三发光元件与所述第三滤光片对应设置。
例如，在本公开一实施例提供的显示基板中，一个所述第一发光元件与对应的所述第一彩色滤光片在垂直于所述驱动基板的方向上的距离为第一垂直距离a1，与对应的所述第一彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为第一横向距离b1，一个所述第二发光元件与对应的所述第二彩色滤光片在垂直于所述驱动基板的方向上的距离为第二垂直距离a2，与对应的所述第二彩色滤光片相邻的所述第一透光开口的边缘在平 行于所述驱动基板的方向上的距离为第二横向距离b2，一个所述第三发光元件与对应的所述第三彩色滤光片在垂直于所述驱动基板的方向上的距离为第三垂直距离a3，与对应的所述第三彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为第三横向距离b3，所述第一横向距离b1、所述第二横向距离b2和所述第三横向距离b3互不相同。
例如，在本公开一实施例提供的显示基板中，所述a1、b1、a2、b2、a3和b3满足以下公式：
Figure PCTCN2022108280-appb-000004
例如，在本公开一实施例提供的显示基板中，所述第一彩色滤光片和所述第二彩色滤光片之间的所述第一透光开口的尺寸大于所述第一彩色滤光片和所述第三彩色滤光片之间的所述第一透光开口的尺寸。
例如，在本公开一实施例提供的显示基板中，所述第一彩色滤光片和所述第二彩色滤光片之间的所述第一透光开口的尺寸大于所述第二彩色滤光片和所述第三彩色滤光片之间的所述第一透光开口的尺寸。
例如，在本公开一实施例提供的显示基板中，所述a1、b1、a2、b2、a3和b3满足以下公式：
Figure PCTCN2022108280-appb-000005
例如，在本公开一实施例提供的显示基板中，所述第一发光元件被配置为发第一颜色的光，所述第二发光元件被配置为发第二颜色的光，所述第三发光元件被配置为发第三颜色的光。
例如，在本公开一实施例提供的显示基板中，所述第一颜色为红色，所述第二颜色为绿色，所述第三颜色为蓝色。
例如，在本公开一实施例提供的显示基板中，各所述发光元件包括阳极、有机发光层和阴极。
例如，本公开一实施例提供的显示基板还包括：光学传感器，位于所述驱动基板远离所述发光元件的一侧。
例如，在本公开一实施例提供的显示基板中，所述光学传感器包括光学指纹识别传感器、面部识别传感器、红外传感器和距离传感器中的至少一种。
例如，在本公开一实施例提供的显示基板中，所述显示基板包括显示区和 围绕所述显示区的非显示区，所述显示区包括指纹识别区和位于所述指纹识别区之外的正常显示区，所述第一透光开口位于所述指纹识别区。
例如，在本公开一实施例提供的显示基板中，所述驱动基板包括：衬底基板；遮光层，设置在所述衬底基板上，包括多个第二透光开口；像素驱动电路层，设置在所述遮光层的远离所述衬底基板的一侧；以及像素界定层，设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括多个子像素开口，所述像素驱动电路层包括多个像素驱动电路，所述多个像素驱动电路与所述多个发光元件电性相连，并被配置为驱动所述多个发光元件进行发光，所述多个发光元件设置在所述多个子像素开口之中，并与所述多个像素驱动电路形成多个子像素；所述多个第二透光开口中的至少部分在所述衬底基板上的正投影与所述第一透光开口在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述多个第二透光开口在所述衬底基板上的正投影位于所述多个子像素开口在所述衬底基板上的正投影之间，所述多个子像素开口在所述衬底基板上的正投影分别与所述多个彩色滤光片在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述多个第二透光开口中的至少部分在所述衬底基板上的正投影位于所述第一透光开口在所述衬底基板上的正投影之内。
例如，在本公开一实施例提供的显示基板中，所述像素驱动电路层还包括相互平行设置且周期排布的第一信号线和第二信号线，所述第一信号线和所述第二信号线配置为向所述多个像素驱动电路提供不同的电信号，各所述第二透光开口在所述衬底基板上的正投影位于相邻的所述第一信号线和所述第二信号线在所述衬底基板上的正投影之间。
例如，在本公开一实施例提供的显示基板中，所述第一信号线为发光控制信号线，所述第二信号线为复位控制线。
例如，在本公开一实施例提供的显示基板中，所述驱动电路层包括相互平行设置且周期排布的第三信号线，所述第三信号线分别与所述第一信号线和所述第二信号线相交，所述第三信号线配置为向所述多个像素驱动电路提供电源信号，所述第三信号线包括镂空部，各所述第二透光开口在所述衬底基板上的正投影位于所述镂空部在所述衬底基板上的正投影之内。
例如，在本公开一实施例提供的显示基板中，所述第一透光开口在所述衬 底基板上的正投影与所述第一信号线和所述第二信号线在所述衬底基板上的正投影不交叠，所述第一透光开口在所述衬底基板上的正投影位于所述镂空部在所述衬底基板上的正投影内。
例如，本公开一实施例提供的显示基板还包括设置在所述像素界定层的远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物，所述隔垫物层的材料的透光率小于5％。
本公开至少一个实施例还提供一种显示装置，其包括上述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的剖面示意图；
图2为另一种显示基板的剖面示意图；
图3为本公开一实施例提供的一种显示基板的结构示意图；
图4为本公开一实施例提供的另一种显示基板的结构示意图；
图5为本公开一实施例提供的一种显示基板的平面示意图；
图6为本公开至少一实施例提供的显示基板的部分截面示意图；
图7为本公开至少一实施例提供的显示基板中遮光层的部分平面示意图；
图8为本公开至少一实施例提供的显示基板中遮光层与彩膜层叠层的部分平面示意图；
图9为本公开至少一实施例提供的显示基板中遮光层、彩膜层与彩色滤光片叠层的部分平面示意图；
图10为本公开至少一实施例提供的显示基板中第一透光开口与第二透光开口叠层的平面示意图；
图11为本公开至少一实施例提供的显示基板中隔垫物层的多个隔垫物的平面排布示意图；
图12为本公开至少一实施例提供的显示基板中彩膜层与触控层叠层的平面示意图；
图13为本公开至少一实施例提供的显示基板中隔垫物层与彩膜层叠层的平面示意图；
图14为本公开至少一实施例提供的一种8T1C像素驱动电路的等效电路示意图；
图15为本公开至少一实施例提供的为一种像素驱动电路的工作时序图；
图16-图27为本公开至少一实施例提供的显示基板中各个层的平面示意图；
图28为本公开一实施例提供的一种第一透光开口和彩色滤光片的层叠示意图；
图29为本公开一实施例提供的一种遮光层、第一电极和子像素开口的层叠示意图；以及
图30为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
在应用COE技术的有机发光二极管显示装置中，COE技术(Color Filter On Encapsulation)通过在封装层上设置彩色滤光片来替换偏光片，一方面可利用彩色滤光片来进一步提高不同颜色子像素的出光的纯度，从而提高显示色域，另一方面还可取消设置偏光片，从而可减少光的损失，进而可降低显示装置的功耗并提高显示装置的待机时长。
另一方面，随着技术的发展，指纹识别功能是显示装置的重要功能之一。由于彩色滤光片的边缘存在黑矩阵，其透光率很低(小于10 -5％)，无法满足光 学指纹识别技术的要求。对此，可在黑矩阵上设置第一透光开口，使得经过指纹反射的光线可以从第一透光开口穿过并进入相应的光学指纹传感器，从而实现光学指纹识别。
图1和图2为一种显示基板的剖面示意图。如图1和图2所示，该显示基板10包括驱动基板11、发光元件12、彩色滤光片13和黑矩阵14；发光元件12和彩色滤光片13对应设置，以使得发光元件12发出的光线大部分可穿过彩色滤光片13并出射；黑矩阵14设置在相邻的彩色滤光片13之间。该显示基板10还包括第一透光开口15和光学指纹传感器20；第一透光开口15位于黑矩阵14中，光学指纹传感器20位于驱动基板11远离发光元件12的一侧。此时，第一透光开口15也位于相邻的彩色滤光片13之间。
如图1所示，显示基板10发出的光线可照射到手指50上，经过手指50的反射后的光线可通过第一透光开口15射入光学指纹传感器20；光学指纹传感器20可对手指进行成像，从而实现指纹识别。然而，如图2所示，在该显示基板10进行显示时，由于第一透光开口15的存在，发光元件12发出的光线部分可通过第一透光开口15射出，形成杂散光，影响正常显示。
对此，为了在实现光学指纹识别的同时消除上述的杂散光，本公开实施例提供一种显示基板和显示装置。该显示基板包括驱动基板、多个发光元件、彩膜层、第一透光开口、光学胶层和盖板；多个发光元件位于驱动基板上；彩膜层位于多个发光元件远离驱动基板的一侧，且包括多个彩色滤光片和位于相邻的彩色滤光片之间的黑矩阵；第一透光开口位于黑矩阵之中；光学胶层位于彩膜层远离驱动基板的一侧；盖板位于光学胶层远离光学胶层的一侧，多个发光元件与多个彩色滤光片一一对应设置，一个发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的距离为垂直距离a，与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离为横向距离b，垂直距离a和横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000006
其中，n1为盖板的折射率，n2为空气的折射率。
在本公开实施例提供的显示基板中，通过控制发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的垂直距离和与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离，该显示基板可限制杂散光 的出射角度，并使得杂散光在显示基板与空气的界面处发生折射，从而使得杂散光的出光角度较大，从而可避免杂散光影响正常显示。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图3为本公开一实施例提供的一种显示基板的结构示意图。如图3所示，该显示基板100包括驱动基板110、多个发光元件120、彩膜层130、第一透光开口140、光学胶层150和盖板160；多个发光元件120位于驱动基板110上；彩膜层130位于多个发光元件120远离驱动基板110的一侧，且包括多个彩色滤光片132和位于相邻的彩色滤光片132之间的黑矩阵135；第一透光开口140位于黑矩阵135之中；例如第一透光开口140贯穿黑矩阵135，使得光线可通过第一透光开口140穿过黑矩阵125。光学胶层150位于彩膜层130远离驱动基板110的一侧；盖板160位于光学胶层150远离彩膜层130的一侧。
如图3所示，多个发光元件120与多个彩色滤光片132一一对应设置，以使得发光元件120发出的光的大部分可通过对应的彩色滤光片132射出。一个发光元件120与对应的彩色滤光片132在垂直于驱动基板110的方向上的距离为垂直距离a，与对应的彩色滤光片132相邻的第一透光开口140的边缘在平行于驱动基板110的方向上的距离为横向距离b，垂直距离a和横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000007
其中，n1为盖板的折射率，n2为空气的折射率。
在本公开实施例提供的显示基板中，通过控制发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的垂直距离和与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离，该显示基板可限制杂散光的出射角度，并使得杂散光在显示基板与空气的界面处发生折射，从而使得杂散光的出光角度较大。此时，使用者在较大的视角范围(例如120度)内无法看到杂散光，从而可避免杂散光影响正常显示。
另一方面，由于多个发光元件与多个彩色滤光片一一对应设置，以使得发光元件发出的光的大部分可通过对应的彩色滤光片射出，因此该显示基板可利用彩色滤光片来进一步提高不同颜色子像素(一个子像素可包括一个发光元件 和对应的彩色滤光片)的出光的纯度，从而提高显示色域。另一方面，该显示基板还可利用彩膜层实现防反光的作用，从而可取消设置偏光片，减少光的损失，进而可降低功耗并提待机时长。
图4为本公开一实施例提供的另一种显示基板的结构示意图。如图4所示，该显示基板100包括驱动基板110、多个发光元件120、彩膜层130、第一透光开口140、光学胶层150和盖板160。多个发光元件120位于驱动基板110上；彩膜层130位于多个发光元件120远离驱动基板110的一侧，且包括多个彩色滤光片132和位于相邻的彩色滤光片132之间的黑矩阵135；第一透光开口140位于黑矩阵135之中；例如第一透光开口140贯穿黑矩阵135，使得光线可通过第一透光开口140穿过黑矩阵125。光学胶层150位于彩膜层130远离驱动基板110的一侧；盖板160位于光学胶层150远离彩膜层130的一侧。
如图4所示，多个发光元件120与多个彩色滤光片132一一对应设置，以使得发光元件120发出的光的大部分可通过对应的彩色滤光片132射出。此时，一个发光元件120与对应的彩色滤光片132在垂直于驱动基板110的方向上的距离为垂直距离a，与对应的彩色滤光片132相邻的第一透光开口140的边缘在平行于驱动基板110的方向上的距离为横向距离b，垂直距离a和横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000008
在该示例提供的显示基板中，通过控制发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的垂直距离和与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离，该显示基板可限制杂散光的出射角度，并使得杂散光在显示基板与空气的界面处发生全反射，从而使得杂散光无法出射，从而可避免杂散光影响正常显示。
在一些示例中，上述的垂直距离a和横向距离b满足以下公式：
Figure PCTCN2022108280-appb-000009
在该示例提供的显示基板中，通过控制发光元件与对应的彩色滤光片在垂直于驱动基板的方向上的垂直距离和与对应的彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的距离，该显示基板可限制杂散光的出射角度，并使得杂散光在显示基板与空气的界面处发生全反射，从而使得杂散光 无法出射，从而可避免杂散光影响正常显示。
在一些示例中，驱动基板110可包括玻璃基板、石英基板、塑料基板等刚性衬底，也可包括聚酰亚胺基板等柔性衬底。另外，驱动基板也可为硅基半导体基板。
在一些示例中，除了上述的衬底，驱动基板110也可包括用于驱动发光元件120进行发光的像素驱动电路、数据线、电源线等结构。这些结构可参见通常设计，本公开实施例在此不再赘述。
在一些示例中，如图3和图4所示，显示基板100还可包括封装层170，封装层170位于多个发光元件120远离驱动基板110的一侧；此时，彩膜层130设置在封装层170远离驱动基板的一侧。由此，该显示基板通过封装层形成平坦的表面，从而便于形成上述的彩膜层130，并提高彩色滤光片132与对应的发光元件120之间的对位精度。
在一些示例中，盖板160的折射率小于等于1.55。由此，当使用者在采用该显示基板的显示装置的表面贴附保护膜时，由于盖板的折射率小于等于1.55，该显示基板可避免杂散光在盖板与保护膜的界面处发生折射后出射角度变小。
在一些示例中，如图3和图4所示，多个发光元件120包括第一发光元件130A、第二发光元件120B和第三发光元件120C，多个彩色滤光片132包括第一滤光片132A、第二滤光片132B和第三滤光片132C；第一滤光片132A被配置为允许第一颜色的光透过，第二滤光片132B被配置为允许第二颜色的光透过，第三滤光片132C被配置为允许第三颜色的光透过，第一发光元件120A与第一滤光片132A对应设置，第二发光元件120B与第二滤光片132B对应设置，第三发光元件120C与第三滤光片132C对应设置。由此，该显示基板可利用第一彩色滤光片来进一步提高第一发光元件的出光的纯度，利用第二彩色滤光片来进一步提高第二发光元件的出光的纯度，利用第三彩色滤光片来进一步提高第三发光元件的出光的纯度。从而该显示基板可提高显示色域。
在一些示例中，第一发光元件130A被配置为发第一颜色的光，第二发光元件120B被配置为发第二颜色的光，第三发光元件120C被配置为发第三颜色的光。当然，本公开实施例包括但不限于此，第一发光元件、第二发光元件和第三发光元件也可发白光。
在一些示例中，第一颜色为红色，第二颜色为绿色，第三颜色为蓝色。当 然，本公开实施例包括但不限于此。
在一些示例中，如图3和图4所示，一个第一发光元件120A与对应的第一彩色滤光片132A在垂直于驱动基板110的方向上的距离为第一垂直距离a1，与对应的第一彩色滤光片132A相邻的第一透光开口140的边缘在平行于驱动基板的方向上的距离为第一横向距离b1；一个第二发光元件120B与对应的第二彩色滤光片132B在垂直于驱动基板110的方向上的距离为第二垂直距离a2，与对应的第二彩色滤光片132B相邻的第一透光开口140的边缘在平行于驱动基板110的方向上的距离为第二横向距离b2；一个第三发光元件120C与对应的第三彩色滤光片132C在垂直于驱动基板110的方向上的距离为第三垂直距离a3，与对应的第三彩色滤光片132C相邻的第一透光开口140的边缘在平行于驱动基板110的方向上的距离为第三横向距离b3；第一横向距离b1、第二横向距离b2和第三横向距离b3互不相同。
在该示例提供的发光基板中，由于不同颜色的光的波长不同，因此不同颜色的光在盖板的折射率也会有一定的差异，通过将第一横向距离b1、第二横向距离b2和第三横向距离b3设置互不相同，该显示基板可使得不同颜色的子像素采用不同的横向距离，从而可更合理地使用该显示基板上的空间。
在一些示例中，由于人眼对于绿色光线比较敏感，因此该显示基板可首先保证绿色杂散光的出射角度较大或者在盖板和空气的界面发生全反射。
在一些示例中，上述的第一垂直距离a1、第一横向距离b1、第二垂直距离a2、第二横向距离b2、第三垂直距离a3和第三横向距离b3满足以下公式：
Figure PCTCN2022108280-appb-000010
在该示例提供的显示基板中，通过使得a1、b1、a2、b2、a3和b3满足上述大小关系，该显示基板可在保证各种颜色的杂散光不影响正常显示的前提下，尽可能合理地利用显示基板上的面积。例如，可使得第一发光元件与对应的第一彩色滤光片相邻的第一透光开口的边缘在平行于驱动基板的方向上的第一横向距离b1设置地较小，并增大对应的第一彩色滤光片相邻的第一透光开口的尺寸，从而在保证各种颜色的杂散光不影响正常显示的前提下，增加第一透光开口的面积，从而增加光学指纹识别传感器的进光量，进而提高指纹识别的性能。
在一些示例中，如图3和图4所示，第一彩色滤光片132A和第二彩色滤 光片132B之间的第一透光开口140的尺寸大于第一彩色滤光片132A和第三彩色滤光片132C之间的第一透光开口140的尺寸。由于上述的第一横向距离b1和第二横向距离b2可设置得比第三横向距离b3小，因此第一彩色滤光片和第二彩色滤光片之间的第一透光开口的尺寸可大于第一彩色滤光片和第三彩色滤光片之间的第一透光开口的尺寸。
在一些示例中，如图3和图4所示，所述第一彩色滤光片和所述第二彩色滤光片之间的所述第一透光开口的尺寸大于所述第二彩色滤光片和所述第三彩色滤光片之间的所述第一透光开口的尺寸。由于上述的第一横向距离b1和第二横向距离b2可设置得比第三横向距离b3小，因此第一彩色滤光片和第二彩色滤光片之间的第一透光开口的尺寸可大于第二彩色滤光片和第三彩色滤光片之间的第一透光开口的尺寸。
在一些示例中，上述的第一垂直距离a1、第一横向距离b1、第二垂直距离a2、第二横向距离b2、第三垂直距离a3和第三横向距离b3满足以下公式：
Figure PCTCN2022108280-appb-000011
在一些示例中，各发光元件120包括阳极121、有机发光层122和阴极123。由此，该发光元件120可为有机发光元件。需要说明的是，各发光元件还可包括用于辅助发光的辅助功能层，例如电子传输层、空穴传输层等。
在一些示例中，如图3和图4所示，该显示基板100还可包括光学传感器180；该光学传感器180位于驱动基板110远离发光元件120的一侧。由此，光学传感器可通过第一透光开口射入的光线实现各种功能，例如指纹识别、面部识别、距离感应等。
在一些示例中，上述的光学传感器可包括光学指纹识别传感器、面部识别传感器、红外传感器和距离传感器中的至少一种。
例如，当上述的光学传感器为光学指纹识别传感器时，经过手指或指纹反射的光线可通过第一透光开口射入光学指纹识别传感器中，从而实现指纹识别功能。
在一些示例中，如图3和图4所示，第一透光开口140在驱动基板110上的正投影落入光学指纹识别传感器180在驱动基板110上的正投影之内。
图5为本公开一实施例提供的一种显示基板的平面示意图。如图5所示，该显示基板100包括显示区101和围绕显示区101的非显示区102；显示区101 包括指纹识别区101A和位于指纹识别区101A之外的正常显示区101B；第一透光开口140位于指纹识别区101。
图6为本公开一实施例提供的一种显示基板的部分截面示意图，图7为本公开一实施例提供的一种显示基板中的遮光层的部分平面示意图。如图6和图7所示，驱动基板110包括衬底基板111、遮光层S、像素驱动电路层112和像素界定层PDL；遮光层S设置在衬底基板111上，且包括多个第二透光开口S1；像素驱动电路层112设置在遮光层S远离衬底基板111的一侧；像素界定层PDL设置在像素驱动电路层112远离衬底基板111的一侧且包括多个子像素开口113。像素驱动电路层112包括多个像素驱动电路1120，多个像素驱动电路1120与多个发光元件120电性相连，并被配置为驱动多个发光元件120进行发光，多个发光元件120设置在多个子像素开口113之中，并与多个像素驱动电路1120形成多个子像素200；多个第二透光开口S1中的至少部分在衬底基板110上的正投影与第一透光开口140在衬底基板110上的正投影交叠。
例如，每个像素驱动电路1120包括薄膜晶体管TFT和存储电容(未示出)等结构，例如可以形成为3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C等结构，稍后详述。例如，如图6所示，薄膜晶体管TFT包括有源层112A、栅极112G、第一极112D和第二极112S等结构。发光元件120包括第一电极121、发光材料层122以及第二电极123。例如，第一电极121作为阳极，与薄膜晶体管TFT的第一极112D电连接。发光材料层122包括有机发光材料，配置为发出单色光或者白光。第二电极123作为阴极，例如形成为面电极，也即，多个子像素的第二电极123连续设置为面状，以整体覆盖衬底基板111；或者，在一些实施例中，在显示基板需要提高透光率的位置，第二电极123可以具有与第一电极121正对的图案，也即第二电极123图案化，以提高显示基板在该位置的透光率。
例如，如图6所示，多个第二透光开口S1在衬底基板111上的正投影分别位于多个子像素开口113中相邻的子像素开口113在衬底基板111上的正投影之间；多个第二透光开口S1中的至少部分在衬底基板110上的正投影与第一透光开口140在衬底基板110上的正投影交叠。
例如，遮光层S的材料可以为铜、铝等金属材料或者合金材料，或者，在一些实施例中，遮光层S也可以为采用树脂材料中添加黑色染料形成的遮光层，以充分实现遮光效果。
本公开的实施例中，遮光层S可以在第二透光开口S1处透过用于指纹识别的信号光，并且在其他位置遮挡显示基板的发光元件120发出的光以及环境光等非信号光，以避免非信号光照射到设置在显示基板非显示侧的光学传感器，由此可以提升光学传感器的识别速度和准确性。
例如，在一些实施例中，如图6所示，显示基板还包括设置在发光元件120的远离衬底基板111一侧的黑矩阵135。
图8为本公开至少一实施例提供的显示基板中遮光层与黑矩阵叠层的部分平面示意图；图9为本公开至少一实施例提供的显示基板中遮光层、黑矩阵与彩色滤光片叠层的部分平面示意图。例如，图8示出了显示基板的黑矩阵135叠层在遮光层S上的示意图，图9示出了显示基板的黑矩阵135、像素界定层PDL和彩色滤光片132叠层的示意图。
例如，如图8和图9所示，多个子像素开口113在衬底基板111上的正投影分别与多个彩色滤光片132在衬底基板111上的正投影至少部分交叠，例如，多个子像素开口113在衬底基板111上的正投影分别位于多个彩色滤光片132在衬底基板111上的正投影内部。
例如，如图9所示，子像素开口113在衬底基板111上的正投影与彩色滤光片132在衬底基板111上的正投影的距离b(b1)为1微米-6.5微米，例如1微米-5微米，例如1微米-3.5微米，例如1微米-2微米，例如1.0微米、1.2微米、1.5微米、1.7微米或者2.0微米等。
例如，如图8和图9所示，多个第一透光开口140分别设置在多个彩色滤光片132中相邻的彩色滤光片132之间，多个第二透光开口S1中的至少部分第二透光开口S1在衬底基板111上的正投影分别与多个第一透光开口140在衬底基板111上的正投影至少部分交叠。
由此，第二透光开口S1与第一透光开口140形成套孔，以透过例如用于指纹识别的信号光，此时，衬底基板111的远离发光元件120的一侧可以设置光学传感器180(或者摄像头、距离传感器、红外传感器等传感器)，该光学传感器180可以接收通过第一透光开口140和第二透光开口S1的信号光来进行纹路采集与识别功能。
例如，在一些实施例中，像素驱动电路层包括多个金属层，例如上述栅极112G、第一极112D、第二极112S等所在的金属层，这些金属层构成的电路图案在衬底基板111上的正投影与多个第二透光开口S1在衬底基板111上的正 投影不交叠，也与第一透光开口140在衬底基板111上的正投影不交叠，以避免电路图案影响信号光的传输。
例如，如图8所示，多个第二透光开口S1中的至少部分第二透光开口S1在衬底基板111上的正投影分别位于多个第一透光开口140在衬底基板111上的正投影内部。
图10示出了一个第二透光开口S1与对应的第一透光开口140的叠层的示意图，如图10所示，多个第二透光开口S1中的至少部分在衬底基板111上的正投影的边界分别与多个第一透光开口140在衬底基板111上的正投影的边界的距离L3为0.5微米-1.5微米，例如0.8微米、1.0微米、1.2微米或者1.5微米等。
例如，在一些实施例中，如图6和图9所示，多个子像素包括第一子像素R、第二子像素G和第三子像素B，多个彩色滤光片132包括第一滤光片132A、第二滤光片132B以及第三滤光片132C。
第一子像素R的子像素开口113在衬底基板111上的正投影位于第一滤光片132A在衬底基板111上的正投影内，从而第一子像素R的发光元件发出的光可以通过第一滤光片132A出射。第二子像素G的子像素开口113在衬底基板111上的正投影位于第二滤光片132B在衬底基板111上的正投影内，从而第二子像素G的发光元件发出的光可以通过第二滤光片132B出射。第三子像素B的子像素开口113在衬底基板111上的正投影位于第三滤光片132C在衬底基板111上的正投影内，从而第三子像素B的发光元件发出的光可以通过第三滤光片132C出射。
例如，如图9所示，多个第一透光开口140中的至少部分位于相邻的第一子像素R和第三子像素B对应的彩色滤光片132之间，且与第一子像素R对应的彩色滤光片132的最小距离为第一距离D1，与第三子像素B对应的彩色滤光片132的最小距离为第二距离D2，第一距离D1不同于第二距离D2。例如，第一距离D1小于第二距离D2，也即位于相邻的第一子像素R和第三子像素B之间的第一透光开口140更靠近第三子像素B。
例如，如图9所示，第一子像素R和第三子像素B排列为多行多列，位于同一列的多个第一子像素R和多个第三子像素B交替排列，且位于同一列的相邻的第一子像素R和第三子像素B对应的彩色滤光片132之间设置一个第一透光开口140，也即第一透光开口140设置在列方向上相邻的第一子像素 R和第三子像素B的彩色滤光片132之间。
例如，图9还示出了第三子像素B对应的子像素开口113、彩色滤光片132、第三滤光片132C以及邻近的第一透光开口140的放大示意图，图9中的其他方框区域示出的结构与该放大部分的结构基本相同。如图4所示，对于第三子像素B对应的子像素开口113和第三滤光片132C，子像素开口113在衬底基板111上的正投影位于第三滤光片132C在衬底基板111上的正投影内部，且子像素开口113在衬底基板111上的正投影的边界与第三滤光片132C在衬底基板111上的正投影的边界在靠近邻近的第一透光开口140一侧的距离b+d小于在远离该第一透光开口140一侧的距离b1+e，也即第三滤光片132C向远离第一透光开口140的方向偏移，以避免在制备过程中由于对位误差第三滤光片132C覆盖到第一透光开口140。
例如，如图9所示，对于第三子像素B对应的子像素开口113和彩色滤光片132，子像素开口113在衬底基板111上的正投影位于彩色滤光片132在衬底基板111上的正投影内部，且子像素开口113在衬底基板111上的正投影的边界与彩色滤光片132在衬底基板111上的正投影的边界在靠近第一透光开口140一侧的距离b小于在远离该第一透光开口140一侧的距离b1，也即彩色滤光片132也向远离第一透光开口140的方向偏移。例如，在一些实施例中，b为0.5微米-1.5微米，例如1.0微米，b1为1.0微米-2.0微米，例如1.5微米；或者b为1.2微米，b1为1.7微米等。
例如，如图9所示，对于第三子像素B对应的彩色滤光片132以及邻近的第一透光开口140，彩色滤光片132在衬底基板111上的正投影的边界与第一透光开口140在衬底基板111上的正投影的边界的距离a大于等于4微米，若彩色滤光片132和第一透光开口140距离太小，一方面会有发光元件120发出的光漏进第一透光开口140中形成干扰，另一方面在制备过程中彩膜层在彩色滤光片132和第一透光开口140处容易打通，从而难以形成分离的彩色滤光片132和第一透光开口140。
例如，如图9所示，对于第三子像素B对应的第三滤光片132C以及邻近的第一透光开口140，第三滤光片132C在衬底基板111上的正投影的边界与第一透光开口140在衬底基板111上的正投影的边界的距离c大于等于0，例如大于0.5微米，从而第三滤光片132C不会遮盖第一透光开口140，以避免对第一透光开口140透过的信号光造成干扰。
例如，如图9所示，对于第三子像素B对应的第三滤光片132C以及彩色滤光片132，在靠近第一透光开口140的一侧，第三滤光片132C在衬底基板111上的正投影的边界与彩色滤光片132在衬底基板111上的正投影的边界的距离d大于等于2微米，也即第三滤光片132C超出彩色滤光片132大于等于2微米的距离，以增大第三滤光片132C与黑矩阵135的接触面积，避免第三滤光片132C从彩色滤光片132处剥离(Peeling)。例如，在远离第一透光开口140的一侧，第三滤光片132C在衬底基板111上的正投影的边界与彩色滤光片132在衬底基板111上的正投影的边界的距离e大于等于3微米，大于上述d。由此，在制备过程中，一旦因d值较小导致第三滤光片132C从彩色滤光片132处剥离时，可将第三滤光片132C整体移动增大d值来改善剥离现象，并保证生产能够继续进行。
例如，如图9所示，对于第一子像素R对应的子像素开口113和第一滤光片132A，子像素开口113在衬底基板111上的正投影位于第一滤光片132A在衬底基板111上的正投影内部，且子像素开口113在衬底基板111上的正投影的边界与第一滤光片132A在衬底基板111上的正投影的边界在靠近第一透光开口140一侧的距离f基本等于在远离该第一透光开口140一侧的距离g。
例如，如图9所示，一个第一子像素R、两个第二子像素G和一个第三子像素B组成一个重复单元，多个重复单元阵列排布，多个重复单元中的多个第二子像素G排列为多行多列，第一透光开口140还设置在行方向上相邻的第二子像素G对应的彩色滤光片132之间。例如，第一透光开口140与在行方向上相邻的第二子像素G对应的彩色滤光片132的距离基本形同。
例如，在一些实施例中，第一子像素R为红色子像素，第二子像素G为绿色子像素，第三子像素B为蓝色子像素；第一滤光片132A为红色滤光片，第二滤光片132B为绿色滤光片，第三滤光片132C为蓝色滤光片。
或者，在另一些实施例中，第一子像素R也可以为绿色子像素或者蓝色子像素，第二子像素G也可以为红色子像素或者蓝色子像素，第三子像素B也可以为红色子像素或者绿色子像素。此时，各个子像素上设置相应颜色的彩色滤光片。
例如，在一些实施例中，如图8和图9所示，每一个重复单元(例如图9中四边形虚线框所示)对应设置两个第二透光开口S1以及两个第一透光开口140；该两个第二透光开口S1在衬底基板111上的正投影应分别位于该两个第 一透光开口140在衬底基板111上的正投影内。
例如，在其他实施例中，每一个重复单元对应设置两个第二透光开口S1，每一个重复单元或者每多个重复单元对应设置一个第一透光开口140，此时，多个第二透光开口S1中的部分第二透光开口S1在衬底基板111上的正投影应分别位于多个第一透光开口140在衬底基板111上的正投影内。也即，在上述实施例中，部分第二透光开口S1与第一透光开口140形成套孔，以用于透过信号光，而其他第二透光开口S1不用于透过信号光。在该实施例中，由于第一透光开口140的数量相比于第二透光开口S1较少，第一透光开口140的位置相对可以灵活设置，此时，在一些实施例中，第三子像素B对应的第三滤光片132C也可以不进行如图9所示的偏移设置。
例如，如图6所示，显示基板还包括设置在像素界定层PDL的远离衬底基板111一侧的隔垫物层190，隔垫物层190包括多个隔垫物PS。多个隔垫物PS可以在显示基板的制备过程中支撑例如掩模板等装置。
图11示出了多个隔垫物的平面排布示意图。如图11所示，在一些实施例中，多个隔垫物PS在衬底基板111上的正投影分别位于在列方向上相邻的第二子像素G的子像素开口113在衬底基板111上的正投影之间，且分别位于在行方向上相邻的第一子像素R和第三子像素G的子像素开口113在衬底基板111上的正投影之间。
例如，在一些实施例中，多个隔垫物PS与多个子像素开口113的最小距离为L，且1微米＜L＜8微米，例如，L为2微米、4微米、6微米或者8微米等。由此，多个隔垫物PS与多个子像素开口113相隔一定的距离，由于子像素开口113的侧壁通常具有一定的倾斜角度，若多个隔垫物PS与多个子像素开口113的距离过近，隔垫物PS可能形成在子像素开口113的侧壁上，从而降低了隔垫物PS相对于衬底基板111的高度，难以实现充分的隔垫作用。
例如，在一些实施例中，如图11所示，多个隔垫物PS中至少部分隔垫物PS的平面形状为矩形。例如，矩形的长L1和宽W1的尺寸范围为13微米-19微米，例如，长L1可以为15微米、17微米或者19微米等，宽W1可以为13微米、15微米或者17微米等，在一些实施例中，至少部分隔垫物PS的平面形状也可以为正方形，此时，正方形的边长可以为12微米、15微米、17微米或者19微米等。
例如，在另一些实施例中，多个隔垫物PS中至少部分隔垫物PS的平面形 状也可以为圆形，此时，圆形的直径可以为13微米-19微米，例如15微米或者17微米等；或者，在再一些实施例中，多个隔垫物PS可以包括主隔垫物和副隔垫物，主隔垫物和副隔垫物的平面形状均可以为圆形，此时，主隔垫物和副隔垫物的圆形的直径之和可以为13微米-19微米，例如15微米或者17微米等。
例如，如图6所示，在垂直于衬底基板111的方向上，也即图中的竖直方向上，多个隔垫物PS的高度为0.5微米-2.0微米，例如1.0微米或者1.5微米等，以充分实现隔垫作用。
例如，如图11所示，多个隔垫物PS的每个在衬底基板111上的正投影与相邻的第一子像素R和第三子像素B中的第一子像素R的子像素开口113在衬底基板111上的正投影的最短距离L11大于与相邻的红色子像素R和蓝色子像素B中的第三子像素B的子像素开口113在衬底基板111上的正投影的最短距离L12，也即相邻的第一子像素R和第三子像素B之间设置的隔垫物PS相比于第一子像素R的子像素开口113，更靠近第三子像素B的子像素开口113。
例如，在一些实施例中，如图11所示，多个隔垫物PS的每个在衬底基板111上的正投影与相邻的第二子像素G的子像素开口113在衬底基板111上的正投影的最短距离L13基本相同，也即相邻的第二子像素G之间设置的隔垫物PS与该相邻的第二子像素G的子像素开口113的距离基本相同。
例如，在一些实施例中，隔垫物层190的材料的透光率小于5％，例如小于2％。例如，多个隔垫物PS可以采用黑色不透光材料形成，例如在树脂材料中掺杂黑色染料形成的黑色不透光材料，该材料对光有很好的吸收效果，因此在外界环境光照射在隔垫物PS上，外界环境光不会被反射而是被吸收，因此可以减弱色分离现象甚至消除色分离现象。
例如，在一些实施例中，像素界定层PDL的材料的透光率小于5％，例如小于2％。例如，像素界定层PDL的材料可以与多个隔垫物PS的材料相同，由此在制备工艺中可以采用半色调掩模板在相同的构图工艺中形成，或者，二者也可以采用相同或者不同的材料分别形成。
由此，当有外界环境光照射在像素界定层PDL上，外界环境光也不会被像素界定层PDL反射，因此可以进一步减弱色分离现象甚至消除色分离现象。
例如，如图6所示，显示基板还包括设置在发光元件120的远离衬底基板111一侧的封装层170，黑矩阵135设置在封装层170的远离衬底基板111的 一侧。例如，封装层170可以为复合封装层，包括依次设置在发光元件120上的第一无机封装层、第一有机封装层和第二无机封装层(图中未示出)，以提高封装效果。
例如，在一些实施例中，用于多个子像素的彩色滤光片可以设置在复合封装层中，例如复合封装层中相邻的两个子封装层之间。例如，在一个示例中，复合封装层包括依次设置在发光元件120上的第一无机封装层、第一有机封装层和第二无机封装层，此时，彩色滤光片可以设置在第一无机封装层和第二无机封装层之间。
例如，在一些实施例中，如图6所示，显示基板还包括设置在封装层170的远离衬底基板111的一侧的触控层FM，黑矩阵135设置在触控层FM的远离衬底基板111的一侧。
图12示出了触控层FM的平面示意图，如图6和12所示，触控层FM包括多条触控走线TL，多条触控走线TL在衬底基板111上的正投影与多个第二透光开口S1在衬底基板111上的正投影不交叠。例如，多条触控走线TL在衬底基板111上的正投影与多个彩色滤光片132在衬底基板111上的正投影也不交叠。由此，多条触控走线TL被黑矩阵135遮挡，以避免光照射到触控走线TL而影响触控走线TL的信号传输性能等，并且，触控走线TL也不会遮挡第二透光开口S1和彩色滤光片132，从而避免影响信号光以及发光元件120发出的光的传输。
例如，在一些实施例中，在平行于衬底基板111的同一方向上，多条触控走线TL与第一滤光片132A、第二滤光片132B和第三滤光片132C中至少两个的距离不同。例如，如图12所示，在虚线框位置处，在图中的水平方向上，触控走线TL与第三滤光片132C的距离大于与第一滤光片132A的距离。由于第三滤光片132C的形状、排布不规则，因此在该方向上将触控走线TL与第三滤光片132C的距离设置的较大，可以避免触控走线TL与第三滤光片132C在该方向上交叠，或者交叠尺寸过大。
例如，在一些实施例中，如图12所示，第一子像素R和第三子像素B排列为多行多列，位于同一列的多个第一子像素R和多个第三子像素B交替排列，例如，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有缺口NT1/NT2/NT3。由此，可以避免触控走线TL对多个第一透光开口140的遮挡。
例如，如图12所示，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧或者靠近第一子像素R的一侧具有缺口NT1，此时，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有一个缺口；或者，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧以及靠近第一子像素R的一侧均具有缺口NT2/NT3，此时，多条触控走线TL中的至少部分在位于同一列的相邻的第一子像素R和第三子像素B之间具有两个缺口。由此，可以避免触控走线TL对多个第一透光开口140的遮挡。
例如，在一些实施例中，如图12所示，多条触控走线TL中的至少部分在位于第N列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧或者靠近第一子像素R的一侧均具有缺口NT1，并且多条触控走线TL中的至少部分在位于第N+1列的相邻的第一子像素R和第三子像素B中靠近第三子像素B的一侧以及靠近第一子像素R的一侧均具有缺口NT2/NT3。此时，每相邻的两列第一子像素R和第三子像素B中，其中的一列中相邻的第一子像素R和第三子像素B之间具有一个缺口，另一列中相邻的第一子像素R和第三子像素B之间具有两个缺口。由此，可以避免触控走线TL对多个第一透光开口140的遮挡。
例如，显示基板还可以包括盖板等其他结构，具体可以参考相关技术，这里不再赘述。
图13为本公开一实施例提供的一种显示基板中隔垫物层与彩膜层叠层的平面示意图。参考图6和图13，该显示基板具有多个子像素，多个子像素包括第一子像素R、第二子像素G、第三子像素B；第一子像素R和第三子像素B沿行方向上交替设置形成多行第一像素行，且多行第一像素行中位于同列的第一子像素R和第三子像素B交替设置，第二子像素G沿行方向并排设置形成多行第二像素行。
参考图6，显示基板包括衬底基板111、像素驱动电路层112、像素界定层PDL和黑矩阵135，像素驱动电路层112设置在衬底基板111上，像素界定层PDL设置在像素驱动电路层112的远离衬底基板111的一侧，包括用于多个子像素的多个子像素开口113，其中，多个子像素130中的每个包括设置在像素驱动电路层112中的像素驱动电路以及至少部分设置在子像素开口113中的发 光元件120。
例如，图13示出了黑矩阵135与隔垫物层190叠层的平面示意图。如图13所示，对于一个第一透光开口140以及与该一个第一透光开口140相邻的第一子像素R和第三子像素B对应的彩色滤光片132，相邻的第一子像素R和第三子像素B对应的彩色滤光片132的中心O1和O2的连线C1穿过该一个第一透光开口140。
例如，如图13所示，上述一个第一透光开口140的中心O3与第一子像素R对应的彩色滤光片132的中心O1的距离h1不同于与第三子像素B对应的彩色滤光片132的中心O1的距离h2，例如，h1大于h2，也即第一透光开口140相比于第一子像素R对应的彩色滤光片132更靠近第三子像素B对应的彩色滤光片132。
例如，如图13所示，多个第一透光开口140还分别设置在行方向上相邻的第二子像素G对应的彩色滤光片132之间。
例如，如图13所示，对于一个第一透光开口140以及与该一个第一透光开口140相邻的第二子像素G对应的彩色滤光片132，相邻的第一子像素G对应的彩色滤光片132的中心O4和O5的连线C2穿过该一个第一透光开口140。例如，如图13所示，该一个第一透光开口140的中心O6与相邻的第二子像素G对应的彩色滤光片132的中心O4和O5的距离h3和h4基本相同。
例如，参考图6和9，多个彩色滤光片132包括第一滤光片132A、第二滤光片132B以及第三滤光片132C。
第一子像素R的子像素开口113在衬底基板111上的正投影位于第一滤光片132A在衬底基板111上的正投影内，从而第一子像素R的发光元件发出的光可以通过第一滤光片132A出射。第二子像素G的子像素开口113在衬底基板111上的正投影位于第二滤光片132B在衬底基板111上的正投影内，从而第二子像素G的发光元件发出的光可以通过第二滤光片132B出射。第三子像素B的子像素开口113在衬底基板111上的正投影位于第三滤光片132C在衬底基板111上的正投影内，从而第三子像素B的发光元件发出的光可以通过第三滤光片132C出射。
例如，参考图9，对于与第三子像素B对应的子像素开口113以及第三滤光片132C，子像素开口113在衬底基板111上的正投影的边界与第三滤光片132C在衬底基板111上的正投影的边界在靠近第一透光开口140一侧的距离 b+d小于在远离该第一透光开口140一侧的距离b1+e。对于子像素开口113、彩色滤光片132、第一透光开口140以及第三滤光片132C的其他设置关系，可以参考上述实施例。
例如，第一子像素R为红色子像素，第二子像素G为绿色子像素，第三子像素B为蓝色子像素。
例如，参考图6和图8，显示基板还包括遮光层S，遮光层S设置在衬底基板111和像素驱动电路层112之间，包括多个第二透光开口S1，多个第二透光开口S1中的至少部分在衬底基板111上的正投影分别位于多个第一透光开口140在衬底基板111上的正投影内。
例如，一个第一子像素R、两个第二子像素G和一个第三子像素B组成一个重复单元，多个重复单元阵列排布，多个重复单元中的每个对应设置两个第二透光开口S1。例如，每个第二透光开口S1对应设置一个第一透光开口140，或者在其他实施例中，每两个或多个第二透光开口S1对应设置一个第一透光开口140，具体可以参考上述实施例，这里不再赘述。
例如，该显示基板还可以包括其他结构，例如隔垫物层、封装层、触控层等，具体可以参考上述实施例，这里不再赘述。
例如，在本公开的各个实施例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C结构。
图14为一种8T1C像素驱动电路的等效电路示意图。如图14所示，该像素驱动电路可以包括8个晶体管(第一晶体管T1到第八晶体管T8)、1个存储电容C和多个信号线(例如数据信号线Data、第一扫描信号线Gate、第二扫描信号线GateN、复位控制信号线Reset、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD、第二电源线VSS和发光控制信号线EM等)。
例如，第一晶体管T1的栅极与复位控制信号线Reset连接，第一晶体管T1的第一极与第二初始信号线INIT2连接，第一晶体管T1的第二极与第五节点N5连接。第二晶体管T2的栅极与第一扫描信号线Gate连接，第二晶体管T2的第一极与第五节点N5连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的栅极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅极与第一扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5 的栅极与发光控制信号线EM连接，第五晶体管T5的第一极与第一电源线
VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅极与发光控制信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4(即发光元件的第一极)连接。第七晶体管T7的栅极与第一扫描信号线Gate或者复位控制信号线Reset连接，第七晶体管T7的第一极与第一初始信号线INIT1连接，第七晶体管T7的第二极与第四节点N4连接。第八晶体管T8的栅极与第二扫描信号线GateN连接，第八晶体管T8的第一极与第五节点N5连接，第八晶体管T8的第二极与第一节点N1连接。存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些实施例中，第一晶体管T1到第七晶体管T7可以是N型薄膜晶体管，第八晶体管T8可以是P型薄膜晶体管；或者，第一晶体管T1到第七晶体管T7可以是P型薄膜晶体管，第八晶体管T8可以是N型薄膜晶体管。
在一些实施例中，第一晶体管T1到第七晶体管T7可以是低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)，第八晶体管T8可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管。
在上述实施例中，铟镓锌氧化物薄膜晶体管与低温多晶硅薄膜晶体管相比，产生的漏电流更少，因此，将第八晶体管T8设置为铟镓锌氧化物薄膜晶体管，可以显著减少漏电流的产生，从而改善显示面板的低频、低亮度闪烁的问题。此外，第一晶体管T1和第二晶体管T2无需设置为铟镓锌氧化物薄膜晶体管，由于低温多晶硅薄膜晶体管的尺寸一般都要小于铟镓锌氧化物薄膜晶体管，因此，本公开实施例的像素驱动电路的占用空间会比较小，利于提高显示面板的分辨率。
本公开实施例提供的上述像素驱动电路，集合了LTPS-TFT的良好开关特性和Oxide-TFT的低漏电特性，可以实现低频驱动(1Hz～60Hz)，大幅降低显示屏功耗。
在一些实施例中，发光元件的第二电极与第二电源线VSS连接，第二电源线VSS的信号为持续提供低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线Gate的信号为本显示行像素驱动电路中的扫描信号，复位控制信号线Reset的信号为上一显示行像素驱动电路中的扫描信号， 即对于第n显示行，第一扫描信号线Gate为Gate(n)，复位控制信号线Reset为Gate(n-1)，本显示行的复位控制信号线Reset的信号与上一显示行像素驱动电路中的第一扫描信号线Gate的信号可以为同一信号，以减少显示面板的信号线，实现显示面板的窄边框。
在一些实施例中，第一扫描信号线Gate、第二扫描信号线GateN、复位控制信号线Reset、发光控制信号线EM、第一初始信号线INIT1和第二初始信号线INIT2均沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线DATA均沿竖直方向延伸。
在一些实施例中，第一初始信号线INIT1，第二初始信号线INIT2，第二电源线VSS、第一电源线VDD的至少部分可以为网状结构，即同时包含水平方向延伸和竖直方向延伸的部分。
图15为一种像素驱动电路的工作时序图。下面通过图14示例的像素驱动电路的工作过程说明本公开示例性实施例，图14中的像素驱动电路包括8个晶体管(第一晶体管T1到第八晶体管T8)和1个存储电容C，本实施例以第一晶体管T1到第七晶体管T7为P型晶体管，第八晶体管T8为N型晶体管，第七晶体管T7的栅极连接第一扫描信号线Gate为例进行说明。
例如，在一些实施例中，像素驱动电路的工作过程可以如下几个阶段。
第一阶段t1，称为复位阶段，第一扫描信号线Gate、复位控制信号线Reset、第二扫描信号线GateN和发光控制信号线EM的信号均为高电平信号，复位控制信号线Reset的信号为低电平信号。发光控制信号线EM的高电平信号使得第五晶体管T5和第六晶体管T6关闭，第二扫描信号线GateN的高电平信号使得第八晶体管T8导通，复位控制信号线Reset的低电平信号使得第一晶体管T1导通，因此，第一节点N1的电压被复位为第二初始信号线INIT2提供的第二初始电压Vinit2，然后复位控制信号线Reset的电位置高，第一晶体管T1关闭。由于第五晶体管T5和第六晶体管T6关闭，此阶段发光元件EL不发光。
第二阶段t2，称为数据写入阶段，第一扫描信号线Gate的信号为低电平信号，第四晶体管T4、第二晶体管T2和第七晶体管T7导通，数据信号线Data输出数据电压，第四节点N4的电压被复位为第一初始电压线INIT1提供的第一初始电压Vinit1，完成初始化。此阶段由于第一节点N1为低电平，因此第三晶体管T3导通。第四晶体管T4和第二晶体管T2导通使得数据信号线Data 输出的数据电压经过导通的第四晶体管T4、第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2、第五节点N5和第八晶体管T8提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管T3的阈值电压之和充入存储电容C，存储电容C的第二端(第一节点N1)的电压为Vdata+Vth，Vdata为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。发光控制信号线EM的信号为高电平信号，第五晶体管T5和第六晶体管T6关闭，确保发光元件EL不发光。
第三阶段t3，称为发光阶段，第一扫描信号线Gate和复位控制信号线Reset的信号为高电平信号，发光控制信号线EM和第二扫描信号线GateN的信号均为低电平信号。复位控制信号线Reset的高电平信号，使第七晶体管T7关闭，发光控制信号线EM的低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的第一极(即第四节点N4)提供驱动电压，驱动发光元件EL发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(即第三晶体管)的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata+Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdata+Vth-Vdd)-Vth] 2＝K*[(Vdata-Vdd)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线Data输出的数据电压，Vdd为第一电源端VDD输出的电源电压。
由上述公式可以看出，流经发光元件EL的电流I与第三晶体管T3的阈值电压Vth无关，消除了第三晶体管T3的阈值电压Vth对电流I的影响，保证了亮度的均一性。
基于上述工作时序，该像素驱动电路消除了发光元件EL在上次发光后残余的正电荷，实现了对第三晶体管栅极电压的补偿，避免了第三晶体管的阈值电压漂移对发光元件EL驱动电流的影响，提高了显示图像的均匀性和显示面板的显示品质。
本公开实施例的像素驱动电路，通过将第四节点N4初始化为第一初始信号线INIT1的信号，通过将第五节点N5初始化为第二初始信号线INIT2的信 号，能够对发光元件EL的复位电压和第一节点N1的复位电压分别进行调整，从而实现更佳的显示效果，改善低频闪烁等问题。
图16-图27示出了本公开至少一实施例提供的显示基板的各个层依次叠层的平面示意图。
例如，图16示出了遮光层的平面示意图，遮光层包括多个第二透光开口S1。
图17示出了第一半导体层叠层在遮光层后的平面示意图，第一半导体层包括多个薄膜晶体管的有源层。第一半导体层可以采用硅材料，硅材料包括非晶硅和多晶硅；在一些实施例中，第一半导体层可以采用非晶硅a-Si，经过结晶化或激光退火等方式形成多晶硅。
图17中虚线框示出的范围为一个子像素的像素驱动电路的设置范围。如图17所示，第一半导体层可以包括第一晶体管T1的第一有源层10、第二晶体管T2的第二有源层20、第三晶体管T3的第三有源层30、第四晶体管T4的第四有源层40、第五晶体管T5的第五有源层50、第六晶体管T6的第六有源层60和第七晶体管T7的第七有源层70。第一有源层10、第二有源层20、第三有源层30、第四有源层40、第五有源层50、第六有源层60和第七有源层70为相互连接的一体结构。
在一些实施例中，第三有源层30的形状可以呈“几”字形，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的形状可以呈“1”字形。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第一半导体层为镜像对称结构。
在一些实施例中，第三有源层30的沟道区沿行方向延伸，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的沟道区沿列方向延伸。
例如，第二透光开口S1在衬底基板111上的正投影与第六有源层60和第七有源层70在衬底基板111上的正投影相邻，相应地，第一透光开口140在衬底基板111上的正投影与第六有源层60和第七有源层70在衬底基板111上的正投影相邻。
在一些实施例中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体 管可以均为LTPS薄膜晶体管。
例如，图18示出了第一导电层叠层在第一半导体层后的平面示意图。在一些实施例中，如图18所示，第一导电层可以包括：第一扫描信号线Gate_P、复位控制信号线Reset_P、发光控制信号线EM_P和储存电容C的第一极板Ce1。在一些实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第一导电层为镜像对称结构。
在一些实施例中，第一扫描信号线Gate_P、复位控制信号线Reset_P和发光控制信号线EM_P均沿第一方向X延伸。在每个子像素内，复位控制信号线Reset_P位于第一扫描信号线Gate_P远离发光控制信号线EM_P的一侧，存储电容的第一极板Ce1设置在第一扫描信号线Gate_P和发光控制信号线EM_P之间。
例如，像素驱动电路层(例如上述第一导电层)包括相互平行设置且周期排布的第一信号线(例如在一些实施例中为发光控制信号线EM_P)和第二信号线(例如在一些实施例中为复位控制线Reset_P)，第一信号线和第二信号线配置为向多个子像素提供不同的电信号，多个第二透光开口S1在衬底基板111上的正投影分别位于一条第一信号线(例如为发光控制信号线EM_P)在衬底基板111上的正投影和与该一条第一信号线距离最近的一条第二信号线(例如为复位控制线Reset_P)在衬底基板111上的正投影之间。相应地，多个第一透光开口140在衬底基板111上的正投影分别位于一条第一信号线(例如为发光控制信号线EM_P)在衬底基板111上的正投影和与该一条第一信号线距离最近的一条第二信号线(例如为复位控制线Reset_P)在衬底基板111上的正投影之间。
例如，多个子像素包括第一行子像素RO1和与第一行子像素RO1相邻且位于第一行子像素RO1下级的第二行子像素RO2，第一行子像素RO1的像素驱动电路共用一条发光控制信号线EM_P和一条复位控制线Reset_P，第二行子像素RO2的像素驱动电路共用一条发光控制信号线EM_P和一条复位控制线Reset_P，其中，第一行子像素RO1的像素驱动电路共用的发光控制信号线EM_P在衬底基板111上的正投影和第二行子像素RO2的像素驱动电路共用的复位控制线Reset_P在衬底基板111上的正投影之间包括一行第二透光开口S1在衬底基板111上的正投影。相应地，第一行子像素RO1的像素驱动电路共 用的发光控制信号线EM_P在衬底基板111上的正投影和第二行子像素RO1的像素驱动电路共用的复位控制线Reset_P在衬底基板111上的正投影之间包括一行第一透光开口140在衬底基板111上的正投影。
在一些实施例中，第一极板Ce1可以为矩形状，矩形状的角部可以设置倒角，第一极板Ce1在衬底基板111上的正投影与第三晶体管T3的第三有源层30在衬底基板111上的正投影存在重叠区域。在一些实施例中，第一极板Ce1同时作为第三晶体管T3的栅极。
在一些实施例中，复位控制信号线Reset_P与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1的栅极，第一扫描信号线Gate_P与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2的栅极，第一扫描信号线Gate_P与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅极，发光控制信号线EM_P与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅极，发光控制信号线EM_P与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅极。每行子像素的下一行子像素中的复位控制信号线Reset_P(与本行子像素中的第一扫描信号线Gate_P的信号相同)与本行子像素中的第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅极。
例如，图19示出了第二导电层叠层在第一导电层后的平面示意图。如图19所示，第二导电层包括：存储电容C的第二极板Ce2和第二扫描信号线GateN的第一分支GateN_B1。在一些实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第二导电层为镜像对称结构。
在一些实施例中，第二扫描信号线GateN的第一分支GateN_B1沿第一方向X延伸。在每个子像素内，存储电容的第二极板Ce2位于第二扫描信号线GateN的第一分支GateN_B1和发光控制信号线EM_P之间。
在一些实施例中，第二极板Ce2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板Ce2在衬底基板111上的正投影与第一极板Ce1在衬底基板111上的正投影存在重叠区域。第二极板Ce2上设置有开口H，开口H可以位于第二极板Ce2的中部。开口H可以为正六边形，使第二极板Ce2形成环形结构。开口H暴露出覆盖第一极板Ce1的第三绝缘层，且第一极板Ce1在 衬底基板111上的正投影包含开口H在衬底基板111上的正投影。在一些实施例中，开口H配置为容置后续形成的第四过孔，第四过孔位于开口H内并暴露出第一极板Ce1，使后续形成的第八晶体管T8的第二极与第一极板Ce1连接。
例如，图20示出了第二半导体层叠层在第二导电层后的平面示意图。在一些实施例中，如图20所示，每个子像素的第二半导体层可以包括第八晶体管T8的第八有源层80。在一些实施例中，第八有源层80沿第二方向Y延伸，第八有源层80的形状可以呈哑铃形。
在第二方向Y上，任意相邻两列子像素的第二半导体层为镜像对称结构。
在一些实施例中，第二半导体层可以采用氧化物，即第八晶体管为氧化物薄膜晶体管。
例如，图21示出了第三导电层叠层在第二导电层后的平面示意图。如图21所示，第三导电层包括：第二扫描信号线GateN的第二分支GateN_B2和第二初始信号线INIT2。在一些实施例中，第三导电层可以称为第三栅金属(GATE3)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第三导电层为镜像对称结构。
在一些实施例中，第二扫描信号线GateN的第二分支GateN_B2沿第一方向X延伸，第二扫描信号线GateN的第二分支GateN_B2与第一扫描信号线Gate的第二分支Gate_B2靠近。在一些实施例中，第二扫描信号线GateN的第二分支GateN_B2与第八有源层80重叠的区域作为第八晶体管的栅极。
在一些实施例中，第二扫描信号线的第二分支GateN_B2在衬底基板111上的正投影与第二扫描信号线的第一分支GateN_B1在衬底基板111上的正投影交叠。在一些实施例中，第二扫描信号线的第一分支GateN_B1与第二扫描信号线的第二分支GateN_B2可以在周边区域通过信号线连接。
在一些实施例中，第二初始信号线INIT2沿第一方向X延伸，在每行子像素内，第二初始信号线INIT2设置在复位控制信号线Reset_P远离第一扫描信号线Gate_P的一侧。
例如，第二透光开口S1在衬底基板111上的正投影还位于发光控制信号线EM_P以及与该发光控制信号线EM_P最近邻的一条第二初始信号线INIT2在衬底基板111上的正投影之间。相应地，第一透光开口140在衬底基板111 上的正投影还还位于在发光控制信号线EM_P以及与该发光控制信号线EM_P最近邻的一条第二初始信号线INIT2在衬底基板111上的正投影之间。
例如，图22示出了第三导电层上形成的绝缘层中的多个过孔的平面分布图。如图22所示，该绝缘层中设置有多个过孔，多个过孔包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
例如，第一过孔V1暴露出第八有源层80的第二区的表面。第二过孔暴露出第八有源层80的第一区的表面。第三过孔V3暴露出第二有源层的第一区的表面。第三过孔V3配置为使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
第四过孔V4位于第二极板Ce2的开口H内，第四过孔V4在衬底基板111上的正投影位于开口H在衬底基板111上的正投影的范围之内，第四过孔V4暴露出第一极板Ce1的表面。第四过孔V4配置为使后续形成的第三连接电极43与通过该过孔与第一极板Ce1连接。
第五过孔V5暴露出第五有源层的第一区的表面。第五过孔V5配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层连接。
第六过孔V6位于第二极板Ce2所在区域，第六过孔V6在衬底基板111上的正投影位于第二极板Ce2在衬底基板111上的正投影的范围之内，第六过孔V6内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板Ce2的表面。第六过孔V6配置为使后续形成的第五连接电极45通过该过孔与第二极板Ce2连接。
第七过孔V7暴露出第一有源层的第一区的表面。第七过孔V7配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。第八过孔V8暴露出第七有源层的第一区的表面。第八过孔V8配置为使后续形成的第一初始信号线通过该过孔与第七有源层连接。第九过孔V9暴露出第六有源层的第二区的表面。第九过孔V9配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
第十过孔V10暴露出第四有源层的第一区的表面。第十过孔V10配置为使后续形成的第二连接电极42通过该过孔与第四有源层连接。第十一过孔V11暴露出第二初始信号线INIT2的表面。第十一过孔V11配置为使后续形成的第 六连接电极46通过该过孔与第二初始信号线INIT2连接。
图23示出了第四导电层叠层在第三导电层后的平面示意图。如图23所示，第四导电层包括：第一初始信号线INIT1、第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45和第六连接电极46。在一些实施例中，第四导电层可以称为第一源漏金属(SD1)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第四导电层为镜像对称结构。
在一些实施例中，第一初始信号线INIT1沿着第一方向X延伸，第一初始信号线INIT1通过第八过孔V8与第七有源层的第一区连接，使第七晶体管T7的第一极与第一初始信号线INIT1具有相同的电位。
在一些实施例中，第一连接电极41的一端通过第三过孔V3与第二有源层的第一区(也是第一有源层的第二区)连接，另一端通过第二过孔V2与第八有源层的第一区连接。在一些实施例中，第一连接电极41可以作为第八晶体管T8的第一极、第二晶体管的第一极和第一晶体管的第二极。
在一些实施例中，第二连接电极42一方面通过第十过孔V10与第四有源层的第一区连接，另一方面通过后续形成的第十三过孔V13与后续形成的数据信号线Data连接。在一些实施例中，第二连接电极42可以作为第四晶体管T4的第一极。
在一些实施例中，第三连接电极43的一端通过第一过孔V1与第八有源层的第二区连接，其另一端通过第四过孔V4与第一极板Ce1连接。在一些实施例中，第三连接电极43可以作为第八晶体管T8的第二极。
在一些实施例中，第四连接电极44一方面通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)，另一方面，通过后续形成的第十二过孔V12与后续形成的第一电极连接电极连接。在一些实施例中，第四连接电极44可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极。
在一些实施例中，第五连接电极45(电源连接电极)，一方面通过第六过孔V6与第二极板Ce2连接，另一方面通过第五过孔V5与第五有源层的第一区连接，第五连接电极45配置为通过后续形成的第十四过孔V14与后续形成的第一电源线VDD连接。
在一些实施例中，第六连接电极46的一端通过第七过孔V7与第一有源层的第一区连接，另一端通过第十一过孔V11与第二初始信号线连接，使第一晶 体管T1的第一极与第二初始信号线INIT2具有相同的电位。
图24示出了第一平坦化层叠层在第四导电层以及第五导电层叠层在第一平坦化层后的平面示意图。在一些实施例中，如图24所示，第一平坦化层97包括：第十二过孔V12、第十三过孔V13和第十四过孔V14，第五导电层包括：数据信号线Data、第一电源线VDD和第一电极连接电极51。在一些实施例中，第五导电层可以称为第二源漏金属(SD2)层。
在一些实施例中，在第二方向Y上，任意相邻两列子像素的第五导电层为镜像对称结构。在另一些示例性实施方式中，在第二方向Y上，任意相邻两列子像素的第五导电层也可以不为镜像对称结构，可以根据需要增加第一透光开口或第二透光开口下方的第二源漏金属层的面积，以增加上层形成的第一电极(阳极)的平坦度，使得子像素整体位于一个平面上，从而可以降低色偏，提高显示质量。
在一些实施例中，如图24所示，在一个重复单元内，相邻两列子像素中的第一电源线VDD可以为相互连接的一体结构。通过使相邻两列子像素中的第一电源线VDD形成相互连接的一体结构，可以使上层形成的阳极更加平坦。
例如，驱动电路层包括相互平行设置且周期排布的第三信号线(例如上述第一电源线VDD)，第三信号线沿第二方向Y延伸，分别与第一信号线和第二信号线相交，第三信号线配置为向多个子像素提供电源信号，如图18所示，第三信号线包括镂空部OD，第二透光开口S1在衬底基板111上的正投影位于镂空部OD在衬底基板111上的正投影内。相应地，第一透光开口140在衬底基板111上的正投影位于镂空部OD1在衬底基板111上的正投影内。
在一些实施例中，第一电极连接电极51可以为矩形状，第一电极连接电极51通过第十二过孔V12与第四连接电极44连接。
在一些实施例中，第一电源线VDD通过第十四过孔V14与第五连接电极45连接。
在一些实施例中，数据信号线Data沿着第二方向Y延伸，数据信号线Data通过第十三过孔V13与第二连接电极42连接，由于第二连接电极42通过第十过孔V10与第四有源层的第一区连接，因而实现了数据信号线与第四晶体管的第一极的连接，使数据信号线Data传输的数据信号可以写入第四晶体管。
例如，图25示出了第二平坦化层叠层在第五导电层后的平面示意图。在一些实施例中，如图25所示，第二平坦层98包括第十五过孔V15。
在一些实施例中，第十五过孔V15位于第一电极连接电极51所在区域，第十五过孔V15内的第二平坦层被去掉，暴露出第一电极连接电极51的表面，第十五过孔V15配置为使后续形成的第一电极(例如阳极)通过该过孔与第一电极连接电极51连接。
例如，为清楚示出，图26示出了第一电极层的平面示意图。如图26所示，第一电极层包括多个子像素的第一电极121，每个第一电极121包括主体部121A和连接部121B，主体部121A被子像素开口113暴露，连接部121B通分别过第十五过孔V15与第一电极连接电极51。
由于第一电极连接电极51通过第十二过孔V12与第四连接电极44连接，第四连接电极44还通过第九过孔V9与第六有源层连接，因而实现了像素驱动电路可以驱动发光元件发光。
例如，图27示出了像素界定层PDL的平面示意图，如图27所示，像素界定层PDL包括多个子像素开口113，多个子像素开口113的形状与第一电极121的主体部121A的形状基板相同，且尺寸略小于主体部121A的尺寸，以充分暴露主体部121A。
例如，像素界定层PDL上方的隔垫物层190、触控层FM、黑矩阵135以及彩色滤光片的结构以及位置关系可以参见图6、图11、图12以及图13等，这里不再赘述。
在本公开的实施例中，衬底基板111可以是柔性基板，或者可以是刚性基板。刚性基板可以为但不限于玻璃、石英中的一种或多种，柔性基板可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一些实施例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
例如，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中 的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。平坦化层可以采用有机材料，触控层FM的多条走线TL可以采用氧化铟锡ITO或氧化铟锌IZO等金属氧化物材料。第一半导体层可以采用多晶硅(p-Si)，第二半导体层(SML2)可以采用氧化物。
本公开实施例提供的显示基板的叠层结构仅仅是一种示例性说明，在一些实施例中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开的实施例在此不做限定。
图28为本公开一实施例提供的一种第一透光开口和彩色滤光片的层叠示意图；如图28所示，第一透光开口140在衬底基板110上的正投影被第一彩色滤光片132A、第二彩色滤光片132B和第三彩色滤光片132C在衬底基板110上的正投影所包围。
例如，如图28所示，第一透光开口140在衬底基板110上的正投影的形状为圆形；当然，本公开实施例包括但不限于此，第一透光开口在衬底基板上的正投影的形状也可为其他形状，例如矩形。
例如，如图28所示，第一彩色滤光片132A在衬底基板110上的正投影的形状为六边形；第二彩色滤光片132B在衬底基板110上的正投影的形状为六边形；第三彩色滤光片132C在衬底基板110上的正投影的形状为直角对称五边形。当然，本公开实施例包括但不限于此，这些彩色滤光片在衬底基板上的正投影的形状也可为其他形状。
图29为本公开一实施例提供的一种遮光层、第一电极和子像素开口的层叠示意图；如图29所示，第二透光开口S1在衬底基板110上的正投影的形状可为长条形，且该长条形的两端分别包括凸出部。
本公开一实施例还提供一种显示装置。图30为本公开一实施例提供的一种显示装置的示意图。如图30所示，该显示装置300包括上述的显示基板100。由此，该显示装置具有可避免杂散光影响正常显示的同时，还具有较高的色域和较长的待机时间。
例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，包括：
    驱动基板；
    多个发光元件，位于所述驱动基板上；
    彩膜层，位于所述多个发光元件远离所述驱动基板的一侧，且包括多个彩色滤光片和位于相邻的所述彩色滤光片之间的黑矩阵；
    第一透光开口，位于所述黑矩阵之中；
    光学胶层，位于所述彩膜层远离所述驱动基板的一侧；以及
    盖板，位于所述光学胶层远离所述彩膜层的一侧，
    其中，所述多个发光元件与所述多个彩色滤光片一一对应设置，一个所述发光元件与对应的所述彩色滤光片在垂直于驱动基板的方向上的距离为垂直距离a，与对应的彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为横向距离b，所述垂直距离a和所述横向距离b满足以下公式：
    Figure PCTCN2022108280-appb-100001
    其中，n1为所述盖板的折射率，n2为空气的折射率。
  2. 根据权利要求1所述的显示基板，其中，所述垂直距离a和所述横向距离b满足以下公式：
    Figure PCTCN2022108280-appb-100002
  3. 根据权利要求1所述的显示基板，其中，所述垂直距离a和所述横向距离b满足以下公式：
    Figure PCTCN2022108280-appb-100003
  4. 根据权利要求1-3中任一项所述的显示基板，其中，所述盖板的折射率小于等于1.55。
  5. 根据权利要求1-3中任一项所述的显示基板，其中，所述多个发光元件包括第一发光元件、第二发光元件和第三发光元件，所述多个彩色滤光片包括第一滤光片、第二滤光片和第三滤光片，
    所述第一滤光片被配置为允许第一颜色的光透过，所述第二滤光片被配置为允许第二颜色的光透过，所述第三滤光片被配置为允许第三颜色的光透过，所述第一发光元件与所述第一滤光片对应设置，所述第二发光元件与所述第二滤光片对应设置，所述第三发光元件与所述第三滤光片对应设置。
  6. 根据权利要求5所述的显示基板，其中，一个所述第一发光元件与对应的所述第一彩色滤光片在垂直于所述驱动基板的方向上的距离为第一垂直距离a1，与对应的所述第一彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为第一横向距离b1，
    一个所述第二发光元件与对应的所述第二彩色滤光片在垂直于所述驱动基板的方向上的距离为第二垂直距离a2，与对应的所述第二彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为第二横向距离b2，
    一个所述第三发光元件与对应的所述第三彩色滤光片在垂直于所述驱动基板的方向上的距离为第三垂直距离a3，与对应的所述第三彩色滤光片相邻的所述第一透光开口的边缘在平行于所述驱动基板的方向上的距离为第三横向距离b3，
    所述第一横向距离b1、所述第二横向距离b2和所述第三横向距离b3互不相同。
  7. 根据权利要求6所述的显示基板，其中，所述a1、b1、a2、b2、a3和b3满足以下公式：
    Figure PCTCN2022108280-appb-100004
  8. 根据权利要求7所述的显示基板，其中，所述第一彩色滤光片和所述第二彩色滤光片之间的所述第一透光开口的尺寸大于所述第一彩色滤光片和所述第三彩色滤光片之间的所述第一透光开口的尺寸。
  9. 根据权利要求7所述的显示基板，其中，所述第一彩色滤光片和所述第二彩色滤光片之间的所述第一透光开口的尺寸大于所述第二彩色滤光片和所述第三彩色滤光片之间的所述第一透光开口的尺寸。
  10. 根据权利要求7所述的显示基板，其中，所述a1、b1、a2、b2、a3和b3满足以下公式：
    Figure PCTCN2022108280-appb-100005
  11. 根据权利要求5所述的显示基板，其中，所述第一发光元件被配置为发第一颜色的光，所述第二发光元件被配置为发第二颜色的光，所述第三发光元件被配置为发第三颜色的光。
  12. 根据权利要求9所述的显示基板，其中，所述第一颜色为红色，所述第二颜色为绿色，所述第三颜色为蓝色。
  13. 根据权利要求1-3中任一项所述的显示基板，其中，各所述发光元件包括阳极、有机发光层和阴极。
  14. 根据权利要求1-3中任一项所述的显示基板，还包括：
    光学传感器，位于所述驱动基板远离所述发光元件的一侧。
  15. 根据权利要求14所述的显示基板，其中，所述光学传感器包括：光学指纹识别传感器、面部识别传感器、红外传感器和距离传感器中的至少一种。
  16. 根据权利要求14所述的显示基板，其中，所述显示基板包括显示区和围绕所述显示区的非显示区，所述显示区包括指纹识别区和位于所述指纹识别区之外的正常显示区，所述第一透光开口位于所述指纹识别区。
  17. 根据权利要求1-16中任一项所述的显示基板，其中，所述驱动基板包括：
    衬底基板；
    遮光层，设置在所述衬底基板上，包括多个第二透光开口；
    像素驱动电路层，设置在所述遮光层的远离所述衬底基板的一侧；以及
    像素界定层，设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括多个子像素开口，
    其中，所述像素驱动电路层包括多个像素驱动电路，所述多个像素驱动电路与所述多个发光元件电性相连，并被配置为驱动所述多个发光元件进行发光，所述多个发光元件设置在所述多个子像素开口之中，并与所述多个像素驱动电路形成多个子像素；
    所述多个第二透光开口中的至少部分在所述衬底基板上的正投影与所述第一透光开口在所述衬底基板上的正投影交叠。
  18. 根据权利要求17所述的显示基板，其中，所述多个第二透光开口在所述衬底基板上的正投影位于所述多个子像素开口在所述衬底基板上的正投 影之间，所述多个子像素开口在所述衬底基板上的正投影分别与所述多个彩色滤光片在所述衬底基板上的正投影交叠。
  19. 根据权利要求17所述的显示基板，其中，所述多个第二透光开口中的至少部分在所述衬底基板上的正投影位于所述第一透光开口在所述衬底基板上的正投影之内。
  20. 根据权利要求17所述的显示基板，其中，所述像素驱动电路层还包括相互平行设置且周期排布的第一信号线和第二信号线，所述第一信号线和所述第二信号线配置为向所述多个像素驱动电路提供不同的电信号，
    各所述第二透光开口在所述衬底基板上的正投影位于相邻的所述第一信号线和所述第二信号线在所述衬底基板上的正投影之间。
  21. 根据权利要求20所述的显示基板，其中，所述第一信号线为发光控制信号线，所述第二信号线为复位控制线。
  22. 根据权利要求20所述的显示基板，其中，所述驱动电路层包括相互平行设置且周期排布的第三信号线，所述第三信号线分别与所述第一信号线和所述第二信号线相交，所述第三信号线配置为向所述多个像素驱动电路提供电源信号，
    所述第三信号线包括镂空部，各所述第二透光开口在所述衬底基板上的正投影位于所述镂空部在所述衬底基板上的正投影之内。
  23. 根据权利要求22所述的显示基板，其中，所述第一透光开口在所述衬底基板上的正投影与所述第一信号线和所述第二信号线在所述衬底基板上的正投影不交叠，
    所述第一透光开口在所述衬底基板上的正投影位于所述镂空部在所述衬底基板上的正投影内。
  24. 根据权利要求17-23中任一项所述的显示基板，其中，还包括设置在所述像素界定层的远离所述衬底基板一侧的隔垫物层，所述隔垫物层包括多个隔垫物，所述隔垫物层的材料的透光率小于5％。
  25. 一种显示装置，包括根据权利要求1-24中任一项所述的显示基板。
PCT/CN2022/108280 2022-07-27 2022-07-27 显示基板和显示装置 WO2024020864A1 (zh)

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JP2007103027A (ja) * 2005-09-30 2007-04-19 Sanyo Electric Co Ltd 有機エレクトロルミネッセンス表示装置及びその製造方法
CN111599846A (zh) * 2020-05-29 2020-08-28 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
CN111668388A (zh) * 2020-06-23 2020-09-15 京东方科技集团股份有限公司 一种有机发光显示器及其制造方法
CN112861763A (zh) * 2021-02-25 2021-05-28 京东方科技集团股份有限公司 显示基板及显示装置
CN113327966A (zh) * 2021-05-31 2021-08-31 京东方科技集团股份有限公司 一种显示面板及其制备方法
CN215578574U (zh) * 2021-01-26 2022-01-18 京东方科技集团股份有限公司 显示基板以及显示装置
CN114628478A (zh) * 2022-03-18 2022-06-14 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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JP2007103027A (ja) * 2005-09-30 2007-04-19 Sanyo Electric Co Ltd 有機エレクトロルミネッセンス表示装置及びその製造方法
CN111599846A (zh) * 2020-05-29 2020-08-28 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
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