WO2022042041A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2022042041A1
WO2022042041A1 PCT/CN2021/104493 CN2021104493W WO2022042041A1 WO 2022042041 A1 WO2022042041 A1 WO 2022042041A1 CN 2021104493 W CN2021104493 W CN 2021104493W WO 2022042041 A1 WO2022042041 A1 WO 2022042041A1
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Prior art keywords
light
sub
pixel
data line
subsection
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PCT/CN2021/104493
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English (en)
French (fr)
Inventor
韩龙
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京东方科技集团股份有限公司
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Priority to US17/921,986 priority Critical patent/US20230189584A1/en
Publication of WO2022042041A1 publication Critical patent/WO2022042041A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • the present application relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Under-screen fingerprint recognition means that the fingerprint recognition module is integrated inside the display panel, and the finger touches the area corresponding to the screen glass cover and the fingerprint recognition module to realize fingerprint recognition.
  • the current display device with the under-screen fingerprint recognition function still has the problem of low fingerprint recognition sensitivity.
  • the current display device with the fingerprint recognition function under the screen still needs to be improved.
  • the present application proposes a display substrate.
  • the display substrate includes: a base substrate including a display area; a plurality of sub-pixels located in the display area, the sub-pixels include a pixel circuit structure, and the plurality of sub-pixels include first sub-pixels adjacent in a first direction a pixel and a second sub-pixel; a light-shielding layer located between the pixel circuit structure and the base substrate, the light-shielding layer having a light-transmitting hole; a first initialization signal line extending along the first direction; light-emitting The control signal line extends along the first direction; the first power line extends along the second direction, and the first direction intersects the second direction; the first data line extends along the second direction, so the The first data line is connected to the pixel circuit structure of the first sub-pixel; the second data line extends along the second direction, and the second data line is connected to the pixel circuit structure of the second sub-pixel, The first data data
  • the display substrate includes a gate line, a reset control signal line and a second initialization signal line extending along the first direction, and in the second direction, the gate line, the reset control signal line and the The second initialization signal lines are sequentially arranged on the side of the light emission control signal line away from the first initialization signal line, the pixel circuit structure of the first sub-pixel and the pixel circuit structure of the second sub-pixel are respectively connected with the second initialization signal lines.
  • the width of the light-transmitting hole is less than 1/3 of the distance between the first data line and the second data line
  • the pixel circuit structure of the first sub-pixel is It includes a first light-emitting control transistor and a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is located on the first side of the light-emitting control signal line, and the second electrode of the first light-emitting control transistor is located on the first side of the light-emitting control signal line.
  • the second pole of the second light-emitting control transistor is located on the first side of the light-emitting control signal line
  • the first pole of the second light-emitting control transistor is located on the light-emitting control signal line the second side, the first side and the second side are opposite sides of the light-emitting control signal line
  • the light-transmitting hole is located at the first pole of the first light-emitting control transistor and the second between the second poles of the light-emitting control transistor.
  • the width of the light-transmitting hole is 1/3-1/2 of the distance between the first data line and the second data line
  • the light-emitting control signal line including a first subsection, a second subsection and a third subsection
  • the first subsection is located between the second subsection and the third subsection
  • the first subsection is along the first subsection direction
  • the second subsection and the third subsection extend along the second direction
  • at least part of the second subsection is located between the first power line and the
  • the pixel circuit structure of the first sub-pixel includes a first light-emitting control transistor and a second light-emitting control transistor
  • the first electrode of the first light-emitting control transistor is located at the first pole of the first sub-section.
  • the second pole of the first light emission control transistor is located on the second side of the first subsection, and the second pole of the second light emission control transistor is located on the first side of the first subsection, so The first pole of the second light-emitting control transistor is located on the second side of the first sub-section, the first side and the second side are opposite sides of the first sub-section, and the light-transmitting hole located in the area enclosed by the first power supply line, the second subsection, the second pole of the second light-emitting control transistor, the first pole of the first light-emitting control transistor, and the first initialization signal line Inside.
  • At least part of the third subsection is located on the side of the first data line away from the first power line, and the second subsection is located in the second light emitting section
  • the second pole of the control transistor is away from the side of the first power line.
  • the width of the light-transmitting hole is greater than 1/2 of the distance between the first data line and the second data line
  • the light-emitting control signal line includes a first sub- part, a second sub-part and a third sub-part
  • the first sub-part is located between the second sub-part and the third sub-part
  • the first sub-part extends along the first direction
  • the second subsection and the third subsection extend along the second direction, and in the first direction, at least part of the second subsection is located on the first power line and the second data line
  • the active layer in the pixel circuit structure of the first sub-pixel is located in the area surrounded by the first initialization signal line, the second initialization signal line, the first data line, and the second data line
  • the active layer in the first sub-pixel is the first active layer
  • the orthographic projection of the first active layer on the base substrate is related to the gate line and the light emission control
  • the orthographic projection of the signal line on the base substrate has no overlapping area
  • At least part of the third subsection is located between the first data line and the first power line.
  • the reset control signal line includes a fourth sub-portion extending along the first direction and bent portions located at both ends of the fourth sub-portion, and at least part of the fourth sub-portion is located in the first data sub-portion line and the second data line
  • the gate line includes a fifth sub-section, a sixth sub-section and a seventh sub-section
  • the fifth sub-section is located in the sixth sub-section and the seventh sub-section
  • the fifth sub-section extends along the first direction
  • the sixth sub-section and the seventh sub-section extend along the second direction, and in the first direction, at least part of all
  • the sixth sub-section is located between the first data line and the second data line
  • the plurality of sub-pixels includes a third sub-pixel adjacent to the second sub-pixel along the first direction
  • the sixth sub-pixel is adjacent to the second sub-pixel along the first direction.
  • Three data lines extend along the second direction and are connected to the pixel circuit structure of the third sub-pixel, and the reset control signal line, the gate line and the light emission control signal line are located on the second data line
  • the part between the third data line and the third data line extends along the first direction, the distance between the fourth subsection and the fifth subsection is D 1
  • the reset control signal line is located in the
  • the distance between the part between the second data line and the third data line and the part of the gate line between the second data line and the third data line is D 2
  • the D 1 is smaller than the D 2
  • the distance between the fifth sub-section and the first sub-section is D 3
  • the gate line is located between the second data line and the third data line
  • the distance between the light-emitting control signal line and the portion of the light-emitting control signal line located between the second data line and the third data line is D 4
  • the D 3 is smaller than the D 4 .
  • the active layer in the pixel circuit structure of the first sub-pixel is located in the area surrounded by the first initialization signal line, the second initialization signal line, the first data line, and the second data line.
  • the active layer in the pixel circuit structure of the second sub-pixel is located around the first initialization signal line, the second initialization signal line, the second data line, and the third data line.
  • the active layer in the first sub-pixel is the first active layer
  • the active layer in the second sub-pixel is the second active layer
  • the width of the first active layer is is D 7
  • the width of the second active layer is D 8
  • the D 7 is smaller than the D 8
  • the length of the first active layer is L 1
  • the length of the second active layer is L 2
  • the L 1 is smaller than the L 2 .
  • the first The sub-pixel includes a light-emitting element, the light-emitting element is located on a side of the pixel circuit structure away from the base substrate, and in the second direction, the anode of the light-emitting element is located in the first sub-section away from the One side of the second pole of the second light emission control transistor.
  • the ratio of the active layer width to the gate length of the thin film transistor in the pixel circuit structure of the first sub-pixel, and the active layer width of the thin film transistor in the pixel circuit structure of the second sub-pixel and The ratio of gate lengths is consistent.
  • the first sub-pixel when the width of the light-transmitting hole is greater than 1/2 of the distance between the first data line and the second data line, the first sub-pixel includes light-emitting
  • the light-emitting element is located on the side of the pixel circuit structure away from the base substrate, and the anode in the light-emitting element is not in contact with the light-emitting layer.
  • the orthographic projection of the first active layer on the base substrate has no overlapping area with the orthographic projection of the reset control signal line on the base substrate.
  • the display substrate includes at least one fingerprint identification area, and the light transmission hole is provided in the fingerprint identification area.
  • the present application provides a display device.
  • the display device includes the aforementioned display substrate. Therefore, the display device has all the features and advantages of the aforementioned display substrate, which are not repeated here. In general, the display device has high fingerprint recognition sensitivity and high resolution.
  • FIG. 1A shows a schematic top view of a first active layer according to an embodiment of the present application
  • FIG. 1B shows a schematic top view of the reset control signal line, the gate line, the light emission control signal line, and the lower electrode plate of the storage capacitor portion formed on the side of the first active layer away from the base substrate according to an embodiment of the present application;
  • FIG. 1C shows a first initialization signal line and a second initialization signal line formed on the side of the reset control signal line, the gate line, the light emission control signal line, and the lower electrode plate of the storage capacitor part away from the base substrate according to an embodiment of the present application
  • 1D shows a schematic diagram of setting via holes on the first initialization signal line, the second initialization signal line, the first active layer, the upper electrode plate of the storage capacitor, and the lower electrode plate of the storage capacitor according to an embodiment of the present application ;
  • 1E shows the first data lines, the second data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the first data lines, the second data lines, and the top electrode plates of the storage capacitor part, which are formed on the side away from the base substrate according to an embodiment of the present application.
  • FIG. 1F shows a schematic structural diagram of a first sub-pixel and a second sub-pixel according to an embodiment of the present application
  • 1G shows a schematic top view of the first active layer and the second active layer according to an embodiment of the present application
  • FIG. 2 shows a schematic top view of a light shielding layer according to an embodiment of the present application
  • FIG. 3 shows a schematic structural diagram of a display substrate according to an embodiment of the present application
  • FIG. 4 shows a schematic diagram of a connection relationship between structures in a sub-pixel according to an embodiment of the present application
  • FIG. 5A shows a schematic top view of the first active layer according to another embodiment of the present application.
  • 5B shows a schematic top view of the reset control signal line, the gate line, the light emission control signal line, and the lower electrode plate of the storage capacitor portion formed on the side of the first active layer away from the base substrate according to another embodiment of the present application;
  • 5C shows the first initialization signal line and the second initialization signal line formed on the reset control signal line, the gate line, the light emission control signal line, and the lower electrode plate of the storage capacitor part on the side away from the base substrate according to another embodiment of the present application A schematic top view of the upper electrode plate of the signal line and the storage capacitor part;
  • FIG. 5D shows via holes provided on the first initialization signal line, the second initialization signal line, the first active layer, the upper electrode plate of the storage capacitor, and the lower electrode plate of the storage capacitor according to another embodiment of the present application.
  • 5E shows the first data lines, the second data lines, the first data lines, the second data lines, the first data lines, the second data lines, the first data lines, the second data lines, the first data lines, the second data lines, the upper electrode plates of the storage capacitor part that are formed on the side away from the base substrate according to another embodiment of the present application.
  • 5F shows a schematic structural diagram of a first sub-pixel and a second sub-pixel according to another embodiment of the present application.
  • 5G shows a schematic top view of the first active layer and the second active layer according to another embodiment of the present application.
  • FIG. 6A shows a schematic top view of a first active layer according to another embodiment of the present application.
  • 6B shows a schematic top view of reset control signal lines, gate lines, and light-emitting control signal lines formed on the side of the first active layer away from the base substrate according to another embodiment of the present application;
  • 6C shows a schematic top view of the first initialization signal line and the second initialization signal line formed on the side of the reset control signal line, the gate line, and the light-emitting control signal line away from the base substrate according to another embodiment of the present application;
  • 6D shows a schematic top view of the first data line, the second data line, and the first power line formed on the side of the first initialization signal line and the second initialization signal line away from the base substrate according to another embodiment of the present application;
  • 6E shows a schematic structural diagram of a first sub-pixel and a second sub-pixel according to another embodiment of the present application.
  • FIG. 6F shows a schematic top view of the first active layer and the second active layer according to another embodiment of the present application.
  • Figure 7 shows the working principle diagram of the 7T1C pixel compensation circuit
  • FIG. 8 shows a schematic diagram of a pixel arrangement according to an embodiment of the present application.
  • the present application proposes a display substrate.
  • the display substrate includes: a base substrate 100 , a light shielding layer 200 and a plurality of sub-pixels 300 (only one sub-pixel is shown in FIG. 3 ), the base substrate 100 includes a display area, A plurality of sub-pixels 300 are located in the display area, the sub-pixels 300 include a pixel circuit structure 320, the light shielding layer 200 is located between the pixel circuit structure 320 and the base substrate 100, and the light shielding layer 200 has a light-transmitting hole 210 (refer to FIG. 2, FIG. 3 ). The light-transmitting holes are not shown).
  • the plurality of sub-pixels includes a first sub-pixel 300A and a second sub-pixel 300B adjacent to each other along a first direction
  • the display substrate further includes: a first initialization signal line 160A extending along the first direction, a light-emitting control signal line 130, the first power line 150, the first data line 140A, and the second data line 140B extending along the second direction, the first direction and the second direction intersect, and the pixel circuit structure of the first data line 140A and the first sub-pixel 300A
  • the second data line 140B is connected to the pixel circuit structure of the second sub-pixel 300B, the first data line 140A and the second data line 140B are located on both sides of the first power supply line 150 respectively, and the light-transmitting holes 210 in the light shielding layer are located in The first power line 150 , the second data line 140B, the light-emitting control signal line 130 and the first initialization signal line 160A are surrounded by the area. Therefore, the display device using the display substrate
  • the display substrate further includes a fingerprint identification sensor (not shown in the figure), the fingerprint identification sensor is disposed on the side of the base substrate away from the light-shielding layer, and the orthographic projection of the light-transmitting hole on the base substrate , which has at least partial overlap with the orthographic projection of the fingerprint identification sensor on the base substrate.
  • the fingerprint identification sensor is used to collect the light signal transmitted through the light-transmitting hole, convert the light signal into an electrical signal, extract the fingerprint information, and realize the fingerprint identification after data processing.
  • a light-shielding layer is provided in the display substrate, and a light-transmitting hole is arranged in the light-shielding layer.
  • the light shielding layer can block the light in the area outside the light-transmitting hole to prevent the light in other areas from interfering with the fingerprint recognition process, thereby improving the fingerprint recognition sensitivity of the display device using the display substrate.
  • the specific material of the light shielding layer is not particularly limited, for example, the light shielding layer may be formed of a metal material.
  • the sub-pixel 300 includes a light-emitting element 310 and a pixel circuit structure 320, the light-emitting element 310 is located on the side of the pixel circuit structure 320 away from the base substrate 100, the light-emitting element 310 is an organic light-emitting diode, and the organic A light-emitting diode includes an anode, a light-emitting layer, and a cathode.
  • the pixel circuit structure 320 may include a storage capacitor portion 80 and a plurality of thin film transistors (eg, a first thin film transistor 10 , a second thin film transistor 20 , a third thin film transistor 30 , a fourth thin film transistor 40 , and a fifth thin film transistor 50 ).
  • the sixth thin film transistor 60, the seventh thin film transistor 70), the electrodes in the thin film transistors and the metal traces electrically connected between the thin film transistors, and the two electrode plates of the storage capacitor part 80 are all opaque parts.
  • the orthographic projection of the light-transmitting hole 210 on the base substrate 100 has no overlapping area with the orthographic projection of the opaque portion of the pixel circuit structure 320 on the base substrate 100 .
  • the opaque portion in the pixel circuit structure will not block the light that needs to be injected into the light-transmitting hole, so as to realize fingerprint recognition.
  • the orthographic projection of the light-transmitting hole 210 on the base substrate 100 has no overlapping area with the orthographic projection of the electrode of the light-emitting element 310 on the base substrate 100.
  • the anode of the organic light emitting diode may be formed of a transparent conductive material or a metal material
  • the cathode may be formed of a transparent conductive material or a semi-transparent conductive material.
  • the electrode of the light-emitting element is formed of a metal material or a semi-transparent conductive material, since the light-transmitting hole of the present application does not overlap with the orthographic projection of the electrode of the light-emitting element on the substrate, the electrode of the light-emitting element will not block the required radiation. Light into the light-transmitting hole to realize fingerprint recognition.
  • the electrode of the light-emitting element is formed of a transparent conductive material, the orthographic projection of the light-transmitting hole and the electrode of the light-emitting element on the base substrate is not overlapped, which can prevent stray light from affecting fingerprint recognition.
  • the present application not only provides a light-shielding layer in the display substrate, but also optimizes the positions of the light-transmitting holes in the light-shielding layer, so that a high-resolution display device can realize fingerprint recognition under the screen.
  • the display substrate further includes a gate line 120 , a reset control signal line 110 and a second initialization signal line 160B extending along a first direction.
  • the control signal line 110 and the second initialization signal line 160B are sequentially arranged on the side of the light emission control signal line 130 away from the first initialization signal line 160A, and the pixel circuit structure of the first sub-pixel 300A and the pixel circuit of the second sub-pixel 300B are arranged in sequence.
  • the structures are respectively connected to the second initialization signal lines 160B (refer to FIG. 1F ).
  • the second direction intersects with the first direction, specifically, the second direction is perpendicular to the first direction, but not limited thereto.
  • FIG. 1A is a schematic top view of the first active layer 321A
  • FIG. 1B is a reset control signal line 110 , a gate line 120 and a light emission control signal line formed on the side of the first active layer 321A away from the base substrate. 130.
  • a schematic top view of the lower electrode plate 81 of the storage capacitor portion FIG. 1C is a diagram formed on the reset control signal line 110, the gate line 120, the light emission control signal line 130, and the lower electrode plate 81 of the storage capacitor portion on the side away from the substrate.
  • FIG. 1A is a schematic top view of the first active layer 321A
  • FIG. 1B is a reset control signal line 110 , a gate line 120 and a light emission control signal line formed on the side of the first active layer 321A away from the base substrate. 130.
  • 1D shows the first initialization signal line 160A, the second initialization signal line 160B, and the first active layer 321A.
  • 82 is a schematic top view of the first data line 140A, the second data line 140B, and the first power line 150 on the side away from the base substrate.
  • 1A to 1E show the stacking sequence and positional relationship between the structures, and in order to facilitate showing the positional relationship of the above structures, FIGS. 1A to 1E do not show the insulating layers between the structures. For the lamination relationship with the insulating layer, please refer to FIG. 3 .
  • the display substrate further includes a protective layer 400 and a buffer layer 500
  • the protective layer 400 covers the light shielding layer 200
  • the buffer layer 500 is located between the protective layer 400 and the pixel circuit structure 320
  • the pixel circuit structure 320 includes an active layer 321, a first insulating layer 322, a first gate metal layer 323, a second insulating layer 324, a second gate metal layer 325, a layer of The interlayer dielectric layer 326, the source-drain metal layer 327 and the planarization layer 328, wherein a part of the source-drain metal layer 327 passes through the via hole passing through the interlayer dielectric layer 326, the second insulating layer 324 and the first insulating layer 322, It is connected to the active layer 321 to form the source electrode 327A and the drain electrode 327B of the thin film transistor.
  • the light-emitting element 310 includes an anode 311 , a pixel defining layer 312 , an anode 311 , a pixel defining layer 312 , an anode 311 , a pixel defining layer 312 and a Layer 313 and cathode 314, the anode 311 is connected to the source or drain of the thin film transistor through a via hole passing through the planarization layer 328, and the light emitting layer 313 is connected to the anode 311 through a via hole passing through the pixel defining layer 312.
  • the first gate metal layer 323 is used to form the gate of the thin film transistor and the reset control signal line, the gate line, the light emission control signal line, and the lower electrode plate of the storage capacitor part.
  • the second gate metal layer 325 is used to form the first initialization signal line, the second initialization signal line and the upper electrode plate of the storage capacitor part.
  • the source-drain metal layer 327 is used to form the source electrode, the drain electrode, the first data line, the second data line and the first power supply line of the thin film transistor.
  • the specific constituent materials of the above-mentioned film layers are not particularly limited, and those skilled in the art can design according to commonly used materials.
  • the material constituting the protective layer 400 may include silicon oxide.
  • the display substrate further includes a second power supply line (VSS) 170 , and the cathode 314 of the light emitting element 310 is connected to the second power supply line 170 .
  • VSS second power supply line
  • each film layer located on the side of the light shielding layer away from the base substrate has high light transmittance (such as the protective layer 400 , the buffer layer 500 , the first insulating layer 322 , the second insulating layer 324 , the interlayer dielectric layer 326, planarization layer 328 and other film layers), therefore, it is only necessary to set light-transmitting holes in the light-shielding layer, and on the basis of realizing fingerprint identification, the stability of the display substrate is ensured.
  • the light-shielding layer 200 has a plurality of light-transmitting holes 210 , and the plurality of light-transmitting holes 210 are arranged periodically (that is, in the light-shielding layer 200 , any two light-transmitting holes 210 are The distance between the holes 210 is the same), the orthographic projection of each light-transmitting hole 210 on the base substrate 100 is located in the orthographic projection of one sub-pixel 300 on the base substrate 100 (as shown in FIG. 2 ) 220) range.
  • the opening sizes of the plurality of light-transmitting holes in the light-shielding layer are the same.
  • the opening shape of the light-transmitting hole is not particularly limited.
  • the opening shape of the light-transmitting hole may be a square, thereby improving imaging quality and obtaining clearer fingerprint information.
  • the specific period for the arrangement of the light-transmitting holes is not particularly limited, and those skilled in the art can design according to specific conditions. For example, it can be designed according to the resolution of the product, the size of the sub-pixel, the thickness and dielectric constant of each film layer on the side of the light shielding layer away from the base substrate, etc.
  • a light-transmitting hole may be provided in an 8 ⁇ 8 pixel unit array, or a light-transmitting hole may be provided in a 12 ⁇ 12 pixel unit array.
  • each pixel unit may include a plurality of sub-pixels, and the light-transmitting holes are arranged according to the positions described above.
  • the display substrate further includes a connection electrode 327C connected to the light shielding layer 200 , the connection electrode 327C is formed by a part of the source-drain metal layer 327 , and the connection electrode 327C passes through the interlayer dielectric layer 326
  • the via holes of the second insulating layer 324, the first insulating layer 322, the buffer layer 500 and the protective layer 400 are connected to the light shielding layer 200, and the connection electrode 327C can be connected to the second power line 170 (not shown in FIG. 3). Thereby, static electricity can be prevented from being formed in the light shielding layer.
  • the following takes the pixel circuit structure including 7 thin film transistors and one storage capacitor part (ie, 7T1C pixel circuit structure) as an example to describe the connection relationship between each thin film transistor and the storage capacitor part:
  • the first thin film transistor 10 and the seventh thin film transistor 70 are reset control transistors
  • the second thin film transistor 20 is a threshold compensation transistor
  • the third thin film transistor 30 is a driving transistor
  • the fourth thin film transistor 40 is a data writing transistor
  • the fifth thin film transistor 50 and the sixth thin film transistor 60 are light emission control transistors.
  • the gate electrode 13 of the first thin film transistor is connected to the reset control signal line 110 , and referring to FIGS. 1B and 1E , the source electrode 11 of the first thin film transistor is connected to the second initialization signal line 160B through the first trace 1 , referring to FIG. 1B and FIG. 1E . 1D and FIG. 1E , the first trace 1 is connected to the source electrode 11 of the first thin film transistor through the via hole 14 , and the first trace 1 is connected to the second initialization signal line 160B through the via hole 15 , refer to FIG. 1B and FIG. 1E , the drain 12 of the first thin film transistor is connected to the gate 33 of the third thin film transistor through the second trace 2. Referring to FIG. 1D and FIG.
  • the second trace 2 is connected to the drain of the first thin film transistor through the via 24 12 is connected, and the second trace 2 is connected to the gate 33 of the third thin film transistor through the via hole 25 .
  • the gate electrode 73 of the seventh thin film transistor is connected to the reset control signal line 110 .
  • the source electrode 71 of the seventh thin film transistor is connected to the second initialization signal line 160B through the first wiring 1 ,
  • the drain 72 of the seventh thin film transistor is connected to the anode 311 of the light emitting element 310 (not shown in FIG. 1 ).
  • the gate electrode 23 of the second thin film transistor is connected to the gate line 120 , with reference to FIGS. 1B and 1E , the source electrode 21 of the second thin film transistor is connected to the gate electrode 33 of the third thin film transistor through the second wiring 2 , The drain 22 of the second thin film transistor is connected to the drain 32 of the third thin film transistor.
  • the gate electrode 43 of the fourth thin film transistor is connected to the gate line 120 , referring to FIG. 1E , the source electrode 41 of the fourth thin film transistor is connected to the first data line 140A through the via 44 , and the drain electrode 42 of the fourth thin film transistor It is connected to the source electrode 31 of the third thin film transistor (refer to FIG. 1B ).
  • the gate 53 of the fifth thin film transistor is connected to the light-emitting control signal line 130.
  • the source 51 of the fifth thin film transistor is connected to the first power line 150 through the via 54, and the drain of the fifth thin film transistor
  • the electrode 52 is connected to the source electrode 31 of the third thin film transistor (refer to FIG. 1B ) (that is, the source electrode of the third thin film transistor, the drain electrode of the fourth thin film transistor and the drain electrode of the fifth thin film transistor are connected to the node N2 (refer to FIG. 1B ) 4)).
  • the gate electrode 63 of the sixth thin film transistor is connected to the light-emitting control signal line 130, and the source electrode 61 of the sixth thin film transistor is connected to the drain electrode 32 of the third thin film transistor (ie, the drain electrode of the second thin film transistor, the third The drain electrode of the thin film transistor and the source electrode of the sixth thin film transistor are connected to the node N 3 (refer to FIG. 4 ).
  • the drain electrode 62 of the sixth thin film transistor is connected to the anode 311 of the light emitting element 310 through the via hole 64 .
  • the lower electrode plate 81 (refer to FIG. 1B ) of the storage capacitor part 80 is connected to the source electrode 21 of the second thin film transistor through the second wiring 2 (in FIG. 1E , the lower electrode plate 81 is connected to the second thin film transistor
  • the position where the trace 2 is connected is the position where the gate 33 of the third thin film transistor is connected to the second trace 2) (that is, the source of the second thin film transistor, the gate of the third thin film transistor and the lower electrode of the storage capacitor part) 1C and 1E
  • the upper electrode plate 82 of the storage capacitor portion 80 is connected to the first power line 150, and the upper electrode plate 82 can pass through two via holes (as shown in Fig.
  • the via holes 84 and 85 shown in 1D and 1E are connected to the first power line 150 to improve the electrical connection performance between the upper electrode plate and the first power line.
  • the reset control signal line is used to apply the Reset signal to the first thin film transistor 10 and the seventh thin film transistor 70
  • the gate line is used to apply the Gate signal to the fourth thin film transistor 40 and the second thin film transistor 20, and the light emission control signal line for applying the EM signal to the fifth thin film transistor 50 and the sixth thin film transistor 60, the first data line for applying the Vdata signal to the fourth thin film transistor 40, the first power line for applying the VDD signal to the fifth thin film transistor 50
  • the second initialization signal line is used to apply the Vint signal to the first thin film transistor 10 and the second thin film transistor 70 .
  • the display substrate further includes a connection part 90 , and the connection part 90 is connected to the first power line 150 through the via hole 91 . Therefore, the connection part can prevent the first data line from causing signal interference to the first power line.
  • the working sequence of the 7T1C pixel compensation circuit is divided into a reset stage, a sampling stage, and a light-emitting stage to complete the compensation for the pixel threshold voltage (Vth).
  • Vth pixel threshold voltage
  • the Reset signal is at a low level.
  • the first thin film transistor is turned on, and the Vint signal initializes the N1 point.
  • Vint the potential of the N1 point is Vint
  • the third thin film transistor is turned on.
  • the seventh thin film transistor is turned on, Vint reduces the voltage difference between the anode and the cathode of the light-emitting element, reduces the brightness of the light-emitting element at a low gray scale, and improves the contrast ratio of the pixel.
  • the Gate signal is at a low level.
  • the fourth thin film transistor is turned on, at this time, the potential of the N 2 point is Vdata, and the data signal voltage is written into the N 2 point.
  • the second thin film transistor is turned on to sample the connection of the third thin film transistor, the potential of the N1 point rises to Vdata+Vth, the third thin film transistor gradually changes from the open state to the closed state, and the threshold voltage of the third thin film transistor is compensated.
  • the EM signal is at a low level.
  • the fifth thin film transistor and the sixth thin film transistor are turned on, at this time, the potential of the N2 point is VDD, the third thin film transistor outputs a driving current, and the light-emitting element emits light.
  • the threshold voltage of the thin film transistor is compensated to eliminate the influence of the difference in the threshold voltage of the driving thin film transistor (ie, the third thin film transistor) of different pixels on the uniformity of display brightness.
  • the width of the light-transmitting hole 210 in the first direction may be less than 1/3 of the distance between the first data line and the second data line, or the width of the light-transmitting hole 210 in the first direction may be 1/3 of the distance between the first data line and the second data line. 1/3-1/2 of the distance between the first data line and the second data line, or the width of the light-transmitting hole 210 in the first direction may be greater than 1/1 of the distance between the first data line and the second data line 2.
  • the width of the light-transmitting hole 210 may be less than 1/3 of the distance between the first data line 140A and the second data line 140B.
  • the pixel circuit structure of the sub-pixel 300A includes a first light-emitting control transistor (ie, the fifth thin film transistor 50 ) and a second light-emitting control transistor (ie, the sixth thin film transistor 60 ).
  • the first electrode of the first light-emitting control transistor (such as the source electrode 51 ) ) is located on the first side of the light-emitting control signal line 130, the second electrode of the first light-emitting control transistor (such as the drain 52) is located on the second side of the light-emitting control signal line 130, and the second electrode (such as the drain electrode) of the second light-emitting control transistor
  • the electrode 62) is located on the first side of the light-emitting control signal line 130, the first electrode (such as the source electrode 61) of the second light-emitting control transistor is located on the second side of the light-emitting control signal line 130, and the first and second sides are for light-emitting control
  • the light-transmitting holes 210 are located between the first electrode 51 of the first light-emitting control transistor and the second electrode 62 of the second light-emitting control transistor.
  • the source and drain of the light emission control transistor will not block the light transmission hole.
  • the driving transistor, reset control transistor, threshold compensation transistor, data writing transistor and storage capacitor are all located on the side of the light-emitting control signal line away from the first initialization signal line, so that the source and drain of the above transistors are The electrode and the storage capacitor part also do not block the light transmission hole.
  • the first sub-pixel 300A has a light-transmitting hole 210
  • the second sub-pixel 300B does not have a light-transmitting hole.
  • the width of the light-transmitting hole 210 is smaller than the distance between the first data line 140A and the second data line 140B 1/3, because the size of the light-transmitting hole is small, the reset control signal line, the gate line, the light-emitting control signal line, the first data line, the first power supply line and the various elements in the pixel circuit structure are in the first
  • the position in the sub-pixel can be consistent with its position in the second sub-pixel (refer to FIG.
  • the size of the first active layer 321A is consistent with the size of the second active layer 321B.
  • the position in the first subpixel is the same as the position of the second active layer 321B in the second subpixel (refer to FIG. 1G ).
  • the "first active layer” is the active layer in the area enclosed by the second initialization signal line, the first initialization signal line, the first data line and the second data line, and the "second active layer”
  • the active layer in the area is enclosed for the second initialization signal line, the first initialization signal line, the second data line and the third data line 140C (refer to FIG. 1F ).
  • the third data line is a data line extending along the second direction and connected to the pixel circuit structure of the third sub-pixel, and the third sub-pixel is a sub-pixel adjacent to the second sub-pixel in the first direction (refer to FIG. 1F, only the third data line in the third sub-pixel is shown in the figure).
  • FIG. 5A is a schematic top view of the first active layer 321A
  • FIG. 5B is a reset diagram formed on the side of the first active layer 321A away from the base substrate.
  • FIG. 5A is a schematic top view of the first active layer 321A
  • FIG. 5B is a reset diagram formed on the side of the first active layer 321A away from the base substrate.
  • FIG. 5D shows the first initialization signal line 160A, The second initialization signal line 160B, the first active layer 321A, the upper electrode plate 82 of the storage capacitor, and the lower electrode plate 81 of the storage capacitor are provided with via holes.
  • FIGS. 5A-5E show the stacking sequence and positional relationship between the structures, and in order to facilitate showing the positional relationship of the above-mentioned structures, FIGS. 5A-5E do not show the insulating layers between the structures. For the lamination relationship with the insulating layer, please refer to FIG. 3 .
  • the width of the light-transmitting hole 210 may be 1/3 ⁇ 1/2 of the distance between the first data line 140A and the second data line 140B.
  • the light-emitting control signal line 130 includes a first sub-section 131, a second sub-section 132 and a third sub-section 133, the first sub-section 131 is located between the second sub-section 132 and the third sub-section 133, the first sub-section 131 Extending along the first direction, the second sub-section 132 and the third sub-section 133 extend in the second direction, and in the first direction, at least part of the second sub-section 132 is located between the first power line 150 and the second data line 140B , the pixel circuit structure of the first sub-pixel 300A includes a first light-emitting control transistor (ie, the fifth thin film transistor 50) and a second light-emitting control transistor (ie, the sixth thin-film
  • the first electrode of the first light-emitting control transistor (such as The source electrode 51) is located on the first side of the first sub-section 131
  • the second electrode (such as the drain electrode 52) of the first light-emitting control transistor is located on the second side of the first sub-section 131
  • the second electrode of the second light-emitting control transistor is located on the second side of the first sub-section 131.
  • the first electrode of the second light emission control transistor (eg source 61 ) is located on the second side of the first sub-section 131 , the first side and the second side
  • the light-transmitting holes 210 are located on the first power line 150, the second sub-section 132, the second pole 62 of the second light-emitting control transistor, the first pole 51 of the first light-emitting control transistor and within the area surrounded by the first initialization signal line 160A.
  • the third sub-section 133 is located on the side of the first data line 140A away from the first power supply line 150
  • the second sub-section 132 is located on the first side of the second light emission control transistor.
  • a side of the diode 62 away from the first power line 150 Therefore, the source and drain of the light emission control transistor will not block the light transmission hole, and thus the source and drain of the driving transistor, reset control transistor, threshold compensation transistor, data writing transistor and storage capacitor will not block the light transmission hole.
  • the light-emitting control signal line, the first data line and the first power supply line are not arranged on the same layer, "in the first direction, at least part of the third subsection is located on the first data line and away from the first power supply.
  • One side of the line refers to the orthographic projection of at least part of the third subsection on the base substrate, and the orthographic projection of the first data line on the base substrate is far from the orthographic projection of the first power line on the base substrate. side.
  • At least part of the second subsection is located between the first power supply line and the second data line
  • at least part of the second subsection is an orthographic projection on the base substrate, located in the first power supply line between the orthographic projection of the line on the base substrate and the orthographic projection of the second data line on the base substrate.
  • the size of the light-transmitting hole can be enlarged to further improve the sensitivity of fingerprint identification, and can be applied to a display device with a smaller sub-pixel size.
  • Traditional fingerprint recognition display devices usually sacrifice resolution, and set light-transmitting holes with larger openings in sub-pixels with larger sizes. That is to say, traditional fingerprint recognition display devices usually have lower resolution.
  • a light-transmitting hole with a larger opening size is arranged in the display device.
  • a light-transmitting hole with a larger opening size can be arranged in a sub-pixel with a smaller size, thus, it can be applied to a display device with a higher resolution, so that the display device can take into account both high resolution and high fingerprint recognition sensitivity .
  • the first sub-pixel 300A has a light-transmitting hole 210, and the second sub-pixel 300B does not have a light-transmitting hole.
  • the reset control signal line 110 includes a first sub-pixel extending along the first direction.
  • the four sub-portions 111 and the bent portions 112 at both ends of the fourth sub-portion 111 refer to FIG. 5F, at least part of the fourth sub-portion 111 is located between the first data line 140A and the second data line 140B, refer to FIGS.
  • the gate line 120 includes a fifth sub-section 121, a sixth sub-section 122 and a seventh sub-section 123, the fifth sub-section 121 is located between the sixth sub-section 122 and the seventh sub-section 123, and the fifth sub-section 121 is located along the Extending in one direction, the sixth sub-section 122 and the seventh sub-section 123 extend in a second direction.
  • the sixth sub-section 122 is located between the first data line 140A and the second data line 140B, and more
  • the sub-pixels include a third sub-pixel (not shown in the figure) adjacent to the second sub-pixel 300B along the first direction, and the third data line 140C extends along the second direction and is connected to the pixel circuit structure of the third sub-pixel , the parts of the reset control signal line 110 , the gate line 120 and the light emission control signal line 130 located between the second data line 140B and the third data line 140C all extend in the first direction (refer to FIG. 5F ).
  • the distance between the fifth subsections 121 is D 1 , the part of the reset control signal line 110 located between the second data line 140B and the third data line 140C, and the gate line 120 located between the second data line 140B and the third data line 140C
  • the distance between the parts 140C is D 2 , D 1 is smaller than D 2
  • the distance between the fifth sub-section 121 and the first sub-section 131 is D 3
  • the gate line 120 is located between the second data line 140B and the third
  • the distance between the part between the data lines 140C and the part of the light emission control signal line 130 between the second data line 140B and the third data line 140C is D 4
  • D 3 is smaller than D 4 . Therefore, by narrowing the spacing between the signal lines in the first sub-pixel, a larger area is reserved corresponding to the light-transmitting hole.
  • the area of the storage capacitor portion in the first subpixel also needs to be smaller than the area of the storage capacitor portion in the second subpixel.
  • the active layer in the pixel circuit structure of the first sub-pixel 300A is located on the first initialization signal line 160A, the second initialization signal line 160B, the first data line 140A, and the second data line 140B In the enclosed area, the active layer in the pixel circuit structure of the second sub-pixel 300B is located in the area enclosed by the first initialization signal line 160A, the second initialization signal line 160B, the second data line 140B, and the third data line 140C.
  • the active layer in the first sub-pixel is the first active layer 321A
  • the active layer in the second sub-pixel is the second active layer 321B
  • the width of the first active layer 321A is D 7
  • the second The width of the active layer 321B is D 8
  • D 7 is smaller than D 8
  • the length of the first active layer 321A is L 1
  • the length of the second active layer 321B is L 2
  • L 1 is smaller than L 2 (refer to FIG. 5G ) . Therefore, by reducing the size of the first active layer, the connection between the source and drain of the thin film transistor and each signal line is ensured.
  • the first sub-pixel 300A emits light normally. Therefore, the narrowing of the spacing between the signal lines and the reduction of the size of the first active layer require the first sub-pixel 300A to emit light. Normal lighting is the premise.
  • the position of the via hole 44 connecting the first data line 140A and the source of the fourth thin film transistor is moved, and the first power line 150 is connected to the fourth thin film transistor source.
  • the positions of the via holes 54 connected to the sources of the five thin film transistors are shifted (refer to FIG. 5F ). Therefore, the portion of the first data line 140A and the first power supply line 150 connected to the pixel circuit structure of the first sub-pixel 300A may have a bent structure (refer to FIG.
  • the first data line 140A and the first power supply line 150 are all bent to the side close to the light-transmitting hole 210 , so that the first data line 140A can apply a signal to the fourth thin film transistor 40 and the first power line 150 A signal can be applied to the fifth thin film transistor 50 .
  • the number of thin film transistors in the first sub-pixel 300A has The ratio of the width of the source layer to the length of the gate is consistent with the ratio of the width of the active layer to the length of the gate of the thin film transistor in the second sub-pixel 300B. Therefore, it can be ensured that the display brightness of the first sub-pixel is consistent with the display brightness of the second sub-pixel, and the uniformity of the brightness of the entire display screen can be ensured.
  • the length of the gate is the dimension of the gate in the extending direction thereof
  • the width of the active layer is the dimension of the active layer perpendicular to the extending direction of the gate.
  • the width of the light-transmitting hole 210 is 1/3 ⁇ 1/2 of the distance between the first data line 140A and the second data line 140B, in the second direction, in the first sub-pixel
  • the anode 311 of the light-emitting element is located on the side of the first sub-section 131 away from the second pole 62 of the second light-emitting control transistor (refer to FIG. 5E ). That is, the light-emitting element in the first sub-pixel 300A is moved to the side away from the light-transmitting hole 210 compared with the light-emitting element in the second sub-pixel 300B, so as to prevent the electrode of the light-emitting element from blocking the light-transmitting hole.
  • the drain 62 of the sixth thin film transistor in a sub-pixel 300A is connected to the anode 311 of the light-emitting element through the third wiring 3 (refer to FIG. 5E ).
  • the light-emitting color of the first sub-pixel described above is not particularly limited.
  • the first sub-pixel may be a sub-pixel that emits red light, or the first sub-pixel is a sub-pixel that emits green light, or the first sub-pixel may be a sub-pixel that emits green light.
  • a pixel is a sub-pixel that emits blue light. That is to say, when the width of the light-transmitting hole does not exceed 1/2 of the width of the sub-pixel, the light-transmitting hole can be arranged in the area of the light-shielding layer corresponding to the sub-pixel that emits red light, or can be arranged in the light-shielding layer. In the layer corresponding to the sub-pixels emitting green light, or may be provided in the region corresponding to the sub-pixels emitting blue light in the light shielding layer.
  • FIG. 6A-6D wherein FIG. 6A is a schematic top view of the first active layer 321A, and FIG. 6B is a reset diagram formed on the side of the first active layer 321A away from the base substrate.
  • FIG. 6C is a first initialization signal line formed on the side of the reset control signal line 110, the gate line 120, and the light-emitting control signal line 130 away from the substrate.
  • FIG. 6D shows the first data line 140A, the second data line 140B, the first data line 140A, the second data line 140B, the first data line 140A, the second A schematic top view of the power cord 150 .
  • FIGS. 6A-6D show the stacking sequence and positional relationship between the structures, and in order to facilitate showing the positional relationship of the above-mentioned structures, FIGS. 6A-6D do not show the insulating layers between the structures. For the lamination relationship with the insulating layer, please refer to FIG. 3 .
  • the width of the light-transmitting hole 210 may be greater than 1/2 of the distance between the first data line 140A and the second data line 140B.
  • the light emission control signal The line 130 includes a first subsection 131, a second subsection 132 and a third subsection 133, the first subsection 131 is located between the second subsection 132 and the third subsection 133, and the first subsection 131 is along a first direction Extending, the second sub-section 132 and the third sub-section 133 extend along the second direction, and in the first direction, at least part of the second sub-section 132 is located between the first power line 150 and the second data line 140B, refer to FIG.
  • the active layer in the pixel circuit structure of the first sub-pixel 300A is located in the area surrounded by the first initialization signal line 160A, the second initialization signal line 160B, the first data line 140A, and the second data line 140B,
  • the active layer in the first sub-pixel 300A is the first active layer 321A.
  • the orthographic projection of the first active layer 321A on the base substrate is connected to the gate line 120 and the light emission control signal line 130 on the substrate.
  • the orthographic non-overlapping region on the substrate that is, the partial region of the first active layer 321A is disconnected and discontinuous, in other words, the pixel circuit structure of the first sub-pixel 300A does not have light-emitting control transistors, driving transistors ), the light-transmitting hole 210 is located in the area surrounded by the first power line 150 , the first sub-section 131 , the second sub-section 132 and the first initialization signal line 160A.
  • the third sub-section 133 is located between the first data line 140A and the first power line 150 .
  • a larger area can be reserved in the first sub-pixel corresponding to the light-transmitting hole.
  • the first sub-pixel can be used as a Dummy sub-pixel, that is, the first sub-pixel does not emit light, so as to reduce the setting of thin film transistors, or even not set thin film transistors to ensure that the first sub-pixel is reserved.
  • a larger area corresponds to the light-transmitting hole.
  • the opening size of the light-transmitting hole is larger, which can further improve the sensitivity of fingerprint recognition, and can be applied to a display device with a smaller sub-pixel size, that is, this embodiment can be set in a sub-pixel with a smaller size
  • the light-transmitting hole with a larger opening size can thus be applied to a display device with higher resolution, so that the display device can take into account both high resolution and high fingerprint recognition sensitivity.
  • the orthographic projection of the first active layer 321A in the first sub-pixel on the base substrate 100 may not overlap with the orthographic projection of the reset control signal line 110 on the base substrate 100 area.
  • the fabrication of the lower electrode plate of the storage capacitor portion can be omitted, the process can be simplified, and a larger area corresponding to the light-transmitting hole can be reserved, and the present application retains part of the first active layer and part of the source-drain metal layer and part of the upper electrode plate of the storage capacitor portion (refer to FIG. 6C ), which is beneficial to maintain the uniformity of the etching process during the manufacturing process of the display substrate, and can.
  • the anode in the light-emitting element of the first sub-pixel does not contact the light-emitting layer . Since the first sub-pixel does not emit light, the anode of the light-emitting element is not in contact with the light-emitting layer, and the process of digging holes in the pixel defining layer can be omitted.
  • the width of the light-transmitting hole 210 is greater than 1/2 of the distance between the first data line 140A and the second data line 140B, referring to FIG. 6E , the first sub-pixel 300A has the light-transmitting hole 210 in it , the second sub-pixel 300B does not have a light-transmitting hole. At this time, it is also satisfied that D 1 is smaller than D 2 , D 3 is smaller than D 4 , D 7 is smaller than D 8 , and L 1 is smaller than L 2 (refer to FIG. 6E and FIG. 6F ), It will not be repeated here.
  • the distance between two adjacent signal lines can continue to be reduced (compared to the width of the light-transmitting hole being the first data line and the second 1/3-1/2 of the distance between the two data lines), so that a larger area can be reserved in the first sub-pixel 300A to correspond to the light-transmitting hole.
  • the plurality of sub-pixels include a fourth sub-pixel (not shown in the figure) adjacent to the first sub-pixel 300A along the second direction, the fourth sub-pixel is a sub-pixel that emits light normally, and the fourth sub-pixel is The material of the middle light-emitting layer is the same as the material of the light-emitting layer in the first sub-pixel. Since the first sub-pixel does not emit light, if the material of the light-emitting layer of the fourth sub-pixel is the same as the material of the light-emitting layer of the first sub-pixel, the brightness compensation can be performed by the fourth sub-pixel, which can ensure that the display performance of the display device does not have a significant occurrence. reduce.
  • each row is arranged with red sub-pixels (R), two in the column direction
  • the green sub-pixels (G) and blue sub-pixels (B) are arranged in the column direction, and the red sub-pixels are located in the row corresponding to the area between the green sub-pixels and the blue sub-pixels in the previous row.
  • the green sub-pixel is located in the row corresponding to the area between the blue sub-pixel and the red sub-pixel in the previous row
  • the blue sub-pixel is located in the row between the red sub-pixel and the green sub-pixel in the previous row.
  • the sub-pixels are staggered and arranged.
  • the above pixel arrangement is such that the red sub-pixel and the blue sub-pixel are shared by two adjacent pixel units, for example, B 1 , R 1 and G 1 form one pixel unit, while B 1 , R 1 and G 2 form the other pixel unit.
  • the above pixel arrangement is such that there is another green sub-pixel (eg G 3 ) adjacent to the green sub-pixel (eg G 2 ), when the width of the light-transmitting hole in the first direction is greater than the first data line and When the distance between the second data lines is 1/2, the light-transmitting hole is arranged in a green sub-pixel, such as in G 2 (that is, the first sub-pixel 300A is the green sub-pixel G 2 ), that is, G 2 is not At this time, the light emission of the pixel unit composed of B 1 , R 1 and G 1 is not affected, but the light emission of the pixel unit composed of B 1 , R 1 and G 2 will be affected.
  • G 3 green sub-pixel
  • the brightness of G 3 can be increased by , the brightness compensation of green light is performed on the pixel unit composed of B 1 , R 1 and G 2 , which can alleviate the problem that the display performance of the pixel unit composed of B 1 , R 1 and G 2 is degraded due to G 2 not emitting light, and B 2 , the pixel unit formed by R 2 and G 3 can also emit light normally, so that the display device as a whole has good display performance.
  • the display substrate may include at least one fingerprint identification area, and the fingerprint identification area has the light-transmitting hole described above.
  • the display substrate may have a fingerprint identification area.
  • the finger needs to Press a specific area (that is, the fingerprint recognition area) to realize fingerprint recognition.
  • the display substrate may have multiple fingerprint recognition areas, for example, any area in the entire display area of the display substrate may be a fingerprint recognition area, and during fingerprint recognition, a finger can press any area to realize fingerprint recognition.
  • the present application provides a display device.
  • the display device includes the aforementioned display substrate. Therefore, the display device has all the features and advantages of the display substrate described above, which will not be repeated here. In general, the display device has high fingerprint recognition sensitivity and high resolution.

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Abstract

一种显示基板、显示装置。显示基板包括衬底基板（100），包括显示区；多个子像素（300），位于显示区中，子像素（300）包括像素电路结构（320），多个子像素（300）包括沿第一方向相邻的第一子像素（300A）和第二子像素（300B）；遮光层（200），位于像素电路结构（320）和衬底基板（100）之间，遮光层（200）中具有透光孔（210）；沿第一方向延伸的第一初始化信号线（160A）、发光控制信号线（130）；第一电源线（150），沿第二方向延伸，第一方向与第二方向交叉；第一数据线（140A），沿第二方向延伸，第一数据线（140A）与第一子像素（300A）的像素电路结构（320）相连；第二数据线（140B），沿第二方向延伸，第二数据线（140B）与第二子像素（300B）的像素电路结构（320）相连，第一数据线（140A）和第二数据线（140B）分别位于第一电源线（150）的两侧；透光孔（210）位于第一电源线（150）、第二数据线（140B）、发光控制信号线（130）和第一初始化信号线（160A）围成的区域内。

Description

显示基板、显示装置 技术领域
本申请涉及显示技术领域，具体地，涉及显示基板、显示装置。
背景技术
随着显示技术的不断发展，目前具有屏下指纹识别功能的显示装置(如智能手机)越来越受到用户的青睐。屏下指纹识别是指将指纹识别模块集成在显示面板内部，手指接触屏幕玻璃盖板与指纹识别模块相对应的区域即可实现指纹识别。然而，目前具有屏下指纹识别功能的显示装置仍存在指纹识别灵敏度较低的问题。
因此，目前具有屏下指纹识别功能的显示装置仍有待改进。
发明内容
鉴于此，在本申请的一个方面，本申请提出了一种显示基板。所述显示基板包括：衬底基板，包括显示区；多个子像素，位于所述显示区中，所述子像素包括像素电路结构，所述多个子像素包括沿第一方向相邻的第一子像素和第二子像素；遮光层，位于所述像素电路结构和所述衬底基板之间，所述遮光层中具有透光孔；第一初始化信号线，沿所述第一方向延伸；发光控制信号线，沿所述第一方向延伸；第一电源线，沿第二方向延伸，所述第一方向与所述第二方向交叉；第一数据线，沿所述第二方向延伸，所述第一数据线与所述第一子像素的像素电路结构相连；第二数据线，沿所述第二方向延伸，所述第二数据线与所述第二子像素的像素电路结构相连，所述第一数据线和所述第二数据线分别位于所述第一电源线的两侧；其中，所述透光孔位于所述第一电源线、所述第二数据线、所述发光控制信号线和所述第一初始化信号线围成的区域内。由此，应用该显示基板的显示装置具有较高的指纹识别灵敏度，且具有较高的分辨率。
进一步地，所述显示基板包括沿所述第一方向延伸的栅线、复位控制信号线和第二初始化信号线，在所述第二方向上，所述栅线、所述复位控制信号线和所述第二初始化信号线在所述发光控制信号线远离所述第一初始化信号线的一侧依次排布，所述第一子像素的像素电路结构和所述第二子像素的像素电路结构分别与所述第二初始化信号线相连。
进一步地，在所述第一方向上，所述透光孔的宽度小于所述第一数据线和所述第二数据线之间距离的1/3，所述第一子像素的像素电路结构包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的第一极位于所述发光控制信号线的第一侧，所述第一发光控制晶体管的第二极位于所述发光控制信号线的第二侧，所述第二发光控制晶体管的第二极位于所述发光控制信号线的第一侧，所述第二发光控制晶体管的第一极位于所述发光控制信号线的第二侧，所述第一侧和所述第二侧为所述发光控制信号线相对的两侧，所述透光孔位于所述第一发光控制晶体管的第一极和所述第二发光控制晶体管的第二极之间。
进一步地，在所述第一方向上，所述透光孔的宽度为所述第一数据线和所述第二数据 线之间距离的1/3～1/2，所述发光控制信号线包括第一子部、第二子部和第三子部，所述第一子部位于所述第二子部和所述第三子部之间，所述第一子部沿所述第一方向延伸，所述第二子部和所述第三子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第二子部位于所述第一电源线和所述第二数据线之间，所述第一子像素的像素电路结构包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的第一极位于所述第一子部的第一侧，所述第一发光控制晶体管的第二极位于所述第一子部的第二侧，所述第二发光控制晶体管的第二极位于所述第一子部的第一侧，所述第二发光控制晶体管的第一极位于所述第一子部的第二侧，所述第一侧和所述第二侧为所述第一子部相对的两侧，所述透光孔位于所述第一电源线、所述第二子部、所述第二发光控制晶体管的第二极、所述第一发光控制晶体管的第一极和所述第一初始化信号线围成的区域内。
进一步地，在所述第一方向上，至少部分所述第三子部，位于所述第一数据线远离所述第一电源线的一侧，所述第二子部位于所述第二发光控制晶体管的第二极远离所述第一电源线的一侧。
进一步地，在所述第一方向上，所述透光孔的宽度大于所述第一数据线和所述第二数据线之间距离的1/2，所述发光控制信号线包括第一子部、第二子部和第三子部，所述第一子部位于所述第二子部和所述第三子部之间，所述第一子部沿所述第一方向延伸，所述第二子部和所述第三子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第二子部位于所述第一电源线和所述第二数据线之间，所述第一子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第一数据线、所述第二数据线围成的区域内，所述第一子像素中的有源层为第一有源层，所述第一有源层在所述衬底基板上的正投影，与所述栅线和所述发光控制信号线在所述衬底基板上的正投影无重叠区域，所述透光孔位于所述第一电源线、所述第一子部、所述第二子部和所述第一初始化信号线围成的区域内。
进一步地，在所述第一方向上，至少部分所述第三子部，位于所述第一数据线和所述第一电源线之间。
进一步地，所述复位控制信号线包括沿所述第一方向延伸的第四子部以及位于所述第四子部两端的弯折部，至少部分所述第四子部位于所述第一数据线和所述第二数据线之间，所述栅线包括第五子部、第六子部和第七子部，所述第五子部位于所述第六子部和所述第七子部之间，所述第五子部沿所述第一方向延伸，所述第六子部和所述第七子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第六子部位于所述第一数据线和所述第二数据线之间，所述多个子像素包括沿所述第一方向与所述第二子像素相邻的第三子像素，第三数据线沿所述第二方向延伸，且与所述第三子像素的像素电路结构相连，所述复位控制信号线、所述栅线和所述发光控制信号线位于所述第二数据线和所述第三数据线之间的部分均沿所述第一方向延伸，所述第四子部与所述第五子部之间的距离为D 1，所述复位控制信号线位于所述第二数据线和所述第三数据线之间的部分，与所述栅线位于所述第二数据线和所述第三数据线之间的部分之间的间距为D 2，所述D 1小于所述D 2，所述第五子部 与所述第一子部之间的间距为D 3，所述栅线位于所述第二数据线和所述第三数据线之间的部分，与所述发光控制信号线位于所述第二数据线和所述第三数据线之间的部分之间的间距为D 4，所述D 3小于所述D 4。
进一步地，所述第一子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第一数据线、所述第二数据线围成的区域内，所述第二子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第二数据线、所述第三数据线围成的区域内，所述第一子像素中的有源层为第一有源层，所述第二子像素中的有源层为第二有源层，所述第一有源层的宽度为D 7，所述第二有源层的宽度为D 8，所述D 7小于所述D 8，所述第一有源层的长度为L 1，所述第二有源层的长度为L 2，所述L 1小于所述L 2。
进一步地，在所述第一方向上，当所述透光孔的宽度为所述第一数据线和所述第二数据线之间距离的1/3～1/2时，所述第一子像素包括发光元件，所述发光元件位于所述像素电路结构远离所述衬底基板的一侧，在所述第二方向上，所述发光元件的阳极位于所述第一子部远离所述第二发光控制晶体管的第二极的一侧。
进一步地，所述第一子像素的像素电路结构中的薄膜晶体管的有源层宽度和栅极长度的比值，与所述第二子像素的像素电路结构中的薄膜晶体管的有源层宽度和栅极长度的比值一致。
进一步地，在所述第一方向上，当所述透光孔的宽度大于所述第一数据线和所述第二数据线之间距离的1/2时，所述第一子像素包括发光元件，所述发光元件位于所述像素电路结构远离所述衬底基板的一侧，所述发光元件中的阳极与发光层不接触。
进一步地，所述第一有源层在所述衬底基板上的正投影，与所述复位控制信号线在所述衬底基板上的正投影无重叠区域。
进一步地，所述显示基板包括至少一个指纹识别区域，所述指纹识别区域内具有所述透光孔。
在本申请的另一方面，本申请提出了一种显示装置。所述显示装置包括前面所述的显示基板。由此，该显示装置具有前面所述的显示基板的全部特征以及优点，在此不再赘述。总的来说，该显示装置具有较高的指纹识别灵敏度，且具有较高的分辨率。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1A显示了根据本申请一个实施例的第一有源层的俯视示意图；
图1B显示了根据本申请一个实施例的形成在第一有源层远离衬底基板一侧的复位控制信号线、栅线、发光控制信号线、存储电容部的下电极板的俯视示意图；
图1C显示了根据本申请一个实施例的形成在复位控制信号线、栅线、发光控制信号线、存储电容部的下电极板远离衬底基板一侧的第一初始化信号线、第二初始化信号线、存储 电容部的上电极板的俯视示意图；
图1D显示了根据本申请一个实施例的在第一初始化信号线、第二初始化信号线、第一有源层、存储电容部的上电极板、存储电容的下电极板上设置过孔的示意图；
图1E显示了根据本申请一个实施例的形成在第一初始化信号线、第二初始化信号线、存储电容部的上电极板远离衬底基板一侧的第一数据线、第二数据线、第一电源线的俯视示意图；
图1F显示了根据本申请一个实施例的第一子像素和第二子像素的结构示意图；
图1G显示了根据本申请一个实施例的第一有源层和第二有源层的俯视示意图；
图2显示了根据本申请一个实施例的遮光层的俯视示意图；
图3显示了根据本申请一个实施例的显示基板的结构示意图；
图4显示了根据本申请一个实施例的子像素中各结构之间连接关系的示意图；
图5A显示了根据本申请另一个实施例的第一有源层的俯视示意图；
图5B显示了根据本申请另一个实施例的形成在第一有源层远离衬底基板一侧的复位控制信号线、栅线、发光控制信号线、存储电容部的下电极板的俯视示意图；
图5C显示了根据本申请另一个实施例的形成在复位控制信号线、栅线、发光控制信号线、存储电容部的下电极板远离衬底基板一侧的第一初始化信号线、第二初始化信号线、存储电容部的上电极板的俯视示意图；
图5D显示了根据本申请另一个实施例的在第一初始化信号线、第二初始化信号线、第一有源层、存储电容部的上电极板、存储电容的下电极板上设置过孔的示意图；
图5E显示了根据本申请另一个实施例的形成在第一初始化信号线、第二初始化信号线、存储电容部的上电极板远离衬底基板一侧的第一数据线、第二数据线、第一电源线的俯视示意图；
图5F显示了根据本申请另一个实施例的第一子像素和第二子像素的结构示意图；
图5G显示了根据本申请另一个实施例的第一有源层和第二有源层的俯视示意图；
图6A显示了根据本申请另一个实施例的第一有源层的俯视示意图；
图6B显示了根据本申请另一个实施例的形成在第一有源层远离衬底基板一侧的复位控制信号线、栅线、发光控制信号线的俯视示意图；
图6C显示了根据本申请另一个实施例的形成在复位控制信号线、栅线、发光控制信号线远离衬底基板一侧的第一初始化信号线、第二初始化信号线的俯视示意图；
图6D显示了根据本申请另一个实施例的形成在第一初始化信号线、第二初始化信号线远离衬底基板一侧的第一数据线、第二数据线、第一电源线的俯视示意图；
图6E显示了根据本申请另一个实施例的第一子像素和第二子像素的结构示意图；
图6F显示了根据本申请另一个实施例的第一有源层和第二有源层的俯视示意图；
图7显示了7T1C像素补偿电路的工作原理图；
图8显示了根据本申请一个实施例的像素排布的示意图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的一个方面，本申请提出了一种显示基板。根据本申请的实施例，参考图3，该显示基板包括：衬底基板100、遮光层200和多个子像素300(图3中仅示出了一个子像素)，衬底基板100包括显示区，多个子像素300位于显示区中，子像素300包括像素电路结构320，遮光层200位于像素电路结构320和衬底基板100之间，遮光层200中具有透光孔210(参考图2，图3中未示出透光孔)。
参考图1F，多个子像素包括沿第一方向相邻的第一子像素300A和第二子像素300B，该显示基板还包括：沿第一方向延伸的第一初始化信号线160A、发光控制信号线130，沿第二方向延伸的第一电源线150、第一数据线140A、第二数据线140B，第一方向和第二方向交叉，第一数据线140A与第一子像素300A的像素电路结构相连，第二数据线140B与第二子像素300B的像素电路结构相连，第一数据线140A和第二数据线140B分别位于第一电源线150的两侧，遮光层中的透光孔210位于第一电源线150、第二数据线140B、发光控制信号线130和第一初始化信号线160A围成的区域内。由此，应用该显示基板的显示装置具有较高的指纹识别灵敏度，且具有较高的分辨率。
根据本申请的实施例，该显示基板还包括指纹识别传感器(图中未示出)，指纹识别传感器设置在衬底基板远离遮光层的一侧，且透光孔在衬底基板上的正投影，与指纹识别传感器在衬底基板上的正投影具有至少部分重叠。指纹识别传感器用于采集从透光孔透过的光信号，并将光信号转换成电信号，提取指纹信息，经数据处理后实现指纹识别。本申请通过在显示基板中设置遮光层，并在遮光层中设置透光孔，基于小孔成像原理，在指纹识别过程中，经手指反射的部分光线可经透光孔射入指纹识别传感器中，实现指纹识别，而遮光层可对透光孔以外区域的光线进行遮挡，防止其他区域的光线对指纹识别过程造成干扰，由此，可提高应用该显示基板的显示装置的指纹识别灵敏度。关于遮光层的具体材料不受特别限制，例如，遮光层可以由金属材料形成。
根据本申请的实施例，参考图3，子像素300包括发光元件310和像素电路结构320，发光元件310位于像素电路结构320远离衬底基板100的一侧，发光元件310为有机发光二极管，有机发光二极管包括阳极、发光层和阴极。参考图4，像素电路结构320可以包括存储电容部80和多个薄膜晶体管(如第一薄膜晶体管10、第二薄膜晶体管20、第三薄膜晶体管30、第四薄膜晶体管40、第五薄膜晶体管50、第六薄膜晶体管60、第七薄膜晶体管70)，薄膜晶体管中的电极及各薄膜晶体管之间电连接的金属走线，以及存储电容部80的两个电极板均为不透光部。本申请中，透光孔210在衬底基板100上的正投影，与像素电路结构320中的不透光部在衬底基板100上的正投影无重叠区域。由此，像素电路结构中的不透光部不会遮挡需要射入透光孔中的光线，以实现指纹识别。并且，本申请中，透光孔210在衬底基板100上的正投影，与发光元件310的电极在衬底基板100上的正投 影也无重叠区域。本领域技术人员所熟知的是，有机发光二极管的阳极可以由透明导电材料或者金属材料形成，阴极可以由透明导电材料或者半透明导电材料形成。当发光元件的电极由金属材料或者半透明导电材料形成时，由于本申请的透光孔与发光元件的电极在衬底基板上的正投影不重叠，因此，发光元件的电极不会遮挡需要射入透光孔中的光线，以实现指纹识别。当发光元件的电极由透明导电材料形成时，令透光孔与发光元件的电极在衬底基板上的正投影不重叠，可以避免杂散光影响指纹识别。关于像素电路结构中的不透光部以及发光元件中的电极与透光孔的具体位置关系，详见后续描述。
发明人发现，目前显示装置的分辨率不断提高，使得子像素的尺寸越来越小，而子像素中的像素电路结构包括存储电容部和多个薄膜晶体管，像素电路结构占用子像素的面积较大，使得透光孔的设计较为困难。本申请不仅在显示基板中设置了遮光层，还对遮光层中透光孔的位置进行了优化，以使高分辨率的显示装置实现屏下指纹识别。
根据本申请的实施例，参考图1C，该显示基板还包括沿第一方向延伸的栅线120、复位控制信号线110和第二初始化信号线160B，在第二方向上，栅线120、复位控制信号线110和第二初始化信号线160B在发光控制信号线130远离第一初始化信号线160A的一侧依次排布，且第一子像素300A的像素电路结构和第二子像素300B的像素电路结构分别与第二初始化信号线160B相连(参考图1F)。由此，便于在子像素中预留出与透光孔相对应的区域，且上述用于施加信号的走线不会遮挡需要射入透光孔中的光线，以实现指纹识别。第二方向和第一方向交叉，具体的，第二方向与第一方向垂直，但不限于此。
需要说明的是，图1A为第一有源层321A的俯视示意图，图1B为形成在第一有源层321A远离衬底基板一侧的复位控制信号线110、栅线120、发光控制信号线130、存储电容部的下电极板81的俯视示意图，图1C为形成在复位控制信号线110、栅线120、发光控制信号线130、存储电容部的下电极板81远离衬底基板一侧的第一初始化信号线160A、第二初始化信号线160B、存储电容部的上电极板82的俯视示意图，图1D为在第一初始化信号线160A、第二初始化信号线160B、第一有源层321A、存储电容部的上电极板82、存储电容的下电极板81上设置过孔的示意图，图1E为形成在第一初始化信号线160A、第二初始化信号线160B、存储电容部的上电极板82远离衬底基板一侧的第一数据线140A、第二数据线140B、第一电源线150的俯视示意图。图1A-图1E示出了各结构之间的层叠顺序以及位置关系，且为了便于示出上述各结构的位置关系，图1A-图1E未示出各结构之间的绝缘层，上述各结构与绝缘层的层叠关系可参考图3。
根据本申请的实施例，参考图3，该显示基板还包括保护层400和缓冲层500，保护层400覆盖遮光层200，缓冲层500位于保护层400和像素电路结构320之间，像素电路结构320包括依次层叠设置在缓冲层500远离保护层400一侧的有源层321、第一绝缘层322、第一栅极金属层323、第二绝缘层324、第二栅极金属层325、层间介电层326、源漏金属层327和平坦化层328，其中，源漏金属层327的一部分通过贯穿层间介电层326、第二绝缘层324和第一绝缘层322的过孔，与有源层321相连，形成薄膜晶体管的源极327A和漏极327B，发光元件310包括依次层叠设置在平坦化层328远离层间介电层326一侧的阳 极311、像素界定层312、发光层313和阴极314，阳极311通过贯穿平坦化层328的过孔，与薄膜晶体管的源极或漏极相连，发光层313通过贯穿像素界定层312的过孔，与阳极311相连。第一栅极金属层323用于形成薄膜晶体管的栅极以及复位控制信号线、栅线、发光控制信号线、存储电容部的下电极板。第二栅极金属层325用于形成第一初始化信号线、第二初始化信号线以及存储电容部的上电极板。源漏金属层327用于形成薄膜晶体管的源极、漏极、第一数据线、第二数据线和第一电源线。关于上述各膜层的具体构成材料不受特别限制，本领域技术人员可以根据常用材料进行设计。其中，构成保护层400的材料可以包括氧化硅。根据本申请的实施例，参考图4，该显示基板还包括第二电源线(VSS)170，发光元件310的阴极314与第二电源线170相连。
本申请中，位于遮光层远离衬底基板一侧的各膜层具有较高的透光率(如保护层400、缓冲层500、第一绝缘层322、第二绝缘层324、层间介电层326、平坦化层328等膜层)，因此，仅需在遮光层中设置透光孔即可，在实现指纹识别的基础上，保证显示基板的稳定性。
根据本申请的实施例，参考图2，遮光层200中具有多个透光孔210，多个透光孔210呈周期排布(也即是说，在遮光层200中，任意两个透光孔210之间的距离是一致的)，每个透光孔210在衬底基板100上的正投影，位于一个子像素300在衬底基板100上的正投影(如图2中所示出的220)范围内。
需要说明的是，遮光层中多个透光孔的开口尺寸是一致的。关于透光孔的开口形状不受特别限制，例如，根据本申请的实施例，透光孔的开口形状可以为正方形，由此，可提高成像质量，获得更加清晰的指纹信息。
关于透光孔排布的具体周期不受特别限制，本领域技术人员可以根据具体情况进行设计。例如，可根据产品的分辨率、子像素的尺寸、遮光层远离衬底基板一侧各膜层的厚度及介电常数等进行设计。具体的，可以在8×8的像素单元阵列中设置一个透光孔，或者，可以在12×12的像素单元阵列中设置一个透光孔。在上述周期内，与第一子像素相邻的第二子像素内无透光孔。需要说明的是，每个像素单元可以包括多个子像素，而透光孔按照前面描述的位置进行设置。
根据本申请的实施例，参考图3，该显示基板还包括与遮光层200相连的连接电极327C，连接电极327C由源漏金属层327的一部分形成，连接电极327C通过贯穿层间介电层326、第二绝缘层324、第一绝缘层322、缓冲层500和保护层400的过孔，与遮光层200相连，连接电极327C可与第二电源线170(图3中未示出)相连。由此，可防止遮光层中形成静电。
下面以包括7个薄膜晶体管和1个存储电容部的像素电路结构(即7T1C像素电路结构)为例，对各薄膜晶体管和存储电容部之间的连接关系进行说明：
参考图4，第一薄膜晶体管10和第七薄膜晶体管70为复位控制晶体管，第二薄膜晶体管20为阈值补偿晶体管，第三薄膜晶体管30为驱动晶体管，第四薄膜晶体管40为数据写入晶体管，第五薄膜晶体管50和第六薄膜晶体管60为发光控制晶体管。
参考图1B，第一薄膜晶体管的栅极13与复位控制信号线110相连，参考图1B和图1E第一薄膜晶体管的源极11通过第一走线1与第二初始化信号线160B相连，参考图1D和图1E，第一走线1通过过孔14与第一薄膜晶体管的源极11相连，第一走线1通过过孔15与第二初始化信号线160B相连，参考图1B和图1E，第一薄膜晶体管的漏极12通过第二走线2与第三薄膜晶体管的栅极33相连，参考图1D和图1E，第二走线2通过过孔24与第一薄膜晶体管的漏极12相连，第二走线2通过过孔25与第三薄膜晶体管的栅极33相连。参考图1B，第七薄膜晶体管的栅极73与复位控制信号线110相连，参考图1B和图1E，第七薄膜晶体管的源极71通过第一走线1与第二初始化信号线160B相连，第七薄膜晶体管的漏极72与发光元件310的阳极311相连(图1中未示出)。
参考图1B，第二薄膜晶体管的栅极23与栅线120相连，参考图1B和图1E，第二薄膜晶体管的源极21通过第二走线2与第三薄膜晶体管的栅极33相连，第二薄膜晶体管的漏极22与第三薄膜晶体管的漏极32相连。
参考图1B，第四薄膜晶体管的栅极43与栅线120相连，参考图1E，第四薄膜晶体管的源极41通过过孔44与第一数据线140A相连，第四薄膜晶体管的漏极42与第三薄膜晶体管的源极31相连(参考图1B)。
参考图1B，第五薄膜晶体管的栅极53与发光控制信号线130相连，参考图1E，第五薄膜晶体管的源极51通过过孔54与第一电源线150相连，第五薄膜晶体管的漏极52与第三薄膜晶体管的源极31相连(参考图1B)(即第三薄膜晶体管的源极、第四薄膜晶体管的漏极和第五薄膜晶体管的漏极连接于节点N 2(参考图4))。参考图1B，第六薄膜晶体管的栅极63与发光控制信号线130相连，第六薄膜晶体管的源极61与第三薄膜晶体管的漏极32相连(即第二薄膜晶体管的漏极、第三薄膜晶体管的漏极和第六薄膜晶体管的源极连接于节点N 3(参考图4))，参考图1E，第六薄膜晶体管的漏极62通过过孔64与发光元件310的阳极311相连。
参考图1B和图1E，存储电容部80的下电极板81(参考图1B)通过第二走线2与第二薄膜晶体管的源极21相连(在图1E中，下电极板81与第二走线2相连的位置即为第三薄膜晶体管的栅极33与第二走线2相连的位置)(即第二薄膜晶体管的源极、第三薄膜晶体管的栅极和存储电容部的下电极板连接于节点N 1(参考图4))，参考图1C和图1E，存储电容部80的上电极板82与第一电源线150相连，上电极板82可通过两个过孔(如图1D和图1E中所示出的过孔84和85)与第一电源线150相连，以提高上电极板和第一电源线之间的电连接性能。
参考图4，复位控制信号线用于向第一薄膜晶体管10和第七薄膜晶体管70施加Reset信号，栅线用于向第四薄膜晶体管40和第二薄膜晶体管20施加Gate信号，发光控制信号线用于向第五薄膜晶体管50和第六薄膜晶体管60施加EM信号，第一数据线用于向第四薄膜晶体管40施加Vdata信号，第一电源线用于向第五薄膜晶体管50施加VDD信号，第二初始化信号线用于向第一薄膜晶体管10和第二薄膜晶体管70施加Vint信号。
根据本申请的实施例，参考图1C、图1D和图1E，该显示基板还包括连接部90，连 接部90通过过孔91与第一电源线150相连。由此，连接部可防止第一数据线对第一电源线造成信号干扰。
为了便于理解，下面首先对7T1C像素补偿电路的工作原理进行简单说明：
7T1C像素补偿电路的工作时序分为复位阶段、采样阶段、发光阶段，完成对像素阈值电压(Vth)的补偿。参考图7：
t1阶段(即复位阶段)，Reset信号为低电平。第一薄膜晶体管打开，Vint信号对N 1点进行初始化，此时N 1点电位为Vint，第三薄膜晶体管打开。第七薄膜晶体管打开，Vint降低发光元件阳极和阴极之间的电压差，在低灰阶时降低发光元件的亮度，提高像素的对比度。
t2阶段(即采样阶段)，Gate信号为低电平。第四薄膜晶体管打开，此时N 2点电位为Vdata，数据信号电压写入N 2点。第二薄膜晶体管打开，对第三薄膜晶体管连接进行采样，N 1点电位升高至Vdata+Vth，第三薄膜晶体管逐渐由打开状态变为关闭状态，对第三薄膜晶体管的阈值电压进行补偿。
t3阶段(即发光阶段)，EM信号为低电平。第五薄膜晶体管和第六薄膜晶体管打开，此时N 2点电位为VDD，第三薄膜晶体管输出驱动电流，发光元件发光。
在采样阶段对薄膜晶体管的阈值电压进行补偿，消除不同像素的驱动薄膜晶体管(即第三薄膜晶体管)阈值电压差异对显示亮度均一性的影响。
本申请中，透光孔210在第一方向上的宽度可以小于第一数据线和第二数据线之间距离的1/3，或者，透光孔210在第一方向上的宽度可以为第一数据线和第二数据线之间距离的1/3-1/2，或者，透光孔210在第一方向上的宽度可以大于第一数据线和第二数据线之间距离的1/2。具体如下：
根据本申请的一些实施例，参考图1E，在第一方向上，透光孔210的宽度可以小于第一数据线140A和第二数据线140B之间距离的1/3，此时，第一子像素300A的像素电路结构包括第一发光控制晶体管(即第五薄膜晶体管50)和第二发光控制晶体管(即第六薄膜晶体管60)，第一发光控制晶体管的第一极(如源极51)位于发光控制信号线130的第一侧，第一发光控制晶体管的第二极(如漏极52)位于发光控制信号线130的第二侧，第二发光控制晶体管的第二极(如漏极62)位于发光控制信号线130的第一侧，第二发光控制晶体管的第一极(如源极61)位于发光控制信号线130的第二侧，第一侧和第二侧为发光控制信号线130相对的两侧，透光孔210位于第一发光控制晶体管的第一极51和第二发光控制晶体管的第二极62之间。由此，发光控制晶体管的源漏极不会遮挡透光孔。本领域技术人员能够理解的是，驱动晶体管、复位控制晶体管、阈值补偿晶体管、数据写入晶体管和存储电容部均位于发光控制信号线远离第一初始化信号线的一侧，从而上述晶体管的源漏极以及存储电容部也不会遮挡透光孔。
参考图1F，第一子像素300A内具有透光孔210，第二子像素300B内不具有透光孔，当透光孔210的宽度小于第一数据线140A和第二数据线140B之间距离的1/3时，由于透光孔的尺寸较小，因此，复位控制信号线、栅线、发光控制信号线、第一数据线、第一电 源线以及像素电路结构中的各个元件在第一子像素内的位置，可以与其在第二子像素内的位置一致(参考图1F)，且第一有源层321A的大小与第二有源层321B的大小一致，第一有源层321A在第一子像素内的位置，与第二有源层321B在第二子像素内的位置一致(参考图1G)。
需要说明的是，“第一有源层”为第二初始化信号线、第一初始化信号线、第一数据线和第二数据线围成区域内的有源层，“第二有源层”为第二初始化信号线、第一初始化信号线、第二数据线和第三数据线140C(参考图1F)围成区域内的有源层。其中，第三数据线为沿第二方向延伸且与第三子像素的像素电路结构相连的数据线，第三子像素为在第一方向上与第二子像素相邻的子像素(参考图1F，图中仅示出了第三子像素中的第三数据线)。
根据本申请的另一些实施例，参考图5A-图5E，其中，图5A为第一有源层321A的俯视示意图，图5B为形成在第一有源层321A远离衬底基板一侧的复位控制信号线110、栅线120、发光控制信号线130、存储电容部的下电极板81的俯视示意图，图5C为形成在复位控制信号线110、栅线120、发光控制信号线130、存储电容部的下电极板81远离衬底基板一侧的第一初始化信号线160A、第二初始化信号线160B、存储电容部的上电极板82的俯视示意图，图5D为在第一初始化信号线160A、第二初始化信号线160B、第一有源层321A、存储电容部的上电极板82、存储电容的下电极板81上设置过孔的示意图，图5E为形成在第一初始化信号线160A、第二初始化信号线160B、存储电容部的上电极板82远离衬底基板一侧的第一数据线140A、第二数据线140B、第一电源线150的俯视示意图。图5A-图5E示出了各结构之间的层叠顺序以及位置关系，且为了便于示出上述各结构的位置关系，图5A-图5E未示出各结构之间的绝缘层，上述各结构与绝缘层的层叠关系可参考图3。
参考图5E，在第一方向上，透光孔210的宽度可以为第一数据线140A和第二数据线140B之间距离的1/3～1/2，此时，参考图5C和图5E，发光控制信号线130包括第一子部131、第二子部132和第三子部133，第一子部131位于第二子部132和第三子部133之间，第一子部131沿第一方向延伸，第二子部132和第三子部133沿第二方向延伸，在第一方向上，至少部分第二子部132位于第一电源线150和第二数据线140B之间，第一子像素300A的像素电路结构包括第一发光控制晶体管(即第五薄膜晶体管50)和第二发光控制晶体管(即第六薄膜晶体管60)，第一发光控制晶体管的第一极(如源极51)位于第一子部131的第一侧，第一发光控制晶体管的第二极(如漏极52)位于第一子部131的第二侧，第二发光控制晶体管的第二极(如漏极62)位于第一子部131的第一侧，第二发光控制晶体管的第一极(如源极61)位于第一子部131的第二侧，第一侧和第二侧为第一子部131相对的两侧，透光孔210位于第一电源线150、第二子部132、第二发光控制晶体管的第二极62、第一发光控制晶体管的第一极51和第一初始化信号线160A围成的区域内。
进一步地，参考图5E，在第一方向上，至少部分第三子部133，位于第一数据线140A远离第一电源线150的一侧，第二子部132位于第二发光控制晶体管的第二极62远离第一电源线150的一侧。由此，发光控制晶体管的源漏极不会遮挡透光孔，从而驱动晶体管、 复位控制晶体管、阈值补偿晶体管、数据写入晶体管的源漏极以及存储电容部也不会遮挡透光孔。
需要说明的是，由于发光控制信号线与第一数据线、第一电源线未设置在同一层，因此，“在第一方向上，至少部分第三子部位于第一数据线远离第一电源线的一侧”是指至少部分第三子部在衬底基板上的正投影，位于第一数据线在衬底基板上的正投影远离第一电源线在衬底基板上的正投影的一侧。类似的，“在第一方向上，至少部分第二子部位于第一电源线和第二数据线之间”是指至少部分第二子部在衬底基板上的正投影，位于第一电源线在衬底基板上的正投影和第二数据线在衬底基板上的正投影之间。
本实施例中，可将透光孔的尺寸做大，进一步提高指纹识别的灵敏度，且可应用在子像素尺寸较小的显示装置中。传统的指纹识别显示装置，通常是牺牲分辨率，在尺寸较大的子像素中设置开口尺寸较大的透光孔，也即是说，传统的指纹识别显示装置通常是在分辨率较低的显示装置中设置开口尺寸较大的透光孔。而本申请可在尺寸较小的子像素中设置开口尺寸较大的透光孔，由此，可以适用于分辨率较高的显示装置中，使得显示装置能够兼顾高分辨率和高指纹识别灵敏度。
更为具体的，参考图5F，第一子像素300A内具有透光孔210，第二子像素300B内不具有透光孔，参考图5C，复位控制信号线110包括沿第一方向延伸的第四子部111以及位于第四子部111两端的弯折部112，参考图5F，至少部分第四子部111位于第一数据线140A和第二数据线140B之间，参考图5C和图5F，栅线120包括第五子部121、第六子部122和第七子部123，第五子部121位于第六子部122和第七子部123之间，第五子部121沿第一方向延伸，第六子部122和第七子部123沿第二方向延伸，在第一方向上，至少部分第六子部122位于第一数据线140A和第二数据线140B之间，多个子像素包括沿第一方向与第二子像素300B相邻的第三子像素(图中未示出)，第三数据线140C沿第二方向延伸，且与第三子像素的像素电路结构相连，复位控制信号线110、栅线120和发光控制信号线130位于第二数据线140B和第三数据线140C之间的部分均沿第一方向延伸(参考图5F)，第四子部111与第五子部121之间的距离为D 1，复位控制信号线110位于第二数据线140B和第三数据线140C之间的部分，与栅线120位于第二数据线140B和第三数据线140C之间的部分之间的间距为D 2，D 1小于D 2，第五子部121与第一子部131之间的间距为D 3，栅线120位于第二数据线140B和第三数据线140C之间的部分，与发光控制信号线130位于第二数据线140B和第三数据线140C之间的部分之间的间距为D 4，D 3小于D 4。由此，通过缩窄第一子像素内各信号线之间的间距，以预留出较大的区域与透光孔相对应。
由于信号线之间的间距变小，因此，在本实施例中，第一子像素中存储电容部的面积也需小于第二子像素中存储电容部的面积。
进一步地，参考图5F和图5G，第一子像素300A的像素电路结构中的有源层位于第一初始化信号线160A、第二初始化信号线160B、第一数据线140A、第二数据线140B围成的区域内，第二子像素300B的像素电路结构中的有源层位于第一初始化信号线160A、第二初始化信号线160B、第二数据线140B、第三数据线140C围成的区域内，第一子像素 中的有源层为第一有源层321A，第二子像素中的有源层为第二有源层321B，第一有源层321A的宽度为D 7，第二有源层321B的宽度为D 8，D 7小于D 8，第一有源层321A的长度为L 1，第二有源层321B的长度为L 2，L 1小于L 2(参考图5G)。由此，通过缩小第一有源层的尺寸，以保证薄膜晶体管的源漏极与各信号线之间的连接。
需要说明的是，在本实施例中，第一子像素300A是正常发光的，因此，上述信号线之间间距的变窄，第一有源层尺寸变小，均需以第一子像素300A正常发光为前提。
根据本申请的实施例，由于第一有源层的尺寸变小，使得第一数据线140A与第四薄膜晶体管源极相连的过孔44的位置发生移动，以及使第一电源线150与第五薄膜晶体管源极相连的过孔54的位置发生移动(参考图5F)。因此，第一数据线140A和第一电源线150与第一子像素300A的像素电路结构相连的部分可具有弯折的结构(参考图5F)，如第一数据线140A和第一电源线150与第一子像素300A的像素电路结构相连的部分均向靠近透光孔210的一侧弯折，以使第一数据线140A能够向第四薄膜晶体管40施加信号，以及使第一电源线150能够向第五薄膜晶体管50施加信号。
根据本申请的实施例，当透光孔210的宽度为第一数据线140A和第二数据线140B之间距离的1/3～1/2时，第一子像素300A中的薄膜晶体管的有源层宽度和栅极长度的比值，与第二子像素300B中的薄膜晶体管的有源层宽度和栅极长度的比值一致。由此，可以保证第一子像素的显示亮度与第二子像素的显示亮度一致，保证整个显示画面亮度的均一性。需要说明的是，栅极的长度为栅极在其延伸方向上的尺寸，有源层的宽度为有源层在垂直于栅极延伸方向上的尺寸。
根据本申请的实施例，当透光孔210的宽度为第一数据线140A和第二数据线140B之间距离的1/3～1/2时，在第二方向上，第一子像素中的发光元件的阳极311位于第一子部131远离第二发光控制晶体管的第二极62的一侧(参考图5E)。即第一子像素300A中的发光元件相较于第二子像素300B中的发光元件向远离透光孔210的一侧发生了移动，以防止发光元件的电极遮挡透光孔，此时，第一子像素300A中第六薄膜晶体管的漏极62通过第三走线3与发光元件的阳极311相连(参考图5E)。
关于前面描述的第一子像素的发光颜色不受特别限制，例如，第一子像素可以为发红光的子像素，或者，第一子像素为发绿光的子像素，或者，第一子像素为发蓝光的子像素。也即是说，当透光孔的宽度不超过子像素宽度的1/2时，透光孔可以设置在遮光层中与发红光的子像素相对应的区域中，或者，可以设置在遮光层中与发绿光的子像素相对应的区域中，或者，可以设置在遮光层中与发蓝光的子像素相对应的区域中。
根据本申请的另一些实施例，参考图6A-图6D，其中，图6A为第一有源层321A的俯视示意图，图6B为形成在第一有源层321A远离衬底基板一侧的复位控制信号线110、栅线120、发光控制信号线130的俯视示意图，图6C为形成在复位控制信号线110、栅线120、发光控制信号线130远离衬底基板一侧的第一初始化信号线160A、第二初始化信号线160B的俯视示意图，图6D为形成在第一初始化信号线160A、第二初始化信号线160B远离衬底基板一侧的第一数据线140A、第二数据线140B、第一电源线150的俯视示意图。 图6A-图6D示出了各结构之间的层叠顺序以及位置关系，且为了便于示出上述各结构的位置关系，图6A-图6D未示出各结构之间的绝缘层，上述各结构与绝缘层的层叠关系可参考图3。
参考图6D，在第一方向上，透光孔210的宽度可以大于第一数据线140A和第二数据线140B之间距离的1/2，此时，参考图6C和图6D，发光控制信号线130包括第一子部131、第二子部132和第三子部133，第一子部131位于第二子部132和第三子部133之间，第一子部131沿第一方向延伸，第二子部132和第三子部133沿第二方向延伸，在第一方向上，至少部分第二子部132位于第一电源线150和第二数据线140B之间，参考图6A和图6E，第一子像素300A的像素电路结构中的有源层位于第一初始化信号线160A、第二初始化信号线160B、第一数据线140A、第二数据线140B围成的区域内，第一子像素300A中的有源层为第一有源层321A，参考图6B，第一有源层321A在衬底基板上的正投影，与栅线120和发光控制信号线130在衬底基板上的正投影无重叠区域(即第一有源层321A的部分区域是断开的，是不连续的，换句话说，第一子像素300A的像素电路结构不具有发光控制晶体管、驱动晶体管)，透光孔210位于第一电源线150、第一子部131、第二子部132和第一初始化信号线160A围成的区域内。
进一步地，参考图6D，在第一方向上，至少部分第三子部133，位于第一数据线140A和第一电源线150之间。由此，可以在第一子像素内预留出更大的区域与透光孔相对应。
由于第一子像素中需要设置像素电路结构，当透光孔的宽度大于第一数据线和第二数据线之间距离的1/2后，第一子像素剩余的面积已无法再设置完整的像素电路结构，因此，本实施例中，第一子像素可作为Dummy子像素，即第一子像素不发光，以减少薄膜晶体管的设置，甚至不设置薄膜晶体管，以保证第一子像素预留出更大的区域与透光孔相对应。本实施例中，透光孔的开口尺寸更大，可进一步提高指纹识别的灵敏度，且可应用在子像素尺寸较小的显示装置中，即本实施例可在尺寸较小的子像素中设置开口尺寸更大的透光孔，由此，可以适用于分辨率较高的显示装置中，使得显示装置能够兼顾高分辨率和高指纹识别灵敏度。
在本实施例中，进一步地，第一子像素中的第一有源层321A在衬底基板100上的正投影，还可以与复位控制信号线110在衬底基板100上的正投影无重叠区域。使第一子像素的像素电路结构中无复位控制晶体管、发光控制晶体管、阈值补偿晶体管、数据写入晶体管、驱动晶体管，可以减少漏电。本实施例中，可省去存储电容部下电极板的制作，简化工艺，并预留出更大的区域与透光孔相对应，且本申请保留部分第一有源层、部分源漏金属层和存储电容部的部分上电极板(参考图6C)，有利于保持显示基板制作过程中刻蚀工艺的均一性，且可以。
根据本申请的实施例，当透光孔210的宽度大于第一数据线140A和第二数据线140B之间距离的1/2时，第一子像素的发光元件中的阳极与发光层不接触。由于第一子像素不发光，因此，令发光元件的阳极和发光层不接触，可省去在像素界定层挖孔的工艺。
根据本申请的实施例，当透光孔210的宽度大于第一数据线140A和第二数据线140B 之间距离的1/2时，参考图6E，第一子像素300A内具有透光孔210，第二子像素300B内不具有透光孔，此时，同样满足D 1小于D 2，D 3小于D 4，D 7小于D 8，L 1小于L 2(参考图6E和图6F)，此处不再赘述。
需要说明的是，在本实施例中，由于第一子像素300A不发光，因此，相邻两个信号线之间的距离可继续缩小(相较于透光孔宽度为第一数据线和第二数据线之间距离的1/3-1/2的方案)，以便第一子像素300A中能够预留出更大的区域与透光孔对应。
在本实施例中，多个子像素包括沿第二方向与第一子像素300A相邻的第四子像素(图中未示出)，第四子像素为正常发光的子像素，第四子像素中发光层的材料与第一子像素中发光层的材料相同。由于第一子像素不发光，因此，令第四子像素发光层的材料与第一子像素发光层的材料相同，可以通过第四子像素进行亮度补偿，可保证显示装置的显示性能不发生显著降低。
例如，以红绿蓝(RGB)三原色方案为例，参考图8(图8仅示出了部分子像素)，在行方向上，每行按红色子像素(R)、两个沿列方向排布的绿色子像素(G)和蓝色子像素(B)排布，在列方向上，红色子像素位于该行中与上一行绿色子像素和蓝色子像素之间的区域相对应的位置处，绿色子像素位于该行中与上一行蓝色子像素和红色子像素之间的区域相对应的位置处，蓝色子像素位于该行中与上一行红色子像素和绿色子像素之间的区域相对应的位置处(即在列方向上，各子像素之间是错开排布的)。上述像素排布使得红色子像素和蓝色子像素被相邻的两个像素单元共用，例如，B 1、R 1和G 1构成一个像素单元，同时B 1、R 1和G 2构成另一个像素单元。且上述像素排布使得与绿色子像素(如G 2)相邻的子像素中有另外一个绿色子像素(如G 3)，当透光孔在第一方向上的宽度大于第一数据线和第二数据线之间距离的1/2时，将透光孔设置在一个绿色子像素中，如设置在G 2中(即第一子像素300A为绿色子像素G 2)，即G 2不发光，此时，B 1、R 1和G 1构成的像素单元发光不受影响，但B 1、R 1和G 2构成的像素单元发光会受到影响，此时，可以通过提高G 3的亮度，向B 1、R 1和G 2构成的像素单元进行绿光的亮度补偿，可缓解B 1、R 1和G 2构成的像素单元因G 2不发光造成的显示性能下降的问题，并且B 2、R 2和G 3构成的像素单元也能正常发光，使得显示装置整体上具有良好的显示性能。且发明人发现，当将透光孔设置在红色子像素或者蓝色子像素中时，显示装置显示时会出现明显的黑点。
根据本申请的实施例，该显示基板可以包括至少一个指纹识别区域，且指纹识别区域内具有前面描述的透光孔，例如，该显示基板可以具有一个指纹识别区域，在指纹识别时，手指需要按压特定的区域(即指纹识别区域)实现指纹识别。或者，该显示基板可以具有多个指纹识别区域，如显示基板的整个显示区内任意一个区域均可为指纹识别区域，在指纹识别时，手指可以按压任意一个区域实现指纹识别。
在本申请的另一方面，本申请提出了一种显示装置。根据本申请的实施例，该显示装置包括前面描述的显示基板。由此，该显示装置具有前面描述的显示基板的全部特征以及优点，在此不再赘述。总的来说，该显示装置具有较高的指纹识别灵敏度，且具有较高的分辨率。
在本申请的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请而不是要求本申请必须以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。另外，需要说明的是，本说明书中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (15)

  1. 一种显示基板，包括：
    衬底基板，包括显示区；
    多个子像素，位于所述显示区中，所述子像素包括像素电路结构，所述多个子像素包括沿第一方向相邻的第一子像素和第二子像素；
    遮光层，位于所述像素电路结构和所述衬底基板之间，所述遮光层中具有透光孔；
    第一初始化信号线，沿所述第一方向延伸；
    发光控制信号线，沿所述第一方向延伸；
    第一电源线，沿第二方向延伸，所述第一方向与所述第二方向交叉；
    第一数据线，沿所述第二方向延伸，所述第一数据线与所述第一子像素的像素电路结构相连；
    第二数据线，沿所述第二方向延伸，所述第二数据线与所述第二子像素的像素电路结构相连，所述第一数据线和所述第二数据线分别位于所述第一电源线的两侧；
    其中，所述透光孔位于所述第一电源线、所述第二数据线、所述发光控制信号线和所述第一初始化信号线围成的区域内。
  2. 根据权利要求1所述的显示基板，包括沿所述第一方向延伸的栅线、复位控制信号线和第二初始化信号线，在所述第二方向上，所述栅线、所述复位控制信号线和所述第二初始化信号线在所述发光控制信号线远离所述第一初始化信号线的一侧依次排布，所述第一子像素的像素电路结构和所述第二子像素的像素电路结构分别与所述第二初始化信号线相连。
  3. 根据权利要求1或2所述的显示基板，其中，在所述第一方向上，所述透光孔的宽度小于所述第一数据线和所述第二数据线之间距离的1/3，
    所述第一子像素的像素电路结构包括第一发光控制晶体管和第二发光控制晶体管，
    所述第一发光控制晶体管的第一极位于所述发光控制信号线的第一侧，所述第一发光控制晶体管的第二极位于所述发光控制信号线的第二侧，
    所述第二发光控制晶体管的第二极位于所述发光控制信号线的第一侧，所述第二发光控制晶体管的第一极位于所述发光控制信号线的第二侧，所述第一侧和所述第二侧为所述发光控制信号线相对的两侧，
    所述透光孔位于所述第一发光控制晶体管的第一极和所述第二发光控制晶体管的第二极之间。
  4. 根据权利要求1或2所述的显示基板，其中，在所述第一方向上，所述透光孔的宽度为所述第一数据线和所述第二数据线之间距离的1/3～1/2，
    所述发光控制信号线包括第一子部、第二子部和第三子部，所述第一子部位于所述第二子部和所述第三子部之间，所述第一子部沿所述第一方向延伸，所述第二子部和所述第三子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第二子部位于所述第一电源线和所述第二数据线之间，
    所述第一子像素的像素电路结构包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的第一极位于所述第一子部的第一侧，所述第一发光控制晶体管的第二极位于所述第一子部的第二侧，所述第二发光控制晶体管的第二极位于所述第一子部的第一侧，所述第二发光控制晶体管的第一极位于所述第一子部的第二侧，所述第一侧和所述第二侧为所述第一子部相对的两侧，
    所述透光孔位于所述第一电源线、所述第二子部、所述第二发光控制晶体管的第二极、所述第一发光控制晶体管的第一极和所述第一初始化信号线围成的区域内。
  5. 根据权利要求4所述的显示基板，其中，在所述第一方向上，至少部分所述第三子部，位于所述第一数据线远离所述第一电源线的一侧，所述第二子部位于所述第二发光控制晶体管的第二极远离所述第一电源线的一侧。
  6. 根据权利要求1或2所述的显示基板，其中，在所述第一方向上，所述透光孔的宽度大于所述第一数据线和所述第二数据线之间距离的1/2，
    所述发光控制信号线包括第一子部、第二子部和第三子部，所述第一子部位于所述第二子部和所述第三子部之间，所述第一子部沿所述第一方向延伸，所述第二子部和所述第三子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第二子部位于所述第一电源线和所述第二数据线之间，
    所述第一子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第一数据线、所述第二数据线围成的区域内，所述第一子像素中的有源层为第一有源层，
    所述第一有源层在所述衬底基板上的正投影，与所述栅线和所述发光控制信号线在所述衬底基板上的正投影无重叠区域，所述透光孔位于所述第一电源线、所述第一子部、所述第二子部和所述第一初始化信号线围成的区域内。
  7. 根据权利要求6所述的显示基板，其中，在所述第一方向上，至少部分所述第三子部，位于所述第一数据线和所述第一电源线之间。
  8. 根据权利要求4～7中任一项所述的显示基板，其中，所述复位控制信号线包括沿所述第一方向延伸的第四子部以及位于所述第四子部两端的弯折部，至少部分所述第四子部位于所述第一数据线和所述第二数据线之间，
    所述栅线包括第五子部、第六子部和第七子部，所述第五子部位于所述第六子部和所述第七子部之间，所述第五子部沿所述第一方向延伸，所述第六子部和所述第七子部沿所述第二方向延伸，在所述第一方向上，至少部分所述第六子部位于所述第一数据线和所述第二数据线之间，
    所述多个子像素包括沿所述第一方向与所述第二子像素相邻的第三子像素，第三数据线沿所述第二方向延伸，且与所述第三子像素的像素电路结构相连，所述复位控制信号线、所述栅线和所述发光控制信号线位于所述第二数据线和所述第三数据线之间的部分均沿所述第一方向延伸，
    所述第四子部与所述第五子部之间的距离为D 1，所述复位控制信号线位于所述第二数 据线和所述第三数据线之间的部分，与所述栅线位于所述第二数据线和所述第三数据线之间的部分之间的间距为D 2，所述D 1小于所述D 2，
    所述第五子部与所述第一子部之间的间距为D 3，所述栅线位于所述第二数据线和所述第三数据线之间的部分，与所述发光控制信号线位于所述第二数据线和所述第三数据线之间的部分之间的间距为D 4，所述D 3小于所述D 4。
  9. 根据权利要求8所述的显示基板，其中，所述第一子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第一数据线、所述第二数据线围成的区域内，所述第二子像素的像素电路结构中的有源层位于所述第一初始化信号线、所述第二初始化信号线、所述第二数据线、所述第三数据线围成的区域内，所述第一子像素中的有源层为第一有源层，所述第二子像素中的有源层为第二有源层，
    所述第一有源层的宽度为D 7，所述第二有源层的宽度为D 8，所述D 7小于所述D 8，
    所述第一有源层的长度为L 1，所述第二有源层的长度为L 2，所述L 1小于所述L 2。
  10. 根据权利要求8或9所述的显示基板，其中，在所述第一方向上，当所述透光孔的宽度为所述第一数据线和所述第二数据线之间距离的1/3～1/2时，所述第一子像素包括发光元件，所述发光元件位于所述像素电路结构远离所述衬底基板的一侧，在所述第二方向上，所述发光元件的阳极位于所述第一子部远离所述第二发光控制晶体管的第二极的一侧。
  11. 根据权利要求8～10中任一项所述的显示基板，其中，所述第一子像素的像素电路结构中的薄膜晶体管的有源层宽度和栅极长度的比值，与所述第二子像素的像素电路结构中的薄膜晶体管的有源层宽度和栅极长度的比值一致。
  12. 根据权利要求8或9所述的显示基板，其中，在所述第一方向上，当所述透光孔的宽度大于所述第一数据线和所述第二数据线之间距离的1/2时，
    所述第一子像素包括发光元件，所述发光元件位于所述像素电路结构远离所述衬底基板的一侧，所述发光元件中的阳极与发光层不接触。
  13. 根据权利要求12所述的显示基板，其中，所述第一有源层在所述衬底基板上的正投影，与所述复位控制信号线在所述衬底基板上的正投影无重叠区域。
  14. 根据权利要求1～13中任一项所述的显示基板，其中，所述显示基板包括至少一个指纹识别区域，所述指纹识别区域内具有所述透光孔。
  15. 一种显示装置，包括权利要求1-14任一项所述的显示基板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220028950A1 (en) * 2021-04-01 2022-01-27 Wuhan Tianma Micro-Electronics Co., Ltd. Display panel and display device
CN115020619A (zh) * 2022-07-08 2022-09-06 武汉华星光电半导体显示技术有限公司 显示面板及移动终端

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200409420A1 (en) * 2019-06-28 2020-12-31 Semiconductor Energy Laboratory Co., Ltd. Functional panel, semiconductor device, display device, input/output device, data processing device
CN115294936A (zh) * 2022-08-09 2022-11-04 京东方科技集团股份有限公司 显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298859A (zh) * 2016-09-30 2017-01-04 京东方科技集团股份有限公司 触控面板及显示装置
US20180053811A1 (en) * 2016-08-22 2018-02-22 Emagin Corporation Arrangement of color sub-pixels for full color oled and method of manufacturing same
CN210349260U (zh) * 2019-11-15 2020-04-17 京东方科技集团股份有限公司 显示面板、显示装置
KR20200047007A (ko) * 2018-10-26 2020-05-07 엘지디스플레이 주식회사 디스플레이 패널 및 디스플레이 장치
CN210535236U (zh) * 2019-11-15 2020-05-15 京东方科技集团股份有限公司 一种显示面板、显示装置
CN111477669A (zh) * 2020-05-09 2020-07-31 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180053811A1 (en) * 2016-08-22 2018-02-22 Emagin Corporation Arrangement of color sub-pixels for full color oled and method of manufacturing same
CN106298859A (zh) * 2016-09-30 2017-01-04 京东方科技集团股份有限公司 触控面板及显示装置
KR20200047007A (ko) * 2018-10-26 2020-05-07 엘지디스플레이 주식회사 디스플레이 패널 및 디스플레이 장치
CN210349260U (zh) * 2019-11-15 2020-04-17 京东方科技集团股份有限公司 显示面板、显示装置
CN210535236U (zh) * 2019-11-15 2020-05-15 京东方科技集团股份有限公司 一种显示面板、显示装置
CN111477669A (zh) * 2020-05-09 2020-07-31 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220028950A1 (en) * 2021-04-01 2022-01-27 Wuhan Tianma Micro-Electronics Co., Ltd. Display panel and display device
US11616109B2 (en) * 2021-04-01 2023-03-28 Wuhan Tianma Micro-Electronics Co., Ltd. Display panel and display device
CN115020619A (zh) * 2022-07-08 2022-09-06 武汉华星光电半导体显示技术有限公司 显示面板及移动终端
CN115020619B (zh) * 2022-07-08 2024-02-13 武汉华星光电半导体显示技术有限公司 显示面板及移动终端

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