WO2022037055A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022037055A1
WO2022037055A1 PCT/CN2021/082008 CN2021082008W WO2022037055A1 WO 2022037055 A1 WO2022037055 A1 WO 2022037055A1 CN 2021082008 W CN2021082008 W CN 2021082008W WO 2022037055 A1 WO2022037055 A1 WO 2022037055A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
auxiliary
area
orthographic projection
sub
Prior art date
Application number
PCT/CN2021/082008
Other languages
English (en)
French (fr)
Inventor
先建波
许晨
李盼
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000543.1A priority Critical patent/CN112823422A/zh
Priority to JP2021540246A priority patent/JP2023538464A/ja
Priority to KR1020217021679A priority patent/KR20230052784A/ko
Priority to US17/426,985 priority patent/US11985861B2/en
Priority to EP21743363.0A priority patent/EP3996145B1/en
Publication of WO2022037055A1 publication Critical patent/WO2022037055A1/zh
Priority to US18/594,819 priority patent/US20240206243A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • other electroluminescent diodes have the advantages of self-luminescence and low energy consumption, and are the most popular electroluminescent display devices in the field of application research today. One of the hot spots.
  • a transistor array layer located on the base substrate
  • a pixel defining layer located on the side of the transistor array layer away from the base substrate;
  • touch electrodes located on the side of the pixel defining layer away from the base substrate;
  • the base substrate has a display area, and the display area includes a plurality of sub-pixels; the sub-pixels include a pixel circuit and a light-emitting element; the pixel circuit includes a grid line pattern, a data line pattern, and a power signal line pattern;
  • the transistor array layer includes a plurality of capacitive conductive parts, and the sub-pixels include the corresponding capacitive conductive parts; wherein, in the same sub-pixel, the capacitive conductive parts and the data line patterns and patterns corresponding to the sub-pixels. /or an overlapping area exists between the power signal line patterns corresponding to the sub-pixels; the capacitive conductive portion is at least coupled to the power signal line patterns corresponding to the sub-pixels or the data line patterns corresponding to the sub-pixels;
  • the pixel defining layer includes a plurality of opening regions, and the sub-pixels include the corresponding opening regions;
  • At least part of the orthographic projection of the touch electrodes on the base substrate is a grid
  • the plurality of sub-pixels further include first-color sub-pixels, second-color sub-pixels and third-color sub-pixels; the area of the opening area of the first-color sub-pixel is smaller than that of the third-color sub-pixel , and the area of the opening area of the second color sub-pixel is smaller than the area of the opening area of the third color sub-pixel;
  • the orthographic projection of the capacitive conductive portion in the first color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a first auxiliary overlapping area
  • the orthographic projection of the capacitive conductive portion in the second color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a second auxiliary overlapping area
  • the orthographic projection of the capacitive conductive portion in the third color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a third auxiliary overlapping area
  • At least one of the first auxiliary overlapping area and the second auxiliary overlapping area is larger than the third auxiliary overlapping area.
  • the first auxiliary overlap area is larger than the second auxiliary overlap area
  • the first auxiliary overlapping area is substantially equal to the second auxiliary overlapping area; or, the third auxiliary overlapping area is substantially equal to the second auxiliary overlapping area.
  • the transistor array layer includes:
  • first conductive layer located between the base substrate and the pixel defining layer; wherein the first conductive layer includes a plurality of data line patterns and a plurality of power signal line patterns;
  • a first insulating layer located between the base substrate and the first conductive layer
  • the second conductive layer is located between the base substrate and the first insulating layer, and the second conductive layer includes: a plurality of auxiliary conductive parts, and the capacitance conductive part of the sub-pixel includes the auxiliary conductive part ; wherein, in the same sub-pixel, the orthographic projection of the first end of the auxiliary conductive portion on the base substrate and the orthographic projection of the power signal line pattern on the base substrate have an overlapping area, so The orthographic projection of the second end of the auxiliary conductive portion on the base substrate and the orthographic projection of the data line pattern on the base substrate have an overlapping area; and the auxiliary conductive portion is coupled to the power signal line pattern;
  • the first auxiliary overlapping area includes the overlap between the orthographic projection of the auxiliary conductive portion in the first color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area;
  • the second auxiliary overlapping area includes an overlap between the orthographic projection of the auxiliary conductive portion in the second color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area;
  • the third auxiliary overlapping area includes the overlap between the orthographic projection of the auxiliary conductive portion in the third color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area.
  • the auxiliary conductive portion in the first color sub-pixel includes a first auxiliary exposed portion, and the orthographic projection of the first auxiliary exposed portion on the base substrate is respectively different from the data line pattern and the data line pattern.
  • the orthographic projections of the power signal line patterns on the base substrate do not overlap; and the first auxiliary overlapping area includes a first auxiliary sub-overlapping area, and the first auxiliary exposed portion is on the base substrate
  • the overlapping area between the orthographic projection of the touch electrode and the orthographic projection of the touch electrode on the base substrate has a first auxiliary sub-overlapping area;
  • the auxiliary conductive part in the second color sub-pixel includes a second auxiliary exposed part, and the orthographic projection of the second auxiliary exposed part on the base substrate is respectively associated with the data line pattern and the power signal line pattern
  • the orthographic projection on the base substrate does not overlap; and the second auxiliary overlapping area includes a second auxiliary sub-overlapping area, and the orthographic projection of the second auxiliary exposed portion on the base substrate is the same as the second auxiliary overlapping area.
  • the overlapping area of the touch electrodes between the orthographic projections of the base substrate has a second auxiliary sub-overlapping area;
  • the auxiliary conductive part in the third color sub-pixel includes a third auxiliary exposed part, and the orthographic projection of the third auxiliary exposed part on the base substrate is respectively associated with the data line pattern and the power signal line pattern
  • the orthographic projection on the base substrate does not overlap; and the third auxiliary overlapping area includes a third auxiliary sub-overlapping area, and the orthographic projection of the third auxiliary exposed portion on the base substrate and the The overlapping area of the touch electrodes between the orthographic projections of the base substrate has a third auxiliary sub-overlapping area;
  • the first auxiliary sub-overlap area is larger than at least one of the second auxiliary sub-overlap area and the third auxiliary sub-overlap area.
  • the second auxiliary sub-overlap area is larger than the third auxiliary sub-overlap area; alternatively, the third auxiliary sub-overlap area is substantially equal to the second auxiliary sub-overlap area.
  • the orthographic projection of the first auxiliary exposed portion on the base substrate is located on the base substrate of the data line pattern and the power signal line pattern. between orthographic projections; and/or,
  • the orthographic projection of the second auxiliary exposed portion on the base substrate is located between the data line pattern and the orthographic projection of the power signal line pattern on the base substrate; and / or,
  • the orthographic projection of the third auxiliary exposed portion on the base substrate is located between the orthographic projection of the data line pattern and the power signal line pattern on the base substrate.
  • the auxiliary conductive portion has a total area in an orthographic projection of the base substrate
  • the range of the ratio between the overlapping area of the first auxiliary sub-subs and the total area is: 1/3 ⁇ 2/3; and/or,
  • the range of the ratio between the overlapping area of the second auxiliary sub-subs and the total area is: 0-1/4; and/or,
  • the range of the ratio between the overlapping area of the third auxiliary sub-subs and the total area is 0 ⁇ 1/16.
  • the orthographic projection of the touch electrodes on the base substrate covers the orthographic projection of the first auxiliary exposed portion on the base substrate;
  • the orthographic projection of the touch electrodes on the base substrate covers the orthographic projection of the second auxiliary exposed portion on the base substrate;
  • the orthographic projection of the touch electrodes on the base substrate covers the orthographic projection of the third auxiliary exposed portion on the base substrate.
  • the auxiliary conductive portion in the first color sub-pixel further includes a first auxiliary shielding portion, and the orthographic projection of the first auxiliary shielding portion on the base substrate is the same as the data line pattern and all the data lines. At least one of the power signal line patterns overlaps the orthographic projection of the base substrate; wherein, the width of the first auxiliary exposed portion in the column direction is smaller than the width of the first auxiliary shielding portion in the column direction. width; and/or,
  • the auxiliary conductive part in the second color sub-pixel further includes a second auxiliary shielding part, and the orthographic projection of the second auxiliary shielding part on the base substrate is related to the data line pattern and the power signal line pattern At least one of the orthographic projections of the base substrate overlaps; wherein, the width of the second auxiliary exposed portion in the column direction is smaller than the width of the second auxiliary shielding portion in the column direction; and/or ,
  • the auxiliary conductive part in the third color sub-pixel further includes a third auxiliary shielding part, and the orthographic projection of the third auxiliary shielding part on the base substrate is related to the data line pattern and the power signal line pattern At least one of the orthographic projections of the base substrate overlaps; wherein, the width of the third auxiliary exposed portion in the column direction is smaller than the width of the third auxiliary shielding portion in the column direction.
  • the pixel circuit further includes a first capacitor
  • the orthographic projection of the first capacitor in the first color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a first storage overlap area
  • the orthographic projection of the first capacitor in the second color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a second storage overlap area
  • the orthographic projection of the first capacitor in the third color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate have a third storage overlap area
  • At least one of the first storage overlap area and the second storage overlap area is larger than the third storage overlap area.
  • the first storage overlap area is larger than the second storage overlap area.
  • the second conductive layer further includes a plurality of storage conductive portions spaced from the auxiliary conductive portion; the sub-pixel includes the storage conductive portion; the storage conductive portion serves as the first capacitor the second plate;
  • the first storage overlap area includes the overlap between the orthographic projection of the storage conductive portion in the first color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area;
  • the second storage overlap area includes the overlap between the orthographic projection of the storage conductive portion in the second color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area;
  • the third storage overlap area includes the overlap between the orthographic projection of the storage conductive portion in the third color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate area.
  • the shape of the orthographic projection of the touch electrodes on the base substrate is a grid, and the orthographic projection of the touch electrodes on the base substrate and the opening area are on the substrate The orthographic projections of the base substrates do not overlap.
  • the touch electrode includes a first electrode part and a second electrode part; wherein, the orthographic projection of the first electrode part on the base substrate and the auxiliary conductive part on the base substrate
  • the orthographic projection of the second electrode portion has an overlapping area, and the orthographic projection of the second electrode portion on the base substrate does not overlap with the orthographic projection of the auxiliary conductive portion on the base substrate;
  • the width of the first electrode portion is greater than the width of the second electrode portion.
  • the display panel further includes:
  • a light-emitting functional layer located between the pixel defining layer and the touch electrodes, and the light-emitting functional layer includes a plurality of first-color light-emitting layers, a plurality of second-color light-emitting layers, and a plurality of third-color light-emitting layers;
  • the orthographic projection of the first color light-emitting layer on the base substrate covers the orthographic projection of the opening region in the first color sub-pixel on the base substrate;
  • the orthographic projection of the second color light-emitting layer on the base substrate covers the orthographic projection of the opening region in the second color sub-pixel on the base substrate;
  • the orthographic projection of the light-emitting layer of the third color on the base substrate covers the orthographic projection of the opening region in the sub-pixel of the third color on the base substrate.
  • the orthographic projections of the touch electrodes located between the adjacent opening regions on the base substrate overlap with the orthographic projections of the light-emitting layers of at least two different colors on the base substrate.
  • the orthographic projection of the touch electrodes surrounding the opening region of the third color sub-pixel on the base substrate is located within the orthographic projection of the third color light-emitting layer on the base substrate; and /or,
  • the orthographic projection of the touch electrodes surrounding the opening region of the second color sub-pixel on the base substrate is located within the orthographic projection of the second color light-emitting layer on the base substrate; and/or,
  • the orthographic projection of the touch electrodes surrounding the opening area of the first color sub-pixel on the base substrate is located within the orthographic projection of the first color light-emitting layer on the base substrate.
  • the third-color light-emitting layer and the second-color light-emitting layer are adjacent to each other, and the third-color light-emitting layer is located at the boundary of the orthographic projection of the base substrate and the touch electrodes. There is a first minimum distance between the boundary of the orthographic projection of the base substrate, the boundary of the orthographic projection of the second color light-emitting layer on the base substrate and the orthographic projection of the touch electrode on the base substrate have the second smallest distance between the boundaries of ;
  • the first minimum distance is greater than the second minimum distance.
  • the area enclosed by the orthographic projection of the touch electrodes surrounding the opening area of the first color sub-pixel on the base substrate is the first grid area
  • the area enclosed by the orthographic projection of the touch electrode surrounding the opening area of the second color sub-pixel on the base substrate is the second grid area
  • the area enclosed by the orthographic projection of the touch electrodes surrounding the opening area of the third color sub-pixel on the base substrate is the third grid area
  • the third grid area is greater than the second grid area and the first grid area is greater.
  • the display panel includes a plurality of repeating units; the repeating units include the first color subpixels, the second color subpixels, and the third color subpixels.
  • the repeating unit further includes a fourth color sub-pixel; the area enclosed by the orthographic projection of the touch electrode surrounding the opening area of the fourth color sub-pixel on the base substrate is the fourth color grid area;
  • the first grid area corresponding to the first color sub-pixel is greater than or substantially equal to the fourth grid area corresponding to the fourth color sub-pixel.
  • the opening area of the third color sub-pixel and the opening area of the first color sub-pixel are arranged along a first direction;
  • the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the third color sub-pixel has a first width perpendicular to the first direction;
  • the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the first color sub-pixel has a second width perpendicular to the first direction;
  • the first width is greater than the second width.
  • the opening area of the second color sub-pixel and the opening area of the fourth color sub-pixel are arranged along a first direction;
  • the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the second color sub-pixel has a third width perpendicular to the first direction;
  • the area surrounded by the inner boundary of the touch electrode of the opening area of the fourth color sub-pixel has a fourth width perpendicular to the first direction;
  • the third width is greater than the fourth width.
  • the extension direction of the grid lines of the touch electrodes having an overlapping area with the orthographic projection of the auxiliary conductive portion has an included angle ⁇ with the third direction; and 15° ⁇ 60°; wherein, the The third direction is substantially perpendicular to the extending direction of the data line pattern.
  • tan ⁇ A1/A2; wherein, A1 represents the width of the auxiliary conductive portion in the third direction perpendicular to the third direction, and A2 represents the width of the auxiliary conductive portion in the third direction.
  • the extending direction of the grid lines of the touch electrodes having an overlapping area with the orthographic projection of the auxiliary conductive portion in the first color sub-pixel and the third direction have a first included angle
  • an extension direction of the grid lines of the touch electrodes having an overlapping area with the orthographic projection of the auxiliary conductive portion in the sub-pixel of the second color and the third direction have a second included angle
  • an extension direction of the grid lines of the touch electrodes having an overlapping area with the orthographic projection of the auxiliary conductive portion in the sub-pixels of the third color and the third direction have a third included angle
  • the first included angle is smaller than the second included angle is smaller than the third included angle.
  • the opening areas of the adjacent four sub-pixels are regarded as an opening group, and the orthographic projection of the grid intersection of the touch electrodes on the base substrate is located in the opening group on the base substrate. in the area enclosed by the orthographic projection of .
  • the orthographic projection of the grid intersection of the touch electrodes on the base substrate is substantially located at the center of an area enclosed by the orthographic projection of the opening group on the base substrate.
  • the emission color of the fourth color sub-pixel is the same as that of the first color sub-pixel.
  • each of the subpixels further includes a first electrode
  • the overlapping area between the orthographic projection of the first electrode in the first color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate has a first anode overlap area
  • the overlapping area between the orthographic projection of the first electrode in the second color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate has a second anode overlap area
  • the overlapping area between the orthographic projection of the first electrode in the third color sub-pixel on the base substrate and the orthographic projection of the touch electrode on the base substrate has a third anode overlap area
  • At least one of the first anode overlap area and the second anode overlap area is larger than the third anode overlap area.
  • the first anode overlap area is greater than the second anode overlap area; or,
  • the first anode overlap area is substantially equal to the second anode overlap area.
  • a transistor array layer located on the base substrate
  • a pixel defining layer located on the side of the transistor array layer away from the base substrate;
  • touch electrodes located on the side of the pixel defining layer away from the base substrate;
  • the base substrate has a display area, and the display area includes a plurality of sub-pixels; the sub-pixels include a pixel circuit and a light-emitting element; the pixel circuit includes a grid line pattern, a data line pattern, and a power signal line pattern;
  • the transistor array layer includes a plurality of capacitive conductive parts, and the sub-pixel includes the corresponding capacitive conductive parts; wherein, in the same sub-pixel, the capacitive conductive parts correspond to the data line patterns and the sub-pixels. /or an overlapping area exists between the power signal line patterns corresponding to the sub-pixels; the capacitive conductive portion is at least coupled to the power signal line patterns corresponding to the sub-pixels or the data line patterns corresponding to the sub-pixels;
  • the pixel defining layer includes a plurality of opening regions, and the sub-pixels include the corresponding opening regions;
  • At least part of the orthographic projection of the touch electrodes on the base substrate is a grid
  • the transistor array layer further includes a first conductive layer, and the capacitor conductive portion is formed on the first conductive layer;
  • the pixel circuit includes a plurality of transistors, and sources and drains of at least some of the transistors are formed on the first conductive layer.
  • the capacitive conductive portion has an arc or irregular pattern.
  • the capacitive conductive portion includes an auxiliary conductive portion, and the auxiliary conductive portion at least partially overlaps with the power signal line pattern, the data line pattern, and the touch electrodes.
  • the power signal line patterns of the sub-pixels in two adjacent columns are electrically connected through a power input line; or the power signal line patterns corresponding to the sub-pixels in two adjacent columns of the same color are electrically connected through a power supply Input line electrical connection.
  • the power input lines and the power signal line patterns are located on different layers.
  • the width of the power signal line pattern is greater than the width of the data line pattern.
  • the data line pattern and the power signal line pattern are not arranged on the same conductive layer; or, the data line pattern and the power input line are not arranged on the same conductive layer.
  • the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer arranged in layers, and a first sub-insulating layer is disposed between the first sub-conductive layer and the second sub-conductive layer.
  • the overlapping area of the capacitive conducting part and the power signal line pattern is larger than the overlapping area of the capacitive conducting part and the data line pattern.
  • the pixel circuit includes: a seventh transistor and a second transistor; a gate of the seventh transistor is coupled to a second reset signal line pattern, and a gate of the second transistor is coupled to the first reset signal Line patterns are coupled; the first reset signal line pattern and the second reset signal line pattern transmit different signals.
  • the pixel circuit includes: a data writing transistor, a first transistor; the gate line pattern coupled to the gate of the data writing transistor, coupled to the gate of the first transistor The gate line patterns transmit different timing signals.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of some display panels in an embodiment of the disclosure
  • Fig. 2 is a partial cross-sectional structural schematic diagram of the display panel shown in Fig. 1 along the AA' direction;
  • FIG. 3 is a schematic structural diagram of some pixel circuits in an embodiment of the disclosure.
  • FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure.
  • FIG. 5a is a schematic diagram of a layout structure of some display panels in an embodiment of the disclosure.
  • FIG. 5b is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • Fig. 5c is a schematic cross-sectional structure diagram of the display panel shown in Fig. 5a along the AA' direction;
  • Fig. 5d is a schematic cross-sectional structure diagram of the display panel shown in Fig. 5a along the BB' direction;
  • FIG. 5e is a schematic cross-sectional structure diagram of the display panel shown in FIG. 5a along the CC' direction;
  • Figure 5f is a schematic cross-sectional structure diagram of the display panel shown in Figure 5a along the DD' direction;
  • 5g is a schematic diagram of a layout structure of a first color sub-pixel in an embodiment of the disclosure.
  • FIG. 5h is a schematic diagram of a layout structure of a second color sub-pixel in an embodiment of the disclosure.
  • FIG. 5i is a schematic diagram of a layout structure of a third color sub-pixel in an embodiment of the disclosure.
  • 6a is a schematic structural diagram of some semiconductor layers in an embodiment of the disclosure.
  • 6b is a schematic structural diagram of some third conductive layers in an embodiment of the disclosure.
  • 6c is a schematic structural diagram of some second conductive layers in an embodiment of the disclosure.
  • 6d is a schematic structural diagram of some first conductive layers in an embodiment of the disclosure.
  • FIG. 6e is a schematic structural diagram of some first electrode layers in an embodiment of the disclosure.
  • 6f is a schematic structural diagram of some light-emitting functional layers in an embodiment of the disclosure.
  • 6g is a schematic structural diagram of some second touch electrodes in an embodiment of the disclosure.
  • FIG. 7a is a schematic structural diagram of further semiconductor layers in an embodiment of the disclosure.
  • FIG. 7b is a schematic structural diagram of further third conductive layers in an embodiment of the disclosure.
  • FIG. 7c is a schematic structural diagram of further second conductive layers in an embodiment of the disclosure.
  • FIG. 7d is a schematic structural diagram of still some first conductive layers in an embodiment of the disclosure.
  • FIG. 7e is a schematic structural diagram of still some first electrode layers in an embodiment of the disclosure.
  • FIG. 7f is a schematic structural diagram of further light-emitting functional layers in an embodiment of the disclosure.
  • 7g is a schematic structural diagram of still some first sub-conducting layers in an embodiment of the disclosure.
  • FIG. 7h is a schematic structural diagram of further second sub-conducting layers in an embodiment of the disclosure.
  • FIG. 8a is a schematic structural diagram of some touch electrodes in an embodiment of the disclosure.
  • FIG. 8b is a schematic structural diagram of further touch electrodes in the embodiment of the disclosure.
  • FIG. 8c is a schematic structural diagram of further touch electrodes in the embodiment of the disclosure.
  • FIG. 8d is a schematic cross-sectional structural diagram of the touch electrode shown in FIG. 8c along the AA' direction;
  • FIG. 9a is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 9b is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 9c is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 10a is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 10b is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 13a is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 13b is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 14a is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 14b is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • FIG. 15 is a schematic diagram of the layout structure of further display panels according to an embodiment of the disclosure.
  • the display panel provided by the embodiment of the present disclosure may include: a base substrate 1000 , a transistor array layer ZA located on the base substrate 1000 , and a transistor array layer ZA located on a side away from the base substrate 1000
  • the base substrate 1000 has a display area AA and a non-display area surrounding the display area.
  • the display area has multiple sub-pixels spx.
  • the non-display area has a barrier wall BK surrounding the display area AA.
  • the non-display area may further include circuit structures such as driving circuits, for example, structures such as gate driver on array (GOA) of the array substrate, which will not be repeated here.
  • GOA gate driver on array
  • the sub-pixel spx may include: a pixel circuit and a light-emitting element.
  • the pixel circuit has transistors and capacitors for driving the light-emitting element to emit light.
  • 7T2C ie, 7 thin film transistors and 2 capacitors
  • the display panel may include different pixel circuits, eg, more or less than 7 thin film transistors, and one or more capacitors.
  • the sub-pixels may include: a gate line pattern GATE (abbreviated as GA), a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, and a data line pattern DATA (abbreviated as DA), a light emission control signal line pattern EM, a power supply signal line pattern VDD, a second reset signal line pattern RST2, and a second initialization signal line pattern VINT2.
  • GA gate line pattern
  • RST1 a first reset signal line pattern
  • VINT1 a first initialization signal line pattern
  • DATA abbreviated as a data line pattern DATA
  • EM light emission control signal line pattern
  • VDD power supply signal line pattern
  • RST2 second reset signal line pattern
  • VINT2 second initialization signal line pattern
  • the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may transmit different signals.
  • the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may be located at different layers.
  • the first reset signal line pattern RST1 is on the same layer as the gate line pattern GA
  • the second reset signal line pattern RST2 is on the same layer as the data line pattern DA or the power signal line pattern VDD.
  • the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may transmit the same signal.
  • the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may also transmit different signals.
  • VINT1 is V1
  • VINT2 is V1 ⁇ 5V.
  • the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may be located at different layers.
  • the first initialization signal line pattern VINT1 is at the same layer as the gate line pattern GA
  • the second initialization signal line pattern VINT2 is at the same layer as the data line pattern DA or the first reset signal line pattern RST1.
  • the pixel circuit in the sub-pixel may include: a first transistor T1, a second transistor T2, a third transistor T3, a data writing transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 , the first capacitor Cst and the second capacitor C1.
  • each transistor included in the pixel circuit adopts P-type transistors.
  • the first transistor T1 may have a double gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern GA, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the first transistor T1 The drain D1 is coupled to the gate 203g of the third transistor T3.
  • the first transistor T1 may have a single-gate structure or a multi-gate structure, which is not limited herein.
  • the second transistor T2 may have a double gate structure, the gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, the second The drain D2 of the transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 may be a single-gate structure or a multi-gate structure, which is not limited herein.
  • the gate 204g of the data writing transistor T4 is coupled to the gate line pattern GA
  • the source S4 of the data writing transistor T4 is coupled to the data line pattern DA
  • the drain D4 of the data writing transistor T4 and the source of the third transistor T3 Pole S3 is coupled.
  • the gate line pattern GA coupled to the gate 204g of the data writing transistor T4 and the gate line pattern GA coupled to the gate 201g of the first transistor T1 may transmit different timing signals, which are not limited herein.
  • the gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 Pole S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM
  • the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3
  • the drain D6 of the sixth transistor T6 is coupled to the light-emitting element L the anode coupling.
  • the light-emitting control signal line pattern EM coupled to the gate 205g of the fifth transistor T5 and the light-emitting control signal line pattern EM coupled to the gate 206g of the sixth transistor T6 can transmit different timing signals, which are not described here. limited.
  • the gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light emitting element L, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line
  • the graphics VINT2 is coupled.
  • the first plate Cst1 of the first capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.
  • the first end of the second capacitor C1 (ie the first plate C11 ) is coupled to the first end of the data writing transistor (such as the data line pattern DA), and the second end of the second capacitor C1 (such as the second plate C12 )
  • the power signal line pattern VDD is coupled.
  • the first plate C11 of the second capacitor C1 is coupled to the data line pattern DA and/or the data writing transistor T4, and the second plate C12 of the second capacitor C1 is coupled to the power signal line pattern VDD.
  • the second plate C12 of the second capacitor C1 is electrically connected to the power signal line pattern VDD, and the first plate C11 of the second capacitor C1 extends below or above the data line pattern DA, so that the first plate The orthographic projection of C12 and the data line pattern DA on the base substrate overlaps.
  • the first end of the data writing transistor T4 may also be the source (or source region, eg, S4 in FIG. 3 ), or the drain (or drain region, eg, FIG. 3 ) of the data writing transistor T4 D4 of 3), or the gate (eg: 204g of Figure 3).
  • S and D in FIG. 3 are only a kind of reference numerals for distinguishing description.
  • the first end of the data writing transistor T4 may also be a connection structure between the source of the data writing transistor T4 and the data line pattern DA.
  • one working cycle includes a first reset period P1 , a write compensation period P2 , a second reset period P3 and a light-emitting period P4 .
  • the first reset signal input from the first reset signal line pattern RST1 is at an active level
  • the second transistor T2 is turned on
  • the initialization signal transmitted from the first initialization signal line pattern VINT1 is input to the third transistor T3
  • the gate 203g of the third transistor T3 is reset. For example, the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared to zero.
  • the first reset signal is at an inactive level
  • the second transistor T2 is turned off
  • the gate scan signal input from the gate line pattern GA is at an active level
  • the first transistor T1 and the data writing transistor T4 are controlled to conduct
  • the data line pattern DA writes the data signal and transmits it to the source S3 of the third transistor T3 through the data writing transistor T4.
  • the first transistor T1 and the data writing transistor T4 are turned on, so that the third transistor T3 forms It is a diode structure, so the first transistor T1, the third transistor T3 and the data writing transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the third transistor T3 can be controlled.
  • the potential of the gate 203g finally reaches Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the gate scan signal is at an inactive level
  • the first transistor T1 and the data writing transistor T4 are both turned off
  • the second reset signal input from the second reset signal line RST2 is at an active level, controlling the seventh
  • the transistor T7 is turned on, the initialization signal transmitted from the second initialization signal line pattern VINT2 is input to the anode of the light-emitting element L, and the light-emitting element L is controlled not to emit light.
  • the light-emitting control signal written by the light-emitting control signal line pattern EM is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power supply signal transmitted by the power supply signal line pattern VDD is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is The voltage value corresponding to the power supply signal, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element L, and drives the corresponding light-emitting element L to emit light.
  • the active level when the transistor is a P-type transistor, the active level may be a low level, and the inactive level may be a high level.
  • the transistor when the transistor is an N-type transistor, the active level can be a high level, and the inactive level can be a low level.
  • the transistors of the pixel circuit may be both P-type transistors or N-type transistors, or may include both P-type transistors and N-type transistors, for example: T3 transistor is a P-type transistor, and T1 is an N-type transistor. It can be understood that FIG. 4 is only an exemplary introduction to the working timing of the pixel circuit, and signals such as RST1 , RST2 , Ga, EM, Da can be adaptively adjusted according to the transistor type of the pixel circuit and the actual situation.
  • each film layer is as follows: the semiconductor layer 400 and the gate insulating layer 910 are sequentially stacked along the direction away from the base substrate 1000 . , the third conductive layer 300 , the interlayer dielectric layer 920 , the second conductive layer 200 , the first interlayer insulating layer 930 , the first conductive layer 100 and the second interlayer insulating layer 940 . It can be understood that other metal layers or insulating layers may also be included between the base substrate 1000 and the semiconductor layer 400 .
  • at least one buffer layer or organic insulating layer is further included between the base substrate 1000 and the semiconductor layer 400.
  • the buffer layer may be silicon oxide or silicon nitride, and the organic insulating layer may be polyimide.
  • the semiconductor layer 400 is used to form the channel region (for example: 101pg-107pg), the source formation region (for example: 101ps-107ps) of each transistor in the pixel circuit, Drain formation region (eg: 101pd ⁇ 107pd) and connection formation region (eg: 101px, 102px), etc.
  • the channel region for example: 101pg-107pg
  • the source formation region for example: 101ps-107ps
  • Drain formation region eg: 101pd ⁇ 107pd
  • connection formation region eg: 101px, 102px
  • LDD lightly doped drain
  • the LDD region doped with low-concentration impurities is formed between the drain formation region of at least one transistor (eg 101pd to 107pd) and the channel region of the transistor (eg 101pg to 107pg), and the source formation region of the transistor (eg 101pg to 107pg) : 101ps ⁇ 107ps) and the channel region of the transistor (eg: 101pg ⁇ 107pg).
  • the semiconductor layer 400 corresponding to the source formation region and the drain formation region has better conductivity than the semiconductor layer 400 corresponding to the channel region due to doping.
  • the semiconductor layer 400 can be made of amorphous silicon, polysilicon, or a combination thereof; for example, the semiconductor layer 400 is low temperature polysilicon (Low Temperature Poly Silicon, LTPS), and the semiconductor layer 400 includes an oxide semiconductor material (eg, indium gallium zinc). Oxide, (Indium Gallium Zinc Oxide, IGZO)), the semiconductor layer 400 includes a low temperature polycrystalline oxide material (Low Temperature Polycrystalline Oxide, LTPO); for example, as shown in FIG. 3: The semiconductor layer 400 of T3 is a low temperature polysilicon LTPS, T1 The semiconductor layer 400 includes an oxide semiconductor material LTPO.
  • LTPS Low Temperature Poly Silicon
  • LTPO Low Temperature Polycrystalline Oxide
  • the above-mentioned source formation region, drain formation region and connection formation region may be the conductive regions of the semiconductor layer doped with n-type impurities or p-type impurities, so that the source electrode formation region and the drain electrode formation region can be formed.
  • the formation region and the connection formation region serve as a connection structure of the semiconductor layer for electrical connection.
  • the semiconductor layers corresponding to the source electrode formation region and the drain electrode formation region may directly serve as the source electrode or the drain electrode of the corresponding transistor.
  • the source electrode in contact with the source electrode formation region may also be made of a conductive material (eg, metal material), and the drain electrode in contact with the drain electrode formation region may be made of a conductive material (eg, metal material).
  • the third conductive layer 300 is used to form the gates (eg, 201g-207g) of the transistors in the pixel circuit, the gate line patterns GA included in the display panel, and the light emission control. At least one of the structure of the signal line pattern EM, the first reset signal line pattern RST1, and the second reset signal line pattern RST2, etc.
  • the gate 203g of the third transistor T3 in the pixel circuit is multiplexed as the first electrode plate Cst1 of the first capacitor Cst in the pixel circuit.
  • the gate 203g of the third transistor T3 in the pixel circuit can also be multiplexed as the second electrode plate Cst2 of the first capacitor Cst in the pixel circuit.
  • the second conductive layer 200 has a plurality of auxiliary conductive parts WD, a plurality of storage conductive parts WCst2 spaced from the auxiliary conductive parts WD, and a first initialization included in the display panel
  • the sub-pixel includes an auxiliary conductive part; in the same sub-pixel, the first end of the auxiliary conductive part WD has an overlapping area on the orthographic projection of the base substrate 1000 and the orthographic projection of the power signal line pattern on the base substrate 1000, and the auxiliary conductive part has an overlapping area.
  • the orthographic projection of the second end of the portion WD on the base substrate 1000 and the orthographic projection of the data line pattern on the base substrate 1000 have an overlapping area.
  • the auxiliary conductive portion WD at least partially overlaps with the power signal line pattern, the data line pattern, and the touch electrodes.
  • the sub-pixel includes a storage conductive portion Cst2 for forming a second electrode plate Cst2 of the first capacitor Cst, that is, the storage conductive portion Cst2 serves as a second electrode plate Cst2 of the first capacitor Cst.
  • the storage conductive portion Cst2 can also be used as the first plate Cst1 of the first capacitor Cst.
  • the shape and structure of the auxiliary conductive portion WD is not limited, and may be a regular rectangle or an irregular shape with at least one side of an arc. Exemplarily, one end of the auxiliary conductive portion WD extends to the other end of the auxiliary conductive portion along the row direction F4.
  • the first conductive layer 100 is used to form the source (eg: S1-S7) and drain (eg: D1-D7) of each transistor in the pixel circuit ), as well as data line patterns (such as DA1, DA2, DA3, DA4, and DA5) and power signal line patterns VDD included in the display panel.
  • data line patterns such as DA1, DA2, DA3, DA4, and DA5
  • power signal line patterns VDD included in the display panel.
  • the width of the power signal line pattern VDD is greater than the width of the data line patterns (eg, DA1, DA2, DA3, DA4, and DA5).
  • the connection lines 401 , 402 , 403 and 404 in FIGS. 6d and 7d may be formed by the first conductive layer, and the specific layout is shown in FIGS. 5a to 5i , 6d and 7d .
  • the data line pattern DA and the power signal line pattern VDD may not be disposed on the same conductive layer.
  • the first conductive layer 100 may include the first sub-layers arranged in layers.
  • the conductive layer 111 and the second sub-conductive layer 112 are provided with a first sub-insulating layer (not shown) between the first sub-conductive layer 111 and the second sub-conductive layer 112 .
  • at least one of the connection lines 401 , 402 , 403 and 404 is arranged on the same layer as the data line pattern (eg DA1 , DA2 ) or the power signal line pattern VDD.
  • data line patterns such as DA1 and DA2
  • connection lines 401 , 402 and 403 may be disposed on the first sub-conducting layer 111
  • a power signal line pattern VDD may be disposed in the second sub-conducting layer 112 . That is, the data line patterns (eg, DA1, DA2) and the power signal line pattern VDD are not disposed on the same conductive layer.
  • the first sub-conducting layer 111 where the data line patterns (eg DA1, DA2) are located is closer to the base substrate 1000 than the second sub-conducting layer where the power signal line pattern VDD is located.
  • connection line 404 as a connection structure between adjacent initialized signal line patterns, may be located in a sub-pixel or in a non-display area.
  • the connection line 404 connects the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2.
  • FIG. 5a-FIG. 5i-FIG. 7d the gate electrode 201g of the first transistor T1 overlaps with the first channel region 101pg, and the source electrode S1 of the first transistor T1 is located in the first transistor T1. In the source formation region 101ps, the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.
  • the gate electrode 202g of the second transistor T2 overlaps with the second channel region 102pg, the source electrode S2 of the second transistor T2 is located in the second source electrode formation region 102ps, and the drain electrode D2 of the second transistor T2 is located in the second drain electrode formation region 102pd.
  • the gate 203g of the third transistor T3 overlaps the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.
  • the gate 204g of the data writing transistor T4 overlaps with the fourth channel region 104pg, the source S4 of the data writing transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the data writing transistor T4 is located in the fourth drain Pole forming region 104pd.
  • the gate electrode 205g of the fifth transistor T5 overlaps with the fifth channel region 105pg, the source electrode S5 of the fifth transistor T5 is located in the fifth source electrode formation region 105ps, and the drain electrode D5 of the fifth transistor T5 is located in the fifth drain electrode formation region 105pd.
  • the gate 206g of the sixth transistor T6 overlaps with the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.
  • the gate 207g of the seventh transistor T7 overlaps with the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the first capacitor Cst, and the second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.
  • the capacitor conducting portion includes an auxiliary conducting portion WD
  • the auxiliary conducting portion WD may include the second electrode plate C12 of the second capacitor C1, that is, the auxiliary conducting portion may partially or fully serve as the second electrode plate C12 of the second capacitor C1.
  • the auxiliary conductive portion WD is used as the second plate C12 of the second capacitor C1
  • the data line pattern DA is used as the first plate C11 of the second capacitor C1
  • the electrode plate C12 has the data line pattern DA in the overlapping area as the first electrode plate C11 of the second capacitor C1.
  • the first electrode layer 500 is used to form the first electrode of the light-emitting element L (eg, 510, 520, 530, 540).
  • the first electrode is the anode of the light-emitting element L (eg, 510, 520, 530, 540).
  • the pixel defining layer 950 includes a plurality of opening regions (eg, KK1, KK2, KK3, and KK4).
  • One first electrode corresponds to one opening area, and the orthographic projection of the opening area on the base substrate 1000 is located within the orthographic projection of the corresponding first electrode on the base substrate 1000 .
  • the opening area KK1 corresponds to the first electrode 510
  • the opening area KK2 corresponds to the first electrode 520
  • the opening area KK3 corresponds to the first electrode 530
  • the opening area KK4 corresponds to the first electrode 540 .
  • the first electrode may be directly electrically connected to the semiconductor layer; alternatively, the first electrode may also be electrically connected to the semiconductor layer through other conductive layers, such as the first conductive layer 100 .
  • the light-emitting functional layer 600 is used to form the light-emitting layer of the light-emitting element L.
  • the first color light emitting layer 610 , the second color light emitting layer 620 , the third color light emitting layer 630 and the fourth color light emitting layer 640 may further include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.
  • the boundaries of the first color light emitting layer 610 , the second color light emitting layer 620 , the third color light emitting layer 630 and the fourth color light emitting layer 640 may or may not overlap.
  • at least two of the first-color light-emitting layer 610, the second-color light-emitting layer 620, the third-color light-emitting layer 630, and the fourth-color light-emitting layer 640 have overlapping regions, for example, the boundary of the first-color light-emitting layer 610 extends to in the second color light-emitting layer 620 .
  • the encapsulation layer FB may include at least one or more layers among FB1 , FB2 and FB3 , wherein at least one layer among FB1 , FB2 and FB3 is an inorganic, organic or organic-inorganic composite material
  • the inorganic material can be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc., and the organic material can be polyimide (PI) and the like.
  • the encapsulation layer FB may include a first inorganic encapsulation layer FB1, an organic encapsulation layer FB2, and a second inorganic encapsulation layer FB3, which are arranged in layers; wherein, the organic encapsulation layer FB2 is located at the inner periphery of the barrier wall 110 and covers the display area AA; the first The inorganic encapsulation layer FB1 and the second inorganic encapsulation layer FB3 cover the display area AA, the retaining wall 110 and the peripheral area of the retaining wall 110 ; wherein, the orthographic projection of the first inorganic encapsulating layer FB1 on the base substrate 1000 and the second inorganic encapsulating layer FB3 The orthographic projections of the base substrate 1000 overlap.
  • the organic encapsulation layer FB and the display area can be well blocked from water and oxygen.
  • the touch electrodes 800 may include a plurality of first touch electrodes 810 and a plurality of second touch electrodes 820 arranged in an intersecting manner, so that the touch electrodes 800 are placed on the backing
  • the shape of the orthographic projection of the base substrate 1000 is a grid shape.
  • the orthographic projections of the touch electrodes 800 on the base substrate 1000 do not overlap with the orthographic projections of the opening regions (eg, KK1 , KK2 , KK3 , and KK4 ) on the base substrate 1000 .
  • the touch electrode 800 may be at least one of a plurality of first touch electrodes 810 and second touch electrodes 820 , for example, in a partial display area of the display panel.
  • the touch electrodes only include a plurality of first touch electrodes 810 or a plurality of second touch electrodes 820 .
  • the plurality of first touch electrodes 810 are disposed on the same conductive film layer, and the plurality of second touch electrodes 820 are disposed on the same conductive film layer.
  • the layer where the first touch electrodes 810 are located is located on the side of the packaging layer FB away from the base substrate 1000
  • the layer where the second touch electrodes 820 are located is located at the side of the layer where the first touch electrodes 810 are located away from the base substrate 1000
  • an electrode insulating layer 830 is disposed between the layer where the first touch electrodes 810 are located and the layer where the second touch electrodes 820 are located.
  • the electrode insulating layer 830 may be located in the display area and cover the display area.
  • the electrode insulating layer 830 may not only cover the display area, but also cover the non-display area.
  • the edge of the electrode insulating layer 830 is located between the two blocking walls BK.
  • it can be designed according to practical application, which is not limited here.
  • one or more insulating layers may also be disposed between the first touch electrodes 810 and the encapsulation layer FB.
  • At least one insulating layer can be an inorganic, organic or organic-inorganic composite material, the inorganic material can be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc., and the organic material can be polyamide imine (PI) etc.
  • at least one layer of touch electrode substrate is disposed between the first touch electrode 810 and the packaging layer FB3, and the material is silicon nitride (SiNx), silicon oxide (SiOX) or polyimide (PI).
  • the touch electrode substrate may be located in the display area and cover the display area.
  • the electrode insulating layer 830 may not only cover the display area, but also cover the non-display area.
  • the edge of the touch electrode substrate is located between the two blocking walls BK.
  • it can be designed according to practical application, which is not limited here.
  • the orthographic projections of the first touch electrodes 810 on the base substrate 1000 and the orthographic projections of the second touch electrodes 820 on the base substrate 1000 may be strip-shaped. Since the first touch electrodes 810 and the second touch electrodes 820 are arranged to intersect, the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of the second touch electrodes 820 on the base substrate 1000 can be formed. grid.
  • the shape of the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of at least one of the second touch electrodes 820 on the base substrate 1000 may also be a grid. shape.
  • the first touch electrodes 810 and the second touch electrodes 820 are disposed crosswise, and the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of the second touch electrodes 820 on the base substrate 1000 are formed. grid.
  • at least part of the first touch electrodes 810 and the second touch electrodes 820 are disposed overlappingly, and the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of the second touch electrodes 820 on the base substrate 1000 overlap .
  • the first touch electrodes 810 may be electrically connected by the first bridge portions 811 .
  • the first end of the first bridging portion 811 can be electrically connected to a first touch electrode 810 through the via hole 831 penetrating the electrode insulating layer 830 , and the second end of the first bridging portion 811 can pass through the electrode insulating layer 830 .
  • the via hole 832 is electrically connected to another first touch electrode 810 .
  • the second touch electrodes 820 may be electrically connected by the second bridge portions 821 .
  • the first end of the second bridging portion 821 can be electrically connected to a second touch electrode 820 through a via hole penetrating the electrode insulating layer 830 , and the second end of the second bridging portion 821 can be electrically connected through a via penetrating the electrode insulating layer 830 .
  • the hole is electrically connected to another second touch electrode 820 .
  • the light-emitting element can be set as an electroluminescent diode, such as at least one of an organic light-emitting diode (Organic Light Emitting Diode, OLED) and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED).
  • the light-emitting element may include a stacked first electrode 500 (for example, an anode of the light-emitting element), a light-emitting functional layer 600 and a second electrode 700 (for example, a cathode of the light-emitting element).
  • this disclosure includes, but is not limited to, this. In practical application, it can be designed according to practical application requirements, which is not limited here.
  • the materials of the third conductive layer 300 , the second conductive layer 200 , the first conductive layer 100 , the second touch electrodes 820 , and the first touch electrodes 810 may be the same or different. At least one of the third conductive layer 300 , the second conductive layer 200 , the first conductive layer 100 , the second touch electrodes 820 , and the first touch electrodes 810 includes metal materials or alloy materials or other conductive materials, such as metal aluminum ( AL), titanium (Ti), molybdenum (Mo), molybdenum-niobium alloy, aluminum-neodymium alloy, graphene, etc. at least one.
  • AL metal aluminum
  • Ti titanium
  • Mo molybdenum
  • molybdenum-niobium alloy aluminum-neodymium alloy
  • graphene etc. at least one.
  • At least one of the third conductive layer 300 , the second conductive layer 200 , the first conductive layer 100 , the second touch electrodes 820 , and the first touch electrodes 810 may form a single-layer structure, or use molybdenum/aluminum /molybdenum, titanium/aluminum/titanium to form a laminated structure obtained by sub-layers.
  • At least one of the third conductive layer 300 , the second conductive layer 200 , the first conductive layer 100 , the second touch electrodes 820 , and the first touch electrodes 810 has a thickness ranging from 100 nm to 500 nm.
  • the third conductive layer 300, the second conductive layer 200, and the first conductive layer 100 may be selected from at least one of metal aluminum (AL), titanium (Ti), molybdenum (Mo), etc.; or, the second touch At least one of the electrodes 820 and the first touch electrodes 810 is a stacked junction formed by forming sub-layers of titanium/aluminum/titanium; or, at least one of the materials of the second touch electrodes 820 and the first touch electrodes 810 includes graphene.
  • AL metal aluminum
  • Ti titanium
  • Mo molybdenum
  • the second capacitor C1 Due to the high surface reflectivity of the conductive layer, for example, the high surface reflectivity of the molybdenum metal material, it is easy to cause the second capacitor C1 to reflect the external ambient light or the light emitted by the light-emitting functional layer 600 into the adjacent opening area. As a result, the problem of luminous crosstalk or poor light mixing effect is caused.
  • the display panel includes a plurality of repeating units; the repeating units may include a plurality of sub-pixels, for example, the plurality of sub-pixels may include a first A sub-pixel of a color, a sub-pixel of a second color and a sub-pixel of a third color. That is, the repeating unit may include the first color subpixel, the second color subpixel, and the third color subpixel. In this way, the display panel can use the sub-pixels of the first color, the sub-pixels of the second color, and the sub-pixels of the third color to mix light, so as to realize color display.
  • the first color, the second color, and the third color may be selected from red, green, and blue.
  • the second color is red
  • the first color is green
  • the third color is blue.
  • the embodiments of the present disclosure include but are not limited to this.
  • the above-mentioned first color, second color and third color can also be other colors.
  • the repeating unit may further include a fourth color sub-pixel.
  • the display panel can use the sub-pixels of the first color, the sub-pixels of the second color, the sub-pixels of the third color, and the sub-pixels of the fourth color to perform light mixing, so as to realize color display.
  • the fourth color sub-pixel may be a green sub-pixel, or a white sub-pixel, or a yellow sub-pixel, or other colors, which are not limited herein.
  • the repeating unit includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel and a fourth color sub-pixel, and the first color and the fourth color are green, the second color is red, and the third color is blue as an example.
  • the first color sub-pixel has the pixel circuit, the first electrode 510 , the first color light emitting layer 610 and the opening area KK1 according to any of the above embodiments.
  • the orthographic projection of the first color light-emitting layer 610 on the base substrate 1000 covers the orthographic projection of the opening area KK1 in the first color sub-pixel on the base substrate 1000 , and the light-emitting area of the first color sub-pixel includes the opening area KK1 .
  • the opening area KK1 may serve as the light-emitting area of the first color sub-pixel.
  • the second color sub-pixel has the pixel circuit of any of the above embodiments, the first electrode 520 , the second color light-emitting layer 620 and the opening area KK2 .
  • the orthographic projection of the second color light-emitting layer 620 on the base substrate 1000 covers the orthographic projection of the opening area KK2 in the second color sub-pixel on the base substrate 1000 , and the light-emitting area of the second color sub-pixel includes the opening area KK2 .
  • the opening area KK2 may serve as the light-emitting area of the second color sub-pixel.
  • the third-color sub-pixel has the pixel circuit of any of the above-mentioned embodiments, the first electrode 530 , the third-color light-emitting layer 630 , and the opening region KK3 .
  • the orthographic projection of the third-color light-emitting layer 630 on the base substrate 1000 covers the orthographic projection of the opening area KK3 in the third-color sub-pixel on the base substrate 1000, and the light-emitting area of the third-color sub-pixel includes the opening area KK3.
  • the opening area KK3 may serve as the light-emitting area of the third color sub-pixel.
  • the fourth color sub-pixel has the pixel circuit of any of the above-mentioned embodiments, the first electrode 540 , the fourth color light-emitting layer 640 , and the opening area KK4 .
  • the orthographic projection of the fourth-color light-emitting layer 640 on the base substrate 1000 covers the orthographic projection of the opening area KK4 in the fourth-color sub-pixel on the base substrate 1000 , and the light-emitting area of the fourth-color sub-pixel includes the opening area KK4 .
  • the opening area KK4 may serve as the light-emitting area of the fourth color sub-pixel.
  • the area of the opening region KK1 in the first color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel.
  • the area of the opening region KK2 in the second color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel.
  • the area of the opening area KK4 in the fourth color sub-pixel is smaller than the area of the opening area KK3 in the third color sub-pixel.
  • the influence on the adjacent sub-pixels is great, so the area of the opening area of the green sub-pixel can be made smaller than that of the blue sub-pixel.
  • the area of the opening region of the red sub-pixel is smaller than that of the blue sub-pixel, so that the emission of blue light can be improved.
  • the second capacitor C1 of the green sub-pixel and the red sub-pixel will have more parts that are not blocked by the opening area, resulting in more exposure of the second capacitor C1, which in turn leads to the problems of light emission interference and poor light mixing effect. .
  • the transistor array layer includes a plurality of capacitive conductive parts R, and at least a part of the sub-pixels includes the capacitive conductive parts R; wherein, in the same sub-pixel, the capacitor
  • the conductive portion R has an overlapping area with the power signal line pattern VDD and/or the data line pattern.
  • the capacitor conductive portion R and the power signal line pattern VDD have an overlapping area.
  • the capacitor conductive portion R and the data line pattern have an overlapping area.
  • the overlapping area of the capacitor conducting portion R and the power signal line pattern VDD is larger than the overlapping area of the capacitor conducting portion R and the data line pattern DA.
  • the orthographic projection of the capacitive conductive portion R in the first color sub-pixel on the base substrate 1000 is connected to the touch electrode (for example, the second touch
  • the orthographic projection of the control electrode 820) on the base substrate 1000 has a first auxiliary overlapping area S1.
  • the orthographic projection of the capacitive conductive portion R in the second color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 have a second auxiliary overlapping area S2 .
  • the orthographic projection of the capacitive conductive portion R in the third color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 have a third auxiliary overlapping area S3 .
  • the orthographic projection of the capacitive conductive portion R in the fourth color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 have a fourth auxiliary overlapping area S4 .
  • at least one of the first auxiliary overlapping area S1, the second auxiliary overlapping area S2 and the fourth auxiliary overlapping area S4 is larger than the third auxiliary overlapping area S3.
  • the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S3; or, the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area area S2, and the second auxiliary overlapping area S2 is equal to the third auxiliary overlapping area S3; or the first auxiliary overlapping area S1 is approximately equal to the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S2 Overlap area S3.
  • the second capacitor C1 can be shielded by the touch electrodes 800 , so that the problems of light emission interference and poor light mixing effect caused by the second capacitor C1 can be improved.
  • the transistor array layer ZA includes a plurality of data line patterns (eg, DA1, DA2) and a plurality of power supply signal line patterns (eg, VDD), and the transistor array layer ZA includes a plurality of capacitors.
  • the conductive portion R, the sub-pixel includes a capacitive conductive portion R, and the capacitive conductive portion R overlaps with the power signal line pattern VDD and/or the data line pattern DA; for example, a plurality of capacitive conductive portions R are formed on the second conductive layer 200 .
  • it can also be formed on other conductive layers, such as the first conductive layer.
  • the capacitor conducting portion R forms a capacitor with the power signal line pattern VDD or the data line pattern DA, that is, at least one insulating layer exists between the capacitor conducting portion R and the power signal line pattern VDD or the data line pattern DA.
  • the capacitor conductive portion R forms a capacitor plate of the second capacitor C1. Specifically, part or the whole of the capacitor conducting part forms the first electrode plate C11 or the second electrode plate C12 of the second capacitor.
  • the capacitive conductive portion R may be arc-shaped or irregular.
  • the capacitive conductive part R includes an auxiliary conductive part WD, which is formed on the second conductive layer 200, the auxiliary conductive part WD is located under the data line pattern (eg DA1, DA2), and the first end of the auxiliary conductive part WD is connected to the power supply.
  • the data line pattern eg DA1, DA2
  • the signal line pattern VDD for example: the first end of the auxiliary conductive portion WD is connected to the power signal line pattern VDD through the via hole of the first interlayer insulating layer 930; the second end of the auxiliary conductive portion WD extends below the data line pattern, the auxiliary The conductive portion WD and the power signal line pattern and/or the data line pattern have an overlapping area, that is, the second electrode plate C12 of the second capacitor C1 is formed on the auxiliary conductive portion WD, and the first electrode plate of the second capacitor C1 is formed on the auxiliary conductive portion WD.
  • the corresponding sub-pixel data line pattern DA (eg DA1, DA2); or the first plate of the second capacitor C1 is formed on the corresponding sub-pixel data line pattern DA (eg DA1, DA2) having an overlapping area with the auxiliary conductive portion WD.
  • the capacitor conductive part R may further include a second auxiliary conductive part WN2 (not shown), the second auxiliary conductive part WN2 is formed on the second conductive layer 200, and the second auxiliary conductive part WN2 is located in the data line pattern of the corresponding sub-pixel.
  • a second auxiliary conductive part WN2 (not shown)
  • the second auxiliary conductive part WN2 is formed on the second conductive layer 200
  • the second auxiliary conductive part WN2 is located in the data line pattern of the corresponding sub-pixel.
  • the first end of the second auxiliary conductive portion WD2 is connected to the data line pattern (for example: data line pattern DA1) corresponding to each sub-pixel, for example: the first end of the second auxiliary conductive portion WD2
  • the via holes of the first interlayer insulating layer 930 are connected to the corresponding data line patterns of each sub-pixel (for example, the data line pattern DA1); the second end of the second auxiliary conductive portion WN2 extends below the power signal line pattern, and the second The auxiliary conductive portion WN2 and the power signal line pattern and/or the data line pattern have an overlapping area, that is, the first electrode plate of the second capacitor C1 is formed on the second auxiliary conductive portion WD2, and the second electrode plate of the second capacitor C1 is formed at this time. It is the power signal line pattern VDD; or the second electrode plate of the second capacitor C1 is formed on the corresponding sub-pixel power signal line pattern VDD in an overlapping area with the second auxiliary conductive portion
  • the capacitor conductive portion R as the auxiliary conductive portion WD as an example.
  • the area of the opening region KK1 in the first color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel, the portion of the capacitive conductive portion R in the first color sub-pixel that is blocked by the opening region is relatively small.
  • more parts of the capacitive conductive part R of the third color sub-pixel are blocked by the opening area, which leads to a stronger effect of light emission from the capacitive conductive part R in the first color sub-pixel.
  • the first auxiliary overlapping area S1 by making the first auxiliary overlapping area S1 larger than the third auxiliary overlapping area S3, more parts of the capacitive conductive part R in the first color sub-pixel are blocked by the touch electrodes 800, thereby reducing the number of the first auxiliary overlapping area S1.
  • the portion of the capacitive conductive portion R in the second color sub-pixel that is blocked by the opening region is relatively small.
  • more parts of the capacitive conductive part R of the third color sub-pixel are blocked by the opening area, which leads to a stronger effect of light emission from the capacitive conductive part R in the second color sub-pixel.
  • the second auxiliary overlapping area S2 larger than the third auxiliary overlapping area S3, more portions of the capacitive conductive portion R in the second color sub-pixel are blocked by the touch electrodes 800, thereby reducing the The problems of light emission interference and poor light mixing effect caused by the capacitive conductive portion R in the two-color sub-pixels.
  • the portion of the capacitive conductive portion R in the fourth color sub-pixel that is blocked by the opening region is relatively small. However, more parts of the capacitive conductive portion R of the third color sub-pixel are blocked by the opening area, which leads to a stronger effect of light emission from the capacitive conductive portion R in the fourth color sub-pixel.
  • the fourth auxiliary overlapping area S4 larger than the third auxiliary overlapping area S3, more parts of the capacitive conductive parts R in the fourth color sub-pixels can be blocked by the touch electrodes 800, thereby reducing the The problems of light emission interference and poor light mixing effect caused by the capacitive conductive portion R in the four-color sub-pixels.
  • the area of the opening area KK1 in the first color sub-pixel may be smaller than the area of the opening area KK2 in the second color sub-pixel.
  • the area of the opening area of the green sub-pixel can be made smaller than the area of the opening area of the red sub-pixel.
  • the capacitance conductive portion R is less covered by the opening area.
  • the first auxiliary overlapping area S1 is approximately equal to the second auxiliary overlapping area S2.
  • the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2, so that the first color sub-pixel has more parts of the capacitive conductive portion R blocked by the touch electrode 800 than the second color sub-pixel, so that it is possible to The problems of light emission interference and poor light mixing effect caused by the capacitive conductive portion R in the first color sub-pixel are further reduced.
  • the area of the opening area KK1 of the first color sub-pixel may be 100 ⁇ m 2 to 130 ⁇ m 2
  • the shape of the opening area KK1 is not limited, for example, it may be: polygon, rectangle, square , rhombus, ellipse, circle, etc.; of course, it can also be other irregular graphics, such as: closed graphics composed of at least 2 arc segments and 1 straight segment.
  • the opening area KK1 of the first color sub-pixel is rectangular, the length of the first side is 12 ⁇ m-13 ⁇ m, and the length of the second side of the opening area KK1 of the first color sub-pixel is 9 ⁇ m-10 ⁇ m.
  • the opening area of the opening region KK1 of the first color sub-pixel is 10*10 ⁇ m 2 to 12*10 ⁇ m 2 or 11*10 ⁇ m 2 to 12*10 ⁇ m 2 .
  • the opening area of the opening region KK1 of the further first color sub-pixel is 13*9 ⁇ m 2 to 12*10 ⁇ m 2 .
  • the area of the opening area KK1 of the first color subpixel may be 13*9 ⁇ m 2 (length*width), or the area of the opening area KK1 of the first color subpixel may be 12*10 ⁇ m 2 (length*width).
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the area of the opening area KK2 of the second color sub-pixel may be 120 ⁇ m 2 to 200 ⁇ m 2
  • the shape of the opening area KK2 is not limited, for example, it may be: rectangle, square, rhombus, An ellipse, a circle, etc.; of course, it can also be other irregular shapes, such as a closed shape composed of at least 2 arc segments and 1 straight line segment.
  • the opening area KK2 of the second color sub-pixel is a square with a side length of 13 ⁇ m-15 ⁇ m.
  • the opening area of the opening region KK2 of the second color sub-pixel is 13*10 ⁇ m 2 to 19*10 ⁇ m 2 or 13*15 ⁇ m 2 to 18*11 ⁇ m 2 .
  • the opening area of the opening region KK1 of the first color sub-pixel may be 13*13 ⁇ m 2 to 14*14 ⁇ m 2 .
  • the area of the opening area KK2 of the second color sub-pixel may be 13*13 ⁇ m 2
  • the area of the opening area KK2 of the second color sub-pixel may be 14*14 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the area of the opening area KK3 of the third color sub-pixel is 180 ⁇ m 2 to 230 ⁇ m 2
  • the shape of the opening area KK3 is not limited, for example, it can be: rectangle, square, diamond, ellipse
  • it can also be other irregular graphics, such as: closed graphics composed of at least 2 arc segments and 1 straight line segment.
  • the opening area KK3 of the third color sub-pixel is a rectangle
  • the length of the first side is 15 ⁇ m-16 ⁇ m
  • the length of the second side of the opening area KK1 of the first color sub-pixel is 13 ⁇ m-14 ⁇ m.
  • the opening area of the opening region KK3 of the third color sub-pixel is 18*10 ⁇ m 2 to 23*10 ⁇ m 2 or 20*10 ⁇ m 2 to 22*10 ⁇ m 2 .
  • the opening area of the opening region KK1 of the first color sub-pixel may be 15*13 ⁇ m 2 to 16*14 ⁇ m 2 (length*width).
  • the area of the opening region KK3 of the third color sub-pixel may be 15*13 ⁇ m 2 (length*width).
  • the area of the opening region KK3 of the third color sub-pixel may be 16*13 ⁇ m 2 (length*width).
  • the area of the opening region KK3 of the third color sub-pixel may be 16*14 ⁇ m 2 (length*width).
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the area of the opening area KK4 of the fourth color sub-pixel may be 100 ⁇ m 2 to 230 ⁇ m 2
  • the shape of the opening area KK4 is not limited, for example, it may be: rectangle, square, diamond, An ellipse, a circle, etc.; of course, it can also be other irregular shapes, such as a closed shape composed of at least 2 arc segments and 1 straight line segment.
  • the opening area of the fourth color sub-pixel is oval, and the area can be 100 ⁇ m 2 -130 ⁇ m 2 ; or, the opening area KK4 of the fourth color sub-pixel is a rectangle, the length of the first side is 12 ⁇ m-13 ⁇ m, and the fourth color sub-pixel The length of the second side of the opening area KK4 is 9 ⁇ m-10 ⁇ m.
  • the opening area of the opening region KK1 of the first color sub-pixel is 13*9 ⁇ m 2 to 12*10 ⁇ m 2 .
  • the area of the opening area KK4 of the fourth color sub-pixel may be 13*9 ⁇ m 2 (length*width), or the area of the opening area KK4 of the fourth color sub-pixel may be 12*10 ⁇ m 2 (length*width).
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the first auxiliary overlapping area S1 may be 3 ⁇ m 2 to 40 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 6 ⁇ m 2 to 20 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 3 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 6 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 10 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 20 ⁇ m 2 .
  • the first auxiliary overlapping area S1 may be 30 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the second auxiliary overlapping area S2 may be 0 ⁇ 10 ⁇ m 2 .
  • the second auxiliary overlapping area S2 may be 0 ⁇ 5 ⁇ m 2 .
  • the second auxiliary overlapping area S2 may be 0 ⁇ m 2 .
  • the second auxiliary overlapping area S2 may be 5 ⁇ m 2 .
  • the second auxiliary overlapping area S2 may be 10 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third auxiliary overlapping area S3 may be 0 ⁇ 6 ⁇ m 2 .
  • the third auxiliary overlapping area S3 may be 0 ⁇ 3 ⁇ m 2 .
  • the third auxiliary overlapping area S3 may be 0 ⁇ m 2 .
  • the third auxiliary overlapping area S3 may be 3 ⁇ m 2 .
  • the third auxiliary overlapping area S3 may be 6 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth auxiliary overlapping area S4 may be 0 ⁇ 40 ⁇ m 2 .
  • the fourth auxiliary overlapping area S4 may be 0 ⁇ 15 ⁇ m 2 .
  • the fourth auxiliary overlapping area S4 may be 0 ⁇ m 2 .
  • the fourth auxiliary overlapping area S4 may be 5 ⁇ m 2 .
  • the fourth auxiliary overlapping area S4 may be 15 ⁇ m 2 .
  • the fourth auxiliary overlapping area S4 is substantially equal to at least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3; or, the fourth auxiliary overlapping area S4 is greater than the third auxiliary overlapping area S4. At least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3 is equal.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the area of the opening area KK1 in the first color sub-pixel can be made larger than the area of the opening area KK4 in the fourth color sub-pixel area.
  • the area of the opening region KK1 in the first color sub-pixel may also be approximately equal to the area of the opening region KK4 in the fourth color sub-pixel.
  • the second conductive layer 200 may include a capacitive conductive portion R(WD) (taking the auxiliary conductive portion WD as the capacitive conductive portion R as
  • the first auxiliary overlapping area S1 may include the orthographic projection of the auxiliary conductive portion in the first color sub-pixel on the base substrate 1000 and the touch electrode (eg, the second touch electrode 820 ) on the base substrate The area of overlap between orthographic projections of 1000.
  • the second auxiliary overlapping area S2 may include the orthographic projection of the auxiliary conductive portion in the second color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 area of overlap.
  • the third auxiliary overlapping area S3 includes between the orthographic projection of the auxiliary conductive portion in the third color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 the overlapping area.
  • the fourth auxiliary overlapping area S4 includes between the orthographic projection of the auxiliary conductive portion in the fourth color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 the overlapping area.
  • the auxiliary conductive portion can be shielded by the touch electrodes (eg, the second touch electrodes 820 ), thereby reducing the problems of light emission interference and poor light mixing effect caused by the reflection of light by the auxiliary conductive portion.
  • the auxiliary conductive portion WD in the first color sub-pixel includes a first auxiliary exposed portion WD1 , and the first auxiliary exposed portion WD1
  • the orthographic projections on the base substrate 1000 do not overlap with the orthographic projections of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000 , respectively.
  • the first auxiliary overlapping area S1 includes the first auxiliary sub-overlapping area S11 , and the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 and the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate There is a first auxiliary sub-overlapping area S11 between the orthographic projections of 1000 .
  • the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 is located between the orthographic projections of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000 .
  • the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 may be located on the side of the orthographic projection of the data line pattern DA2 on the base substrate 1000 away from the orthographic projection of the power signal line pattern VDD on the base substrate 1000 .
  • the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 may be located on the side of the orthographic projection of the power signal line pattern VDD on the base substrate 1000 away from the orthographic projection of the data line pattern DA2 on the base substrate 1000 .
  • the first auxiliary exposed portion WD1 may include a first auxiliary exposed portion first region WD11 (not shown), a first auxiliary exposed portion second region WD12 (not shown), and a first auxiliary exposed portion third region WD13 At least one of them (not shown); wherein, the first area WD11 of the first auxiliary exposed portion is the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 located on the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000.
  • the first area between the orthographic projections, the first auxiliary exposed portion, the second area WD12 is the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000
  • the orthographic projection of the data line pattern DA2 on the base substrate 1000 is away from the power signal line pattern VDD
  • the first auxiliary exposed portion and the third area WD13 are the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 .
  • the projection is away from the third area of the data line pattern DA2 on the side of the orthographic projection of the base substrate 1000 .
  • the first auxiliary sub-overlapping area S11 may be 2 ⁇ m 2 to 10 ⁇ m 2 .
  • the first auxiliary sub-overlapping area S11 may be 3 ⁇ m 2 to 6 ⁇ m 2 .
  • the first auxiliary sub-overlap area S11 may be 2 ⁇ m 2 .
  • the first auxiliary sub-overlap area S11 may be 3 ⁇ m 2 .
  • the first auxiliary sub-overlapping area S11 may be 5 ⁇ m 2 .
  • the first auxiliary sub-overlap area S11 may be 6 ⁇ m 2 .
  • the first auxiliary sub-overlapping area S11 may be 10 ⁇ m 2 , which is not limited herein.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm.
  • the ratio between the first auxiliary overlapping area S1 and the total area Sm may range from 1/6 to 3/4.
  • the range of the ratio between the first auxiliary overlapping area S1 and the total area Sm may be 1/3 ⁇ 2/3, that is, 1/3 ⁇ S1/Sm ⁇ 2/3.
  • the specific values of S1/Sm can be set according to the requirements of practical applications, which are not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm.
  • the range of the ratio between the first auxiliary sub-overlapping area S11 and the total area Sm may be: 1/8 to 2/3.
  • the ratio of the first auxiliary sub-overlapping area S11 to the total area Sm may range from 1/6 to 1/3, that is, 1/6 ⁇ S11/Sm ⁇ 1/3.
  • the specific values of S11/Sm can be set according to the requirements of practical applications, which are not limited here.
  • the touch electrodes (eg, the second touch electrodes 820 ) may also be arranged on the bottom of the base substrate 1000 .
  • the orthographic projection covers the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 . In this way, the first auxiliary exposed portion WD1 that may reflect light can be covered as much as possible.
  • the auxiliary conductive part WD in the first color sub-pixel may further include a first auxiliary shielding part WZ1, and the first auxiliary shielding part WZ1 is in the The orthographic projection of the base substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000 .
  • the first auxiliary shielding portion WZ1 and the first auxiliary exposed portion WD1 of the same auxiliary conductive portion are integrally provided, thereby forming the auxiliary conductive portion.
  • the width of the first auxiliary exposed portion WD1 in the column direction F3 may be approximately equal to the width of the first auxiliary shielding portion WZ1 in the column direction F3. In this way, the difficulty of preparing the auxiliary conductive portion in the first color sub-pixel can be reduced. As shown in FIG. 9 c , the width of the first auxiliary exposed portion WD1 in the column direction F3 may also be smaller than the width of at least a part of the first auxiliary shielding portion WZ1 in the column direction F3 . In this way, the first auxiliary exposed portion WD1 can be further shielded.
  • the width of the first auxiliary exposed portion WD1 in the row direction F4 can also be smaller than the width of at least a part of the first auxiliary shielding portion WZ1 in the row direction F4, so that the area of the exposed auxiliary conductive portion WD can be smaller. It is beneficial to reduce the reflected light generated by the auxiliary conductive portion WD.
  • the auxiliary conductive portion WD in the second color sub-pixel includes a second auxiliary exposed portion WD2 , and the second auxiliary exposed portion WD2
  • the orthographic projection on the base substrate 1000 does not overlap with the orthographic projections of the data line pattern DA3 and the power signal line pattern VDD respectively on the base substrate 1000; and the second auxiliary overlapping area S2 includes the second auxiliary sub-overlapping area S12, And the second auxiliary exposed portion WD2 has a second auxiliary sub-overlapping area S12 between the orthographic projection of the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 .
  • the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000 is located between the orthographic projections of the data line pattern DA3 and the power signal line pattern VDD on the base substrate 1000 .
  • the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000 is located on the side of the orthographic projection of the data line pattern DA3 on the base substrate 1000 away from the orthographic projection of the power signal line pattern VDD on the base substrate 1000 .
  • the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000 is located on the side of the orthographic projection of the power signal line pattern VDD on the base substrate 1000 away from the orthographic projection of the data line pattern DA3 on the base substrate 1000 .
  • the second auxiliary sub-overlap area S12 may be 0 ⁇ 4.5 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 0 ⁇ 2.2 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 0 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 1.5 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 2.2 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 3.5 ⁇ m 2 .
  • the second auxiliary sub-overlap area S12 may be 4.5 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the ratio between the second auxiliary overlapping area S2 and the total area Sm may range from 1/20 to 3/4.
  • the range of the ratio between the second auxiliary overlapping area S2 and the total area Sm (second color sub-pixels) may be: 1/10 ⁇ 7/20, that is, 1/10 ⁇ S2/Sm ⁇ 7/20 .
  • the specific value of S2/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the range of the ratio between the second auxiliary sub-overlap area S12 and the total area Sm may be: 1/10 ⁇ 1/2.
  • the ratio of the second auxiliary sub-overlap area S12 to the total area Sm may range from 1/5 to 1/4, that is, 1/5 ⁇ S12/Sm ⁇ 1/4.
  • the specific value of S12/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the touch electrodes (for example, the second touch electrodes 820 ) may also be located on the bottom of the base substrate 1000 .
  • the orthographic projection covers the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000 . In this way, the second auxiliary exposed portion WD2 that may reflect light can be covered as much as possible.
  • the auxiliary conductive portion WD in the second color sub-pixel may further include a second auxiliary shielding portion WZ2.
  • the orthographic projection of the second auxiliary shielding portion WZ2 on the base substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000 .
  • the second auxiliary shielding portion WZ2 and the second auxiliary exposed portion WD2 of the same auxiliary conductive portion are integrally provided, thereby forming the auxiliary conductive portion.
  • the width of the second auxiliary exposed portion WD2 in the column direction F3 may be approximately equal to the width of the second auxiliary shielding portion WZ2 in the column direction F3. In this way, the difficulty of preparing the auxiliary conductive portion in the second color sub-pixel can be reduced. As shown in FIG. 9 c , the width of the second auxiliary exposed portion WD2 in the column direction F3 may also be smaller than the width of at least a part of the second auxiliary shielding portion WZ2 in the column direction F3 . In this way, the second auxiliary exposed portion WD2 can be further shielded. Exemplarily, the width of the second auxiliary exposed portion WD2 in the row direction F4 is smaller than the width of at least a portion of the second auxiliary shielding portion WZ2 in the row direction F4.
  • the auxiliary conductive portion WD in the third color sub-pixel includes a third auxiliary exposed portion WD3, and the third auxiliary exposed portion WD3
  • the orthographic projection on the base substrate 1000 does not overlap with the orthographic projections of the data line pattern DA1 and the power signal line pattern VDD respectively on the base substrate 1000; and the third auxiliary overlapping area S3 includes the third auxiliary sub-overlapping area S13, And the third auxiliary exposed portion WD3 has a third auxiliary sub-overlap area S13 between the orthographic projection of the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 .
  • the orthographic projection of the third auxiliary exposed portion WD3 on the base substrate 1000 is located between the orthographic projections of the data line pattern DA1 and the power signal line pattern VDD on the base substrate 1000 .
  • the third auxiliary sub-overlap area S13 may be 0 ⁇ 2.5 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 0 ⁇ 1.2 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 0 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 0.5 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 1.0 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 1.2 ⁇ m 2 .
  • the third auxiliary sub-overlap area S13 may be 2.5 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not specifically limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the range of the ratio between the third auxiliary overlapping area S3 and the total area Sm may be: 0 to 1/2; optionally, the range of the ratio between the third auxiliary overlapping area S3 and the total area Sm may be: 0 ⁇ 1/4, namely 0 ⁇ S3/Sm ⁇ 1/4.
  • the specific value of S3/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the range of the ratio between the third auxiliary sub-overlap area S13 and the total area Sm may be: 0 to 1/8; optionally, the range of the ratio between the third auxiliary sub-overlap area S13 and the total area Sm may be It is: 0 ⁇ 1/16, that is, 0 ⁇ S13/Sm ⁇ 1/16.
  • the specific value of S13/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the touch electrodes (eg, the second touch electrodes 820 ) may also be located on the bottom of the base substrate 1000 .
  • the orthographic projection covers the orthographic projection of the third auxiliary exposed portion WD3 on the base substrate 1000 . In this way, the third auxiliary exposed portion WD3 that may reflect light can be covered as much as possible.
  • the auxiliary conductive portion WD in the third color sub-pixel may further include a third auxiliary shielding portion WZ3.
  • the orthographic projection of the third auxiliary shielding portion WZ3 on the base substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000 .
  • the third auxiliary shielding portion WZ3 and the third auxiliary exposed portion WD3 of the same auxiliary conductive portion are integrally provided, thereby forming the auxiliary conductive portion.
  • the width of the third auxiliary exposed portion WD3 in the column direction F3 may be approximately equal to the width of the third auxiliary shielding portion WZ3 in the column direction F3. In this way, the difficulty of preparing the auxiliary conductive portion in the third color sub-pixel can be reduced. As shown in FIG. 9 c , the width of the third auxiliary exposed portion WD3 in the column direction F3 may be smaller than the width of at least a part of the third auxiliary shielding portion WZ3 in the column direction F3 . In this way, the third auxiliary exposed portion WD3 can be further shielded. Exemplarily, the width of the third auxiliary exposed portion WD3 in the row direction F4 is smaller than the width of at least a part of the third auxiliary shielding portion WZ3 in the row direction F4.
  • the auxiliary conductive portion WD in the fourth color sub-pixel includes a fourth auxiliary exposed portion WD4 , and the fourth auxiliary exposed portion WD4
  • the orthographic projections on the base substrate 1000 do not overlap with the orthographic projections of the data line pattern DA4 and the power signal line pattern VDD on the base substrate 1000 , respectively.
  • the fourth auxiliary overlapping area S4 includes a fourth auxiliary sub-overlapping area S14, and the orthographic projection of the fourth auxiliary exposure portion WD4 on the base substrate 1000 and the touch electrodes (eg, the second touch electrodes 820 ) on the substrate There is a fourth auxiliary sub-overlapping area S14 between the orthographic projections of the substrate 1000 .
  • the orthographic projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000 is located between the orthographic projections of the data line pattern DA4 and the power signal line pattern VDD on the base substrate 1000 .
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the range of the ratio between the fourth auxiliary overlapping area S4 and the total area Sm may be: 1/6 to 5/6, that is, 1/6 ⁇ S4/Sm ⁇ 5/6.
  • the specific value of S4/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has Total area Sm.
  • the range of the ratio between the fourth auxiliary sub-overlap area S14 and the total area Sm may be 1/3 ⁇ 2/3, that is, 1/3 ⁇ S14/Sm ⁇ 2/3.
  • the specific value of S14/Sm can be set according to the requirements of practical applications, which is not limited here.
  • the fourth auxiliary sub-overlap area S14 may be 2 ⁇ m 2 to 10 ⁇ m 2 .
  • the fourth auxiliary sub-overlapping area S14 may be 3 ⁇ m 2 to 6 ⁇ m 2 .
  • the fourth auxiliary sub-overlap area S14 may be 2 ⁇ m 2 .
  • the fourth auxiliary sub-overlap area S14 may be 3 ⁇ m 2 .
  • the fourth auxiliary sub-overlap area S14 may be 5 ⁇ m 2 .
  • the fourth auxiliary sub-overlap area S14 may be 6 ⁇ m 2 .
  • the fourth auxiliary sub-overlapping area S14 may be 10 ⁇ m 2 , which is not limited herein.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the touch electrodes (for example, the second touch electrodes 820 ) may also be located on the bottom of the base substrate 1000 .
  • the orthographic projection covers the orthographic projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000 . In this way, the fourth auxiliary exposed portion WD4 that may reflect light can be covered as much as possible.
  • the auxiliary conductive portion in the fourth color sub-pixel may further include a fourth auxiliary shielding portion WZ4.
  • the orthographic projection of the fourth auxiliary shielding portion WZ4 on the base substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000 .
  • the fourth auxiliary shielding portion WZ4 and the fourth auxiliary exposed portion WD4 of the same auxiliary conductive portion are integrally provided, thereby forming the auxiliary conductive portion.
  • the width of the fourth auxiliary exposed portion WD4 in the column direction F3 may be approximately equal to the width of the fourth auxiliary shielding portion WZ4 in the column direction F3. In this way, the difficulty of preparing the auxiliary conductive portion in the fourth color sub-pixel can be reduced. As shown in FIG. 9 c , the width of the fourth auxiliary exposed portion WD4 in the column direction F3 may also be smaller than the width of at least a part of the fourth auxiliary shielding portion WZ4 in the column direction F3 . In this way, the fourth auxiliary exposed portion WD4 can be further shielded. Exemplarily, the width of the fourth auxiliary exposed portion WD4 in the row direction F4 is smaller than the width of at least a portion of the fourth auxiliary shielding portion WZ4 in the row direction F4.
  • the first auxiliary sub-overlap area S11 may be made larger than the second auxiliary sub-overlap area S12 .
  • the first-color sub-pixels can have more auxiliary conductive parts in the first-color sub-pixels shielded by the touch electrodes (eg, the second touch electrodes 820 ), thereby reducing the number of first-color sub-pixels.
  • the auxiliary exposed portion WD1 reflects light, which leads to the problems of light emission interference and poor light mixing effect.
  • the first auxiliary sub-overlap area S11 can be made larger than the third auxiliary sub-overlap area S13 .
  • the sub-pixels of the first color can have more auxiliary conductive parts in the sub-pixels of the first color that are shielded by the touch electrodes (for example, the second touch electrodes 820 ), thereby reducing the number of first color sub-pixels.
  • the auxiliary exposed portion WD1 reflects light, which leads to the problems of light emission interference and poor light mixing effect.
  • the fourth auxiliary sub-overlapping area S14 may be made larger than the second auxiliary sub-overlapping area S12 .
  • the fourth color subpixels can have more auxiliary conductive parts in the fourth color subpixels shielded by the touch electrodes (for example, the second touch electrodes 820 ), so that the fourth color subpixel can be reduced.
  • the auxiliary exposed part WD4 reflects light, which leads to the problems of light emission interference and poor light mixing effect.
  • the fourth auxiliary sub-overlapping area S14 may be made larger than the third auxiliary sub-overlapping area S13 .
  • the fourth color subpixels can have more auxiliary conductive parts in the fourth color subpixels shielded by the touch electrodes (for example, the second touch electrodes 820 ), so that the fourth color subpixel can be reduced.
  • the auxiliary exposed part WD4 reflects light, which leads to the problems of light emission interference and poor light mixing effect.
  • the second auxiliary sub-overlap area S12 may be made larger than the third auxiliary sub-overlap area S13, so that the first auxiliary sub-overlap area S13
  • the overlapping area S11 is larger than the second auxiliary sub-overlapping area S12
  • the second auxiliary sub-overlapping area S12 is larger than the third auxiliary sub-overlapping area S13.
  • the areas of the first auxiliary exposed portion WD1 , the second auxiliary exposed portion WD2 , and the third auxiliary exposed portion WD3 shielded by the touch electrodes can be sequentially increased, thereby further reducing the first auxiliary exposure portion.
  • the exposed part WD1 , the second auxiliary exposed part WD2 and the third auxiliary exposed part WD3 reflect light, which leads to the problems of light emission interference and poor light mixing effect.
  • the second auxiliary sub-overlap area S12 may also be approximately equal to the third auxiliary sub-overlap area S13, for example, the second auxiliary sub-overlap area S12 is equal to the third auxiliary sub-overlap area S13, both equal to 0; or,
  • the fourth auxiliary sub-overlap area S14 is equal to at least one of the first auxiliary sub-overlap area S11, the second auxiliary sub-overlap area S12, and the third auxiliary sub-overlap area S13; or, the fourth auxiliary sub-overlap area S14 is larger than at least one of the first auxiliary sub-overlapping area S11 , the second auxiliary sub-overlapping area S12 , and the third auxiliary sub-overlapping area S13 .
  • the fourth auxiliary sub-overlap area S14 may be made larger than the first auxiliary sub-overlap area S11 .
  • the fourth auxiliary exposed portion WD4 shielded by the touch electrodes (for example, the second touch electrodes 820 ) can be made larger than the first auxiliary exposed portion WD1 , thereby further reducing the light reflected from the fourth auxiliary exposed portion WD4 , resulting in light emission interference and The problem of poor mixing effect.
  • the fourth auxiliary sub-overlap area S14 may also be substantially equal to the first auxiliary sub-overlap area S11.
  • the first capacitor in the first color sub-pixel (for example, a second capacitor of the first capacitor
  • the orthographic projection of the electrode plate Cst2 on the base substrate 1000 and the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 have a first storage overlap area SC1 .
  • the first storage overlap area SC1 includes the orthographic projection of the storage conductive portion Cst2 in the first color sub-pixel on the base substrate 1000 and the touch electrode (eg, the second touch electrode 820 ) on the base substrate 1000 .
  • the grid structure formed by the touch electrodes in at least one sub-pixel includes at least 5 inner corners, including at least 2 obtuse corners and 2 an acute angle.
  • the grid structure formed by the touch electrodes in at least one sub-pixel has at least 4 inner corner angles that are not equal.
  • the second touch electrodes 820 form inner angles A1 to A5, where A1 is equal to 90°, A2 and A5 are acute angles, and the angles are 30°-80°; A3 and A4 are continuous obtuse angles, and the angle It is 95° ⁇ 150°.
  • A2 and A5 are equal acute angles
  • A3 and A4 are equal obtuse angles.
  • the interior angles that form the grid are all equal, for example: forming a regular pentagon, or a hexagon.
  • the grid structure formed by the touch electrodes in at least one sub-pixel includes at least 5 sides, of which at least 2 sides have different lengths. equal.
  • the second touch electrodes 820 form five sides of the inner corners of A1-A5.
  • a1 to a5 are not equal in length.
  • the structure formed by the touch electrodes in at least one sub-pixel includes at least four sides, at least two of which have unequal widths.
  • the width of at least one side gradually decreases.
  • the a4 side from the beginning of the A4 corner to the end of the A5 corner, the width becomes smaller.
  • at least one side includes three parts with unequal widths. For example, as shown in FIG.
  • one side of the touch electrode includes at least three parts with unequal widths, DC1 is greater than DC2, and DC1 is greater than DC4. Among them, the width of DC4 is small, which can reduce the overlap with the power signal line and reduce the influence on the touch signal.
  • the touch electrodes may form a polygonal structure with equal sides or equal widths.
  • regular pentagon regular hexagon.
  • the orthographic projection of the control electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 has a second storage overlap area SC2 .
  • the second storage overlap area SC2 includes the orthographic projection of the storage conductive portion Cst2 in the second color sub-pixel on the base substrate 1000 and the touch electrode (eg, the second touch electrode 820 ) on the base substrate 1000 .
  • the orthographic projection of the control electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 has a third storage overlap area SC3 .
  • the third storage overlap area SC3 includes the orthographic projection of the storage conductive portion Cst2 in the third color sub-pixel on the base substrate 1000 and the touch electrode (eg, the second touch electrode 820 ) on the base substrate 1000 .
  • the orthographic projection of the control electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 has a fourth storage overlap area SC4 .
  • the fourth storage overlap area SC4 includes the orthographic projection of the storage conductive portion Cst2 in the fourth color sub-pixel on the base substrate 1000 and the touch electrode (eg, the second touch electrode 820 ) on the base substrate 1000 .
  • the first storage overlap area SC1 , the second storage overlap area SC2 and the fourth storage overlap area SC1 may be At least one of the storage overlap areas SC4 is larger than the third storage overlap area SC3.
  • the first storage overlap area SC1, the second storage overlap area SC2, and the fourth storage overlap area SC4 may all be larger than the third storage overlap area SC3; or, the first storage overlap area SC1 or the fourth storage overlap area SC1 At least one of the overlapping areas SC4 is larger than the second storage overlapping area SC2, and the second storage overlapping area SC2 is equal to the third storage overlapping area SC3.
  • the first storage overlap area SC1 may be larger than the second storage overlap area SC2 .
  • the first capacitors in the first color sub-pixels can be blocked by the touch electrodes (eg, the second touch electrodes 820 ) as much as possible.
  • the touch electrodes include a first electrode portion DC1 and a second electrode portion DC2 ;
  • the orthographic projection of the first electrode portion DC1 on the base substrate 1000 and the orthographic projection of the auxiliary conductive portion on the base substrate 1000 have an overlapping area, and the orthographic projection of the second electrode portion DC2 on the base substrate 1000 and the auxiliary conductive portion on the base substrate 1000 overlap.
  • the orthographic projections of the base substrate 1000 do not overlap.
  • the width of the first electrode portion DC1 can be made larger than the width of the second electrode portion DC2. In this way, the touch electrodes can better shield the auxiliary conductive portion.
  • the touch electrode (eg, the second touch electrode 820 ) includes at least three parts with different widths, and the touch electrode includes a first electrode part DC1 and a second The electrode portion DC2 and the third electrode portion DC3 (not shown); for example, the orthographic projection of the first electrode portion DC1 on the base substrate 1000 and the orthographic projection of the auxiliary conductive portion on the base substrate 1000 have an overlapping area, and the second electrode portion DC1 has an overlapping area.
  • the orthographic projection of the portion DC2 on the base substrate 1000 does not overlap with the orthographic projection of the auxiliary conductive portion on the base substrate 1000, and the orthographic projection of the third electrode portion DC3 on the base substrate 1000 and the orthographic projection of the storage conducting portion on the base substrate 1000 do not overlap. Projections have overlapping areas.
  • the width of the first electrode portion DC1 is smaller than the width of the second electrode portion DC2, and the width of the second electrode portion DC2 is smaller than the width of the third electrode portion DC3.
  • the touch electrode has a protruding part in at least one corresponding sub-pixel area; for example: DC1.
  • the touch electrodes have protruding parts in at least two corresponding sub-pixel regions, and the protruding parts have different protruding directions or different widths.
  • the touch electrodes located between adjacent opening regions are on the lining
  • the orthographic projection of the base substrate 1000 overlaps with the orthographic projection of the at least two light emitting layers of different colors on the base substrate 1000 .
  • the orthographic projection of the touch electrodes located between adjacent opening regions on the base substrate 1000 is replaced by the orthographic projection of the light-emitting layers of at least two different colors on the base substrate 1000 . cover.
  • the orthographic projection of the touch electrodes located between adjacent opening regions on the base substrate 1000 can be caused by two light-emitting layers of different colors on the front side of the base substrate 1000 .
  • Projection overlay The orthographic projections of the touch electrodes (eg, the second touch electrodes 820 ) located between adjacent opening regions on the base substrate 1000 can also be covered by the orthographic projections of the light-emitting layers of three different colors on the base substrate 1000 .
  • the touch electrode (for example, 820 ) and the storage conductive portion WCst2 have an overlapping area (for example, SC1 ), and the touch electrode (for example, 820 ) is covered by at least three light-emitting layers of different colors on the substrate.
  • the orthographic projections of the substrates 1000 overlap, and the area of the orthographic projection of the storage conductive portion WCst2 on the base substrate 1000 is Sn, where SC1 /Sn is approximately 1/5 to 4/5.
  • the area of the touch electrode covered by the orthographic projection of the light-emitting layers of at least three different colors on the base substrate 1000 and the area of the orthographic projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 are equal to each other.
  • the ratio is approximately 3/10 to 2/5.
  • the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 1/5.
  • the ratio of the area of the touch electrode covered by the orthographic projection of the light-emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 3/10.
  • the ratio of the area of the touch electrode covered by the orthographic projection of the at least three light-emitting layers of different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 2/5.
  • the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 1/2.
  • it can be designed according to the requirements of the actual application environment, which is not limited here.
  • the touch electrodes eg, , the orthographic projection of the second touch electrodes 820
  • the touch electrodes is located within the orthographic projection of the first color light-emitting layer 610 on the base substrate 1000 .
  • the area of the first color light-emitting layer 610 can be increased to ensure the light-emitting effect.
  • the auxiliary conductive part is further shielded.
  • the touch electrodes eg, , the orthographic projection of the second touch electrodes 820
  • the touch electrodes is located within the orthographic projection of the second color light-emitting layer 620 on the base substrate 1000 .
  • the area of the light-emitting layer 620 of the second color can be increased to ensure the light-emitting effect.
  • the auxiliary conductive part is further shielded.
  • the touch electrodes eg, , the orthographic projection of the second touch electrode 820
  • the touch electrodes is located within the orthographic projection of the third color light-emitting layer 630 on the base substrate 1000 .
  • the area of the third-color light-emitting layer 630 can be increased to ensure the light-emitting effect.
  • the auxiliary conductive part is further shielded by covering at least part of the boundary ES3 of the third color light emitting layer 630 with the auxiliary conductive part.
  • the touch electrodes (for example, , the orthographic projection of the second touch electrodes 820 ) on the base substrate 1000 is located within the orthographic projection of the fourth color light-emitting layer 640 on the base substrate 1000 .
  • the area of the fourth color light-emitting layer 640 can be increased to ensure the light-emitting effect.
  • the auxiliary conductive part is further shielded.
  • the stacking position of the light-emitting layers is not limited to those listed in this embodiment, and can be adjusted according to the actual situation or process conditions, for example: different color light-emitting layers are in the same steps. Production or production in different steps.
  • the stacking position of the light-emitting layers is not limited to that shown in FIG. 5e, the sequence is 610, 620, 630 from the pixel defining layer 950 to the top, of course, it can also be sequentially from the pixel defining layer 950 to the top, the sequence is 630, 620 , 610 or 610, 630, 620, or 630, 610, 620, etc.
  • the third Between the boundary ES3 of the orthographic projection of the color light-emitting layer 630 on the base substrate 1000 and the boundary CK3 of the orthographic projection of the base substrate 1000 surrounding the touch electrodes (eg, the second touch electrodes 820 ) surrounding the third color sub-pixels
  • the touch electrodes eg, the second touch electrodes 820
  • the boundary ES2 of the orthographic projection of the second color light-emitting layer 620 on the base substrate 1000 and the touch electrodes (eg, the second touch electrodes 820 ) surrounding the second color sub-pixels are on the base substrate
  • the first minimum distance W0S1 is greater than the second minimum distance W0S2.
  • the area of the third-color light-emitting layer 630 can be further increased to ensure the light-emitting effect.
  • the auxiliary conductive portion is further shielded.
  • the light-emitting area of the second color sub-pixel is small, when the third-color light-emitting layer 630 extends into the second-color light-emitting layer 620, the influence on the light-emitting effect of the second color sub-pixel is small.
  • the touch electrodes for example, the first color sub-pixels surrounding the opening area KK1 in the first color sub-pixels
  • the area enclosed by the orthographic projections of the two touch electrodes 820) on the base substrate 1000 is the first grid area WG1.
  • the area enclosed by the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 surrounding the opening area KK2 in the second color sub-pixel is the second grid area WG2 .
  • the area enclosed by the orthographic projection of the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 surrounding the opening area KK3 in the sub-pixels of the third color is the third grid area WG3 .
  • the third grid area WG3 is greater than the second grid area WG2 is greater than the first grid area WG1.
  • the third grid area WG3, the second grid area WG2 and the first grid area WG1 can be respectively associated with the opening area KK3 in the third color sub-pixel, the opening area KK2 in the second color sub-pixel and the first color sub-pixel
  • the opening area KK1 in the sub-pixel is proportional, so that the light transmittance can be improved.
  • the first touch electrodes 810 and/or the second touch electrodes are not required to be all closed grids, and the touch electrodes corresponding to partial regions or individual sub-pixels may have gaps. or disconnect.
  • the touch electrodes corresponding to partial regions or individual sub-pixels may have gaps. or disconnect.
  • Fig. 1-Fig. 2 and Fig. 5a-Fig. 5i, Fig. 6f, Fig. 6g-Fig. 11: at the edge of the display area AA near the non-display area, or in the non-display area, or corresponding to individual sub-pixels
  • the touch electrodes are chipped or disconnected.
  • the touch electrodes for example, the touch electrodes of the fourth color sub-pixels surrounding the opening area KK4 of the fourth color sub-pixels, for example, the The area enclosed by the orthographic projections of the two touch electrodes 820) on the base substrate 1000 is the fourth grid area WG4.
  • the first grid area WG1 corresponding to the first color sub-pixel can be made larger than the fourth grid area WG4 corresponding to the fourth color sub-pixel.
  • the first grid area WG1 corresponding to the first color sub-pixel may be approximately equal to the fourth grid area WG4 corresponding to the fourth color sub-pixel, which is not limited herein.
  • the first mesh area WG1 may be 850 ⁇ 920 ⁇ m 2 .
  • the first mesh area WG1 may be 860 ⁇ m 2 to 910 ⁇ m 2 .
  • the first mesh area WG1 may be 850 ⁇ m 2 .
  • the first mesh area WG1 may be 860 ⁇ m 2 .
  • the first mesh area WG1 may be 900 ⁇ m 2 .
  • the first mesh area WG1 may be 910 ⁇ m 2 .
  • the first mesh area WG1 may be 920 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the first mesh area WG1 may also be 30.5*28.5 ⁇ m 2 to 35.5*30.5 ⁇ m 2 .
  • the first mesh area WG1 may be 30.5*28.5 ⁇ m 2 .
  • the first mesh area WG1 may be 31.5*29.5 ⁇ m 2 .
  • the first mesh area WG1 may be 32.5*29.1 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the second mesh area WG2 may be 950-1050 ⁇ m 2 .
  • the second mesh area WG2 may be 960 ⁇ 1040 ⁇ m 2 .
  • the second mesh area WG2 may be 950 ⁇ m 2 .
  • the second mesh area WG2 may be 960 ⁇ m 2 .
  • the second mesh area WG2 may be 980 ⁇ m 2 .
  • the second mesh area WG2 may be 1000 ⁇ m 2 .
  • the second mesh area WG2 may be 1040 ⁇ m 2 .
  • the second mesh area WG2 may be 1050 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the second mesh area WG2 may be 30.1*30.1 ⁇ m 2 to 32.1*32.1 ⁇ m 2 .
  • the second mesh area WG2 may be 30.5*30.5 ⁇ m 2 to 32.0*32.0 ⁇ m 2 .
  • the second mesh area WG2 may be 30.1*30.1 ⁇ m 2 .
  • the second mesh area WG2 may be 30.5*30.5 ⁇ m 2 .
  • the second mesh area WG2 may be 31.6*31.6 ⁇ m 2 .
  • the second mesh area WG2 may be 32.0*32.0 ⁇ m 2 .
  • the second mesh area WG2 may be 32.1*32.1 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third mesh area WG3 may be 1100 ⁇ m 2 to 1300 ⁇ m 2 .
  • the third mesh area WG3 may be 1150 ⁇ m 2 to 1250 ⁇ m 2 .
  • the third mesh area WG3 may be 1100 ⁇ m 2 .
  • the third mesh area WG3 may be 1150 ⁇ m 2 .
  • the third mesh area WG3 may be 1200 ⁇ m 2 .
  • the third mesh area WG3 may be 1225 ⁇ m 2 .
  • the third mesh area WG3 may be 1300 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third mesh area WG3 may be 32*32 ⁇ m 2 to 37*37 ⁇ m 2 .
  • the third mesh area WG3 may be 33*33 ⁇ m 2 to 36*36 ⁇ m 2 .
  • the third mesh area WG3 may be 32*32 ⁇ m 2 .
  • the third mesh area WG3 may be 33*33 ⁇ m 2 .
  • the third grid area WG3 may be 34*34 ⁇ m 2.
  • the third mesh area WG3 may be 35*35 ⁇ m 2 .
  • the third mesh area WG3 may be 36*36 ⁇ m 2 .
  • the third mesh area WG3 may be 37*37 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth grid area WG4 may be 850 ⁇ 920 ⁇ m 2 .
  • the fourth mesh area WG4 may be 860 ⁇ m 2 to 910 ⁇ m 2 .
  • the fourth mesh area WG4 may be 850 ⁇ m 2 .
  • the fourth mesh area WG4 may be 860 ⁇ m 2 .
  • the fourth mesh area WG4 may be 900 ⁇ m 2 .
  • the fourth mesh area WG4 may be 910 ⁇ m 2 .
  • the fourth mesh area WG4 may be 920 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth mesh area WG4 may also be 30.5*28.5 ⁇ m 2 to 35.5*30.5 ⁇ m 2 .
  • the fourth mesh area WG4 may be 30.5*28.5 ⁇ m 2 .
  • the fourth mesh area WG4 may be 31.5*29.5 ⁇ m 2 .
  • the fourth mesh area WG4 may be 32.5*29.1 ⁇ m 2 .
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the opening area KK3 in the third color sub-pixel and the opening area KK1 in the first color sub-pixel are may be arranged along the first direction F1.
  • the opening areas KK2 in the second color sub-pixels and the opening areas KK4 in the fourth color sub-pixels may also be arranged along the first direction F1.
  • the area surrounded by the inner boundary NS3 of the touch electrodes (eg, the second touch electrodes 820 ) surrounding the opening area KK3 in the third color sub-pixel has a first width WK1 perpendicular to the first direction F1 .
  • the area surrounded by the inner boundary NS1 of the touch electrodes (eg, the second touch electrodes 820 ) surrounding the opening area KK1 in the first color sub-pixel has a second width WK2 perpendicular to the first direction F1 .
  • the area surrounded by the inner boundary NS2 of the touch electrodes (eg, the second touch electrodes 820 ) surrounding the opening area KK2 in the second color sub-pixel has a third width WK3 perpendicular to the first direction F1 .
  • the area surrounded by the inner boundary NS4 of the touch electrodes (eg, the second touch electrodes 820 ) surrounding the opening area KK4 in the fourth color sub-pixel has a fourth width WK4 perpendicular to the first direction F1.
  • the first direction F1 and the row direction F3 may form a certain angle, for example, the angle may be greater than 0 degrees and less than 90 degrees.
  • the first direction F1 and the row direction F3 may form 25 to 75 degrees.
  • the first direction F1 and the row direction F3 may form 30 to 60 degrees.
  • the first direction F1 and the row direction F3 may form 25 degrees.
  • the first direction F1 and the row direction F3 may form 30 degrees.
  • the first direction F1 and the row direction F3 may form 45 degrees.
  • the first direction F1 and the row direction F3 may form 60 degrees.
  • the first direction F1 and the row direction F3 may form 75 degrees.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the first width WK1 may be 34.0 ⁇ m ⁇ 35.0 ⁇ m.
  • the first width WK1 may be 34.1 ⁇ m ⁇ 34.9 ⁇ m.
  • the first width WK1 may be 34.0 ⁇ m.
  • the first width WK1 may be 34.1 ⁇ m.
  • the first width WK1 may be 34.4 ⁇ m.
  • the first width WK1 may be 34.8 ⁇ m.
  • the first width WK1 may be 34.9 ⁇ m.
  • the first width WK1 may be 35.0 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the second width WK2 may be 30.5 ⁇ m ⁇ 31.5 ⁇ m.
  • the second width WK2 may be 30.7 ⁇ m ⁇ 31.4 ⁇ m.
  • the second width WK2 may be 30.5 ⁇ m.
  • the second width WK2 may be 30.7 ⁇ m.
  • the second width WK2 may be 31.2 ⁇ m.
  • the second width WK2 may be 31.4 ⁇ m.
  • the second width WK2 may be 31.5 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third width WK3 may be 30.8 ⁇ m ⁇ 32.5 ⁇ m.
  • the third width WK3 may be 31.0 ⁇ m ⁇ 32.0 ⁇ m.
  • the third width WK3 may be 30.8 ⁇ m.
  • the third width WK3 may be 31.0 ⁇ m.
  • the third width WK3 may be 31.6 ⁇ m.
  • the third width WK3 may be 31.8 ⁇ m.
  • the third width WK3 may be 32.0 ⁇ m.
  • the third width WK3 may be 32.5 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth width WK4 may be 28.8 ⁇ 31.5 ⁇ m.
  • the fourth width WK4 may be 29.2 ⁇ m ⁇ 30.5 ⁇ m.
  • the fourth width WK4 may be 28.8 ⁇ m.
  • the fourth width WK4 may be 29.2 ⁇ m.
  • the fourth width WK4 may be 29.9 ⁇ m.
  • the fourth width WK4 may be 30.5 ⁇ m.
  • the fourth width WK4 may be 31.5 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the first width WK1 can be made larger than the second width WK2 .
  • the opening area KK3 in the third color sub-pixel and the opening area KK1 in the first color sub-pixel can be guaranteed, and the light transmittance can be improved.
  • the difference between the first width WK1 and the second width WK2 may be 3.0 ⁇ m ⁇ 4.0 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.1 ⁇ m ⁇ 3.9 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.0 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.3 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.6 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.8 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 3.9 ⁇ m.
  • the difference between the first width WK1 and the second width WK2 may be 4.0 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third width WK3 can be made larger than the fourth width WK4 .
  • the opening area KK2 in the second color sub-pixel and the opening area KK4 in the fourth color sub-pixel can be guaranteed, and the light transmittance can be improved.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.0 ⁇ m ⁇ 2.0 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.2 ⁇ m ⁇ 1.8 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.0 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.2 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.5 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.7 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 1.8 ⁇ m.
  • the difference between the third width WK3 and the fourth width WK4 may be 2.0 ⁇ m.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the touch electrodes (eg, the second touch electrodes 820 ) having an overlapping area with the orthographic projection of the auxiliary conductive portion
  • the extension direction F0 of the grid lines has an included angle ⁇ with the third direction; and 15° ⁇ 60°; optionally, the included angle ⁇ is 20° ⁇ 50°.
  • the third direction is substantially perpendicular to the extending direction of the data line pattern, for example, the third direction may be the row direction F4.
  • tan ⁇ A1/A2; wherein, A1 represents the width of the auxiliary conductive portion in the third direction perpendicular to the third direction, and A2 represents the width of the auxiliary conductive portion in the third direction.
  • A1 represents the width of the auxiliary conductive portion in the third direction perpendicular to the third direction
  • A2 represents the width of the auxiliary conductive portion in the third direction.
  • the specific value of ⁇ can be determined according to the requirements of practical applications, which is not limited here.
  • the touch electrodes (for example, the first color sub-pixels) have an overlapping area with the orthographic projection of the auxiliary conductive parts in the first color sub-pixels.
  • the extending direction of the grid lines of the two touch electrodes 820) and the third direction have a first included angle ⁇ 1.
  • the extending direction of the grid lines of the touch electrodes (eg, the second touch electrodes 820 ) having an overlapping area with the orthographic projection of the auxiliary conductive portions in the second color sub-pixels has a second included angle ⁇ 2 with the third direction.
  • the extending direction of the grid lines of the touch electrodes (eg, the second touch electrodes 820 ) having overlapping areas with the orthographic projections of the auxiliary conductive portions in the third color sub-pixels has a third included angle ⁇ 3 with the third direction.
  • the first included angle can be made smaller than the second included angle and smaller than the third included angle, so that the touch electrodes (eg, the second touch electrodes 820 ) can cover the auxiliary conductive layer as much as possible.
  • at least two angles of ⁇ 1, ⁇ 2, and ⁇ 3 may be the same.
  • the opening areas of the adjacent four sub-pixels are used as an opening group
  • the touch electrodes for example, the second The orthographic projection of the grid intersection points of the touch electrodes 820
  • the orthographic projection of the grid intersections of the touch electrodes is approximately at the center of the area surrounded by the orthographic projection of the opening group on the base substrate 1000 . In this way, the grid intersections can be evenly distributed in the display area, which further improves the display uniformity.
  • the orthographic projection of the first electrode 510 (eg, the anode) in the first color sub-pixel on the base substrate 1000 and the touch electrode (eg, the overlapping area between the orthographic projections of the second touch electrodes 820) on the base substrate 1000 has a first anode overlap area BS1;
  • the overlapping area between the projection and the orthographic projection of the touch electrode (eg, the second touch electrode 820 ) on the base substrate 1000 has a second anode overlap area BS2 ;
  • the first electrode 530 in the third color sub-pixel is in
  • the overlapping area between the orthographic projection of the base substrate 1000 and the touch electrodes (eg, the second touch electrodes 820 ) on the base substrate 1000 has a third anode overlap area BS3; in the fourth color sub-pixel
  • the first anode overlap area BS1 may be made larger than the third anode overlap area BS3. It is also possible to make the second anode overlap area BS2 larger than the third anode overlap area BS3. It is also possible to make the fourth anode overlap area BS4 larger than the third anode overlap area BS3.
  • the first anode overlapping area BS1 can be made larger than the second anode overlapping area BS2 .
  • the first anode overlapping area BS1 may be made substantially equal to the second anode overlapping area BS2.
  • the first anode overlapping area BS1 is larger than the fourth anode overlapping area BS4 .
  • the first anode overlap area BS1 may be made substantially equal to the fourth anode overlap area BS4.
  • the fourth anode overlapping area BS4 is larger than the second anode overlapping area BS2 .
  • the fourth anode overlapping area BS4 may be substantially equal to the second anode overlapping area BS2.
  • the first anode overlap area BS1 is 2.5 ⁇ m 2 -35 ⁇ m 2 .
  • the first anode overlap area BS1 is 3 ⁇ m 2 -25 ⁇ m 2 .
  • the first anode overlap area BS1 may be set to 6 ⁇ m 2 to 20 ⁇ m 2 .
  • the second anode overlap area BS2 is 0 ⁇ m 2 -30 ⁇ m 2 .
  • the second anode overlap area BS2 is 1.5 ⁇ m 2 -25 ⁇ m 2 .
  • the second anode overlap area BS2 may be set to 6 ⁇ m 2 to 20 ⁇ m 2 .
  • the third anode overlap area BS3 is 0 ⁇ m 2 -25 ⁇ m 2 .
  • the third anode overlap area BS3 is 1.5 ⁇ m 2 -25 ⁇ m 2 .
  • the third anode overlap area BS3 may be 5 ⁇ m 2 to 20 ⁇ m 2 .
  • the fourth anode overlap area BS4 is 0 ⁇ m 2 -30 ⁇ m 2 .
  • the fourth anode overlap area BS4 is 1.5 ⁇ m 2 -25 ⁇ m 2 .
  • the first anode overlap area BS4 may be 6 ⁇ m 2 to 20 ⁇ m 2 .
  • an auxiliary insulating layer may be provided on the side of the second touch electrodes 820 away from the base substrate 1000 .
  • An auxiliary electrode 840 may also be provided on the side of the auxiliary insulating layer facing away from the base substrate 1000 .
  • the auxiliary electrode 840 is in a floating state and does not transmit signals.
  • the auxiliary electrodes 840 and the first touch electrodes 810 may be fabricated in the same layer and/or formed of the same material.
  • an insulating layer 830 is provided on the side of the first touch electrodes 810 away from the base substrate 1000 .
  • Auxiliary electrodes 840 can also be provided on the side of 830 away from the base substrate 1000.
  • the auxiliary electrodes 840 are in a floating state and do not transmit signals.
  • the auxiliary electrodes 840 can be fabricated in the same layer as the second touch electrodes 820 (or 811) and/or or the same material.
  • the display panel further includes a power input line VDDIN located in the non-display area.
  • the power signal line pattern VDD in the display area is electrically connected to the power input line VDDIN.
  • the power signal line patterns VDD of two adjacent columns of sub-pixels are electrically connected through a power input line VDDIN; or, the power signal line patterns VDD corresponding to two adjacent columns of sub-pixels with the same color are electrically connected through a power input line VDDIN.
  • the power input line VDDIN may be disposed on the same layer as the power signal line pattern VDD.
  • the power supply input line VDDIN can also be arranged in a different layer from the power supply signal line pattern VDD, so that the power supply signal line pattern VDD and the power supply input line VDDIN also need to be electrically connected through via holes.
  • the data line pattern DA and the power input line VDDIN may not be provided on the same conductive layer.
  • An embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure, for example, an organic light emitting diode (Organic Light Emitting Diode, OLED).
  • OLED Organic Light Emitting Diode
  • the problem-solving principle of the display device is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the aforementioned implementation of the display panel, and repeated details will not be repeated here.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, a watch, a wristband, etc.
  • Other essential components of the display device are all components that those of ordinary skill in the art should understand, and will not be repeated here, nor should it be used as a limitation to the present disclosure.

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Abstract

本公开提供了显示面板及显示装置，其中，显示面板，包括：衬底基板，晶体管阵列层，像素限定层，触控电极，其中，第一颜色子像素的开口区域的面积小于第三颜色子像素的开口区域的面积，且第二颜色子像素的开口区域的面积小于第三颜色子像素的开口区域的面积；第一颜色子像素中的第二电容在衬底基板的正投影与触控电极在衬底基板的正投影具有第一辅助交叠面积；第二颜色子像素中的第二电容在衬底基板的正投影与触控电极在衬底基板的正投影具有第二辅助交叠面积；第三颜色子像素中的第二电容在衬底基板的正投影与触控电极在衬底基板的正投影具有第三辅助交叠面积；第一辅助交叠面积和第二辅助交叠面积中的至少一个大于第三辅助交叠面积。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求在2020年08月17日提交中国专利局、申请号为202010822808.3、申请名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。
发明内容
本公开实施例提供的一种显示面板，包括：
衬底基板；
晶体管阵列层，位于所述衬底基板上；
像素限定层，位于所述晶体管阵列层背离所述衬底基板一侧；
触控电极，位于所述像素限定层背离所述衬底基板一侧；
所述衬底基板具有显示区，所述显示区包括多个子像素；所述子像素包括像素电路和发光元件；所述像素电路包括栅线图形、数据线图形、电源信号线图形；
所述晶体管阵列层包括多个电容导电部，所述子像素包括对应的所述电容导电部；其中，同一所述子像素中，所述电容导电部与所述子像素对应的数据线图形和/或所述子像素对应的电源信号线图形存在交叠区域；所述电容 导电部至少耦接所述子像素对应的电源信号线图形或所述子像素对应的数据线图形；
所述像素限定层包括多个开口区域，所述子像素包括对应的所述开口区域；
至少部分所述触控电极在所述衬底基板的正投影为网格；
其中，所述多个子像素还包括第一颜色子像素、第二颜色子像素以及第三颜色子像素；所述第一颜色子像素的开口区域的面积小于所述第三颜色子像素的开口区域的面积，且所述第二颜色子像素的开口区域的面积小于所述第三颜色子像素的开口区域的面积；
所述第一颜色子像素中的电容导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第一辅助交叠面积；
所述第二颜色子像素中的电容导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第二辅助交叠面积；
所述第三颜色子像素中的电容导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第三辅助交叠面积；
所述第一辅助交叠面积和所述第二辅助交叠面积中的至少一个大于所述第三辅助交叠面积。
在一些示例中，所述第一辅助交叠面积大于所述第二辅助交叠面积；或者，
所述第一辅助交叠面积大致等于所述第二辅助交叠面积；或者，所述第三辅助交叠面积大致等于所述第二辅助交叠面积。
在一些示例中，所述晶体管阵列层包括：
第一导电层，位于所述衬底基板与所述像素限定层之间；其中，所述第一导电层包括多条数据线图形和多条电源信号线图形；
第一绝缘层，位于所述衬底基板与所述第一导电层之间；
第二导电层，位于所述衬底基板与所述第一绝缘层之间，且所述第二导电层包括：多个辅助导电部，所述子像素的电容导电部包括所述辅助导电部； 其中，同一所述子像素中，所述辅助导电部的第一端在所述衬底基板的正投影与所述电源信号线图形在所述衬底基板的正投影具有交叠区域，所述辅助导电部的第二端在所述衬底基板的正投影与所述数据线图形在所述衬底基板的正投影具有交叠区域；且所述辅助导电部耦接电源信号线图形；
所述第一辅助交叠面积包括所述第一颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
所述第二辅助交叠面积包括所述第二颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
所述第三辅助交叠面积包括所述第三颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积。
在一些示例中，所述第一颜色子像素中的辅助导电部包括第一辅助暴露部，且所述第一辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第一辅助交叠面积包括第一辅助子交叠面积，且所述第一辅助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第一辅助子交叠面积；
所述第二颜色子像素中的辅助导电部包括第二辅助暴露部，且所述第二辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第二辅助交叠面积包括第二辅助子交叠面积，且所述第二辅助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第二辅助子交叠面积；
所述第三颜色子像素中的辅助导电部包括第三辅助暴露部，且所述第三辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第三辅助交叠面积包括第三辅助子交叠面积，且所述第三辅助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第三辅助子交叠面积；
所述第一辅助子交叠面积大于所述第二辅助子交叠面积和所述第三辅助 子交叠面积中的至少一个。
在一些示例中，所述第二辅助子交叠面积大于所述第三辅助子交叠面积；或者，所述第三辅助子交叠面积大致等于所述第二辅助子交叠面积。
在一些示例中，所述第一颜色子像素中，所述第一辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间；和/或，
所述第二颜色子像素中，所述第二辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间；和/或，
所述第三颜色子像素中，所述第三辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间。
在一些示例中，所述辅助导电部在所述衬底基板的正投影具有总面积；
所述第一辅助子交叠面积与所述总面积之间的比值范围为：1/3～2/3；和/或，
所述第二辅助子交叠面积与所述总面积之间的比值范围为：0～1/4；和/或，
所述第三辅助子交叠面积与所述总面积之间的比值范围为：0～1/16。
在一些示例中，所述第一颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第一辅助暴露部在所述衬底基板的正投影；和/或，
所述第二颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第二辅助暴露部在所述衬底基板的正投影；和/或，
所述第三颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第三辅助暴露部在所述衬底基板的正投影。
在一些示例中，所述第一颜色子像素中的辅助导电部还包括第一辅助遮挡部，且所述第一辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第一辅助暴露部在列方向的宽度小于所述第一辅助遮挡部在所述列方向的 宽度；和/或，
所述第二颜色子像素中的辅助导电部还包括第二辅助遮挡部，且所述第二辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第二辅助暴露部在列方向的宽度小于所述第二辅助遮挡部在所述列方向的宽度；和/或，
所述第三颜色子像素中的辅助导电部还包括第三辅助遮挡部，且所述第三辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第三辅助暴露部在列方向的宽度小于所述第三辅助遮挡部在所述列方向的宽度。
在一些示例中，所述像素电路还包括第一电容；
所述第一颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第一存储交叠面积；
所述第二颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第二存储交叠面积；
所述第三颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第三存储交叠面积；
所述第一存储交叠面积和所述第二存储交叠面积中的至少一个大于所述第三存储交叠面积。
在一些示例中，所述第一存储交叠面积大于所述第二存储交叠面积。
在一些示例中，所述第二导电层还包括与所述辅助导电部间隔设置的多个存储导电部；所述子像素包括所述存储导电部；所述存储导电部作为所述第一电容的第二极板；
所述第一存储交叠面积包括所述第一颜色子像素中的存储导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
所述第二存储交叠面积包括所述第二颜色子像素中的存储导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
所述第三存储交叠面积包括所述第三颜色子像素中的存储导电部在所述 衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积。
在一些示例中，所述触控电极在所述衬底基板的正投影的形状为网格状，且所述触控电极在所述衬底基板的正投影与所述开口区域在所述衬底基板的正投影不交叠。
在一些示例中，所述触控电极包括第一电极部和第二电极部；其中，所述第一电极部在所述衬底基板的正投影与所述辅助导电部在所述衬底基板的正投影具有交叠区域，所述第二电极部在所述衬底基板的正投影与所述辅助导电部在所述衬底基板的正投影不交叠；
所述第一电极部的宽度大于所述第二电极部的宽度。
在一些示例中，所述显示面板还包括：
发光功能层，位于所述像素限定层与所述触控电极之间，且所述发光功能层包括多个第一颜色发光层、多个第二颜色发光层以及多个第三颜色发光层；
其中，所述第一颜色发光层在所述衬底基板的正投影覆盖所述第一颜色子像素中的开口区域在所述衬底基板的正投影；
所述第二颜色发光层在所述衬底基板的正投影覆盖所述第二颜色子像素中的开口区域在所述衬底基板的正投影；
所述第三颜色发光层在所述衬底基板的正投影覆盖所述第三颜色子像素中的开口区域在所述衬底基板的正投影。
在一些示例中，位于相邻所述开口区域之间的触控电极在所述衬底基板的正投影与至少两种不同颜色的发光层在所述衬底基板的正投影交叠。
在一些示例中，围绕于所述第三颜色子像素的开口区域的触控电极在所述衬底基板的正投影位于所述第三颜色发光层在所述衬底基板的正投影内；和/或，
围绕于所述第二颜色子像素的开口区域的触控电极在所述衬底基板的正投影位于所述第二颜色发光层在所述衬底基板的正投影内；和/或，
围绕于所述第一颜色子像素的开口区域的触控电极在所述衬底基板的正 投影位于所述第一颜色发光层在所述衬底基板的正投影内。
在一些示例中，相邻的所述第三颜色发光层和所述第二颜色发光层，所述第三颜色发光层在所述衬底基板的正投影的边界与所述触控电极在所述衬底基板的正投影的边界之间具有第一最小距离，所述第二颜色发光层在所述衬底基板的正投影的边界与所述触控电极在所述衬底基板的正投影的边界之间具有第二最小距离；
所述第一最小距离大于所述第二最小距离。
在一些示例中，围绕于所述第一颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第一网格面积；
围绕于所述第二颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第二网格面积；
围绕于所述第三颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第三网格面积；
所述第三网格面积大于所述第二网格面积大于第一网格面积。
在一些示例中，所述显示面板包括多个重复单元；所述重复单元包括所述第一颜色子像素、所述第二颜色子像素以及所述第三颜色子像素。
在一些示例中，所述重复单元还包括第四颜色子像素；围绕于所述第四颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第四网格面积；
所述第一颜色子像素对应的第一网格面积大于或大致等于所述第四颜色子像素对应的第四网格面积。
在一些示例中，同一所述重复单元中，所述第三颜色子像素的开口区域和所述第一颜色子像素的开口区域沿第一方向排列；
围绕于所述第三颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向上具有第一宽度；
围绕于所述第一颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向上具有第二宽度；
所述第一宽度大于所述第二宽度。
在一些示例中，同一所述重复单元中，所述第二颜色子像素的开口区域和所述第四颜色子像素的开口区域沿第一方向排列；
围绕于所述第二颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向上具有第三宽度；
围绕于所述第四颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向上具有第四宽度；
所述第三宽度大于所述第四宽度。
在一些示例中，与所述辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与第三方向具有夹角β；且15°≤β≤60°；其中，所述第三方向与所述数据线图形的延伸方向大致垂直。
在一些示例中，tanβ＝A1/A2；其中，A1代表所述辅助导电部在垂直于所述第三方向上的宽度，A2代表所述辅助导电部在所述第三方向上的宽度。
在一些示例中，与第一颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第一夹角；
与第二颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第二夹角；
与第三颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第三夹角；
所述第一夹角小于所述第二夹角小于所述第三夹角。
在一些示例中，以相邻的四个子像素的开口区域为一个开口组，所述触控电极的网格交叉点在所述衬底基板的正投影位于所述开口组在所述衬底基板的正投影所围成的区域中。
在一些示例中，所述触控电极的网格交叉点在所述衬底基板的正投影大致位于所述开口组在所述衬底基板的正投影所围成的区域的中心处。
在一些示例中，所述第四颜色子像素与所述第一颜色子像素的发光颜色相同。
在一些示例中，各所述子像素还包括第一电极；
所述第一颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第一阳极交叠面积；
所述第二颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第二阳极交叠面积；
所述第三颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第三阳极交叠面积；
所述第一阳极交叠面积和所述第二阳极交叠面积中的至少一个大于所述第三阳极交叠面积。
在一些示例中，所述第一阳极交叠面积大于所述第二阳极交叠面积；或者，
所述第一阳极交叠面积大致等于所述第二阳极交叠面积。
本公开实施例提供的另一种显示面板，包括：
衬底基板；
晶体管阵列层，位于所述衬底基板上；
像素限定层，位于所述晶体管阵列层背离所述衬底基板一侧；
触控电极，位于所述像素限定层背离所述衬底基板一侧；
所述衬底基板具有显示区，所述显示区包括多个子像素；所述子像素包括像素电路和发光元件；所述像素电路包括栅线图形、数据线图形、电源信号线图形；
所述晶体管阵列层包括多个电容导电部，所述子像素包括对应的所述电容导电部；其中，同一所述子像素中，所述电容导电部与所述子像素对应的数据线图形和/或所述子像素对应的电源信号线图形存在交叠区域；所述电容导电部至少耦接所述子像素对应的电源信号线图形或所述子像素对应的数据线图形；
所述像素限定层包括多个开口区域，所述子像素包括对应的所述开口区域；
至少部分所述触控电极在所述衬底基板的正投影为网格；
所述晶体管阵列层还包括第一导电层，所述电容导电部形成在所述第一导电层；
所述像素电路包括多个晶体管，至少部分晶体管的源极和漏极形成在所述第一导电层。
在一些示例中，所述电容导电部为弧形或不规则图形。
在一些示例中，所述电容导电部包括辅助导电部，所述辅助导电部与所述电源信号线图形、数据线图形、所述触控电极均至少部分交叠。
在一些示例中，相邻两列所述子像素的所述电源信号线图形通过电源输入线电性连接；或者颜色相同的相邻两列所述子像素对应的所述电源信号线图形通过电源输入线电性连接。
在一些示例中，所述电源输入线与所述电源信号线图形位于不同层。
在一些示例中，所述电源信号线图形的宽度大于所述数据线图形的宽度。
在一些示例中，所述数据线图形和所述电源信号线图形不设置于同一导电层；或，所述数据线图形和所述电源输入线不设置于同一导电层。
在一些示例中，所述第一导电层包括层叠设置的第一子导电层和第二子导电层，第一子导电层和第二子导电层之间设置有第一子绝缘层。
在一些示例中，所述电容导电部与所述电源信号线图形交叠面积大于所述电容导电部与所述数据线图形交叠面积。
在一些示例中，所述像素电路包括：第七晶体管、第二晶体管；所述第七晶体管的栅极与第二复位信号线图形耦接，所述第二晶体管的栅极与第一复位信号线图形耦接；第所述一复位信号线图形和所述第二复位信号线图形传输不相同的信号。
在一些示例中，所述像素电路包括：数据写入晶体管、第一晶体管；所述数据写入晶体管的栅极耦接的所述栅线图形，与所述第一晶体管的栅极藕接的所述栅线图形传输不同的时序信号。
本公开实施例提供的一种显示装置，包括上述显示面板。
附图说明
图1为本公开实施例中的一些显示面板的结构示意图；
图2为图1所示的显示面板沿AA’方向上的局部剖视结构示意图；
图3为本公开实施例中的一些像素电路的结构示意图；
图4为本公开实施例中的一些信号时序图；
图5a为本公开实施例中的一些显示面板的布局结构示意图；
图5b为本公开实施例中的又一些显示面板的布局结构示意图；
图5c为图5a所示的显示面板沿AA’方向的剖视结构示意图；
图5d为图5a所示的显示面板沿BB’方向的剖视结构示意图；
图5e为图5a所示的显示面板沿CC’方向的剖视结构示意图；
图5f为图5a所示的显示面板沿DD’方向的剖视结构示意图；
图5g为本公开实施例中的第一颜色子像素中的布局结构示意图；
图5h为本公开实施例中的第二颜色子像素中的布局结构示意图；
图5i为本公开实施例中的第三颜色子像素中的布局结构示意图；
图6a为本公开实施例中的一些半导体层的结构示意图；
图6b为本公开实施例中的一些第三导电层的结构示意图；
图6c为本公开实施例中的一些第二导电层的结构示意图；
图6d为本公开实施例中的一些第一导电层的结构示意图；
图6e为本公开实施例中的一些第一电极层的结构示意图；
图6f为本公开实施例中的一些发光功能层的结构示意图；
图6g为本公开实施例中的一些第二触控电极的结构示意图；
图7a为本公开实施例中的又一些半导体层的结构示意图；
图7b为本公开实施例中的又一些第三导电层的结构示意图；
图7c为本公开实施例中的又一些第二导电层的结构示意图；
图7d为本公开实施例中的又一些第一导电层的结构示意图；
图7e为本公开实施例中的又一些第一电极层的结构示意图；
图7f为本公开实施例中的又一些发光功能层的结构示意图；
图7g为本公开实施例中的又一些第一子导电层的结构示意图；
图7h为本公开实施例中的又一些第二子导电层的结构示意图；
图8a为本公开实施例中的一些触控电极的结构示意图；
图8b为本公开实施例中的又一些触控电极的结构示意图；
图8c为本公开实施例中的又一些触控电极的结构示意图；
图8d为图8c所示的触控电极沿AA’方向的剖视结构示意图；
图9a为本公开实施例中的又一些显示面板的布局结构示意图；
图9b为本公开实施例中的又一些显示面板的布局结构示意图；
图9c为本公开实施例中的又一些显示面板的布局结构示意图；
图10a为本公开实施例中的又一些显示面板的布局结构示意图；
图10b为本公开实施例中的又一些显示面板的布局结构示意图；
图11为本公开实施例中的又一些显示面板的布局结构示意图；
图12为本公开实施例中的又一些显示面板的布局结构示意图；
图13a为本公开实施例中的又一些显示面板的布局结构示意图；
图13b为本公开实施例中的又一些显示面板的布局结构示意图；
图14a为本公开实施例中的又一些显示面板的布局结构示意图；
图14b为本公开实施例中的又一些显示面板的布局结构示意图；
图15为本公开实施例中的又一些显示面板的布局结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的显示面板，如图1与图2所示，可以包括：衬底基板1000，位于衬底基板1000上的晶体管阵列层ZA，位于晶体管阵列层ZA背离衬底基板1000一侧的第一电极层500，位于第一电极层500背离衬底基板1000一侧的像素限定层950，位于像素限定层950背离衬底基板1000一侧的发光功能层600，位于发光功能层600背离衬底基板1000一侧的第二电极700，位于第二电极700背离衬底基板1000一侧的封装层FB以及位于封装层FB背离衬底基板1000一侧的触控电极800。
在本公开一些实施例中，如图1所示，衬底基板1000具有显示区AA和围绕显示区的非显示区。显示区具有多个子像素spx。非显示区具有包围显示区AA的挡墙BK。并且，非显示区还可以包括驱动电路等电路结构，例如：阵列基板行驱动电路(Gate Driver on Array，GOA)等结构，在此不作赘述。
示例性地，子像素spx可以包括：像素电路和发光元件。其中，像素电路具有晶体管和电容，用于驱动发光元件发光。需要说明的是，本文描述的一个或多个实施方式对应于具有7T2C(即7个薄膜晶体管和2个电容)像素电路的显示面板。在另一实施方式中，显示面板可包括不同的像素电路，例如，大于或小于7个薄膜晶体管，以及包括一个或多个电容。
如图3所示，本公开实施例提供的显示面板中，子像素可包括：栅线图形GATE(简写为GA)、第一复位信号线图形RST1、第一初始化信号线图形 VINT1、数据线图形DATA(简写为DA)、发光控制信号线图形EM、电源信号线图形VDD、第二复位信号线图形RST2和第二初始化信号线图形VINT2。
示例性地，第一复位信号线图形RST1和第二复位信号线图形RST2可以传输不相同的信号。
示例性地，第一复位信号线图形RST1和第二复位信号线图形RST2可以位于不同层。例如：第一复位信号线图形RST1与栅线图形GA同层，第二复位信号线图形RST2与数据线图形DA或电源信号线图形VDD同层。
示例性地，第一初始化信号线图形VINT1，第二初始化信号线图形VINT2可以传输相同的信号。
示例性地，第一初始化信号线图形VINT1，第二初始化信号线图形VINT2也可以传输不相同的信号。例如：VINT1为V1，VINT2为V1±5V。
示例性地，第一初始化信号线图形VINT1，第二初始化信号线图形VINT2可以位于不同层。例如：第一初始化信号线图形VINT1与栅线图形GA同层，第二初始化信号线图形VINT2与数据线图形DA或第一复位信号线图形RST1同层。
如图3所示，子像素中的像素电路可包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、数据写入晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一电容Cst以及第二电容C1。
以一个像素电路为例，该像素电路包括的各晶体管均采用P型晶体管。第一晶体管T1可为双栅结构，第一晶体管T1的栅极201g与栅线图形GA耦接，第一晶体管T1的源极S1与第三晶体管T3的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。当然，第一晶体管T1可以为单栅结构或多栅结构，在此不作限定。
第二晶体管T2可为双栅结构，第二晶体管T2的栅极202g与第一复位信号线图形RST1耦接，第二晶体管T2的源极S2与第一初始化信号线图形VINT1耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。当然，第二晶体管T2可以为单栅结构或多栅结构，在此不作限定。
数据写入晶体管T4的栅极204g与栅线图形GA耦接，数据写入晶体管T4的源极S4与数据线图形DA耦接，数据写入晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。示例性地，数据写入晶体管T4的栅极204g耦接的栅线图形GA，与第一晶体管T1的栅极201g藕接的栅线图形GA可以传输不同的时序信号，在此不作限定。
第五晶体管T5的栅极205g与发光控制信号线图形EM耦接，第五晶体管T5的源极S5与电源信号线图形VDD耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形EM耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与发光元件L的阳极耦接。示例性地，第五晶体管T5的栅极205g耦接的发光控制信号线图形EM，与第六晶体管T6的栅极206g藕接的发光控制信号线图形EM可以传输不同的时序信号，在此不作限定。
第七晶体管T7的栅极207g与第二复位信号线图形RST2耦接，第七晶体管T7的漏极D7与发光元件L的阳极耦接，第七晶体管T7的源极S7与第二初始化信号线图形VINT2耦接。
第一电容Cst的第一极板Cst1与第三晶体管T3的栅极203g耦接，第一电容Cst的第二极板Cst2与电源信号线图形VDD耦接。
第二电容C1的第一端(即第一极板C11)耦接数据写入晶体管的第一端(如数据线图形DA)，第二电容C1的第二端(如第二极板C12)耦接电源信号线图形VDD。例如：第二电容C1的第一极板C11与数据线图形DA和/或数据写入晶体管T4耦接，第二电容C1的第二极板C12与电源信号线图形VDD耦接。
可选地，可以是第二电容C1的第二极板C12电性连接电源信号线图形VDD，第二电容C1的第一极板C11延伸到数据线图形DA下方或上方，使得第一极板C12与数据线图形DA在衬底基板上正投影有交叠。
可选地，数据写入晶体管T4的第一端还可以是数据写入晶体管T4的源 极(或者源极区，例如：图3的S4)，或漏极(或者漏极区，例如：图3的D4)，或者栅极(例如：图3的204g)。需要说明的是，图3中的S和D仅是为了进行区别说明的一种附图标记。
可选地，数据写入晶体管T4的第一端还可以是数据写入晶体管T4的源极与数据线图形DA的连接结构。
如图4所示，示例性地，上述结构的像素电路在工作时，其中一个工作周期包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在第一复位时段P1，第一复位信号线图形RST1输入的第一复位信号处于有效电平，第二晶体管T2导通，由第一初始化信号线图形VINT1传输的初始化信号输入至第三晶体管T3的栅极203g，对第三晶体管T3的栅极203g复位。例如：使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零。
在写入补偿时段P2，第一复位信号处于非有效电平，第二晶体管T2截止，栅线图形GA输入的栅极扫描信号处于有效电平，控制第一晶体管T1和数据写入晶体管T4导通，数据线图形DA写入数据信号，并经数据写入晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和数据写入晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和数据写入晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，栅极扫描信号处于非有效电平，第一晶体管T1和数据写入晶体管T4均截止，第二复位信号线RST2输入的第二复位信号处于有效电平，控制第七晶体管T7导通，由第二初始化信号线图形VINT2传输的初始化信号输入至发光元件L的阳极，控制发光元件L不发光。
在发光时段P4，发光控制信号线图形EM写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形VDD 传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件L的阳极，驱动对应的发光元件L发光。
需要说明的是，在晶体管为P型晶体管时，有效电平可以为低电平，无效电平可以为高电平。在晶体管为N型晶体管时，有效电平可以为高电平，无效电平可以为低电平。像素电路的晶体管可以同为P型晶体管或N型晶体管，也可以是同时包括P型晶体管和N型晶体管，例如：T3晶体管为P型晶体管，T1是N型晶体管。可以理解的是，图4仅是对像素电路工作时序的一种示例性介绍，可以根据像素电路的晶体管类型以及实际情况对RST1、RST2、Ga、EM、Da等信号进行适应性调整。
如图5a至图5i所示，示例性地，在制作上述晶体管阵列层ZA时，各膜层的布局如下：沿远离衬底基板1000的方向上依次层叠设置的半导体层400、栅绝缘层910、第三导电层300、层间介质层920、第二导电层200、第一层间绝缘层930、第一导电层100和第二层间绝缘层940。可以理解的是，在衬底基板1000与半导体层400之间还可以包括其他金属层或绝缘层。例如：在衬底基板1000与半导体层400之间还包括至少一层缓冲层或有机绝缘层，例如缓冲层可以是氧化硅或氮化硅等，有机绝缘层可以是聚酰亚胺等。
如图5a至图5i、图6a、图7a所示，半导体层400用于形成像素电路中各晶体管的沟道区(如：101pg～107pg)、源极形成区(如：101ps～107ps)、漏极形成区(如：101pd～107pd)以及连接形成区(如：101px、102px)等；当然，还可以根据需要形成其他结构，例如：形成轻掺杂漏区(lightly doped drain，LDD)，掺杂低浓度杂质的LDD区域形成在至少一个晶体管的漏极形成区(如：101pd～107pd)和晶体管的沟道区(如：101pg～107pg)之间，以及晶体管的源极形成区(如：101ps～107ps)和晶体管的沟道区(如：101pg～107pg)之间。其中，源极形成区和漏极形成区对应的半导体层400由于掺杂作用，导电性 能会优于沟道区对应的半导体层400。可选地，半导体层400可采用非晶硅、多晶硅或者其组合等；例如：半导体层400是低温多晶硅(Low Temperature Poly Silicon，LTPS)、半导体层400包括氧化物半导体材料(例如：铟镓锌氧化物，(Indium Gallium Zinc Oxide，IGZO))，半导体层400包括低温多晶氧化物材料(Low Temperature Polycrystalline Oxide，LTPO)；例如图3所示：T3的半导体层400是低温多晶硅LTPS，T1的半导体层400包括氧化物半导体材料LTPO。
需要说明的是，上述的源极形成区和漏极形成区以及连接形成区可为半导体层在掺杂有n型杂质或p型杂质的导体化区域，从而可以使源极形成区和漏极形成区以及连接形成区作为半导体层的连接结构，以进行电连接。示例性地，源极形成区和漏极形成区对应的半导体层可直接作为对应晶体管的源极或漏极。或者，也可以采用导电材料(例如金属材料)制作与源极形成区接触的源极，采用导电材料(例如金属材料)制作与漏极形成区接触的漏极。
如图5a至图5i、图6b、图7b所示，第三导电层300用于形成像素电路中晶体管的栅极(如：201g～207g)、以及显示面板包括的栅线图形GA、发光控制信号线图形EM、第一复位信号线图形RST1以及第二复位信号线图形RST2的等结构中的至少一个。可选地，像素电路中的第三晶体管T3的栅极203g均复用为该像素电路中的第一电容Cst的第一极板Cst1。当然，像素电路中的第三晶体管T3的栅极203g也可以均复用为该像素电路中的第一电容Cst的第二极板Cst2。
如图5a至图5i、图6c、图7c所示，第二导电层200具有多个辅助导电部WD、与辅助导电部WD间隔设置的多个存储导电部WCst2以及显示面板包括的第一初始化信号线图形VINT1和第二初始化信号线图形VINT2。其中，子像素包括辅助导电部；同一子像素中，辅助导电部WD的第一端在衬底基板1000的正投影与电源信号线图形在衬底基板1000的正投影具有交叠区域，辅助导电部WD的第二端在衬底基板1000的正投影与数据线图形在衬底基板 1000的正投影具有交叠区域。可选地，辅助导电部WD与电源信号线图形、数据线图形、触控电极均至少部分交叠。
并且，子像素包括存储导电部Cst2，用于形成第一电容Cst的第二极板Cst2，即存储导电部Cst2作为第一电容Cst的第二极板Cst2。当然，存储导电部Cst2也可以作为第一电容Cst的第一极板Cst1。辅助导电部WD的形状结构不作限制，可以为规则的长方形，也可以为至少有一个边为弧形的不规则图形。示例性地，辅助导电部WD的一端沿行方向F4延伸到辅助导电部的另一端。
如图3、图5a至图5i、图6d、图7d所示，第一导电层100用于形成像素电路中各晶体管的源极(如：S1～S7)和漏极(如：D1～D7)、以及显示面板包括的数据线图形(如DA1、DA2、DA3、DA4以及DA5)和电源信号线图形VDD。可选地，电源信号线图形VDD的宽度大于数据线图形(如DA1、DA2、DA3、DA4以及DA5)的宽度。需要说明，图6d和图7d中的连接线401、402、403和404，可以是由第一导电层形成，具体布局如图5a至图5i、图6d、图7d所示。
当然，在实际应用中，数据线图形DA和电源信号线图形VDD也可以不设置于同一导电层，例如，如图7g与图7h所示，第一导电层100可以包括层叠设置的第一子导电层111和第二子导电层112，第一子导电层111和第二子导电层112之间设置有第一子绝缘层(未示出)。示例性地，连接线401、402、403和404中的至少一个，与数据线图形(如DA1、DA2)或电源信号线图形VDD同层设置。例如：数据线图形(如DA1、DA2)、连接线401、402和403可以设置于第一子导电层111，电源信号线图形VDD可以设置于第二子导电层112。即，数据线图形(如DA1、DA2)和电源信号线图形VDD不设置于同一导电层。
示例性地，数据线图形(如DA1、DA2)所在的第一子导电层111比电源信号线图形VDD所在的第二子导电层更靠近衬底基板1000。
示例性地，连接线404作为相邻的始化信号线图形之间的连接结构，可 以位于子像素内，也可以位于非显示区。例如：连接线404连接第一初始化信号线图形VINT1和第二初始化信号线图形VINT2。
更详细地说，请继续参阅如图3、图5a至图5i～图7d，第一晶体管T1的栅极201g与第一沟道区101pg交叠，第一晶体管T1的源极S1位于第一源极形成区101ps，第一晶体管T1的漏极D1位于第一漏极形成区101pd。
第二晶体管T2的栅极202g与第二沟道区102pg交叠，第二晶体管T2的源极S2位于第二源极形成区102ps，第二晶体管T2的漏极D2位于第二漏极形成区102pd。
第三晶体管T3的栅极203g与第三沟道区103pg交叠，第三晶体管T3的源极S3位于第三源极形成区103ps，第三晶体管T3的漏极D3位于第三漏极形成区103pd。
数据写入晶体管T4的栅极204g与第四沟道区104pg交叠，数据写入晶体管T4的源极S4位于第四源极形成区104ps，数据写入晶体管T4的漏极D4位于第四漏极形成区104pd。
第五晶体管T5的栅极205g与第五沟道区105pg交叠，第五晶体管T5的源极S5位于第五源极形成区105ps，第五晶体管T5的漏极D5位于第五漏极形成区105pd。
第六晶体管T6的栅极206g与第六沟道区106pg交叠，第六晶体管T6的源极S6位于第六源极形成区106ps，第六晶体管T6的漏极D6位于第六漏极形成区106pd。
第七晶体管T7的栅极207g与第七沟道区107pg交叠，第七晶体管T7的源极S7位于第七源极形成区107ps，第七晶体管T7的漏极D7位于第七漏极形成区107pd。
第三晶体管T3的栅极203g复用为第一电容Cst的第一极板Cst1，第一电容Cst的第二极板Cst2与电源信号线图形VDD耦接。
可选地，电容导电部包括辅助导电部WD，辅助导电部WD可以包括第二电容C1的第二极板C12，即辅助导电部可以部分或全部作为第二电容C1 的第二极板C12。例如：在同一子像素内，辅助导电部WD作为第二电容C1的第二极板C12，数据线图形DA作为第二电容C1的第一极板C11；或者，与第二电容C1的第二极板C12有交叠区域的数据线图形DA作为第二电容C1的第一极板C11。
如图5a至图5i、图6e、图7e所示，第一电极层500用于形成发光元件L的第一电极(如：510、520、530、540)。示例性地，第一电极为发光元件L的阳极(如：510、520、530、540)。需要说明的是，像素限定层950包括多个开口区域(如：KK1、KK2、KK3、KK4)。其中，一个第一电极对应一个开口区域，该开口区域在衬底基板1000的正投影位于对应的第一电极在衬底基板1000的正投影内。例如，开口区域KK1对应第一电极510，开口区域KK2对应第一电极520，开口区域KK3对应第一电极530，开口区域KK4对应第一电极540。示例性地，第一电极可以直接与半导体层电连接；或者，第一电极也可以通过其他导电层与半导体层电连接，例如：第一导电层100。
如图5a至图5i、图6f、图7f所示，发光功能层600用于形成发光元件L的发光层。例如，第一颜色发光层610、第二颜色发光层620、第三颜色发光层630以及第四颜色发光层640。进一步地，发光功能层600还可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。其中，第一颜色发光层610、第二颜色发光层620、第三颜色发光层630以及第四颜色发光层640的边界可以交叠或不交叠。例如，第一颜色发光层610、第二颜色发光层620、第三颜色发光层630以及第四颜色发光层640中的至少两个存在交叠区域，例如：第一颜色发光层610边界延伸到第二颜色发光层620中。
如图2所示，示例性地，封装层FB可以包括FB1、FB2、FB3中的至少一层或多层，其中FB1、FB2、FB3中的至少一层为无机、有机或者有机-无机复合材料，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一、有机材料可以聚酰亚胺(PI)等。例如：封装层FB可以包括层叠设置的第一无机封装层FB1、有机封装层FB2以及第二无机封装层FB3；其中，有机封装层FB2位于挡墙110的内围且覆盖显示区AA；第 一无机封装层FB1与第二无机封装层FB3覆盖显示区AA、挡墙110以及挡墙110的外围区域；其中，第一无机封装层FB1在衬底基板1000的正投影与第二无机封装层FB3在衬底基板1000的正投影重叠。这样通过使第一无机封装层FB1与第二无机封装层FB3延伸到挡墙110的外围区域，从而可以对有机封装层FB与显示区可以较好的阻水与阻氧。
如图2、图6g、图8a、图8b所示，触控电极800可以包括交叉设置的多个第一触控电极810和多个第二触控电极820，以使触控电极800在衬底基板1000的正投影的形状为网格状。示例性地，触控电极800在衬底基板1000的正投影与开口区域(例如KK1、KK2、KK3、KK4)在衬底基板1000的正投影不交叠。可以理解的是，在显示面板中，触控电极800可以是多个第一触控电极810和第二触控电极820中的至少一个，例如：在显示面板的局部显示区域。例如：第一颜色、第二颜色、第三颜色以及第四颜色至少部分对应的子像素区域，触控电极只包括多个第一触控电极810或多个第二触控电极820。
示例性地，多个第一触控电极810设置于同一导电膜层，多个第二触控电极820设置于同一导电膜层。并且，第一触控电极810所在层位于封装层FB背离衬底基板1000一侧，第二触控电极820所在层位于第一触控电极810所在层背离衬底基板1000一侧。以及，第一触控电极810所在层与第二触控电极820所在层之间设置有电极绝缘层830。示例性地，电极绝缘层830可以位于显示区且覆盖显示区。或者，电极绝缘层830也可以不仅覆盖显示区，还可以覆盖非显示区。或者，电极绝缘层830的边缘位于两个挡墙BK之间。当然，在实际应用中，可以根据实际应用进行设计，在此不作限定。
示例性地，在第一触控电极810与封装层FB之间还可以设置一层或多层绝缘层(未出示)。至少一层绝缘层可以为无机、有机或者有机-无机复合材料，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一，有机材料可以聚酰亚胺(PI)等。例如：在第一触控电极810与封装层FB3之间至少设置一层触控电极衬底，材料为氮化硅(SiNx)或氧化硅(SiOX) 或聚酰亚胺(PI)。
示例性地，触控电极衬底可以位于显示区且覆盖显示区。或者，电极绝缘层830也可以不仅覆盖显示区，还可以覆盖非显示区。或者，触控电极衬底的边缘位于两个挡墙BK之间。当然，在实际应用中，可以根据实际应用进行设计，在此不作限定。
在一些示例中，如图8a所示，第一触控电极810在衬底基板1000的正投影和第二触控电极820在衬底基板1000的正投影的形状可以为条状。由于第一触控电极810和第二触控电极820交叉设置，因此可以使第一触控电极810在衬底基板1000的正投影和第二触控电极820在衬底基板1000的正投影形成网格状。或者，如图8b所示，第一触控电极810在衬底基板1000的正投影和第二触控电极820至少之一的部分结构在衬底基板1000的正投影的形状也可以为网格状。
示例性地，第一触控电极810和第二触控电极820交叉设置，第一触控电极810在衬底基板1000的正投影和第二触控电极820在衬底基板1000的正投影形成网格状。或者，至少部分第一触控电极810和第二触控电极820重叠设置，第一触控电极810在衬底基板1000的正投影和第二触控电极820在衬底基板1000的正投影重叠。
当然，本公开包括但不限于此。在实际应用中，可以根据实际应用需求进行设计，在此不作限定。下面以图8b所示的第二触控电极820为例进行说明。
在一些示例中，如图8c和图8d所示，第一触控电极810可以采用第一桥接部811进行电连接。其中，第一桥接部811的第一端可以通过贯穿电极绝缘层830的过孔831与一个第一触控电极810电连接，第一桥接部811的第二端可以通过贯穿电极绝缘层830的过孔832与另一个第一触控电极810电连接。同理，如图8c和图8d所示，第二触控电极820可以采用第二桥接部821进行电连接。其中，第二桥接部821的第一端可以通过贯穿电极绝缘层830的过孔与一个第二触控电极820电连接，第二桥接部821的第二端可 以通过贯穿电极绝缘层830的过孔与另一个第二触控电极820电连接。
需要说明，发光元件可以设置为电致发光二极管，例如有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。其中，发光元件可以包括层叠设置的第一电极500(例如：发光元件的阳极)、发光功能层600以及第二电极700(例如：发光元件的阴极)。当然，本公开包括但不限于此。在实际应用中，可以根据实际应用需求进行设计，在此不作限定。
在实际应用中，上述第三导电层300、第二导电层200、第一导电层100、第二触控电极820、第一触控电极810的材料可以相同或不相同。第三导电层300、第二导电层200、第一导电层100、第二触控电极820、第一触控电极810至少之一包括金属材料或者合金材料或其他导电材料，例如：金属铝(AL)、钛(Ti)、钼(Mo)、钼铌合金、铝钕合金、石墨烯等至少之一。
可选地，第三导电层300、第二导电层200、第一导电层100、第二触控电极820、第一触控电极810至少之一可以形成单层结构，或为采用钼/铝/钼、钛/铝/钛形成子层得到的叠层结构。
可选地，第三导电层300、第二导电层200、第一导电层100、第二触控电极820、第一触控电极810至少之一厚度范围为100nm-500nm。
示例性地：第三导电层300、第二导电层200、第一导电层100可以选自金属铝(AL)、钛(Ti)、钼(Mo)等至少之一；或者，第二触控电极820、第一触控电极810至少之一为钛/铝/钛形成子层得到的叠层结；或者，第二触控电极820、第一触控电极810至少之一材料包括石墨烯。由于导电层表面反射率较高，例如：钼金属材料的表面反射率较高，容易导致第二电容C1会将外界环境光或发光功能层600发的光，反射到相邻的开口区域中，从而导致发光串扰或混光效果差的问题。
有鉴于此，本公开实施例提供了一些显示面板，如图5a至图5i至图7f所示，显示面板包括多个重复单元；重复单元可以包括多个子像素，例如，多个子像素可以包括第一颜色子像素、第二颜色子像素以及第三颜色子像素。 也就是说，可以使重复单元包括第一颜色子像素、第二颜色子像素以及第三颜色子像素。这样可以使显示面板采用第一颜色子像素、第二颜色子像素以及第三颜色子像素进行混光，以实现彩色显示。在一些示例中，第一颜色、第二颜色以及第三颜色可以从红色、绿色以及蓝色中进行选取。例如，第二颜色为红色、第一颜色为绿色、第三颜色为蓝色。当然，本公开实施例包括但不限于此。上述的第一颜色、第二颜色和第三颜色还可为其他颜色。
可选地，重复单元还可以包括第四颜色子像素。这样可以使显示面板采用第一颜色子像素、第二颜色子像素、第三颜色子像素以及第四颜色子像素进行混光，以实现彩色显示。在一些示例中，第四颜色子像素可以为绿色子像素，或者也可以为白色子像素，或者也可以为黄色子像素，还可为其他颜色，在此不作限定。
下面以重复单元包括第一颜色子像素、第二颜色子像素、第三颜色子像素以及第四颜色子像素，且第一颜色和第四颜色为绿色，第二颜色为红色，第三颜色为蓝色为例进行说明。
在一些示例中，如图5a至图5i至图7f所示，第一颜色子像素具有上述任一实施例的像素电路、第一电极510、第一颜色发光层610以及开口区域KK1。其中，第一颜色发光层610在衬底基板1000的正投影覆盖第一颜色子像素中的开口区域KK1在衬底基板1000的正投影，第一颜色子像素的发光区域包括开口区域KK1。示例性地，开口区域KK1可以作为第一颜色子像素的发光区域。
并且，第二颜色子像素具有上述任一实施例的像素电路、第一电极520、第二颜色发光层620以及开口区域KK2。其中，第二颜色发光层620在衬底基板1000的正投影覆盖第二颜色子像素中的开口区域KK2在衬底基板1000的正投影，第二颜色子像素的发光区域包括开口区域KK2。示例性地，开口区域KK2可以作为第二颜色子像素的发光区域。
并且，第三颜色子像素具有上述任一实施例的像素电路、第一电极530、第三颜色发光层630以及开口区域KK3。其中，第三颜色发光层630在衬底 基板1000的正投影覆盖第三颜色子像素中的开口区域KK3在衬底基板1000的正投影，第三颜色子像素的发光区域包括开口区域KK3。示例性地，开口区域KK3可以作为第三颜色子像素的发光区域。
并且，第四颜色子像素具有上述任一实施例的像素电路、第一电极540、第四颜色发光层640以及开口区域KK4。其中，第四颜色发光层640在衬底基板1000的正投影覆盖第四颜色子像素中的开口区域KK4在衬底基板1000的正投影，第四颜色子像素的发光区域包括开口区域KK4。示例性地，开口区域KK4可以作为第四颜色子像素的发光区域。
其中，第一颜色子像素中的开口区域KK1的面积小于第三颜色子像素中的开口区域KK3的面积。第二颜色子像素中的开口区域KK2的面积小于第三颜色子像素中的开口区域KK3的面积。第四颜色子像素中的开口区域KK4的面积小于第三颜色子像素中的开口区域KK3的面积。
示例性地，当绿色发光元件和红色发光元件的发光效率比蓝色发光元件的发光效率高时，对相邻子像素影响大，因此可以使绿色子像素的开口区域的面积小于蓝色子像素的开口区域的面积，以及使红色子像素的开口区域的面积小于蓝色子像素的开口区域的面积，从而可以提高蓝光的出射。并且，这样还会使得绿色子像素和红色子像素的第二电容C1未被开口区域遮挡的部分较多，从而导致第二电容C1露出的较多，进而导致发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图3至图6g所示，晶体管阵列层包括多个电容导电部R，至少一部分子像素包括电容导电部R；其中，同一子像素中，电容导电部R与电源信号线图形VDD和/或数据线图形存在交叠区域。例如，同一子像素中，电容导电部R与电源信号线图形VDD和数据线图形存在交叠区域。或者，同一子像素中，电容导电部R与电源信号线图形VDD存在交叠区域。或者，同一子像素中，电容导电部R与数据线图形存在交叠区域。可选地，电容导电部R与电源信号线图形VDD的交叠面积大于电容导电部R与数据线图形DA的交叠面积。
在具体实施时，在本公开实施例中，如图3至图6g所示，第一颜色子像素中的电容导电部R在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第一辅助交叠面积S1。第二颜色子像素中的电容导电部R在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第二辅助交叠面积S2。第三颜色子像素中的电容导电部R在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第三辅助交叠面积S3。第四颜色子像素中的电容导电部R在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第四辅助交叠面积S4。其中，第一辅助交叠面积S1和第二辅助交叠面积S2以及第四辅助交叠面积S4中的至少一个大于第三辅助交叠面积S3。例如：第一辅助交叠面积S1大于第二辅助交叠面积S2，且第二辅助交叠面积S2大于第三辅助交叠面积S3；或者，第一辅助交叠面积S1大于第二辅助交叠面积S2，且第二辅助交叠面积S2等于第三辅助交叠面积S3；或者第一辅助交叠面积S1大致等于第二辅助交叠面积S2，且第二辅助交叠面积S2大于第三辅助交叠面积S3。这样可以通过触控电极800对第二电容C1进行遮挡，从而可以改善第二电容C1导致的发光干扰和混光效果差的问题。
示例性地，如图3至图6g所示，晶体管阵列层ZA包括多条数据线图形(例如DA1，DA2)和多条电源信号线图形(例如VDD)，且晶体管阵列层ZA包括多个电容导电部R，子像素包括电容导电部R，电容导电部R与电源信号线图形VDD和/或数据线图形DA存在交叠区域；例如：多个电容导电部R形成在第二导电层200。当然，也可以形成在其他导电层，例如：第一导电层。
可选地，至少一部分电容导电部R与电源信号线图形VDD或数据线图形DA形成电容，即；电容导电部R与电源信号线图形VDD或数据线图形DA之间至少存在一层绝缘层。例如：电容导电部R形成第二电容C1的一个电容极板。具体地，电容导电部的部分或全部形成第二电容的第一极板C11或第 二极板C12。
可选地，电容导电部R可以为弧形或不规则图形。
可选地，电容导电部R包括辅助导电部WD，形成在第二导电层200，辅助导电部WD位于数据线图形(例如DA1，DA2)下方，并且辅助导电部WD的第一端连接到电源信号线图形VDD，例如：辅助导电部WD的第一端通过第一层间绝缘层930的过孔连接到电源信号线图形VDD；辅助导电部WD的第二端延伸到数据线图形下方，辅助导电部WD与电源信号线图形和/或数据线图形存在交叠区域，即此时第二电容C1的第二极板C12形成于辅助导电部WD，第二电容C1的第一极板形成于对应子像素数据线图形DA(例如DA1，DA2)；或者第二电容C1的第一极板形成于与辅助导电部WD有交叠区域的对应子像素数据线图形DA(例如DA1，DA2)。
可选地，电容导电部R还可以包括第二辅助导电部WN2(未出示)，第二辅助导电部WN2形成在第二导电层200，第二辅助导电部WN2位于对应子像素的数据线图形(例如DA1，DA2)下方，并且第二辅助导电部WD2的第一端连接到各子像素对应的数据线图形(例如：数据线图形DA1)，例如：第二辅助导电部WD2的第一端通过第一层间绝缘层930的过孔连接到各子像素对应的数据线图形(例如：数据线图形DA1)；第二辅助导电部WN2的第二端延伸到电源信号线图形下方，第二辅助导电部WN2与电源信号线图形和/或数据线图形存在交叠区域，即此时第二电容C1的第一极板形成在第二辅助导电部WD2，第二电容C1的第二极板为电源信号线图形VDD；或者第二电容C1的第二极板形成于与第二辅助导电部WD2有交叠区域的对应子像素电源信号线图形VDD。
为了便于理解，下述至少部分实施例以电容导电部R为辅助导电部WD为例进行说明。示例性地，由于第一颜色子像素中的开口区域KK1的面积小于第三颜色子像素中的开口区域KK3的面积，使得第一颜色子像素中的电容导电部R被开口区域遮挡的部分较少，而第三颜色子像素的电容导电部R被开口区域遮挡的部分较多，这样导致第一颜色子像素中的电容导电部R发射 光的效果较强。本公开实施例通过使第一辅助交叠面积S1大于第三辅助交叠面积S3，可以使第一颜色子像素中的电容导电部R被触控电极800遮挡的部分较多，从而可以降低第一颜色子像素中的电容导电部R导致的发光干扰和混光效果差的问题。
示例性地，由于第二颜色子像素中的开口区域KK2的面积小于第三颜色子像素中的开口区域KK3的面积，使得第二颜色子像素中的电容导电部R被开口区域遮挡的部分较少，而第三颜色子像素的电容导电部R被开口区域遮挡的部分较多，这样导致第二颜色子像素中的电容导电部R发射光的效果较强。本公开实施例通过使第二辅助交叠面积S2大于第三辅助交叠面积S3，可以使第二颜色子像素中的电容导电部R被触控电极800遮挡的部分较多，从而可以降低第二颜色子像素中的电容导电部R导致的发光干扰和混光效果差的问题。
示例性地，由于第四颜色子像素中的开口区域KK4的面积小于第三颜色子像素中的开口区域KK3的面积，使得第四颜色子像素中的电容导电部R被开口区域遮挡的部分较少，而第三颜色子像素的电容导电部R被开口区域遮挡的部分较多，这样导致第四颜色子像素中的电容导电部R发射光的效果较强。本公开实施例通过使第四辅助交叠面积S4大于第三辅助交叠面积S3，可以使第四颜色子像素中的电容导电部R被触控电极800遮挡的部分较多，从而可以降低第四颜色子像素中的电容导电部R导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图6e所示，可以使第一颜色子像素中的开口区域KK1的面积小于第二颜色子像素中的开口区域KK2的面积。例如，可以使绿色子像素的开口区域的面积小于红色子像素的开口区域的面积。这样使得第一颜色子像素相比第二颜色子像素，电容导电部R被开口区域遮挡的部分较少，本公开实施例通过使第一辅助交叠面积S1大致等于第二辅助交叠面积S2；或者，第一辅助交叠面积S1大于第二辅助交叠面积S2，使得第一颜色子像素相比第二颜色子像素，电容导电部R被触控电极800遮 挡的部分较多，从而可以进一步降低第一颜色子像素中的电容导电部R导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，第一颜色子像素的开口区域KK1的面积可以为100μm 2～130μm 2，开口区域KK1的形状不受限制，例如：可以为：多边形，长方形，正方形，菱形，椭圆形，圆形等；当然，还可以是其他不规则图形，例如：至少2条弧线段和1条直线段组成的封闭图形。例如：第一颜色子像素的开口区域KK1为长方形，第一边长度12μm-13μm，第一颜色子像素的开口区域KK1的第二边长度9μm-10μm。
可选地，第一颜色子像素的开口区域KK1的开口面积为10*10μm 2～12*10μm 2或者11*10μm 2～12*10μm 2。可选地，进一步的第一颜色子像素的开口区域KK1的开口面积为13*9μm 2～12*10μm 2。例如，第一颜色子像素的开口区域KK1的面积可以为13*9μm 2(长度*宽度)，或者第一颜色子像素的开口区域KK1的面积可以为12*10μm 2(长度*宽度)。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第二颜色子像素的开口区域KK2的面积可以为120μm 2～200μm 2，开口区域KK2的形状不受限制，例如可以为：长方形，正方形，菱形，椭圆形，圆形等；当然，还可以是其他不规则图形，例如：至少2条弧线段和1条直线段组成的封闭图形。例如：第二颜色子像素的开口区域KK2为正方形，边长度13μm-15μm。可选地，第二颜色子像素的开口区域KK2的开口面积为13*10μm 2～19*10μm 2或者13*15μm 2～18*11μm 2。可选地，第一颜色子像素的开口区域KK1的开口面积可以为13*13μm 2～14*14μm 2。例如，第二颜色子像素的开口区域KK2的面积可以为13*13μm 2，或者，第二颜色子像素的开口区域KK2的面积可以为14*14μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第三颜色子像素的开口区域KK3的面积为180μm 2～230μm 2，开口区域KK3的形状不受限制，例如可以为：长 方形，正方形，菱形，椭圆形，圆形等；当然，还可以是其他不规则图形，例如：至少2条弧线段和1条直线段组成的封闭图形。例如：第三颜色子像素的开口区域KK3为长方形，第一边长度15μm-16μm，第一颜色子像素的开口区域KK1的第二边长度13μm-14μm。可选地，第三颜色子像素的开口区域KK3的开口面积为18*10μm 2～23*10μm 2或者20*10μm 2～22*10μm 2。可选地，第一颜色子像素的开口区域KK1的开口面积可以为15*13μm 2～16*14μm 2(长度*宽度)。例如，第三颜色子像素的开口区域KK3的面积可以为15*13μm 2(长度*宽度)。或者，第三颜色子像素的开口区域KK3的面积可以为16*13μm 2(长度*宽度)。或者，第三颜色子像素的开口区域KK3的面积可以为16*14μm 2(长度*宽度)。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第四颜色子像素的开口区域KK4的面积可以为100μm 2～230μm 2，开口区域KK4的形状不受限制，例如可以为：长方形，正方形，菱形，椭圆形，圆形等；当然，还可以是其他不规则图形，例如：至少2条弧线段和1条直线段组成的封闭图形。例如：第四颜色子像素的开口区域为椭圆形，面积可以为100μm 2～130μm 2；或者，第四颜色子像素的开口区域KK4为长方形，第一边长度12μm-13μm，第四颜色子像素的开口区域KK4的第二边长度9μm-10μm。可选地，第一颜色子像素的开口区域KK1的开口面积为13*9μm 2～12*10μm 2。例如，第四颜色子像素的开口区域KK4的面积可以为13*9μm 2(长度*宽度)，或者第四颜色子像素的开口区域KK4的面积可以为12*10μm 2(长度*宽度)。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第一辅助交叠面积S1可以为3μm 2～40μm 2。可选地，第一辅助交叠面积S1可以为6μm 2～20μm 2。例如，第一辅助交叠面积S1可以为3μm 2。或者，第一辅助交叠面积S1可以为6μm 2。或者，第一辅助交叠面积S1可以为10μm 2。或者，第一辅助交叠面积S1可以为20μm 2。或者，第一辅助交叠面积S1可以为30μm 2。当然，在实 际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第二辅助交叠面积S2可以为0～10μm 2。可选地，第二辅助交叠面积S2可以为0～5μm 2。例如，第二辅助交叠面积S2可以为0μm 2。或者，第二辅助交叠面积S2可以为5μm 2。或者，第二辅助交叠面积S2可以为10μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第三辅助交叠面积S3可以为0～6μm 2。可选地，第三辅助交叠面积S3可以为0～3μm 2。例如，第三辅助交叠面积S3可以为0μm 2。或者，第三辅助交叠面积S3可以为3μm 2。或者，第三辅助交叠面积S3可以为6μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第四辅助交叠面积S4可以为0～40μm 2。可选地，第四辅助交叠面积S4可以为0～15μm 2。例如，第四辅助交叠面积S4可以为0μm 2。或者，第四辅助交叠面积S4可以为5μm 2。或者，第四辅助交叠面积S4可以为15μm 2。或者，第四辅助交叠面积S4大致与第一辅助交叠面积S3、第二辅助交叠面积S2、第三辅助交叠面积S3中至少一个相等；或者，第四辅助交叠面积S4大于第一辅助交叠面积S3、第二辅助交叠面积S2、第三辅助交叠面积S3中至少一个相等。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6g所示，可以使第一颜色子像素中的开口区域KK1的面积大于第四颜色子像素中的开口区域KK4的面积。也可以使第一颜色子像素中的开口区域KK1的面积大致等于第四颜色子像素中的开口区域KK4的面积。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6g所示，第二导电层200可以包括电容导电部R(WD)(以辅助导电部WD为电容导电部R为例进行介绍)，第一辅助交叠面积S1可以包括第一颜色子像素中的辅助 导电部在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。第二辅助交叠面积S2可以包括第二颜色子像素中的辅助导电部在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。第三辅助交叠面积S3包括第三颜色子像素中的辅助导电部在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。第四辅助交叠面积S4包括第四颜色子像素中的辅助导电部在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。这样可以通过触控电极(例如，第二触控电极820)将辅助导电部进行遮挡，从而可以降低辅助导电部反射光，导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图5a至图5i至图9c所示，第一颜色子像素中的辅助导电部WD包括第一辅助暴露部WD1，且第一辅助暴露部WD1在衬底基板1000的正投影分别与数据线图形DA2和电源信号线图形VDD在衬底基板1000的正投影不交叠。第一辅助交叠面积S1包括第一辅助子交叠面积S11，且第一辅助暴露部WD1在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间具有第一辅助子交叠面积S11。
示例性地，第一颜色子像素中，第一辅助暴露部WD1在衬底基板1000的正投影位于数据线图形DA2和电源信号线图形VDD在衬底基板1000的正投影之间。
可选地，也可以使第一辅助暴露部WD1在衬底基板1000的正投影位于数据线图形DA2在衬底基板1000的正投影背离电源信号线图形VDD在衬底基板1000的正投影一侧。或者，也可以使第一辅助暴露部WD1在衬底基板1000的正投影位于电源信号线图形VDD在衬底基板1000的正投影背离数据线图形DA2在衬底基板1000的正投影一侧。
可以理解的是，第一辅助暴露部WD1可以包括第一辅助暴露部第一区域 WD11(未出示)，第一辅助暴露部第二区域WD12(未出示)，第一辅助暴露部第三区域WD13中的至少一个(未出示)；其中，第一辅助暴露部第一区域WD11为辅助导电部WD在衬底基板1000的正投影位于数据线图形DA2和电源信号线图形VDD在衬底基板1000的正投影之间的第一区域，第一辅助暴露部第二区域WD12为辅助导电部WD在衬底基板1000的正投影位于数据线图形DA2在衬底基板1000的正投影背离电源信号线图形VDD在衬底基板1000的正投影一侧的第二区域，第一辅助暴露部第三区域WD13为辅助导电部WD在衬底基板1000的正投影位于电源信号线图形VDD在衬底基板1000的正投影背离数据线图形DA2在衬底基板1000的正投影一侧的第三区域。
在具体实施时，在本公开实施例中，第一辅助子交叠面积S11可以为2μm 2～10μm 2。可选地，第一辅助子交叠面积S11可以为3μm 2～6μm 2。示例性地，第一辅助子交叠面积S11可以为2μm 2。或者，第一辅助子交叠面积S11可以为3μm 2。或者，第一辅助子交叠面积S11可以为5μm 2。或者，第一辅助子交叠面积S11可以为6μm 2。或者，第一辅助子交叠面积S11可以为10μm 2，在此不作限定。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第一辅助交叠面积S1与总面积Sm之间的比值范围可以为1/6～3/4。可选地，第一辅助交叠面积S1与总面积Sm之间的比值范围可以为：1/3～2/3，即1/3≤S1/Sm≤2/3。例如，可以使S1/Sm＝1/3，也可以使S1/Sm＝2/3，也可以使S1/Sm＝1/2。当然，在实际应用中，可以根据实际应用的需求设置S1/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第一辅助子交叠面积S11与总面积Sm之间的比值范围可以为：1/8～2/3。可选地，第一辅助子交叠面积S11与总面积Sm之间的比值范围可以为：1/6～1/3， 即1/6≤S11/Sm≤1/3。例如，可以使S11/Sm＝1/6，也可以使S11/Sm＝1/4，也可以使S11/Sm＝1/3。当然，在实际应用中，可以根据实际应用的需求设置S11/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图9a至图9c所示，第一颜色子像素中，也可以使触控电极(例如，第二触控电极820)在衬底基板1000的正投影覆盖第一辅助暴露部WD1在衬底基板1000的正投影。这样可以尽可能的将可能会反光的第一辅助暴露部WD1进行覆盖。
在具体实施时，在本公开实施例中，如图9b与图9c所示，第一颜色子像素中的辅助导电部WD还可以包括第一辅助遮挡部WZ1，且第一辅助遮挡部WZ1在衬底基板1000的正投影与数据线图形DA2和电源信号线图形VDD中的至少一种在衬底基板1000的正投影交叠。其中，同一辅助导电部的第一辅助遮挡部WZ1和第一辅助暴露部WD1一体设置，从而形成辅助导电部。示例性地，如图9b所示，可以使第一辅助暴露部WD1在列方向F3的宽度大致等于第一辅助遮挡部WZ1在列方向F3的宽度。这样可以降低第一颜色子像素中的辅助导电部的制备难度。如图9c所示，也可以使第一辅助暴露部WD1在列方向F3的宽度小于至少一部分第一辅助遮挡部WZ1在列方向F3的宽度。这样可以进一步遮挡第一辅助暴露部WD1。示例性地，也可以使第一辅助暴露部WD1在行方向F4的宽度小于至少一部分第一辅助遮挡部WZ1在行方向F4的宽度，这样可以使得暴露出来的辅助导电部WD面积更小，有利于减小辅助导电部WD的产生的反射光。
在具体实施时，在本公开实施例中，如图5a至图5i至图9c所示，第二颜色子像素中的辅助导电部WD包括第二辅助暴露部WD2，且第二辅助暴露部WD2在衬底基板1000的正投影分别与数据线图形DA3和电源信号线图形VDD在衬底基板1000的正投影不交叠；以及第二辅助交叠面积S2包括第二辅助子交叠面积S12，且第二辅助暴露部WD2在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间具有第二辅助子交叠面积S12。示例性地，第二颜色子像素中，第二辅助暴露部WD2 在衬底基板1000的正投影位于数据线图形DA3和电源信号线图形VDD在衬底基板1000的正投影之间。或者，第二辅助暴露部WD2在衬底基板1000的正投影位于数据线图形DA3在衬底基板1000的正投影背离电源信号线图形VDD在衬底基板1000的正投影一侧。或者，第二辅助暴露部WD2在衬底基板1000的正投影位于电源信号线图形VDD在衬底基板1000的正投影背离数据线图形DA3在衬底基板1000的正投影一侧。
在具体实施时，在本公开实施例中，第二辅助子交叠面积S12可以为0～4.5μm 2。可选地，第二辅助子交叠面积S12可以为0～2.2μm 2。例如，第二辅助子交叠面积S12可以为0μm 2。或者，第二辅助子交叠面积S12可以为1.5μm 2。或者，第二辅助子交叠面积S12可以为2.2μm 2。或者，第二辅助子交叠面积S12可以为3.5μm 2。或者，第二辅助子交叠面积S12可以为4.5μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第二颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，同一子像素中，第二辅助交叠面积S2与总面积Sm(第二颜色子像素)之间的比值范围可以为：1/20～3/4。可选地，第二辅助交叠面积S2与总面积Sm(第二颜色子像素)之间的比值范围可以为：1/10～7/20，即1/10≤S2/Sm≤7/20。例如，可以使S2/Sm＝1/10，也可以使S2/Sm＝1/5，也可以使S2/Sm＝7/20。当然，在实际应用中，可以根据实际应用的需求设置S2/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第二颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第二辅助子交叠面积S12与总面积Sm之间的比值范围可以为：1/10～1/2。第二辅助子交叠面积S12与总面积Sm之间的比值范围可以为：1/5～1/4，即1/5≤S12/Sm≤1/4。例如，可以使S12/Sm＝1/4，也可以使S12/Sm＝1/5，也可以使S12/Sm＝9/40。当然，在实际应用中，可以根据 实际应用的需求设置S12/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图9a至图9c所示，第二颜色子像素中，也可以使触控电极(例如，第二触控电极820)在衬底基板1000的正投影覆盖第二辅助暴露部WD2在衬底基板1000的正投影。这样可以尽可能的将可能会反光的第二辅助暴露部WD2进行覆盖。
在具体实施时，在本公开实施例中，如图9b与图9c所示，第二颜色子像素中的辅助导电部WD还可以包括第二辅助遮挡部WZ2。且第二辅助遮挡部WZ2在衬底基板1000的正投影与数据线图形和电源信号线图形VDD中的至少一种在衬底基板1000的正投影交叠。其中，同一辅助导电部的第二辅助遮挡部WZ2和第二辅助暴露部WD2一体设置，从而形成辅助导电部。示例性地，如图9b所示，可以使第二辅助暴露部WD2在列方向F3的宽度大致等于第二辅助遮挡部WZ2在列方向F3的宽度。这样可以降低第二颜色子像素中的辅助导电部的制备难度。如图9c所示，也可以使第二辅助暴露部WD2在列方向F3的宽度小于至少一部分第二辅助遮挡部WZ2在列方向F3的宽度。这样可以进一步遮挡第二辅助暴露部WD2。示例性地，第二辅助暴露部WD2在行方向F4的宽度小于至少一部分第二辅助遮挡部WZ2在行方向F4的宽度。
在具体实施时，在本公开实施例中，如图5a至图5i至图6g所示，第三颜色子像素中的辅助导电部WD包括第三辅助暴露部WD3，且第三辅助暴露部WD3在衬底基板1000的正投影分别与数据线图形DA1和电源信号线图形VDD在衬底基板1000的正投影不交叠；以及第三辅助交叠面积S3包括第三辅助子交叠面积S13，且第三辅助暴露部WD3在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间具有第三辅助子交叠面积S13。示例性地，第三颜色子像素中，第三辅助暴露部WD3在衬底基板1000的正投影位于数据线图形DA1和电源信号线图形VDD在衬底基板1000的正投影之间。
在具体实施时，在本公开实施例中，第三辅助子交叠面积S13可以为0～2.5μm 2。可选地，第三辅助子交叠面积S13可以为0～1.2μm 2。例如，第三辅助 子交叠面积S13可以为0μm 2。或者，第三辅助子交叠面积S13可以为0.5μm 2。或者，第三辅助子交叠面积S13可以为1.0μm 2。或者，第三辅助子交叠面积S13可以为1.2μm 2。或者，第三辅助子交叠面积S13可以为2.5μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，具体在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第三颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第三辅助交叠面积S3与总面积Sm之间的比值范围可以为：0～1/2；可选地，第三辅助交叠面积S3与总面积Sm之间的比值范围可以为：0～1/4，即0≤S3/Sm≤1/4。例如，可以使S3/Sm＝0，也可以使S3/Sm＝1/16，也可以使S3/Sm＝1/4。当然，在实际应用中，可以根据实际应用的需求设置S3/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第三颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第三辅助子交叠面积S13与总面积Sm之间的比值范围可以为：0～1/8；可选地，第三辅助子交叠面积S13与总面积Sm之间的比值范围可以为：0～1/16，即0≤S13/Sm≤1/16。例如，可以使S13/Sm＝0，也可以使S13/Sm＝1/16，也可以使S13/Sm＝1/32。当然，在实际应用中，可以根据实际应用的需求设置S13/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图9a至图9c所示，第三颜色子像素中，也可以使触控电极(例如，第二触控电极820)在衬底基板1000的正投影覆盖第三辅助暴露部WD3在衬底基板1000的正投影。这样可以尽可能的将可能会反光的第三辅助暴露部WD3进行覆盖。
在具体实施时，在本公开实施例中，如图9b与图9c所示，第三颜色子像素中的辅助导电部WD还可以包括第三辅助遮挡部WZ3。且第三辅助遮挡部WZ3在衬底基板1000的正投影与数据线图形和电源信号线图形VDD中的至少一种在衬底基板1000的正投影交叠。其中，同一辅助导电部的第三辅助 遮挡部WZ3和第三辅助暴露部WD3一体设置，从而形成辅助导电部。示例性地，如图9b所示，可以使第三辅助暴露部WD3在列方向F3的宽度大致等于第三辅助遮挡部WZ3在列方向F3的宽度。这样可以降低第三颜色子像素中的辅助导电部的制备难度。如图9c所示，也可以使第三辅助暴露部WD3在列方向F3的宽度小于至少一部分第三辅助遮挡部WZ3在列方向F3的宽度。这样可以进一步遮挡第三辅助暴露部WD3。示例性地，第三辅助暴露部WD3在行方向F4的宽度小于至少一部分第三辅助遮挡部WZ3在行方向F4的宽度。
在具体实施时，在本公开实施例中，如图5a至图5i至图6g所示，第四颜色子像素中的辅助导电部WD包括第四辅助暴露部WD4，且第四辅助暴露部WD4在衬底基板1000的正投影分别与数据线图形DA4和电源信号线图形VDD在衬底基板1000的正投影不交叠。以及第四辅助交叠面积S4包括第四辅助子交叠面积S14，且第四辅助暴露部WD4在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间具有第四辅助子交叠面积S14。示例性地，第四颜色子像素中，第四辅助暴露部WD4在衬底基板1000的正投影位于数据线图形DA4和电源信号线图形VDD在衬底基板1000的正投影之间。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第四颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第四辅助交叠面积S4与总面积Sm之间的比值范围可以为：1/6～5/6，即1/6≤S4/Sm≤5/6。例如，可以使S4/Sm＝1/6，也可以使S4/Sm＝2/3，也可以使S4/Sm＝5/6。当然，在实际应用中，可以根据实际应用的需求设置S4/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，同一子像素中，例如：第四颜色子像素，辅助导电部WD在衬底基板1000的正投影具有总面积Sm。其中，第四辅助子交叠面积S14与总面积Sm之间的比值范围可以为：1/3～2/3，即1/3≤S14/Sm≤2/3。例如，可以使S14/Sm＝1/3，也可以使S14/Sm＝2/3，也可以使S14/Sm＝1/2。当然，在实际应用中，可以根据 实际应用的需求设置S14/Sm的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，第四辅助子交叠面积S14可以为2μm 2～10μm 2。可选地，第四辅助子交叠面积S14可以为3μm 2～6μm 2。示例性地，第四辅助子交叠面积S14可以为2μm 2。或者，第四辅助子交叠面积S14可以为3μm 2。或者，第四辅助子交叠面积S14可以为5μm 2。或者，第四辅助子交叠面积S14可以为6μm 2。或者，第四辅助子交叠面积S14可以为10μm 2，在此不作限定。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图9a至图9c所示，第四颜色子像素中，也可以使触控电极(例如，第二触控电极820)在衬底基板1000的正投影覆盖第四辅助暴露部WD4在衬底基板1000的正投影。这样可以尽可能的将可能会反光的第四辅助暴露部WD4进行覆盖。
在具体实施时，在本公开实施例中，如图9b与图9c所示，第四颜色子像素中的辅助导电部还可以包括第四辅助遮挡部WZ4。且第四辅助遮挡部WZ4在衬底基板1000的正投影与数据线图形和电源信号线图形VDD中的至少一种在衬底基板1000的正投影交叠。其中，同一辅助导电部的第四辅助遮挡部WZ4和第四辅助暴露部WD4一体设置，从而形成辅助导电部。示例性地，如图9b所示，可以使第四辅助暴露部WD4在列方向F3的宽度大致等于第四辅助遮挡部WZ4在列方向F3的宽度。这样可以降低第四颜色子像素中的辅助导电部的制备难度。如图9c所示，也可以使第四辅助暴露部WD4在列方向F3的宽度小于至少一部分第四辅助遮挡部WZ4在列方向F3的宽度。这样可以进一步遮挡第四辅助暴露部WD4。示例性地，第四辅助暴露部WD4在行方向F4的宽度小于至少一部分第四辅助遮挡部WZ4在行方向F4的宽度。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第一辅助子交叠面积S11大于第二辅助子交叠面积S12。这样可以使第一颜色子像素相比第二颜色子像素，通过触控电极(例如，第二触控电极820)遮挡的第一颜色子像素中的辅助导电部较多，从而可以降低第一辅助暴露部 WD1反射光，导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第一辅助子交叠面积S11大于第三辅助子交叠面积S13。这样可以使第一颜色子像素相比第三颜色子像素，通过触控电极(例如，第二触控电极820)遮挡的第一颜色子像素中的辅助导电部较多，从而可以降低第一辅助暴露部WD1反射光，导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第四辅助子交叠面积S14大于第二辅助子交叠面积S12。这样可以使第四颜色子像素相比第二颜色子像素，通过触控电极(例如，第二触控电极820)遮挡的第四颜色子像素中的辅助导电部较多，从而可以降低第四辅助暴露部WD4反射光，导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第四辅助子交叠面积S14大于第三辅助子交叠面积S13。这样可以使第四颜色子像素相比第三颜色子像素，通过触控电极(例如，第二触控电极820)遮挡的第四颜色子像素中的辅助导电部较多，从而可以降低第四辅助暴露部WD4反射光，导致的发光干扰和混光效果差的问题。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第二辅助子交叠面积S12大于第三辅助子交叠面积S13，以使第一辅助子交叠面积S11大于第二辅助子交叠面积S12，第二辅助子交叠面积S12大于第三辅助子交叠面积S13。这样可以使触控电极(例如，第二触控电极820)遮挡的第一辅助暴露部WD1、第二辅助暴露部WD2以及第三辅助暴露部WD3的面积依次增加，从而可以进一步降低第一辅助暴露部WD1、第二辅助暴露部WD2以及第三辅助暴露部WD3反射光，导致的发光干扰和混光效果差的问题。当然，也可以是第二辅助子交叠面积S12大致等于第三辅助子交叠面积S13，例如：第二辅助子交叠面积S12等于第三辅助子交叠面积S13，均等于0；或者，第四辅助子交叠面积S14至少与第一辅助子交叠面积S11、第二辅助子交叠面积S12、第三辅助子交叠面积S13中的一个相等；或者，第四辅助 子交叠面积S14大于第一辅助子交叠面积S11、第二辅助子交叠面积S12、第三辅助子交叠面积S13中的至少一个。
在具体实施时，在本公开实施例中，如图5a至图5i至图6d所示，可以使第四辅助子交叠面积S14大于第一辅助子交叠面积S11。这样可以使触控电极(例如，第二触控电极820)遮挡的第四辅助暴露部WD4大于第一辅助暴露部WD1，从而可以进一步降低第四辅助暴露部WD4反射光，导致的发光干扰和混光效果差的问题。当然，也可以是第四辅助子交叠面积S14大致等于第一辅助子交叠面积S11。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，第一颜色子像素中的第一电容(例如：以第一电容的第二极板Cst2为例)在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第一存储交叠面积SC1。示例性地，第一存储交叠面积SC1包括第一颜色子像素中的存储导电部Cst2在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。
示例性地，如图5a至图5i至图7f以及图10a、图10b所示，触控电极在至少一个子像素中形成的网格结构包括至少5个内角，其中至少有2个钝角和2个锐角。例如：5～10个内角，其中至少有2个钝角和2个锐角。
可选地，触控电极在至少一个子像素中形成的网格结构至少有4个内角角度不相等。例如：第一颜色子像素中，第二触控电极820形成A1～A5个内角，其中A1等于90°，A2和A5为锐角，角度30°-80°；A3和A4为连续的钝角，角度为95°～150°。
当然，不局限上述情况。例如，可选地，A2和A5为相等的锐角，A3和A4相等的钝角。或者，形成网格的内角均相等，例如：形成正五边形，或六边形。
示例性地，如图5a至图5i至图7f以及图10a、图10b所示，触控电极在至少一个子像素中形成的网格结构包括至少5条边，其中至少有2条边长度 不相等。例如：第一颜色子像素中，第二触控电极820形成A1～A5个内角的5条边。例如：a1～a5长度均不相等。
示例性地，如图5a至图5i至图7f以及图10a、图10b所示，触控电极在至少一个子像素中形成的结构包括至少4条边，其中至少有2条边宽度不相等。可选地，触控电极在至少对应一个子像素中的多条边中，至少有一条边的宽度逐渐变小。例如：a4边，从A4角的起始端到A5角方向的末端，宽度变小。可选地，触控电极在对应一个子像素中的多条边中，至少有一条边的包括宽度不相等的三个部分。例如：如图9b所示，触控电极的一条边包括至少3个宽度不相等3个部分，DC1大于DC2，DC1大于DC4。其中，DC4宽度较小，可以减小与电源信号线交叠，减小对触控信号的影响。
当然，不局限上述情况。例如，可选地，触控电极可以形成边长相等或宽度相等多边形结构。例如：正五边形，正六边形。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，第二颜色子像素中的第一电容在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第二存储交叠面积SC2。示例性地，第二存储交叠面积SC2包括第二颜色子像素中的存储导电部Cst2在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，第三颜色子像素中的第一电容在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第三存储交叠面积SC3。示例性地，第三存储交叠面积SC3包括第三颜色子像素中的存储导电部Cst2在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，第四颜色子像素中的第一电容在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影具有第四存储交 叠面积SC4。示例性地，第四存储交叠面积SC4包括第四颜色子像素中的存储导电部Cst2在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠面积。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，可以使第一存储交叠面积SC1、第二存储交叠面积SC2以及第四存储交叠面积SC4中的至少一个大于第三存储交叠面积SC3。例如，可以使第一存储交叠面积SC1、第二存储交叠面积SC2以及第四存储交叠面积SC4均大于第三存储交叠面积SC3；或者，第一存储交叠面积SC1或第四存储交叠面积SC4至少之一大于第二存储交叠面积SC2，第二存储交叠面积SC2等于第三存储交叠面积SC3。
在具体实施时，在本公开实施例中，如图5a至图5i至图7f以及图10a、图10b所示，可以使第一存储交叠面积SC1大于第二存储交叠面积SC2。这样可以使第一颜色子像素中的第一电容尽可能被触控电极(例如，第二触控电极820)进行遮挡。
在具体实施时，在本公开实施例中，如图5a至图5i至图9b所示，触控电极(例如，第二触控电极820)包括第一电极部DC1和第二电极部DC2；其中，第一电极部DC1在衬底基板1000的正投影与辅助导电部在衬底基板1000的正投影具有交叠区域，第二电极部DC2在衬底基板1000的正投影与辅助导电部在衬底基板1000的正投影不交叠。其中，可以使第一电极部DC1的宽度大于第二电极部DC2的宽度。这样可以使触控电极更好的遮挡辅助导电部。
可选地，如图5a至图5i至图9b所示，触控电极(例如，第二触控电极820)包括至少3个宽度不同的部分，触控电极包括第一电极部DC1和第二电极部DC2和第三电极部DC3(未示出)；例如：第一电极部DC1在衬底基板1000的正投影与辅助导电部在衬底基板1000的正投影具有交叠区域，第二电极部DC2在衬底基板1000的正投影与辅助导电部在衬底基板1000的正投影不交叠，第三电极部DC3在衬底基板1000的正投影与存储导电部在衬底基板1000 的正投影具有交叠区域。可选地，第一电极部DC1的宽度小于第二电极部DC2的宽度，第二电极部DC2的宽度小于第三电极部DC3的宽度。
可选地，如图5a至图5i至图9b所示，触控电极至少在对应的一个子像素区有凸出部；例如：DC1。触控电极在至少对应的两个子像素区有凸出部，且凸出部的凸出方向不同或者凸出部的宽度不同。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f以及图6g所示，位于相邻开口区域之间的触控电极(例如，第二触控电极820)在衬底基板1000的正投影与至少两种不同颜色的发光层在衬底基板1000的正投影交叠。可选地，位于相邻开口区域之间的触控电极(例如，第二触控电极820)在衬底基板1000的正投影被至少两种不同颜色的发光层在衬底基板1000的正投影覆盖。
示例性地，可以使位于相邻开口区域之间的触控电极(例如，第二触控电极820)在衬底基板1000的正投影被两种不同颜色的发光层在衬底基板1000的正投影覆盖。也可以使位于相邻开口区域之间的触控电极(例如，第二触控电极820)在衬底基板1000的正投影被三种不同颜色的发光层在衬底基板1000的正投影覆盖。
示例性地，在同一子像素中，触控电极(例如820)与存储导电部WCst2存在交叠区域(例如SC1)，触控电极(例如820)被至少三种不同颜色的发光层在衬底基板1000的正投影交叠，存储导电部WCst2在衬底基板1000的正投影的面积为Sn，其中，SC1/Sn大致为1/5～4/5。
可选地，同一子像素中，被至少三种不同颜色的发光层在衬底基板1000的正投影覆盖的触控电极的面积与对应存储导电部WCst2在衬底基板1000的正投影的面积之比大致为3/10～2/5。例如，被至少三种不同颜色的发光层在衬底基板1000的正投影覆盖的触控电极的面积与对应存储导电部WCst2在衬底基板1000的正投影的面积之比大致为1/5。或者，被至少三种不同颜色的发光层在衬底基板1000的正投影覆盖的触控电极的面积与对应存储导电部WCst2在衬底基板1000的正投影的面积之比大致为3/10。或者，被至少三种 不同颜色的发光层在衬底基板1000的正投影覆盖的触控电极的面积与对应存储导电部WCst2在衬底基板1000的正投影的面积之比大致为2/5。或者，被至少三种不同颜色的发光层在衬底基板1000的正投影覆盖的触控电极的面积与对应存储导电部WCst2在衬底基板1000的正投影的面积之比大致为1/2。当然，在实际应用中，可以根据实际应用环境的需求进行设计，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，可以使围绕于第一颜色子像素中的开口区域KK1的触控电极(例如，第二触控电极820)在衬底基板1000的正投影位于第一颜色发光层610在衬底基板1000的正投影内。这样一方面可以提高第一颜色发光层610的面积保证发光效果。
可选地，通过使第一颜色发光层610的边界ES1中的至少部分覆盖辅助导电部，进一步对辅助导电部进行遮挡。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，可以使围绕于第二颜色子像素中的开口区域KK2的触控电极(例如，第二触控电极820)在衬底基板1000的正投影位于第二颜色发光层620在衬底基板1000的正投影内。这样可以提高第二颜色发光层620的面积保证发光效果。
可选地，通过使第二颜色发光层620的边界ES2中的至少部分覆盖辅助导电部，进一步对辅助导电部进行遮挡。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，可以使围绕于第三颜色子像素中的开口区域KK3的触控电极(例如，第二触控电极820)在衬底基板1000的正投影位于第三颜色发光层630在衬底基板1000的正投影内。这样可以提高第三颜色发光层630的面积保证发光效果。
可选地，通过使第三颜色发光层630的边界ES3中的至少部分覆盖辅助导电部，进一步对辅助导电部进行遮挡。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，可以使围绕于第四颜色子像素中的开口区域KK4的触控电极(例如，第二触控电极820)在衬底基板1000的正投影位于第四颜色发光层640在衬底基板1000的正投影内。这样可以提高第四颜色发光层640的面积保证发光效果。
可选地，通过使第四颜色发光层640的边界ES4中的至少部分覆盖辅助导电部，进一步对辅助导电部进行遮挡。
可以理解的是，在有至少两种颜色发光层交叠的区域，发光层的层叠位置不局限本实施例列举情况，可以根据实际情况或工艺条件进行调整，例如：不同的颜色发光层同步骤制作或者不同步骤制作。例如：发光层的层叠位置并不局限于图5e中，从像素界定层950依次往上，顺序是610，620，630，当然也可以是从像素界定层950依次往上，顺序是630，620，610或者610，630，620，或者630，610，620等。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，针对相邻的第三颜色发光层630和第二颜色发光层620，第三颜色发光层630在衬底基板1000的正投影的边界ES3与围绕该第三颜色子像素的触控电极(例如，第二触控电极820)在衬底基板1000的正投影的边界CK3之间具有第一最小距离W0S1，第二颜色发光层620在衬底基板1000的正投影的边界ES2与围绕该第二颜色子像素的触控电极(例如，第二触控电极820)在衬底基板1000的正投影的边界CK1之间具有第二最小距离W0S2。其中，第一最小距离W0S1大于第二最小距离W0S2。这样一方面可以进一步提高第三颜色发光层630的面积保证发光效果。另一方面，通过使第三颜色发光层630的边界ES3中的至少部分覆盖辅助导电部，进一步对辅助导电部进行遮挡。并且，由于第二颜色子像素的发光面积较小，因此在第三颜色发光层630延伸到第二颜色发光层620中时，对第二颜色子像素的发光效果的影响较小。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，围绕于第一颜色子像素中的开口区域KK1的触控电极(例如， 第二触控电极820)在衬底基板1000的正投影所围成的面积为第一网格面积WG1。围绕于第二颜色子像素中的开口区域KK2的触控电极(例如，第二触控电极820)在衬底基板1000的正投影所围成的面积为第二网格面积WG2。围绕于第三颜色子像素中的开口区域KK3的触控电极(例如，第二触控电极820)在衬底基板1000的正投影所围成的面积为第三网格面积WG3。其中，第三网格面积WG3大于第二网格面积WG2大于第一网格面积WG1。这样可以使第三网格面积WG3、第二网格面积WG2以及第一网格面积WG1分别与第三颜色子像素中的开口区域KK3、第二颜色子像素中的开口区域KK2以及第一颜色子像素中的开口区域KK1成正比，从而可以提高透光率。
可以理解的是，本公开实施例中第一触控电极810和/或第二触控电极并不要求全部均为封闭的网格状，局部地区或个别子像素对应的触控电极可以有缺口或断开。例如：结合图1-图2，以及图5a至图5i、图6f、图6g-图11所示：在靠近非显示区的显示区AA边缘，或者在非显示区，或者个别子像素对应的触控电极有缺口或断开。
在具体实施时，在本公开实施例中，如图5a至图5i、图6f、图6g以及图11所示，围绕于第四颜色子像素中的开口区域KK4的触控电极(例如，第二触控电极820)在衬底基板1000的正投影所围成的面积为第四网格面积WG4。可以使第一颜色子像素对应的第一网格面积WG1大于第四颜色子像素对应的第四网格面积WG4。或者，也可以使第一颜色子像素对应的第一网格面积WG1大致等于第四颜色子像素对应的第四网格面积WG4，在此不作限定。
在具体实施时，在本公开实施例中，第一网格面积WG1可以为850～920μm 2。可选地，第一网格面积WG1可以为860μm 2～910μm 2。例如，第一网格面积WG1可以为850μm 2。或者，第一网格面积WG1可以为860μm 2。或者，第一网格面积WG1可以为900μm 2。或者，第一网格面积WG1可以为910μm 2。或者，第一网格面积WG1可以为920μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
或者，在具体实施时，在本公开实施例中，第一网格面积WG1也可以为30.5*28.5μm 2～35.5*30.5μm 2。可选地，第一网格面积WG1可以为30.5*28.5μm 2。例如，第一网格面积WG1可以为31.5*29.5μm 2。或者，第一网格面积WG1可以为32.5*29.1μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第二网格面积WG2可以为950～1050μm 2。可选地，第二网格面积WG2可以为960～1040μm 2。例如，第二网格面积WG2可以为950μm 2。或者，第二网格面积WG2可以为960μm 2。或者，第二网格面积WG2可以为980μm 2。或者，第二网格面积WG2可以为1000μm 2。或者，第二网格面积WG2可以为1040μm 2。或者，第二网格面积WG2可以为1050μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
或者，在具体实施时，在本公开实施例中，第二网格面积WG2可以为30.1*30.1μm 2～32.1*32.1μm 2。可选地，第二网格面积WG2可以为30.5*30.5μm 2～32.0*32.0μm 2。例如，第二网格面积WG2可以为30.1*30.1μm 2。或者，第二网格面积WG2可以为30.5*30.5μm 2。或者，第二网格面积WG2可以为31.6*31.6μm 2。或者，第二网格面积WG2可以为32.0*32.0μm 2。或者，第二网格面积WG2可以为32.1*32.1μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第三网格面积WG3可以为1100μm 2～1300μm 2。可选地，第三网格面积WG3可以为1150μm 2～1250μm 2。例如，第三网格面积WG3可以为1100μm 2。或者，第三网格面积WG3可以为1150μm 2。或者，第三网格面积WG3可以为1200μm 2。或者，第三网格面积WG3可以为1225μm 2。或者，第三网格面积WG3可以为1300μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
或者，在具体实施时，在本公开实施例中，第三网格面积WG3可以为 32*32μm 2～37*37μm 2。可选地，第三网格面积WG3可以为33*33μm 2～36*36μm 2。例如，第三网格面积WG3可以为32*32μm 2。或者，第三网格面积WG3可以为33*33μm 2。或者，第三网格面积WG3可以为34*34μm 2.。或者，第三网格面积WG3可以为35*35μm 2。或者，第三网格面积WG3可以为36*36μm 2。或者，第三网格面积WG3可以为37*37μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第四网格面积WG4可以为850～920μm 2。可选地，第四网格面积WG4可以为860μm 2～910μm 2。例如，第四网格面积WG4可以为850μm 2。或者，第四网格面积WG4可以为860μm 2。或者，第四网格面积WG4可以为900μm 2。或者，第四网格面积WG4可以为910μm 2。或者，第四网格面积WG4可以为920μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
或者，在具体实施时，在本公开实施例中，第四网格面积WG4也可以为30.5*28.5μm 2～35.5*30.5μm 2。可选地，第四网格面积WG4可以为30.5*28.5μm 2。例如，第四网格面积WG4可以为31.5*29.5μm 2。或者，第四网格面积WG4可以为32.5*29.1μm 2。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i与图11所示，同一重复单元中，第三颜色子像素中的开口区域KK3和第一颜色子像素中的开口区域KK1可以沿第一方向F1排列。第二颜色子像素中的开口区域KK2和第四颜色子像素中的开口区域KK4也可以沿第一方向F1排列。其中，围绕于第三颜色子像素中的开口区域KK3的触控电极(例如，第二触控电极820)的内边界NS3所围成的区域在垂直于第一方向F1上具有第一宽度WK1。围绕于第一颜色子像素中的开口区域KK1的触控电极(例如，第二触控电极820)的内边界NS1所围成的区域在垂直于第一方向F1上具有第二宽度WK2。围绕于第二颜色子像素中的开口区域KK2的触控电极(例如，第二触控电极820)的内边界NS2所围成的区域在垂直于第一方向F1上具有第三宽度WK3。围 绕于第四颜色子像素中的开口区域KK4的触控电极(例如，第二触控电极820)的内边界NS4所围成的区域在垂直于第一方向F1上具有第四宽度WK4。
可选地，第一方向F1与行方向F3方向可以形成一定角度，例如，该角度可以大于0度且小于90度。可选地，第一方向F1与行方向F3方向可以形成25～75度。可选地，第一方向F1与行方向F3方向可以形成30～60度。例如，第一方向F1与行方向F3方向可以形成25度。或者，第一方向F1与行方向F3方向可以形成30度。或者，第一方向F1与行方向F3方向可以形成45度。或者，第一方向F1与行方向F3方向可以形成60度。或者，第一方向F1与行方向F3方向可以形成75度。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第一宽度WK1可以为34.0μm～35.0μm。可选地，第一宽度WK1可以为34.1μm～34.9μm。例如，第一宽度WK1可以为34.0μm。或者，第一宽度WK1可以为34.1μm。或者，第一宽度WK1可以为34.4μm。或者，第一宽度WK1可以为34.8μm。或者，第一宽度WK1可以为34.9μm。或者，第一宽度WK1可以为35.0μm。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第二宽度WK2可以为30.5μm～31.5μm。可选地，第二宽度WK2可以为30.7μm～31.4μm。例如，第二宽度WK2可以为30.5μm。或者，第二宽度WK2可以为30.7μm。或者，第二宽度WK2可以为31.2μm。或者，第二宽度WK2可以为31.4μm。或者，第二宽度WK2可以为31.5μm。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第三宽度WK3可以为30.8μm～32.5μm。可选地，第三宽度WK3可以为31.0μm～32.0μm。例如，第三宽度WK3可以为30.8μm。或者，第三宽度WK3可以为31.0μm。或者，第三宽度WK3可以为31.6μm。第三宽度WK3可以为31.8μm。或者，第三宽度WK3可以为32.0μm。或者，第三宽度WK3可以为32.5μm。当然，在实际 应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，第四宽度WK4可以为28.8～31.5μm。可选地，第四宽度WK4可以为29.2μm～30.5μm。例如，第四宽度WK4可以为28.8μm。或者，第四宽度WK4可以为29.2μm。或者，第四宽度WK4可以为29.9μm。或者，第四宽度WK4可以为30.5μm。或者，第四宽度WK4可以为31.5μm。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，如图11所示，可以使第一宽度WK1大于第二宽度WK2。这样可以使保证第三颜色子像素中的开口区域KK3和第一颜色子像素中的开口区域KK1，提高透光率。示例性地，第一宽度WK1与第二宽度WK2之间的差值可以为3.0μm～4.0μm。可选地，第一宽度WK1与第二宽度WK2之间的差值可以为3.1μm～3.9μm。例如，第一宽度WK1与第二宽度WK2之间的差值可以为3.0μm。或者，第一宽度WK1与第二宽度WK2之间的差值可以为3.3μm。或者，第一宽度WK1与第二宽度WK2之间的差值可以为3.6μm。或者，第一宽度WK1与第二宽度WK2之间的差值可以为3.8μm。或者，第一宽度WK1与第二宽度WK2之间的差值可以为3.9μm。或者，第一宽度WK1与第二宽度WK2之间的差值可以为4.0μm。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，如图11所示，可以使第三宽度WK3大于第四宽度WK4。这样可以使保证第二颜色子像素中的开口区域KK2和第四颜色子像素中的开口区域KK4，提高透光率。示例性地，第三宽度WK3与第四宽度WK4之间的差值可以为1.0μm～2.0μm。可选地，第三宽度WK3与第四宽度WK4之间的差值可以为1.2μm～1.8μm。例如，第三宽度WK3与第四宽度WK4之间的差值可以为1.0μm。或者，第三宽度WK3与第四宽度WK4之间的差值可以为1.2μm。或者，第三宽度WK3与第四宽度WK4之间的差值可以为1.5μm。或者，第三宽度WK3与第四宽度WK4之间的差值可以为1.7μm。或者，第三宽度WK3与第四宽度WK4之间的差值可以为1.8μm。或者，第三 宽度WK3与第四宽度WK4之间的差值可以为2.0μm。当然，在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i与图12所示，与辅助导电部的正投影具有交叠面积的触控电极(例如，第二触控电极820)的网格线的延伸方向F0与第三方向具有夹角β；且15°≤β≤60°；可选地，夹角β为20°≤β≤50°。其中，第三方向与数据线图形的延伸方向大致垂直，例如第三方向可以为行方向F4。示例性地，可以使tanβ＝A1/A2；其中，A1代表辅助导电部在垂直于第三方向上的宽度，A2代表辅助导电部在第三方向上的宽度。例如，可以使β＝15°，也可以使β＝25°，也可以使β＝35°，也可以使β＝45°，也可以使β＝50°，也可以使β＝60°。当然，在实际应用中，可以根据实际应用的需求确定β的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图5a至图5i与图12所示，与第一颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极(例如，第二触控电极820)的网格线的延伸方向与第三方向具有第一夹角β1。与第二颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极(例如，第二触控电极820)的网格线的延伸方向与第三方向具有第二夹角β2。与第三颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极(例如，第二触控电极820)的网格线的延伸方向与第三方向具有第三夹角β3。其中，可以使第一夹角小于第二夹角小于第三夹角，从而可以尽可能使触控电极(例如，第二触控电极820)覆盖辅助导电层。当然，根据实际情况，也可以是β1，β2，β3其中至少两个角度相同。
在具体实施时，在本公开实施例中，如图5a至图5i、图9a、图10a所示，以相邻的四个子像素的开口区域为一个开口组，触控电极(例如，第二触控电极820)的网格交叉点在衬底基板1000的正投影位于开口组在衬底基板1000的正投影所围成的区域中。进一步地，触控电极(例如，第二触控电极820)的网格交叉点在衬底基板1000的正投影大致位于开口组在衬底基板1000的正投影所围成的区域的中心处。这样可以使网格交叉点均匀分散在显示区 中，进一步提高显示均一性。
在具体实施时，在本公开实施例中，如图13a与图13b所示，第一颜色子像素中的第一电极510(例如：阳极)在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠区域具有第一阳极交叠面积BS1；第二颜色子像素中的第一电极520在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠区域具有第二阳极交叠面积BS2；第三颜色子像素中的第一电极530在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠区域具有第三阳极交叠面积BS3；第四颜色子像素中的第一电极540在衬底基板1000的正投影与触控电极(例如，第二触控电极820)在衬底基板1000的正投影之间的交叠区域具有第四阳极交叠面积BS4。其中，第一阳极交叠面积BS1、第二阳极交叠面积BS2以及第四阳极交叠面积BS4中的至少一个大于第三阳极交叠面积BS3。
示例性地，可以使第一阳极交叠面积BS1大于第三阳极交叠面积BS3。也可以使第二阳极交叠面积BS2大于第三阳极交叠面积BS3。也可以使第四阳极交叠面积BS4大于第三阳极交叠面积BS3。
在具体实施时，在本公开实施例中，如图13a与图13b所示，可以使第一阳极交叠面积BS1大于第二阳极交叠面积BS2。或者，也可以使第一阳极交叠面积BS1大致等于第二阳极交叠面积BS2。
在具体实施时，在本公开实施例中，如图13a与图13b所示，第一阳极交叠面积BS1大于第四阳极交叠面积BS4。或者，也可以使第一阳极交叠面积BS1大致等于第四阳极交叠面积BS4。
在具体实施时，在本公开实施例中，如图13a与图13b所示，第四阳极交叠面积BS4大于第二阳极交叠面积BS2。或者，也可以使第四阳极交叠面积BS4大致等于第二阳极交叠面积BS2。
可选地，第一阳极交叠面积BS1为2.5μm 2-35μm 2。可选地，第一阳极交叠面积BS1为3μm 2-25μm 2。或者，也可以使第一阳极交叠面积BS1为6 μm 2-20μm 2。
可选地，第二阳极交叠面积BS2为0μm 2-30μm 2。可选地，第二阳极交叠面积BS2为1.5μm 2-25μm 2。或者，也可以使第二阳极交叠面积BS2为6μm 2-20μm 2。
可选地，第三阳极交叠面积BS3为0μm 2-25μm 2。可选地，第三阳极交叠面积BS3为1.5μm 2-25μm 2。或者，也可以使第三阳极交叠面积BS3为5μm 2-20μm 2。
可选地，第四阳极交叠面积BS4为0μm 2-30μm 2。可选地，第四阳极交叠面积BS4为1.5μm 2-25μm 2。或者，也可以使第一阳极交叠面积BS4为6μm 2-20μm 2。
在具体实施时，在本公开实施例中，如图14a与图14b所示，结合图8a-图8d，在第二触控电极820背离衬底基板1000一侧还可以设置辅助绝缘层。在辅助绝缘层背离衬底基板1000的一侧还可以设置辅助电极840。示例性地，辅助电极840处于浮接状态，不进行传输信号。当然，辅助电极840可以与第一触控电极810同层制作和/或相同材料形成。
可以理解的是，如图14a与图14b所示以及结合图8a-图8d，在第一触控电极810背离衬底基板1000一侧设置绝缘层830。在830背离衬底基板1000的一侧还可以设置辅助电极840，辅助电极840处于浮接状态，不进行传输信号，辅助电极840可以与第二触控电极820(或者811)同层制作和/或相同材料形成。
在具体实施时，在本公开实施例中，如图15所示，显示面板还包括位于非显示区中的电源输入线VDDIN。显示区中的电源信号线图形VDD与电源输入线VDDIN电连接。示例性地，相邻两列子像素的电源信号线图形VDD通过电源输入线VDDIN电性连接；或者，颜色相同的相邻两列子像素对应的电源信号线图形VDD通过电源输入线VDDIN电性连接。示例性地，电源输入线VDDIN可以与电源信号线图形VDD同层设置。或者，电源输入线VDDIN也可以与电源信号线图形VDD异层设置，这样还需要使电源信号线图形VDD 和电源输入线VDDIN通过过孔电连接。并且，数据线图形DA和电源输入线VDDIN也可以不设置于同一导电层。
可以理解的是，以上各公开的实施例之间可以根据需要进行适应性组合，各数值范围可以进行相应调整。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板,例如：一种有机发光二极管(Organic Light Emitting Diode，OLED)。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表、手环等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的部件，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (43)

  1. 一种显示面板，其中，包括：
    衬底基板；
    晶体管阵列层，位于所述衬底基板上；
    像素限定层，位于所述晶体管阵列层背离所述衬底基板一侧；
    触控电极，位于所述像素限定层背离所述衬底基板一侧；
    所述衬底基板具有显示区，所述显示区包括多个子像素；所述子像素包括像素电路和发光元件；所述像素电路包括栅线图形、数据线图形、电源信号线图形；
    所述晶体管阵列层包括多个电容导电部，所述子像素包括对应的所述电容导电部；其中，同一所述子像素中，所述电容导电部与所述子像素对应的数据线图形和/或所述子像素对应的电源信号线图形存在交叠区域；所述电容导电部至少耦接所述子像素对应的电源信号线图形或所述子像素对应的数据线图形；
    所述像素限定层包括多个开口区域，所述子像素包括对应的所述开口区域；
    至少部分所述触控电极在所述衬底基板的正投影为网格；
    其中，所述多个子像素还包括第一颜色子像素、第二颜色子像素以及第三颜色子像素；所述第一颜色子像素的开口区域的面积小于所述第三颜色子像素的开口区域的面积，且所述第二颜色子像素的开口区域的面积小于所述第三颜色子像素的开口区域的面积；
    所述第一颜色子像素中的电容导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第一辅助交叠面积；
    所述第二颜色子像素中的电容导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第二辅助交叠面积；
    所述第三颜色子像素中的电容导电部在所述衬底基板的正投影与所述触 控电极在所述衬底基板的正投影具有第三辅助交叠面积；
    所述第一辅助交叠面积和所述第二辅助交叠面积中的至少一个大于所述第三辅助交叠面积。
  2. 如权利要求1所述的显示面板，其中，所述第一辅助交叠面积大于所述第二辅助交叠面积；或者，
    所述第一辅助交叠面积大致等于所述第二辅助交叠面积；或者，
    所述第三辅助交叠面积大致等于所述第二辅助交叠面积。
  3. 如权利要求1所述的显示面板，其中，所述晶体管阵列层包括：
    第一导电层，位于所述衬底基板与所述像素限定层之间；其中，所述第一导电层包括多条数据线图形和多条电源信号线图形；
    第一绝缘层，位于所述衬底基板与所述第一导电层之间；
    第二导电层，位于所述衬底基板与所述第一绝缘层之间，且所述第二导电层包括：多个辅助导电部，所述子像素的电容导电部包括所述辅助导电部；其中，同一所述子像素中，所述辅助导电部的第一端在所述衬底基板的正投影与所述电源信号线图形在所述衬底基板的正投影具有交叠区域，所述辅助导电部的第二端在所述衬底基板的正投影与所述数据线图形在所述衬底基板的正投影具有交叠区域；且所述辅助导电部耦接电源信号线图形；
    所述第一辅助交叠面积包括所述第一颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
    所述第二辅助交叠面积包括所述第二颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
    所述第三辅助交叠面积包括所述第三颜色子像素中的辅助导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积。
  4. 如权利要求3所述的显示面板，其中，所述第一颜色子像素中的辅助导电部包括第一辅助暴露部，且所述第一辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第一辅助交叠面积包括第一辅助子交叠面积，且所述第一辅 助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第一辅助子交叠面积；
    所述第二颜色子像素中的辅助导电部包括第二辅助暴露部，且所述第二辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第二辅助交叠面积包括第二辅助子交叠面积，且所述第二辅助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第二辅助子交叠面积；
    所述第三颜色子像素中的辅助导电部包括第三辅助暴露部，且所述第三辅助暴露部在所述衬底基板的正投影分别与所述数据线图形和所述电源信号线图形在所述衬底基板的正投影不交叠；以及所述第三辅助交叠面积包括第三辅助子交叠面积，且所述第三辅助暴露部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第三辅助子交叠面积；
    所述第一辅助子交叠面积大于所述第二辅助子交叠面积和所述第三辅助子交叠面积中的至少一个。
  5. 如权利要求4所述的显示面板，其中，所述第二辅助子交叠面积大于所述第三辅助子交叠面积；或者，所述第三辅助子交叠面积大致等于所述第二辅助子交叠面积。
  6. 如权利要求4所述的显示面板，其中，所述第一颜色子像素中，所述第一辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间；和/或，
    所述第二颜色子像素中，所述第二辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间；和/或，
    所述第三颜色子像素中，所述第三辅助暴露部在所述衬底基板的正投影位于所述数据线图形和所述电源信号线图形在所述衬底基板的正投影之间。
  7. 如权利要求6所述的显示面板，其中，所述辅助导电部在所述衬底基板的正投影具有总面积；
    所述第一辅助子交叠面积与所述总面积之间的比值范围为：1/3～2/3；和/或，
    所述第二辅助子交叠面积与所述总面积之间的比值范围为：0～1/4；和/或，
    所述第三辅助子交叠面积与所述总面积之间的比值范围为：0～1/16。
  8. 如权利要求7所述的显示面板，其中，所述第一颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第一辅助暴露部在所述衬底基板的正投影；和/或，
    所述第二颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第二辅助暴露部在所述衬底基板的正投影；和/或，
    所述第三颜色子像素中，所述触控电极在所述衬底基板的正投影覆盖所述第三辅助暴露部在所述衬底基板的正投影。
  9. 如权利要求4-8任一项所述的显示面板，其中，所述第一颜色子像素中的辅助导电部还包括第一辅助遮挡部，且所述第一辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第一辅助暴露部在列方向的宽度小于所述第一辅助遮挡部在所述列方向的宽度；和/或，
    所述第二颜色子像素中的辅助导电部还包括第二辅助遮挡部，且所述第二辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第二辅助暴露部在列方向的宽度小于所述第二辅助遮挡部在所述列方向的宽度；和/或，
    所述第三颜色子像素中的辅助导电部还包括第三辅助遮挡部，且所述第三辅助遮挡部在所述衬底基板的正投影与所述数据线图形和所述电源信号线图形中的至少一种在所述衬底基板的正投影交叠；其中，所述第三辅助暴露部在列方向的宽度小于所述第三辅助遮挡部在所述列方向的宽度。
  10. 如权利要求3所述的显示面板，其中，所述像素电路还包括第一电容；
    所述第一颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第一存储交叠面积；
    所述第二颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第二存储交叠面积；
    所述第三颜色子像素中的第一电容在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影具有第三存储交叠面积；
    所述第一存储交叠面积和所述第二存储交叠面积中的至少一个大于所述第三存储交叠面积。
  11. 如权利要求10所述的显示面板，其中，所述第一存储交叠面积大于所述第二存储交叠面积。
  12. 如权利要求10所述的显示面板，其中，所述第二导电层还包括与所述辅助导电部间隔设置的多个存储导电部；所述子像素包括所述存储导电部；所述存储导电部作为所述第一电容的第二极板；
    所述第一存储交叠面积包括所述第一颜色子像素中的存储导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
    所述第二存储交叠面积包括所述第二颜色子像素中的存储导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积；
    所述第三存储交叠面积包括所述第三颜色子像素中的存储导电部在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠面积。
  13. 如权利要求1所述的显示面板，其中，所述触控电极在所述衬底基板的正投影的形状为网格状，且所述触控电极在所述衬底基板的正投影与所述开口区域在所述衬底基板的正投影不交叠。
  14. 如权利要求13所述的显示面板，其中，所述触控电极包括第一电极部和第二电极部；其中，所述第一电极部在所述衬底基板的正投影与辅助导电部在所述衬底基板的正投影具有交叠区域，所述第二电极部在所述衬底基板的正投影与所述辅助导电部在所述衬底基板的正投影不交叠；
    所述第一电极部的宽度大于所述第二电极部的宽度。
  15. 如权利要求1所述的显示面板，其中，所述显示面板还包括：
    发光功能层，位于所述像素限定层与所述触控电极之间，且所述发光功能层包括多个第一颜色发光层、多个第二颜色发光层以及多个第三颜色发光层；
    其中，所述第一颜色发光层在所述衬底基板的正投影覆盖所述第一颜色子像素中的开口区域在所述衬底基板的正投影；
    所述第二颜色发光层在所述衬底基板的正投影覆盖所述第二颜色子像素中的开口区域在所述衬底基板的正投影；
    所述第三颜色发光层在所述衬底基板的正投影覆盖所述第三颜色子像素中的开口区域在所述衬底基板的正投影。
  16. 如权利要求15所述的显示面板，其中，位于相邻所述开口区域之间的触控电极在所述衬底基板的正投影与至少两种不同颜色的发光层在所述衬底基板的正投影交叠。
  17. 如权利要求15所述的显示面板，其中，围绕于所述第三颜色子像素的开口区域的触控电极在所述衬底基板的正投影位于所述第三颜色发光层在所述衬底基板的正投影内；和/或，
    围绕于所述第二颜色子像素的开口区域的触控电极在所述衬底基板的正投影位于所述第二颜色发光层在所述衬底基板的正投影内；和/或，
    围绕于所述第一颜色子像素的开口区域的触控电极在所述衬底基板的正投影位于所述第一颜色发光层在所述衬底基板的正投影内。
  18. 如权利要求15所述的显示面板，其中，对于相邻的所述第三颜色发光层和所述第二颜色发光层而言，所述第三颜色发光层在所述衬底基板的正投影的边界与所述触控电极在所述衬底基板的正投影的边界之间具有第一最小距离，所述第二颜色发光层在所述衬底基板的正投影的边界与所述触控电极在所述衬底基板的正投影的边界之间具有第二最小距离；
    所述第一最小距离大于所述第二最小距离。
  19. 如权利要求13所述的显示面板，其中，围绕于所述第一颜色子像素 的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第一网格面积；
    围绕于所述第二颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第二网格面积；
    围绕于所述第三颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第三网格面积；
    所述第三网格面积大于所述第二网格面积大于第一网格面积。
  20. 如权利要求19所述的显示面板，其中，所述显示面板包括多个重复单元；所述重复单元包括所述第一颜色子像素、所述第二颜色子像素以及所述第三颜色子像素。
  21. 如权利要求20所述的显示面板，其中，所述重复单元还包括第四颜色子像素；围绕于所述第四颜色子像素的开口区域的触控电极在所述衬底基板的正投影所围成的面积为第四网格面积；
    所述第一颜色子像素对应的第一网格面积大于或大致等于所述第四颜色子像素对应的第四网格面积。
  22. 如权利要求21所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素的开口区域和所述第一颜色子像素的开口区域沿第一方向排列；
    围绕于所述第三颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向的方向上具有第一宽度；
    围绕于所述第一颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向的方向上具有第二宽度；
    所述第一宽度大于所述第二宽度。
  23. 如权利要求21或22所述的显示面板，其中，同一所述重复单元中，所述第二颜色子像素的开口区域和所述第四颜色子像素的开口区域沿第一方向排列；
    围绕于所述第二颜色子像素的开口区域的触控电极的内边界所围成的区 域在垂直于所述第一方向的方向上具有第三宽度；
    围绕于所述第四颜色子像素的开口区域的触控电极的内边界所围成的区域在垂直于所述第一方向的方向上具有第四宽度；
    所述第三宽度大于所述第四宽度。
  24. 如权利要求13所述的显示面板，其中，与辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与第三方向具有夹角β；且15°≤β≤60°；其中，所述第三方向与所述数据线图形的延伸方向大致垂直。
  25. 如权利要求24所述的显示面板，其中，tanβ＝A1/A2；其中，A1代表所述辅助导电部在垂直于所述第三方向的方向上的宽度，A2代表所述辅助导电部在所述第三方向上的宽度。
  26. 如权利要求24所述的显示面板，其中，与第一颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第一夹角；
    与第二颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第二夹角；
    与第三颜色子像素中的辅助导电部的正投影具有交叠面积的触控电极的网格线的延伸方向与所述第三方向具有第三夹角；
    所述第一夹角小于所述第二夹角小于所述第三夹角。
  27. 如权利要求24所述的显示面板，其中，以相邻的四个子像素的开口区域为一个开口组，所述触控电极的网格交叉点在所述衬底基板的正投影位于所述开口组在所述衬底基板的正投影所围成的区域中。
  28. 如权利要求27所述的显示面板，其中，所述触控电极的网格交叉点在所述衬底基板的正投影大致位于所述开口组在所述衬底基板的正投影所围成的区域的中心处。
  29. 如权利要求21所述的显示面板，其中，所述第四颜色子像素与所述第一颜色子像素的发光颜色相同。
  30. 如权利要求1所述的显示面板，其中，各所述子像素还包括第一电 极；
    所述第一颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第一阳极交叠面积；
    所述第二颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第二阳极交叠面积；
    所述第三颜色子像素中的第一电极在所述衬底基板的正投影与所述触控电极在所述衬底基板的正投影之间的交叠区域具有第三阳极交叠面积；
    所述第一阳极交叠面积和所述第二阳极交叠面积中的至少一个大于所述第三阳极交叠面积。
  31. 如权利要求30所述的显示面板，其中，所述第一阳极交叠面积大于所述第二阳极交叠面积；或者，
    所述第一阳极交叠面积大致等于所述第二阳极交叠面积。
  32. 一种显示面板，其中，包括：
    衬底基板；
    晶体管阵列层，位于所述衬底基板上；
    像素限定层，位于所述晶体管阵列层背离所述衬底基板一侧；
    触控电极，位于所述像素限定层背离所述衬底基板一侧；
    所述衬底基板具有显示区，所述显示区包括多个子像素；所述子像素包括像素电路和发光元件；所述像素电路包括栅线图形、数据线图形、电源信号线图形；
    所述晶体管阵列层包括多个电容导电部，所述子像素包括对应的所述电容导电部；其中，同一所述子像素中，所述电容导电部与所述子像素对应的数据线图形和/或所述子像素对应的电源信号线图形存在交叠区域；所述电容导电部至少耦接所述子像素对应的电源信号线图形或所述子像素对应的数据线图形；
    所述像素限定层包括多个开口区域，所述子像素包括对应的所述开口区域；
    至少部分所述触控电极在所述衬底基板的正投影为网格；
    所述晶体管阵列层还包括第一导电层，所述电容导电部形成在所述第一导电层；
    所述像素电路包括多个晶体管，至少部分晶体管的源极和漏极形成在所述第一导电层。
  33. 如权利要求32所述的显示面板，其中，所述电容导电部为弧形或不规则图形。
  34. 如权利要求32所述的显示面板，其中，所述电容导电部包括辅助导电部，所述辅助导电部与所述电源信号线图形、数据线图形、所述触控电极均至少部分交叠。
  35. 如权利要求32所述的显示面板，其中，相邻两列所述子像素的所述电源信号线图形通过电源输入线电性连接；或者颜色相同的相邻两列所述子像素对应的所述电源信号线图形通过电源输入线电性连接。
  36. 如权利要求35所述的显示面板，其中，所述电源输入线与所述电源信号线图形位于不同层。
  37. 如权利要求32所述的显示面板，其中，所述电源信号线图形的宽度大于所述数据线图形的宽度。
  38. 如权利要求35所述的显示面板，其中，所述数据线图形和所述电源信号线图形不设置于同一导电层；或，所述数据线图形和所述电源输入线不设置于同一导电层。
  39. 如权利要求32所述的显示面板，其中，所述第一导电层包括层叠设置的第一子导电层和第二子导电层，第一子导电层和第二子导电层之间设置有第一子绝缘层。
  40. 如权利要求32所述的显示面板，其中，所述电容导电部与所述电源信号线图形交叠面积大于所述电容导电部与所述数据线图形交叠面积。
  41. 如权利要求32所述的显示面板，其中，所述像素电路包括：第七晶体管、第二晶体管；所述第七晶体管的栅极与第二复位信号线图形耦接，所 述第二晶体管的栅极与第一复位信号线图形耦接；第所述一复位信号线图形和所述第二复位信号线图形传输不相同的信号。
  42. 如权利要求32所述的显示面板，其中，所述像素电路包括：数据写入晶体管、第一晶体管；所述数据写入晶体管的栅极耦接的所述栅线图形，与所述第一晶体管的栅极藕接的所述栅线图形传输不同的时序信号。
  43. 一种显示装置，其中，包括如权利要求1-42任一项所述的显示面板。
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