WO2023185630A1 - 显示基板 - Google Patents

显示基板 Download PDF

Info

Publication number
WO2023185630A1
WO2023185630A1 PCT/CN2023/083397 CN2023083397W WO2023185630A1 WO 2023185630 A1 WO2023185630 A1 WO 2023185630A1 CN 2023083397 W CN2023083397 W CN 2023083397W WO 2023185630 A1 WO2023185630 A1 WO 2023185630A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
display area
pixel
light
display
Prior art date
Application number
PCT/CN2023/083397
Other languages
English (en)
French (fr)
Other versions
WO2023185630A9 (zh
Inventor
丁彦红
王铸
刘斌
杨淦淞
闫政龙
马丹阳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023185630A1 publication Critical patent/WO2023185630A1/zh
Publication of WO2023185630A9 publication Critical patent/WO2023185630A9/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • Embodiments of the present disclosure relate to a display substrate.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the width of the frame is an important factor affecting the visual effect. Generally speaking, the narrower the frame, the better the visual effect.
  • At least one embodiment of the present disclosure provides a display substrate having a display area.
  • the display area includes a substrate substrate, a plurality of sub-pixels, a plurality of data lines and a plurality of first signal lines.
  • the plurality of sub-pixels are disposed on the substrate.
  • the base substrate is provided on the first metal layer.
  • a plurality of first signal lines are provided on the base substrate and is provided on the second metal layer.
  • the second metal layer is provided on the first metal layer.
  • the display area includes a first display area, in the first display area, the plurality of first signal lines extend along a first direction, and the first display area includes a plurality of first compensation patterns, wherein, In the first display area, the first electrodes of the light-emitting devices of the plurality of sub-pixels are located on the plurality of first signal lines and the plurality of first compensation patterns away from the base substrate.
  • the orthographic projection of at least one first compensation pattern among the plurality of first compensation patterns on the base substrate is in contact with the first electrode of the light-emitting device of at least one sub-pixel among the plurality of sub-pixels.
  • the orthographic projections on the substrate at least partially overlap.
  • the plurality of first compensation patterns are provided on the second metal layer.
  • the display area further includes a second display area, and in the second display area, the plurality of first signal lines extend along the second direction, and the first signal lines extend in the second display area.
  • the second display area includes a plurality of second compensation patterns, wherein in the second display area, the first electrodes of the light-emitting devices of the plurality of sub-pixels are located on the plurality of first signal lines and the plurality of second compensation patterns.
  • an orthographic projection of at least one of the plurality of second compensation patterns on the base substrate is consistent with at least one of the plurality of sub-pixels. Orthographic projections of the first electrodes of the light-emitting devices on the base substrate at least partially overlap; the first direction is different from the second direction.
  • the first direction is perpendicular to the second direction.
  • the plurality of first signal lines are electrically connected to the plurality of data lines through a plurality of first via holes, and the plurality of first via holes are located at the corresponding
  • the second display area is arranged in a straight line, and the straight line intersects the first direction and the second direction.
  • the plurality of first signal lines extend along the second direction to the edge of the display area.
  • the plurality of first signal lines extend to the edge of the display area along the second direction, and in the plurality of first signal lines, A side of the first via hole close to the edge is disconnected.
  • the portions of the plurality of first signal lines that are disconnected on the side of the plurality of via holes close to the edge are respectively connected with the plurality of data lines. Electrical connection.
  • the pixel driving circuit and the first electrode are electrically connected through a second via hole.
  • the second via hole In a direction perpendicular to the base substrate, the second via hole The hole does not overlap with the first via hole.
  • the plurality of first compensation patterns and the plurality of second compensation patterns are respectively in a straight shape, a cross shape, a field shape, a rice shape, a ring shape, or a The ones are in block shape.
  • the plurality of second compensation patterns are provided on the second metal layer.
  • the plurality of first compensation patterns include electrically connected to the plurality of first signal lines respectively and along the second direction. Extended straight-line first compensation pattern.
  • the plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels, and the light-emitting devices of the red sub-pixel and the blue sub-pixel are located in the same rows, the light-emitting devices of the green sub-pixels are located in the same row, the rows of the light-emitting devices of the red sub-pixels and the blue sub-pixels are alternately arranged with the rows of the light-emitting devices of the green sub-pixels; the red sub-pixels The light-emitting devices of the pixel and the blue sub-pixel are located in the same column, the light-emitting devices of the green sub-pixel are located in the same column, and the light-emitting devices of the red sub-pixel and the blue sub-pixel are located in the same column as the green sub-pixel. The columns of light-emitting devices are arranged alternately.
  • the first signal line and the light-emitting device of the green sub-pixel are at least Partially overlapping, the first signal line does not overlap with the light-emitting devices of the red sub-pixel and the blue sub-pixel.
  • the first electrode of the light-emitting device of the green sub-pixel is connected to the first electrode of the light-emitting device of the green sub-pixel.
  • the glyph first compensation patterns at least partially overlap.
  • the plurality of first compensation patterns further include cross-shaped first compensation patterns respectively provided on at least one side of the plurality of first signal lines.
  • the first compensation pattern includes two portions extending along the first direction and the second direction respectively.
  • the cross-shaped first compensation pattern is spaced apart from the plurality of first signal lines.
  • the first electrodes of the light-emitting devices of the red sub-pixel and the blue sub-pixel are respectively connected to a cross-shaped The first compensation pattern overlaps.
  • the plurality of second compensation patterns include ten lines respectively disposed on at least one side of the plurality of first signal lines.
  • a glyph-shaped second compensation pattern, the cross-shaped second compensation pattern includes two parts extending along the first direction and the second direction respectively; in a direction perpendicular to the base substrate, the green sub-shape
  • the first electrodes of the light-emitting devices of the pixel, the red sub-pixel and the blue sub-pixel respectively overlap with a cross-shaped second compensation pattern.
  • the light-emitting device further includes a luminescent material layer disposed on a side of the first electrode away from the base substrate and a luminescent material layer disposed on a side of the first electrode away from the base substrate.
  • the cross-shaped second compensation pattern is electrically connected to the first power signal line.
  • the display substrate further includes a second power signal line, and the plurality of first signal lines are provided away from the second power signal line and away from the base substrate.
  • the cross-shaped second compensation pattern is electrically connected to the second power signal line.
  • the display area further includes a third display area, the third display area includes a metal pattern, and the first electrodes of the light-emitting devices of the plurality of sub-pixels are disposed on the display substrate.
  • the metal pattern On the side of the metal pattern away from the base substrate, the metal pattern includes a plurality of metal lines extending and intersecting at least along the first direction and the second direction; or, the metal pattern includes a plurality of metal lines respectively connected with A plurality of block patterns in which first electrodes of light-emitting devices of at least part of the plurality of sub-pixels overlap.
  • the metal pattern and the plurality of first signal lines are arranged in the same layer.
  • the second display area includes a first sub-display area and a second sub-display area, and the first display area is between the first sub-display area and the between the second sub-display area.
  • the third display area is provided on one side of the first display area and the second display area.
  • Figure 1 is a schematic plan view of a display substrate
  • FIG. 2A is a schematic plan view of some sub-pixels in the first sub-region of the display substrate in FIG. 1;
  • FIG. 2B is a schematic plan view of some sub-pixels in the second sub-region of the display substrate in FIG. 1;
  • 3A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • 3B is another schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4A is a partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure
  • 4B is a partial cross-sectional schematic diagram of the connection between the first signal line and the data line in the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of some sub-pixels in the first display area of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of some sub-pixels in the second display area of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic plan view of some sub-pixels in the third display area of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG 8 is another plan view of some sub-pixels in the second display area or the third display area of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic plan view of a compensation pattern in a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is another plan view of a compensation pattern in a display substrate according to at least one embodiment of the present disclosure.
  • Figure 11 is another plan view of a compensation pattern in a display substrate provided by at least one embodiment of the present disclosure.
  • 15A-15I are schematic plan views of functional layers in a display substrate sequentially stacked according to at least one embodiment of the present disclosure.
  • FIG. 1 shows a schematic plan view of a display substrate.
  • the display substrate has a display area A and a peripheral area B surrounding the display area A.
  • some traces in the peripheral area B can also be arranged in the display area A to reduce the area of the peripheral area B and achieve a narrow frame.
  • the width of the peripheral area B can be reduced to about 1.0 mm, thereby achieving an extremely narrow bezel.
  • the display area A is provided with multiple traces extending laterally or vertically.
  • the traces in different areas of the display area A extend in different directions.
  • the display area A includes a plurality of sub-areas, namely a first sub-area 1 , a second sub-area 2 and a third sub-area 3 .
  • the traces extend in the longitudinal direction
  • the traces extend in the transverse direction
  • the traces extend in the transverse direction.
  • the light-emitting device used for display on the display substrate is disposed above these traces.
  • the inventor of the present disclosure found during research that when a light-emitting device is disposed above these traces, at least part of the structure of the light-emitting device, such as an electrode (such as an anode) close to these traces, will be uneven, so the light-emitting device emits The light will be unevenly reflected by the uneven electrode, which will affect the display effect of the display substrate. For example, the Mura phenomenon will appear, and traces of wiring will also appear when lighting.
  • FIG. 2A shows the impact of the wiring in the first sub-region 1 on the electrodes of the light-emitting device.
  • 2B shows the impact of the wiring in the second sub-region 2 on the electrodes of the light-emitting device.
  • traces of wiring will appear on the electrode C of the light-emitting device.
  • the traces of the traces extend longitudinally, as shown by the rectangular box in Figure 2A; as shown in Figure 2B, in the second sub-region 2, the traces of the traces extend horizontally Extend, as shown by the rectangular box in Figure 2B.
  • the display substrate will have screen-off Mura when in the dark state, and the shape of the screen-off Mura completely matches the shape of the traces; when the display substrate is lit, there are obvious traces of penetrating traces under the electrodes, which affects The display effect of the display substrate is improved.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate has a display area.
  • the display area includes a base substrate, a plurality of sub-pixels, a plurality of data lines and a plurality of first signal lines.
  • the plurality of sub-pixels are disposed on the base substrate.
  • the plurality of sub-pixels each includes a pixel driving circuit and a light-emitting device, and the light-emitting device includes a first electrode electrically connected to the pixel driving circuit; a plurality of data lines are provided on the base substrate, and are provided on the first A metal layer, a plurality of first signal lines are provided on the base substrate, and are provided on a second metal layer, the second metal layer is provided on a side of the first metal layer away from the base substrate, the plurality of first signal lines At least one first signal line in the first signal line is electrically connected to at least one first signal line among the plurality of data lines through a first via hole; the display area includes a first display area, and in the first display area, the plurality of first signal lines A signal line extends along a first direction.
  • the first display area includes a plurality of first compensation patterns.
  • first electrodes of light-emitting devices of a plurality of sub-pixels are located on the plurality of first signal lines and a plurality of first compensation patterns.
  • an orthographic projection of at least one first compensation pattern among the plurality of first compensation patterns on the base substrate is in contact with the first electrode of the light-emitting device of at least one sub-pixel among the plurality of sub-pixels.
  • the orthographic projections on the base substrate at least partially overlap.
  • the first compensation pattern can reduce or even eliminate the unevenness caused by the first signal line to the first electrode of the light-emitting device, thereby avoiding the screen-off Mura that occurs when the display substrate is in a dark state. Phenomenon, uneven display when lit, improve the display effect of the display substrate.
  • FIG. 3A shows a schematic plan view of the display substrate
  • FIG. 4A shows a partial cross-sectional view of a sub-pixel of the display substrate.
  • the display substrate has a display area AA.
  • the display substrate also includes a base substrate 110 , a plurality of sub-pixels and a plurality of first signal lines L1 .
  • the plurality of sub-pixels are arranged on the base substrate 110 For example, multiple sub-pixels are arranged in an array of multiple rows and columns.
  • the pixel driving circuit includes a plurality of thin film transistors (a first thin film transistor T1 and a second thin film transistor T1 are shown in FIG. 4A
  • the structure of the thin film transistor T2 as an example) and the storage capacitor C can be formed as a 3T1C pixel drive circuit (including three thin film transistors and a storage capacitor) or a 7T1C pixel drive circuit (including seven thin film transistors and a storage capacitor), etc.
  • the embodiments of the present disclosure do not limit the specific form of the pixel driving circuit.
  • the light-emitting device EM includes a first electrode 141 electrically connected to the pixel driving circuit, a second electrode 143 spaced apart from the first electrode 141, and a light-emitting material layer 142 between the first electrode 141 and the second electrode 143.
  • the pixel driving circuit can drive the light-emitting device EM to emit light.
  • the first electrode 141 may serve as the anode of the light-emitting device EM
  • the second electrode 143 may serve as the cathode of the light-emitting device EM.
  • the luminescent material layer 142 may include organic luminescent materials, and different sub-pixels may include organic luminescent materials that emit different colors as needed.
  • the display area AA includes a first display area AA1
  • the first display area AA1 includes a plurality of first compensation patterns S1 .
  • a plurality of first signal lines L1 are provided on the substrate 110 and extend along a first direction (the vertical direction in FIG. 3A), and a plurality of first compensation patterns S1 are provided on the substrate 110.
  • On the substrate 110 and respectively disposed on at least one side of the plurality of first signal lines L1 in a direction parallel to the base substrate 110 , for example, on one side or both sides of the plurality of first signal lines L1 .
  • the first electrodes 141 of the light-emitting devices EM of the plurality of sub-pixels are located on the side of the plurality of first signal lines L1 and the plurality of first compensation patterns S1 away from the base substrate 110 , the orthographic projection of at least one first compensation pattern S1 among the plurality of first compensation patterns S1 on the base substrate 110 and the first electrode 141 of the light-emitting device of at least one of the plurality of sub-pixels on the base substrate 110
  • the first electrodes 141 correspond one to one and at least partially overlap.
  • the first compensation pattern S1 can at least partially raise the first electrode 141, thereby weakening or even eliminating the unevenness caused by the first signal line L1 to the first electrode 141 of the light emitting device EM. Eliminating the uneven reflection caused by the unevenness of the first electrode 141 can avoid the screen-off Mura phenomenon that occurs when the display substrate is in a dark state and the display unevenness when it is lit, thereby improving the display effect of the display substrate.
  • FIG. 4B shows a schematic cross-sectional view of the display substrate at the first via hole.
  • the display substrate also includes a plurality of data lines DT, and the plurality of data lines DT are disposed on the base substrate, and Disposed on the first metal layer M1, the plurality of first signal lines L1 are provided on the base substrate, and are provided on the second metal layer M2.
  • the second metal layer M2 is disposed on a side of the first metal layer M1 away from the base substrate. side, at least one first signal line L1 among the plurality of first signal lines L1 is electrically connected to at least one data line DT among the plurality of data lines DT through the first via VH1.
  • the plurality of first signal lines L1 are respectively It is electrically connected to the plurality of data lines DT through the plurality of first via holes VH1. Therefore, the plurality of first signal lines L1 can transmit data signals to the plurality of data lines DT, thereby providing data signals to the plurality of sub-pixels.
  • the plurality of first compensation patterns S1 are disposed on the second metal layer M2 and thus are disposed on the same layer as the plurality of first signal lines L1. Therefore, the same material layer can be used in the preparation process to be formed through the same patterning process. This can simplify the preparation process of the display substrate.
  • the display area AA also includes a second display area AA2
  • the second display area AA2 includes a plurality of second compensation patterns S2 , for example, in the second display area AA2 , a plurality of first signal lines L1 are disposed on the base substrate 110 and extend along the second direction (horizontal direction in FIG. 3A), and a plurality of second compensation patterns S2 are disposed on the base substrate 110 and are parallel to the substrate.
  • the substrate 110 is disposed on at least one side of the plurality of first signal lines L1, for example, on one side or both sides of the plurality of first signal lines L1.
  • the first electrodes 141 of the light-emitting devices EM of the plurality of sub-pixels are located on the side of the plurality of first signal lines L1 and the plurality of second compensation patterns S2 away from the base substrate 110, and the plurality of The orthographic projection of at least one second compensation pattern S2 of the two compensation patterns S2 on the base substrate 110 is at least the same as the orthographic projection of the first electrode 141 of the light emitting device of at least one sub-pixel among the plurality of sub-pixels on the base substrate 110 .
  • the plurality of second compensation patterns S2 correspond one-to-one with the first electrodes 141 of the light-emitting devices EM of at least some of the sub-pixels and at least partially overlap.
  • the second compensation pattern S2 can at least partially raise the first electrode 141, thereby weakening or even eliminating the unevenness caused by the first signal line L1 to the first electrode 141 of the light emitting device EM. Eliminating the uneven reflection caused by the unevenness of the first electrode 141 can avoid the screen-off Mura phenomenon that occurs when the display substrate is in a dark state and the display unevenness when it is lit, thereby improving the display effect of the display substrate.
  • the above-mentioned first direction is different from the second direction.
  • the first party perpendicular to the second direction.
  • the first direction is the vertical direction, that is, the column direction of the subpixels
  • the second direction is the horizontal direction, that is, the row direction of the subpixels.
  • the first direction may also be the row direction of the sub-pixels
  • the second direction may be the column direction of the sub-pixels.
  • the plurality of first compensation patterns S1 and the plurality of second compensation patterns S2 may respectively be in a straight shape, a cross shape, a field shape, a rice shape, an annular shape, or a block shape.
  • the shapes of the plurality of first compensation patterns S1 and the plurality of second compensation patterns S2 may be the same or different.
  • the plurality of second compensation patterns S2 are also provided on the second metal layer M2, that is, the plurality of second compensation patterns S2 are provided on the same layer as the plurality of first compensation patterns S1 and the first signal line L1. , to simplify the preparation process of the display substrate and fully realize the compensation effect of the compensation pattern on the wiring.
  • “same layer arrangement” means that two (or more) functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate, that is, during the preparation process , the two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process.
  • a plurality of first via holes VH1 are located in the second display area AA2 and are arranged in a straight line.
  • the straight line intersects the first direction and the second direction, and is, for example, reflected as a diagonal line in the figure.
  • the plurality of first signal lines L1 extend along the second direction to the edges of the display area AA (shown as the edges on the left and right sides in the figure). ). Therefore, the first signal line L1 can have better etching uniformity during the preparation process, avoid the unevenness of the preparation process caused by the first signal line L1 of different lengths, and improve the yield of the display substrate.
  • the first signal line L1 can obtain a data signal from the driving circuit FPC provided below the display area AA, and then the data signal is transmitted along the first direction in the first display area AA1, and then in the second direction along the second display area AA2. transmitted, and then transmitted to the data line DT located on the first metal layer M1, and then transmitted to each sub-pixel through the data line DT.
  • the plurality of first signal lines L1 extend to the edge of the display area along the second direction, and in the plurality of first via holes VH1 One side is disconnected near the edge of the display area.
  • the first signal line L1 can still obtain the data signal from the driving circuit FPC provided below the display area AA, and then transmit the data signal to the data line DT located on the first metal layer M1, and then the data line DT transmits it to each sub-pixel.
  • a portion of the disconnected signal lines DT1 close to the edge of the display area AA may be floating; or, in some embodiments, the plurality of first signal lines L1
  • the disconnected portions DT1 on one side of the plurality of vias VH1 close to the edge can be electrically connected to the plurality of data lines DT respectively.
  • a section of the signal line DT1 is connected in parallel to the plurality of data lines DT, which can reduce the voltage drop of the data lines DT. .
  • the pixel driving circuit and the first electrode 141 are electrically connected through the second via hole VH2.
  • the second via hole VH2 does not intersect with the plurality of first via holes VH1. Stack. That is, the second via hole VH2 and the first via hole VH1 adopt an avoidance design to avoid poor preparation of the display substrate near each via hole.
  • FIG. 5 shows a schematic plan view of some sub-pixels of the first display area.
  • a plurality of sub-pixels include a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, one red sub-pixel R, two green sub-pixels G and one blue sub-pixel B constitutes a pixel unit, and multiple pixel units are arranged in an array on the base substrate 110 .
  • a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B may also form a pixel unit.
  • the embodiments of the present disclosure do not limit the specific composition of the pixel unit.
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same row
  • the light-emitting devices of the green sub-pixel G are located in the same row
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel G are located in the same row.
  • the rows in which the light-emitting devices of the pixel B are located and the rows in which the light-emitting devices of the green sub-pixel G are located are alternately arranged.
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same column
  • the light-emitting devices of the green sub-pixel G are located in the same column
  • the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same column as the green sub-pixel G.
  • the columns of light-emitting devices are arranged alternately.
  • the first signal line L1 in the first display area AA1, in the direction perpendicular to the base substrate, the first signal line L1 at least partially overlaps the light-emitting device of the green sub-pixel G.
  • a signal line L1 does not overlap with the light emitting devices of the red sub-pixel R and the blue sub-pixel B.
  • the plurality of first compensation patterns S1 include linear first compensation patterns S11 that are respectively electrically connected to the plurality of first signal lines L1 and extend along the second direction.
  • the straight-shaped first compensation pattern S11 passes through the first signal line L1 and thus includes two parts respectively located on both sides of the first signal line L1.
  • the first electrode 141 of the light-emitting device of the green sub-pixel G overlaps the first signal line L1.
  • the straight-shaped first compensation pattern S11 can at least partially raise the first electrode of the light-emitting device of the green sub-pixel G, that is, the straight-shaped first compensation pattern S11 is disposed below the first electrode of the light-emitting device of the green sub-pixel G, Therefore, in the direction perpendicular to the base substrate 110, the green sub-pixel G The first electrode of the light-emitting device at least partially overlaps with the straight-shaped first compensation pattern S11.
  • the plurality of first compensation patterns S1 further include a cross-shaped first compensation pattern S12 respectively disposed on at least one side of the plurality of first signal lines L1, and the cross-shaped first compensation pattern S12 includes a cross-shaped first compensation pattern S12 respectively along the first signal line L1. Two parts extending in one direction and a second direction.
  • the cross-shaped first compensation pattern S12 is spaced apart from the plurality of first signal lines L1, that is, the cross-shaped first compensation pattern S12 is not electrically connected to the plurality of first signal lines L1.
  • the first signal line L1 is not connected to the first electrode 141 of the light emitting device of the red sub-pixel R and the blue sub-pixel B.
  • the cross-shaped first compensation pattern S12 can be used to pad the first electrodes 141 of the light-emitting devices of the red sub-pixel R and the blue sub-pixel B, that is, the light emission of the red sub-pixel R and the blue sub-pixel B.
  • the first electrodes 141 of the device respectively overlap with a cross-shaped first compensation pattern S12.
  • the first signal line L1 and the linear first compensation pattern S11 that overlap with the first electrode of the light-emitting device of the green sub-pixel G also have a cross shape as a whole. Therefore, they overlap with the green sub-pixel G.
  • the shapes of the overlapping compensation patterns or traces of the first electrodes 141 of the light-emitting devices of the pixel G, the red sub-pixel R and the blue sub-pixel B are basically the same, so that the surfaces where the light-emitting devices of each color sub-pixel are located have basically the same shape.
  • the first electrode of the light-emitting device of each color sub-pixel has uniform reflectivity, which can improve the light-emitting uniformity of the light-emitting device of each color sub-pixel, thereby improving the display uniformity of the display substrate and improving the display effect of the display substrate .
  • FIG. 6 shows a schematic plan view of some sub-pixels of the second display area.
  • the plurality of second compensation patterns S2 include cross-shaped second compensation patterns S21 respectively provided on at least one side of the plurality of first signal lines L1.
  • the font second compensation pattern S21 includes two parts extending along the first direction and the second direction respectively. For example, in the direction perpendicular to the base substrate 110, the first electrodes 141 of the light-emitting devices of the green sub-pixel G, the red sub-pixel R and the blue sub-pixel B respectively overlap with a cross-shaped second compensation pattern S21.
  • the surface where the light-emitting devices of each color sub-pixel is located has substantially the same flatness, and also has the same flatness as the surface where the light-emitting devices of each color sub-pixel are located in the first display area AA1.
  • the first electrodes of the light-emitting devices of each color sub-pixel have uniform light reflectivity, thereby improving display uniformity in multiple display areas.
  • the luminescent material layer 142 of the light-emitting device EM is disposed on a side of the first electrode 141 away from the base substrate 110
  • the second electrode 143 is disposed on a side of the luminescent material layer 142 away from the base substrate 110 .
  • the display substrate also has a peripheral area surrounding the display area AA
  • the display substrate further includes a first power signal line L22 configured to provide a first power signal to the second electrodes 143 of the plurality of sub-pixels.
  • the first power signal is a low-level power signal.
  • the first power signal line L22 is electrically connected to the second electrodes 143 of the plurality of sub-pixels in the peripheral area NA to provide low-level power signals to the second electrodes 143 of the plurality of sub-pixels; the setting of the first power signal line L22 can be effective Reduce the power supply voltage drop (drop), thereby reducing the power consumption of the display substrate.
  • the cross-shaped second compensation pattern S21 is electrically connected to the first power signal line L22, but is not electrically connected to the first signal line L1 that provides a data signal.
  • the cross-shaped second compensation pattern S21 is integrally connected to the first power signal line L22, but is spaced apart from the first signal line L1 that provides a data signal.
  • the display area AA also includes a third display area AA3.
  • the third display area AA3 includes a metal pattern L3.
  • the first electrodes 141 of the light-emitting devices EM of the multiple sub-pixels are disposed away from the substrate of the metal pattern L3.
  • the metal pattern L3 includes a plurality of metal lines extending and intersecting at least in the first direction and the second direction (the situation shown in FIG. 3A).
  • the plurality of metal lines form a grid; or, in other embodiments, the metal pattern L3 includes a plurality of block patterns (described in detail later) respectively overlapping with the first electrodes 131 of the light-emitting devices EM of at least part of the plurality of sub-pixels.
  • the plurality of The block pattern corresponds to one-to-one and overlaps with the first electrode 131 of the light-emitting device EM of at least part of the sub-pixels.
  • the metal pattern L3 may be a dummy metal pattern that is not electrically connected to any circuit; or, in other embodiments, parts of the metal pattern L3 may be traces for transmitting electrical signals, such as transmitting low voltage The wiring of level power signals, etc., and the other part is the compensation pattern.
  • FIG. 7 shows a schematic plan view of some sub-pixels of the third display area.
  • the metal pattern L3 includes a plurality of traces L31 and a plurality of traces L32.
  • the plurality of traces L31 are electrically connected to data lines that provide data signals to multiple sub-pixels.
  • the trace L32 is electrically connected to a first power signal line that provides a first power signal, such as a low-level power signal, to the second electrode 143 of the plurality of sub-pixels.
  • the metal pattern L3 also includes a trace L31 and a trace, respectively.
  • Line L32 is electrically connected to the third compensation pattern S3. At this time, the entire data line L31, the first power signal line L32 and the third compensation pattern S3 form an interlaced mesh metal pattern.
  • each third compensation pattern S3 is in a cross shape, and in the direction perpendicular to the base substrate 110 , the light emitters of the green sub-pixel G, the red sub-pixel R and the blue sub-pixel B
  • the first electrodes 141 of the components respectively overlap with a cross-shaped third compensation pattern S3.
  • the surface where the light-emitting devices of each color sub-pixel is located has substantially the same flatness, and is similar to the surface of the light-emitting devices of each color sub-pixel in the first display area AA1 and the second display area AA2.
  • the surface they are located on also has substantially the same flatness, and the first electrode of the light-emitting device of each color sub-pixel has uniform light reflectivity, thereby improving the display uniformity of multiple display areas.
  • FIG. 8 shows another plan view of some sub-pixels in the second display area AA2 or the third display area AA3 in the display substrate.
  • the display substrate may also include a second power signal line L4.
  • the second power signal line L4 is connected to the first connection electrode CE1 (details will be introduced later) or the source and drain electrodes 123 and 124 are arranged in the same layer.
  • the second power signal line is a power line that provides a high-level power signal.
  • the plurality of first signal lines L1 are disposed on a side of the second power signal line L4 away from the base substrate 110.
  • the cross-shaped second compensation pattern S21 can be connected with the second power signal line L4.
  • the line L4 is electrically connected without being electrically connected to the plurality of first signal lines L1.
  • the second planarization layer PLN2 has a via V, and the cross-shaped second compensation pattern S21 passes through
  • the hole V is electrically connected to the second power supply signal line L4; or, in the case where the second power supply signal line L4 and the source and drain electrodes 123 and 124 are arranged in the same layer, the first planarization layer PLN1 and the second planarization layer PLN2 have Through the via hole V, the cross-shaped second compensation pattern S21 is electrically connected to the second power signal line L4 through the via hole V.
  • the metal pattern L3 is disposed on a side of the second power signal line L4 away from the base substrate 110. At this time, the metal pattern L3 may be electrically connected to the second power signal line L4.
  • the metal pattern L3 may have a via V in the planarization layer between the metal pattern L3 and the second power signal line L4, and the metal pattern L3 and the second power signal line L4 are electrically connected through the via V.
  • the metal pattern L3 is provided on the same layer as the plurality of first signal lines L1, that is, on the second metal layer M2, thereby simplifying the preparation process of the display substrate.
  • the second display area AA2 may include a first sub-display area AA21 and a second sub-display area AA22, and the first display area AA1 is between the first sub-display area AA21 and the second sub-display area AA21. between sub-display areas AA22.
  • the first sub-display area AA21 and the second sub-display area AA22 have substantially the same structure and are arranged substantially symmetrically.
  • the third display area AA3 is provided on one side of the first display area AA1 and the second display area AA2 , and is shown in FIG. 3A as being between the first display area AA1 and the second display area AA3 . upper side.
  • a plurality of first compensation patterns S1 and a plurality of second compensation patterns S2 are each in a straight shape or a cross shape.
  • a plurality of first compensation patterns S1 and a plurality of second compensation patterns S2 are each in a straight shape or a cross shape.
  • the first compensation pattern S1 and the plurality of second compensation patterns S2 may also be in the shape of a field, a triangle, a block, or other suitable shapes.
  • the block shape may be in the form of a rectangle, a square, or a pattern that is substantially consistent with the pattern of the first electrode 141 , thereby providing a substantially flat surface for the placement of the first electrode 141 .
  • the specific shapes of multiple block compensation patterns for different color sub-pixels may be the same or different.
  • FIG. 9 shows the situation where the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in the shape of a field
  • FIG. 10 shows the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern.
  • the pattern S3 is in the shape of a rice.
  • Figures 11, 12 and 13 show the situation in which the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in a block shape.
  • Figure 14 shows the first compensation pattern.
  • the pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in a ring shape.
  • the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in the shape of a rectangular block; in Figure 12, the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in the shape of a block that is basically the same as the shape of the first electrode 141; in FIG. 13, the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in the shape of a circular block. In FIG. 14 , the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 is in the shape of a circular ring. In other embodiments, the first compensation pattern S1, the second compensation pattern S2 or the third compensation pattern S3 may also be in the shape of a rectangular ring.
  • These compensation patterns are arranged below the first electrode to at least partially raise the first electrode, thereby reducing or even eliminating the unevenness caused by the first signal line L1 to the first electrode 141 of the light-emitting device EM, thereby reducing or even eliminating the first electrode 141 Uneven reflection causes uneven reflection, thereby improving the display effect of the display substrate.
  • the shapes of the plurality of first compensation patterns S1 may be the same or different
  • the shapes of the plurality of second compensation patterns S2 may be the same or different
  • the shapes of the plurality of third compensation patterns S3 may be the same or different.
  • the first thin film transistor T1 and the second thin film transistor T2 included in the pixel driving circuit may have different structures.
  • the first thin film transistor T1 includes an active layer 121, a gate electrode 122, and source and drain electrodes 123 and 124.
  • the display substrate also includes a first connection electrode CE1 located on the side of the source and drain electrodes 123 and 124 away from the substrate substrate 110 and a first connection electrode CE1 located on the side of the source and drain electrodes 123 and 124 away from the substrate substrate 110 A connection electrode CE1 is away from the second connection electrode CE2 on the side of the base substrate 110.
  • the source and drain electrode 124 is electrically connected to the first electrode 141 of the light emitting device EM through the first connection electrode CE1 and the second connection electrode CE2.
  • the second thin film transistor T2 includes an active layer 131, a first gate electrode 132, a second gate electrode 133, and source and drain electrodes 134 and 135.
  • the second thin film transistor T2 is a double-gate thin film transistor. In the direction of , the first gate electrode 132 and the second gate electrode 133 are disposed on opposite sides of the active layer 131 .
  • the plurality of first signal lines L1, the plurality of first compensation patterns S1, the plurality of second compensation patterns S2, and the metal patterns L3 are arranged in the same layer as the second connection electrode CE2, that is, they are arranged on the same layer as the second connection electrode CE2.
  • the storage capacitor C included in the pixel driving circuit includes a first capacitor electrode C1 and a second capacitor electrode C2.
  • the first capacitor electrode C1 and the gate electrode 122 of the first thin film transistor T1 are arranged on the same layer, and the second capacitor electrode C2 and the first gate electrode 132 of the second thin film transistor T2 are arranged on the same layer to simplify the preparation process of the display substrate.
  • the display substrate further includes a light-shielding layer SH disposed between the base substrate 110 and the active layer 121 .
  • the light-shielding layer SH can achieve a light-shielding effect for the active layer 121 to prevent leakage from the base substrate 110 The incident light irradiates the active layer 121 and affects the normal operation of the first thin film transistor T1.
  • the display substrate further includes a barrier layer 111 and a buffer layer 112 disposed on the base substrate 110.
  • the barrier layer 111 and the buffer layer 112 can prevent impurities in the base substrate 110 from entering into the multiple functional layers of the display substrate, thereby Play a protective role.
  • the base substrate 110 may be a rigid substrate such as glass or quartz or a flexible substrate such as polyimide.
  • the barrier layer 111 and the buffer layer 112 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the buffer layer 112 may have multiple sub-layers, and the materials of the multiple sub-layers may be the same or different.
  • the material of one sub-layer is silicon oxide
  • the material of another sub-layer is silicon nitride, etc.
  • the light-shielding layer SH can be made of metal materials such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or alloy materials.
  • An insulating layer 113 and a buffer layer 114 may also be provided on the light-shielding layer SH.
  • the insulating layer 113 and the buffer layer 114 may also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the active layer 121 may be made of silicon-based semiconductor material, such as amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • the active layer 131 can be made of metal oxide semiconductor materials, such as IGZO, ZnO, AZO, IZTO, etc.
  • the gate 122, the first gate 132, the second gate 133, the first capacitor electrode C1 and the second capacitor electrode C2 can be made of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) and other metals.
  • the material or alloy material is, for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium/aluminum/titanium.
  • the source and drain electrodes 123 and 124 and the source and drain electrodes 134 and 135 can be made of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) and other metal materials or alloy materials, for example, formed into a single-layer metal layer structure or Multi-layer metal layer structures, such as titanium/aluminum/titanium and other multi-layer metal layer structures.
  • the first connection electrode CE1 and the second connection electrode CE2 and each wiring and compensation pattern can be made of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) and other metal materials or alloy materials, such as It can be formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as titanium/aluminum/titanium and other multi-layer metal layer structures.
  • a gate insulating layer 115 may be provided between the active layer and the gate electrode, and between the first capacitor electrode and the second capacitor electrode.
  • the gate insulating layer 115 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • an interlayer insulating layer 116 may be provided between the second gate electrode 133 and the source and drain electrodes 134 and 135.
  • the interlayer insulating layer 116 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • a passivation layer PVX can be provided on the source and drain electrodes 123 and 124 and the source and drain electrodes 134 and 135, a first planarization layer PLN1 can be provided on the passivation layer PVX, and a second planarization layer can be provided on the first connection electrode CE1 PLN2, a third planarization layer PLN3 may be disposed on the second connection electrode CE2.
  • the passivation layer PVX can use inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the first planarization layer PLN1, the second planarization layer PLN2 and the third planarization layer PLN3 may be made of organic insulating materials such as polyimide and resin.
  • the first electrode 141 includes a high work function material as the anode, such as an ITO/Ag/ITO stack structure; the second electrode 143 includes a low work function material as the cathode, such as a semi-transmissive metal. Or metal alloy materials, such as Ag/Mg alloy materials.
  • the light-emitting material layer 142 may also include, for example, a hole transport layer, a hole injection layer, an electrode transport layer, an electron injection layer and other auxiliary light-emitting layers.
  • the display substrate further includes a pixel defining layer PDL disposed on the first electrode 141 and a spacer layer SP disposed on the pixel defining layer PDL.
  • the pixel definition layer PDL includes a plurality of sub-pixel openings for defining light-emitting areas of the sub-pixels.
  • the spacer layer SP is used to define the packaging space.
  • the pixel definition layer PDL and the spacer layer SP can be Use organic insulating materials such as polyimide and resin.
  • the display substrate may further include an encapsulation layer (not shown) disposed on the spacer layer SP, and the encapsulation layer may be a composite encapsulation layer, including a stack of multiple organic encapsulation layers and inorganic encapsulation layers.
  • the inorganic encapsulating layer can use inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; the organic encapsulating layer can use organic insulating materials such as polyimide and resin.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • the display substrate may also include other structures besides the above-mentioned structures.
  • other structures please refer to related technologies, which will not be described again here.
  • each thin film transistor may be a P-type thin film transistor or an N-type thin film transistor, and the structure may be a bottom gate type, a top gate type, or a double gate type.
  • the structures shown in the drawings are only exemplary. , the embodiments of the present disclosure do not limit the specific form of each thin film transistor.
  • FIGS. 15A to 15I show schematic plan views of various functional layers of a display panel stacked in sequence according to at least one embodiment of the present disclosure.
  • the pixel driving circuit adopts an 8T1C structure, that is, it includes eight thin film transistors. T1-T8 and a storage capacitor.
  • Figure 15A shows the first semiconductor layer pattern.
  • the first active layer film can be made of silicon material, and the silicon material includes amorphous silicon and polycrystalline silicon.
  • the first semiconductor layer pattern may include a first active layer 10 of the first transistor T1, a second active layer 20 of the second transistor T2, a third active layer 30 of the third transistor T3, The fourth active layer 40 of the fourth transistor T4, the fifth active layer 50 of the fifth transistor T5, the sixth active layer 60 of the sixth transistor T6, and the seventh active layer 70 of the seventh transistor T7.
  • the first active layer 10 , the second active layer 20 , the third active layer 30 , the fourth active layer 40 , the fifth active layer 50 , the sixth active layer 60 and the seventh active layer 70 are interconnected. Connected one-piece structure.
  • the third active layer 30 may be in the shape of a "ji"
  • the sixth active layer 60 and the seventh active layer 70 may have a "1" shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 102 of the first active layer 10 simultaneously serves as the first region 201 of the second active layer 20 , that is, the second region 102 of the first active layer 10 and the second active layer 102 simultaneously serve as the first region 201 of the second active layer 20 .
  • the first areas 201 of the layer 20 are interconnected.
  • the first region 301 of the third active layer 30 simultaneously serves as the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50 , that is, the first region 301 of the third active layer 30 , Second area 402 of fourth active layer 40 and the second region 502 of the fifth active layer 50 are connected to each other.
  • the second area 302 of the third active layer 30 simultaneously serves as the first area 601 of the sixth active layer 60 and the second area 202 of the second active layer 20 , that is, the second area 302 of the third active layer 30 ,
  • the first region 601 of the sixth active layer 60 and the second region 202 of the second active layer 20 are connected to each other.
  • the second region 602 of the sixth active layer 60 simultaneously serves as the second region 702 of the seventh active layer 70 , that is, the second region 602 of the sixth active layer 60 and the second region 702 of the seventh active layer 70 . interconnected.
  • the first region 101 of the first active layer 10, the first region 401 of the fourth active layer 40, the first region 501 of the fifth active layer 50, and the first region 701 of the seventh active layer 70 are provided separately.
  • the first semiconductor layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the channel region of the third active layer 30 extends along the row direction, and the first active layer 10 , the second active layer 20 , the fourth active layer 40 , and the fifth active layer 50
  • the channel regions of the sixth active layer 60 and the seventh active layer 70 extend along the column direction.
  • the first semiconductor layer may be polysilicon (p-Si), that is, the first, second, third, fourth, fifth, sixth and seventh transistors may be All are LTPS thin film transistors.
  • FIG. 15B shows a schematic plan view of a first conductive layer pattern superimposed on a first semiconductor layer pattern.
  • the first conductive layer pattern at least includes: a first scanning signal line Gate_P, a reset control signal line Reset_P, a light emission control signal line EM_P, and a first plate Ce1 of the storage capacitor.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first scanning signal line Gate_P, the reset control signal line Reset_P, and the light emission control signal line EM_P are all along the second direction.
  • the reset control signal line Reset_P is located on the side of the first scanning signal line Gate_P away from the emission control signal line EM_P, and the first plate Ce1 of the storage capacitor is disposed between the first scanning signal line Gate_P and the emission control signal line EM_P between.
  • the first plate Ce1 may be in a rectangular shape, the corners of the rectangular shape may be chamfered, and the orthographic projection of the first plate Ce1 on the base substrate is consistent with the third transistor T3 There is an overlapping area in the orthographic projections of the three active layers 30 on the base substrate.
  • the first plate Ce1 simultaneously serves as the gate electrode of the third transistor T3, and the area where the third active layer 30 of the third transistor T3 overlaps the first plate Ce1 serves as the gate electrode of the third transistor T3.
  • the channel region has one end connected to the first region of the third active layer 30 and the other end connected to the second region of the third active layer 30 .
  • the area where the reset control signal line Reset_P overlaps with the first active layer of the first transistor T1 serves as the gate electrode of the first transistor T1
  • the first scanning signal line Gate_P overlaps with the first active layer of the second transistor T2.
  • the area where the two active layers overlap serves as the gate electrode of the second transistor T2
  • the area where the first scanning signal line Gate_P overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4
  • the emission control signal The area where the line EM_P overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and the area where the light emission control signal line EM_P overlaps with the sixth active layer of the sixth transistor T6 serves as the sixth transistor.
  • the reset control signal line Reset_P in the sub-pixels of the next row of each row of sub-pixels (the same signal as the first scanning signal line Gate_P in the sub-pixels of this row) is connected to the seventh active terminal of the seventh transistor T7 in the sub-pixels of this row.
  • the area where the layers overlap serves as the gate electrode of the seventh transistor T7.
  • the first conductive layer can be used as a shield to perform a conductive treatment on the first semiconductor layer, and the first semiconductor layer in the area blocked by the first conductive layer forms each transistor.
  • the channel region of the first semiconductor layer that is not blocked by the first conductive layer is conductive, that is, the first region and the second region of each active layer are conductive.
  • FIG. 15C shows a schematic plan view of superimposing the second conductive layer pattern on the basis of FIG. 15B.
  • the second conductive layer pattern at least includes: the second plate Ce2 of the storage capacitor and the first branch GateN_B1 of the second scanning signal line GateN.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first branch GateN_B1 of the second scanning signal line GateN extends along the second direction.
  • the second plate Ce2 of the storage capacitor is located between the first branch GateN_B1 of the second scanning signal line GateN and the light emission control signal line EM_P.
  • the outline of the second electrode plate Ce2 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate Ce2 on the base substrate is consistent with the first electrode plate Ce1 There are overlapping areas for orthographic projections on the base substrate.
  • the second electrode plate Ce2 is provided with an opening H, and the opening H may be located in the middle of the second electrode plate Ce2.
  • the opening H may be a regular hexagon, so that the second electrode plate Ce2 forms a ring structure.
  • the opening H is configured to accommodate a subsequently formed fourth via hole.
  • the fourth via hole is located in the opening H and exposes the first plate Ce1, so that the second via hole of the subsequently formed eighth transistor T8 The pole is connected to the first plate Ce1.
  • FIG. 15D shows a schematic plan view of superimposing a second semiconductor layer pattern on the basis of FIG. 15C.
  • the second semiconductor layer of each sub-pixel may include an eighth active layer 80 of the eighth transistor T8.
  • the eighth active layer 80 extends along the first direction, and the eighth active layer 80 may be shaped like a dumbbell. In the first direction, the second semiconductor layers of any two adjacent columns of sub-pixels have a mirror-symmetric structure.
  • the first region 801 of the eighth active layer 80 is adjacent to the first active layer of the first transistor T1, and the second region 802 of the eighth active layer 80 is adjacent to the first capacitor C1.
  • the second semiconductor layer may be made of oxide, that is, the eighth transistor is an oxide thin film transistor.
  • FIG. 15E shows a schematic plan view of superimposing a third conductive layer pattern on the basis of FIG. 15D.
  • the third conductive layer pattern at least includes: a second branch GateN_B2 of the second scanning signal line GateN and a second initial signal line INIT2.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the second branch GateN_B2 of the second scanning signal line GateN extends along the second direction, and the second branch GateN_B2 of the second scanning signal line GateN is close to the second branch Gate_B2 of the first scanning signal line Gate. In some exemplary embodiments, a region where the second branch GateN_B2 of the second scanning signal line GateN overlaps the eighth active layer 80 serves as the gate electrode of the eighth transistor.
  • the orthographic projection of the second branch GateN_B2 of the second scanning signal line on the substrate substrate overlaps with the orthographic projection of the first branch GateN_B1 of the second scanning signal line on the substrate substrate.
  • the first branch GateN_B1 of the second scanning signal line and the second branch GateN_B2 of the second scanning signal line may be connected by signal lines in the peripheral area.
  • the second initial signal line INIT2 extends along the second direction, and within each row of sub-pixels, the second initial signal line INIT2 is disposed on a side of the reset control signal line Reset_P away from the first scanning signal line Gate_P. .
  • FIG. 15F shows a schematic plan view in which multiple via holes are formed based on FIG. 15E .
  • an insulating layer is formed on the pattern of FIG. 15E and between adjacent conductive layers, and multiple via holes are provided in the insulating layer.
  • the multiple via holes at least include: the first via hole V1 , the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the The tenth via hole V10 and the eleventh via hole V11.
  • the first via hole V1 exposes the surface of the second region of the eighth active layer 80 .
  • the second via hole V2 exposes the surface of the first region of the eighth active layer 80 .
  • the third via V3 exposes the surface of the first area of the second active layer (also the second area of the first active layer).
  • the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor T2 to the second active layer through the via hole, and to connect the second electrode of the subsequently formed first transistor T1 to the second active layer through the via hole.
  • the fourth via V4 is located within the opening H of the second plate Ce2, and the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the opening H on the substrate.
  • the fourth via hole V4 exposes the surface of the first plate Ce1.
  • the fourth via hole V4 is configured to connect the subsequently formed third connection electrode 43 to the first electrode plate Ce1 through the via hole.
  • the fifth via hole V5 exposes the surface of the first region of the fifth active layer.
  • the fifth via hole V5 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the fifth active layer through the via hole.
  • the sixth via hole V6 is located in the area where the second electrode plate Ce2 is located, and the orthographic projection of the sixth via hole V6 on the substrate is located on the orthogonal projection of the second electrode plate Ce2 on the substrate. Within the range, the sixth via hole V6 exposes the surface of the second electrode plate Ce2. The sixth via hole V6 is configured so that the fifth connection electrode 45 formed later is connected to the second electrode plate Ce2 through the via hole.
  • the seventh via hole V7 exposes the surface of the first region of the first active layer.
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via hole.
  • the eighth via hole V8 exposes the surface of the first region of the seventh active layer.
  • the eighth via hole V8 is configured to allow the subsequently formed first initial signal line to pass through the via hole V8 and the seventh via hole V8. Active layer connections.
  • the ninth via V9 exposes the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer).
  • the ninth via hole V9 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the sixth active layer through the via hole. Seven active layer connections.
  • the tenth via hole V10 exposes the surface of the first region of the fourth active layer.
  • the tenth via hole V10 is configured so that the second connection electrode 42 formed later is connected to the fourth active layer through the via hole.
  • the eleventh via hole V11 exposes the surface of the second initial signal line INIT2.
  • the eleventh via hole V11 is configured so that the sixth connection electrode 46 formed later is connected to the second initial signal line INIT2 through the via hole.
  • FIG. 15G shows a schematic plan view of superposing a fourth conductive layer pattern on the basis of FIG. 15F.
  • the fourth conductive layer at least includes: a first initial signal line INIT1, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45 and The sixth connection electrode 46 is provided.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the first initial signal line INIT1 extends along the second direction, and the first initial signal line INIT1 is connected to the first region of the seventh active layer through the eighth via V8 so that the seventh transistor T7 The first pole has the same potential as the first initial signal line INIT1.
  • one end of the first connection electrode 41 is connected to the first region of the second active layer (also the second region of the first active layer) through the third via hole V3, and the other end is connected to the first region of the second active layer through the third via V3.
  • the via V2 is connected to the first region of the eighth active layer.
  • the first connection electrode 41 may serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor, and the second electrode of the first transistor.
  • the second connection electrode 42 is connected to the first region of the fourth active layer through the tenth via hole V10 on the one hand, and is connected to the subsequently formed thirteenth via hole V13 on the other hand. Data signal line Data connection.
  • the second connection electrode 42 may serve as the first electrode of the fourth transistor T4.
  • one end of the third connection electrode 43 is connected to the second region of the eighth active layer through the first via hole V1, and the other end thereof is connected to the first plate Ce1 through the fourth via hole V4.
  • the third connection electrode 43 may serve as the second electrode of the eighth transistor T8.
  • the fourth connection electrode 44 passes through the ninth via hole V9 and the second region of the sixth active layer (also the second region of the seventh active layer) on the one hand, and on the other hand passes through the subsequent The formed twelfth via hole V12 is connected to the subsequently formed anode connection electrode.
  • the fourth connection electrode 44 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the fifth connection electrode 45 (power connection electrode) is connected to the second plate Ce2 through the sixth via V6 on the one hand, and to the fifth active layer through the fifth via V5 on the other hand.
  • the fifth connection electrode 45 is configured to be connected to the subsequently formed first power line VDD through the subsequently formed fourteenth via hole V14.
  • one end of the sixth connection electrode 46 is connected to the first region of the first active layer through the seventh via hole V7, and the other end is connected to the second initial signal line through the eleventh via hole V11,
  • the first electrode of the first transistor T1 and the second initial signal line INIT2 have the same potential.
  • FIG. 15H shows a schematic plan view of superimposing the first flat layer and the fifth conductive layer pattern on the basis of FIG. 15G.
  • the first flat layer at least includes: a twelfth via hole V12, a thirteenth via hole V13, and a fourteenth via hole V14;
  • the fifth conductive layer at least includes: a data signal line Data, a first power line VDD and anode are connected to electrode 51 .
  • the fifth conductive layer may be called the second source-drain metal (SD2) layer, which is also the first metal layer in the embodiment of the present disclosure, and the data signal line Data is the above-mentioned data line DT.
  • SD2 second source-drain metal
  • the fifth conductive layers of any two adjacent columns of sub-pixels have a mirror symmetric structure.
  • the fifth conductive layers of any two adjacent columns of sub-pixels may not have a mirror-symmetric structure, and a second opening or a second source under the third opening may be added as needed.
  • the area of the drain metal layer is increased to increase the flatness of the anode formed on the upper layer, so that the entire sub-pixel is located on a plane, thereby reducing color shift and improving display quality.
  • the first power lines VDD in two adjacent columns of sub-pixels may be an integral structure connected to each other.
  • the first power supply line VDD in the column sub-pixel forms an integrated structure connected to each other, which can make the anode formed on the upper layer flatter.
  • the anode connection electrode 51 may be in a rectangular shape, and the anode connection electrode 51 is connected to the fourth connection electrode 44 through the twelfth via hole V12.
  • the first power line VDD is connected to the fifth connection electrode 45 through the fourteenth via hole V14.
  • the data signal line Data extends along the first direction, and the data signal line Data is connected to the second connection electrode 42 through the thirteenth via hole V13 because the second connection electrode 42 passes through the tenth via hole V10 It is connected to the first area of the fourth active layer, thus realizing the connection between the data signal line and the first pole of the fourth transistor, so that the data signal transmitted by the data signal line Data can be written into the fourth transistor.
  • FIG. 15I shows a schematic plan view of superimposing a second flat layer pattern on the basis of FIG. 15H. As shown in FIG. 15I , at least a fifteenth via hole V15 is provided on the second flat layer.
  • the fifteenth via hole V15 is located in the area where the anode connection electrode 51 is located, and the second flat layer in the fifteenth via hole V15 is removed to expose the surface of the anode connection electrode 51.
  • the hole V15 is configured such that a subsequently formed anode is connected to the anode connection electrode 51 through the via hole.
  • a sixth conductive layer pattern which is also the second metal layer in the embodiment of the present disclosure, can also be superimposed.
  • the sixth conductive layer pattern includes the above-mentioned plurality of first signal lines L1.
  • Figures 6 to 8 which will not be described again here.
  • the sixth conductive layer pattern overlaps the first electrode (anode) pattern.
  • the anode is connected to the anode connection electrode 51 through the fifteenth via hole V15. Since the anode connection electrode 51 is connected to the fourth connection electrode 44 through the twelfth via hole V12, the fourth connection electrode 44 is also connected to the second area of the sixth active layer (also the seventh active layer) through the ninth via hole V9. second area) connection, thereby realizing that the pixel circuit can drive the light-emitting element to emit light.
  • the display panel certainly includes other functional layers such as a luminescent material layer, a second electrode layer, and an encapsulation layer, which will not be described again here.
  • the display device can be: a mobile phone, a tablet computer, a television, a display Monitors, laptops, digital photo frames, navigators and other products or components with display functions.

Landscapes

  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，该显示基板具有显示区域(AA)，且包括衬底基板(110)、多个子像素、多条数据线(DT)和多条第一信号线(L1)，至少部分子像素的每个包括像素驱动电路和发光器件(EM)，发光器件(EM)包括与像素驱动电路电连接的第一电极(141)；多条数据线(DT)在第一金属层(M1)，多条第一信号线(L1)在第二金属层(M2)，第二金属层(M2)在第一金属层(M1)的远离衬底基板(110)的一侧；显示区域(AA)包括第一显示区域(AA1)，在第一显示区域(AA1)，多条第一信号线(L1)沿第一方向延伸，第一显示区域(AA1)包括多个第一补偿图案(S1)，第一电极位于多条第一信号线(L1)和多个第一补偿图案(S1)的远离衬底基板(110)的一侧，至少一个第一补偿图案(S1)在衬底基板(110)上的正投影与至少一个子像素的发光器件(EM)的第一电极(141)在衬底基板(110)上的正投影至少部分交叠。该显示基板具有更好的显示效果。

Description

显示基板
本申请要求于2022年03月30日递交的中国专利申请第202210334033.4号的优先权，在此出于所有目标全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。
对于OLED显示装置，边框的宽度是影响视觉效果的重要因素，通常来说，边框越窄，视觉效果越好。
发明内容
本公开至少一实施例提供一种显示基板，具有显示区域，所述显示区域包括衬底基板、多个子像素、多条数据线和多条第一信号线，多个子像素设置在所述衬底基板上，其中，所述多个子像素中至少部分子像素的每个包括像素驱动电路和发光器件，所述发光器件包括与所述像素驱动电路电连接的第一电极；多条数据线设置在所述衬底基板上，且设置在第一金属层，多条第一信号线设置在所述衬底基板上，且设置在第二金属层，所述第二金属层设置在所述第一金属层的远离所述衬底基板的一侧，所述多条第一信号线中的至少一条第一信号线通过第一过孔与所述多条数据线中的至少一条数据线电连接；其中，所述显示区域包括第一显示区域，在所述第一显示区域，所述多条第一信号线沿第一方向延伸，所述第一显示区域包括多个第一补偿图案，其中，在所述第一显示区域，所述多个子像素的发光器件的第一电极位于所述多条第一信号线和所述多个第一补偿图案的远离所述衬底基板的 一侧，所述多个第一补偿图案中的至少一个第一补偿图案在所述衬底基板上的正投影与所述多个子像素中的至少一个子像素的发光器件的第一电极在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第一补偿图案设置在所述第二金属层。
例如，本公开至少一实施例提供的显示基板中，所述显示区域还包括第二显示区域，在所述第二显示区域，所述多条第一信号线沿第二方向延伸，所述第二显示区域包括多个第二补偿图案，其中，在所述第二显示区域，所述多个子像素的发光器件的第一电极位于所述多条第一信号线和所述多个第二补偿图案的远离所述衬底基板的一侧，所述多个第二补偿图案中的至少一个第二补偿图案在所述衬底基板上的正投影与所述多个子像素中的至少一个子像素的发光器件的第一电极在所述衬底基板上的正投影至少部分交叠；所述第一方向不同于所述第二方向。
例如，本公开至少一实施例提供的显示基板中，所述第一方向垂直于所述第二方向。
例如，本公开至少一实施例提供的显示基板中，所述多条第一信号线分别通过多个第一过孔与所述多条数据线电连接，所述多个第一过孔位于所述第二显示区域，且呈直线排列，所述直线与所述第一方向和第二方向相交。
例如，本公开至少一实施例提供的显示基板中，在所述第二显示区域，所述多条第一信号线沿所述第二方向延伸至所述显示区域的边缘。
例如，本公开至少一实施例提供的显示基板中，在所述第二显示区域，所述多条第一信号线沿所述第二方向延伸至所述显示区域的边缘，并且在所述多个第一过孔的靠近所述边缘的一侧断开。
例如，本公开至少一实施例提供的显示基板中，所述多条第一信号线的在所述多个过孔的靠近所述边缘的一侧断开的部分分别与所述多条数据线电连接。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路与所述第一电极通过第二过孔电连接，在垂直于所述衬底基板的方向上，所述第二过孔与所述第一过孔不交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第一补偿图案和所述多个第二补偿图案分别呈一字形、十字形、田字形、米字形、环形或 者呈块状。
例如，本公开至少一实施例提供的显示基板中，所述多个第二补偿图案设置在所述第二金属层。
例如，本公开至少一实施例提供的显示基板中，在所述第一显示区域，所述多个第一补偿图案包括与所述多条第一信号线分别电连接且沿所述第二方向延伸的一字形第一补偿图案。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，所述红色子像素和所述蓝色子像素的发光器件位于同一行，所述绿色子像素的发光器件位于同一行，所述红色子像素和所述蓝色子像素的发光器件所在行与所述绿色子像素的发光器件所在行交替排布；所述红色子像素和所述蓝色子像素的发光器件位于同一列，所述绿色子像素的发光器件位于同一列，所述红色子像素和所述蓝色子像素的发光器件所在列与所述绿色子像素的发光器件所在列交替排布。
例如，本公开至少一实施例提供的显示基板中，在所述第一显示区域，在垂直于所述衬底基板的方向上，所述第一信号线与所述绿色子像素的发光器件至少部分交叠，所述第一信号线与所述红色子像素和所述蓝色子像素的发光器件不交叠。
例如，本公开至少一实施例提供的显示基板中，在所述第一显示区域，在垂直于所述衬底基板的方向上，所述绿色子像素的发光器件的第一电极与所述一字形第一补偿图案至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第一补偿图案还包括分别设置在所述多条第一信号线至少一侧的十字形第一补偿图案，所述十字形第一补偿图案包括分别沿所述第一方向和所述第二方向延伸的两个部分。
例如，本公开至少一实施例提供的显示基板中，所述十字形第一补偿图案与所述多条第一信号线间隔设置。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述红色子像素和所述蓝色子像素的发光器件的第一电极分别与一个十字形第一补偿图案交叠。
例如，本公开至少一实施例提供的显示基板中，在所述第二显示区域，所述多个第二补偿图案包括分别设置在所述多条第一信号线至少一侧的十 字形第二补偿图案，所述十字形第二补偿图案包括分别沿所述第一方向和所述第二方向延伸的两个部分；在垂直于所述衬底基板的方向上，所述绿色子像素、所述红色子像素和所述蓝色子像素的发光器件的第一电极分别与一个十字形第二补偿图案交叠。
例如，本公开至少一实施例提供的显示基板中，所述发光器件还包括设置在所述第一电极远离所述衬底基板一侧的发光材料层以及设置在所述发光材料层远离所述衬底基板一侧的第二电极；所述显示基板还具有围绕所述显示区域的周边区域，所述显示基板还包括第一电源信号线，所述第一电源信号线配置为向所述多个子像素的第二电极提供第一电源信号，且所述第一电源信号线在所述周边区域与所述多个子像素的第二电极电连接。
例如，本公开至少一实施例提供的显示基板中，在所述第二显示区域，所述十字形第二补偿图案与所述第一电源信号线电连接。
例如，本公开至少一实施例提供的显示基板中，所述显示基板还包括第二电源信号线，所述多条第一信号线设置在所述第二电源信号线的远离所述衬底基板的一侧，所述十字形第二补偿图案与所述第二电源信号线电连接。
例如，本公开至少一实施例提供的显示基板中，所述显示区域还包括第三显示区域，所述第三显示区域包括金属图案，所述多个子像素的发光器件的第一电极设置在所述金属图案的远离所述衬底基板的一侧，所述金属图案包括至少沿所述第一方向和所述第二方向延伸且交叉的多条金属线；或者，所述金属图案包括分别与所述多个子像素中的至少部分子像素的发光器件的第一电极交叠的多个块状图案。
例如，本公开至少一实施例提供的显示基板中，所述金属图案与所述多条第一信号线同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二显示区域包括第一子显示区域和第二子显示区域，所述第一显示区域在所述第一子显示区域和所述第二子显示区域之间。
例如，本公开至少一实施例提供的显示基板中，所述第三显示区域设置在所述第一显示区域和所述第二显示区域的一侧。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的平面示意图；
图2A为图1中的显示基板的第一子区域中的部分子像素的平面示意图；
图2B为图1中的显示基板的第二子区域中的部分子像素的平面示意图；
图3A为本公开至少一实施例提供的显示基板的平面示意图；
图3B为本公开至少一实施例提供的显示基板的另一平面示意图；
图4A为本公开至少一实施例提供的显示基板的一个子像素的部分截面示意图；
图4B为本公开至少一实施例提供的显示基板中第一信号线与数据线连接的部分截面示意图；
图5为本公开至少一实施例提供的显示基板的第一显示区域的部分子像素的平面示意图；
图6为本公开至少一实施例提供的显示基板的第二显示区域的部分子像素的平面示意图；
图7为本公开至少一实施例提供的显示基板的第三显示区域的部分子像素的平面示意图；
图8为本公开至少一实施例提供的显示基板的第二显示区域或第三显示区域的部分子像素的另一平面示意图；
图9为本公开至少一实施例提供的显示基板中的补偿图案的平面示意图；
图10为本公开至少一实施例提供的显示基板中的补偿图案的另一平面示意图；以及
图11为本公开至少一实施例提供的显示基板中的补偿图案的再一平面示意图；
图12-图14为本公开至少一实施例提供的显示基板中的补偿图案的多种示例性平面示意图；以及
图15A-图15I为本公开至少一实施例提供的显示基板中各个功能层依次叠层的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了一种显示基板的平面示意图，如图1所示，该显示基板具有显示区域A和围绕显示区域A的周边区域B。为了实现显示基板的大屏化、窄边框设计，周边区域B中的部分走线也可以设置在显示区域A，以减小周边区域B的面积，实现窄边框。例如，在一些实施例中，周边区域B的宽度可以减小为约1.0mm，由此可以实现极窄边框。
例如，如图1所示，显示区域A中设置有横向或者纵向延伸的多条走线，例如，显示区域A中不同区域的走线的延伸方向不同。
例如，如图1所示，显示区域A包括多个子区域，即第一子区域1、第二子区域2和第三子区域3。在显示区域A的第一子区域1中，走线沿纵向延伸，在第二子区域2中，走线沿横向延伸，第三子区域3中，走线沿横向延伸。通常，显示基板用于显示的发光器件设置在这些走线上方。
本公开的发明人在研究中发现，当发光器件设置在这些走线上方时，发光器件的至少部分结构，例如距离这些走线较近的电极(例如阳极)会不平坦，因此该发光器件发出的光在该不平坦的电极的反射下会不均匀，从而影响了显示基板的显示效果，例如会出现息屏Mura现象，在点亮时也会出现走线的痕迹。
例如，图2A示出了第一子区域1中的走线对发光器件的电极造成的影 响，图2B示出了第二子区域2中的走线对发光器件的电极造成的影响。如图2A和图2B所示，发光器件的电极C上会出现走线的痕迹。如图2A所示，在第一子区域1中，走线的痕迹纵向延伸，如图2A中的矩形框所示；如图2B所示，在第二子区域2中，走线的痕迹横向延伸，如图2B中的矩形框所示。
通过测试，该显示基板在暗态时会出现熄屏Mura，并且熄屏Mura的形状与走线的形状完全匹配；该显示基板在点亮时，电极下方存在明显的贯穿走线的痕迹，影响了显示基板的显示效果。
本公开至少一实施例提供一种显示基板，该显示基板具有显示区域，显示区域包括衬底基板、多个子像素、多条数据线和多条第一信号线，多个子像素设置在衬底基板上，多个子像素中至少部分子像素的每个包括像素驱动电路和发光器件，发光器件包括与像素驱动电路电连接的第一电极；多条数据线设置在衬底基板上，且设置在第一金属层，多条第一信号线设置在衬底基板上，且设置在第二金属层，第二金属层设置在第一金属层的远离衬底基板的一侧，多条第一信号线中的至少一条第一信号线通过第一过孔与多条数据线中的至少一条第一信号线电连接；显示区域包括第一显示区域，在所述第一显示区域，所述多条第一信号线沿第一方向延伸，第一显示区域包括多个第一补偿图案，在第一显示区域，多个子像素的发光器件的第一电极位于多条第一信号线和多个第一补偿图案的远离衬底基板的一侧，多个第一补偿图案中的至少一个第一补偿图案在衬底基板上的正投影与多个子像素中的至少一个子像素的发光器件的第一电极在衬底基板上的正投影至少部分交叠。
本公开实施例提供的上述显示基板中，第一补偿图案可以减弱甚至消除第一信号线对发光器件的第一电极造成的不平坦，进而可以避免显示基板在暗态时会出现的熄屏Mura现象、在点亮时出现显示不均匀的现象，提高显示基板的显示效果。
下面通过几个具体的实施例对本公开实施例提供的显示基板进行说明。
本公开至少一实施例提供一种显示基板，图3A示出了该显示基板的平面示意图，图4A示出了该显示基板的一个子像素的部分截面示意图。如图3A和图4A所示，该显示基板具有显示区域AA，该显示基板还包括衬底基板110、多个子像素以及多条第一信号线L1，多个子像素设置在衬底基板110 上，例如，多个子像素排布为多行多列的阵列。
如图3A和图4A所示，多个子像素中至少部分子像素的每个包括像素驱动电路和发光器件，像素驱动电路包括多个薄膜晶体管(图4A中示出第一薄膜晶体管T1和第二薄膜晶体管T2作为示例)和存储电容C等结构，例如可以形成为3T1C像素驱动电路(包括三个薄膜晶体管和一个存储电容)或者7T1C像素驱动电路(包括七个薄膜晶体管和一个存储电容)等，本公开的实施例对像素驱动电路的具体形式不做限定。
发光器件EM包括与像素驱动电路电连接的第一电极141，还包括与第一电极141间隔的第二电极143以及第一电极141和第二电极143之间的发光材料层142。像素驱动电路可以驱动发光器件EM进行发光。例如，第一电极141可以作为发光器件EM的阳极，第二电极143作为发光器件EM的阴极。发光材料层142可以包括有机发光材料，根据需要，不同的子像素可以包括发出不同颜色的有机发光材料。
如图3A和图4A所示，显示区域AA包括第一显示区域AA1，第一显示区域AA1包括多个第一补偿图案S1。例如，在第一显示区域AA1，多条第一信号线L1设置在衬底基板110上且沿第一方向(图3A中的竖直方向)延伸，多个第一补偿图案S1设置在衬底基板110上，且在平行于衬底基板110的方向上分别设置在多条第一信号线L1的至少一侧，例如位于多条第一信号线L1的一侧或者两侧。
如图4A所示，在第一显示区域AA1，多个子像素的发光器件EM的第一电极141位于多条第一信号线L1和多个第一补偿图案S1的远离衬底基板110的一侧，多个第一补偿图案S1中的至少一个第一补偿图案S1在衬底基板110上的正投影与多个子像素中的至少一个子像素的发光器件的第一电极141在衬底基板110上的正投影至少部分交；例如，在垂直于衬底基板110的方向(图4A中的竖直方向)上，多个第一补偿图案S1与多个子像素中的至少部分子像素的发光器件EM的第一电极141一一对应且至少部分交叠。
由此，在第一显示区域AA1，第一补偿图案S1可以至少部分垫高第一电极141，从而减弱甚至消除第一信号线L1对发光器件EM的第一电极141造成的不平坦，减弱甚至消除第一电极141不均匀导致的反光不均匀，进而可以避免显示基板在暗态时会出现的熄屏Mura现象、在点亮时出现显示不均匀的现象，提高显示基板的显示效果。
例如，图4B示出了该显示基板在第一过孔处的截面示意图，如图4B所示，该显示基板还包括多条数据线DT，多条数据线DT设置在衬底基板上，且设置在第一金属层M1，多条第一信号线L1设置在衬底基板上，且设置在第二金属层M2，第二金属层M2设置在第一金属层M1的远离衬底基板的一侧，多条第一信号线L1中的至少一条第一信号线L1通过第一过孔VH1与多条数据线DT中的至少一条数据线DT电连接，例如，多条第一信号线L1分别通过多个第一过孔VH1与多条数据线DT电连接。由此，多条第一信号线L1可以向多条数据线DT传输数据信号，进而向多个子像素提供数据信号。
例如，多个第一补偿图案S1设置在第二金属层M2，由此与多条第一信号线L1同层设置，因此在制备工艺中可以采用相同的材料层通过相同的构图工艺形成，由此可以简化显示基板的制备过程。
例如，在一些实施例中，如图3A和图4A所示，显示区域AA还包括第二显示区域AA2，第二显示区域AA2包括多个第二补偿图案S2，例如，在第二显示区域AA2，多条第一信号线L1设置在衬底基板110上且沿第二方向(图3A中的水平方向)延伸，多个第二补偿图案S2设置在衬底基板110上且在平行于衬底基板110的方向上分别设置在多条第一信号线L1的至少一侧，例如设置在多条第一信号线L1的一侧或者两侧。
例如，在第二显示区域AA2，多个子像素的发光器件EM的第一电极141位于多条第一信号线L1和多个第二补偿图案S2的远离衬底基板110的一侧，多个第二补偿图案中S2的至少一个第二补偿图案S2在衬底基板110上的正投影与多个子像素中的至少一个子像素的发光器件的第一电极141在衬底基板110上的正投影至少部分交叠；例如，在垂直于衬底基板110的方向上，多个第二补偿图案S2与多个子像素中的至少部分子像素的发光器件EM的第一电极141一一对应且至少部分交叠。
由此，在第二显示区域AA2，第二补偿图案S2可以至少部分垫高第一电极141，从而减弱甚至消除第一信号线L1对发光器件EM的第一电极141造成的不平坦，减弱甚至消除第一电极141不均匀导致的反光不均匀，进而可以避免显示基板在暗态时会出现的熄屏Mura现象、在点亮时出现显示不均匀的现象，提高显示基板的显示效果。
例如，上述第一方向不同于第二方向。例如，在一些实施例中，第一方 向垂直于第二方向。例如，在图3A示出的示例中，第一方向为竖直方向，即子像素的列方向，第二方向为水平方向，即子像素的行方向。在其他示例中，第一方向也可以为子像素的行方向，第二方向为子像素的列方向。
例如，在一些实施例中，多个第一补偿图案S1和多个第二补偿图案S2可以分别呈一字形、十字形、田字形、米字形、环形或者呈块状。多个第一补偿图案S1和多个第二补偿图案S2的形状可以相同或者不同。
例如，在一些实施例中，多个第二补偿图案S2也设置在第二金属层M2，也即多个第二补偿图案S2与多个第一补偿图案S1和第一信号线L1同层设置，以简化显示基板的制备工艺，并充分实现补偿图案对走线的补偿效果。
需要注意的是，在本公开的实施例中，“同层设置”为两个(或更多个)功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，如图3A所示，多个第一过孔VH1位于第二显示区域AA2，且呈直线排列，该直线与第一方向和第二方向相交，例如在图中体现为斜线。
例如，如图3A所示，在一些实施例中，在第二显示区域AA2，多条第一信号线L1沿第二方向延伸至显示区域AA的边缘(图中示出为左右两侧的边缘)。由此，第一信号线L1在制备过程中可以具有更好的刻蚀均匀性，避免不同长度的第一信号线L1带来制备过程的不均匀性，提高显示基板的良率。例如，第一信号线L1可以从显示区域AA下方设置的驱动电路FPC处获得数据信号，然后该数据信号在第一显示区域AA1沿第一方向传输，然后在第二显示区域AA2沿第二方向传输，之后传输给位于第一金属层M1的数据线DT，进而由数据线DT传输给各个子像素。
例如，在另一些实施例中，如图3B所示，在第二显示区域AA2，多条第一信号线L1沿第二方向延伸至显示区域的边缘，并且在多个第一过孔VH1的靠近显示区域的边缘的一侧断开。此时，第一信号线L1仍然可以从显示区域AA下方设置的驱动电路FPC处获得数据信号，然后将该数据信号传输给位于第一金属层M1的数据线DT，再由数据线DT传输给各个子像素。
例如，在一些实施例中，被断开的靠近显示区域AA边缘的部分信号线DT1可以悬置(floating)；或者，在一些实施例中，多条第一信号线L1的 在多个过孔VH1的靠近边缘的一侧断开的部分DT1可以分别与多条数据线DT电连接，由此为多条数据线DT并联一段信号线DT1，可以降低数据线DT的压降。
例如，在一些实施例中，像素驱动电路与第一电极141通过第二过孔VH2电连接，在垂直于衬底基板的方向上，第二过孔VH2与多个第一过孔VH1不交叠。也即，第二过孔VH2与第一过孔VH1采用避让设计，以避免显示基板在各个过孔附近出现制备不良等。
例如，图5示出了第一显示区域的部分子像素的平面示意图。如图5所示，在一些实施例中，多个子像素包括红色子像素R、绿色子像素G和蓝色子像素B，一个红色子像素R、两个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个像素单元在衬底基板110上排布为阵列。例如，在其他实施例中，也可以一个红色子像素R、一个绿色子像素G和一个蓝色子像素B组成一个像素单元，本公开的实施例对像素单元的具体组成不作限定。
例如，如图5所示，在一些实施例中，红色子像素R和蓝色子像素B的发光器件位于同一行，绿色子像素G的发光器件位于同一行，红色子像素R和蓝色子像素B的发光器件所在行与绿色子像素G的发光器件所在行交替排布。例如，红色子像素R和蓝色子像素B的发光器件位于同一列，绿色子像素G的发光器件位于同一列，红色子像素R和蓝色子像素B的发光器件所在列与绿色子像素G的发光器件所在列交替排布。
例如，如图5所示，在一些实施例中，在第一显示区域AA1，在垂直于衬底基板的方向上，第一信号线L1与绿色子像素G的发光器件至少部分交叠，第一信号线L1与红色子像素R和蓝色子像素B的发光器件不交叠。
例如，如图5所示，在一些实施例中，多个第一补偿图案S1包括与多条第一信号线L1分别电连接且沿第二方向延伸的一字形第一补偿图案S11。一字形第一补偿图案S11穿过第一信号线L1，从而包括分别位于第一信号线L1两侧的两个部分。
例如，在一些实施例中，在第一显示区域AA1，在垂直于衬底基板110的方向上，绿色子像素G的发光器件的第一电极141与第一信号线L1交叠，此时，一字形第一补偿图案S11可以至少部分垫高绿色子像素G的发光器件的第一电极，也即，一字形第一补偿图案S11设置在绿色子像素G的发光器件的第一电极的下方，从而在垂直于衬底基板110的方向上，绿色子像素G 的发光器件的第一电极与一字形第一补偿图案S11至少部分交叠。
例如，在一些实施例中，多个第一补偿图案S1还包括分别设置在多条第一信号线L1至少一侧的十字形第一补偿图案S12，十字形第一补偿图案S12包括分别沿第一方向和第二方向延伸的两个部分。例如，十字形第一补偿图案S12与多条第一信号线L1间隔设置，也即十字形第一补偿图案S12不与多条第一信号线L1电连接。
例如，在一些实施例中，如图5所示，在垂直于衬底基板110的方向上，第一信号线L1不与红色子像素R和蓝色子像素B的发光器件的第一电极141交叠，因此，十字形第一补偿图案S12可以用于垫高红色子像素R和蓝色子像素B的发光器件的第一电极141，也即红色子像素R和蓝色子像素B的发光器件的第一电极141分别与一个十字形第一补偿图案S12交叠。
由此，在第一显示区域11中，与绿色子像素G的发光器件的第一电极交叠的第一信号线L1和一字形第一补偿图案S11整体也呈十字形，因此，与绿色子像素G、红色子像素R和蓝色子像素B的发光器件的第一电极141交叠的补偿图案或走线的形状基本一致，从而各个颜色子像素的发光器件所处的表面具有基本相同的平整度，各个颜色子像素的发光器件的第一电极具有均匀的反光性，从而可以提高各个颜色子像素的发光器件的发光均匀性，进而提高显示基板的显示均匀性，提高显示基板的显示效果。
例如，图6示出了第二显示区域的部分子像素的平面示意图。如图6所示，在一些实施例中，在第二显示区域AA2，多个第二补偿图案S2包括分别设置在多条第一信号线L1至少一侧的十字形第二补偿图案S21，十字形第二补偿图案S21包括分别沿第一方向和第二方向延伸的两个部分。例如，在垂直于衬底基板110的方向上，绿色子像素G、红色子像素R和蓝色子像素B的发光器件的第一电极141分别与一个十字形第二补偿图案S21交叠。
由此，第二显示区域AA2中，各个颜色子像素的发光器件所处的表面具有基本相同的平整度，并且与第一显示区域AA1中的各个颜色子像素的发光器件所处的表面也具有基本相同的平整度，各个颜色子像素的发光器件的第一电极具有均匀的反光性，由此可以提高多个显示区域的显示均匀性。
例如，如图4A所示，发光器件EM的发光材料层142设置在第一电极141的远离衬底基板110的一侧，第二电极143设置在发光材料层142的远离衬底基板110的一侧。例如，显示基板还具有围绕显示区域AA的周边区 域NA，显示基板还包括第一电源信号线L22，第一电源信号线L22配置为向多个子像素的第二电极143提供第一电源信号，例如，第一电源信号为低电平电源信号。
例如，第一电源信号线L22在周边区域NA与多个子像素的第二电极143电连接，以为多个子像素的第二电极143提供低电平电源信号；第一电源信号线L22的设置可以有效降低电源压降(drop)，从而降低显示基板的功耗。
例如，在一些实施例中，在第二显示区域AA2，十字形第二补偿图案S21与第一电源信号线L22电连接，但不与提供数据信号的第一信号线L1电连接。例如，十字形第二补偿图案S21与第一电源信号线L22连接为一体，但与提供数据信号的第一信号线L1具有间隔。
例如，如图3A所示，显示区域AA还包括第三显示区域AA3，第三显示区域AA3包括金属图案L3，多个子像素的发光器件EM的第一电极141设置在金属图案L3的远离衬底基板110的一侧，金属图案L3包括至少沿第一方向和第二方向延伸且交叉的多条金属线(图3A示出的情况)，例如，多条金属线形成网格状；或者，在另一些实施例中，金属图案L3包括分别与多个子像素中的至少部分子像素的发光器件EM的第一电极131交叠的多个块状图案(稍后详细介绍)，此时，多个块状图案与至少部分子像素的发光器件EM的第一电极131一一对应且交叠。
例如，在一些实施例中，金属图案L3可以为虚设金属图案，不与任何电路电连接；或者，在另一些实施例中，金属图案L3中的部分为传输电信号的走线，例如传输低电平电源信号的走线等，另一部分为补偿图案。
例如，图7示出了第三显示区域的部分子像素的平面示意图。如图7所示，在一些实施例中，金属图案L3包括多条走线L31和多条走线L32，例如，多条走线L31与向多个子像素提供数据信号的数据线电连接，多条走线L32与向多个子像素的第二电极143提供第一电源信号，例如为低电平电源信号的第一电源信号线电连接，例如，金属图案L3还包括分别与走线L31和走线L32电连接的第三补偿图案S3。此时，数据线L31、第一电源信号线L32和第三补偿图案S3的整体呈交织的网状金属图案。
例如，如图7所示，每个第三补偿图案S3呈十字形，且在垂直于衬底基板110的方向上，绿色子像素G、红色子像素R和蓝色子像素B的发光器 件的第一电极141分别与一个十字形第三补偿图案S3交叠。
由此，第三显示区域AA3中，各个颜色子像素的发光器件所处的表面具有基本相同的平整度，并且与第一显示区域AA1和第二显示区域AA2中的各个颜色子像素的发光器件所处的表面也具有基本相同的平整度，各个颜色子像素的发光器件的第一电极具有均匀的反光性，由此可以提高多个显示区域的显示均匀性。
例如，在另一些实施例中，图8示出了显示基板中第二显示区域AA2或者第三显示区域AA3中的部分子像素的另一平面示意图。如图8所示，在第二显示区域AA2或者第三显示区域AA3中，显示基板还可以包括第二电源信号线L4，参考图4A，第二电源信号线L4例如与第一连接电极CE1(稍后详细介绍)或者源漏电极123和124同层设置。例如，第二电源信号线为提供高电平电源信号的电源线。
例如，在第二显示区域AA2，多条第一信号线L1设置在第二电源信号线L4的远离衬底基板110的一侧，此时，十字形第二补偿图案S21可以与第二电源信号线L4电连接，而不与多条第一信号线L1电连接。
例如，参考图4A和图8，在第二电源信号线L4与第一连接电极CE1同层设置的情况下，第二平坦化层PLN2中具有过孔V，十字形第二补偿图案S21通过过孔V与第二电源信号线L4电连接；或者，在第二电源信号线L4与源漏电极123和124同层设置的情况下，第一平坦化层PLN1和第二平坦化层PLN2中具有过孔V，十字形第二补偿图案S21通过过孔V与第二电源信号线L4电连接。
例如，在第三显示区域AA3，金属图案L3设置在第二电源信号线L4的远离衬底基板110的一侧，此时，金属图案L3可以与第二电源信号线L4电连接。例如，金属图案L3可以与第二电源信号线L4之间的平坦化层中具有过孔V，金属图案L3与第二电源信号线L4通过过孔V电连接。
例如，在一些实施例中，金属图案L3与多条第一信号线L1同层设置，也即设置在第二金属层M2，由此可以简化显示基板的制备工艺。
例如，在一些实施例中，如图3A所示，第二显示区域AA2可以包括第一子显示区域AA21和第二子显示区域AA22，第一显示区域AA1在第一子显示区域AA21和第二子显示区域AA22之间。例如，第一子显示区域AA21和第二子显示区域AA22具有基本相同的结构，且基本对称设置。
例如，如图3A所示，第三显示区域AA3设置在第一显示区域AA1和第二显示区域AA2的一侧，在图3A中示出为在第一显示区域AA1和第二显示区域AA3的上侧。
例如，在图5-图7的实施例中，以多个第一补偿图案S1和多个第二补偿图案S2分别呈一字形或者十字形为例进行了介绍，在其他实施例中，多个第一补偿图案S1和多个第二补偿图案S2也可以呈田字形、米字形或者呈块状等其他合适的图形。例如，块状可以呈矩形、正方形或者与第一电极141的图案基本一致的图形等，由此可以为第一电极141的设置提供基本平坦的表面。例如，用于不同颜色子像素的多个块状补偿图案的具体形状可以相同或者不相同。
例如，图9示出了第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈田字形的情形，图10示出了第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈米字形的情形，图11、图12和图13示出了第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈块状的情形，图14示出了第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈环形的情形。例如，在图11中，第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈矩形块状；在图12中，第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈第一电极141的形状基本形同的块状；在图13中，第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈圆形块状。在图14中，第一补偿图案S1、第二补偿图案S2或者第三补偿图案S3呈圆环形，在其他实施例中也可以呈矩形环形等。
这些补偿图案设置在第一电极下方均可以实现至少部分垫高第一电极，从而减弱甚至消除第一信号线L1对发光器件EM的第一电极141造成的不平坦，减弱甚至消除第一电极141不均匀导致的反光不均匀，从而提高显示基板的显示效果。例如，多个第一补偿图案S1的形状可以相同或者不相同，多个第二补偿图案S2形状可以相同或者不相同，多个第三补偿图案S3形状可以相同或者不相同。
例如，在一些实施例中，如图4A所示，像素驱动电路包括的第一薄膜晶体管T1和第二薄膜晶体管T2可以具有不同的结构。例如，第一薄膜晶体管T1包括有源层121、栅极122和源漏电极123和124。显示基板还包括位于源漏电极123和124远离衬底基板110一侧的第一连接电极CE1和位于第 一连接电极CE1远离衬底基板110一侧的第二连接电极CE2，源漏电极124通过第一连接电极CE1和第二连接电极CE2与发光器件EM的第一电极141电连接。例如，第二薄膜晶体管T2包括有源层131、第一栅极132、第二栅极133和源漏电极134和135，第二薄膜晶体管T2为双栅薄膜晶体管，在垂直于衬底基板110的方向上，第一栅极132和第二栅极133设置在有源层131的相对两侧。
例如，在一些实施例中，多条第一信号线L1和多个第一补偿图案S1、多个第二补偿图案S2以及金属图案L3与第二连接电极CE2同层设置，也即设置在第二金属层M2。
例如，像素驱动电路包括的存储电容C包括第一电容电极C1和第二电容电极C2。例如，第一电容电极C1与第一薄膜晶体管T1的栅极122同层设置，第二电容电极C2和第二薄膜晶体管T2的第一栅极132同层设置，以简化显示基板的制备工艺。
例如，在一些实施例中，显示基板还包括设置在衬底基板110与有源层121之间的遮光层SH，遮光层SH可以实现为有源层121遮光的效果，防止从衬底基板110射入的光照射到有源层121而影响第一薄膜晶体管T1的正常工作。
例如，显示基板还包括设置在衬底基板110上的阻挡层111和缓冲层112，阻挡层111和缓冲层112可以防止衬底基板110中的杂质进入到显示基板的多个功能层中，从而起到保护作用。
例如，本公开的实施例中，衬底基板110可以采用玻璃、石英等刚性基板或者聚酰亚胺等柔性基板。阻挡层111和缓冲层112可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。例如，缓冲层112可以具有多个子层，多个子层的材料可以相同也可以不同。例如，在一个示例中，一个子层的材料为氧化硅，另一个子层的材料为氮化硅等。
例如，遮光层SH可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料。遮光层SH上还可以设置绝缘层113和缓冲层114，绝缘层113和缓冲层114可以也采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。
例如，有源层121可以采用硅基半导体材料，例如非晶硅a-Si，多晶硅p-Si等。有源层131可以采用金属氧化物半导体材料，例如IGZO，ZnO， AZO，IZTO等。栅极122、第一栅极132、第二栅极133、第一电容电极C1和第二电容电极C2可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。源漏电极123和124以及源漏电极134和135可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。
例如，第一连接电极CE1和第二连接电极CE2以及各个走线、补偿图案可以采用铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)等金属材料或者合金材料，例如也可以形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。
例如，有源层与栅极之间、第一电容电极和第二电容电极之间可以设置栅绝缘层115，栅绝缘层115可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。例如，第二栅极133与源漏电极134和135之间可以设置层间绝缘层116，层间绝缘层116可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。
例如，源漏电极123和124以及源漏电极134和135上可以设置钝化层PVX，钝化层PVX上可以设置第一平坦化层PLN1，第一连接电极CE1上可以设置第二平坦化层PLN2，第二连接电极CE2上可以设置第三平坦化层PLN3。例如，钝化层PVX可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。第一平坦化层PLN1、第二平坦化层PLN2和第三平坦化层PLN3可以采用聚酰亚胺、树脂等有机绝缘材料。
例如，第一电极141包括高功函数的材料，以作为阳极，例如可以为ITO/Ag/ITO叠层结构；第二电极143包括低功函数的材料，以作为阴极，例如采用半透射的金属或金属合金材料，例如为Ag/Mg合金材料。发光材料层142除了包括有机发光材料外，例如还可以包括空穴传输层、空穴注入层、电极传输层、电子注入层等辅助发光层。
例如，如图4A所示，显示基板还包括设置在第一电极141上的像素界定层PDL以及设置在像素界定层PDL上的隔垫物层SP。像素界定层PDL包括多个子像素开口，用于限定子像素的发光区域。隔垫物层SP用于限定封装空间。例如，像素界定层PDL和隔垫物层SP可以采 用聚酰亚胺、树脂等有机绝缘材料。
例如，显示基板还可以包括设置在隔垫物层SP上的封装层(未示出)，封装层可以为复合封装层，包括多个有机封装层和无机封装层的叠层。例如，无机封装层可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料；有机封装层可以采用聚酰亚胺、树脂等有机绝缘材料。
例如，显示基板还可以包括除上述结构以外的其他结构，具体可以参考相关技术，这里不再赘述。
另外，需要说明的是，本公开的实施例对各功能层的材料不做限定，且各功能层的材料并不局限于上述示例。在本公开的实施例中，各薄膜晶体管可以为P型薄膜晶体管或者N型薄膜晶体管，结构可以为底栅型、顶栅型或者双栅型，附图中示出的结构仅仅是示例性的，本公开的实施例对各薄膜晶体管的具体形式不做限定。
例如，图15A-图15I示出了本公开至少一实施例提供的显示面板的各个功能层依次叠层的平面示意图，在该显示面板中，像素驱动电路采用8T1C结构，即包括八个薄膜晶体管T1-T8和一个存储电容。
图15A示出了第一半导体层图案。第一有源层薄膜可以采用硅材料，硅材料包括非晶硅和多晶硅。如图15A所示，第一半导体层图案可以包括第一晶体管T1的第一有源层10、第二晶体管T2的第二有源层20、第三晶体管T3的第三有源层30、第四晶体管T4的第四有源层40、第五晶体管T5的第五有源层50、第六晶体管T6的第六有源层60和第七晶体管T7的第七有源层70。第一有源层10、第二有源层20、第三有源层30、第四有源层40、第五有源层50、第六有源层60和第七有源层70为相互连接的一体结构。
在一些示例性实施方式中，第三有源层30的形状可以呈“几”字形，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的形状可以呈“1”字形。
在一些示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在一些示例性实施方式中，第一有源层10的第二区102同时作为第二有源层20的第一区201，即第一有源层10的第二区102和第二有源层20的第一区201之间相互连接。第三有源层30的第一区301同时作为第四有源层40的第二区402和第五有源层50的第二区502，即第三有源层30的第一区301、第四有源层40的第二区402 和第五有源层50的第二区502之间相互连接。第三有源层30的第二区302同时作为第六有源层60的第一区601和第二有源层20的第二区202，即第三有源层30的第二区302、第六有源层60的第一区601和第二有源层20的第二区202之间相互连接。第六有源层60的第二区602同时作为第七有源层70的第二区702，即第六有源层60的第二区602和第七有源层70的第二区702之间相互连接。第一有源层10的第一区101、第四有源层40的第一区401、第五有源层50的第一区501和第七有源层70的第一区701单独设置。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第一半导体层为镜像对称结构。
在一些示例性实施方式中，第三有源层30的沟道区沿行方向延伸，第一有源层10、第二有源层20、第四有源层40、第五有源层50、第六有源层60和第七有源层70的沟道区沿列方向延伸。
在一些示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管可以均为LTPS薄膜晶体管。
例如，图15B示出了第一半导体层图案上叠加第一导电层图案的平面示意图。在一些示例性实施方式中，如图15B所示，第一导电层图案至少包括：第一扫描信号线Gate_P、复位控制信号线Reset_P、发光控制信号线EM_P和存储电容的第一极板Ce1。在一些示例性实施方式中，第一导电层可以称为第一栅金属(GATE 1)层。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第一导电层为镜像对称结构。
在一些示例性实施方式中，第一扫描信号线Gate_P、复位控制信号线Reset_P和发光控制信号线EM_P均沿第二方向。在每个子像素内，复位控制信号线Reset_P位于第一扫描信号线Gate_P远离发光控制信号线EM_P的一侧，存储电容的第一极板Ce1设置在第一扫描信号线Gate_P和发光控制信号线EM_P之间。
在一些示例性实施方式中，第一极板Ce1可以为矩形状，矩形状的角部可以设置倒角，第一极板Ce1在基底基板上的正投影与第三晶体管T3的第 三有源层30在基底基板上的正投影存在重叠区域。在一些示例性实施方式中，第一极板Ce1同时作为第三晶体管T3的栅电极，第三晶体管T3的第三有源层30与第一极板Ce1相重叠的区域作为第三晶体管T3的沟道区，沟道区的一端连接第三有源层30的第一区，另一端连接第三有源层30的第二区。
在一些示例性实施方式中，复位控制信号线Reset_P与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1的栅电极，第一扫描信号线Gate_P与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线Gate_P与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅电极，发光控制信号线EM_P与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制信号线EM_P与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅电极。每行子像素的下一行子像素中的复位控制信号线Reset_P(与本行子像素中的第一扫描信号线Gate_P的信号相同)与本行子像素中的第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在显示面板的制备过程中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成各个晶体管的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即各个有源层的第一区和第二区均被导体化。
图15C示出了在图15B的基础上叠加第二导电层图案的平面示意图。在一些示例性实施方式中，如图15C所示，第二导电层图案至少包括：存储电容的第二极板Ce2和第二扫描信号线GateN的第一分支GateN_B1。在一些示例性实施方式中，第二导电层可以称为第二栅金属(GATE 2)层。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第二导电层为镜像对称结构。
在一些示例性实施方式中，第二扫描信号线GateN的第一分支GateN_B1沿第二方向延伸。在每个子像素内，存储电容的第二极板Ce2位于第二扫描信号线GateN的第一分支GateN_B1和发光控制信号线EM_P之间。
在一些示例性实施方式中，第二极板Ce2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板Ce2在衬底基板上的正投影与第一极板Ce1 在衬底基板上的正投影存在重叠区域。第二极板Ce2上设置有开口H，开口H可以位于第二极板Ce2的中部。开口H可以为正六边形，使第二极板Ce2形成环形结构。在一些示例性实施方式中，开口H配置为容置后续形成的第四过孔，第四过孔位于开口H内并暴露出第一极板Ce1，使后续形成的第八晶体管T8的第二极与第一极板Ce1连接。
图15D示出了在图15C的基础上叠加第二半导体层图案的平面示意图。在一些示例性实施方式中，如图15D所示，每个子像素的第二半导体层可以包括第八晶体管T8的第八有源层80。在一些示例性实施方式中，第八有源层80沿第一方向延伸，第八有源层80的形状可以呈哑铃形。在第一方向上，任意相邻两列子像素的第二半导体层为镜像对称结构。
在一些示例性实施方式中，第八有源层80的第一区801与第一晶体管T1的第一有源层邻近，第八有源层80的第二区802与第一电容C1邻近。
在一些示例性实施方式中，第二半导体层可以采用氧化物，即第八晶体管为氧化物薄膜晶体管。
图15E示出了在图15D的基础上叠加第三导电层图案的平面示意图。在一些示例性实施方式中，如图15E所示，第三导电层图案至少包括：第二扫描信号线GateN的第二分支GateN_B2和第二初始信号线INIT2。在一些示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第三导电层为镜像对称结构。
在一些示例性实施方式中，第二扫描信号线GateN的第二分支GateN_B2沿第二方向延伸，第二扫描信号线GateN的第二分支GateN_B2与第一扫描信号线Gate的第二分支Gate_B2靠近。在一些示例性实施方式中，第二扫描信号线GateN的第二分支GateN_B2与第八有源层80重叠的区域作为第八晶体管的栅电极。
在一些示例性实施方式中，第二扫描信号线的第二分支GateN_B2在衬底基板上的正投影与第二扫描信号线的第一分支GateN_B1在衬底基板上的正投影交叠。在一些示例性实施方式中，第二扫描信号线的第一分支GateN_B1与第二扫描信号线的第二分支GateN_B2可以在周边区域通过信号线连接。
在一些示例性实施方式中，第二初始信号线INIT2沿第二方向延伸，在每行子像素内，第二初始信号线INIT2设置在复位控制信号线Reset_P远离第一扫描信号线Gate_P的一侧。
图15F示出了在图15E的基础上形成了多个过孔的平面示意图。在一些示例性实施方式中，在图15E的图案上以及相邻的导电层之间形成有绝缘层，该绝缘层中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在一些示例性实施方式中，第一过孔V1暴露出第八有源层80的第二区的表面。第二过孔V2暴露出第八有源层80的第一区的表面。第三过孔V3暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第三过孔V3配置为使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接，以及使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接。
在一些示例性实施方式中，第四过孔V4位于第二极板Ce2的开口H内，第四过孔V4在衬底基板上的正投影位于开口H在衬底基板上的正投影的范围之内，第四过孔V4暴露出第一极板Ce1的表面。第四过孔V4配置为使后续形成的第三连接电极43与通过该过孔与第一极板Ce1连接。
在一些示例性实施方式中，第五过孔V5暴露出第五有源层的第一区的表面。第五过孔V5配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层连接。
在一些示例性实施方式中，第六过孔V6位于第二极板Ce2所在区域，第六过孔V6在衬底基板上的正投影位于第二极板Ce2在衬底基板上的正投影的范围之内，第六过孔V6暴露出第二极板Ce2的表面。第六过孔V6配置为使后续形成的第五连接电极45通过该过孔与第二极板Ce2连接。
在一些示例性实施方式中，第七过孔V7暴露出第一有源层的第一区的表面。第七过孔V7配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在一些示例性实施方式中，第八过孔V8暴露出第七有源层的第一区的表面。第八过孔V8配置为使后续形成的第一初始信号线通过该过孔与第七 有源层连接。
在一些示例性实施方式中，第九过孔V9暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第九过孔V9配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在一些示例性实施方式中，第十过孔V10暴露出第四有源层的第一区的表面。第十过孔V10配置为使后续形成的第二连接电极42通过该过孔与第四有源层连接。
在一些示例性实施方式中，第十一过孔V11暴露出第二初始信号线INIT2的表面。第十一过孔V11配置为使后续形成的第六连接电极46通过该过孔与第二初始信号线INIT2连接。
图15G示出了在图15F的基础上叠加第四导电层图案的平面示意图。如图15G所示，第四导电层至少包括：第一初始信号线INIT1、第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45和第六连接电极46。在一些示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第四导电层为镜像对称结构。
在一些示例性实施方式中，第一初始信号线INIT1沿着第二方向延伸，第一初始信号线INIT1通过第八过孔V8与第七有源层的第一区连接，使第七晶体管T7的第一极与第一初始信号线INIT1具有相同的电位。
在一些示例性实施方式中，第一连接电极41的一端通过第三过孔V3与第二有源层的第一区(也是第一有源层的第二区)连接，另一端通过第二过孔V2与第八有源层的第一区连接。在一些示例性实施方式中，第一连接电极41可以作为第八晶体管T8的第一极、第二晶体管的第一极和第一晶体管的第二极。
在一些示例性实施方式中，第二连接电极42一方面通过第十过孔V10与第四有源层的第一区连接，另一方面通过后续形成的第十三过孔V13与后续形成的数据信号线Data连接。在一些示例性实施方式中，第二连接电极42可以作为第四晶体管T4的第一极。
在一些示例性实施方式中，第三连接电极43的一端通过第一过孔V1与第八有源层的第二区连接，其另一端通过第四过孔V4与第一极板Ce1连接。在一些示例性实施方式中，第三连接电极43可以作为第八晶体管T8的第二极。
在一些示例性实施方式中，第四连接电极44一方面通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)，另一方面，通过后续形成的第十二过孔V12与后续形成的阳极连接电极连接。在一些示例性实施方式中，第四连接电极44可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极。
在一些示例性实施方式中，第五连接电极45(电源连接电极)，一方面通过第六过孔V6与第二极板Ce2连接，另一方面通过第五过孔V5与第五有源层的第一区连接，第五连接电极45配置为通过后续形成的第十四过孔V14与后续形成的第一电源线VDD连接。
在一些示例性实施方式中，第六连接电极46的一端通过第七过孔V7与第一有源层的第一区连接，另一端通过第十一过孔V11与第二初始信号线连接，使第一晶体管T1的第一极与第二初始信号线INIT2具有相同的电位。
图15H示出了在图15G的基础上叠加第一平坦层和第五导电层图案的平面示意图。如图15H所示，第一平坦层至少包括：第十二过孔V12、第十三过孔V13和第十四过孔V14，第五导电层至少包括：数据信号线Data、第一电源线VDD和阳极连接电极51。在一些示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层，也是本公开实施例中的第一金属层，数据信号线Data即为上述数据线DT。
在一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第五导电层为镜像对称结构。在另一些示例性实施方式中，在第一方向上，任意相邻两列子像素的第五导电层也可以不为镜像对称结构，可以根据需要增加第二开口或第三开口下方的第二源漏金属层的面积，以增加上层形成的阳极的平坦度，使得子像素整体位于一个平面上，从而可以降低色偏，提高显示质量。
在一些示例性实施方式中，如图15H所示，在一个重复单元内，相邻两列子像素中的第一电源线VDD可以为相互连接的一体结构。通过使相邻两 列子像素中的第一电源线VDD形成相互连接的一体结构，可以使上层形成的阳极更加平坦。
在一些示例性实施方式中，阳极连接电极51可以为矩形状，阳极连接电极51通过第十二过孔V12与第四连接电极44连接。
在一些示例性实施方式中，第一电源线VDD通过第十四过孔V14与第五连接电极45连接。
在一些示例性实施方式中，数据信号线Data沿着第一方向延伸，数据信号线Data通过第十三过孔V13与第二连接电极42连接，由于第二连接电极42通过第十过孔V10与第四有源层的第一区连接，因而实现了数据信号线与第四晶体管的第一极的连接，使数据信号线Data传输的数据信号可以写入第四晶体管。
图15I示出了在图15H的基础上叠加第二平坦层图案的平面示意图。如图15I所示，第二平坦层上至少设置有第十五过孔V15。
在一些示例性实施方式中，第十五过孔V15位于阳极连接电极51所在区域，第十五过孔V15内的第二平坦层被去掉，暴露出阳极连接电极51的表面，第十五过孔V15配置为使后续形成的阳极通过该过孔与阳极连接电极51连接。
例如，在图15I的基础上，还可以叠加第六导电层图案，也是本公开实施例中的第二金属层。第六导电层图案包括上述多条第一信号线L1，具体可参考图6-图8，这里不再赘述。
例如，第六导电层图案叠加第一电极(阳极)图案。在一些示例性实施方式中，阳极通过第十五过孔V15与阳极连接电极51连接。由于阳极连接电极51通过第十二过孔V12与第四连接电极44连接，第四连接电极44还通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了像素电路可以驱动发光元件发光。
显示面板上当然包括发光材料层、第二电极层以及封装层等其他功能层，这里不再赘述。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一的显示基板。例如，该显示装置可以为：手机、平板电脑、电视机、显 示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (26)

  1. 一种显示基板，其特征在于，具有显示区域，所述显示区域包括：
    衬底基板，
    多个子像素，设置在所述衬底基板上，其中，所述多个子像素中至少部分子像素的每个包括像素驱动电路和发光器件，所述发光器件包括与所述像素驱动电路电连接的第一电极，
    多条数据线，设置在所述衬底基板上，且设置在第一金属层，以及
    多条第一信号线，设置在所述衬底基板上，且设置在第二金属层，所述第二金属层设置在所述第一金属层的远离所述衬底基板的一侧，所述多条第一信号线中的至少一条第一信号线通过第一过孔与所述多条数据线中的至少一条数据线电连接；
    其中，所述显示区域包括第一显示区域，在所述第一显示区域，所述多条第一信号线沿第一方向延伸，所述第一显示区域包括多个第一补偿图案，
    其中，在所述第一显示区域，所述多个子像素的发光器件的第一电极位于所述多条第一信号线和所述多个第一补偿图案的远离所述衬底基板的一侧，所述多个第一补偿图案中的至少一个第一补偿图案在所述衬底基板上的正投影与所述多个子像素中的至少一个子像素的发光器件的第一电极在所述衬底基板上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其特征在于，所述多个第一补偿图案设置在所述第二金属层。
  3. 根据权利要求1或2所述的显示基板，其特征在于，所述显示区域还包括第二显示区域，在所述第二显示区域，所述多条第一信号线沿第二方向延伸，所述第二显示区域包括第二补偿图案，
    其中，在所述第二显示区域，所述多个子像素的发光器件的第一电极位于所述多条第一信号线和所述多个第二补偿图案的远离所述衬底基板的一侧，所述多个第二补偿图案中的至少一个第二补偿图案在所述衬底基板上的正投影与所述多个子像素中的至少一个子像素的发光器件的第一电极在所述衬底基板上的正投影至少部分交叠；
    所述第一方向不同于所述第二方向。
  4. 根据权利要求3所述的显示基板，其特征在于，所述第一方向垂直 于所述第二方向。
  5. 根据权利要求3或4所述的显示基板，其特征在于，所述多条第一信号线分别通过多个第一过孔与所述多条数据线电连接，所述多个第一过孔位于所述第二显示区域，且呈直线排列，所述直线与所述第一方向和第二方向相交。
  6. 根据权利要求3-5任一所述的显示基板，其特征在于，在所述第二显示区域，所述多条第一信号线沿所述第二方向延伸至所述显示区域的边缘。
  7. 根据权利要求3-5任一所述的显示基板，其特征在于，在所述第二显示区域，所述多条第一信号线沿所述第二方向延伸至所述显示区域的边缘，并且在所述多个第一过孔的靠近所述边缘的一侧断开。
  8. 根据权利要求7所述的显示基板，其特征在于，所述多条第一信号线的在所述多个过孔的靠近所述边缘的一侧断开的部分分别与所述多条数据线电连接。
  9. 根据权利要求1-8任一所述的显示基板，其特征在于，所述像素驱动电路与所述第一电极通过第二过孔电连接，在垂直于所述衬底基板的方向上，所述第二过孔与所述第一过孔不交叠。
  10. 根据权利要求3-8任一所述的显示基板，其特征在于，所述多个第一补偿图案和所述多个第二补偿图案分别呈一字形、十字形、田字形、米字形、环形或者呈块状。
  11. 根据权利要求3-8任一所述的显示基板，其特征在于，所述多个第二补偿图案设置在所述第二金属层。
  12. 根据权利要求3-8任一所述的显示基板，其特征在于，在所述第一显示区域，所述多个第一补偿图案包括与所述多条第一信号线分别电连接且沿所述第二方向延伸的一字形第一补偿图案。
  13. 根据权利要求12所述的显示基板，其特征在于，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    所述红色子像素和所述蓝色子像素的发光器件位于同一行，所述绿色子像素的发光器件位于同一行，所述红色子像素和所述蓝色子像素的发光器件所在行与所述绿色子像素的发光器件所在行交替排布；
    所述红色子像素和所述蓝色子像素的发光器件位于同一列，所述绿色子 像素的发光器件位于同一列，所述红色子像素和所述蓝色子像素的发光器件所在列与所述绿色子像素的发光器件所在列交替排布。
  14. 根据权利要求13所述的显示基板，其特征在于，在所述第一显示区域，在垂直于所述衬底基板的方向上，所述第一信号线与所述绿色子像素的发光器件至少部分交叠，所述第一信号线与所述红色子像素和所述蓝色子像素的发光器件不交叠。
  15. 根据权利要求14所述的显示基板，其特征在于，
    在所述第一显示区域，在垂直于所述衬底基板的方向上，所述绿色子像素的发光器件的第一电极与所述一字形第一补偿图案至少部分交叠。
  16. 根据权利要求14或15所述的显示基板，其特征在于，所述多个第一补偿图案还包括分别设置在所述多条第一信号线至少一侧的十字形第一补偿图案，
    所述十字形第一补偿图案包括分别沿所述第一方向和所述第二方向延伸的两个部分。
  17. 根据权利要求16所述的显示基板，其特征在于，所述十字形第一补偿图案与所述多条第一信号线间隔设置。
  18. 根据权利要求16或17所述的显示基板，其特征在于，在垂直于所述衬底基板的方向上，所述红色子像素和所述蓝色子像素的发光器件的第一电极分别与一个十字形第一补偿图案交叠。
  19. 根据权利要求13-18任一所述的显示基板，其特征在于，在所述第二显示区域，所述多个第二补偿图案包括分别设置在所述多条第一信号线至少一侧的十字形第二补偿图案，所述十字形第二补偿图案包括分别沿所述第一方向和所述第二方向延伸的两个部分；
    在垂直于所述衬底基板的方向上，所述绿色子像素、所述红色子像素和所述蓝色子像素的发光器件的第一电极分别与一个十字形第二补偿图案交叠。
  20. 根据权利要求3-8和10-19任一所述的显示基板，其特征在于，所述发光器件还包括设置在所述第一电极远离所述衬底基板一侧的发光材料层以及设置在所述发光材料层远离所述衬底基板一侧的第二电极；
    所述显示基板还具有围绕所述显示区域的周边区域，
    所述显示基板还包括第一电源信号线，所述第一电源信号线配置为向所 述多个子像素的第二电极提供第一电源信号，且所述第一电源信号线在所述周边区域与所述多个子像素的第二电极电连接。
  21. 根据权利要求20所述的显示基板，其特征在于，在所述第二显示区域，所述十字形第二补偿图案与所述第一电源信号线电连接。
  22. 根据权利要求20或21所述的显示基板，其特征在于，所述显示基板还包括第二电源信号线，所述多条第一信号线设置在所述第二电源信号线的远离所述衬底基板的一侧，所述十字形第二补偿图案与所述第二电源信号线电连接。
  23. 根据权利要求1-22任一所述的显示基板，其特征在于，所述显示区域还包括第三显示区域，所述第三显示区域包括金属图案，所述多个子像素的发光器件的第一电极设置在所述金属图案的远离所述衬底基板的一侧，
    所述金属图案包括至少沿所述第一方向和所述第二方向延伸且交叉的多条金属线；或者，所述金属图案包括分别与所述多个子像素中的至少部分子像素的发光器件的第一电极交叠的多个块状图案。
  24. 根据权利要求23所述的显示基板，其特征在于，所述金属图案与所述多条第一信号线同层设置。
  25. 根据权利要求1-24任一所述的显示基板，其特征在于，所述第二显示区域包括第一子显示区域和第二子显示区域，所述第一显示区域在所述第一子显示区域和所述第二子显示区域之间。
  26. 根据权利要求25所述的显示基板，其特征在于，所述第三显示区域设置在所述第一显示区域和所述第二显示区域的一侧。
PCT/CN2023/083397 2022-03-30 2023-03-23 显示基板 WO2023185630A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210334033.4 2022-03-30
CN202210334033.4A CN116940175A (zh) 2022-03-30 2022-03-30 显示基板

Publications (2)

Publication Number Publication Date
WO2023185630A1 true WO2023185630A1 (zh) 2023-10-05
WO2023185630A9 WO2023185630A9 (zh) 2023-11-16

Family

ID=88199243

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/083397 WO2023185630A1 (zh) 2022-03-30 2023-03-23 显示基板

Country Status (2)

Country Link
CN (1) CN116940175A (zh)
WO (1) WO2023185630A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257885A (zh) * 2021-07-07 2021-08-13 北京京东方技术开发有限公司 显示面板和显示装置
WO2021217296A1 (zh) * 2020-04-26 2021-11-04 京东方科技集团股份有限公司 显示基板以及显示装置
CN113707704A (zh) * 2021-09-02 2021-11-26 京东方科技集团股份有限公司 显示基板和显示装置
US20210408203A1 (en) * 2019-07-31 2021-12-30 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210408203A1 (en) * 2019-07-31 2021-12-30 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display device
WO2021217296A1 (zh) * 2020-04-26 2021-11-04 京东方科技集团股份有限公司 显示基板以及显示装置
CN113257885A (zh) * 2021-07-07 2021-08-13 北京京东方技术开发有限公司 显示面板和显示装置
CN113707704A (zh) * 2021-09-02 2021-11-26 京东方科技集团股份有限公司 显示基板和显示装置

Also Published As

Publication number Publication date
CN116940175A (zh) 2023-10-24
WO2023185630A9 (zh) 2023-11-16

Similar Documents

Publication Publication Date Title
KR102423800B1 (ko) 박막 트랜지스터 기판 및 이를 이용한 표시장치
US11600234B2 (en) Display substrate and driving method thereof
WO2022057491A1 (zh) 显示基板及其制备方法、显示装置
KR102302362B1 (ko) 박막 트랜지스터 기판 및 이를 이용한 표시장치
KR102424108B1 (ko) 박막 트랜지스터 기판 및 이를 이용한 표시장치
US20210366393A1 (en) Display substrate and display device
KR102326170B1 (ko) 박막 트랜지스터 기판 및 그 제조 방법
KR102142481B1 (ko) 유기전계 발광소자
KR102181825B1 (ko) 박막 트랜지스터 기판 및 이를 이용한 표시장치
WO2022042046A1 (zh) 显示基板及其制备方法、显示装置
JP2019121598A (ja) 上部発光型有機発光ダイオード表示装置
KR20150101418A (ko) 표시장치
KR102346544B1 (ko) 박막 트랜지스터 기판 및 이를 이용한 표시장치
WO2022188442A1 (zh) 显示面板及显示装置
US20230030745A1 (en) Display substrate and display apparatus
US20220376003A1 (en) Display panel and display apparatus
CN113964109A (zh) 显示基板及其制备方法、显示装置
EP4307860A1 (en) Display substrate and display apparatus
US20230189596A1 (en) Display panel and display device
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2023185630A1 (zh) 显示基板
US11296153B2 (en) OLED pixel structure and OLED display panel
CN219999921U (zh) 显示基板
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置
WO2023226050A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23777999

Country of ref document: EP

Kind code of ref document: A1