WO2024000317A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024000317A1
WO2024000317A1 PCT/CN2022/102512 CN2022102512W WO2024000317A1 WO 2024000317 A1 WO2024000317 A1 WO 2024000317A1 CN 2022102512 W CN2022102512 W CN 2022102512W WO 2024000317 A1 WO2024000317 A1 WO 2024000317A1
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WO
WIPO (PCT)
Prior art keywords
light
layer
emitting device
emitting
electrode
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Application number
PCT/CN2022/102512
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English (en)
French (fr)
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WO2024000317A9 (zh
Inventor
李硕
石领
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102512 priority Critical patent/WO2024000317A1/zh
Priority to CN202280002014.XA priority patent/CN117652225A/zh
Publication of WO2024000317A1 publication Critical patent/WO2024000317A1/zh
Publication of WO2024000317A9 publication Critical patent/WO2024000317A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a display panel and a display device.
  • OLED (organic electroluminescent diode) display panels have the advantages of self-illumination, wide color gamut, high contrast, flexibility, high response and flexibility, etc., and have broad application prospects.
  • current display panels have phenomena such as color separation and color cast that affect the display effect.
  • the present disclosure provides a display panel and a display device.
  • a display panel including:
  • the driving backplane includes a substrate, a circuit layer, a wiring layer and a first flat layer sequentially stacked in a direction away from the substrate;
  • the circuit layer includes a plurality of pixel circuits distributed in an array;
  • the wiring layer includes Data lines and power lines are distributed along the row direction, and one of the data lines and one of the power lines are connected to one column of the pixel circuits; the width of the power lines is larger than that of the data lines;
  • the power lines are provided along the A plurality of through holes distributed in the column direction, the through holes are provided with transfer parts on the same layer and spaced apart from the power lines, and one of the transfer parts is connected to one of the pixel circuits;
  • a plurality of light-emitting devices are arrayed on a side of the first flat layer away from the substrate and connected to the pixel circuit;
  • the light-emitting devices include first electrodes stacked sequentially in a direction away from the substrate , a light-emitting layer and a second electrode;
  • the light-emitting device includes at least two light-emitting devices with different light-emitting colors; at least part of the light-emitting device overlaps with the area of the power line where the through hole is not provided;
  • An anti-reflective layer is provided on the side of the light-emitting device away from the substrate, and includes a plurality of filter parts distributed in an array, one of the filter parts overlaps with one of the light-emitting devices; the filter part The color is the same as the color of the overlapping light-emitting device.
  • each of the data lines and power lines are alternately distributed along the row direction; one power line overlaps a column of the light-emitting devices, and two adjacent data lines A row of the light-emitting devices is arranged therebetween; among the overlapping light-emitting devices and the power lines, at least part of the boundaries of the light-emitting devices are located within the boundaries of the overlapping power lines.
  • each of the light-emitting devices is arranged in a plurality of device columns along the row direction, and the light-emitting devices of one device column overlap one of the power lines.
  • the light-emitting device includes a first light-emitting device of a first color, a second light-emitting device of a second color, and a third light-emitting device of a third color;
  • the range of the first light-emitting device is larger than that of the second light-emitting device and the third light-emitting device, and the boundary of at least one of the second light-emitting device and the third light-emitting device is located within the boundary of the power line overlapping it.
  • each of the device columns includes a first device column and a second device column alternately distributed along the row direction; the first device column includes a first device column alternately distributed along the column direction. the first light-emitting device and the second light-emitting device, and the second device column includes the third light-emitting device.
  • the first electrode includes an electrode body and an electrode connection portion extending outward from the electrode body, and one of the electrode connection portions passes through a contact penetrating the first planar layer.
  • the hole is connected to one of the pixel circuits;
  • the display panel also includes:
  • a pixel definition layer is provided on a side of the first flat layer away from the substrate, and is provided with a plurality of openings for defining the range of the light-emitting device, one of the openings exposes one of the electrode bodies, and The boundary of the opening is located within the boundary of the exposed electrode body;
  • the distance between the contact hole connected to the electrode connecting portion connected to the exposed electrode body through the opening is the offset distance of the light-emitting device defined by the opening;
  • the offset distance of the first light-emitting device is 2.9 ⁇ m-3 ⁇ m; the offset distance of the second light-emitting device is 6.5 ⁇ m-6.6 ⁇ m; and the offset distance of the third light-emitting device is 5.2 ⁇ m-5.3 ⁇ m.
  • the data lines are divided into multiple data line groups, and one data line group includes two data lines; the power line is divided into multiple power line groups, A power cord set includes two power cords, and the two power cords are an integrated structure; the data cord set and the power cord set are alternately distributed along the row direction; a power cord set The two columns of pixel circuits connected by the two power lines are arranged symmetrically about the central axis of the two power lines;
  • At least part of the boundary of the light-emitting device is located within the boundary of the power line group, and at most part of the light-emitting device overlaps the data line group.
  • each of the light-emitting devices is arranged in a plurality of device columns along the row direction, and the light-emitting devices of some of the device columns overlap with one of the power line groups, and some of the light-emitting devices of the device columns overlap with one of the power line groups.
  • the light-emitting devices of the device column overlap with the data line group.
  • the light-emitting device includes a first light-emitting device of a first color, a second light-emitting device of a second color, and a third light-emitting device of a third color;
  • the range of the first light-emitting device is larger than that of the second light-emitting device and the third light-emitting device, the boundary of the first light-emitting device is located within the boundary of the power line group overlapping it, the second light-emitting device and the third light-emitting device At most one of the light emitting devices overlaps the data line group.
  • each of the device columns includes a first device column and a second device column alternately distributed along the row direction; the first device column includes a first device column alternately distributed along the column direction.
  • the boundary of the light-emitting devices of the first device column is located within the boundary of the power line group overlapping therewith; the light-emitting devices of the second device column overlap with the data line group.
  • the first electrode includes an electrode body and an electrode connection portion extending outward from the electrode body, and one of the electrode connection portions passes through a contact penetrating the first planar layer.
  • the hole is connected to one of the pixel circuits;
  • the display panel also includes:
  • a pixel definition layer is provided on a side of the first flat layer away from the substrate, and is provided with a plurality of openings for defining the range of the light-emitting device, one of the openings exposes one of the electrode bodies, and The boundary of the opening is located within the boundary of the exposed electrode body;
  • the distance between the contact hole connected to the electrode connecting portion connected to the exposed electrode body through the opening is the offset distance of the light-emitting device defined by the opening;
  • the offset distance of the first light-emitting device is 9 ⁇ m-11 ⁇ m; the offset distance of the second light-emitting device is 15 ⁇ m-17 ⁇ m; and the offset distance of the third light-emitting device is 6 ⁇ m-8 ⁇ m.
  • the pixel circuit includes a plurality of transistors; the circuit layer includes a semiconductor layer, a first gate insulating layer, and a first gate electrode layer distributed in a direction away from the substrate. , a second gate insulating layer, a second gate electrode layer, a dielectric layer, a source and drain layer, a passivation layer and a second planar layer; the wiring layer is provided on a side of the second planar layer away from the substrate. side;
  • the channel of each transistor is located in the semiconductor layer.
  • the pixel circuit in a pixel circuit and its connected data lines and power lines, includes a first reset transistor, a compensation transistor, a driving transistor, a writing transistor, a third a light emission control transistor, a second light emission control transistor, a second reset transistor and a storage capacitor;
  • the first pole of the first reset transistor is used to receive the first reset signal, and the second pole is connected to the gate of the drive transistor and the first plate of the storage capacitor;
  • the first pole of the compensation transistor is connected to the second pole of the driving transistor, and the second pole is connected to the gate of the driving transistor; the compensation transistor has two channels connected in series;
  • the first pole of the write transistor is connected to one of the data lines, and the second pole is connected to the first pole of the drive transistor;
  • the first pole of the first light-emitting control transistor and the second plate of the storage capacitor are connected to the power line, and the second pole is connected to the first pole of the driving transistor;
  • the first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode through the adapter part.
  • the first pole of the second reset transistor is used to receive the second reset signal, and the second pole is connected to the second pole of the second light emitting control transistor;
  • the first gate layer includes the gate electrode of each of the transistors and the first plate of the storage capacitor;
  • the second gate layer includes the second plate of the storage capacitor, a blocking block and a shield.
  • Block the source-drain layer includes a connection portion connecting the second electrode of the compensation transistor and the gate electrode of the drive transistor, and the connection portion and the gate electrode of the drive transistor are located on the same side of the data line;
  • At least part of the shielding block overlaps the semiconductor layer between the two channels of the compensation transistor; the shielding block is at least partially located between the data line and the connection part, and the shielding block Connect to the power cord.
  • the display panel includes a display area, the display area includes a secondary display area and a main display area located outside the secondary display area; the light-emitting devices are distributed in the main display area and the secondary display area;
  • a pixel circuit connected to at least part of the light-emitting devices in the secondary display area is located in the main display area and is connected to the light-emitting devices through conductive lines;
  • the circuit layer also includes a conductive layer and an insulating layer.
  • the conductive layer is provided on a side of the passivation layer away from the substrate.
  • the insulating layer covers the conductive layer.
  • the second flat layer covers the The insulating layer; the conductive layer includes the conductive line.
  • the conductive layer further includes a plurality of overlapping portions located in the display area, and a pixel circuit is connected to the power line through one of the overlapping portions.
  • a display device including the display panel according to any one of the above.
  • FIG. 1 is a schematic diagram of a display area and a peripheral area of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a partial cross-sectional view of an embodiment of the display panel of the present disclosure.
  • FIG. 3 is a schematic diagram of the light-emitting device and wiring layer of the first embodiment of the display panel of the present disclosure.
  • FIG. 4 is a schematic diagram of the light-emitting device and wiring layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a pixel circuit in an embodiment of the display panel of the present disclosure.
  • 6-12 are partial top views of each film layer of the display panel according to the first embodiment of the present disclosure.
  • FIG. 13 is a partial top view of the semiconductor layer and the first gate layer of the display panel according to the first embodiment of the present disclosure.
  • FIG 14 is a partial top view of the semiconductor layer to the second gate layer of the display panel according to the first embodiment of the present disclosure.
  • FIG. 15 is a partial top view of the semiconductor layer to the conductive layer of the display panel according to the first embodiment of the present disclosure.
  • FIG. 16 is a partial top view of the semiconductor layer to the wiring layer of the display panel according to the first embodiment of the present disclosure.
  • FIG. 17 is a partial top view of the first embodiment of the display panel of the present disclosure.
  • 18-24 are partial top views of each film layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 25 is a partial top view of the semiconductor layer and the first gate layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 26 is a partial top view of the semiconductor layer to the second gate layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 27 is a partial top view of the semiconductor layer to the conductive layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 28 is a partial top view of the semiconductor layer to the wiring layer of the display panel according to the second embodiment of the present disclosure.
  • FIG. 29 is a partial top view of the second embodiment of the display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • row direction X and the column direction Y in this article are only two mutually perpendicular directions.
  • overlap of feature A and feature B in this article means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.
  • the transistors in the pixel circuit of the present disclosure may be N-type transistors, P-type transistors, or both may exist at the same time.
  • the transistor may have a gate, a first pole and a second pole.
  • the gate may control the on and off of the transistor.
  • the first pole and the second pole may be used for input and output signals.
  • the first pole may be the source of the transistor. pole, and the second pole can be the drain of the transistor. But when the operating state of the transistor changes, such as when the direction of the current changes, the source and drain of the transistor can be interchanged.
  • a display panel which may include a driving backplane BP, a light emitting device LD, and an anti-reflective layer COE, wherein:
  • the driving backplane BP may include a substrate SU and a circuit layer CL, a wiring layer SD2 and a first flat layer PLN2 sequentially stacked in a direction away from the substrate SU;
  • the circuit layer CL includes a plurality of pixel circuits PC distributed in an array;
  • wiring Layer SD2 includes data lines DAL and power lines VDL distributed along the row direction There are a plurality of through-holes VDH distributed in the direction.
  • the through-hole VDH is provided with an adapter part VDL1 on the same layer and spaced apart from the power line VDL.
  • One adapter part VDL1 is connected to a pixel circuit PC.
  • the number of light-emitting devices LD is multiple, and the array is distributed on the side of the first flat layer PLN2 away from the substrate SU, and is connected to the pixel circuit PC;
  • the light-emitting device LD includes first electrodes stacked sequentially in the direction away from the substrate SU ANO, the light-emitting layer EL and the second electrode CAT;
  • the light-emitting device LD includes at least two light-emitting devices LD with different emitting colors; at least part of the light-emitting device LD overlaps the power line VDL.
  • the anti-reflective layer COE can be disposed on the side of the light-emitting device LD away from the substrate SU, and includes a plurality of filter portions CF distributed in an array.
  • One filter portion CF overlaps with one light-emitting device LD; the color of the filter portion CF and The light-emitting device LD overlapping therewith emits the same color.
  • the filter portion CF of the anti-reflection layer COE can only transmit monochromatic light, so that the filter portion CF can be used to reduce the ambient light entering the interior of the display panel, and even if part of the ambient light is emitted by the light-emitting device LD and the pixels Due to the reflection of the circuit PC, the partially reflected ambient light will be blocked by the filter part CF and cannot be emitted, thereby reducing the reflection of the ambient light by the display panel and acting as a circular polarizer, thereby eliminating the need for a large Thick circular polarizer, thereby reducing the thickness of the display panel.
  • the first electrode ANO is made of reflective material.
  • the width of the power line VDL is larger than the data line DAL, and the area where the through hole VDH is not provided overlaps the light-emitting device LD, it is beneficial to make the first electrode ANO flatter and avoid being caused by the first
  • the unevenness of the electrode ANO interferes with the propagation of light, thereby improving the phenomenon of color separation and color shift when the light emerges from the anti-reflective layer COE due to interference in the optical path.
  • the display panel may have a display area AA and a peripheral area WA located outside the display area AA.
  • the peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA, or it may be a semi-enclosed area.
  • the shape of the peripheral area WA is not particularly limited here.
  • the light-emitting devices LD may be distributed in the display area AA, and by causing the light-emitting devices LD to emit light, an image may be displayed, while the peripheral area WA does not emit light.
  • the driving backplane BP may include a substrate SU, a circuit layer CL, a wiring layer SD2 and a first planar layer PLN2 stacked on one side of the substrate SU, where:
  • the substrate SU can be a substrate for the driving backplane BP, which can carry the circuit layer CL.
  • the substrate SU can be a hard or flexible structure, and it can be a single-layer or multi-layer structure, which is not specifically limited here.
  • the circuit layer CL may include a driving circuit for driving the light-emitting devices LD to emit light independently to display images.
  • the driving circuit may include a pixel circuit PC and a peripheral circuit.
  • the pixel circuit PC may be located in the display area AA and connected to the light emitting device LD. Of course, a part of the pixel circuit PC may be located in the peripheral area WA.
  • the peripheral circuit is located in the peripheral area WA, and is connected to the pixel circuit PC.
  • the peripheral circuit can be connected to the light-emitting device LD through the pixel circuit PC and apply the first power signal VDD to the first electrode ANO of the light-emitting device LD.
  • the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD.
  • the second power signal VSS is applied to the second electrode CAT, and the current passing through the light-emitting device LD can be controlled by controlling the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD.
  • the peripheral circuit may include a gate drive circuit, a light-emitting control circuit, etc., and of course may also include other circuits. The specific structure of the peripheral circuit is not particularly limited here.
  • Each pixel circuit PC may include multiple transistors and storage capacitors.
  • the channels of each transistor may be arranged on the same layer, and they may all be made of semiconductor materials such as polysilicon.
  • the pixel circuit PC can include multiple transistors, and can also include capacitors, which can be 3T1C, 7T1C and other pixel circuit PCs.
  • nTmC means that a pixel circuit PC includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter “C” means).
  • the number of pixel circuits PC can be multiple, and the array distribution is in multiple rows and columns.
  • One pixel circuit PC can be connected to one light-emitting device LD. Of course, there can also be a situation where one pixel circuit PC is connected to multiple light-emitting devices LD. This article Only the one-to-one connection between the pixel circuit PC and the light-emitting device LD will be described as an example.
  • the wiring layer SD2 is provided on the side of the circuit layer CL facing away from the substrate SU, and includes at least the data line DAL and the power line VDL connected to the pixel circuit PC.
  • the wiring layer SD2 and the circuit layer CL can be formed Drive circuit.
  • data lines DAL and power lines VDL there are also multiple data lines DAL and power lines VDL, and they both extend along the column direction Y and are distributed along the row direction X.
  • One data line DAL can connect to at least one column of pixel circuits PC.
  • a power line VDL may also be connected to at least one column of pixel circuits PC.
  • the data line DAL can input the data signal DA to the pixel circuit PC, and the power line VDL can input the first power signal VDD to the pixel circuit PC.
  • the first flat layer PLN2 can cover the wiring layer SD2.
  • the material of the first flat layer PLN2 can be organic materials such as transparent resin, and the surface of the first flat layer PLN2 away from the driving backplane BP is flat. In order to arrange the light emitting device LD thereon.
  • each light-emitting device LD can be array-distributed on the surface of the first planar layer PLN2 facing away from the wiring layer SD2.
  • the light-emitting device LD can be an organic light-emitting diode, which includes a first electrode stacked in a direction away from the substrate SU.
  • ANO, luminescent layer EL and second electrode CAT where:
  • a first electrode ANO is connected to a pixel circuit PC.
  • the first electrode ANO serves as an anode. It can be a single-layer or multi-layer structure, and its material can include one or more of conductive metals, metal oxides and alloys.
  • the first electrode ANO may have a light-shielding structure.
  • the first electrode ANO may include three metal layers. The material of the middle metal layer may be silver, aluminum, etc., and the material of the other two metal layers may be titanium or other metals. There are no special restrictions here.
  • the luminescent layer EL is at least partially disposed within the opening PH, and may include a hole injection layer, a hole transport layer, a luminescent material layer, an electron transport layer and an electron injection layer sequentially stacked in a direction away from the substrate SU. layer, holes and electrons can be combined into excitons in the luminescent material layer, and the excitons radiate photons, thereby generating visible light.
  • a hole injection layer a hole transport layer
  • a luminescent material layer an electron transport layer and an electron injection layer sequentially stacked in a direction away from the substrate SU.
  • holes and electrons can be combined into excitons in the luminescent material layer, and the excitons radiate photons, thereby generating visible light.
  • the specific luminescence principle will not be described in detail here.
  • the light-emitting layer EL can be distributed in an array, and each light-emitting device LD has a light-emitting layer EL that emits light independently, so that each light-emitting device LD can emit light independently, and the light-emitting colors of different light-emitting devices LD can be different.
  • the number of the light-emitting layers EL is multiple, and the arrays are distributed in each opening PH, and are stacked with the first electrode ANO exposed by the opening PH.
  • each of the light-emitting layers EL may share at least part of the film layers except the light-emitting material layer, but the light-emitting material layers may be provided independently. It is also possible to obtain light-emitting devices LD with different emitting colors.
  • the second electrode CAT can cover the light-emitting layer EL, which can serve as the cathode of the light-emitting device LD.
  • the second electrode CAT can be a single-layer or multi-layer structure, and its materials can include conductive metals, metal oxides and One or more alloys.
  • Each light-emitting device LD can share the same second electrode CAT.
  • the second electrode CAT is a continuous conductive layer CR covering the light-emitting layer EL and the pixel definition layer PDL of each light-emitting device LD. That is to say, the second electrode CAT is The orthographic projection of the pixel definition layer PDL covers each opening PH.
  • a pixel definition layer PDL can also be provided on the surface of the first planar layer PLN2 facing away from the substrate SU.
  • the pixel definition layer PDL can be used to separate each light-emitting device LD, thereby preventing Adjacent light-emitting devices LD cross-color.
  • the pixel definition layer PDL may be provided with a plurality of openings PH, each opening PH exposes each first electrode ANO in one-to-one correspondence, and the boundary of the opening PH is located within the boundary of the exposed first electrode ANO.
  • the range defined by each opening PH is the range of a light-emitting device LD.
  • the first electrode ANO may include an electrode body AN1 and an electrode connection part AN2 extending outward from the electrode body AN1.
  • An opening PH exposes an electrode body AN1, and the opening PH The boundary of is located within the boundary of its exposed electrode body AN1.
  • the electrode connection part AN2 extends beyond the boundary of the opening PH, and can be connected to a pixel circuit PC through the contact hole AH penetrating the first planar layer PLN2, so that the contact hole AH does not need to be provided within the range of the light-emitting device LD to avoid affecting the light-emitting area. .
  • the distance between an opening PH and the contact hole AH connected to the electrode connecting portion AN2 connected to the exposed electrode body AN1 can be defined as the offset distance of the light-emitting device LD defined by the opening PH.
  • the light-emitting device LD may include a first light-emitting device LDb of a first color, a second light-emitting device LDr of a second color, and a third light-emitting device LDg of a third color, where the first color may be blue and the second color may be red, The third color may be green.
  • the range of the first light-emitting device LDb (the range of the opening PHb of the first light-emitting device LDb) can be made larger than the second light-emitting device LDr (the range of the opening PHr of the second light-emitting device LDr).
  • the third light-emitting device LDg (the range of the opening PHg of the third light-emitting device LDg).
  • the life of the blue-light-emitting light-emitting device LD with a short life can be improved.
  • the range of the second light-emitting device LDr can also be increased. is greater than the range of the third light emitting device LDg.
  • Each light-emitting device LD can be arranged into multiple device columns along the row direction X, and one device column can include multiple light-emitting devices LD distributed along the column direction Y.
  • one device column can include multiple light-emitting devices LD distributed along the column direction Y.
  • Each device column may include first device columns and second device columns alternately distributed along the row direction X.
  • the first device column may include first light-emitting devices LDb and second light-emitting devices LDr alternately distributed along the column direction Y.
  • the second device column The column includes the third light emitting device LDg, that is, the third light emitting device LDg is not in the same column as the first light emitting device LDb and the second light emitting device LDr.
  • each light-emitting device LD can be divided into a plurality of light-emitting units, and each light-emitting unit can include a first light-emitting device LDb, a second light-emitting device LDr and Two third light-emitting devices LDg, the first light-emitting device LDb and the second light-emitting device LDr may be distributed along the column direction Y, and the two third light-emitting devices LDg may be distributed along the row direction X between the first light-emitting device LDb and the second light-emitting device The two sides of LDr are thus distributed in a quadrilateral, which may be a rhombus.
  • Adjacent light-emitting units may share part of the light-emitting device LD, and of course, may not share the light-emitting device LD.
  • the light-emitting devices LD can also be arranged in other ways, and the arrangement is not particularly limited here. Only the above-mentioned diamond-shaped arrangement will be described herein.
  • the anti-reflection layer COE can be provided on the side of the light-emitting device LD away from the driving backplane BP, and has a plurality of filter parts CF.
  • the filter parts CF can be used to transmit monochromatic light, and the monochromatic light can Is red light, blue light, green light, etc.
  • Each filter part CF can be overlapped with each light-emitting device LD in a one-to-one correspondence, and the colors of the overlapping light-emitting devices LD and the filter parts CF are the same, that is, the color of the light emitted by the light-emitting device LD is the same as the color of the light emitted by the light-emitting device LD overlapping with it.
  • the anti-reflection layer COE can also include a light-shielding portion BM that separates each filter portion CF.
  • the light-shielding portion BM can be a black resin material. Of course, other materials can also be used as long as they can block light.
  • the orthographic projection of the light-emitting device LD on the substrate SU can be located within the orthographic projection of the overlapping filter portion CF on the substrate SU.
  • the display panel can also include an encapsulation layer, which can cover the light-emitting device LD to protect the light-emitting device LD and prevent external water and oxygen from corroding the light-emitting device LD.
  • the anti-reflection layer COE can be provided on a side of the encapsulation layer facing away from the substrate SU.
  • the encapsulation layer can be encapsulated by thin film encapsulation, which can include a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the light-emitting device LD, and the organic layer can be disposed on the first
  • the inorganic layer is away from the surface of the driving backplane BP, and the boundary of the organic layer is limited to the inside of the boundary of the first inorganic layer.
  • the boundary of the orthographic projection of the organic layer on the driving backplane BP can be located in the peripheral area WA to ensure that the organic layer can cover Each light emitting device LD.
  • the second inorganic layer can cover the organic layer and the first inorganic layer that is not covered by the organic layer, can block the intrusion of water and oxygen through the second inorganic layer, and achieve planarization through the flexible organic layer.
  • the display panel may further include a touch layer, which may be disposed between the anti-reflective layer COE and the encapsulation layer.
  • the touch layer may adopt a self-capacitive or mutual-capacitive touch structure.
  • the touch layer can also be provided on the side of the anti-reflective layer COE away from the driving backplane BP, and its specific location and process are not particularly limited here.
  • the display panel may further include a transparent cover plate, which may be bonded to the anti-reflective layer COE and achieve planarization.
  • the transparent cover is used to protect the film layer below, and its material can be transparent materials such as glass or acrylic, which is not specifically limited here.
  • the display panel may be a display panel capable of off-screen photography, and its displayable area AA may include a secondary display area FA and a main display area located outside the secondary display area FA.
  • the pixel circuit PC connected to at least part of the light-emitting devices LD in the sub-display area FA can be located in the main display area MA and connected to the light-emitting devices LD through conductive lines, thereby reducing the number of pixel circuits PC in the sub-display area FA.
  • the conductive lines can be made of transparent conductive materials such as indium tin oxide to improve the light transmittance of the sub-display area FA, and can extend from the sub-display area FA to the main display area MA, and the lengths of different conductive lines can be different.
  • the conductive line may be located in the circuit layer CL or between the driving backplane BP and the light emitting device LD. This article only takes the example that the conductive line is located in the circuit layer CL for explanation.
  • the pixel circuit PC may have a 7T1C structure, that is, it may have 7 transistors and 1 capacitor, namely the first reset transistor T1, the compensation transistor T2, the driving transistor T3, The writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7 and the storage capacitor Cst.
  • the first electrode of the first reset transistor T1 is connected to the first reset signal line VIL1 for receiving the first reset signal Vinit1, and the second electrode is connected to the gate electrode of the driving transistor T3 and the first terminal of the storage capacitor Cst. Plate connection.
  • the first electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the gate electrode of the driving transistor T3.
  • the first electrode of the writing transistor T4 is connected to the data line DAL for receiving the data signal DA, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the first pole of the first light-emitting control transistor T5 and the second plate of the storage capacitor Cst are connected to the power line VDL for receiving the first power signal VDD, and the second pole is connected to the first pole of the driving transistor T3.
  • the first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode ANO of a light emitting device LD.
  • the first electrode of the second reset transistor T7 is connected to the second reset signal line VIL2 for receiving the second reset signal Vinit2, and the second electrode is connected to the second electrode of the second light emitting control transistor T6.
  • the second electrode CAT of the light emitting device LD may receive the second power signal VSS.
  • the gate of the first reset transistor T1 is connected to the first reset control line REL1 for inputting the first reset control signal RE1
  • the gate of the second reset transistor T7 is connected to the first reset control line REL1.
  • the two reset control lines REL2 are connected and used to input the second reset control signal RE2.
  • the gates of the compensation transistor T2 and the writing transistor T4 are connected to the scan line GL for inputting the scan signal GA
  • the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line EML for inputting the scan signal GA.
  • Light emission control signal EM The pixel circuit PC can be used to drive the connected light-emitting device LD to emit light in response to signals provided by each connected signal terminal.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors all adopt P-type transistors as an example for description. Based on the description and teaching of this implementation method in this disclosure, those of ordinary skill in the art can easily think of using N-type transistors for at least some of the transistors in the PC structure of the pixel circuit in the embodiment of the present disclosure, without having to make creative efforts, that is, using Implementations of N-type transistors or combinations of N-type transistors and P-type transistors, therefore, these implementations are also within the protection scope of the embodiments of the present disclosure.
  • each transistor of the pixel circuit PC is a P-type low-temperature polysilicon transistor to explain its working principle:
  • the first reset control signal RE1 is a low-level signal
  • the first reset transistor T1 is turned on
  • the gate of the driving transistor T3 and the first plate of the storage capacitor Cst are written with the reset signal Vinit1
  • the N1 node is implemented Initialize to eliminate the influence of the data of the previous frame of image.
  • the writing transistor T4 and the compensation transistor T2 can be turned on, and the data signal DA can be written to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst. , that is, writing the data signal DA to the N1 node through the N3 node and the N2 node until the potential reaches Vdata+Vth.
  • Vdata is the voltage of the data signal DA
  • Vth is the threshold voltage of the driving transistor T3.
  • the scanning signal GA of the writing transistor T4 and the compensation transistor T2 may be the same signal.
  • the second reset control signal RE2 is a low-level signal, turning on the second reset transistor T7, and the second reset signal Vinit2 is written into the first electrode ANO of the light-emitting device LD and the second pole of the second light-emitting control transistor T6. , reset the N4 node to implement initialization, and further eliminate the influence of the data of the previous frame image.
  • the light-emitting control signal EM is a low-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on
  • the driving transistor T3 is the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD.
  • the light-emitting device LD emits light.
  • the transistors and capacitors of the pixel circuit PC are located on the circuit layer CL.
  • the circuit layer CL may include a layer along the edge away from the substrate.
  • the semiconductor layer SEL, the first gate insulating layer GI1, the first gate layer GAT1, the second gate insulating layer GI2, the second gate layer GAT2, the dielectric layer ILD, the source and drain layer SD1, and passivation are distributed in the direction of the bottom SU.
  • layer PVX and the second flat layer PLN1 where,
  • the semiconductor layer SEL may include channels of each transistor (T1-T7) and a doped region connecting at least part of the channel, through which the connection of some of the transistors may be realized.
  • the first gate layer GAT1 may include a first plate Cst1 of a storage capacitor Cst, a scan line GL, a first reset control line REL1, and a second reset control line REL2. and the emission control line EML, and the area where the scanning line GL overlaps with the semiconductor layer SEL is the gate electrode of the writing transistor T4 and the compensation transistor T2.
  • the overlapping area of the first reset control line REL1 and the semiconductor layer SEL is the gate electrode of the first reset transistor T1.
  • the overlapping area of the second reset control line REL2 and the semiconductor layer SEL is the gate electrode of the second reset transistor T7.
  • the overlapping area of the emission control line EML and the semiconductor layer SEL is the gate electrode of the first emission control transistor T5 and the second emission control transistor T6.
  • the area where the first plate Cst1 overlaps with the semiconductor layer SEL is the gate electrode of the driving transistor T3, that is, the first plate Cst1 is multiplexed as the gate electrode of the driving transistor T3.
  • the second reset control line REL2 connected to the n-th row pixel circuit PC can be multiplexed as the first reset control line REL1 connected to the n+1-th row pixel circuit PC, so that when the n-th row pixel circuit PC is in the reset phase, the The n+1 row pixel circuit PC can reset the light-emitting device LD, thereby improving work efficiency.
  • the second gate layer GAT2 may include a second plate Cst2 of a storage capacitor Cst, a first reset signal line VIL1 and a second reset signal line VIL2.
  • the first reset signal The line VIL1 and the second reset signal line VIL2 may extend along the row direction X and be distributed along the column direction Y.
  • the second plate Cst2 is located between the first reset signal line VIL1 and the second reset signal line VIL2.
  • the second plate Cst2 overlaps the first plate Cst1 and has an opening.
  • the orthographic projection of the first plate Cst1 on the substrate SU can cover the orthographic projection of the opening on the substrate SU.
  • the second gate layer GAT2 may also include a shielding block BL1.
  • the shielding block BL1 overlaps with the semiconductor layer SEL between the two channels of the compensation transistor T2, thereby shielding the compensation transistor T2 and preventing light from causing the compensation.
  • the electrical characteristics of transistor T2 change.
  • the shielding block BL1 can also be connected to the power line VDL. On the one hand, it can function as a signal shield to prevent the compensation transistor T2 from being interfered by other signals. On the other hand, it can reduce the impedance of the power line VDL.
  • the source and drain layer SD1 may include a plurality of connection parts.
  • the connection parts may include a first connection part SDL1 and a second connection part SDL2 .
  • the first connection part SDL1 may pass through The hole connects the first reset transistor T1 and the first reset signal line VIL1.
  • the second connection part SDL2 can be connected to the compensation transistor T2 and the first plate Cst1 through a via hole, and the via hole connecting the compensation transistor T2 and the first plate Cst1 passes through the opening of the second plate Cst2, thereby connecting the compensation transistor T2 and the first plate Cst1.
  • the second connection portion SDL2 can extend along the column direction Y, and the second connection portion SDL2 and the gate of the driving transistor T3 are located on the same side of the data line DAL.
  • the second gate layer GAT2 may further include a shielding block BL2, which is at least partially located on the data line DAL and the second connection part SDL2 , that is, the orthographic projection of the shielding block BL2 on the substrate SU is at least partially located between the data line DAL and the orthographic projection of the second connection portion SDL2 on the substrate SU.
  • the shielding block BL2 can be connected to the power line VDL, so that by inputting a constant first power signal to the shielding block BL2, the data signal of the data line DAL can be shielded to prevent it from interfering with the signal of the gate of the driving transistor T3.
  • the shielding blocks BL1 and BL2 of two adjacent columns of pixel circuits PC can be of an integral structure, or of course, can also be structures that are independent of each other and distributed at intervals.
  • the second flat layer PLN1 may be disposed on a side of the source and drain layer SD1 away from the substrate SU.
  • the circuit layer CL may also include a conductive layer CR and an insulating layer EBB.
  • the conductive layer CR may be provided on the surface of the passivation layer PVX away from the substrate SU, and the insulating layer EEB can cover the conductive layer CR, and the second flat layer PLN1 can cover the insulating layer EEB.
  • the material of the insulating layer EEB can be inorganic materials such as silicon nitride, and of course, organic insulating materials.
  • the conductive lines connecting the main display area MA and the auxiliary display area FA are located on the conductive layer CR.
  • the conductive layer CR can also include a plurality of overlapping portions CR1 located in the display area AA.
  • the overlapping portions CR1 are spaced apart from the conductive lines.
  • a pixel circuit PC can be connected to the power line VDL through an overlapping portion CR1, so that it can be connected to the power line VDL through an overlapping portion CR1.
  • the overlapping portion CR1 functions as a transfer.
  • the conductive layer CR can be made of transparent conductive materials such as indium tin oxide to reduce the impact of the conductive lines on the light transmittance of the secondary display area FA.
  • the wiring layer SD2 may be provided on the surface of the first flat layer PLN2 away from the substrate SU.
  • the inventor proposed that the power line VDL can be made wider than the data line DAL and overlap with at least part of the light emitting device LD, so that at least the first electrode ANO is located in the inner area of the opening PH range through the power line VDL Perform padding to improve the flatness of the first electrode ANO within the opening PH range, thereby improving display abnormality such as color separation and color cast.
  • the width of the power line VDL is larger than the data line DAL, thereby increasing the area of the power line VDL, which is beneficial to flattening the first electrode ANO.
  • the following is an exemplary description of the solution of flattening the first electrode ANO on the power line VDL:
  • each data line DAL and power line VDL are alternately distributed along the row direction X, and there is only one power line between two adjacent data lines DAL. VDL.
  • two adjacent pixel circuits PC in the row direction X can be obtained by translating the pixel circuit PC along the row direction X.
  • a row of light-emitting devices LD can be disposed between two adjacent data lines DAL, that is, there is only one row of light-emitting devices LD (using openings PH) between the front projections of two adjacent data lines DAL on the substrate SU. projection. It should be noted that for a column of light-emitting devices LD, as long as more than 80% of its area is between the two data lines DAL, it can be considered to be located between the two data lines DAL, but not necessarily completely located in front of the two data lines DAL. , can be stored in a certain overlap with the data line DAL.
  • a power line VDL overlaps a column of light-emitting devices LD, and among the overlapping light-emitting devices LD and the power line VDL, at least part of the boundary of the light-emitting device LD is within the boundary of the overlapping power line VDL, that is, at least part of the light-emitting device LD emits light.
  • the orthographic projection of the opening PH of the device LD on the substrate SU is located within the boundary of the power line VDL, so that at least the first electrode ANO within the range of the opening PH can be padded flat using the power line VDL.
  • at least part of the boundary of the first electrode ANO can be made within the boundary of the power line VDL to further improve the flatness of the first electrode ANO.
  • the light-emitting device LD of a device column can overlap with a power line VDL.
  • the boundary of at least one of the second light-emitting device LDr and the third light-emitting device LDg is located on the power line VDL overlapping it.
  • the boundaries of the second light-emitting device LDr and the third light-emitting device LDg are both located within the boundary of the power supply line VDL overlapping them, while the first light-emitting device LDb has a larger range and can exceed the power supply line overlapping it.
  • the boundary of the line VDL overlaps the data line DAL, but the area exceeding the boundary is no more than 20% of the first light emitting device LDb.
  • the power line VDL can be provided with a plurality of through holes VDH distributed along the column direction Y.
  • the through holes VDH are provided with an adapter portion VDL1 on the same layer and spaced apart from the power line VDL.
  • the adapter portion VDL1 can be connected to an overlapping portion CR1 and connected to a pixel circuit PC through the overlapping portion CR1, so that a first electrode ANO can be connected to a pixel circuit PC.
  • the data line DAL can be divided into multiple data line DAL groups, and one data line group DAS includes two data lines DAL
  • the power line VDL can also be divided into multiple power line groups VDS, and one power line group VDS includes two power lines VDL.
  • the two power lines VDL of the same power line group VDS can have an integrated structure, and the range of one power line group VDS is equivalent to the sum of the ranges of the two power lines VDL.
  • the data line group DAS and the power line group VDS can be distributed alternately along the row direction X, and a data line group DAS is provided between two adjacent power line groups VDS.
  • the two columns of pixel circuits PC connected to the two power lines VDL of the power line group VDS can be arranged symmetrically about the central axis of the two power lines VDL.
  • the symmetrical arrangement refers to the pixels
  • the patterns of each film layer of the circuit PC are mirrored with respect to the central axis.
  • the power line set VDS has two integrated power lines VDL
  • the area is increased, and at least part of the boundaries of the light-emitting devices LD can be located within the boundaries of the power line VDL group, thereby utilizing the increase in the power line VDL to flatten the light.
  • the first electrode ANO of the device LD thereby improves display abnormality problems such as color shift and color separation.
  • some of the light-emitting devices LD may overlap with the data line DAL group.
  • the light-emitting devices LD of some device columns in each device column overlap with a power line group VDL, and the light-emitting devices LD of some device columns overlap with the data line group DAS.
  • the second light emitting device LDr and the third light emitting device LDg overlaps the data line DAL group.
  • the boundary of the light-emitting devices LD of the first device column may be located within the boundary of the power line VDL group overlapping therewith, and the light-emitting device LD of the second device column may overlap the data line DAL group.
  • the shielding blocks BL1 of the two adjacent columns of pixel circuits PC have an integrated structure, and the shielding blocks BL2 of the two adjacent columns of pixel circuits PC can be integrated. , of course, they can also be structures that are independent of each other and distributed at intervals.
  • each through hole VDH can be provided with the same layer as the power line VDL.
  • the connecting portion VDL1 is spaced apart, and one connecting portion VDL1 can be connected to a pixel circuit PC.
  • the third light-emitting device LDg of the second device column not only overlaps with the data line group DAS, but also overlaps with part of the through hole VDH.
  • the inventor also found that opening a hole in the first flat layer PLN2 will affect the flatness around the opening. Based on this, if the distance between the contact hole AH and the opening PH connecting the first electrode ANO and the overlap portion CR1 is too close, that is, If the offset distance defined above is too small, it will affect the flatness of the area where the first electrode ANO is located in the opening PH. Therefore, based on the first and second embodiments above, the inventor has tested and analyzed the offset distance. The distance is limited, for example:
  • the offset distance Sb of the first light-emitting device LDb is 2.9 ⁇ m-3 ⁇ m, such as 2.93 ⁇ m; the offset of the second light-emitting device LDr The distance is 6.5 ⁇ m-6.6 ⁇ m, for example, 6.56 ⁇ m; the offset distance Sg of the third light emitting device LDg is 5.2 ⁇ m-5.3 ⁇ m, for example, 5.24 ⁇ m.
  • the distance Sbg between the first light-emitting device LDb and the third light-emitting device LDg is smaller than the distance Srg between the second light-emitting device LDr and the third light-emitting device LDg.
  • the offset distance Sb of the first light-emitting device LDb is 9 ⁇ m-11 ⁇ m, such as 10 ⁇ m; the offset distance Sr of the second light-emitting device LDr
  • the offset distance Sg of the third light-emitting device LDg is 6 ⁇ m-8 ⁇ m, such as 7 ⁇ m.
  • the present disclosure also provides a display device, which may include a display panel according to any of the above embodiments.
  • a display device which may include a display panel according to any of the above embodiments.
  • the display device of the present disclosure can be a smart watch or a bracelet. Of course, it can also be used in electronic devices with display functions such as mobile phones and tablet computers, which will not be listed here.

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Abstract

一种显示面板和显示装置，显示面板包括：驱动背板；驱动背板包括衬底和沿远离衬底的方向依次堆叠的电路层、走线层和第一平坦层；电路层包括多个像素电路；走线层包括沿行方向分布的数据线和电源线，电源线的宽度大于数据线；电源线设有沿列方向分布的多个通孔，通孔内设有与电源线同层且间隔的转接部，一转接部与一像素电路连接；发光器件分布于第一平坦层远离衬底的一侧，且与像素电路连接；发光器件包括第一电极、发光层和第二电极；至少部分发光器件与电源线未设置通孔的区域交叠；抗反射层设于发光器件远离衬底的一侧，且包括多个阵列分布的滤光部，一滤光部与一发光器件交叠；滤光部的颜色和与其交叠的发光器件的发光颜色相同。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
OLED(有机电致发光二极管)显示面板具有自发光、广色域、高对比度、可柔性化、高响应可柔性化等优点，具有广泛的应用前景。但是，目前的显示面板的存在色分离、色偏等影响显示效果的现象。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，包括：
驱动背板，包括衬底和沿远离所述衬底的方向依次堆叠的电路层、走线层和第一平坦层；所述电路层包括阵列分布的多个像素电路；所述走线层包括沿行方向分布的数据线和电源线，一所述数据线和一所述电源线与一列所述像素电路连接；所述电源线的宽度大于所述数据线；所述电源线设有沿所述列方向分布的多个通孔，所述通孔内设有与所述电源线同层且间隔的转接部，一所述转接部与一所述像素电路连接；
多个发光器件，阵列分布于所述第一平坦层远离所述衬底的一侧，且与所述像素电路连接；所述发光器件包括沿远离所述衬底的方向依次堆叠的第一电极、发光层和第二电极；所述发光器件中至少包括两种发光颜色不同的发光器件；至少部分所述发光器件与所述电源线未设置所述通孔的区域交叠；
抗反射层，设于所述发光器件远离所述衬底的一侧，且包括多个阵列分布的滤光部，一所述滤光部与一所述发光器件交叠；所述滤光部的 颜色和与其交叠的发光器件的发光颜色相同。
在本公开的一种示例性实施方式中，各所述数据线和电源线沿所述行方向交替分布；一所述电源线与一列所述发光器件交叠，且相邻两所述数据线之间设有一列所述发光器件；在相互交叠的发光器件和所述电源线中，至少部分发光器件的边界位于与其交叠的电源线的边界以内。
在本公开的一种示例性实施方式中，各所述发光器件沿所述行方向排成多个器件列，且一所述器件列的发光器件与一所述电源线交叠。
在本公开的一种示例性实施方式中，所述发光器件包括第一颜色的第一发光器件、第二颜色的第二发光器件和第三颜色的第三发光器件；
所述第一发光器件的范围大于所述第二发光器件和第三发光器件，所述第二发光器件和第三发光器件中至少一个的边界位于与其交叠的电源线的边界以内。
在本公开的一种示例性实施方式中，各所述器件列包括沿所述行方向交替分布的第一器件列和第二器件列；所述第一器件列包括沿所述列方向交替分布的所述第一发光器件和第二发光器件，所述第二器件列包括所述第三发光器件。
在本公开的一种示例性实施方式中，所述第一电极包括电极本体和由所述电极本体向外延伸的电极连接部，一所述电极连接部通过贯穿所述第一平坦层的接触孔与一所述像素电路连接；
所述显示面板还包括：
像素定义层，设于所述第一平坦层远离所述衬底的一侧，且设有多个用于限定所述发光器件的范围的开口，一所述开口露出一所述电极本体，且所述开口的边界位于其露出的电极本体的边界以内；
一所述开口与其露出的电极本体连接的电极连接部所连接的接触孔之间的距离为所述开口限定的发光器件的偏移距离；
所述第一发光器件的偏移距离为2.9μm-3μm；所述第二发光器件的偏移距离为6.5μm-6.6μm；所述第三发光器件的偏移距离为5.2μm-5.3μm。
在本公开的一种示例性实施方式中，所述数据线划分为多个数据线组，一所述数据线组包括两个所述数据线；所述电源线划分为多个电源线组，一所述电源线组包括两个所述电源线，且两个所述电源线为一体 结构；所述数据线组和所述电源线组沿所述行方向交替分布；一所述电源线组的两电源线连接的两列所述像素电路关于所述两所述电源线的中轴线对称设置；
至少部分所述发光器件的边界位于所述电源线组的边界内，至多部分所述发光器件与所述数据线组交叠。
在本公开的一种示例性实施方式中，各所述发光器件沿所述行方向排成多个器件列，且部分所述器件列的发光器件与一所述电源线组交叠，部分所述器件列的发光器件与所述数据线组交叠。
在本公开的一种示例性实施方式中，所述发光器件包括第一颜色的第一发光器件、第二颜色的第二发光器件和第三颜色的第三发光器件；
所述第一发光器件的范围大于所述第二发光器件和第三发光器件，所述第一发光器件的边界位于与其交叠的电源线组的边界以内，所述第二发光器件和第三发光器件中的至多一个与所述数据线组交叠。
在本公开的一种示例性实施方式中，各所述器件列包括沿所述行方向交替分布的第一器件列和第二器件列；所述第一器件列包括沿所述列方向交替分布的所述第一发光器件和第二发光器件，所述第二器件列包括所述第三发光器件；
所述第一器件列的发光器件的边界位于与其交叠的电源线组的边界内；所述第二器件列的发光器件与所述数据线组交叠。
在本公开的一种示例性实施方式中，所述第一电极包括电极本体和由所述电极本体向外延伸的电极连接部，一所述电极连接部通过贯穿所述第一平坦层的接触孔与一所述像素电路连接；
所述显示面板还包括：
像素定义层，设于所述第一平坦层远离所述衬底的一侧，且设有多个用于限定所述发光器件的范围的开口，一所述开口露出一所述电极本体，且所述开口的边界位于其露出的电极本体的边界以内；
一所述开口与其露出的电极本体连接的电极连接部所连接的接触孔之间的距离为所述开口限定的发光器件的偏移距离；
所述第一发光器件的偏移距离为9μm-11μm；所述第二发光器件的偏移距离为15μm-17μm；所述第三发光器件的偏移距离为6μm-8μm。
在本公开的一种示例性实施方式中，所述像素电路包括多个晶体管；所述电路层包括沿远离所述衬底的方向分布的半导体层、第一栅绝缘层、第一栅极层、第二栅绝缘层、第二栅极层、介电层、源漏层、钝化层和第二平坦层；所述走线层设于所述第二平坦层远离所述衬底的一侧；
各所述晶体管的沟道均位于所述半导体层。
在本公开的一种示例性实施方式中，在一所述像素电路及其连接的数据线和电源线中，所述像素电路包括第一复位晶体管、补偿晶体管、驱动晶体管、写入晶体管、第一发光控制晶体管、第二发光控制晶体管、第二复位晶体管以及存储电容；
所述第一复位晶体管的第一极用于接收第一复位信号，第二极与所述驱动晶体管的栅极和所述存储电容的第一极板连接；
所述补偿晶体管的第一极与所述驱动晶体管的第二极连接，第二极与所述驱动晶体管的栅极连接；所述补偿晶体管具有串联的两个沟道；
所述写入晶体管的第一极与一所述数据线连接，第二极与所述驱动晶体管的第一极连接；
所述第一发光控制晶体管的第一极和所述存储电容的第二极板与以所述电源线连接，第二极与所述驱动晶体管的第一极连接；
所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，第二极通过一所述转接部与一所述第一电极连接。
所述第二复位晶体管的第一极用于接收第二复位信号，第二极与所述第二发光控制晶体管的第二极连接；
所述第一栅极层包括所述各所述晶体管的栅极和所述存储电容的第一极板；所述第二栅极层包括所述存储电容的第二极板、遮挡块和屏蔽块；所述源漏层包括连接所述补偿晶体管的第二极和所述驱动晶体管的栅极的连接部，所述连接部和所述驱动晶体管的栅极位于所述数据线的同一侧；
所述遮挡块的至少部分区域与所述补偿晶体管的两个沟道之间的半导体层交叠；所述屏蔽块至少部分位于所述数据线和所述连接部之间，且所述屏蔽块与所述电源线连接。
在本公开的一种示例性实施方式中，所述显示面板包括显示区，所 述显示区包括副显示区和位于副显示区外的主显示区；所述发光器件分布于所述主显示区和所述副显示区；
连接所述副显示区内的至少部分发光器件的像素电路位于所述主显示区，且通过导电线与所述发光器件连接；
所述电路层还包括导电层和绝缘层，所述导电层设于所述钝化层远离所述衬底的一侧，所述绝缘层覆盖所述导电层，所述第二平坦层覆盖所述绝缘层；所述导电层包括所述导电线。
在本公开的一种示例性实施方式中，所述导电层还包括位于所述显示区的多个搭接部，一所述像素电路通过一所述搭接部与所述电源线连接。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式的显示区和外围区的示意图。
图2为本公开显示面板一实施方式的局部截面图。
图3为本公开显示面板的第一实施方式的发光器件和走线层的示意图。
图4为本公开显示面板的第二实施方式的发光器件和走线层的示意图。
图5为本公开显示面板一实施方式中像素电路的原理图。
图6-图12为本公开显示面板的第一实施方式的各膜层的局部俯视图。
图13为本公开显示面板的第一实施方式的半导体层和第一栅极层的局部俯视图。
图14为本公开显示面板的第一实施方式的半导体层至第二栅极层的局部俯视图
图15为本公开显示面板的第一实施方式的半导体层至导电层的局部俯视图。
图16为本公开显示面板的第一实施方式的半导体层至走线层的局部俯视图。
图17为本公开显示面板的第一实施方式的局部俯视图。
图18-图24为本公开显示面板的第二实施方式的各膜层的局部俯视图。
图25为本公开显示面板的第二实施方式的半导体层和第一栅极层的局部俯视图。
图26为本公开显示面板的第二实施方式的半导体层至第二栅极层的局部俯视图
图27为本公开显示面板的第二实施方式的半导体层至导电层的局部俯视图。
图28为本公开显示面板的第二实施方式的半导体层至走线层的局部俯视图。
图29为本公开显示面板的第二实施方式的局部俯视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表 示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本文中的行方向X和列方向Y仅为两个相互垂直的方向，在本公开的附图中，行方向X可以是横向，列方向Y可以是纵向，但并不限于此，若显示面板发生旋转，则行方向X和列方向Y的实际朝向可能发生变化。
本文中的A特征和B特征“交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影至少部分重合。
本公开的像素电路中的晶体管可以采用N型晶体管，也可以采用P型晶体管，或者二者同时存在。晶体管可以具有栅极、第一极和第二极，通过栅极可控制晶体管的导通和关断，第一极和第二极可以用于输入和输出信号，第一极可以为晶体管的源极，第二极可以为晶体管的漏极。但当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
如图2-图4所示，本公开实施方式提供了一种显示面板，该显示面板可包括驱动背板BP、发光器件LD和抗反射层COE，其中：
驱动背板BP可包括衬底SU和沿远离衬底SU的方向依次堆叠的电路层CL、走线层SD2和第一平坦层PLN2；电路层CL包括阵列分布的多个像素电路PC；走线层SD2包括沿行方向X分布的数据线DAL和电源线VDL，一数据线DAL和一电源线VDL与一列像素电路PC连接；电源线VDL的宽度大于数据线DAL；电源线VDL设有沿列方向分布的多个通孔VDH，通孔VDH内设有与电源线VDL同层且间隔的转接部VDL1，一转接部VDL1与一像素电路PC连接。
发光器件LD的数量为多个，且阵列分布于第一平坦层PLN2远离衬底SU的一侧，且与像素电路PC连接；发光器件LD包括沿远离衬底SU的方向依次堆叠的第一电极ANO、发光层EL和第二电极CAT；发光器件LD中至少包括两种发光颜色不同的发光器件LD；至少部分发光 器件LD与电源线VDL交叠。
抗反射层COE可设于发光器件LD远离衬底SU的一侧，且包括多个阵列分布的滤光部CF，一滤光部CF与一发光器件LD交叠；滤光部CF的颜色和与其交叠的发光器件LD的发光颜色相同。
本公开的显示面板，抗反射层COE的滤光部CF仅能透光单色光，从而可以利用滤光部CF减少进入显示面板内部的环境光，且即便部分环境光被发光器件LD及像素电路PC反射，在部分反射的环境光又会被滤光部CF阻挡，而无法出射，从而可以降低显示面板对环境光的反射，起到圆偏光片的作用，进而可以省去通常具有较大厚度的圆偏光片，从而降低显示面板的厚度。同时，第一电极ANO为反光材质，由于电源线VDL的宽度大于数据线DAL，且未设置通孔VDH的区域与发光器件LD交叠，有利于使第一电极ANO更加平坦，避免因第一电极ANO凹凸不平而干扰光线的传播，从而改善因光路被干扰而使光线在从抗反射层COE出射时出现色分离、色偏等现象。
下面对本公开的显示面板的整体架构进行详细说明：
如图1所示，显示面板可具有显示区AA和位于显示区AA外的外围区WA，外围区WA可以是围绕显示区AA的连续或间断的环形区域，或者也可以是半封闭的区域，在此不对外围区WA的形状做特殊限定。发光器件LD可分布于显示区AA，通过使发光器件LD发光，可以显示图像，而外围区WA则不发光。
如图2所示，驱动背板BP其可包括衬底SU和层叠于衬底SU一侧的电路层CL、走线层SD2和第一平坦层PLN2，其中：
衬底SU可为驱动背板BP的基底，其可承载电路层CL，衬底SU可为硬质或柔性结构，其可以是单层或多层结构，在此不做特殊限定。
电路层CL可包括驱动电路，用于驱动发光器件LD分别独立发光，以显示图像。驱动电路可包括像素电路PC和外围电路，像素电路PC可位于显示区AA内，且与发光器件LD连接，当然，可以存在一部分像素电路PC的部分区域位于外围区WA。外围电路位于外围区WA内，且外围电路与像素电路PC连接。外围电路一方面可通过像素电路PC与发 光器件LD连接，向发光器件LD的第一电极ANO施加第一电源信号VDD，另一方面，外围电路也可与发光器件LD的第二电极CAT连接，并向第二电极CAT施加第二电源信号VSS，通过控制像素电路PC可控制通过发光器件LD的电流，从而控制发光器件LD的亮度。外围电路可包括栅极驱动电路和发光控制电路等，当然，还可包括其它电路，在此不对外围电路的具体结构做特殊限定。
每个像素电路PC可包括多个晶体管和存储电容，各晶体管的沟道可同层设置，且均为多晶硅等半导体材料。像素电路PC可包括多个晶体管，还可以包括电容，其可以是3T1C、7T1C等像素电路PC，nTmC表示一个像素电路PC包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。像素电路PC的数量可以是多个，且阵列分布呈多行和多列，一像素电路PC可连接一个发光器件LD，当然，也可以存在一个像素电路PC连接多个发光器件LD的情况，本文仅以像素电路PC和发光器件LD一一对应的连接为例进行说明。
如图2所示，走线层SD2设于电路层CL背离衬底SU的一侧，且至少包括与像素电路PC连接的数据线DAL和电源线VDL，走线层SD2和电路层CL可形成驱动电路。
如图3和图4所示，数据线DAL和电源线VDL的数量也为多个，且均沿列方向Y延伸，并沿行方向X分布，一数据线DAL可连接至少一列像素电路PC，一电源线VDL也可连接至少一列像素电路PC。数据线DAL可向像素电路PC输入数据信号DA，电源线VDL可向像素电路PC输入第一电源信号VDD。
如图2所示，第一平坦层PLN2可覆盖走线层SD2，第一平坦层PLN2的材料可以是透明的树脂等有机材料，且第一平坦层PLN2背离驱动背板BP的表面为平面，以便在其上设置发光器件LD。
如图2所示，各发光器件LD可阵列分布于第一平坦层PLN2背离走线层SD2的表面，发光器件LD可为有机发光二极管，其包括沿背离衬底SU的方向层叠的第一电极ANO、发光层EL和第二电极CAT，其中：
一第一电极ANO与一像素电路PC连接，第一电极ANO作为阳极， 其可以是单层或多层结构，其材料可包括导电的金属、金属氧化物以及合金中的一种或多种。第一电极ANO可为遮光结构，例如，第一电极ANO可包括三层金属层，中间一层金属层的材料可以是银、铝等，另外两层金属层的材料可以是钛或其它金属，在此不做特殊限定。
如图2所示，发光层EL至少部分设于开口PH内，且可包括沿背离衬底SU的方向依次层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层，可通过使空穴和电子在发光材料层复合成激子，由激子辐射光子，从而产生可见光，具体发光原理在此不再详述。发光层EL可以阵列分布，每个发光器件LD具有一个独立发光的发光层EL，使得每个发光器件LD可独立发光，且不同的发光器件LD的发光颜色可以不同。举例而言，发光层EL的数量为多个，且阵列分布于各个开口PH，且与开口PH露出的第一电极ANO层叠。或者，各发光层EL可共用除发光材料层外的至少部分膜层，但发光材料层则分别独立设置，也可以得到发光颜色不同的发光器件LD。
如图2所示，第二电极CAT可覆盖发光层EL，其可作为发光器件LD的阴极，第二电极CAT可以是单层或多层结构，其材料可包括导电的金属、金属氧化物以及合金中的一种或多种。各发光器件LD可共用同一第二电极CAT，具体而言，第二电极CAT为覆盖各发光器件LD的发光层EL和像素定义层PDL的连续导电层CR，也就是说，第二电极CAT在像素定义层PDL的正投影覆盖各个开口PH。
如图2所示，为了限定各发光器件LD的范围，还可在第一平坦层PLN2背离衬底SU的表面设置像素定义层PDL，可用像素定义层PDL用于分隔各个发光器件LD，从而防止相邻的发光器件LD串色。具体而言，像素定义层PDL可设有多个开口PH，各开口PH一一对应地露出各第一电极ANO，且开口PH的边界位于其露出的第一电极ANO的边界以内。每个开口PH限定出的范围即为一发光器件LD的范围。
进一步的，如图2、图12和图24所示，第一电极ANO可包括电极本体AN1和由电极本体AN1向外延伸的电极连接部AN2，一开口PH露出一电极本体AN1，且开口PH的边界位于其露出的电极本体AN1的边界以内。电极连接部AN2则延伸至开口PH的边界以外，且可通过贯 穿第一平坦层PLN2的接触孔AH与一像素电路PC连接，使得发光器件LD的范围内不用设置接触孔AH，避免影响发光面积。同时，可将一开口PH与其露出的电极本体AN1连接的电极连接部AN2所连接的接触孔AH之间的距离定义为该开口PH限定的发光器件LD的偏移距离。发明人发现，接触孔AH和开口PH会对第一平坦层PLN2的平整性造成影响，且偏移距离越小，电极本体AN1周边的第一平坦层PLN2越不平整，这会导致第一电极ANO不平坦，从而也会造成色分离和色偏等问题。
发光器件LD可包括第一颜色的第一发光器件LDb、第二颜色的第二发光器件LDr和第三颜色的第三发光器件LDg，第一颜色可为蓝色，第二颜色可为红色，第三颜色可为绿色。为了保证发光器件LD的寿命的一致性，可使第一发光器件LDb的范围(第一发光器件LDb的开口PHb的范围)大于第二发光器件LDr(第二发光器件LDr的开口PHr的范围)和第三发光器件LDg(第三发光器件LDg的开口PHg的范围)，通过增大尺寸可以提高寿命较短的发蓝光的发光器件LD的寿命，此外，还可以使第二发光器件LDr的范围大于第三发光器件LDg的范围。
各发光器件LD可沿行方向X排成多个器件列，一个器件列可包括沿列方向Y分布的多个发光器件LD，举例而言：
各器件列可包括沿行方向X交替分布的第一器件列和第二器件列，第一器件列可包括沿列方向Y交替分布的第一发光器件LDb和第二发光器件LDr，第二器件列包括第三发光器件LDg，也就是说，第三发光器件LDg与第一发光器件LDb和第二发光器件LDr不在同一列。
如图12和图24所示，在本公开的一些实施方式中，各发光器件LD可划分为多个发光单元，每个发光单元可包括一个第一发光器件LDb、一个第二发光器件LDr和两个第三发光器件LDg，第一发光器件LDb和第二发光器件LDr可沿列方向Y分布，两个第三发光器件LDg可沿行方向X分布于第一发光器件LDb和第二发光器件LDr的两侧，从而呈四边形分布，该四边形可以是菱形。相邻的发光单元可以共用部分发光器件LD，当然，也可以不共用发光器件LD。此外，在本公开的其它实施方式中，发光器件LD还可以其它方式排布，在此不对其排布方式做特殊限定，本文中仅以上述的菱形的排布方式进行说明。
如图2所示，抗反射层COE可设于发光器件LD背离驱动背板BP的一侧，具有多个滤光部CF，滤光部CF可用于透过单色光，该单色光可以是红光、蓝光、绿光等。各个滤光部CF可与各发光器件LD一一对应的交叠设置，且相互交叠的发光器件LD和滤光部CF的颜色相同，即发光器件LD发出的光线的颜色和与其交叠的滤光部CF的颜色相同。同时，抗反射层COE还可包括分隔各滤光部CF的遮光部BM，遮光部BM可为黑色的树脂材料，当然，也可以采用其它材料，只要能够遮光即可。进一步的，为了提高出光效率，减少遮光部BM对光线的遮挡，可使发光器件LD在衬底SU上的正投影位于与其交叠的滤光部CF在衬底SU上的正投影以内。
此外，显示面板还可以包括封装层，其可覆盖发光器件LD，用于保护发光器件LD，阻隔外界的水、氧对发光器件LD造成侵蚀。抗反射层COE可设于封装层背离衬底SU的一侧。举例而言，封装层可采用薄膜封装的方式实现封装，其可包括第一无机层、有机层和第二无机层，其中，第一无机层覆盖于发光器件LD，有机层可设于第一无机层背离驱动背板BP的表面，且有机层的边界限定于第一无机层的边界的内侧，有机层在驱动背板BP上的正投影的边界可位于外围区WA，确保有机层能覆盖各发光器件LD。第二无机层可覆盖有机层和未被有机层覆盖的第一无机层，可通过第二无机层阻挡水氧侵入，通过具有柔性的有机层实现平坦化。
在本公开的一些实施方式中，显示面板还可包括触控层，其可设于抗反射层COE和封装层远离之间，触控层可采用自容或互容式触控结构，在此不对其具体结构做特殊限定，只要能实现触控功能即可。当然，触控层也可设于抗反射层COE背离驱动背板BP的一侧，在此不对其具体位置和工艺做特殊限定。
此外，在本公开的一些实施方式中，显示面板还可包括透明盖板，透明盖板可粘接于抗反射层COE上，并可实现平坦化。透明盖板用于保护下方的膜层，其材料可以是玻璃或亚克力等透明材料，在此不做特殊限定。
在本公开的一些实施方式中，如图1所示，显示面板可以是能进行屏下摄像的显示面板，其可显示区AA可包括副显示区FA和位于副显示区FA外的主显示区MA；发光器件LD可分布于主显示区MA和副显示区FA。其中，连接副显示区FA内的至少部分发光器件LD的像素电路PC可位于主显示区MA内，且通过导电线与发光器件LD连接，从而可以减少副显示区FA内的像素电路PC的数量，提高副显示区FA的透光率，从而可通过副显示区FA实现屏下摄像。当然，为了在主显示区MA内容纳更多的像素电路PC，可对部分像素电路PC的尺寸进行压缩，例如沿行方向X减小部分像素电路PC的宽度。导电线可采用氧化铟锡等透明导电材料，以提高副显示区FA的透光率，并可从副显示区FA延伸至主显示区MA，且不同的导电线的长度可以不同。导电线可以位于电路层CL中，也可以位于驱动背板BP和发光器件LD之间。本文中仅以导电线位于电路层CL中为例进行说明。
下面对本公开的像素电路PC的结构进行示例性说明：
在本公开的一些实施方式中，如图5所示，像素电路PC可以是7T1C结构，即其可具有7个晶体管和1个电容，即第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7以及存储电容Cst。
如图5所示，第一复位晶体管T1的第一极与第一复位信号线VIL1连接，用于接收第一复位信号Vinit1，第二极与驱动晶体管T3的栅极和存储电容Cst的第一极板连接。
补偿晶体管T2的第一极与驱动晶体管T3的第二极连接，第二极与驱动晶体管T3的栅极连接。
写入晶体管T4的第一极与数据线DAL连接，用于接收数据信号DA，第二极与驱动晶体管T3的第一极连接。
第一发光控制晶体管T5的第一极和存储电容Cst的第二极板与电源线VDL连接，用于接收第一电源信号VDD，第二极与驱动晶体管T3的第一极连接。
第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极连接， 第二极与一发光器件LD的第一电极ANO连接。
第二复位晶体管T7的第一极与第二复位信号线VIL2连接，用于接收第二复位信号Vinit2，第二极与第二发光控制晶体管T6的第二极连接。发光器件LD的第二电极CAT可接收第二电源信号VSS。
同时，为了控制各晶体管的导通和关断，第一复位晶体管T1的栅极与第一复位控制线REL1连接，用于输入第一复位控制信号RE1，第二复位晶体管T7的栅极与第二复位控制线REL2连接，用于输入第二复位控制信号RE2。补偿晶体管T2和写入晶体管T4的栅极与扫描线GL连接，用于输入扫描信号GA，第一发光控制晶体管T5和第二发光控制晶体管T6的栅极与发光控制线EML连接，用于输入发光控制信号EM。该像素电路PC可以用于响应于所连接的各信号端提供的信号，驱动所连接的发光器件LD发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路PC结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开实施例的保护范围内的。
下面以像素电路PC的各晶体管均为P型低温多晶硅晶体管为例，对其工作原理进行说明：
在复位阶段：第一复位控制信号RE1为低电平信号，第一复位晶体管T1导通，驱动晶体管T3的栅极和存储电容Cst的第一极板被写入复位信号Vinit1，对N1节点实现初始化，消除上一帧图像的数据的影响。
在写入阶段：通过扫描信号GA为低电平信号，可使写入晶体管T4和补偿晶体管T2导通，向驱动晶体管T3的栅极和存储电容Cst的第一极板Cst1写入数据信号DA，即经过N3节点和N2节点向N1节点写入数据信号DA，直至电位达到Vdata+Vth。其中，Vdata为数据信号DA的电压，Vth为驱动晶体管T3的阈值电压。写入晶体管T4和补偿晶体管T2的扫描信号GA可为同一信号。同时，第二复位控制信号RE2为低电平信号，使第二复位晶体管T7导通，发光器件LD的第一电极ANO 和第二发光控制晶体管T6的第二极被写入第二复位信号Vinit2，对N4节点进行复位，实现初始化，进一步消除上一帧图像的数据的影响。
在发光阶段：发光控制信号EM为低电平信号，第一发光控制晶体管T5和第二发光控制晶体管T6导通，驱动晶体管T3在存储电容Cst存储的电压Vdata+Vth和第一电源信号VDD的作用下导通，此时，发光器件LD发光。
下面一上述的7T1C像素电路为例对驱动背板BP进行详细说明：
在一些实施方式中，如图2所示，像素电路PC的晶体管和电容均位于电路层CL，以像素电路PC的晶体管的为顶栅型低温多晶硅晶体管为例，电路层CL可包括沿远离衬底SU的方向分布的半导体层SEL、第一栅绝缘层GI1、第一栅极层GAT1、第二栅绝缘层GI2、第二栅极层GAT2、介电层ILD、源漏层SD1、钝化层PVX和第二平坦层PLN1，其中，
如图6和图18所示，半导体层SEL可包括各晶体管(T1-T7)的沟道以及连接至少部分沟道的掺杂区，通过掺杂区可实现部分晶体管的连接。
如图7、图13、图19和图25所示，第一栅极层GAT1可包括存储电容Cst的第一极板Cst1、扫描线GL、第一复位控制线REL1、第二复位控制线REL2和发光控制线EML，且扫描线GL与半导体层SEL交叠的区域为写入晶体管T4和补偿晶体管T2的栅极。第一复位控制线REL1与半导体层SEL的交叠的区域为第一复位晶体管T1的栅极。第二复位控制线REL2与半导体层SEL的交叠的区域为第二复位晶体管T7的栅极。发光控制线EML与半导体层SEL的交叠的区域为第一发光控制晶体管T5和第二发光控制晶体管T6的栅极。第一极板Cst1与半导体层SEL交叠的区域为驱动晶体管T3的栅极，即第一极板Cst1复用为驱动晶体管T3的栅极。其中，扫描线GL与半导体层SEL存在相互连接的两个交叠区域，形成串联的两个沟道，该两个沟道为补偿晶体管T2的沟道。
此外，连接第n行像素电路PC的第二复位控制线REL2可复用为连 接第n+1行像素电路PC的第一复位控制线REL1，使得第n行像素电路PC处于复位阶段时，第n+1行像素电路PC可以对发光器件LD进行复位，从而提高工作效率。
如图8、图14、图20和26所示，第二栅极层GAT2可包括存储电容Cst的第二极板Cst2、第一复位信号线VIL1和第二复位信号线VIL2，第一复位信号线VIL1和第二复位信号线VIL2可沿行方向X延伸，且沿列方向Y分布，第二极板Cst2位于第一复位信号线VIL1和第二复位信号线VIL2之间。第二极板Cst2与第一极板Cst1交叠，且具有一个开孔。第一极板Cst1在衬底SU上的正投影可以覆盖该开孔在衬底SU上的正投影。此外，第二栅极层GAT2还可包括遮挡块BL1，遮挡块BL1的至少部分区域与补偿晶体管T2的两个沟道之间的半导体层SEL交叠，从而遮挡补偿晶体管T2，防止光照使补偿晶体管T2的电学特性发生变化。此外，还可将遮挡块BL1与电源线VDL连接，一方面可以起到信号屏蔽的作用，防止补偿晶体管T2受到其他信号的干扰，另一方面，可以降低电源线VDL的阻抗。
如图9、图15、图21和图27所示，源漏层SD1可包括多个连接部，连接部可包括第一连接部SDL1和第二连接部SDL2，第一连接部SDL1可以通过过孔连接第一复位晶体管T1和第一复位信号线VIL1。第二连接部SDL2可以通过过孔连接与补偿晶体管T2和第一极板Cst1，且连接补偿晶体管T2和第一极板Cst1的过孔穿过上述第二极板Cst2的开孔，从而连接补偿晶体管T2的第二极和驱动晶体管T3的栅极。同时，对于一像素电路及其连接的数据线DAL而言，第二连接部SDL2可沿列方向Y延伸，且第二连接部SDL2和驱动晶体管T3的栅极位于数据线DAL的同一侧。
为了防止数据线DAL上的数据信号通过第二连接部SDL2对驱动晶体管T3的栅极造成干扰，第二栅极层GAT2还可包括屏蔽块BL2，其至少部分位于数据线DAL和第二连接部SDL2之间，即屏蔽块BL2在衬底SU上的正投影至少部分位于数据线DAL和第二连接部SDL2在衬底SU上的正投影之间。同时，屏蔽块BL2可与电源线VDL连接，从而可通过向屏蔽块BL2输入恒定的第一电源信号，对数据线DAL的数据信 号进行屏蔽，防止其干扰驱动晶体管T3的栅极的信号。
相邻两列像素电路PC的遮挡块BL1和屏蔽块BL2可为一体结构，当然，也可以是相互独立且间隔分布的结构。
第二平坦层PLN1可设于源漏层SD1远离衬底SU的一侧。
此外，如图10、图15、图22和图27所示，电路层CL还可包括导电层CR和绝缘层EBB，导电层CR可设于钝化层PVX远离衬底SU的表面，绝缘层EEB则可覆盖导电层CR，第二平坦层PLN1可覆盖绝缘层EEB，绝缘层EEB的材料可以是氮化硅等无机材料，当然，也开始有机绝缘材料。连接主显示区MA和副显示区FA的导电线则位于导电层CR。同时，导电层CR还可包括位于显示区AA的多个搭接部CR1，搭接部CR1与导电线间隔分布，一像素电路PC可通过一搭接部CR1与电源线VDL连接，从而可通过搭接部CR1起到转接的作用。导电层CR的材料可采用氧化铟锡等透明导电材料，减小导电线对副显示区FA的透光率的影响。
如图11、图16、图23和图28所示，走线层SD2可设于第一平坦层PLN2远离衬底SU的表面。发明人发现，走线层SD2并非连续的整层结果，其图案会对第一平坦层PLN2远离衬底SU的表面的平坦程度造成影响，而这又会直接影响发光器件LD的第一电极ANO的平坦程度，若第一电极ANO的平坦性较低，则会对其反射的光线的光路造成影响，在从抗反射层COE出射后，容易出现色分离和色偏的显示不良现象。为了解决该问题，发明人提出，可以通过使电源线VDL的宽度大于数据线DAL，且与至少部分发光器件LD交叠，从而通过电源线VDL至少对第一电极ANO位于开口PH范围的内区域进行垫平，提高第一电极ANO在开口PH范围内的平整度，从而改善色分离和色偏等显示异常现象。
电源线VDL的宽度大于数据线DAL，从而增大电源线VDL的面积，有利于垫平第一电极ANO。下面对电源线VDL垫平第一电极ANO的方案进行示例性的说明：
如图3、图12和图17所示，在本公开的第一种实施方式中，各数 据线DAL和电源线VDL沿行方向X交替分布，相邻两数据线DAL之间只有一个电源线VDL。在本实施方式中，在行方向X上相邻的两像素电路PC可由像素电路PC沿行方向X平移得到。
相邻两数据线DAL之间可设有一列发光器件LD，即相邻两数据线DAL在衬底SU上的正投影之间只有一列发光器件LD(用开口PH)在衬底SU上的正投影。需要说明的是，对于一列发光器件LD而言，只要其80％以上的区域在两数据线DAL之间既可以认为其位于两数据线DAL之间，而不一定是完全位于两数据线DAL之前，可以与数据线DAL储存在一定的交叠。
一电源线VDL与一列发光器件LD交叠，且在相互交叠的发光器件LD和电源线VDL中，至少部分发光器件LD的边界位于与其交叠的电源线VDL的边界以内，即至少一部分发光器件LD的开口PH在衬底SU上的正投影位于电源线VDL的边界以内，从而至少可以利用电源线VDL将开口PH范围内的第一电极ANO垫平。当然，也可以使至少部分第一电极ANO的边界在电源线VDL的边界以内，进一步提高第一电极ANO的平坦性。
进一步的，可使一器件列的发光器件LD可与一电源线VDL交叠，举例而言，第二发光器件LDr和第三发光器件LDg中至少一个的边界位于与其交叠的电源线VDL的边界以内，例如，第二发光器件LDr和第三发光器件LDg的边界均位于与其交叠的电源线VDL的边界以内，而第一发光器件LDb的范围较大，其可以超出与其交叠的电源线VDL的边界，而与数据线DAL交叠，但超出的区域的不大于第一发光器件LDb的20％。
为了便于发光器件LD与像素电路PC连接，电源线VDL可设有沿列方向Y分布的多个通孔VDH，通孔VDH内设有与电源线VDL同层且间隔的转接部VDL1，一转接部VDL1可与一搭接部CR1连接，并通过该搭接部CR1与一像素电路PC连接，从而可将一第一电极ANO与一像素电路PC连接。
如图4、图24和图29所示，在本公开的第二种实施方式中，可将 数据线DAL划分为多个数据线DAL组，且一数据线组DAS包括两个数据线DAL，还可将电源线VDL划分为多个电源线组VDS，且一电源线组VDS包括两个电源线VDL。同时，同一电源线组VDS的两个电源线VDL可为一体结构，一个电源线组VDS的范围相当于两个电源线VDL的范围的总和。同时，数据线组DAS和电源线组VDS可沿行方向X交替分布，相邻两个电源线组VDS之间设有一个数据线组DAS。为了与电源线组VDS的一体结构相匹配，可使一电源线组VDS的两电源线VDL连接的两列像素电路PC可关于该两个电源线VDL的中轴线对称设置，对称设置是指像素电路PC的各膜层的图案均关于该中轴线镜像分布。
由于电源线组VDS具有两个一体结构的电源线VDL，增大了面积，可使至少部分发光器件LD的边界位于电源线VDL组的边界内，从而利用电源线VDL的增大，垫平发光器件LD的第一电极ANO，从而改善色偏和色分离等显示异常问题。同时，由于发光器件LD的分布，可以有部分发光器件LD与数据线DAL组交叠。
进一步的，各器件列中的部分器件列的发光器件LD与一电源线VDL组交叠，部分器件列的发光器件LD与数据线组DAS交叠。举例而言，第二发光器件LDr和第三发光器件LDg中的至多一个与所述数据线DAL组交叠。进一步的，第一器件列的发光器件LD的边界可位于与其交叠的电源线VDL组的边界内，第二器件列的发光器件LD可与数据线DAL组交叠。
同一电源线组VDS连接的两列像素电路PC中，相邻两列像素电路PC的遮挡块BL1为一体结构，相邻两列像素电路PC的屏蔽块BL2可为一体结。，当然，也可以是相互独立且间隔分布的结构。
此外，为了便于发光器件LD与像素电路PC连接，可在每个电源线VDL组开设沿列方向Y分布的多个通孔VDH，每个通孔VDH内可设有与电源线VDL同层且间隔的转接部VDL1，一转接部VDL1可与一像素电路PC连接。第二器件列的第三发光器件LDg除与数据线组DAS交叠外，还与部分通孔VDH交叠。
发明人还发现，由于在第一平坦层PLN2开孔会影响开孔周边的平坦性，基于此，若连接第一电极ANO和搭接部CR1的接触孔AH和开口PH的距离过近，即上文定义的偏移距离过小，会第一电极ANO位于开口PH内的区域的平坦性，因此，发明人基于上文中的第一和第二种实施方式，经过试验和分析，对偏移距离进行了限定，举例而言：
如图3、图12和图17所示，针对上文的第一种实施方式，第一发光器件LDb的偏移距离Sb为2.9μm-3μm，例如2.93μm；第二发光器件LDr的偏移距离为6.5μm-6.6μm，例如6.56μm；第三发光器件LDg的偏移距离Sg为5.2μm-5.3μm，例如，5.24μm。此外，在同一发光单元中，第一发光器件LDb和第三发光器件LDg的距离Sbg小于第二发光器件LDr和第三发光器件LDg的距离Srg。
如图4、图24和图29所示，针对上文的第二种实施方式，第一发光器件LDb的偏移距离Sb为9μm-11μm，例如10μm；第二发光器件LDr的偏移距离Sr为15μm-17μm，例如16μm；第三发光器件LDg的偏移距离Sg为6μm-8μm，例如7μm。
本公开还提供一种显示装置，其可包括上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是智能手表、手环，当然，也可以用于手机、平板电脑等具有显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种显示面板，包括：
    驱动背板，包括衬底和沿远离所述衬底的方向依次堆叠的电路层、走线层和第一平坦层；所述电路层包括阵列分布的多个像素电路；所述走线层包括沿行方向分布的数据线和电源线，一所述数据线和一所述电源线与一列所述像素电路连接；所述电源线的宽度大于所述数据线；所述电源线设有沿所述列方向分布的多个通孔，所述通孔内设有与所述电源线同层且间隔的转接部，一所述转接部与一所述像素电路连接；
    多个发光器件，阵列分布于所述第一平坦层远离所述衬底的一侧，且与所述像素电路连接；所述发光器件包括沿远离所述衬底的方向依次堆叠的第一电极、发光层和第二电极；所述发光器件中至少包括两种发光颜色不同的发光器件；至少部分所述发光器件与所述电源线未设置所述通孔的区域交叠；
    抗反射层，设于所述发光器件远离所述衬底的一侧，且包括多个阵列分布的滤光部，一所述滤光部与一所述发光器件交叠；所述滤光部的颜色和与其交叠的发光器件的发光颜色相同。
  2. 根据权利要求1所述的显示面板，其中，各所述数据线和电源线沿所述行方向交替分布；一所述电源线与一列所述发光器件交叠，且相邻两所述数据线之间设有一列所述发光器件；在相互交叠的发光器件和所述电源线中，至少部分发光器件的边界位于与其交叠的电源线的边界以内。
  3. 根据权利要求2所述的显示面板，其中，各所述发光器件沿所述行方向排成多个器件列，且一所述器件列的发光器件与一所述电源线交叠。
  4. 根据权利要求3所述的显示面板，其中，所述发光器件包括第一颜色的第一发光器件、第二颜色的第二发光器件和第三颜色的第三发光器件；
    所述第一发光器件的范围大于所述第二发光器件和第三发光器件，所述第二发光器件和第三发光器件中至少一个的边界位于与其交叠的电源线的边界以内。
  5. 根据权利要求4所述的显示面板，其中，各所述器件列包括沿所述行方向交替分布的第一器件列和第二器件列；所述第一器件列包括沿所述列方向交替分布的所述第一发光器件和第二发光器件，所述第二器件列包括所述第三发光器件。
  6. 根据权利要求4所述的显示面板，其中，所述第一电极包括电极本体和由所述电极本体向外延伸的电极连接部，一所述电极连接部通过贯穿所述第一平坦层的接触孔与一所述像素电路连接；
    所述显示面板还包括：
    像素定义层，设于所述第一平坦层远离所述衬底的一侧，且设有多个用于限定所述发光器件的范围的开口，一所述开口露出一所述电极本体，且所述开口的边一所述开口与其露出的电极本体连接的电极连接部所连接的接触孔之间的距离为所述开口限定的发光器件的偏移距离；
    所述第一发光器件的偏移距离为2.9μm-3μm；所述第二发光器件的偏移距离为6.5μm-6.6μm；所述第三发光器件的偏移距离为5.2μm-5.3μm。
  7. 根据权利要求1所述的显示面板，其中，所述数据线划分为多个数据线组，一所述数据线组包括两个所述数据线；所述电源线划分为多个电源线组，一所述电源线组包括两个所述电源线，且两个所述电源线为一体结构；所述数据线组和所述电源线组沿所述行方向交替分布；一所述电源线组的两电源线连接的两列所述像素电路关于所述两所述电源线的中轴线对称设置；
    至少部分所述发光器件的边界位于所述电源线组的边界内，至多部分所述发光器件与所述数据线组交叠。
  8. 根据权利要求7所述的显示面板，其中，各所述发光器件沿所述行方向排成多个器件列，且部分所述器件列的发光器件与一所述电源线组交叠，部分所述器件列的发光器件与所述数据线组交叠。
  9. 根据权利要求8所述的显示面板，其中，所述发光器件包括第一颜色的第一发光器件、第二颜色的第二发光器件和第三颜色的第三发光器件；
    所述第一发光器件的范围大于所述第二发光器件和第三发光器件， 所述第一发光器件的边界位于与其交叠的电源线组的边界以内，所述第二发光器件和第三发光器件中的至多一个与所述数据线组交叠。
  10. 根据权利要求9所述的显示面板，其中，各所述器件列包括沿所述行方向交替分布的第一器件列和第二器件列；所述第一器件列包括沿所述列方向交替分布的所述第一发光器件和第二发光器件，所述第二器件列包括所述第三发光器件；
    所述第一器件列的发光器件的边界位于与其交叠的电源线组的边界内；所述第二器件列的发光器件与所述数据线组交叠。
  11. 根据权利要求10所述的显示面板，其中，所述第一电极包括电极本体和由所述电极本体向外延伸的电极连接部，一所述电极连接部通过贯穿所述第一平坦层的接触孔与一所述像素电路连接；
    所述显示面板还包括：
    像素定义层，设于所述第一平坦层远离所述衬底的一侧，且设有多个用于限定所述发光器件的范围的开口，一所述开口露出一所述电极本体，且所述开口的边界位于其露出的电极本体的边界以内；
    一所述开口与其露出的电极本体连接的电极连接部所连接的接触孔之间的距离为所述开口限定的发光器件的偏移距离；
    所述第一发光器件的偏移距离为9μm-11μm；所述第二发光器件的偏移距离为15μm-17μm；所述第三发光器件的偏移距离为6μm-8μm。
  12. 根据权利要求1所述的显示面板，其中，所述像素电路包括多个晶体管；所述电路层包括沿远离所述衬底的方向分布的半导体层、第一栅绝缘层、第一栅极层、第二栅绝缘层、第二栅极层、介电层、源漏层、钝化层和第二平坦层；所述走线层设于所述第二平坦层远离所述衬底的一侧；
    各所述晶体管的沟道均位于所述半导体层。
  13. 根据权利要求12所述的显示面板，其中，在一所述像素电路及其连接的数据线和电源线中，所述像素电路包括第一复位晶体管、补偿晶体管、驱动晶体管、写入晶体管、第一发光控制晶体管、第二发光控制晶体管、第二复位晶体管以及存储电容；
    所述第一复位晶体管的第一极用于接收第一复位信号，第二极与所述驱动晶体管的栅极和所述存储电容的第一极板连接；
    所述补偿晶体管的第一极与所述驱动晶体管的第二极连接，第二极与所述驱动晶体管的栅极连接；所述补偿晶体管具有串联的两个沟道；
    所述写入晶体管的第一极与一所述数据线连接，第二极与所述驱动晶体管的第一极连接；
    所述第一发光控制晶体管的第一极和所述存储电容的第二极板与以所述电源线连接，第二极与所述驱动晶体管的第一极连接；
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，第二极通过一所述转接部与一所述第一电极连接。
    所述第二复位晶体管的第一极用于接收第二复位信号，第二极与所述第二发光控制晶体管的第二极连接；
    所述第一栅极层包括所述各所述晶体管的栅极和所述存储电容的第一极板；所述第二栅极层包括所述存储电容的第二极板、遮挡块和屏蔽块；所述源漏层包括连接所述补偿晶体管的第二极和所述驱动晶体管的栅极的连接部，所述连接部和所述驱动晶体管的栅极位于所述数据线的同一侧；
    所述遮挡块的至少部分区域与所述补偿晶体管的两个沟道之间的半导体层交叠；所述屏蔽块至少部分位于所述数据线和所述连接部之间，且所述屏蔽块与所述电源线连接。
  14. 根据权利要求6或11所述的显示面板，其中，所述显示面板包括显示区，所述显示区包括副显示区和位于副显示区外的主显示区；所述发光器件分布于所述主显示区和所述副显示区；
    连接所述副显示区内的至少部分发光器件的像素电路位于所述主显示区，且通过导电线与所述发光器件连接；
    所述电路层还包括导电层和绝缘层，所述导电层设于所述钝化层远离所述衬底的一侧，所述绝缘层覆盖所述导电层，所述第二平坦层覆盖所述绝缘层；所述导电层包括所述导电线。
  15. 根据权利要求14所述的显示面板，其中，所述导电层还包括位于所述显示区的多个搭接部，一所述像素电路通过一所述搭接部与所述 电源线连接。
  16. 一种显示装置，包括权利要求1-15任一项所述的显示面板。
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