WO2021103504A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021103504A1
WO2021103504A1 PCT/CN2020/097124 CN2020097124W WO2021103504A1 WO 2021103504 A1 WO2021103504 A1 WO 2021103504A1 CN 2020097124 W CN2020097124 W CN 2020097124W WO 2021103504 A1 WO2021103504 A1 WO 2021103504A1
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WIPO (PCT)
Prior art keywords
sub
pixel
orthographic projection
base substrate
repeating
Prior art date
Application number
PCT/CN2020/097124
Other languages
English (en)
French (fr)
Inventor
王蓉
张波
董向丹
舒晓青
都蒙蒙
杨双宾
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from PCT/CN2019/122201 external-priority patent/WO2021103010A1/zh
Priority claimed from PCT/CN2019/122156 external-priority patent/WO2021102988A1/zh
Priority claimed from PCT/CN2019/122184 external-priority patent/WO2021102999A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/416,078 priority Critical patent/US20220077244A1/en
Priority to CN202080001059.6A priority patent/CN114679914B/zh
Priority to EP20892526.3A priority patent/EP4068381A4/en
Publication of WO2021103504A1 publication Critical patent/WO2021103504A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • AMOLED Active-matrix organic light emitting diode
  • a display substrate including: a base substrate; and a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels including: a first metal layer located on the On the base substrate, the first metal layer includes a plurality of first power lines; a first flat layer is located on a side of the first metal layer away from the base substrate; and a first electrode layer is located on the side of the base substrate.
  • the first flat layer is on a side away from the first metal layer and has a plurality of first electrodes spaced apart from each other; and a pixel defining layer located on a side of the first electrode layer away from the first flat layer Side, and has a plurality of openings corresponding to the plurality of first electrodes one-to-one and exposing the plurality of first electrodes, and the plurality of openings correspond to at least two sub-pixels of different colors, wherein the plurality of The orthographic projection of one of the first power lines on the base substrate separates the orthographic projection of one of the plurality of openings on the base substrate to be located on the first side of the first power line.
  • the first part and the second part located on the second side of the first power line, for at least two sub-pixels of different colors, the area ratio between the first part of the orthographic projection of the opening and that of the orthographic projection of the opening
  • the ratio between the area ratios between the second parts is in the range of 0.8-1.2.
  • the at least two different color sub-pixels include a first sub-pixel of a first color
  • the first power line extends along a first direction
  • the first portion and the second portion are along a first direction.
  • the plurality of first power lines include first sub-power lines arranged in parallel to each other, and the first sub-power lines are on the base substrate
  • the orthographic projection of the first sub-pixel divides the opening orthographic projection corresponding to the first sub-pixel into a first part and a second part
  • the first sub power line includes a first repeating part and a second repeating part that are sequentially connected as repeating units, so
  • the orthographic projections of the first sub-pixels on the base substrate overlap with the orthographic projections of the first and second repetitive parts of the corresponding first sub-power lines on the base substrate, respectively, and the first sub-pixel
  • the first sub-pixel of the first color includes a red sub-pixel (R) and/or a blue sub-pixel (B), and the central axis of the first repeating part is relative to the second repeating part.
  • the central axis of the part is far away from the second part (R2, B2) of the orthographic projection of the corresponding opening of the red sub-pixel (R) and/or the blue sub-pixel (B), and the first repeated part is close to the
  • the red sub-pixel (R) and/or the blue sub-pixel (B) are hollowed out on one side of the second part (R2, B2) corresponding to the orthographic projection of the opening.
  • the at least two sub-pixels of different colors further include a second sub-pixel of a second color that is different from the first color of the first sub-pixel
  • the plurality of first power lines further include A second sub-power supply line alternately arranged in parallel with the first sub-power supply line, the second sub-power supply line includes a third repeating part, a fourth repeating part, and a fifth repeating part that are sequentially connected as repeating units, so
  • the orthographic projections of the second sub-pixels on the base substrate overlap with the orthographic projections of the fourth and fifth repetitive parts of the corresponding second sub-power lines on the base substrate, respectively, and the first
  • the overlap area of the orthographic projection of the two sub-pixels on the base substrate and the orthographic projection of the fifth repeating portion on the base substrate is larger than the orthographic projection of the second sub-pixels on the base substrate
  • the overlap area with the orthographic projection of the fourth repeating part on the base substrate is larger than the orthographic projection of the second sub-pixels on the base substrate.
  • the sub-pixels of at least two different colors further include a third sub-pixel that is the same as the second color of the second sub-pixel, and the third sub-pixel is located on the base substrate.
  • the orthographic projection overlaps with the orthographic projection of the fifth repeating portion of the corresponding second sub power line on the base substrate.
  • the second sub-pixel and the third sub-pixel of the second color include green sub-pixels, the central axis of the third repeating part, the central axis of the fourth repeating part, and the fifth
  • the central axis of the repeated part is in turn close to the second part (G2) of the green sub-pixel (G) corresponding to the opening orthographic projection
  • the third repeated part is close to the second part (G2) of the green sub-pixel (G) corresponding to the opening orthographic projection.
  • the second part (G2) is hollowed out on one side
  • the fifth repeated part is hollowed out on the side away from the second part (G2) of the orthographic projection of the corresponding opening of the green sub-pixel (G).
  • the line width of the first repeating part is between 3 ⁇ m and 4.6 ⁇ m
  • the line width of the second repeating part is between 4.5 ⁇ m and 6.9 ⁇ m
  • the line width of the third repeating part is between 4.5 ⁇ m and 6.9 ⁇ m.
  • the line width of the fourth repeating part is between 5.3 ⁇ m and 8.1 ⁇ m
  • the line width of the fifth repeating part is between 2.4 ⁇ m and 3.6 ⁇ m.
  • the line width of the first repeating part is 3.8 ⁇ m
  • the line width of the second repeating part is 5.7 ⁇ m
  • the line width of the third repeating part is 3.8 ⁇ m
  • the line width of the fourth repeating part is 3.8 ⁇ m.
  • the line width of the fifth repeating part is 6.7 ⁇ m
  • the line width of the fifth repeating part is 3.0 ⁇ m.
  • the display substrate further includes: a second metal layer located on the base substrate, including a plurality of second power lines, the plurality of second power lines extending along the first direction , And the orthographic projection of the plurality of first power lines on the base substrate and the orthographic projection of the plurality of second power lines on the base substrate are in a direction perpendicular to the base substrate Respectively at least partially overlap; a second flat layer, which is located on the second metal layer, the first metal layer is located on the second flat layer, and the plurality of first power lines and the plurality of The second power line is connected through a via hole penetrating the second flat layer.
  • the display substrate further includes a plurality of third power lines, wherein the plurality of third power lines extend along the second direction and electrically connect the plurality of first power lines,
  • the orthographic projection of the plurality of third power lines on the base substrate and the orthographic projection of the opening of each sub-pixel on the base substrate do not overlap in a direction perpendicular to the base substrate.
  • a third power line is arranged on the same layer as the first power line and is an integrated structure.
  • each of the plurality of third power supply lines includes a third sub-power supply line and a fourth sub-power supply line that are sequentially connected as repeating units, and the third sub-power supply line and the fourth sub-power supply line are sequentially connected.
  • the sub-power supply lines alternately extend along the second direction, and the plurality of third power supply lines are arranged along the first direction; the third sub-power supply line includes a sixth repeating part and a first repeating unit that are sequentially connected as repeating units.
  • the extension direction of the seventh repeating part is parallel to the second direction, and the extension direction of the sixth repeating part intersects both the first direction and the second direction,
  • the extension direction of the eighth repeating part intersects the first direction and the second direction and is different from the extension direction of the sixth repeating part;
  • the fourth power line includes a ninth repeating part and a tenth repeating part.
  • the extension direction of the ninth repeating part is parallel to the second direction, and the extension direction of the tenth repeating part intersects both the first direction and the second direction.
  • the at least two different color sub-pixels include a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel (G), and the red sub-pixel (R) and the The blue sub-pixels (B) are alternately arranged along the first direction and the second direction, and along the first direction, the fourth sub-power supply line is located in the second part of the red sub-pixel (R) (R2) between the orthographic projection on the base substrate and the second portion (R2) of the adjacent blue sub-pixel (B) on the orthographic projection on the base substrate; the green sub-pixel The pixels (G) are arranged along the first direction and the second direction, and along the first direction, the third sub-power supply line is located in the second part (G2) of the adjacent green sub-pixel (G). ) Between the orthographic projections on the base substrate.
  • one pixel includes a red sub-pixel (R) and a blue sub-pixel (B), and the openings corresponding to the red sub-pixel (R) and the blue sub-pixel (B) are corresponding to each other.
  • the projections are divided into corresponding first and second parts by the orthographic projection of the first power line on the base substrate, and the first part (R1) of the orthographic projection of the opening corresponding to the red sub-pixel (R) is separated from
  • the area ratio of the first part (B1) of the aperture orthographic projection corresponding to the blue sub-pixel (B) is R1/B1
  • the second part (R2) of the aperture orthographic projection corresponding to the red sub-pixel (R) is
  • one pixel includes a red sub-pixel (R) and a green sub-pixel (G), and the first part (R1) of the orthographic projection of the opening corresponding to the red sub-pixel (R) is in relation to the green sub-pixel (G).
  • the area ratio of the first part (G1) of the corresponding aperture orthographic projection is R1/G1
  • one pixel includes a blue sub-pixel (B) and a green sub-pixel (G), and the first part (B1) of the orthographic projection of the opening corresponding to the blue sub-pixel (B) is the same as the green sub-pixel.
  • the area ratio of the first part (G1) of the corresponding aperture orthographic projection is B1/G1
  • one pixel includes a red sub-pixel (R), a first green sub-pixel (G'), and a second green sub-pixel (G"), and the corresponding opening of the red sub-pixel (R) is orthographically projected
  • the first part (R1) is the first part (G'1) of the opening orthographic projection corresponding to the first green sub-pixel (G') and the first part of the opening orthographic projection corresponding to the second green sub-pixel (G")
  • the area ratio between the sum of (G”2) is R1/(G'1+G”1), and the second part (R2) of the orthographic projection of the opening corresponding to the red sub-pixel (R), and the The second part (G'2) of the aperture orthographic projection corresponding to the first green sub-pixel (G') and the second part (G"2) of the aperture orthographic projection corresponding to the second green sub-pixel (G")
  • one pixel includes a blue sub-pixel (B), a first green sub-pixel (G'), and a second green sub-pixel (G"), and the corresponding opening of the blue sub-pixel (B) is positive
  • the area ratio between the sum of the first part (G”1) of the blue sub-pixel (B) is B1/(G'1+G”1), and the second part (B2) of the orthographic projection of the opening corresponding to the blue sub-pixel (B),
  • the area ratio between the sum of 2) is B2/(G'2+G”2), where B1/(G'1+G”
  • each of the plurality of sub-pixels includes a pixel circuit for driving the light-emitting element to emit light; the plurality of pixel circuits of the plurality of sub-pixels are distributed along the first direction and the second direction as Multiple rows and multiple columns; the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit; the driving sub-circuit includes a control terminal, a first terminal and a second terminal, and is configured to The light-emitting element is coupled to and controls the driving current flowing through the light-emitting element; the data writing sub-circuit includes a control terminal, a first terminal and a second terminal, and the control terminal of the data writing sub-circuit is configured to receive the first scan Signal, the first end of the data writing sub-circuit is configured to receive a data signal, the second end of the data writing sub-circuit is electrically connected to the driving sub-circuit, and the data writing sub-circuit is configured
  • a power supply line is coupled; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are directly adjacent in the second direction, and the first capacitor electrode in the first sub-pixel is connected to the second sub-pixel.
  • the first capacitor electrodes in the sub-pixels are arranged in the same layer and spaced apart from each other.
  • the display substrate further includes a plurality of data lines extending along the first direction, and the plurality of data lines are configured to provide data signals to the sub-pixels.
  • the plurality of second power lines and the plurality of data lines are insulated in the same layer.
  • each sub-pixel further includes a light-emitting element, the light-emitting element includes the first electrode, the light-emitting layer, and the second electrode stacked in sequence, and the first electrode is located on the light-emitting layer near the substrate.
  • the orthographic projection of the third power line on the base substrate and the orthographic projection of the first electrode of each sub-pixel on the base substrate are perpendicular to the base substrate The directions do not overlap.
  • a display device including the above-mentioned display substrate.
  • a method for manufacturing a display substrate including: providing a base substrate; forming a plurality of sub-pixels on the base substrate, wherein each of the plurality of sub-pixels One includes: a first metal layer, which is located on the base substrate, the first metal layer includes a plurality of first power lines; a first flat layer, which is located on the first metal layer away from the base substrate A first electrode layer, which is located on the side of the first flat layer away from the first metal layer, and has a plurality of first electrodes spaced apart from each other; and a pixel defining layer, which is located on the first An electrode layer is far away from the first flat layer, and has a plurality of openings corresponding to the plurality of first electrodes and exposing the plurality of first electrodes, and the plurality of openings correspond to at least two Sub-pixels of different colors, wherein the orthographic projection of one of the plurality of first power lines on the base substrate separates the orthographic projection of one of
  • the openings for the sub-pixels of different colors are realized by adjusting the width of the first power line corresponding to the position of the plurality of openings in the area where the orthographic projection of the base substrate is located, and the orthographic projection of the openings
  • the ratio of the area ratio between the first part and the area ratio between the second part of the orthographic projection of the opening is in the range of 0.8-1.2.
  • the corresponding first power line is adjusted to be in contact with the plurality of openings.
  • the width of the opening outside the corresponding position of the area where the orthographic projection of the base substrate is located.
  • the first power line is formed to extend in a first direction, the first part and the second part are arranged in a second direction, the first direction and the second direction intersect, the The at least two different color sub-pixels include red sub-pixels (R), blue sub-pixels (B), and green sub-pixels (G), and the plurality of first power supply lines include first sub-power supply lines alternately arranged in parallel to each other And the second sub-power line, the orthographic projection of the first sub-power line on the base substrate separates the red sub-pixel (R) and the blue sub-pixel (B) corresponding to the opening orthographic projection into the first part (R1 , B1) and the second part (R2, B2), the orthographic projection of the second sub-power line on the base substrate separates the opening orthographic projection corresponding to the green sub-pixel (G) into the first part (G1) and The second part (G2), the first sub power line includes a first repeating part and a second repeating part as repeating units connected in sequence, and the central
  • the central axis is far away from the second part (R2, B2) of the orthographic projection of the corresponding openings of the red sub-pixel (R) and the blue sub-pixel (B) and the first repeated part is close to the red sub-pixel ( R) and the blue sub-pixel (B) are hollowed out on one side of the second part (R2, B2) of the orthographic projection of the opening corresponding to the red sub-pixel (R) and the blue sub-pixel (B)
  • the orthographic projections on the base substrate overlap with the orthographic projections of the first and second repetitive parts of the corresponding first sub power lines on the base substrate respectively; the second sub power lines include sequential connections
  • the third repeating part, the fourth repeating part and the fifth repeating part as the repeating unit, the central axis of the third repeating part, the central axis of the fourth repeating part and the central axis of the fifth repeating part are in sequence Close to the second part (G2) of the orthographic projection of the corresponding opening of the green sub-pixel (G), and
  • the fifth repeating part is hollowed out on the side away from the second part (G2) of the orthographic projection of the corresponding opening of the green sub-pixel (G), and the green sub-pixel (G) is hollowed out on the base substrate
  • the orthographic projection on the corresponding second sub-power line is the fourth and fifth repetitive portion on the substrate or the corresponding second sub-power line’s fifth repetitive portion on the substrate.
  • the orthographic projections on the substrate overlap.
  • the line width of the first repeating part is 3.8 ⁇ m
  • the line width of the second repeating part is 5.7 ⁇ m
  • the line width of the third repeating part is 3.8 ⁇ m
  • the line width of the fourth repeating part is 3.8 ⁇ m.
  • the line width of the fifth repeating part is 6.7 ⁇ m
  • the line width of the fifth repeating part is 3.0 ⁇ m.
  • FIG. 1A is a schematic diagram of a partial structure of a display substrate in the related art
  • 1B is a schematic diagram showing the warpage of the opening of the substrate
  • FIG. 2 is a schematic diagram of a display substrate according to an embodiment of the present disclosure
  • 3A is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • 3B is a schematic diagram of a pixel circuit structure of a display substrate according to an embodiment of the present disclosure
  • 3C is a pixel circuit diagram of a display substrate according to an embodiment of the present disclosure.
  • 4A-4D are schematic diagrams of various layers of a pixel circuit according to an embodiment of the present disclosure.
  • Fig. 4E is a cross-sectional view of Fig. 4D along the section line C-C';
  • Figure 4F is a cross-sectional view of Figure 4D along the section line C'-C";
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram of a part of the structure according to an embodiment of the present disclosure.
  • Figure 6 is a cross-sectional view of Figure 5 along the section line A-A';
  • FIG. 7 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Fig. 8A is a cross-sectional view of Fig. 2 along the section line B-B';
  • FIG. 8B is a circuit diagram of a pixel in a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a first capacitor electrode according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1A is a schematic diagram of a part of the structure of a display substrate in the related art
  • FIG. 1B is a schematic diagram of the opening warpage of the display substrate in FIG. 1A.
  • FIG. 1A shows the sub-pixel opening and the power supply line under it. Since the flat layer and the pixel defining layer are sequentially arranged on the power signal line, the opening of the pixel defining layer is divided into two parts by the superimposed power signal line. Due to the presence of the power signal line, there is a height difference under the opening, which may cause the organic light-emitting material in the opening to warp on the side of the opening that is divided into two parts with a smaller area (indicated by the dotted line), resulting in Color casts appear.
  • Figure 1B shows the warpage at the pixel opening.
  • a flat layer 16 is provided on the power signal line 15
  • an anode 17 of a light-emitting element is provided on the flat layer 16
  • a pixel defining layer 18 is provided on the anode 17.
  • the pixel defining layer 18 has an opening 181, the anode 17 is exposed at the opening 181, and the organic light-emitting material layer 19 is located on the anode 17 exposed by the opening 181.
  • the presence of the power signal line 15 causes the anode 17 to warp, which in turn causes the organic light-emitting material layer 19 to warp, resulting in a mismatch in the light intensity emitted by the light-emitting regions on the left and right sides of the sub-pixels of different colors.
  • Figure 1A shows the positional relationship between the power signal line 15 and the opening 181, where the four openings G1 (first green), G2 (second green), R (red), and B (blue) are respectively used
  • the four-color organic light-emitting layers are used to form sub-pixels of corresponding colors, and are repeatedly arranged on the display panel as repeating units.
  • each opening 181 is divided into left and right parts by the power signal line 15, for example, divided into left and right parts with unequal areas, where the area of the left part is smaller than the area of the right part.
  • the power signal line 15 has different widths at different positions, for example, the power signal line 15 has a width of 6.7 ⁇ m at the first position and a width of 4.3 ⁇ m at the second position.
  • the first direction D1 and the second direction D2 cross for example, are orthogonal.
  • a display device using such a display substrate may have a large visual role shift, and when viewed by human eyes, a color shift similar to that of red on one side and cyan on the other side appears.
  • a dual power line pixel structure is usually adopted, that is, to reduce the load, another layer of power line is usually superimposed on the power signal line.
  • another layer of power lines is arranged above or below the power signal line 15, and the two are separated by an insulating layer and connected by vias in the insulating layer.
  • the present disclosure takes a dual power line pixel structure as an example. Be explained.
  • the display substrate includes: a base substrate; and a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels including: A metal layer located on the base substrate, the first metal layer including a plurality of first power lines; a first flat layer located on the side of the first metal layer away from the base substrate; A first electrode layer, which is located on the side of the first flat layer away from the first metal layer, and has a plurality of first electrodes spaced apart from each other; and a pixel defining layer, which is located away from the first electrode layer
  • One side of the first flat layer has a plurality of openings corresponding to the plurality of first electrodes and exposing the plurality of first electrodes, the plurality of openings corresponding to at least two different colors Sub-pixels.
  • the orthographic projection of one of the plurality of first power lines on the base substrate divides the orthographic projection of one of the plurality of openings on the base substrate into the first power source
  • the first part on the first side of the line and the second part on the second side of the first power line, for at least two different color sub-pixels, the area ratio between the first part orthographically projected by the opening is
  • the ratio between the area ratios of the second parts of the orthographic projection of the openings is in the range of 0.8-1.2. This ratio range can make it impossible for human eyes to distinguish the color shift caused by the different light mixing ratios on both sides, that is, improve the color shift of the display panel.
  • the first power supply line extends along the direction D1
  • a plurality of first power supply lines are arranged along the direction D2
  • the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G are on the base substrate.
  • the orthographic projection on the above is divided into first parts R1, B1, G1 by the first power line respectively, where the green sub-pixel G includes a first green sub-pixel G'and a second green sub-pixel G", and the first green sub-pixel G 'And the second green sub-pixel G" are also separated by the first power line into a first part G'1, G"1 and a second part G'2, G"2, respectively.
  • the two parts of each sub-pixel separated by the first power line are arranged along the D2 direction.
  • the first part G'1, G"1, R1, B1 is located on the first side of the first power line
  • the second part G'2, G"2, R2, B2 is located on the second side of the first power line.
  • the display substrate 20 includes a plurality of sub-pixels 100, a plurality of gate lines 11, and a plurality of data lines 12 distributed in an array.
  • Each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element.
  • a plurality of gate lines 11 and a plurality of data lines 12 cross each other to define a plurality of pixel regions distributed in an array in the display region, and a pixel circuit of a sub-pixel 100 is provided in each pixel region.
  • the pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (that is, two transistors and a capacitor) pixel circuit, 4T2C, 5T1C, 7T1C and other nTmC (n, m are positive integers) pixel circuits, and in different embodiments,
  • the pixel circuit may further include a compensation sub-circuit.
  • the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit.
  • the compensation sub-circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, and the like.
  • the display substrate may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area.
  • the gate driving sub-circuit 13 is connected to the pixel circuit through the gate line 11 to provide various scanning signals
  • the data driving sub-circuit 14 is connected to the pixel circuit through the data line 12 to provide data signals.
  • the gate driving sub-circuit 13 and the data driving sub-circuit 14 shown in FIG. 3A, the positional relationship of the gate line 11 and the data line 12 in the display substrate are just examples, and the actual arrangement position can be designed according to needs.
  • the display substrate 20 may further include a control circuit (not shown).
  • the control circuit is configured to control the data driving sub-circuit 14 to apply the data signal and the gate driving sub-circuit to apply the scan signal.
  • An example of this control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, for example, including a processor and a memory.
  • the memory includes executable code, and the processor runs the executable code to execute the above detection method.
  • the processor may be a central processing unit (CPU) or other form of processing device with data processing capability and/or instruction execution capability, for example, may include a microprocessor, a programmable logic controller (PLC), and the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • the storage device may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include random access memory (RAM) and/or cache memory (cache), for example.
  • the non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions can be stored on a computer-readable storage medium, and the processor can execute functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit, and may also include a light-emission control sub-circuit, a reset circuit, etc., as required.
  • Fig. 3B shows a schematic diagram of a pixel circuit.
  • the pixel circuit includes a driving sub-circuit 122, a data writing sub-circuit 126, a compensation sub-circuit 128, a storage sub-circuit 127, a first light-emission control sub-circuit 123, a second light-emission control sub-circuit 124, and a reset circuit. 129.
  • the driving sub-circuit 122 includes a control terminal 131, a first terminal 132, and a second terminal 133, which are configured to control the driving current flowing through the light-emitting element 120, and the control terminal 131 of the driving sub-circuit 122 is connected to the first node N1,
  • the first terminal 132 of the driving sub-circuit 122 is connected to the second node N2, and the second terminal 133 of the driving sub-circuit 122 is connected to the third node N3.
  • the data writing sub-circuit 126 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the first scan signal
  • the first terminal is configured to receive the data signal
  • the second terminal is connected to the second terminal of the driving sub-circuit 122.
  • One end 132 (the second node N2) is connected, and is configured to write the data signal into the first end 132 of the driving sub-circuit 122 in response to the first scan signal Ga1.
  • the first terminal of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal
  • the control terminal is connected to the scan line 11 to receive the first scan signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written to the first terminal 132 (the second node N2) of the driving sub-circuit 122, and
  • the data signal is stored in the storage sub-circuit 127, so that a driving current for driving the light-emitting element 120 to emit light can be generated according to the data signal during the light-emitting phase, for example.
  • the compensation sub-circuit 128 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the second scan signal Ga2.
  • the first terminal and the second terminal are respectively connected to the control terminal 131 and the second terminal of the driving sub-circuit 122.
  • the two terminals 133 are electrically connected, and the compensation sub-circuit is configured to perform threshold compensation on the driving sub-circuit 120 in response to the second scan signal.
  • the storage sub-circuit 127 is electrically connected to the control terminal 131 and the first voltage terminal VDD of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126.
  • the compensation sub-circuit 128 may be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127.
  • the compensation sub-circuit 128 can electrically connect the control terminal 131 and the second terminal 133 of the driving sub-circuit 122, so that the threshold voltage related information of the driving sub-circuit 122 can be stored accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting phase, so that the output of the driving sub-circuit 122 is compensated.
  • the first light-emitting control sub-circuit 123 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122 and the first voltage terminal VDD, and is configured to reduce the voltage of the first voltage terminal VDD in response to the first light-emitting control signal.
  • the first power supply voltage is applied to the first terminal 132 of the driving sub-circuit 122.
  • the first light emission control sub-circuit 123 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.
  • the second light-emitting control sub-circuit 124 and the second light-emitting control terminal EM2 are connected, and are configured to drive current in response to the second light-emitting control signal. It can be applied to the light emitting element 122.
  • the second light-emission control sub-circuit 123 is turned on in response to the second light-emission control signal provided by the second light-emission control terminal EM2, so that the driving sub-circuit 122 can be electrically connected to the light-emitting element 120 through the second light-emission control sub-circuit 123 Is connected to drive the light-emitting element 120 to emit light under the control of the driving current; and in the non-light-emitting phase, the second light-emitting control sub-circuit 123 is turned off in response to the second light-emitting control signal, so as to avoid current flowing through the light-emitting element 120 to cause it to emit light , Can improve the contrast of the corresponding display device.
  • the second light-emitting control sub-circuit 124 can also be turned on in response to the second light-emitting control signal, so that the reset circuit can be combined with the reset circuit to perform a reset operation on the driving sub-circuit 122 and the light-emitting element 120.
  • the second light emission control signal EM2 can be the same as or different from the first light emission control signal EM1, for example, the two can be connected to the same or different signal output terminals.
  • the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light emitting element 122, and is configured to apply a reset voltage to the first terminal 134 of the light emitting element 120 in response to a reset signal.
  • the reset signal may also be applied to the control terminal 131 of the driving sub-circuit, that is, the first node N1.
  • the reset signal is the second scan signal, and the reset signal may also be another signal synchronized with the second scan signal, which is not limited in the embodiment of the present disclosure. For example, as shown in FIG.
  • the reset circuit 129 is respectively connected to the first terminal 134 of the light emitting element 120, the reset voltage terminal Vinit, and the reset control terminal Rst (reset control line).
  • the reset circuit 129 can be turned on in response to a reset signal, so that a reset voltage can be applied to the first terminal 134 and the first node N1 of the light-emitting element 120, so that the driving sub-circuit 122 and the compensation sub-circuit 128 can be And the light-emitting element 120 performs a reset operation to eliminate the influence of the previous light-emitting stage.
  • the light-emitting element 120 includes a first end 134 and a second end 135.
  • the first end 134 of the light-emitting element 120 is configured to be coupled to the second end 133 of the driving sub-circuit 122, and the second end 135 of the light-emitting element 120 is configured to be coupled to The second voltage terminal VSS is connected.
  • the first end 134 of the light-emitting element 120 may be connected to the third node N3 through the second light-emitting control sub-circuit 124.
  • the embodiments of the present disclosure include but are not limited to this situation.
  • the light-emitting element 120 can be various types of OLEDs, such as top-emission, bottom-emission, double-side emission, etc., which can emit red light, green light, blue light, or white light.
  • the first electrode and the second electrode of the OLED serve as The first end 134 and the second end 135 of the light-emitting element.
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but rather represent the connections of related circuits in the circuit diagram. Meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can both represent the first scan signal and the second scan signal.
  • the signal can also represent the first scan signal terminal and the second scan signal terminal.
  • Rst can represent both the reset control terminal and the reset signal.
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage.
  • the symbol VDD can both represent the first A voltage terminal can also represent the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 3C is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 3B.
  • the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving sub-circuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 131 of the driving sub-circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 132 of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the first transistor T1 serves as the second terminal 133 of the driving sub-circuit 122 and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first pole of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal ,
  • the second pole of the second transistor T2 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122.
  • the second transistor T2 is a P-type transistor, for example, the active layer is a thin film transistor with low-temperature doped polysilicon.
  • the compensation sub-circuit 128 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first pole of the third transistor T3 and the control terminal 131 (first The node N1) is connected, and the second electrode of the third transistor T3 is connected to the second end 133 (third node N3) of the driving sub-circuit 122.
  • the storage sub-circuit 127 may be implemented as a storage capacitor Cst.
  • the storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb.
  • the first capacitor electrode Ca is coupled to the first voltage terminal VDD.
  • the second capacitor electrode Cb and the control terminal 131 of the driving sub-circuit 122 are coupled, such as electrical connection.
  • the first light emission control sub-circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first emission control line (first emission control terminal EM1) to receive the first emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply Voltage, the second pole of the fourth transistor T4 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122.
  • the light-emitting element 120 may be embodied as an OLED, and the first electrode 134 (here, the anode) and the fourth node N4 are connected and configured to receive the driving current from the second end 133 of the driving sub-circuit 122 through the second light-emitting control sub-circuit 124
  • the second electrode 135 (here, the cathode) of the light-emitting element 120 is configured to be connected to the second voltage terminal VSS to receive the second power voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second light emission control sub-circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second emission control line (the second emission control terminal EM2) to receive the second emission control signal.
  • the first pole of the fifth transistor T5 and the second terminal 133 are connected to receive the second emission control signal.
  • the three nodes N3) are connected, and the second electrode of the fifth transistor T5 is connected to the first end 134 (fourth node N4) of the light-emitting element 120.
  • the reset circuit 129 may include a first reset circuit configured to apply a first reset voltage Vini1 to the first node N1 in response to a first reset signal Rst1 and a second reset circuit configured to The second reset voltage Vini2 is applied to the fourth node N4 in response to the second reset signal Rst2.
  • the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset signal Rst1, and the first pole of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1.
  • the second pole of the six transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, and the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2.
  • the second pole of the seven transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • FIG. 2 is a schematic diagram of a display substrate 20 according to an embodiment of the present disclosure.
  • the display substrate 20 includes a base substrate 101 on which a plurality of sub-pixels 100 are located.
  • the pixel circuits of the plurality of sub-pixels 100 are arranged as a pixel circuit array.
  • the column direction of the pixel circuit array is the first direction D1, the row direction is the second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonally.
  • the first direction D1 may also be a row direction
  • the second direction D2 may also be a column direction.
  • the pixel circuit of each sub-pixel may have exactly the same structure except for the connection structure with the light-emitting element, that is, the pixel circuit is repeatedly arranged in the row and column directions, and the connection structure of the different sub-pixels with the light-emitting element is based on The arrangement shape and position of the electrode of the light emitting structure of each sub-pixel may be different.
  • the general frame of the pixel circuit of the sub-pixels of different colors for example, the shape and position of each signal line is basically the same, and the relative positional relationship of each transistor is also basically the same.
  • FIG. 2 exemplarily shows four sub-pixels (ie, the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d) that are directly adjacent to each other in a row of sub-pixels.
  • the embodiment is not limited to this layout.
  • FIG. 4A corresponds to FIG. 2 and illustrates the semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 in the four sub-pixels 100.
  • FIG. 4B also shows the second conductive layer (gate layer) 201 based on FIG. 4A.
  • FIG. 4C also shows a third conductive layer 203 on the basis of FIG. 4B, and
  • FIG. 4D also shows a fourth conductive layer 204 on the basis of FIG. 4C. It should be noted that the figure only schematically shows the corresponding structure of four adjacent sub-pixels in a row of sub-pixels, but this should not be regarded as a limitation of the present disclosure.
  • the semiconductor layer 102, the first conductive layer 201, the second conductive layer 202, the third conductive layer 203, and the fourth conductive layer 204 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 2.
  • Tng, Tns, Tnd, and Tna are used to denote the gate, the first electrode, the second electrode, and the active layer of the n-th transistor Tn, respectively, where n is 1-7.
  • the “same layer arrangement” in the present disclosure refers to a structure formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different.
  • the "integrated structure” in the present disclosure refers to two (or more than two) structures that are formed by the same deposition process and patterned by the same patterning process, and their materials can be the same or different. .
  • the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines.
  • a large dashed frame shows the area where each sub-pixel 100 is located, and a small dashed frame shows the gates T1g-T7g of the first to seventh transistors T1-T7 in one sub-pixel 100.
  • the semiconductor layer 102 includes the active layers T1a-T7a of the first to seventh transistors T1-T7. As shown in FIG. 4A, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integral structure. For example, the semiconductor layer 20 in each column of sub-pixels is an integrated structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.
  • the first conductive layer 201 includes gates T1g-T7g of the first to seventh transistors T1-T7.
  • the third transistor T3 and the sixth transistor T6 adopt a double gate structure, which can improve the gate control capability of the transistor and reduce the leakage current.
  • the first conductive layer 201 further includes a plurality of scan lines 210, a plurality of reset control lines 220, and a plurality of light-emitting control lines 230 that are insulated from each other.
  • each row of sub-pixels is respectively connected to a scan line 210, a reset control line 220, and a light emission control line 230.
  • the scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide the first scan signal Ga1, and the reset control line 220 is connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels.
  • the gate is electrically connected to provide the first reset signal Rst1
  • the emission control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 may be the same signal;
  • the control line 230 is also electrically connected to the gate of the fifth transistor T5 to provide the second light emission control signal EM2, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal.
  • the gate of the seventh transistor T7 of the pixel circuit of the current row and the pixel circuit of the next row (that is, according to the scanning order of the scan line, the pixel circuit row where the scan line is sequentially turned on after the scan line of the current row is located )
  • the corresponding reset control line 220 is electrically connected to receive the second reset signal Rst2.
  • the gate line 11 dividing the pixel area in the column direction (first direction D1) can be the reset control line 220 or the light emission control line 230, and each pixel circuit area includes a reset control line 220. , Each part of a light-emitting control line 230 and a scan line 210.
  • the display substrate 20 adopts a self-aligned process, using the first conductive layer 201 as a mask to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102, so that the semiconductor layer 102 is not
  • a conductive treatment for example, doping treatment
  • the portion covered by the first conductive layer 201 is conductive, so that the portions of the active layer of each transistor located on both sides of the channel region are conductive to form the first electrode and the second electrode of the transistor, respectively.
  • the second conductive layer 202 includes a first capacitor electrode Ca.
  • the first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in the direction perpendicular to the base substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the first transistor of the storage capacitor Cst.
  • the first capacitor electrode Ca includes a via 301 that exposes at least part of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.
  • the second conductive layer 202 may further include a plurality of reset voltage lines 240, and the plurality of reset voltage lines 240 are connected to a plurality of rows of sub-pixels in a one-to-one correspondence.
  • the reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1.
  • the first pole of the seventh transistor T7 in the sub-pixels of the current row is electrically connected to the reset voltage line 240 corresponding to the sub-pixels of the next row to receive the second reset voltage Vinit2.
  • the second conductive layer 202 may further include a shielding electrode 221 that overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 so as to protect the The signal in the first pole T2s of the second transistor T2 is not interfered by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display gray scale of the sub-pixel, the shield electrode 221 improves the stability of the data signal, thereby improving the display performance.
  • the third conductive layer 203 includes a plurality of second power lines 250 extending along the first direction D1 (the plurality of second power lines 250 correspond to the second metal layer).
  • the plurality of second power lines 250 are electrically connected to the plurality of columns of sub-pixels in a one-to-one correspondence to provide the first power voltage VDD.
  • the second power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via hole 302, and is electrically connected to the first electrode of the fourth transistor T4 through the via hole 303.
  • the second power line 250 is also electrically connected to the shield electrode 221 through the via 304, so that the shield electrode 221 has a fixed potential, which improves the shielding ability of the shield electrode.
  • the third conductive layer 203 further includes the plurality of data lines 12.
  • the multiple data lines 12 are electrically connected to multiple columns of sub-pixels in a one-to-one correspondence to provide data signals.
  • the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in the corresponding column of sub-pixels through the via 305 to provide the data signal.
  • the vias are usually arranged in the row and column direction, the vias 304 and the vias 305 are approximately on the same straight line in the row direction, and the vias 304 are located between the data lines 12 and
  • the connection via 305 of the first electrode T2s of the second transistor T2 is away from the side of the data line 12.
  • the via 305 is located at a position where the data line overlaps the first electrode T2s of the second transistor T2 (for example, the end of the first electrode T2s of the second transistor T2, that is, the end of the semiconductor layer 102 on the left side).
  • the hole 304 is located at a position covered by the second power cord 250.
  • the data line 12 is located on the left side of the second power line 250, and extends in the column direction with the second power line 250, and the first shield electrode 221 extends downward from the position covering the via 304 and is located at Extending to the left not beyond the position of the scan line and covering part of the first electrode T2s of the second transistor T2, the shape of the first shield electrode 221 is approximately an L-shaped left and right mirror image pattern.
  • the left side refers to the side of the data line opposite to the second power line.
  • the boundary of a pixel circuit area divided in the row direction is roughly the data line of a pixel circuit and the same line.
  • the data line of the next (for example, the adjacent right) pixel circuit that is, the part between two adjacent data lines and the data line of the pixel circuit constitute the range of the pixel circuit in the row direction.
  • the second power line or the reset signal line is used as the boundary of the pixel circuit division, which is designed according to needs.
  • the third conductive layer 203 further includes a first connection electrode 231, and one end of the first connection electrode 231 passes through the via 301 in the first capacitor electrode Ca and the via 401 in the insulating layer.
  • the gate T1g of the first transistor T1, that is, the second capacitor electrode Cb, is electrically connected, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402, so that the second capacitor electrode Cb is electrically connected to the third capacitor electrode Cb.
  • the first electrode T3s of the transistor T3 is electrically connected.
  • the via hole 401 penetrates the second insulating layer 104 and the second insulating layer 105
  • the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 (refer to FIG. 6).
  • the third conductive layer 203 further includes a second connecting electrode 232.
  • One end of the second connecting electrode 232 is electrically connected to the reset voltage line through a via 403, and the other end is electrically connected to the sixth via a via 404.
  • the transistor T6 is electrically connected so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240.
  • the via hole 403 penetrates the third insulating layer 105
  • the via hole 404 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 (refer to FIG. 6).
  • the third conductive layer 203 further includes a third connection electrode 233, which is electrically connected to the second electrode T5d of the fifth transistor T5 through a via 405, and is used for the second electrode T5d of the fifth transistor T5.
  • the second electrode T5d of the five transistor T5 is electrically connected to the first electrode 134 of the light-emitting element.
  • the via 405 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 (refer to FIG. 6). This will be explained in detail later.
  • the fourth conductive layer 204 includes a third power line 260 that extends along the second direction D2 and electrically connects a plurality of second power lines 250 to form a mesh The power cord structure.
  • This structure helps to reduce the resistance of the power line, thereby reducing the voltage drop of the power line, and helps to uniformly transmit the first power supply voltage to each sub-pixel of the display substrate.
  • the fourth conductive layer 204 further includes a plurality of first power lines 270 (the plurality of first power lines 270 correspond to the first metal layer), and the first power lines 270 extend along the first direction D1 and are connected to a plurality of The second power cords 250 are electrically connected in a one-to-one correspondence.
  • the first power line 270 and the corresponding second power line 250 at least partially overlap each other in a direction perpendicular to the base substrate 101, and are electrically connected to each other through the via 306.
  • one via 306 is provided corresponding to each sub-pixel, so that each first power line 270 and the corresponding second power line 250 form a parallel structure, which helps to reduce the resistance of the power line.
  • the second power line 250 located in the third conductive layer may widen or narrow the line width at some positions in order to avoid certain structures such as vias or connection lines, or to make the upper structure flat.
  • the first power line 270 located in the fourth conductive layer may widen or narrow the line width at some locations in order to avoid certain structures such as vias or connecting lines, or to make the upper structure flat. In this way, the first power line 270 and the corresponding second power line 250 may not completely overlap in the direction perpendicular to the base substrate 101.
  • the third power line 260 and the first power line 270 are electrically connected to each other or form an integral structure, so that the plurality of second power lines 250, the plurality of third power lines 260, and the plurality of first power lines 270 are formed as Mesh power cord structure.
  • the first power line 270 extends along the first direction D1, the first part and the second part of the corresponding opening of each sub-pixel are arranged along the second direction D2, and the first direction D1 and the second direction D2 perpendicularly intersect.
  • the plurality of first power supply lines 270 include first sub power supply lines 31 and second sub power supply lines 32 alternately arranged in parallel to each other.
  • the orthographic projection of the first sub-power supply line 31 on the base substrate 101 separates the orthographic projection of the opening 101 corresponding to the red sub-pixel and the blue sub-pixel on the base substrate into a first part and a second part.
  • the orthographic projection of the second sub-power line 32 on the base substrate 101 separates the orthographic projection of the opening corresponding to the green sub-pixel on the base substrate into a first part and a second part.
  • the first sub-power supply line 31 includes a first repeating part 311 and a second repeating part 312 as repeating units connected in sequence.
  • the central axis of the first repeating part 311 is far away from the second part of the orthographic projection of the red sub-pixel and the blue sub-pixel corresponding to the opening on the base substrate with respect to the central axis of the second repeating part 312.
  • the first repeating portion 311 is hollowed out and retracted on the side close to the second portion where the corresponding openings of the red sub-pixel and the blue sub-pixel are orthographically projected on the base substrate.
  • the red sub-pixel and the blue sub-pixel overlap the first repeating portion 311 and the second repeating portion 312 of the corresponding first sub power line 31, respectively.
  • the second sub power line 32 includes a third repeating part 321, a fourth repeating part 322, and a fifth repeating part 323 as repeating units connected in sequence.
  • the center axis of the third repeating portion 321, the center axis of the fourth repeating portion 322, and the center axis of the fifth repeating portion 323 are sequentially close to the second portion of the orthographic projection of the corresponding opening of the green sub-pixel on the base substrate.
  • the third repeated portion 321 is hollowed out on the side of the second portion that is orthographically projected on the base substrate near the corresponding opening of the green sub-pixel
  • the fifth repeated portion 323 is orthographically projected on the base substrate near the corresponding opening of the green sub-pixel.
  • the first part is hollowed out on one side.
  • the green sub-pixels overlap the fourth repeating portion 322 and the fifth repeating portion 323 of the corresponding second sub power line 32, respectively.
  • the fourth conductive layer 204 further includes a fourth connection electrode 234 insulated from the first power line 270, and the fourth connection electrode 234 is electrically connected to the third connection electrode 233 through a via 307, so that the fifth transistor
  • the second electrode T5d of T5 is electrically connected to the first electrode 134 of the light-emitting element.
  • the fourth connection electrode 234 and the third connection electrode 233 at least partially overlap in a direction perpendicular to the base substrate 101.
  • FIG. 5 also shows a fifth conductive layer 205 on the basis of FIG. 4D, and the fifth conductive layer 205 includes the first electrode 134 of the light-emitting element 120.
  • Fig. 6 shows a cross-sectional view of Fig. 5 along the section line A-A'.
  • the semiconductor layer 102, the first insulating layer 103, the first conductive layer 201, the second insulating layer 104, the second conductive layer 202, the third insulating layer 105, the third conductive layer 203, and the fourth insulating layer 106, the fourth conductive layer 204, the fifth insulating layer 107, and the fifth conductive layer 205 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 5.
  • the first electrode 134 may include a main body portion 141 and a connecting portion 142.
  • the main body portion 141 is mainly used to drive the light emitting layer to emit light.
  • the orthographic projection of the main body portion 141 on the base substrate 101 covers the first The orthographic projection of the opening area 600 of the sub-pixel to which the electrode belongs on the base substrate, and the connection portion 142 is mainly used for connection with the pixel circuit.
  • the third power line 260 and each first electrode 134 do not overlap in a direction perpendicular to the base substrate 101. This arrangement can prevent the first electrode 134 of the light-emitting element from overlapping with the third power line 260 and being uneven and causing display problems such as color shift.
  • a pixel defining layer is formed on the first electrode 134, and an opening area 600 is formed on the pixel defining layer.
  • the opening area 600 exposes at least part of the main body portion 141 of the first electrode 134 and defines the light-emitting area of each corresponding sub-pixel (Opening area), the light-emitting layer of the light-emitting element 120 is formed at least in the opening area of the pixel defining layer.
  • the flatness of the first electrode 134 will directly affect the uniformity of the light emission of the light-emitting layer, thereby affecting the display effect.
  • the third power line 260 may have a curved structure to adapt to the pattern of the first electrode 134, for example, a broken line shape or a wavy line shape.
  • two adjacent third power lines 260 define a row of sub-pixels 100.
  • each of the plurality of third power supply lines 260 includes a third sub power supply line 41 and a fourth sub power supply line 42 that are sequentially connected as repeating units.
  • the third sub power line 41 includes a sixth repeating part 261, a seventh repeating part 262, and an eighth repeating part 263 as repeating units connected in sequence.
  • the extension direction of the seventh repeating portion 262 is parallel to the second direction D2
  • the extension direction of the sixth repeating portion 261 intersects both the first direction D1 and the second direction D2
  • the extension direction of the eighth repeating portion 263 is parallel to the first direction D1 and D2.
  • the second directions D2 all intersect and are different from the extending direction of the sixth repeating portion 261. As shown in FIG.
  • the green sub-pixels G are alternately arranged along the first direction, and the third sub-power supply line 41 is located at the first of the green sub-pixels G (including the first green sub-pixel G'and the second green sub-pixel G").
  • the two parts G2 (including the second part G'2 of the orthographic projection of the opening corresponding to the first green sub-pixel G'and the second part G"2 of the orthographic projection of the opening corresponding to the second green sub-pixel G") are on the base substrate
  • the orthographic projection of the green sub-pixel G and the second portion G2 of the green sub-pixel G are between the orthographic projection on the base substrate.
  • the third sub-power line 41 is located corresponding to the green sub-pixel
  • the opening is in the region between the first side of the orthographic projection on the base substrate and the corresponding opening of the adjacent red sub-pixel or the blue sub-pixel on the second side of the orthographic projection on the base substrate.
  • the fourth sub power line 42 includes a ninth repeating part 264 and a tenth repeating part 265.
  • the extension direction of the ninth repeating part 264 is parallel to the second direction
  • the extension direction of the tenth repeating part 265 is the same as the first direction and the second direction. intersect.
  • the red sub-pixels R and the blue sub-pixels B are alternately arranged along the first direction
  • the fourth sub-power supply line is located in the orthographic projection and blue sub-pixels of the second part R2 of the red sub-pixel R on the base substrate.
  • the second portion R2 of the sub-pixel B is between the orthographic projections on the base substrate.
  • the fourth sub-power supply line 42 is located at the first side of the orthographic projection of the red sub-pixel or the blue sub-pixel corresponding to the opening on the base substrate and the opening corresponding to the adjacent green sub-pixel. The area between the second side of the orthographic projection on the base substrate.
  • the arrangement principle of the third power line is to maintain the maximum overlap area with the semiconductor layer pattern to increase the aperture ratio.
  • the shape of the body portion 141 of the first electrode 134 is quadrilateral, for example, each ninth repeating portion 264 corresponds to a vertex of the body portion 141 of the first electrode 134, and the ninth repeating portion 264 and the semiconductor layer 102
  • the portion along the first direction D1 overlaps to the maximum extent, and the adjacent tenth repeating portion 265 overlaps the portion of the semiconductor layer that is different from the first direction D1 and the second direction D2.
  • the sixth, seventh, and eighth repeating portions 261, 262, and 263 of the third power line, as well as the portions of the first power line 270 and the second power line 250 are also along the extending direction of the pattern of the semiconductor layer 102. Make settings.
  • Fig. 4E shows a cross-sectional view of Fig. 4D along the C-C plane.
  • the ninth repeating portion 264 of the third power line 260 and the reset control line 220 overlap in a direction perpendicular to the base substrate 101; the tenth repeating portion 265 overlaps with a data line 12 There is overlap in the direction perpendicular to the base substrate 101, and the data line 12 is electrically connected to a column of pixel circuits corresponding to the tenth repeating portion 265 to provide the data signal.
  • FIG. 4F shows a cross-sectional view of FIG. 4D along the section line C'-C".
  • the sixth repeating portion 261 and the seventh repeating portion 262 of the third power line 260 are in contact with the first connecting electrode 231, respectively.
  • the seventh repeating portion 262 and the scan line 210 overlap in the direction perpendicular to the base substrate 101, and the eighth repeating portion 263 is perpendicular to the data line 12
  • the eighth repeating portion 263 is perpendicular to the data line 12
  • the base substrate 101 There is overlap in the direction of the base substrate 101.
  • FIG. 5 shows the first electrodes 134a, 134b, 134c, and 134d of the four adjacent sub-pixels, for example, the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d It constitutes a repeating unit of the display substrate 20.
  • the color of the light emitted by the light-emitting element of the second sub-pixel 100b and the color of the light emitted by the light-emitting element of the fourth sub-pixel 100d are the same, that is, the second sub-pixel 100b and the fourth sub-pixel 100b
  • the sub-pixels 100d are sub-pixels of the same color.
  • the second sub-pixel 100b and the fourth sub-pixel 100d are sensitive color sub-pixels.
  • the above-mentioned sensitive color is green, that is, the second sub-pixel 100b and the fourth
  • the sub-pixels 100d are all green sub-pixels.
  • the first sub-pixel 100a may be a red sub-pixel
  • the third sub-pixel 100c may be a blue sub-pixel.
  • the first sub-pixel 100a and the third sub-pixel 100c are alternately arranged in the row direction, and the second sub-pixel 100b and the fourth sub-pixel 100d are respectively located in the first sub-pixel 100a and the first sub-pixel 100a and the first sub-pixel 100a in adjacent rows. Between the three sub-pixels 100c, and between the third sub-pixel 100c and the first sub-pixel 100a in the next repeating unit.
  • the first sub-pixel 100a and the third sub-pixel 100c are alternately arranged in the column direction.
  • two first sub-pixels 100a and two third sub-pixels 100c located in two rows and two columns form a 2*2 matrix.
  • two first sub-pixels 100a are located in At one diagonal position of the matrix
  • two third sub-pixels 100c are located at the other diagonal position of the matrix
  • the two first sub-pixels 100a and two third sub-pixels 100c surround one second sub-pixel 100b or The fourth sub-pixel 100d.
  • the 2*2 matrix is repeated in the row direction and the column direction in a manner of sharing one column or row of sub-pixels.
  • each repeating unit may form two dummy pixels, and the first sub-pixel 100a and the third sub-pixel 100c in the repeating unit are respectively shared by the two dummy pixels.
  • the first sub-pixel 100a and the second sub-pixel 100b located on its right side and adjacent to it constitute a virtual pixel
  • the third sub-pixel 100c in the adjacent (right) virtual pixel is borrowed.
  • a light-emitting pixel unit is formed; the third sub-pixel 100c and the fourth sub-pixel 100d located on the right side thereof and adjacent to it form a virtual pixel, and the adjacent (not shown on the right) first sub-pixel 100a is used to form a light-emitting pixel unit.
  • the sub-pixels in the multiple repeating units form a pixel array.
  • the sub-pixel density is 1.5 times the virtual pixel density
  • the sub-pixel density is 1.5 times the virtual pixel density
  • the second sub-pixel 100b and the fourth sub-pixel 100d belong to two virtual pixels, respectively.
  • each virtual pixel is not limited.
  • the division of virtual pixels is related to the driving mode, and the specific division mode of virtual pixels can be determined according to the actual driving mode, which is not specifically limited in the present disclosure.
  • the shape and size of the plurality of opening regions corresponding to the sub-pixel 100 can be changed according to the luminous efficiency and service life of the luminescent materials that emit light of different colors.
  • the corresponding openings of the luminescent material with a shorter luminescence lifetime can be changed.
  • the area is set larger to improve the stability of light emission.
  • the size of the opening area of the blue sub-pixel, the red sub-pixel, and the green sub-pixel may be sequentially reduced. Since the opening area is provided on the first electrode 134, correspondingly, as shown in FIG. 5, the first electrodes 134a, 121b of the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d The areas of, 121c and 121d decrease sequentially.
  • the main body portions of the first electrodes of the light-emitting elements of the sub-pixels are arranged along the second direction and alternately arranged along the first direction.
  • the main body of the first electrode and the first capacitor electrode of one of two adjacent sub-pixels overlap in a direction perpendicular to the base substrate, and the other of the two sub-pixels
  • the main body of the first electrode and the first capacitor electrode do not overlap in a direction perpendicular to the base substrate.
  • a green area with the smallest area is provided between the first electrode 134a of each adjacent red sub-pixel (first sub-pixel 100a) and the first electrode 134c of the blue sub-pixel (third sub-pixel 100c).
  • the first electrodes 134b/134d of the sub-pixels, and the body portions of the first electrodes 134b/134d and the body portions of the first electrodes 134a and 134c are alternately arranged along the second direction.
  • the body portions of the first electrodes 134a and 134c overlap with the first capacitor electrode Ca in the respective sub-pixels in a direction perpendicular to the base substrate, and the body portions of the first electrodes 134b/134d respectively overlap with the first capacitor electrodes Ca in the respective sub-pixels.
  • the first capacitor electrode Ca in the sub-pixel does not overlap in the direction perpendicular to the base substrate. This can increase the utilization of the layout space, thereby increasing the pixel density.
  • the main body portion 141 of each first electrode extends in the second direction D2 in a zigzag shape.
  • the main body of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c is, for example, a quadrilateral, and they are arranged in the row and column directions with the top corners facing each other, and the third power supply line 260 extends along the contour of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c away from the second sub-pixel 100b and the fourth sub-pixel 100d.
  • the second sub-pixel 100b and the fourth sub-pixel 100d are located in the row direction, that is, in the D2 direction, at positions between the corresponding adjacent two sub-pixels in the sub-pixel row formed by the first sub-pixel 100a and the third sub-pixel 100c, Moreover, the main body of the first electrode 134 of the second sub-pixel 100b and the fourth sub-pixel 100d is, for example, a quadrangular shape, and the main body of the first electrode 134 of each adjacent sub-pixel has opposite and parallel sides, and the third power line 260 extends along the contour of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c away from the second sub-pixel 100b and the fourth sub-pixel 100d, and also along the second sub-pixel 100b and the first The contour of the first electrode 134 of the four sub-pixel 100d that is away from the first sub-pixel 100a and the third sub-pixel 100c extends.
  • the third power line 260 is along the first electrode 134 of the sub-pixel row formed by the first sub-pixel 100a and the third sub-pixel 100c, and is connected to the first electrode 134 of the sub-pixel row formed by the second sub-pixel 100b and the fourth sub-pixel 100d.
  • the gap between one electrode 134 extends to form a wave shape, and is formed as a wave crest at the position of the electrode apex of the main body portion of the first electrode 134 corresponding to the first sub-pixel 100a and the third sub-pixel 100c, which corresponds to the second sub-pixel 100a and the third sub-pixel 100c.
  • the electrode vertex positions of the main body of the first electrode 134 are formed as troughs.
  • the direction close to the upper row is the convex direction of the wave peak
  • the direction close to the next row is the convex direction of the wave trough.
  • the connecting portion 142 of the first electrode 134 of each sub-pixel is electrically connected to the fourth connecting electrode 234 through the via 308, so that the second electrode T5d of the fifth transistor T5 is connected to the light emitting element.
  • the first electrode 134 of 120 is electrically connected.
  • the connecting portion 142 of the first electrode 134 and the fourth connecting electrode 234 at least partially overlap in a direction perpendicular to the base substrate 101.
  • the opening area 600 and the connecting portion 142 of the first electrode 134 do not overlap in a direction perpendicular to the base substrate 101, and the via 307 and the via 308 are perpendicular to the connecting portion 142 of the first electrode 134.
  • the directions on the base substrate 101 are overlapped, so as to prevent the via 308 and the via 307 from affecting the flatness of the light-emitting layer in the opening area and thereby affecting the light-emitting quality.
  • the via 307 may partially overlap the opening area, because the layer where the via 307 is located and the layer where the first electrode 134 is located are at least separated from the layer where the fourth connection electrode 234 is located, and where the via 308 is located. Therefore, the influence of the via 307 on the flatness of the opening area is smaller than the influence of the via 308 on the flatness of the opening area.
  • the corresponding fourth connection electrode is located on the side of the first electrode 134 away from the reset control line 220 in the pixel circuit.
  • the connection of the first electrode 134 The electrode is also located on the side of the first electrode 134 away from the reset control line 220 in the pixel circuit, and the connection electrode of the first electrode 134 and the corresponding fourth connection electrode at least partially overlap.
  • the corresponding fourth connection electrode is located on the side of the first electrode 134 close to the reset control line 220 in the pixel circuit, correspondingly, the connection of the first electrode 134
  • the electrode is also located on the side of the first electrode 134 away from the reset control line 220 in the pixel circuit, and the connection electrode of the first electrode 134 and the corresponding fourth connection electrode at least partially overlap.
  • the display substrate 20 further includes a pixel defining layer 108 on the first electrode of the light-emitting element.
  • An opening is formed in the pixel defining layer 108 to define the opening area 600 of the display substrate.
  • the light-emitting layer 136 is formed at least in the opening (the light-emitting layer 136 may also cover part of the pixel defining layer), and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120.
  • the second electrode 135 is a common electrode, and the entire surface is arranged in the display substrate 20.
  • the first electrode is the anode of the light-emitting element
  • the second electrode is the cathode of the light-emitting element.
  • the orthographic projection of the via 307 and the via 308 on the base substrate 101 are located on the third connecting electrode 234 on the base substrate.
  • the via holes 307 and the via holes 308 are arranged side by side in the D1 direction, and their center lines along the first direction D1 are substantially coincident.
  • the via 308 is farther away from the main body portion 141 of the first electrode 134 than the via 307, so that the opening area 600 relative to the sub-pixel (for example, the first electrode 134 The area is larger than the area of the corresponding opening area 600, which is approximately located in the middle area of the first electrode 134).
  • the orthographic projection of the via 308 on the base substrate 101 is compared with that of the via 307 on the base substrate 101. The orthographic projection is farther away from the orthographic projection of the opening area 600 on the base substrate.
  • the insulating layer (for example, the second flat layer) where the via 308 is located is closer to the first flat layer than the insulating layer (for example, the first flat layer) where the via 307 is located.
  • the main body portion 142 of an electrode 134 so the via hole 308 has a greater influence on the flatness of the first electrode 134.
  • the via hole 308 is set farther away from the mouth area or the main body portion of the first electrode 134 (in parallel to On the surface of the base substrate), the influence of the via on the flatness of the light-emitting layer 136 in the opening area can be reduced, and the performance of the light-emitting element can be improved.
  • the vias 307 and 308 in the pixel circuits of the first sub-pixel 100a and the third sub-pixel 100c are both located at their corresponding first electrodes 134 away from the reset control line 220 in the pixel circuit.
  • the corresponding fourth connecting electrode is located on the side of the first electrode 134 close to the reset control line 220 in the pixel circuit, that is, in a row of repeating units, each sub-pixel
  • the via holes 307 and 308 in the pixel circuit of the pixel are both located between the row formed by the first sub-pixel 100a and the third sub-pixel 100c and the row formed by the second sub-pixel 100b and the fourth sub-pixel 100d.
  • the shapes of the fourth connecting electrodes in the pixel circuits of the first sub-pixel 100a, the third sub-pixel 100c, the second sub-pixel 100b, and the fourth sub-pixel 100d are approximately the same, and they are approximately arranged in the same shape.
  • the via 307 and the via 308 located in the orthographic projection of the fourth connection electrode do not substantially overlap or not completely overlap, so as to avoid in the vertical substrate direction, the via stacking leads to the location of the via which is prone to poor connection, disconnection or failure. flat.
  • the vias 307 of the first sub-pixel 100a and the third sub-pixel 100c are approximately on the same line as the vias 308 of the second sub-pixel 100b and the fourth sub-pixel 100d.
  • the via hole 308 of the pixel 100c is approximately on the same straight line as the via hole 307 of the second sub-pixel 100b and the fourth sub-pixel 100d.
  • the orthographic projection of the opening area 600 and the via 308 on the base substrate 101 does not overlap.
  • the opening area 600 and the orthographic projection of the fourth connection electrode 234 on the base substrate 101 do not overlap. This helps to improve the flatness of the light-emitting layer 136 and thus the light-emitting efficiency.
  • the orthographic projection of the opening on the base substrate is warped at least part of the two parts separated by the first power line, causing color shift.
  • the line width of the first power line 270 is such that for the openings of different color sub-pixels, the ratio between the area ratio between the first portion of the orthographic projection of the opening and the area ratio between the second portion of the orthographic projection of the opening is within a certain range , For example, in the range of 0.8-1.2.
  • the line width of the first repeating part can be adjusted between 3 ⁇ m and 4.6 ⁇ m, and the line width of the second repeating part can be adjusted between 4.5 ⁇ m and 6.9 ⁇ m.
  • Adjust the line width of the third repeat part between 3 ⁇ m-4.6 ⁇ m, adjust the line width of the fourth repeat part between 5.3 ⁇ m-8.1 ⁇ m, and set the line width of the fifth repeat part between 2.4 ⁇ m- Adjust between 3.6 ⁇ m so that the ratio between the area ratio between the first portion of the orthographic projection of the opening and the area ratio between the second portion of the orthographic projection of the opening is within the above-mentioned range of 0.8-1.2.
  • the line width of the first repeating part may be 3.8 ⁇ m
  • the line width of the second repeating part may be 5.7 ⁇ m
  • the line width of the third repeating part may be 3.8 ⁇ m
  • the line width of the fourth repeating part may be It is 6.7 ⁇ m
  • the line width of the fifth repeating part can be 3.0 ⁇ m.
  • the width of the first power line 270 in the R and B sub-pixels corresponding to the opening orthographic projection is adjusted from 4.3 from the line to 3.8 from the line, and the G'and G" sub-pixels are corresponding to the opening orthographic projection.
  • the width of the first power line 270 is adjusted from 4.4 from the line and 4.7 ⁇ . to 3.0 as the line, so that for the openings of different color sub-pixels, the ratio of the area between the first part of the orthographic projection of the opening and the second of the orthographic projection of the opening is The ratio of the area ratio between the parts is within the above range.
  • the ratio of the area ratio between the first portion of the orthographic projection of the opening to the area ratio between the second portion of the orthographic projection of the opening is 1.
  • the sum of the first part of the orthographic projection of the aperture of the red sub-pixel, the first part of the orthographic projection of the aperture of the first green sub-pixel G′ and the first part of the orthographic projection of the aperture of the second green sub-pixel G" ) R1/(G'1+G”1) 1:1.04
  • the ratio R2/(G'2+G"2) 1:1.04 between the sum of the first part of the orthographic projection of the opening of the second green sub-pixel G".
  • the area ratio between the sum of the second part of B2/(G'2+G”2) 1.04:1.644.
  • the area ratio between the first part of the sub-pixel's aperture orthographic projection is R1: (G'1+G”1): B1, the second part of the red sub-pixel's aperture orthographic projection, and the first green sub-pixel G''s aperture is normal
  • the light transmission ratio between the sub-pixels of different colors corresponding to the first part of the orthographic projection of the opening is equal to the opening ratio.
  • the light transmission ratio between the sub-pixels of different colors corresponding to the second part of the projection can still emit white light even if warping occurs, thereby improving the color shift.
  • the second power line 250 has a strip shape and extends along the first direction D1.
  • the orthographic projection of the second power cord 250 on the base substrate at least partially overlaps with the orthographic projection of the first power cord 260 on the base substrate, and overlaps with the orthographic projection of the plurality of openings on the base substrate.
  • the width of the first power line and the width of the second power line may be different.
  • the difference between the red sub-pixel, the blue sub-pixel, the first green sub-pixel, and the second green sub-pixel the difference between the red sub-pixel, the blue sub-pixel, the first green sub-pixel, and the second green sub-pixel.
  • the orthographic projections of the openings (181a, 181c, 181, and 181d) corresponding to the two green sub-pixels on the base substrate are divided into two parts by the orthographic projection of the first power line base substrate, for example, the first side ( The first part on the left side) and the second part on the second side (right side).
  • the area ratio between the first part of the opening of the red sub-pixel, the first part of the opening of the blue sub-pixel, and the sum of the first part of the opening of the first green sub-pixel and the first part of the opening of the second green sub-pixel is compared with the red
  • the second part of the opening of the sub-pixel, the second part of the opening of the blue sub-pixel, and the sum of the second part of the opening of the first green sub-pixel and the second part of the opening of the second green sub-pixel The area ratio is equal, for example, 1:1.04:1.644.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET) ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC) and so on.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polys
  • the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , Polythiophene, etc.).
  • the material of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and the above Alloy materials composed of metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the light-emitting element 120 has a top-emitting structure
  • the first electrode 134 has reflectivity
  • the second electrode 135 has transmissive or semi-transmissive properties.
  • the first electrode 134 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminate structure
  • the second electrode 135 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrides. Oxides, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • the fourth insulating layer 106, the fifth insulating layer 107 and the pixel defining layer 108 are respectively organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethylmethacrylate (PMMA) And other organic insulating materials.
  • the fourth insulating layer 106 and the fifth insulating layer 107 are planarization layers.
  • the pixel circuit of the first sub-pixel 100a is electrically connected to the first data line 12a to receive the data signal Vd
  • the pixel circuit of the second sub-pixel 100b is electrically connected to the second data line 12b to receive the data signal Vd.
  • the second data line 12b is located between the pixel circuit of the first sub-pixel 100a and the pixel circuit of the second sub-pixel 100b.
  • the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b are spaced apart from each other, that is, in the first sub-pixel 100a and the second sub-pixel 100b
  • the first capacitor electrodes Ca are disconnected from each other in the conductive layer where they are located. This arrangement can reduce the overlap between the adjacent first capacitor electrodes Ca when they are connected to each other and other signal lines, thereby reducing parasitic capacitance.
  • the area and shape of the first capacitor electrode Ca in each sub-pixel 100 are substantially the same.
  • the relative position of the first capacitor electrode Ca in each sub-pixel 100 in the sub-pixel is the same.
  • the first capacitor electrodes Ca in each row of sub-pixels 100 are linearly arranged along the second direction D2.
  • the first capacitor electrode Ca in each sub-pixel 100 has an island-shaped structure in the conductive layer where it is located, that is, it is not electrically connected to other structures of the conductive layer where it is located.
  • the second pole T3d of the third transistor T3 in the pixel circuit of the first sub-pixel 100a there are the second pole T1d of the first transistor T1, and the second pole T1d of the first transistor T1 between the adjacent first capacitor electrodes Ca.
  • the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b are disconnected from each other to avoid the second sub-pixel.
  • the first capacitor electrode Cab in the pixel 100b overlaps with the junction to generate parasitic capacitance, which adversely affects the signal at the junction.
  • the first capacitor electrode Cab in the second sub-pixel 100b does not overlap in a direction perpendicular to the base substrate 101.
  • the range of the first capacitor electrode Ca in the sub-pixel 100 does not exceed the pixel area (the area where the pixel circuit is located) of the sub-pixel, that is, the first capacitor electrode Cab of the sub-pixel 100 does not extend to the adjacent sub-pixel.
  • the structure in the pixel area of the pixel overlaps with the structure in the sub-pixel, causing crosstalk.
  • FIG. 7 there is a second data line 12b between the first capacitor electrode Ca of the adjacent first sub-pixel 100a and the second sub-pixel 100b, and the first capacitor electrode Caa of the first sub-pixel 100a and The orthographic projections of the first capacitor electrode Cab of the second sub-pixel 100b and the second data line 12b on the base substrate do not overlap.
  • Disconnecting the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b from each other can prevent the first capacitor electrode and the second data line 12b from overlapping and generating parasitic capacitance.
  • the transmission of the data signal on the data line is adversely affected, for example, the data signal is delayed.
  • the data signal Vd is usually a high-frequency signal
  • the first capacitor electrode Ca transmits the first power supply voltage VDD
  • the first power supply voltage is likely to follow the sudden change of the data signal Vd.
  • the RC load between the first capacitor electrode Ca and the data line is too large, causing the first power supply voltage to fail to recover in a short time after a sudden change.
  • disconnecting the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b from each other also helps to improve the stability of the light emission of the light-emitting element.
  • the distance can be 1.75 ⁇ m, for example, the orthographic projection of the source electrode T1s of the first sub-pixel 100b adjacent to the second data line 12b on the base substrate and the orthographic projection of the second data line 12b on the base substrate The distance between them can be 2.8 ⁇ m.
  • the distance between the second data line 12b and the source or drain of the adjacent sub-pixel may also be another value to avoid overlap.
  • the inventor of the present disclosure found that due to the overlap between the signal lines, a parasitic capacitance is generated between the data line 12 and the second capacitor electrode Cb of the storage capacitor Cst, which affects the stability of the storage capacitor Cst.
  • the storage capacitor Cst is configured to store the data signal Vd and information related to the threshold voltage of the driving sub-circuit, and is configured to use the stored information to control the driving sub-circuit 122 during the light-emitting phase, so that the output of the driving sub-circuit 122 is It is compensated, so the stability of the voltage (stored information) across the storage capacitor Cst will affect the stability of the display gray scale, thereby affecting the quality of the display picture.
  • the first capacitor electrode Ca in at least one sub-pixel includes an extension 290, and the extension 290 is connected to the data line of the sub-pixel. 12 overlap each other in a direction perpendicular to the base substrate 101 to provide a first capacitor C1.
  • the fluctuation of the data signal in the data line 12 is coupled to the second capacitor electrode Cb of the storage capacitor Cst through the parasitic capacitor, and is also coupled to the storage capacitor Cst through the first capacitor C1. ⁇ first capacitor electrode Ca. This improves the stability of the information stored in the storage capacitor Cst and improves the display performance.
  • Fig. 8A shows a cross-sectional view of Fig. 2 along the section line B-B'
  • Fig. 8B shows an equivalent circuit diagram of the pixel circuit. 2 and 8A-8B
  • the data line 12 and the scan line 210 overlap in the direction perpendicular to the base substrate 101 to form a second capacitor C2
  • the first connection electrode 231 and the scan line 210 are perpendicular to the substrate 101
  • the direction of the substrate 101 overlaps to form a third capacitor C3.
  • the second capacitor C2 and the third capacitor C3 are connected in series between the data line 12 and the second capacitor electrode Cb of the storage capacitor Cst.
  • the fluctuation of the data signal in the line 12 will be coupled to the second capacitor electrode Cb of the storage capacitor Cst through the second capacitor C2 and the third capacitor C3.
  • the fluctuation of the data signal in the data line 12 is also coupled to the first capacitor electrode Ca of the storage capacitor Cst through the first capacitor C1. This improves the stability of the information stored in the storage capacitor Cst and improves the display performance.
  • the extension portion 290 extends (protrudes) from the main body portion of the first capacitor electrode Ca in the direction of the data line 12 overlapping it.
  • the shape of the first capacitor electrode Ca is a convex shape that is inverted toward the data line in the pixel circuit where it is located, that is, the first capacitor electrode Ca is a substantially rectangular electrode block and is close to the pixel circuit.
  • the first capacitor electrode Ca still does not extend beyond the pixel area where the sub-pixel is located, that is, the first capacitor electrode Cab of the pixel circuit does not extend to the pixel area of the adjacent sub-pixel and the pixel area.
  • the structures in the sub-pixels overlap and cause crosstalk.
  • FIG. 9 shows a schematic diagram of the first capacitor electrode Ca.
  • the ratio of the area of the extension portion 290 to the area of the first capacitor electrode Ca ranges from 1/10 to 1/3, for example, 1/5.
  • the ratio of the maximum dimension D2 of the extension portion 290 to the maximum dimension D1 of the first capacitor electrode ranges from 1/4 to 1/2, for example, 1/3.
  • At least one embodiment of the present disclosure also provides a display panel including any of the above display substrates 20.
  • the above-mentioned display substrate 20 provided by at least one embodiment of the present disclosure may or may not include the light-emitting element 120, that is, the light-emitting element 120 may be formed in a panel factory after the display substrate 20 is completed.
  • the display panel provided by the embodiment of the present disclosure includes the light emitting element 120 in addition to the display substrate 20.
  • the display panel is an OLED display panel, and accordingly the display substrate 20 included therein is an OLED display substrate.
  • the display panel 30 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20.
  • the encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture. The penetration of gas and oxygen into the light-emitting element and the driving sub-circuit causes damage to the device.
  • the encapsulation layer 801 includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked.
  • a water absorption layer (not shown) may be further provided between the encapsulation layer 801 and the display substrate 20, configured to absorb residual water vapor or sol in the preliminary manufacturing process of the light-emitting element.
  • the cover plate 802 is, for example, a glass cover plate.
  • the cover plate 802 and the encapsulation layer 801 may be an integral structure.
  • the display device 40 includes any of the above-mentioned display substrate 20 or display panel 30.
  • the display device in this embodiment may be: a display, an OLED Panels, OLED TVs, electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • the embodiment of the present disclosure also provides a manufacturing method of the above-mentioned display substrate 20.
  • the structure and manufacturing method of the display substrate provided by the embodiments of the present disclosure will be exemplarily described below in conjunction with FIGS. 2, 4A-4E, and FIGS. 5-6, but the embodiments of the present disclosure are not limited thereto.
  • the manufacturing method includes the following steps S61-S70 as shown in FIG. 12.
  • Step S61 A semiconductor material layer is formed on the base substrate, and a patterning process is performed on the semiconductor material layer to form a semiconductor layer 102 as shown in FIG. 4A.
  • the semiconductor layer 102 includes first to seventh transistors in each pixel area.
  • T1-T7 active layers T1a-T7a and doped region patterns that is, corresponding to the source regions and drain regions of the first to seventh transistors T1-T7), and the active layer patterns of each transistor in the same pixel region It is integrated with the doped region pattern.
  • the active layer may include an integrally formed low-temperature polysilicon layer, in which the source region and the drain region may be conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel region includes a doped region pattern (ie, a source region and a drain region) and an active layer Pattern, the active layers of different transistors are separated by doped structures.
  • Step S62 forming a first insulating layer 103 (for example, a transparent layer), such as a gate insulating layer, on the semiconductor layer 102, and forming a plurality of first insulating layer via holes on the first insulating layer for subsequent formation
  • the pattern of the third conductive layer 203 is connected.
  • corresponding first insulating layer via holes are formed in the first insulating layer, that is, the first insulating layer via holes are respectively connected to the source region and the drain region in the semiconductor layer.
  • the drain region overlaps for the source region and the drain region and the data line 12, the second power line 250, the first connection electrode 231, the second connection electrode 232, and the third connection electrode 233 in the third conductive layer Connect with other structures, such as vias 402, vias 405, vias 303, and vias 305 that penetrate the first insulating layer.
  • Step S63 forming a first conductive material layer on the first insulating layer, and performing a patterning process on the first conductive material layer to form a first conductive layer 201 as shown in FIG.
  • the scanning line 210, the reset control line 220, and the light emission control line 230 extending in the direction.
  • the correspondingly connected reset control lines 220, scan lines 210, and light emission control lines 230 are sequentially arranged in the first direction D1.
  • the first conductive layer 201 further includes the gates T1g-T7g of the first to seventh transistors T1-T7.
  • the gate T6g of the sixth transistor T6 and the reset control line 220 are integrated, that is, a part of the reset control line 220 serves as the gate T6g of the sixth transistor T6;
  • the gate T2g of the second transistor T2 and the scan line 210 are The integrated structure, that is, the part of the scan line 210 serves as the gate T2g of the second transistor T2;
  • the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5 are both integrated with the light emission control line 230, that is, light emission
  • a part of the control line 230 serves as the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5;
  • the gate T7g of the seventh transistor T7 and the reset control line 220 corresponding to the next row of pixel circuits are integrated.
  • the sixth transistor T6 and the third transistor T3 both have a double-gate structure
  • the two gates T6g of the sixth transistor T6 are both part of the reset control line 220
  • one gate of the third transistor T3 is a part of the scan line 210.
  • the other gate of the third transistor T3 is a part that is integrally connected to the scan line 210 and protrudes toward the reset control line 220.
  • the overlapping portion of the semiconductor layer 102 and the first conductive layer 201 in a direction perpendicular to the base substrate defines the active layers (channel regions) T1a-T7a of the first to seventh transistors T1-T7.
  • the gate of the second transistor for example, a data writing transistor
  • the gate of the third transistor for example, a threshold compensation transistor
  • the sixth transistor for example, the first reset transistor
  • the gate of the seventh transistor (for example, the second reset transistor) and the gate of the seventh transistor (for example, the second reset transistor) T7 are located on the first side of the gate of the first transistor (for example, the driving transistor) T1, and the fourth transistor (for example, the first light-emitting control transistor)
  • the gate of T4 and the gate of the fifth transistor (for example, the second light-emitting control transistor) T5 are both located on the second side of the gate of the first transistor T1.
  • the first side of the gate of the first transistor T1 in the same pixel area may be the side of the gate T1g of the first transistor T1 close to the scan line 230, and the gate of the first transistor T1
  • the second side of the pole may be a side of the gate of the first transistor T1 away from the scan line 230.
  • the gate of the second transistor T2 and the gate of the fourth transistor T4 are both located on the third side of the gate of the first transistor T1, and the first gate of the third transistor T3 (and The scan line 210 is an integrated gate), the gate of the fifth transistor T5 and the gate of the seventh transistor T7 are all located on the fourth side of the gate of the first transistor T1.
  • the third side and the fourth side of the gate of the first transistor T1 in the same pixel area are opposite sides of the gate of the first transistor T1 in the D2 direction.
  • the third side of the gate of the first transistor T1 in the same pixel area may be the left side of the gate of the first transistor T1
  • the fourth side of the gate of the first transistor T1 may be the gate of the first transistor T1.
  • Step S64 As shown in FIG. 4A, a self-aligned process is used to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102 using the first conductive layer 201 as a mask, so that the semiconductor layer 102 is not exposed to the semiconductor layer 102.
  • the portion covered by the first conductive layer 201 is made conductive, so that the portions of the semiconductor layer 102 located on both sides of the active layer of each transistor are made conductive to form the source regions and drains of the first to seventh transistors T1-T7, respectively.
  • the pole regions that is, the first pole (T1s-T7s) and the second pole (T1d-T7d) of the first to seventh transistors T1-T7.
  • Step S65 forming a second insulating layer 104 (for example, a transparent layer) on the first conductive layer 201, for example, a second gate insulating layer. At least a second insulating layer via hole corresponding to the first insulating layer via hole is formed on the second insulating layer.
  • the via holes corresponding to at least the first insulating layer and the second insulating layer include at least via 402, via 405, via 303, via 305, and so on.
  • Step S66 forming a second conductive material layer on the second insulating layer 104 and on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive layer 202 as shown in FIG. 4B, that is, The shield electrode 221, the first capacitor electrode Ca, and the reset voltage line 240 extending in the first direction are formed to be insulated from each other.
  • the shield electrode 221 overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 to protect the signal in the first electrode T2s of the second transistor T2 from interference by other signals.
  • the first capacitor electrode Ca and the gate T1g of the first transistor T1 at least partially overlap in a direction perpendicular to the base substrate 101.
  • the patterning process also forms a via 301 in the first capacitor electrode Ca, and the via 301 exposes at least part of the gate T1g of the first transistor T1.
  • Step S67 forming a third insulating layer 105 on the second conductive layer 202.
  • the third insulating layer may be, for example, an interlayer insulating layer.
  • a via hole is formed in the third insulating layer for connection with the third conductive layer formed later. At least part of the vias correspond to the positions of the first insulating layer vias and the second insulating layer vias, and pass through the first insulating layer, the second insulating layer and the third insulating layer at the same time, such as vias 402, vias 405, and vias 303, via 305.
  • Step S68 A third conductive material layer is formed on the third insulating layer 105, and a patterning process is performed on the third conductive material layer to form a third conductive layer 203 as shown in FIG. 4C, that is, to form data lines 12 insulated from each other. , The second power line 250, the first connection electrode 231, the second connection electrode 232, and the third connection electrode 233. The data line 12 and the second power line 250 extend along the first direction D1.
  • the data line 12 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 and is electrically connected to the first electrode T2s of the second transistor T2 through the via 305.
  • the via 305 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105, for example.
  • the second power line 250 overlaps the shield electrode 221 in a direction perpendicular to the base substrate 101 and is electrically connected to the shield electrode 221 through a via 304, such as the via 304 penetrates the third insulating layer 105.
  • the second power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via 302, and is electrically connected to the first electrode T4s of the fourth transistor T4 through the via 303.
  • Electric connection For example, the via hole 302 penetrates the third insulating layer 105, and the via hole 303 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the first connecting electrode 231 passes through the via 301 in the first capacitor electrode Ca and the via 401 in the insulating layer and the gate T1g of the first transistor T1, namely The second capacitor electrode Cb is electrically connected, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402, so that the second capacitor electrode Cb is electrically connected to the first electrode T3s of the third transistor T3.
  • the via hole 401 penetrates the second insulating layer 104 and the third insulating layer 105
  • the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the second connecting electrode 232 is electrically connected to the reset voltage line through the via 403, and the other end is electrically connected to the sixth transistor T6 through the via 404, so that the first The terminal T6s can receive the first reset voltage Vinit1 from the reset voltage line 240.
  • the via hole 403 penetrates the third insulating layer 105
  • the via hole 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • the third connecting electrode 233 is electrically connected to the second electrode T5d of the fifth transistor T5 through the via 405, and is used to connect the second electrode T5d of the fifth transistor T5 to the light emitting element.
  • the first electrode 134 is electrically connected.
  • the via 405 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105.
  • Step S69 forming a fourth insulating layer 106 on the third conductive layer 203. And forming a via hole in the third insulating layer for connecting with the fourth conductive layer to be formed later.
  • the fourth insulating layer 106 includes a first planar layer.
  • the fourth insulating layer 106 includes two layers of a passivation layer and a first flat layer, and the via hole formed in the fourth insulating layer needs to penetrate through the two layers of the passivation layer and the first flat layer.
  • the first flat layer is located on the side of the passivation layer away from the third conductive layer.
  • Step S70 A fourth conductive material layer is formed on the fourth insulating layer 106, and a patterning process is performed on the fourth conductive material layer to form a fourth conductive layer 204 as shown in FIG. 4D, that is, a third power line 260, The first power line 270 and the fourth connection electrode 234 are connected to each other and the third power line 260 and the first power line 270 are insulated from the fourth connection electrode 234.
  • the plurality of first power lines 270 extend along the first direction D1, and are respectively electrically connected to the plurality of second power lines 250 through the vias 306 in a one-to-one correspondence.
  • each first power line 270 and the corresponding second power line 250 overlap each other in a direction perpendicular to the base substrate 101.
  • the via 306 penetrates the fourth insulating layer 106.
  • the fourth connection electrode 234 and the third connection electrode 233 overlap in a direction perpendicular to the base substrate 101, and the third connection electrode 234 passes through a via 307 penetrating the fourth insulating layer 106. It is electrically connected to the third connection electrode 233.
  • the manufacturing method of the display substrate may further include forming a fifth insulating layer 107 on the fourth conductive layer 204, and forming a fifth insulating layer 107 in the fifth insulating layer 107 for subsequent formation.
  • the fifth insulating layer 107 may be a second flat layer.
  • the fifth insulating layer via hole for example, is used to connect the drain of the first transistor to the first electrode of the light emitting device.
  • the fifth insulating layer via hole and the second electrode of the first transistor may or may not overlap.
  • a connecting line connection may be additionally provided in the third conductive layer, and the specific situation is related to the position and shape of the first electrode of the sub-pixel arrangement structure.
  • the manufacturing method of the display substrate may further include forming a fifth conductive material layer on the fifth insulating layer 107, and performing a patterning process on the fifth conductive material layer to form the fifth conductive layer 205, that is, forming a plurality of insulating layers.
  • the first electrode 134 is used to form a light-emitting element.
  • each first electrode 134 includes a main body portion 141 and a connection portion 142.
  • the main body portion 141 is mainly used to drive the light-emitting layer to emit light
  • the connection portion 142 is mainly used to electrically connect with the pixel circuit.
  • the connecting portion 142 is electrically connected to the fourth connecting electrode 234 through a via 308 in the fifth insulating layer 107, for example, in a direction parallel to the surface of the base substrate 101, the via 308 Compared with the via 307, it is farther away from the main portion 141 of the first electrode 134, that is, the opening area 600 of the sub-pixel, that is, the orthographic projection of the via 308 on the base substrate 101 is compared with that of the via 307 on the lining. The orthographic projection on the base substrate 101 is farther away from the orthographic projection of the opening area 600 on the base substrate.
  • the manufacturing method of the display substrate may further include sequentially forming a pixel defining layer 108 on the fifth conductive layer 205, and in the pixel defining layer 108 corresponding to the main body of each first electrode 134
  • the portion 141 forms an opening area 600, and then at least a light emitting layer 136 is formed in the opening area 600, and a second electrode 135 is formed on the light emitting layer.
  • the openings for the sub-pixels of different colors are realized, which are separated by the first power line 270.
  • the ratio of the area ratio between the first part and the area ratio between the second part of the two parts of the orthographic projection of the opening is within a certain range.
  • the width of the first power line at the position corresponding to the area where the plurality of openings are in the orthographic projection of the base substrate adjust the corresponding first power line in the orthographic projection of the plurality of openings on the base substrate.
  • the width of the area outside the corresponding position to maintain the power line load balance.
  • the directions of the first power line, the second power line and the third power line and the first can be adjusted to make the overlap area of each power line and the semiconductor layer as large as possible to increase the aperture ratio.
  • one pixel When forming one pixel includes forming four sub-pixels: red sub-pixel, blue sub-pixel, first green sub-pixel, and second green sub-pixel, where the red sub-pixel and blue sub-pixel are shared, the formation of the red sub-pixel, the blue sub-pixel,
  • the openings corresponding to each of the blue sub-pixel, the first green sub-pixel, and the second green sub-pixel are divided into two parts by the orthographic projection of the first power line on the base substrate, including: the opening for the red sub-pixel, the blue The openings of the color sub-pixels, the openings of the first green sub-pixels, and the openings of the second green sub-pixels make the first part of the orthographic projection of the red sub-pixels, the first part of the openings of the blue sub-pixels, and the first green sub-pixels
  • the material of the semiconductor material layer includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene , Polythiophene, etc.).
  • silicon-based materials a-Si, polysilicon, p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene , Polythiophene, etc.
  • the materials of the first conductive material layer, the second conductive material layer, the third conductive material layer, the fourth conductive material layer, the fifth conductive material layer, and the second electrode may include gold (Au), silver (Ag), Copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combined with the above metals; or transparent metal oxide conductive materials, such as indium tin oxide (ITO), Indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • ITO indium tin oxide
  • IZO Indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • some of these insulating layers may also be organic materials, such as the first flat layer and the second flat layer, such as polyimide (PI), acrylate, epoxy, polymethylmethacrylate (PMMA), etc.
  • PI polyimide
  • PMMA polymethylmethacrylate
  • the fourth insulating layer 106 and the fifth insulating layer 107 may include flat layers, respectively.
  • the above-mentioned patterning process may use a conventional photolithography process, for example, including the steps of photoresist coating, exposure, development, drying, and etching.

Abstract

一种显示基板（20）及其制作方法和显示装置（40），显示基板（20）包括位于衬底基板（101）上的多个子像素（100），包括：第一金属层，其包括多条第一电源线（270）；第一平坦层；第一电极层，其具有彼此间隔开的多个第一电极（134）；以及像素界定层，其具有与多个第一电极（134）一一对应并暴露出多个第一电极（134）的多个开口（181），多个开口（181）对应至少两种不同颜色的子像素，多条第一电源线（270）中的一条在衬底基板（101）上的正投影将多个开口（181）中的一个在衬底基板（101）上的正投影分隔为位于多条第一电源线（270）的第一侧的第一部分（R1、B1、G'1、G"1）和位于条第一电源线（270）的第二侧的第二部分（R2、B2、G'2、G"2），针对至少两种不同颜色的子像素，开口（181）正投影的第一部分（R1、B1、G'1、G"1）之间的面积比与开口（181）正投影的第二部分（R2、B2、G'2、G"2）之间的面积比之间的比值在0.8-1.2范围内。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
随着有源矩阵有机发光二极管(AMOLED，Active-matrix organic light emitting diode)显示器件的高速发展，优化像素结构从而改善显示效果成为必然趋势。
发明内容
根据本公开的一个方面，提供了一种显示基板，包括：衬底基板；以及多个子像素，其位于所述衬底基板上，所述多个子像素包括：第一金属层，其位于所述衬底基板上，所述第一金属层包括多条第一电源线；第一平坦层，其位于所述第一金属层远离所述衬底基板的一侧；第一电极层，其位于所述第一平坦层远离所述第一金属层的一侧，并具有彼此间隔开的多个第一电极；以及像素界定层，其位于所述第一电极层远离所述第一平坦层的一侧，并具有与所述多个第一电极一一对应并暴露出所述多个第一电极的多个开口，所述多个开口对应至少两种不同颜色的子像素，其中，所述多条第一电源线中的一条在所述衬底基板上的正投影将所述多个开口中的一个在所述衬底基板上的正投影分隔为位于该条第一电源线的第一侧的第一部分和位于该条第一电源线的第二侧的第二部分，针对至少两种不同颜色的子像素，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比之间的比值在0.8-1.2范围内。
在一些实施例中，所述至少两种不同颜色的子像素包括第一颜色的第一子像素，所述第一电源线沿第一方向延伸，所述第一部分和 所述第二部分沿第二方向排列，所述第一方向和所述第二方向相交，所述多条第一电源线包括彼此平行设置的第一子电源线，所述第一子电源线在所述衬底基板上的正投影将所述第一子像素对应的开口正投影分隔为第一部分和第二部分，所述第一子电源线包括依次连接的作为重复单元的第一重复部分和第二重复部分，所述第一子像素在所述衬底基板上的正投影分别与相应第一子电源线的第一重复部分和第二重复部分在所述衬底基板上的正投影交叠，并且所述第一子像素在所述衬底基板上的正投影与所述第一重复部分在所述衬底基板上的正投影的重叠面积大于所述第一子像素在所述衬底基板上的正投影与所述第二重复部分在所述衬底基板上的正投影的重叠面积。
在一些实施例中，所述第一颜色的第一子像素包括红色子像素(R)和/或蓝色子像素(B)，所述第一重复部分的中轴线相对于所述第二重复部分的中轴线远离所述红色子像素(R)和/或所述蓝色子像素(B)的对应开口正投影的第二部分(R2，B2)并且所述第一重复部分在靠近所述红色子像素(R)和/或所述蓝色子像素(B)对应开口正投影的第二部分(R2，B2)的一侧挖空。
在一些实施例中，所述至少两种不同颜色的子像素还包括与所述第一子像素的第一颜色不同的第二颜色的第二子像素，所述多条第一电源线还包括与所述第一子电源线彼此平行交替设置的第二子电源线，所述第二子电源线包括依次连接的作为重复单元的第三重复部分、第四重复部分和第五重复部分，所述第二子像素在所述衬底基板上的正投影分别与相应第二子电源线的第四重复部分和第五重复部分在所述衬底基板上的正投影交叠，并且所述第二子像素在所述衬底基板上的正投影与所述第五重复部分在所述衬底基板上的正投影的重叠面积大于所述第二子像素在所述衬底基板上的正投影与所述第四重复部分在所述衬底基板上的正投影的重叠面积。
在一些实施例中，所述至少两种不同颜色的子像素还包括与所述第二子像素的第二颜色相同的第三子像素，所述第三子像素在所述衬底基板上的正投影与相应第二子电源线的第五重复部分在所述衬底基板上的正投影交叠。
在一些实施例中，所述第二颜色的第二子像素和第三子像素包括绿色子像素，所述第三重复部分的中轴线、所述第四重复部分的中轴线和所述第五重复部分的中轴线依次靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)，并且所述第三重复部分在靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空，所述第五重复部分在远离所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空。
在一些实施例中，所述第一重复部分的线宽在3μm-4.6μm之间，所述第二重复部分的线宽在4.5μm-6.9μm之间，所述第三重复部分的线宽3μm-4.6μm之间，所述第四重复部分的线宽5.3μm-8.1μm之间，所述第五重复部分的线宽2.4μm-3.6μm之间。
在一些实施例中，所述第一重复部分的线宽为3.8μm，所述第二重复部分的线宽在5.7μm，所述第三重复部分的线宽3.8μm，所述第四重复部分的线宽6.7μm，所述第五重复部分的线宽3.0μm。
在一些实施例中，所述显示基板还包括：第二金属层，其位于所述衬底基板上，包括多条第二电源线，所述多条第二电源线沿所述第一方向延伸，并且所述多条第一电源线在所述衬底基板上的正投影和所述多条第二电源线在所述衬底基板上的正投影在垂直于所述衬底基板的方向上分别至少部分交叠；第二平坦层，其位于所述第二金属层上，所述第一金属层位于所述第二平坦层上，并且所述多条第一电源线和所述多条第二电源线通过贯穿所述第二平坦层的过孔连接。
在一些实施例中，所述显示基板还包括多条第三电源线，其中，所述多条第三电源线沿所述第二方向延伸，并将所述多条第一电源线电连接，所述多条第三电源线在所述衬底基板上的正投影与每个子像素的开口在所述衬底基板上的正投影在垂直于衬底基板的方向上均不重叠，所述多条第三电源线与所述第一电源线同层设置且为一体的结构。
在一些实施例中，所述多条第三电源线中的每一条包括依次连接的作为重复单元的第三子电源线和第四子电源线，所述第三子电源线和所述第四子电源线沿所述第二方向交替延伸，并且所述多条第三 电源线沿所述第一方向排列；所述第三子电源线包括依次连接的作为重复单元的第六重复部分、第七重复部分和第八重复部分，所述第七重复部分的延伸方向与所述第二方向平行，所述第六重复部分的延伸方向与所述第一方向和所述第二方向均相交，所述第八重复部分的延伸方向与所述第一方向和所述第二方向均相交且与所述第六重复部分的延伸方向不同；所述第四电源线包括第九重复部分和第十重复部分，所述第九重复部分的延伸方向与所述第二方向平行，所述第十重复部分的延伸方向与所述第一方向和所述第二方向均相交。
在一些实施例中，所述至少两种不同颜色的子像素包括红色子像素(R)、蓝色子像素(B)和绿色子像素(G)，所述红色子像素(R)和所述蓝色子像素(B)分别沿所述第一方向和所述第二方向交替排列，沿所述第一方向，所述第四子电源线位于所述红色子像素(R)的第二部分(R2)在所述衬底基板上的正投影和相邻的所述蓝色子像素(B)的第二部分(R2)在所述衬底基板上的正投影之间；所述绿色子像素(G)沿所述第一方向和所述第二方向排列，沿所述第一方向，所述第三子电源线位于相邻的所述绿色子像素(G)的第二部分(G2)在所述衬底基板上的正投影之间。
在一些实施例中，一个像素包括红色子像素(R)和蓝色子像素(B)，与所述红色子像素(R)和所述蓝色子像素(B)分别一一对应的开口正投影均被所述第一电源线在所述衬底基板上的正投影分隔为对应的第一部分和第二部分，所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述蓝色子像素(B)对应的开口正投影的第一部分(B1)的面积比为R1/B1，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)与所述蓝色子像素(B)对应的开口正投影的第二部分(B2)的面积比为R2/B2，其中，R1/B1＝R2/B2＝1∶1.644。
在一些实施例中，一个像素包括红色子像素(R)和绿色子像素(G)，所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述绿色子像素(G)对应的开口正投影的第一部分(G1)的面积比为R1/G1，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)与所述绿色子像素(G)对应的开口正投影的第二部分(G2)的面积比为R2/G2， 其中，R1/G1＝R2/G2＝1∶1.04。
在一些实施例中，一个像素包括蓝色子像素(B)和绿色子像素(G)，所述蓝色子像素(B)对应的开口正投影的第一部分(B1)与所述绿色子像素(G)对应的开口正投影的第一部分(G1)的面积比为B1/G1，所述蓝色子像素(B)对应的开口正投影的第二部分(B2)与所述绿色子像素(G)对应的开口正投影的第二部分(G2)的面积比为B2/G2，其中，B1/G1＝B2/G2＝1.644∶1.04。
在一些实施例中，一个像素包括红色子像素(R)、第一绿色子像素(G’)和第二绿色子像素(G”)，所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述第一绿色子像素(G’)对应的开口正投影的第一部分(G’1)和所述第二绿色子像素(G”)对应的开口正投影的第一部分(G”2)的和之间的面积比为R1/(G’1+G”1)，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)、与所述第一绿色子像素(G’)对应的开口正投影的第二部分(G’2)和所述第二绿色子像素(G”)对应的开口正投影的第二部分(G”2)的和之间的面积比为R2/(G’2+G”2)，其中，R1/(G’1+G”1)＝R2/(G’2+G”2)＝1∶1.04。
在一些实施例中，一个像素包括蓝色子像素(B)、第一绿色子像素(G’)和第二绿色子像素(G”)，所述蓝色子像素(B)对应的开口正投影的第一部分(B1)、与所述第一绿色子像素(G’)对应的开口正投影的第一部分(G’1)和所述第二绿色子像素(G”)对应的开口正投影的第一部分(G”1)的和之间的面积比为B1/(G’1+G”1)，所述蓝色子像素(B)对应的开口正投影的第二部分(B2)、与所述第一绿色子像素(G’)对应的开口正投影的第二部分(G’2)和所述第二绿色子像素(G”)对应的开口正投影的第二部分(G”2)的和之间的面积比为B2/(G’2+G”2)，其中，B1/(G’1+G”1)＝B2/(G’2+G”2)＝1.644∶1.04。
在一些实施例中，所述多个子像素中的每一个包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路沿第一方向和第二方向分布为多行多列；所述像素电路包括驱动子电路、数据写入子电路、补偿子电路和存储子电路；所述驱动子电路包括控制端、第一端和第二端，且配置为与所述发光元件耦接并且控 制流经发光元件的驱动电流；所述数据写入子电路包括控制端、第一端和第二端，所述数据写入子电路的控制端配置为接收第一扫描信号，所述数据写入子电路的第一端配置为接收数据信号，所述数据写入子电路的第二端与所述驱动子电路电连接，所述数据写入子电路配置为响应于所述第一扫描信号将所述数据信号写入所述驱动子电路的第一端；所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；所述存储子电路与所述驱动子电路的控制端和第一电压端电连接，且被配置为存储所述数据信号；所述存储子电路包括存储电容，所述存储电容的第一电容电极和所述第一电压端耦接，第二电容电极和所述驱动子电路的控制端电耦接，所述第一电压端与所述多条第一电源线耦接；所述多个子像素包括在所述第二方向上直接相邻的第一子像素和第二子像素，所述第一子像素中的第一电容电极与所述第二子像素中的第一电容电极同层设置且彼此间隔。
在一些实施例中，所述显示基板还包括多条数据线，所述多条数据线沿所述第一方向延伸，所述多条数据线被配置为向所述子像素提供数据信号。
在一些实施例中，所述多条第二电源线与所述多条数据线同层绝缘设置。
在一些实施例中，每个子像素还包括发光元件，所述发光元件包括依次层叠设置的所述第一电极、发光层和第二电极，所述第一电极位于所述发光层靠近所述衬底基板的一侧；所述第三电源线在所述衬底基板上的正投影与每个子像素的所述第一电极在所述衬底基板上的正投影在垂直于所述衬底基板的方向上不重叠。
根据本公开的另一方面，还提供了一种显示装置，包括以上所述的显示基板。
根据本公开的另一方面，还提供了一种用于制作显示基板的方法，包括：提供衬底基板；在所述衬底基板上形成多个子像素，其中， 所述多个子像素中的每一个包括：第一金属层，其位于所述衬底基板上，所述第一金属层包括多条第一电源线；第一平坦层，其位于所述第一金属层远离所述衬底基板的一侧；第一电极层，其位于所述第一平坦层远离所述第一金属层的一侧，并具有彼此间隔开的多个第一电极；以及像素界定层，其位于所述第一电极层远离所述第一平坦层的一侧，并具有与所述多个第一电极一一对应并暴露出所述多个第一电极的多个开口，所述多个开口对应至少两种不同颜色的子像素，其中，所述多条第一电源线中的一条在所述衬底基板上的正投影将所述多个开口中的一个在所述衬底基板上的正投影分隔为位于该条第一电源线的第一侧的第一部分和位于该条第一电源线的第二侧的第二部分，针对至少两种不同颜色的子像素，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比之间的比值在0.8-1.2范围内。
在一些实施例中，通过调整与所述多个开口在所述衬底基板的正投影所在区域对应位置处的第一电源线的宽度来实现针对不同颜色子像素的开口，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比的比值在0.8-1.2范围内。
在一些实施例中，在调整与所述多个开口在所述衬底基板的正投影所在区域对应位置处的第一电源线的宽度的同时，调整相应第一电源线在与所述多个开口在所述衬底基板的正投影所在区域对应位置之外的宽度。
在一些实施例中，所述第一电源线形成为沿第一方向延伸，所述第一部分和所述第二部分沿第二方向排列，所述第一方向和所述第二方向相交，所述至少两种不同颜色的子像素包括红色子像素(R)、蓝色子像素(B)和绿色子像素(G)，所述多条第一电源线包括彼此平行交替设置的第一子电源线和第二子电源线，所述第一子电源线在所述衬底基板上的正投影将红色子像素(R)和蓝色子像素(B)对应的开口正投影分隔为第一部分(R1，B1)和第二部分(R2，B2)，所述第二子电源线在所述衬底基板上的正投影将绿色子像素(G)对应的开口正投影分隔为第一部分(G1)和第二部分(G2)，所述第一子电源线包括依次连接 的作为重复单元的第一重复部分和第二重复部分，所述第一重复部分的中轴线相对于所述第二重复部分的中轴线远离所述红色子像素(R)和所述蓝色子像素(B)的对应开口正投影的第二部分(R2，B2)并且所述第一重复部分在靠近所述红色子像素(R)和所述蓝色子像素(B)对应开口正投影的第二部分(R2，B2)的一侧挖空，所述红色子像素(R)和所述蓝色子像素(B)在所述衬底基板上的正投影分别与相应第一子电源线的第一重复部分和第二重复部分在所述衬底基板上的正投影交叠；所述第二子电源线包括依次连接的作为重复单元的第三重复部分、第四重复部分和第五重复部分，所述第三重复部分的中轴线、所述第四重复部分的中轴线和所述第五重复部分的中轴线依次靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)，并且所述第三重复部分在靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空，所述第五重复部分在远离所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空，所述绿色子像素(G)在所述衬底基板上的正投影分别与相应第二子电源线的第四重复部分和第五重复部分在所述衬底基板上的正投影或者与相应第二子电源线的第五重复部分在所述衬底基板上的正投影交叠。
在一些实施例中，所述第一重复部分的线宽为3.8μm，所述第二重复部分的线宽在5.7μm，所述第三重复部分的线宽3.8μm，所述第四重复部分的线宽6.7μm，所述第五重复部分的线宽3.0μm。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1A为相关技术中的一种显示基板的部分结构示意图；
图1B为显示基板的开口翘曲示意图；
图2为根据本公开实施例的显示基板的示意图；
图3A为根据本公开实施例的显示基板的示意图；
图3B为根据本公开实施例的显示基板的像素电路结构示意图；
图3C为根据本公开实施例的显示基板的像素电路图；
图4A-图4D为根据本公开实施例的像素电路的各层的示意图；
图4E为图4D沿剖面线C-C’的剖视图；
图4F为图4D沿剖面线C’-C”的剖视图；
图5为根据本公开实施例的的显示装置的示意图；
图5A为根据本公开实施例的部分结构示意图；
图6为图5沿剖面线A-A’的剖视图；
图7为根据本公开实施例的显示基板的示意图；
图8A为图2沿剖面线B-B’的剖视图；
图8B为根据本公开实施例的显示基板中的像素电路图；
图9为根据本公开实施例的第一电容电极的示意图；
图10为根据本公开实施例的显示面板的示意图；
图11为根据本公开实施例的显示装置的示意图；以及
图12为根据本公开实施例的显示基板的制作方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
图1A为相关技术中一种显示基板的部分结构的示意图，图1B 为图1A中显示基板的开口翘曲示意图。
如图1A示出了子像素开口及其下的电源线。由于在电源信号线上依次设置平坦层和像素界定层，像素界定层的开口被叠加的该电源信号线分隔成两部分。由于存在电源信号线，该处开口下方出现高度差，可能会使开口中的有机发光材料在开口的被分隔为两部分中的面积较小的一侧(虚线标注所示)发生翘曲，导致出现色偏。
如图1B示出了像素开口处的翘曲。如图1B所示，在电源信号线15上设置有平坦层16，在平坦层16上设置有发光元件的阳极17，阳极17上设置有像素界定层18。像素界定层18具有开口181，阳极17在开口181处暴露，有机发光材料层19位于开口181暴露的阳极17上。由于存在电源信号线15，导致阳极17发生翘曲，进而使得有机发光材料层19发生翘曲，导致不同颜色子像素的左右两侧发光区发出的光强度不匹配。
如图1A示出了电源信号线15与开口181之间的位置关系，其中，四个开口G1(第一绿色)、G2(第二绿色)、R(红色)、B(蓝色)分别用于形成对应颜色的有机发光层，该四种颜色的有机发光层用于形成对应颜色的子像素，并作为重复单元在显示面板上重复排列。
如图1A所示，沿D2方向，各开口181被电源信号线15分隔成左右两部分，例如被分隔成面积不等的左右两部分，其中左部分的面积小于右部分的面积。沿D1方向，电源信号线15在不同位置具有不同宽度，例如，电源信号线15在第一位置处具有宽度6.7μm，在第二位置处具有宽度4.3μm。第一方向D1与第二方向D2交叉，例如正交。由于存在电源信号线15，使得开口181下方出现高度差，会使得开口181中的有机发光材料层19被电源信号线15分隔的两部分中面积较小部分发生翘曲，从而出现色偏，如图1B中虚线框内所示。这会导致不同颜色子像素的左右两侧发光区发出的光强度不匹配。采用这样的显示基板的显示装置会发生大视角色偏，人眼观看时，出现类似一侧发红，另一侧发青的色偏现象。
在相关技术中，通常采用双电源线像素结构，即为减小负载， 在电源信号线上通常叠加另一层电源线。例如，在电源信号线15之上或之下设置另一层电源线，两者之间通过绝缘层间隔开并通过绝缘层中的过孔连接，本公开以双电源线像素结构为例来进行说明。
因此，根据本公开的一个方面，提供了一种显示基板及显示装置，该显示基板包括：衬底基板；以及多个子像素，其位于所述衬底基板上，所述多个子像素包括：第一金属层，其位于所述衬底基板上，所述第一金属层包括多条第一电源线；第一平坦层，其位于所述第一金属层远离所述衬底基板的一侧；第一电极层，其位于所述第一平坦层远离所述第一金属层的一侧，并具有彼此间隔开的多个第一电极；以及像素界定层，其位于所述第一电极层远离所述第一平坦层的一侧，并具有与所述多个第一电极一一对应并暴露出所述多个第一电极的多个开口，所述多个开口对应至少两种不同颜色的子像素。其中，所述多条第一电源线中的一条在所述衬底基板上的正投影将所述多个开口中的一个在所述衬底基板上的正投影分隔为位于该条第一电源线的第一侧的第一部分和位于该条第一电源线的第二侧的第二部分，针对至少两种不同颜色的子像素，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比之间的比值在0.8-1.2范围内。该比值范围可以使得人眼不能分辨出两侧的混光比例不同导致的色偏，即改善显示面板的色偏。
为有利于理解，以图1A为例，第一电源线沿D1方向延伸，多条第一电源线沿D2方向排列，红色子像素R、蓝色子像素B、绿色子像素G在衬底基板上的正投影分别被第一电源线分为第一部分R1，B1，G1，其中，绿色子像素G包括第一绿色子像素G’和第二绿色子像素G”，并且第一绿色子像素G’和第二绿色子像素G”也分别被第一电源线分隔为第一部分G’1，G”1和第二部分G’2，G”2。各子像素被第一电源线分隔的两部分沿D2方向排列。第一部分G’1，G”1，R1，B1位于第一电源线的第一侧，第二部分G’2，G”2，R2，B2位于第一电源线的第二侧。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
如图3A所示，该显示基板20包括阵列分布的多个子像素100、多条栅线11和多条数据线12。每个子像素100包括发光元件和驱动该发光元件的像素电路。多条栅线11和多条数据线12彼此交叉在显示区中定义出阵列分布的多个像素区，每个像素区中设置一个子像素100的像素电路。该像素电路例如为常规的像素电路，例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路，并且不同的实施例中，该像素电路还可以进一步包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示基板还可以包括位于非显示区中的栅极驱动子电路13和数据驱动子电路14。该栅极驱动子电路13通过栅线11与像素电路连接以提供各种扫描信号，该数据驱动子电路14通过数据线12与像素电路连接以提供数据信号。其中，图3A中示出的栅极驱动子电路13和数据驱动子电路14，栅线11和数据线12在显示基板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
例如，显示基板20还可以包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动子电路14施加该数据信号，以及控制栅极驱动子电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器 例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。图3B示出了一种像素电路的示意图。
如图3B所示，该像素电路包括驱动子电路122、数据写入子电路126、补偿子电路128、存储子电路127、第一发光控制子电路123、第二发光控制子电路124及复位电路129。
例如，驱动子电路122包括控制端131、第一端132和第二端133，其配置为控制流经发光元件120的驱动电流，且驱动子电路122的控制端131和第一节点N1连接，驱动子电路122的第一端132和第二节点N2连接，驱动子电路122的第二端133和第三节点N3连接。
例如，数据写入子电路126包括控制端、第一端和第二端，其控制端配置为接收第一扫描信号，第一端配置为接收数据信号，第二端与驱动子电路122的第一端132(第二节点N2)连接，且配置为响应于该第一扫描信号Ga1将该数据信号写入驱动子电路122的第一端132。例如，数据写入子电路126的第一端与数据线12连接以接收该数据信号，控制端与扫描线11连接以接收该第一扫描信号Ga1。
例如，在数据写入阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端132(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件120发光的驱动电流。
例如，补偿子电路128包括控制端、第一端和第二端，其控制端配置为接收第二扫描信号Ga2，其第一端和第二端分别与驱动子电路122的控制端131和第二端133电连接，该补偿子电路配置为响 应于该第二扫描信号对该驱动子电路120进行阈值补偿。
例如，存储子电路127与驱动子电路122的控制端131及第一电压端VDD电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端131和第二端133电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端132(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电源电压施加至驱动子电路122的第一端132。例如，如图3B所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光元件120的第一端510以及驱动子电路122的第二端132连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光元件122。
例如，在发光阶段，第二发光控制子电路123响应于第二发光控制端EM2提供的第二发光控制信号而开启，从而驱动子电路122可以通过第二发光控制子电路123与发光元件120电连接，从而驱动发光元件120在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路123响应于第二发光控制信号而截止，从而避免有电流流过发光元件120而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动子电路122以及发光元件120进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同或不同，例如二者可以连接到相同或不同的信号输出端。
例如，复位电路129与复位电压端Vinit以及发光元件122的第一端134(第四节点N4)连接，且配置为响应于复位信号将复位电压施加至发光元件120的第一端134。在另一些示例中，如图3B所示，该复位信号还可以施加至驱动子电路的控制端131，也即第一节点N1。例如，复位信号为该第二扫描信号，复位信号还可以是和第二扫描信号同步的其他信号，本公开的实施例对此不作限制。例如，如图3B所示，该复位电路129分别和发光元件120的第一端134、复位电压端Vinit以及复位控制端Rst(复位控制线)连接。例如，在初始化阶段，复位电路129可以响应于复位信号而开启，从而可以将复位电压施加至发光元件120的第一端134及第一节点N1，从而可以对驱动子电路122、补偿子电路128以及发光元件120进行复位操作，消除之前的发光阶段的影响。
例如，发光元件120包括第一端134和第二端135，发光元件120的第一端134配置为与驱动子电路122的第二端133耦接，发光元件120的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图3B所示，发光元件120的第一端134可以通过第二发光控制子电路124连接至第三节点N3。本公开的实施例包括但不限于此情形。例如，发光元件120可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，该OLED的第一电极和第二电极分别作为该发光元件的第一端134和第二端135。本公开的实施例对发光元件的具体结构不作限制。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位信 号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图3C为图3B所示的像素电路的一种具体实现示例的电路图。如图3C所示，该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图3C所示，驱动子电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动子电路122的控制端131，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端132，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端133，和第三节点N3连接。
例如，如图3C所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端132(第二节点N2)连接。例如，该第二晶体管T2为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图3C所示，补偿子电路128可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动子电路122的控制端131(第一节点N1)连接，第三晶体管T3的第二极和驱动子电路122的第二端133(第三节点N3)连接。
例如，如图3C所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极Ca和第二电容电极Cb，该第一电容电极Ca和第一电压端VDD耦接，例如电连接，该第二电容电极Cb和驱动子电路122的控制端131耦接，例如电连接。
例如，如图3C所示，第一发光控制子电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制 端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端132(第二节点N2)连接。
例如，发光元件120可以具体实现为OLED，其第一电极134(这里为阳极)和第四节点N4连接配置为通过第二发光控制子电路124从驱动子电路122的第二端133接收驱动电流，发光元件120的第二电极135(这里为阴极)配置为和第二电压端VSS连接以接收第二电源电压。例如第二电压端可以接地，即VSS可以为0V。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端133(第三节点N3)连接，第五晶体管T5的第二极和发光元件120的第一端134(第四节点N4)连接。
例如，复位电路129可以包括第一复位电路和第二复位电路，该第一复位电路配置为响应于第一复位信号Rst1将第一复位电压Vini1施加到第一节点N1，该第二复位电路配置为响应于第二复位信号Rst2将第二复位电压Vini2施加到第四节点N4。例如，如图1C所示，该第一复位电路实现为第六晶体管T6，该第二复位电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述 了其中一极为第一极，另一极为第二极。
图2为根据本公开实施例的显示基板20的示意图。该显示基板20包括衬底基板101，多个子像素100位于该衬底基板101上。多个子像素100的像素电路布置为像素电路阵列。该像素电路阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。在一些实施例中，所述第一方向D1也可以为行方向，第二方向D2也可以为列方向。在一些实施例中，各子像素的像素电路除与发光元件的连接结构外，可以具有完全相同的结构，即像素电路在行和列方向重复排列，不同子像素的与发光元件的连接结构根据各个子像素的发光结构的电极的布置形状和位置可以不同。在一些实施例中，不同颜色子像素的像素电路的大致框架例如各个信号线的形状和位置基本相同，各个晶体管的相对位置关系也基本相同，但对于有些信号线或连接线的宽度、形状，或者某些晶体管的例如沟道尺寸、形状，或者用于与不同子像素的发光元件连接的连接线或者过孔位置等可以有不同，可以根据各个布局结构以及子像素排列进行调整。图2中示例性地示出了一行子像素中直接相邻的四个子像素(即第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d)，本公开的实施例不限于此布局。
图4A对应于图2示意出了该四个子像素100中晶体管T1-T7的半导体层102和第一导电层(栅极层)201，图4B在图4A的基础上还示出了第二导电层202，图4C在图4B的基础上还示出了第三导电层203，图4D在图4C的基础上还示出了第四导电层204。需要说明的是，图中仅示意性地示出了一行子像素中相邻的四个子像素的相应结构，但这不应作为对本公开的限制。该半导体层102、第一导电层201、第二导电层202、第三导电层203、第四导电层204依次设置于衬底基板101上，从而形成如图2所示的显示基板的结构。
为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和有源层，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，如图4A所示，该第一导电层201包括每个晶体管的栅极以及一些扫描线和控制线。图4A中用大虚线框示出了每个子像素100所在的区域，用小虚线框示出了一个子像素100中第一到第七晶体管T1-T7的栅极T1g-T7g。
该半导体层102包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图4A所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层20为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔。
例如，如图4A所示，该第一导电层201包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第三晶体管T3和第六晶体管T6采用双栅结构，这样可以提高晶体管的栅控能力，降低漏电流。
例如，该第一导电层201还包括彼此绝缘的多条扫描线210、多条复位控制线220和多条发光控制线230。例如，每行子像素分别对应连接一条扫描线210、一条复位控制线220和一条发光控制线230。
扫描线210与对应一行子像素中的第二晶体管T2的栅极电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线220与对应一行子像素中的第六晶体管T6的栅极电连接以提供第一复位信号Rst1，发光控制线230与对应一行子像素中的第四晶体管T4的的栅极电连接以提供第一发光控制信号EM1。
例如，如图4A所示，该扫描线210还与第三晶体管T3的栅极电连接以提供第二扫描信号Ga2，即第一扫描信号Ga1和第二扫描信号Ga2可以为同一信号；该发光控制线230还与第五晶体管T5的栅 极电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，如图4A所示，本行像素电路的第七晶体管T7的栅极与下一行像素电路(即按照扫描线的扫描顺序，在本行扫描线之后顺序开启的扫描线所在的像素电路行)所对应的复位控制线220电连接以接收第二复位信号Rst2。
例如，从图4A可知，在列方向(第一方向D1)划分像素区的栅线11可以是该复位控制线220或该发光控制线230，每个像素电路的区域都包含一条复位控制线220，一条发光控制线230和一条扫描线210的各一部分。
例如，如图4A所示，该显示基板20采用自对准工艺，利用第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。
例如，如图4B所示，该第二导电层202包括第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板101的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括过孔301，该过孔301暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。
例如，该第二导电层202还可以包括多条复位电压线240，该多条复位电压线240与多行子像素一一对应连接。该复位电压线240与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，如图4B所示，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应的的复位电压线240电连接以接收第二复位电压Vinit2。
例如，如图4B所示，该第二导电层202还可以包括屏蔽电极221，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底 基板101的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。由于该第二晶体管T2的第一极T2s配置为接收数据信号Vd，而该数据信号Vd决定了该子像素的显示灰阶，因此该屏蔽电极221提高了数据信号的稳定性，从而提高了显示性能。
例如，如图4C所示，该第三导电层203包括沿第一方向D1延伸的多条第二电源线250(多条第二电源线250对应第二金属层)。例如，该多条第二电源线250与多列子像素一一对应电连接以提供第一电源电压VDD。该第二电源线250通过过孔302与所对应的一列子像素中的第一电容电极Ca电连接，通过过孔303与第四晶体管T4的第一极电连接。例如，该第二电源线250还通过过孔304与屏蔽电极221电连接，从而使得屏蔽电极221具有固定电位，提高了该屏蔽电极的屏蔽能力。
例如，该第三导电层203还包括该多条数据线12。该多条数据线12与多列子像素一一对应电连接以提供数据信号。例如，该数据线12与所对应的的一列子像素中的第二晶体管T2的第一极T2s通过过孔305电连接以提供该数据信号。
具体的，考虑工艺余量(margin)的均一性和可靠性，通常过孔在行列方向排列，过孔304和过孔305在行方向大致位于同一直线上，且过孔304位于数据线12与第二晶体管T2的第一极T2s的连接过孔305远离数据线12的一侧。例如，过孔305位于数据线与第二晶体管T2的第一极T2s交叠的位置(例如第二晶体管T2的第一极T2s的端部，即半导体层102在左侧的端部)，过孔304位于第二电源线250覆盖的位置。
在一些实施例中，数据线12位于第二电源线250的左侧，且与第二电源线250均在列方向延伸，第一屏蔽电极221从覆盖过孔304的位置向下延伸一段并在不超出扫描线的位置向左侧延伸并且覆盖部分第二晶体管T2的第一极T2s，第一屏蔽电极221的形状大致为L型的左右镜像图案。需要说明的是，本实施例中，左侧是指数据线相对第二电源线所在的一侧，例如，一个像素电路的区域在行方向划 分的边界大致为一像素电路的数据线和同行中下一个(例如右侧相邻)像素电路的数据线，即相邻两条数据线之间的部分以及该像素电路的数据线构成该像素电路在行方向的范围。在其他实施例中，第二电源线或复位信号线等作为像素电路划分的边界，根据需要进行设计。
例如，如图4C所示，该第三导电层203还包括第一连接电极231，该第一连接电极231的一端通过第一电容电极Ca中的过孔301以及绝缘层中的过孔401与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔402与该第三晶体管T3的第一极电连接，从而将该第二电容电极Cb与该第三晶体管T3的第一极T3s电连接。例如，该过孔401贯穿第二绝缘层104和第二绝缘层105，该过孔402贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105(参考图6)。
例如，如图4C所示，该第三导电层203还包括第二连接电极232，该第二连接电极232的一端通过过孔403与复位电压线电连接，另一端通过过孔404与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔403贯穿第三绝缘层105，该过孔404贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105(参考图6)。
例如，如图4C所示，该第三导电层203还包括第三连接电极233，该第三连接电极233通过过孔405与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，例如，该过孔405贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105(参考图6)。后文将对此详细说明。
例如，如图4D所示，该第四导电层204包括第三电源线260，该第三电源线260沿第二方向D2延伸，并将多条第二电源线250电连接，从而形成网状的电源线结构。这种结构有助于降低电源线上的电阻从而降低电源线的压降，并有助于将第一电源电压均匀地输送至显示基板的各个子像素中。
例如，该第四导电层204还包括多条第一电源线270(多条第 一电源线270对应第一金属层)，该第一电源线270沿第一方向D1延伸，且分别与多条第二电源线250一一对应电连接。如图3D所示，该第一电源线270与对应的第二电源线250在垂直于衬底基板101的方向上彼此至少部分重叠，并通过过孔306彼此电连接。例如，对应于每个子像素分别设置一个该过孔306，从而每条第一电源线270与对应的第二电源线250形成并联结构，这有助于降低电源线的电阻。在一些实施例中，位于第三导电层中的第二电源线250为了避让某些结构例如过孔或者连接线，或者为了使得上层结构平坦，可以在部分位置线宽加宽或变窄。在一些实施例中，位于第四导电层中的第一电源线270为了避让某些结构例如过孔或者连接线，或者为了使得上层结构平坦，也可以在部分位置线宽加宽或变窄。这样，该第一电源线270与对应的第二电源线250在垂直于衬底基板101的方向上也会有部分位置不能完全重叠。
例如，该第三电源线260与第一电源线270彼此电连接或为一体的结构，从而该多条第二电源线250、多条第三电源线260及多条第一电源线270形成为网状的电源线结构。
如图5所示，第一电源线270沿第一方向D1延伸，各子像素对应开口的第一部分和第二部分沿第二方向D2排列，第一方向D1和第二方向D2垂直相交。多条第一电源线270包括彼此平行交替设置的第一子电源线31和第二子电源线32。第一子电源线31在衬底基板上101的正投影将红色子像素和蓝色子像素对应的开口在衬底基板上101的正投影分隔为第一部分和第二部分。第二子电源线32在衬底基板101上的正投影将绿色子像素对应的开口在衬底基板上的正投影分隔为第一部分和第二部分。
如图5所示，第一子电源线31包括依次连接的作为重复单元的第一重复部分311和第二重复部分312。第一重复部分311的中轴线相对于第二重复部分312的中轴线远离红色子像素和蓝色子像素对应开口在衬底基板上正投影的第二部分。并且，第一重复部分311在靠近红色子像素和蓝色子像素对应开口在衬底基板上正投影的第二部分的一侧挖空而缩进。红色子像素和蓝色子像素分别与相应第一 子电源线31的第一重复部分311和第二重复部分312交叠。
如图5所示，第二子电源线32包括依次连接的作为重复单元的第三重复部分321、第四重复部分322和第五重复部分323。第三重复部分321的中轴线、第四重复部分322的中轴线和第五重复部分323的中轴线依次靠近绿色子像素对应开口在衬底基板上正投影的第二部分。并且，第三重复部分321在靠近绿色子像素对应开口在衬底基板上正投影的第二部分一侧挖空，第五重复部分323在靠近绿色子像素对应开口在衬底基板上正投影的第一部分一侧挖空。绿色子像素分别与相应第二子电源线32的第四重复部分322和第五重复部分323交叠。
例如，该第四导电层204还包括与该第一电源线270绝缘的第四连接电极234，该第四连接电极234通过过孔307与第三连接电极233电连接，以将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接。例如，该第四连接电极234与该第三连接电极233在垂直于衬底基板101的方向至少部分重叠。
图5在图4D的基础上还示出了第五导电层205，该第五导电层205包括发光元件120的第一电极134。图6示出了图5沿剖面线A-A’的剖视图。
如图6所示，半导体层102、第一绝缘层103、第一导电层201、第二绝缘层104、第二导电层202、第三绝缘层105、第三导电层203、第四绝缘层106、第四导电层204、第五绝缘层107、第五导电层205依次设置于衬底基板101上，从而形成如图5所示的显示基板的结构。
结合图5和图6所示，第一电极134可以包括主体部141和连接部142，主体部141主要用于驱动发光层发光，主体部141在衬底基板101上的正投影覆盖该第一电极所属的子像素的开口区600在所述衬底基板上的正投影，连接部142主要用于与像素电路进行连接。如图5所示，第三电源线260与各第一电极134在垂直于衬底基板101的方向上不重叠。这种设置可以避免发光元件的第一电极134因与第三电源线260重叠而不平整导致色偏等显示问题。在 第一电极134上形成有像素界定层，像素界定层上形成开口区600，该开口区600暴露出第一电极134的主体部141的至少部分，并限定每个对应的子像素的发光区域(开口区)，发光元件120的发光层至少形成在像素界定层的开口区内。第一电极134的平整度会直接影响发光层的出光均匀性，从而影响显示效果。例如，该第三电源线260可以为曲线结构以与第一电极134的图案相适应，例如为折线状或波浪线形状。例如，相邻的两条第三电源线260界定一行子像素100。
例如，如图5所示，多条第三电源线260中的每一条包括依次连接的作为重复单元的第三子电源线41和第四子电源线42。
第三子电源线41包括依次连接的作为重复单元的第六重复部分261、第七重复部分262和第八重复部分263。第七重复部分262的延伸方向与第二方向D2平行，第六重复部分261的延伸方向与第一方向D1和第二方向D2均相交，第八重复部分263的延伸方向与第一方向D1和第二方向D2均相交且与第六重复部分261的延伸方向不同。如图5A所示，绿色子像素G沿所述第一方向交替排列，第三子电源线41位于绿色子像素G(包括第一绿色子像素G’和第二绿色子像素G”)的第二部分G2(包括第一绿色子像素G’对应的开口正投影的第二部分G’2和第二绿色子像素G”对应的开口正投影的第二部分G”2)在衬底基板上的正投影和绿色子像素G的第二部分G2在所述衬底基板上的正投影之间。并且，如图2中的子像素100a所示，第三子电源线41位于绿色子像素对应开口在衬底基板上正投影的第一侧与相邻红色子像素或蓝色子像素对应开口在衬底基板上正投影的第二侧之间的区域中。
第四子电源线42包括第九重复部分264和第十重复部分265，第九重复部分264的延伸方向与第二方向平行，第十重复部分265的延伸方向与第一方向和第二方向均相交。如图5A所示，红色子像素R和蓝色子像素B分别沿第一方向交替排列，第四子电源线位于红色子像素R的第二部分R2在衬底基板上的正投影和蓝色子像素B的第二部分R2在衬底基板上的正投影之间。并且，如图2中的子像 素100b所示，第四子电源线42位于红色子像素或蓝色子像素对应开口在衬底基板上正投影的第一侧与相邻绿色子像素对应开口在衬底基板上正投影的第二侧之间的区域。
第三电源线的设置原则为保持与半导体层图案的最大重叠面积，以增大开口率。例如，第一电极134的主体部141形状为四边形，例如，每个第九重复部分264对应一个第一电极134的主体部141的一个顶角设置，与该第九重复部分264与半导体层102中沿第一方向D1的部分最大限度交叠，相邻的第十重复部分265与半导体层的不同于第一方向D1和第二方向D2的部分交叠。同理，第三电源线的第六重复部分261、第七重复部分262和第八重复部分263，以及第一电源线270和第二电源线250的各部分也沿半导体层102图案的延伸方向进行设置。
图4E示出了图4D沿剖面线C-C面的剖视图。如图4E所示，该第三电源线260的第九重复部分264和该复位控制线220在垂直于衬底基板101的方向上存在交叠；该第十重复部分265与一条数据线12在垂直于衬底基板101的方向上存在交叠，该数据线12与该第十重复部分265所对应的一列像素电路电连接以提供该数据信号。
图4F示出了图4D沿剖面线C’-C”的剖视图。如图4F所示，该第三电源线260的第六重复部分261和第七重复部分262分别与第一连接电极231在垂直于衬底基板101的方向上存在交叠；该第七重复部分262与扫描线210在垂直于衬底基板101的方向上存在交叠，该第八重复部分263与数据线12在垂直于衬底基板101的方向上存在交叠。
图5示出了该相邻的四个子像素的第一电极134a、134b、134c和134d，例如，该第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d构成该显示基板20的一个重复单元。
例如，在每个重复单元中，第二子像素100b的发光元件发出的光的颜色和第四子像素100d的发光元件发出的光的颜色相同，也就是说，第二子像素100b和第四子像素100d为相同颜色的子像素。 例如，第二子像素100b和第四子像素100d为敏感颜色子像素，当显示基板20采用红绿蓝(RGB)显示模式时，上述的敏感颜色为绿色，即第二子像素100b和第四子像素100d均为绿色子像素。例如，第一子像素100a可以为红色子像素，第三子像素100c可以为蓝色子像素。
例如，在每个重复单元中，第一子像素100a和第三子像素100c在行方向交替排列，第二子像素100b和第四子像素100d分别位于相邻行中第一子像素100a和第三子像素100c之间，以及第三子像素100c和下一个重复单元中的第一子像素100a之间。
例如，在每个重复单元中，第一子像素100a和第三子像素100c在列方向交替排列。相邻两行的重复单元中，位于两行两列的两个第一子像素100a和两个第三子像素100c构成一个2*2的矩阵，该矩阵中，两个第一子像素100a位于该矩阵的一个对角位置，两个第三子像素100c位于该矩阵的另一个对角位置，且该两个第一子像素100a和两个第三子像素100c包围一个第二子像素100b或第四子像素100d。该2*2矩阵在行方向和列方向上以共用一列或一行子像素的方式重复。
例如，每个重复单元中的四个子像素可以形成两个虚拟像素，重复单元中的第一子像素100a和第三子像素100c分别被所述两个虚拟像素共用。例如，如图5所示，第一子像素100a与位于其右侧并与其相邻的第二子像素100b构成一个虚拟像素，并借用相邻(右侧)虚拟像素中的第三子像素100c形成发光像素单元；第三子像素100c和位于其右侧并与其相邻的第四子像素100d构成一个虚拟像素，并借用相邻(右侧未示出)的第一子像素100a形成发光像素单元。多个重复单元中的子像素形成像素阵列，在像素阵列的行方向上，子像素密度是虚拟像素密度的1.5倍，在像素阵列的列方向上，子像素密度是虚拟像素密度的1.5倍。
例如，第二子像素100b和第四子像素100d分别属于两个虚拟像素。
需要说明的是，第一，由于第一子像素100a和第三子像素100c 是被相邻的两个虚拟像素共享，因而每个虚拟像素的边界也是非常模糊的，因而，本公开实施例并不对每个虚拟像素的形状进行限定。第二、虚拟像素的划分与驱动方式相关，虚拟像素的具体划分方式可以根据实际的驱动方式确定，本公开对此不作具体限制。
例如，子像素100对应的多个开口区的形状和大小可以根据发出不同颜色的光的发光材料的发光效率、使用寿命等而改变，例如，可以将发光寿命较短的发光材料的对应的开口区设置得较大，从而提高发光的稳定性。例如，可以将蓝色子像素、红色子像素、绿色子像素的开口区的大小依次减小。由于开口区设置于第一电极134上，相应地，如图5所示，第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d的第一电极134a、121b、121c和121d的面积依次减小。
对于每一行子像素，所述子像素的发光元件的第一电极的主体部沿第二方向布置，并沿在第一方向上交错设置。在所述第二方向上任意相邻的两个子像素中一个的第一电极的主体部和第一电容电极在垂直于所述衬底基板的方向上重叠，所述两个子像素中的另一个的第一电极的主体部和第一电容电极在垂直于所述衬底基板的方向上不重叠。例如，如图5所示每相邻红色子像素(第一子像素100a)的第一电极134a和蓝色子像素(第三子像素100c)的第一电极134c之间设置一个面积最小的绿色子像素的第一电极134b/134d，且该第一电极134b/134d的主体部与该第一电极134a、134c的主体部沿第二方向交错设置。例如，该第一电极134a、134c的主体部分别与各所属子像素中的第一电容电极Ca在垂直于衬底基板的方向上重叠，该第一电极134b/134d的主体部分别与各所属子像素所中的第一电容电极Ca在垂直于衬底基板的方向上不重叠。这样可以提高版图空间利用率，从而提高像素密度。如图5所示，各第一电极的主体部141成Z字形沿第二方向D2延伸。
例如，对于重复单元行，第一子像素100a和第三子像素100c的的第一电极134的主体部例如为四边形，且其以顶角相对的方式在行和列方向排列，第三电源线260沿着第一子像素100a和第三子 像素100c的第一电极134的远离第二子像素100b和第四子像素100d的一侧的轮廓延伸。例如第二子像素100b和第四子像素100d在行方向即D2方向上，位于第一子像素100a和第三子像素100c构成的子像素行的对应相邻的两个子像素之间的位置，且第二子像素100b和第四子像素100d的第一电极的134的主体部例如为四边形，各个相邻的子像素的第一电极134的主体部具有相对且平行的边，第三电源线260沿着第一子像素100a和第三子像素100c的第一电极134的远离第二子像素100b和第四子像素100d的一侧的轮廓延伸，同时也沿着第二子像素100b和第四子像素100d的第一电极134的远离第一子像素100a和第三子像素100c的一侧的轮廓延伸。例如，第三电源线260沿着第一子像素100a和第三子像素100c构成的子像素行的第一电极134，与第二子像素100b和第四子像素100d构成的子像素行的第一电极134之间的间隙延伸，形成波浪状，且在对应第一子像素100a和第三子像素100c的第一电极134的主体部的电极顶角位置处形成为波峰，在对应第二子像素100b和第四子像素100d的第一电极134的主体部的电极顶角位置处形成为波谷。其中，靠近上一行的方向为波峰的凸出方向，靠近下一行的方向为波谷的凸出方向。例如，如图5和图6所示，各子像素的第一电极134的连接部142通过过孔308与第四连接电极234电连接，从而使得第五晶体管T5的第二极T5d与发光元件120的第一电极134电连接。例如，该第一电极134的连接部142与该第四连接电极234在垂直于衬底基板101的方向至少部分重叠。
例如，该开口区600与该第一电极134的连接部142在垂直于衬底基板101上的方向上不重叠，且过孔307和过孔308与该第一电极134的连接部142在垂直于衬底基板101上的方向均有交叠，从而避免该过孔308和过孔307影响开口区内的发光层的平整度从而影响发光品质。在一些实施例中，过孔307可以与开口区有部分交叠，因为过孔307所在的层与第一电极134所在的层中间至少间隔第四连接电极234所在的层，以及过孔308所在的绝缘层，所以过孔307对开口区的平坦性影响较过孔308对开口区的平坦性影响 小。
例如，对于第一子像素100a和第三子像素100c，其对应的第四连接电极位于其第一电极134远离该像素电路中复位控制线220的一侧，对应的，第一电极134的连接电极也位于第一电极134远离该像素电路中复位控制线220的一侧，第一电极134的连接电极与对应的第四连接电极至少部分交叠。
例如，对于第二子像素100b和第四子像素100d，其对应的第四连接电极位于其第一电极134靠近该像素电路中复位控制线220的一侧，对应的，第一电极134的连接电极也位于第一电极134远离该像素电路中复位控制线220的一侧，第一电极134的连接电极与对应的第四连接电极至少部分交叠。
例如，如图6所示，显示基板20还包括位于发光元件的第一电极上的像素界定层108。像素界定层108中形成开口从而界定显示基板的开口区600。发光层136至少形成于该开口内(发光层136还可以覆盖部分的像素界定层)，第二电极135形成于发光层136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如第一电极为发光元件的阳极，第二电极为发光元件的阴极。
例如，结合图5和图6所示，如图5所示，对于每个像素电路，过孔307和过孔308在衬底基板101的正投影均位于第三连接电极234在衬底基板的正投影内。例如，过孔307和过孔308在D1方向并列排布，且其沿第一方向D1的中心线大致重合。在平行于衬底基板101板面的方向上，过孔308相较于过孔307更加远离第一电极134的主体部141，使得相对于该子像素的开口区600(例如第一电极134的面积大于对应的开口区600的面积，开口区600大致位于第一电极134的中部区域)，该过孔308在衬底基板101上的正投影相较于过孔307在衬底基板101上的正投影更加远离该开口区600在衬底基板上的正投影。这是由于在垂直于衬底基板101的方向上，过孔308位于的绝缘层(例如为第二平坦层)，相对于过孔307位于的绝缘层(例如为第一平坦层)更靠近第一电极134的主 体部142，因此该过孔308对于第一电极134的平整度的影响较大，将该过孔308设置得离开口区或者第一电极134的主体部更远(在平行于衬底基板的表面上)可以降低过孔对于开口区内的发光层136的平整度的影响，提高发光元件的性能。
例如，在一行重复单元中，第一子像素100a和第三子像素100c的像素电路中的过孔307和过孔308均位于其对应的第一电极134远离该像素电路中复位控制线220的一侧，第二子像素100b和第四子像素100d，其对应的第四连接电极位于其第一电极134靠近该像素电路中复位控制线220的一侧，即在一行重复单元中，各子像素的像素电路中过孔307和308均位于第一子像素100a和第三子像素100c组成的行，以及第二子像素100b和第四子像素100d组成的行之间的位置。
例如，在一个重复单元中，第一子像素100a、第三子像素100c、第二子像素100b和第四子像素100d的像素电路中第四连接电极的形状大致相同，且大致排布在同一条平行D2方向的直线上。例如，位于第四连接电极正投影内的过孔307和过孔308大致不重叠或者不完全重叠，避免在垂直基板方向上，过孔堆叠导致过孔所在位置容易产生连接不良、断线或不平坦。例如，第一子像素100a和第三子像素100c的过孔307，与第二子像素100b和第四子像素100d的过孔308大致位于同一条直线上，第一子像素100a和第三子像素100c的过孔308，与第二子像素100b和第四子像素100d的过孔307大致位于同一条直线上。
例如，如图6所示，该开口区600与过孔308在衬底基板101上的正投影不重叠。例如，该开口区600与第四连接电极234在衬底基板101上的正投影不重叠。这样有助于提高发光层136的平整度从而提高发光效率。
如图1A所示，由于第一电源线270引起的高度差导致开口在衬底基板上的正投影被第一电源线分隔的两部分中至少一部分发生翘曲而引起色偏，本公开通过调整第一电源线270的线宽来使得针对不同颜色子像素的开口，开口正投影的第一部分之间的面积比与开口 正投影的第二部分之间的面积比之间的比值在一定范围内，例如0.8-1.2范围内。
调整位于开口正投影区中的第一电源线270的宽度，例如可以将第一重复部分的线宽在3μm-4.6μm之间调整，将第二重复部分的线宽在4.5μm-6.9μm之间调整，将第三重复部分的线宽在3μm-4.6μm之间调整，将第四重复部分的线宽在5.3μm-8.1μm之间调整，将第五重复部分的线宽在2.4μm-3.6μm之间调整，以使得开口正投影的第一部分之间的面积比与开口正投影的第二部分之间的面积比之间的比值在上述0.8-1.2范围内。在一个具体示例中，第一重复部分的线宽可以为3.8μm，第二重复部分的线宽可以为5.7μm，第三重复部分的线宽可以为3.8μm，第四重复部分的线宽可以为6.7μm，第五重复部分的线宽可以为3.0μm。
例如，参考图1A和图5A，将R和B子像素对应开口正投影中第一电源线270的宽度从4.3从线调整为3.8从线，将G’和G”子像素对应开口正投影中第一电源线270的宽度从4.4从线和4.7μ.均调整为3.0为线，从而使得针对不同颜色子像素的开口，开口正投影的第一部分之间的面积比与开口正投影的第二部分之间的面积比的比值在上述范围内。
在一个具体示例中，开口正投影的第一部分之间的面积比与开口正投影的第二部分之间的面积比的比值为1。例如，红色子像素的开口正投影的第一部分、与第一绿色子像素G’的开口正投影的第一部分和第二绿色子像素G”的开口正投影的第一部分的和(即绿色子像素)之间的比值R1/(G’1+G”1)＝1∶1.04，红色子像素的开口正投影的第二部分、与第一绿色子像素G’的开口正投影的第二部分和第二绿色子像素G”的开口正投影的第一部分的和之间的比值R2/(G’2+G”2)＝1∶1.04。红色子像素的开口正投影的第一部分、以及蓝色子像素的开口的第一部分之间的面积比R1/B1＝1∶1.644，红色子像素的开口正投影的第二部分、以及蓝色子像素的开口的第二部分之间的面积比R2/B2＝1∶1.644。蓝色子像素的开口的第一部分、第一绿色子像素G’的开口正投影的第一部分和第二绿色子像素G”的开口 正投影的第一部分的和之间的面积比B1/(G’1+G”1)＝1.04∶1.644，蓝色子像素的开口的第二部分、第一绿色子像素G’的开口正投影的第二部分和第二绿色子像素G”的开口正投影的第二部分的和之间的面积比B2/(G’2+G”2)＝1.04∶1.644。
也就是说，红色子像素的开口正投影的第一部分、第一绿色子像素G’的开口正投影的第一部分和第二绿色子像素G”的开口正投影的第一部分的和、以及蓝色子像素的开口正投影的第一部分之间的面积比R1∶(G’1+G”1)∶B1，红色子像素的开口正投影的第二部分、第一绿色子像素G’的开口正投影的第二部分和第二绿色子像素G”的开口正投影的第二部分的和、以及蓝色子像素的开口正投影的第二部分之间的面积比R2∶(G’2+G”2)∶B2，均为1∶1.04∶1.644。采用上述开口设置，可以使得三种颜色子像素的透射光混合产生白光。
这样可以使得在包括多个子像素的一个像素单元中，以及整个显示基板中，由于针对不同颜色子像素的开口，开口正投影的第一部分对应的不同颜色子像素之间的透光比例等于开口正投影的第二部分对应的不同颜色子像素之间的透光比例，即使发生翘曲，依然能够发白光，从而改善色偏。
如图4C所示，第二电源线250呈条状，并沿第一方向D1延伸。由图4D所示，第二电源线250在衬底基板上的正投影与第一电源线260在衬底基板上的正投影至少部分重叠，并且与多个开口在衬底基板的正投影所在区域对应位置处，由于调整第一电源线的宽度，第一电源线的宽度与第二电源线的宽度可以不等。
如图5所示，针对一个像素包括红色子像素、蓝色子像素、第一绿色子像素和第二绿色子像素的情况，与红色子像素、蓝色子像素、第一绿色子像素和第二绿色子像素分别一一对应的开口(181a、181c、181和181d)在衬底基板上的正投影均被第一电源线衬底基板上的正投影分割为两部分，例如第一侧(左侧)的第一部分和第二侧(右侧)的第二部分。红色子像素的开口的第一部分、蓝色子像素的开口的第一部分、以及第一绿色子像素的开口的第一部分和第二绿色子像素的开口的第一部分的和之间的面积比与红色子像素的开口 的第二部分、蓝色子像素的开口的第二部分、以及所述第一绿色子像素的开口的第二部分和第二绿色子像素的开口的第二部分的和之间的面积比相等，例如为1∶1.04∶1.644。
例如，衬底基板101可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层102的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该第一到第四导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该发光元件120为顶发射结构，第一电极具134有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，第四绝缘层106、第五绝缘层107和像素界定层108分别为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层106和第五绝缘层107为平坦化层。
如图2所示，第一子像素100a的像素电路与第一数据线12a 电连接以接收数据信号Vd，第二子像素100b的像素电路与第二数据线12b电连接以接收数据信号Vd。例如，第二数据线12b位于第一子像素100a的像素电路与第二子像素100b的像素电路之间。
如图2所示，第一子像素100a中的第一电容电极Caa与第二子像素100b中的第一电容电极Cab彼此间隔设置，也即该第一子像素100a和第二子像素100b中的第一电容电极Ca在其所在导电层内彼此断开。这种设置可以减少相邻的第一电容电极Ca彼此连接而与其它信号线之间产生的交叠，从而降低了寄生电容。
例如，各子像素100中的第一电容电极Ca面积和形状大致相同。
例如，各子像素100中的第一电容电极Ca在该子像素中的相对位置相同。例如，每行子像素100中的第一电容电极Ca沿第二方向D2直线排布。
例如，各子像素100中的第一电容电极Ca在其所在导电层为岛状结构，也即不与其所在导电层的其它结构电连接。
例如，如图7所示，相邻的第一电容电极Ca之间存在第一子像素100a的像素电路的中第三晶体管T3的第二极T3d、第一晶体管T1的第二极T1d、第五晶体管T5的第一极T1s彼此连接的汇合处，将该第一子像素100a中的第一电容电极Caa和第二子像素100b中的第一电容电极Cab彼此断开可以避免该第二子像素100b中的第一电容电极Cab与该汇合处发生重叠而产生寄生电容，对该汇合处的信号造成不良影响。例如，该第一子像素100a中的第三晶体管T3的第二极T3d、第一晶体管T1的第二极T1d、第五晶体管T5的第一极T1s在垂直于衬底基板上的正投影与该第二子像素100b中的第一电容电极Cab在垂直于衬底基板101的方向均上不重叠。
例如，子像素100中的第一电容电极Ca的范围不超出该子像素的像素区(像素电路所在的区域)，也即该子像素100的第一电容电极Cab不延伸至与相邻的子像素的像素区内与该子像素中的结构发生重叠而引起串扰。
例如，如图7所示，相邻的第一子像素100a和第二子像素100b的第一电容电极Ca之间还存在第二数据线12b，第一子像素100a 的第一电容电极Caa和第二子像素100b的第一电容电极Cab与第二数据线12b在衬底基板上的正投影没有交叠。将该第一子像素100a中的第一电容电极Caa和第二子像素100b中的第一电容电极Cab彼此断开可以避免该第一电容电极与该第二数据线12b发生重叠产生寄生电容，对该数据线上的数据信号的传输造成不良影响，例如造成该数据信号的延迟等。另一方面，由于数据信号Vd通常为高频信号，而第一电容电极Ca传输的是第一电源电压VDD，由于寄生电容的存在，该第一电源电压容易随数据信号Vd的突变而跟着突变，而该第一电容电极Ca与数据线之间的阻容负载太大，导致该第一电源电压发生突变后不能短时间恢复。根据发光阶段第一晶体管T1中的饱和电流的公式Id＝k/2*(Vd-VDD)2可以知道，该第一电源电压VDD的波动造成驱动电流的波动，从而导致发光亮度不稳定。因此，将该第一子像素100a中的第一电容电极Caa和第二子像素100b中的第一电容电极Cab彼此断开还有助于提高发光元件发光的稳定性。如图7所示，例如，与第二数据线12b相邻的第一子像素100a的漏极T1d在衬底基板上的正投影与第二数据线12b在衬底基板上的正投影之间的距离可以为1.75μm，例如，与第二数据线12b相邻的第一子像素100b的源极T1s在衬底基板上的正投影与第二数据线12b在衬底基板上的正投影之间的距离可以为2.8μm。第二数据线12b与其相邻的子像素的源极或漏极之间的距离也可以为避免交叠的其他值。
本公开的发明人发现，由于信号线之间的交叠，导致数据线12与存储电容Cst的第二电容电极Cb之间产生寄生电容，影响该存储电容Cst的稳定性。由于该存储电容Cst配置为存储数据信号Vd以及驱动子电路的阈值电压的相关信息，并配置为在发光阶段将该存储的信息用于对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿，因此存储电容Cst两端的电压(存储的信息)的稳定性将影响显示灰阶的稳定性，从而影响显示画面的质量。
本公开另一些实施例还提供一种显示基板，如图2和图8A所示，至少一个子像素中的第一电容电极Ca包括延伸部290，该延伸部290与该子像素连接的数据线12在垂直于衬底基板101的方向上彼此重 叠以提供第一电容C1。
由于该第一电容C1的存在，数据线12中的数据信号的波动在通过寄生电容耦合到该存储电容Cst的第二电容电极Cb的同时，还通过该第一电容C1耦合到该存储电容Cst的第一电容电极Ca。这样提高了该存储电容Cst中存储信息的稳定性，改善了显示性能。
图8A示出了图2沿剖面线B-B’的剖视图，图8B示出了该像素电路的等效电路图。结合参考图2和图8A-图8B，数据线12与扫描线210在垂直于衬底基板101的方向上交叠形成第二电容C2，第一连接电极231与扫描线210在垂直于衬底基板101的方向上交叠形成第三电容C3。
由于该第一连接电极231与存储电容Cst的第二电容电极Cb电连接，因此该第二电容C2与第三电容C3串联在数据线12与存储电容Cst的第二电容电极Cb之间，数据线12中的数据信号的波动将通过该第二电容C2与第三电容C3耦合到该存储电容Cst的第二电容电极Cb。由于该第一电容C1的存在，数据线12中的数据信号的波动同时还通过该第一电容C1耦合到该存储电容Cst的第一电容电极Ca。这样提高了该存储电容Cst中存储信息的稳定性，改善了显示性能。
例如，该第一电容C1的电容值接近于等于该第二电容C2与第三电容C3串联的电容值，例如二者相等，也即C1＝(C2*C3)/(C2+C3)。
例如，该延伸部290从该第一电容电极Ca的主体部向该与之重叠的数据线12的方向延伸(突出)。例如，该第一电容电极Ca的形状为朝向其所在的像素电路中的数据线方向倒着的的凸字型，即第一电容电极Ca为一个大致矩形的电极块，且在靠近该像素电路中的数据线的侧边上有一个向数据线方向突出的凸起，且位于该边上的大致中部，且在该第一电容电极Ca内部存在一个过孔。
例如，在这种情形，该第一电容电极Ca仍然不超出该子像素所在的像素区，也即该像素电路的第一电容电极Cab不延伸至与相邻的子像素的像素区内与该子像素中的结构发生重叠而引起串扰。
图9示出了该第一电容电极Ca的示意图。如图9所示，例如， 该延伸部290的面积与该第一电容电极Ca的面积比例范围为1/10-1/3，例如为1/5。
例如，在第一方向D1上，延伸部290的最大尺寸D2与第一电容电极的最大尺寸D1的比例范围为1/4-1/2，例如为1/3。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板20。需要说明的是，本公开至少一实施例提供的上述显示基板20可以包括发光元件120，也可以不包括发光元件120，也即该发光元件120可以在显示基板20完成后在面板厂形成。在该显示基板20本身不包括发光元件120的情形下，本公开实施例提供的显示面板除了包括显示基板20之外，还进一步包括发光元件120。
例如，该显示面板为OLED显示面板，相应地其包括的显示基板20为OLED显示基板。如图10所示，例如，该显示面板30还包括设置于显示基板20上的封装层801和盖板802，该封装层801配置为对显示基板20上的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动子电路的渗透而造成对器件的损坏。例如，封装层801包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层801与显示基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板802例如为玻璃盖板。例如，盖板802和封装层801可以为一体的结构。
本公开的至少一实施例还提供一种显示装置40，如图11所示，该显示装置40包括上述任一显示基板20或显示面板30，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供上述显示基板20的制作方法。以下将结合图2、图4A-图4E和图5-图6对本公开实施例提供的显示基板的结构和制作方法进行实例性说明，然而本公开实施例并不限于此。
在一些示例中，该制作方法包括如图12所示的如下步骤S61-S70。
步骤S61：在衬底基板上形成半导体材料层，并对该半导体材料层进行构图工艺从而形成如图4A所示的半导体层102，半导体层102包括在每个像素区内第一到第七晶体管T1-T7的有源层T1a-T7a和掺杂区图案(即对应第一到第七晶体管T1-T7的源极区域和漏极区域)，且同一像素区中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素区中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
步骤S62：在半导体层102层上形成第一绝缘层103(例如可以为透明层)，例如为栅绝缘层，并在第一绝缘层上形成多个第一绝缘层过孔用于与后续形成的第三导电层203的图案连接。例如对应半导体层中的源极区域和漏极区域的位置，分别在第一绝缘层中形成对应的第一绝缘层过孔，即第一绝缘层过孔分别与半导体层中的源极区域和漏极区域交叠，以用于源极区域和漏极区域与第三导电层中的数据线12、第二电源线250、第一连接电极231、第二连接电极232和第三连接电极233等结构进行连接，例如贯穿第一绝缘层的过孔402，过孔405，过孔303，过孔305等。
步骤S63：在第一绝缘层上形成第一导电材料层，并对该第一导电材料层进行构图工艺从而形成如图3A所示的第一导电层201，也即形成彼此绝缘且沿第二方向延伸的扫描线210、复位控制线220和发光控制线230。例如，对于一行像素电路，其对应连接的复位控制线220、扫描线210和发光控制线230在第一方向D1上依次排布。
例如，该第一导电层201还包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第六晶体管T6的栅极T6g和复位控制线220为一体的结构，即复位控制线220的一部分作为第六晶体管T6的栅极T6g；第二晶体管T2的栅极T2g和扫描线210为一体的结构，即扫 描线210的部分作为第二晶体管T2的栅极T2g；第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g均与发光控制线230为一体的结构，即发光控制线230的一部分作为第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g；第七晶体管T7的栅极T7g与下一行像素电路所对应的复位控制线220为一体的结构。例如，第六晶体管T6和第三晶体管T3均为双栅结构，第六晶体管T6的两个栅极T6g均为复位控制线220的一部分，第三晶体管T3的一个栅极为扫描线210的一部分，第三晶体管T3的另一个栅极为在扫描线210一体连接并朝向复位控制线220上突出的一部分。
例如，该半导体层102与该第一导电层201在垂直于衬底基板的方向上重叠的部分定义出该第一到第七晶体管T1-T7的有源层(沟道区)T1a-T7a。
例如，在D1方向上，第二晶体管(例如为数据写入晶体管)T2的栅极、第三晶体管(例如为阈值补偿晶体管)T3的栅极、第六晶体管(例如为第一复位晶体管)T6的栅极和第七晶体管(例如为第二复位晶体管)T7的栅极均位于第一晶体管(例如为驱动晶体管)T1的栅极的第一侧，第四晶体管(例如为第一发光控制晶体管)T4的栅极、第五晶体管(例如为第二发光控制晶体管)T5的栅极均位于第一晶体管T1的栅极的第二侧。在平行于衬底基板的平面内，同一个像素区的第一晶体管T1的栅极的第一侧可以为第一晶体管T1的栅极T1g靠近扫描线230的一侧，第一晶体管T1的栅极的第二侧可以为第一晶体管T1的栅极远离扫描线230的一侧。
例如，在第二方向D2上，第二晶体管T2的栅极和第四晶体管T4的栅极均位于第一晶体管T1的栅极的第三侧，第三晶体管T3的第一个栅极(与扫描线210为一体的栅极)、第五晶体管T5的栅极和第七晶体管T7的栅极均位于第一晶体管T1的栅极的第四侧。例如同一像素区的第一晶体管T1的栅极的第三侧和第四侧为在D2方向上第一晶体管T1的栅极的彼此相对的两侧。例如，同一像素区的第一晶体管T1的栅极的第三侧可以为第一晶体管T1的栅极的左侧，第一晶体管T1的栅极的第四侧可以为第一晶体管T1的栅极的右侧。 所述左侧和右侧，例如在同一像素区中，数据线12在第二电源线250左侧，第二电源线250在数据线右侧。
步骤S64：如图4A所示，采用自对准工艺，利用该第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，从而使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而使得该半导体层102位于各晶体管的有源层两侧的部分被导体化而分别形成第一到第七晶体管T1-T7的源极区域和漏极区域，也即第一到第七晶体管T1-T7的第一极(T1s-T7s)和第二极(T1d-T7d)。
步骤S65：在第一导电层201上形成第二绝缘层104(例如可以为透明层)，例如可以为第二栅绝缘层。并在第二绝缘层上至少形成与第一绝缘层过孔对应的第二绝缘层过孔。例如对应至少贯穿第一绝缘层和第二绝缘层的过孔至少包括过孔402，过孔405，过孔303，过孔305等。
步骤S66：在该第二绝缘层104并在该第二绝缘层上形成第二导电材料层，对该第二导电材料层进行构图工艺形成如图4B所示的第二导电层202，也即形成彼此绝缘的屏蔽电极221、第一电容电极Ca以及沿第一方向延伸的复位电压线240。
例如，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。
例如，该第一电容电极Ca与该第一晶体管T1的栅极T1g在垂直于衬底基板101的方向上至少部分重叠。该构图工艺还在该第一电容电极Ca中形成过孔301，该过孔301暴露出第一晶体管T1的栅极T1g的至少部分。
步骤S67：在该第二导电层202上形成第三绝缘层105。第三绝缘层例如可以为层间绝缘层。在第三绝缘层中形成用于连接与后续形成的第三导电层的连接的过孔。至少部分过孔与第一绝缘层过孔和第二绝缘层过孔位置对应，且同时贯穿第一绝缘层、第二绝缘层和第三绝缘层，例如过孔402，过孔405，过孔303，过孔305。
步骤S68：在该第三绝缘层105上形成第三导电材料层，对该第三导电材料层进行构图工艺形成如图4C所示的第三导电层203，也即形成彼此绝缘的数据线12、第二电源线250、第一连接电极231、第二连接电极232和第三连接电极233。该数据线12和该第二电源线250沿第一方向D1延伸。
例如，如图4C所示，该数据线12与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠并通过过孔305与该第二晶体管T2的第一极T2s电连接，该过孔305例如贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图6所示，该第二电源线250与该屏蔽电极221在垂直于衬底基板101的方向上重叠并通过过孔304与该屏蔽电极221电连接，例如该过孔304贯穿第三绝缘层105。
例如，如图4C所示，该第二电源线250通过过孔302与所对应的一列子像素中的第一电容电极Ca电连接，并通过过孔303与第四晶体管T4的第一极T4s电连接。例如，该过孔302贯穿第三绝缘层105，该过孔303贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图6所示，该第一连接电极231的一端通过第一电容电极Ca中的过孔301以及绝缘层中的过孔401与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔402与该第三晶体管T3的第一极电连接，从而将该第二电容电极Cb与该第三晶体管T3的第一极T3s电连接。例如，该过孔401贯穿第二绝缘层104和第三绝缘层105，该过孔402贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图4C所示，该第二连接电极232的一端通过过孔403与复位电压线电连接，另一端通过过孔404与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔403贯穿第三绝缘层105，该过孔404贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图6所示，该第三连接电极233通过过孔405 与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，例如，该过孔405贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
步骤S69：在第三导电层203上形成第四绝缘层106。并在第三绝缘层中形成用于与后续形成的第四导电层连接的过孔。在一些实施例中，例如第四绝缘层106包括第一平坦层。在另一些实施例中，例如第四绝缘层106包括钝化层和第一平坦层两层，则形成在第四绝缘层中的过孔需要贯穿钝化层和第一平坦层两层。例如，第一平坦层位于钝化层远离第三导电层的一侧。
步骤S70：在该第四绝缘层106上形成第四导电材料层，对该第四导电材料层进行构图工艺形成如图4D所示的第四导电层204，也即形成第三电源线260、第一电源线270以及第四连接电极234，该第三电源线260和该第一电源线270彼此连接，并与第四连接电极234绝缘。
例如，如图4D所示，多条第一电源线270沿第一方向D1延伸，并分别与多条第二电源线250通过过孔306一一对应电连接。例如，每条第一电源线270与对应的第二电源线250在垂直于衬底基板101的方向上彼此重叠。例如，该过孔306贯穿第四绝缘层106。
例如，如图4D所示，该第四连接电极234与第三连接电极233在垂直于衬底基板101的方向上重叠，并且该第三连接电极234通过贯穿第四绝缘层106的过孔307与第三连接电极233电连接。
例如，参考图5和图6，该显示基板的制作方法还可以包括在该第四导电层204上形成第五绝缘层107，并在第五绝缘层107中形成用于与后续形成的第五导电层进行连接的过孔。例如第五绝缘层107可以为第二平坦层。第五绝缘层过孔例如用于连接第一晶体管漏极和发光器件的第一电极，第五绝缘层过孔与第一晶体管的第二极可以有交叠，也可以没有交叠，没有交叠的情况，可以额外在第三导电层中设置连接线连接，具体情况与子像素排列结构例如第一电极的位置和形状有关。
例如，该显示基板的制作方法还可以包括在该第五绝缘层107 上形成第五导电材料层，对该第五导电材料层进行构图工艺形成第五导电层205，即形成彼此绝缘的多个用于形成发光元件的第一电极134。
例如，每个第一电极134包括主体部141和连接部142，主体部141主要用于驱动发光层发光，连接部142主要用于与像素电路进行电连接。
例如，如图6所示，该连接部142通过第五绝缘层107中的过孔308与第四连接电极234电连接，例如，在平行于衬底基板101板面的方向上，过孔308相较于过孔307更加远离第一电极134的主体部141，也即该子像素的开口区600，也即该过孔308在衬底基板101上的正投影相较于过孔307在衬底基板101上的正投影更加远离该开口区600在衬底基板上的正投影。
例如，如图6所示，该显示基板的制作方法还可以包括依次在该第五导电层205上形成像素界定层108，并在该像素界定层108中对应于每个第一电极134的主体部141形成开口区600，然后至少在该开口区600中形成发光层136，并在该发光层上形成第二电极135。
在形成开口区600之前，通过调整与多个开口在衬底基板的正投影所在区域对应位置处的第一电源线的宽度来实现针对不同颜色子像素的开口，被第一电源线270分隔的开口正投影两部分中的第一部分之间的面积比与第二部分之间的面积比的比值在一定范围内。
可选地，在调整与多个开口在衬底基板的正投影所在区域对应位置处的第一电源线的宽度的同时，调整相应第一电源线在与多个开口在衬底基板的正投影所在区域对应位置之外的宽度以保持电源线负载均衡。同时，还可以调整第一电源线、第二电源线和第三电源线和第一的走向，以使得各电源线与半导体层的重叠面积尽可能大，以增大开口率。
在形成一个像素包括形成红色子像素、蓝色子像素、第一绿色子像素和第二绿色子像素四个子像素，其中红色子像素和蓝色子像素共享的情况下，形成与红色子像素、蓝色子像素、第一绿色子像素和 第二绿色子像素分别一一对应的开口均被第一电源线在衬底基板上的正投影分隔为两部分包括：针对红色子像素的开口、蓝色子像素的开口、第一绿色子像素的开口和第二绿色子像素的开口，使得红色子像素的开口正投影的第一部分、蓝色子像素的开口的第一部分、和第一绿色子像素的开口正投影的第一部分和所述第二绿色子像素的开口正投影的第一部分的和之间的面积比与所述红色子像素的开口正投影的第二部分、蓝色子像素的开口正投影的第二部分、以及第一绿色子像素的开口正投影的第二部分和第二绿色子像素的开口正投影的第二部分的和之间的面积比相等，例如为1∶1.04∶1.644。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，上述第一导电材料层、第二导电材料层、第三导电材料层、第四导电材料层、第五导电材料层及第二电极的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者透明金属氧化物导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105、第四绝缘层106、第五绝缘层107例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，这些绝缘层部分层也可以是有机材料，例如第一平坦层和第二平坦层，例如聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等，本公开实施例对此不作限制。例如，第四绝缘层106和第五绝缘层107可以分别包括平坦层。
例如，上述构图工艺可以采用常规的光刻工艺，例如包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板；以及
    多个子像素，其位于所述衬底基板上，
    所述多个子像素包括：
    第一金属层，其位于所述衬底基板上，所述第一金属层包括多条第一电源线；
    第一平坦层，其位于所述第一金属层远离所述衬底基板的一侧；
    第一电极层，其位于所述第一平坦层远离所述第一金属层的一侧，并具有彼此间隔开的多个第一电极；以及
    像素界定层，其位于所述第一电极层远离所述第一平坦层的一侧，并具有与所述多个第一电极一一对应并暴露出所述多个第一电极的多个开口，所述多个开口对应至少两种不同颜色的子像素，
    其中，所述多条第一电源线中的一条在所述衬底基板上的正投影将所述多个开口中的一个在所述衬底基板上的正投影分隔为位于该条第一电源线的第一侧的第一部分和位于该条第一电源线的第二侧的第二部分，针对至少两种不同颜色的子像素，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比之间的比值在0.8-1.2范围内。
  2. 根据权利要求1所述的显示基板，其中，所述至少两种不同颜色的子像素包括第一颜色的第一子像素，
    所述第一电源线沿第一方向延伸，所述第一部分和所述第二部分沿第二方向排列，所述第一方向和所述第二方向相交，
    所述多条第一电源线包括彼此平行设置的第一子电源线，所述第一子电源线在所述衬底基板上的正投影将所述第一子像素对应的开口正投影分隔为第一部分和第二部分，
    所述第一子电源线包括依次连接的作为重复单元的第一重复部分和第二重复部分，所述第一子像素在所述衬底基板上的正投影分别 与相应第一子电源线的第一重复部分和第二重复部分在所述衬底基板上的正投影交叠，并且所述第一子像素在所述衬底基板上的正投影与所述第一重复部分在所述衬底基板上的正投影的重叠面积大于所述第一子像素在所述衬底基板上的正投影与所述第二重复部分在所述衬底基板上的正投影的重叠面积。
  3. 根据权利要求2所述的显示基板，其中，所述第一颜色的第一子像素包括红色子像素(R)和/或蓝色子像素(B)，所述第一重复部分的中轴线相对于所述第二重复部分的中轴线远离所述红色子像素(R)和/或所述蓝色子像素(B)的对应开口正投影的第二部分(R2，B2)并且所述第一重复部分在靠近所述红色子像素(R)和/或所述蓝色子像素(B)对应开口正投影的第二部分(R2，B2)的一侧挖空。
  4. 根据权利要求2或3所述的显示基板，其中，
    所述至少两种不同颜色的子像素还包括与所述第一子像素的第一颜色不同的第二颜色的第二子像素，
    所述多条第一电源线还包括与所述第一子电源线彼此平行交替设置的第二子电源线，
    所述第二子电源线包括依次连接的作为重复单元的第三重复部分、第四重复部分和第五重复部分，
    所述第二子像素在所述衬底基板上的正投影分别与相应第二子电源线的第四重复部分和第五重复部分在所述衬底基板上的正投影交叠，并且所述第二子像素在所述衬底基板上的正投影与所述第五重复部分在所述衬底基板上的正投影的重叠面积大于所述第二子像素在所述衬底基板上的正投影与所述第四重复部分在所述衬底基板上的正投影的重叠面积。
  5. 根据权利要求4所述的显示基板，其中，
    所述至少两种不同颜色的子像素还包括与所述第二子像素的第二颜色相同的第三子像素，
    所述第三子像素在所述衬底基板上的正投影与相应第二子电源线的第五重复部分在所述衬底基板上的正投影交叠。
  6. 根据权利要求5所述的显示基板，其中，
    所述第二颜色的第二子像素和第三子像素包括绿色子像素，
    所述第三重复部分的中轴线、所述第四重复部分的中轴线和所述第五重复部分的中轴线依次靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)，并且所述第三重复部分在靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空，所述第五重复部分在远离所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空。
  7. 根据权利要求2-6中任一项所述的显示基板，其中，所述第一重复部分的线宽在3μm-4.6μm之间，所述第二重复部分的线宽在4.5μm-6.9μm之间，所述第三重复部分的线宽3μm-4.6μm之间，所述第四重复部分的线宽5.3μm-8.1μm之间，所述第五重复部分的线宽2.4μm-3.6μm之间。
  8. 根据权利要求7所述的显示基板，其中，所述第一重复部分的线宽为3.8μm，所述第二重复部分的线宽在5.7μm，所述第三重复部分的线宽3.8μm，所述第四重复部分的线宽6.7μm，所述第五重复部分的线宽3.0μm。
  9. 根据权利要求1-8中任一项所述的显示基板，还包括：
    第二金属层，其位于所述衬底基板上，包括多条第二电源线，所述多条第二电源线沿所述第一方向延伸，并且所述多条第一电源线在所述衬底基板上的正投影和所述多条第二电源线在所述衬底基板上的正投影在垂直于所述衬底基板的方向上分别至少部分交叠；
    第二平坦层，其位于所述第二金属层上，所述第一金属层位于所述第二平坦层上，并且所述多条第一电源线和所述多条第二电源线 通过贯穿所述第二平坦层的过孔连接。
  10. 根据权利要求9所述的显示基板，还包括多条第三电源线，其中，所述多条第三电源线沿所述第二方向延伸，并将所述多条第一电源线电连接，所述多条第三电源线在所述衬底基板上的正投影与每个子像素的开口在所述衬底基板上的正投影在垂直于衬底基板的方向上均不重叠，所述多条第三电源线与所述第一电源线同层设置且为一体的结构。
  11. 根据权利要求10所述的显示基板，其中，所述多条第三电源线中的每一条包括依次连接的作为重复单元的第三子电源线和第四子电源线，所述第三子电源线和所述第四子电源线沿所述第二方向交替延伸，并且所述多条第三电源线沿所述第一方向排列；
    所述第三子电源线包括依次连接的作为重复单元的第六重复部分、第七重复部分和第八重复部分，所述第七重复部分的延伸方向与所述第二方向平行，所述第六重复部分的延伸方向与所述第一方向和所述第二方向均相交，所述第八重复部分的延伸方向与所述第一方向和所述第二方向均相交且与所述第六重复部分的延伸方向不同；
    所述第四电源线包括第九重复部分和第十重复部分，所述第九重复部分的延伸方向与所述第二方向平行，所述第十重复部分的延伸方向与所述第一方向和所述第二方向均相交。
  12. 根据权利要求1所述的显示基板，其中，
    所述至少两种不同颜色的子像素包括红色子像素(R)、蓝色子像素(B)和绿色子像素(G)，
    所述红色子像素(R)和所述蓝色子像素(B)分别沿所述第一方向和所述第二方向交替排列，沿所述第一方向，所述第四子电源线位于所述红色子像素(R)的第二部分(R2)在所述衬底基板上的正投影和相邻的所述蓝色子像素(B)的第二部分(R2)在所述衬底基板上的正投影之间；
    所述绿色子像素(G)沿所述第一方向和所述第二方向排列，沿所述第一方向，所述第三子电源线位于相邻的所述绿色子像素(G)的第二部分(G2)在所述衬底基板上的正投影之间。
  13. 根据权利要求1或2所述的显示基板，其中，一个像素包括红色子像素(R)和蓝色子像素(B)，
    与所述红色子像素(R)和所述蓝色子像素(B)分别一一对应的开口正投影均被所述第一电源线在所述衬底基板上的正投影分隔为对应的第一部分和第二部分，
    所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述蓝色子像素(B)对应的开口正投影的第一部分(B1)的面积比为R1/B1，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)与所述蓝色子像素(B)对应的开口正投影的第二部分(B2)的面积比为R2/B2，其中，R1/B1＝R2/B2＝1∶1.644。
  14. 根据权利要求1或2所述的显示基板，其中，一个像素包括红色子像素(R)和绿色子像素(G)，
    所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述绿色子像素(G)对应的开口正投影的第一部分(G1)的面积比为R1/G1，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)与所述绿色子像素(G)对应的开口正投影的第二部分(G2)的面积比为R2/G2，其中，R1/G1＝R2/G2＝1∶1.04。
  15. 根据权利要求1或2所述的显示基板，其中，一个像素包括蓝色子像素(B)和绿色子像素(G)，
    所述蓝色子像素(B)对应的开口正投影的第一部分(B1)与所述绿色子像素(G)对应的开口正投影的第一部分(G1)的面积比为B1/G1，所述蓝色子像素(B)对应的开口正投影的第二部分(B2)与所述绿色子像素(G)对应的开口正投影的第二部分(G2)的面积比为B2/G2，其中，B1/G1＝B2/G2＝1.644∶1.04。
  16. 根据权利要求1或2所述的显示基板，其中，一个像素包括红色子像素(R)、第一绿色子像素(G’)和第二绿色子像素(G”)，
    所述红色子像素(R)对应的开口正投影的第一部分(R1)与所述第一绿色子像素(G’)对应的开口正投影的第一部分(G’1)和所述第二绿色子像素(G”)对应的开口正投影的第一部分(G”2)的和之间的面积比为R1/(G’1+G”1)，以及所述红色子像素(R)对应的开口正投影的第二部分(R2)、与所述第一绿色子像素(G’)对应的开口正投影的第二部分(G’2)和所述第二绿色子像素(G”)对应的开口正投影的第二部分(G”2)的和之间的面积比为R2/(G’2+G”2)，其中，R1/(G’1+G”1)＝R2/(G’2+G”2)＝1∶1.04。
  17. 根据权利要求1或2所述的显示基板，其中，一个像素包括蓝色子像素(B)、第一绿色子像素(G’)和第二绿色子像素(G”)，
    所述蓝色子像素(B)对应的开口正投影的第一部分(B1)、与所述第一绿色子像素(G’)对应的开口正投影的第一部分(G’1)和所述第二绿色子像素(G”)对应的开口正投影的第一部分(G”1)的和之间的面积比为B1/(G’1+G”1)，所述蓝色子像素(B)对应的开口正投影的第二部分(B2)、与所述第一绿色子像素(G’)对应的开口正投影的第二部分(G’2)和所述第二绿色子像素(G”)对应的开口正投影的第二部分(G”2)的和之间的面积比为B2/(G’2+G”2)，其中，B1/(G’1+G”1)＝B2/(G’2+G”2)＝1.644∶1.04。
  18. 根据权利要求1-17中任一项所述的显示基板，其中，所述多个子像素中的每一个包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路沿第一方向和第二方向分布为多行多列；
    所述像素电路包括驱动子电路、数据写入子电路、补偿子电路和存储子电路；
    所述驱动子电路包括控制端、第一端和第二端，且配置为与所 述发光元件耦接并且控制流经发光元件的驱动电流；
    所述数据写入子电路包括控制端、第一端和第二端，所述数据写入子电路的控制端配置为接收第一扫描信号，所述数据写入子电路的第一端配置为接收数据信号，所述数据写入子电路的第二端与所述驱动子电路电连接，所述数据写入子电路配置为响应于所述第一扫描信号将所述数据信号写入所述驱动子电路的第一端；
    所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；
    所述存储子电路与所述驱动子电路的控制端和第一电压端电连接，且被配置为存储所述数据信号；所述存储子电路包括存储电容，所述存储电容的第一电容电极和所述第一电压端耦接，第二电容电极和所述驱动子电路的控制端电耦接，所述第一电压端与所述多条第一电源线耦接；
    所述多个子像素包括在所述第二方向上直接相邻的第一子像素和第二子像素，所述第一子像素中的第一电容电极与所述第二子像素中的第一电容电极同层设置且彼此间隔。
  19. 根据权利要求18所述的显示基板，还包括多条数据线，所述多条数据线沿所述第一方向延伸，所述多条数据线被配置为向所述子像素提供数据信号。
  20. 根据权利要求19所述的显示基板，其中，所述多条第二电源线与所述多条数据线同层绝缘设置。
  21. 根据权利要求20所述的显示基板，其中，每个子像素还包括发光元件，所述发光元件包括依次层叠设置的所述第一电极、发光层和第二电极，所述第一电极位于所述发光层靠近所述衬底基板的一侧；
    所述第三电源线在所述衬底基板上的正投影与每个子像素的所述第一电极在所述衬底基板上的正投影在垂直于所述衬底基板的方向上不重叠。
  22. 一种显示装置，包括如权利要求1-21任一所述的显示基板。
  23. 一种用于制作显示基板的方法，包括：
    提供衬底基板；
    在所述衬底基板上形成多个子像素，
    其中，所述多个子像素中的每一个包括：
    第一金属层，其位于所述衬底基板上，所述第一金属层包括多条第一电源线；
    第一平坦层，其位于所述第一金属层远离所述衬底基板的一侧；
    第一电极层，其位于所述第一平坦层远离所述第一金属层的一侧，并具有彼此间隔开的多个第一电极；以及
    像素界定层，其位于所述第一电极层远离所述第一平坦层的一侧，并具有与所述多个第一电极一一对应并暴露出所述多个第一电极的多个开口，所述多个开口对应至少两种不同颜色的子像素，
    其中，所述多条第一电源线中的一条在所述衬底基板上的正投影将所述多个开口中的一个在所述衬底基板上的正投影分隔为位于该条第一电源线的第一侧的第一部分和位于该条第一电源线的第二侧的第二部分，针对至少两种不同颜色的子像素，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比之间的比值在0.8-1.2范围内。
  24. 根据权利要求23所述的方法，其中，通过调整与所述多个开口在所述衬底基板的正投影所在区域对应位置处的第一电源线的宽度来实现针对不同颜色子像素的开口，所述开口正投影的第一部分之间的面积比与所述开口正投影的第二部分之间的面积比的比值在0.8-1.2范围内。
  25. 根据权利要求24所述的方法，其中，在调整与所述多个开口在所述衬底基板的正投影所在区域对应位置处的第一电源线的宽度的同时，调整相应第一电源线在与所述多个开口在所述衬底基板的正投影所在区域对应位置之外的宽度。
  26. 根据权利要求23-25中任一项所述的方法，其中，所述第一电源线形成为沿第一方向延伸，所述第一部分和所述第二部分沿第二方向排列，所述第一方向和所述第二方向相交，所述至少两种不同颜色的子像素包括红色子像素(R)、蓝色子像素(B)和绿色子像素(G)，
    所述多条第一电源线包括彼此平行交替设置的第一子电源线和第二子电源线，所述第一子电源线在所述衬底基板上的正投影将红色子像素(R)和蓝色子像素(B)对应的开口正投影分隔为第一部分(R1，B1)和第二部分(R2，B2)，所述第二子电源线在所述衬底基板上的正投影将绿色子像素(G)对应的开口正投影分隔为第一部分(G1)和第二部分(G2)，
    所述第一子电源线包括依次连接的作为重复单元的第一重复部分和第二重复部分，所述第一重复部分的中轴线相对于所述第二重复部分的中轴线远离所述红色子像素(R)和所述蓝色子像素(B)的对应开口正投影的第二部分(R2，B2)并且所述第一重复部分在靠近所述红色子像素(R)和所述蓝色子像素(B)对应开口正投影的第二部分(R2，B2)的一侧挖空，所述红色子像素(R)和所述蓝色子像素(B)在所述衬底基板上的正投影分别与相应第一子电源线的第一重复部分和第二重复部分在所述衬底基板上的正投影交叠；
    所述第二子电源线包括依次连接的作为重复单元的第三重复部分、第四重复部分和第五重复部分，所述第三重复部分的中轴线、所述第四重复部分的中轴线和所述第五重复部分的中轴线依次靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)，并且所述第三重复部分在靠近所述绿色子像素(G)对应开口正投影的第二部分(G2)一侧挖空，所述第五重复部分在远离所述绿色子像素(G)对应开口正投 影的第二部分(G2)一侧挖空，所述绿色子像素(G)在所述衬底基板上的正投影分别与相应第二子电源线的第四重复部分和第五重复部分在所述衬底基板上的正投影或者与相应第二子电源线的第五重复部分在所述衬底基板上的正投影交叠。
  27. 根据权利要求26所述的方法，其中，所述第一重复部分的线宽为3.8μm，所述第二重复部分的线宽在5.7μm，所述第三重复部分的线宽3.8μm，所述第四重复部分的线宽6.7μm，所述第五重复部分的线宽3.0μm。
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