WO2023066279A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023066279A1
WO2023066279A1 PCT/CN2022/126073 CN2022126073W WO2023066279A1 WO 2023066279 A1 WO2023066279 A1 WO 2023066279A1 CN 2022126073 W CN2022126073 W CN 2022126073W WO 2023066279 A1 WO2023066279 A1 WO 2023066279A1
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Prior art keywords
base substrate
pixel
electrode
sub
line
Prior art date
Application number
PCT/CN2022/126073
Other languages
English (en)
French (fr)
Inventor
刘旭
王红丽
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020237042199A priority Critical patent/KR20240084508A/ko
Priority to EP22882884.4A priority patent/EP4340569A1/en
Priority to US18/549,800 priority patent/US20240155881A1/en
Publication of WO2023066279A1 publication Critical patent/WO2023066279A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • Embodiments of the disclosure relate to a display substrate and a display device.
  • Organic light emitting diode Organic Light Emitting Diode, OLED
  • OLED Organic Light Emitting Diode
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate and a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the base substrate.
  • the first insulating layer includes a first recess structure
  • the first conductive layer includes a first conductive structure
  • the first conductive structure includes a bottom surface close to the base substrate and a top surface far away from the base substrate and a first side surface between the bottom surface and the top surface
  • the second insulating layer includes a first via hole
  • the second conductive layer includes a second conductive structure
  • the first via hole is in The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the first recessed structure on the base substrate;
  • the first via hole exposes at least a portion of the first side surface of the first conductive structure part, the second conductive structure is in contact with the at least part of the first side surface of the first conductive structure;
  • the second conductive structure includes a first protrusion, and the orthographic projection of the first protrusion on the base substrate is located at the orthographic projection of the first recessed structure on the base substrate. Inside; the first protrusion is in contact with at least part of the first side surface of the first conductive structure.
  • the orthographic projection of the first recess structure on the base substrate at least partially overlaps the orthographic projection of the first via hole on the base substrate.
  • the first conductive structure further includes a second side surface between the bottom surface and the top surface, the first side surface is opposite to the second side surface, and the first side surface is opposite to the second side surface.
  • a dimension of the side surface in a direction perpendicular to the base substrate is greater than a dimension of the second side surface in a direction perpendicular to the base substrate.
  • the first side surface includes a first side surface portion located on a side of the first insulating layer away from the base substrate; the first side surface portion is not covered by the second conductive structure A dimension of the portion along a direction perpendicular to the base substrate is larger than a dimension of the second side surface along a direction perpendicular to the base substrate.
  • At least a portion of the top surface of the first conductive structure directly connected to the first side surface is separated from the second conductive layer.
  • the display substrate has a first cross-section, and the dimension of the first recessed structure in the first cross-section is b along a reference direction, and the reference direction is parallel to the board surface of the base substrate ;
  • the dimension of the overlapping region of the first via hole and the first recess structure along the reference direction is c, and the first side surface of the first conductive structure is covered by the first
  • the dimension of the part covered by the two conductive structures in the direction perpendicular to the base substrate is d;
  • the dimension of the contact portion of the structural contact in the direction perpendicular to the base substrate is e; c/b is greater than 0.1; d/e is greater than 0.3.
  • c/b is greater than 0.15 and d/e is less than 0.8.
  • c/b is less than 0.19 and d/e is less than 0.5.
  • the maximum depth of the first recessed structure is i
  • one side of the first recessed structure in the first cross-section is in contact with the plate of the base substrate
  • the angle formed by the planes is j
  • the thickness of the part of the second conductive structure in contact with the first conductive structure in the direction perpendicular to the substrate is k; d/e ⁇ 0.0273*i*sin( j)/k.
  • c/b 0.0102*i*sin(j)/k.
  • a dimension of the first side surface in a direction perpendicular to the base substrate is n
  • a dimension of the second side surface in a direction perpendicular to the base substrate is e; 0.1 *(n/e)/sin(j)>(d/n).
  • the contact portion includes a second protruding portion facing the first recessed structure, and the orthographic projection of the second protruding portion on the base substrate is located on the substrate of the first recessed structure.
  • the size of the second protrusion in the direction perpendicular to the base substrate is larger than that of the first conductive layer located in the first recessed structure A dimension of a portion of the side surface in a direction perpendicular to the side surface of the first recessed structure.
  • the first insulating layer further includes a second recessed structure spaced apart from the first recessed structure
  • the first conductive structure further includes a second side surface between the bottom surface and the top surface, so The first side surface is opposite to the second side surface, and the orthographic projection of the second side surface on the base substrate at least partially overlaps with the orthographic projection of the second recessed structure on the base substrate ;
  • the first via hole also exposes at least part of the second side surface, and the second conductive structure covers at least part of the second side surface of the first conductive structure.
  • the size of the portion of the first side surface of the first conductive structure covered by the second conductive structure is the same as that of the second side surface covered by the The size of the portion covered by the second conductive structure is different.
  • the overlapping dimension of the orthographic projection of the first via hole on the base substrate and the orthographic projection of the first recessed structure on the base substrate and the first via hole on the base substrate are different.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the base substrate;
  • the first conductive layer includes a first conductive structure;
  • the second conductive layer includes a second conductive structure;
  • the first conductive structure includes a bottom surface close to the base substrate, a top surface away from the base substrate, and a The first side surface between the bottom surface and the top surface;
  • the second insulating layer includes a first via hole, and the second conductive structure is in contact with the first conductive structure through the first via hole
  • the second conductive structure includes a first protrusion, the first via hole exposes at least part of the first side surface of the first conductive structure, and the first protrusion is connected to the first side surface of the first conductive structure.
  • the at least partial contact of one side surface; the first insulating layer includes a first recessed structure and a second recessed structure spaced apart from each other, and the first conductive structure further includes a A second side surface of a second side surface, the first side surface is opposite to the second side surface, at least part of the first conductive structure is respectively located in the first recessed structure and the second recessed structure.
  • the first conductive structure includes a second protrusion facing the first recessed structure, and the orthographic projection of the second protrusion on the base substrate is located at the position of the first recessed structure. within the orthographic projection on the substrate substrate.
  • the display substrate further includes a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, The first direction is different from the second direction;
  • the first conductive layer further includes a first signal line and a second signal line spaced apart from the first conductive structure, the first signal line and the first signal line
  • the two signal lines extend along the second direction;
  • the orthographic projection of the first protrusion on the base substrate and the orthographic projection of the first signal line on the base substrate are in the first direction
  • the upward distance is l, the distance m between the orthographic projection of the second signal line on the base substrate and the orthographic projection of the first signal line on the base substrate in the first direction
  • the display substrate includes a first cross-section perpendicular to the base substrate, and in the first cross-section, a part of the first conductive structure located on a side of the first insulating layer away from the
  • the display substrate further includes a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, The first direction is different from the second direction;
  • the second insulating layer includes a plurality of via holes arranged in a plurality of via hole rows along the first direction and the second direction and a plurality of via hole columns, the plurality of via holes include a plurality of the first via holes;
  • the plurality of via hole rows include the first via hole row, and in the first via hole row, every 1 There are three consecutive first via holes.
  • the plurality of via columns include a first via column, and in the first via column, each via is the first via, or every other via exists one of the first vias.
  • the plurality of pixel columns include a first pixel column and a second pixel column adjacent in the first direction
  • the first signal line is connected to the sub-pixels of the first pixel column to Provide the first signal
  • the second signal line is connected to the sub-pixels of the second pixel column to provide the second signal
  • the electrode of the light-emitting element of the first pixel column close to the substrate is on the side of the substrate
  • the orthographic projection on the base substrate is at least partially overlapped with the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate respectively.
  • the display substrate further includes a pixel defining layer located on a side of the pixel electrode away from the base substrate, the pixel defining layer includes a plurality of pixel opening regions, and the plurality of pixel opening regions are connected to the pixel opening regions.
  • the plurality of sub-pixels are in one-to-one correspondence, and the orthographic projection of the plurality of pixel opening regions on the base substrate is separated from the orthographic projection of the first protrusion on the base substrate.
  • the pixel defining layer includes a plurality of protrusions, and the plurality of protrusions are located between the plurality of pixel opening areas; the plurality of protrusions include surrounding the same pixel opening area.
  • the first raised part, the second raised part and the third raised part, the front of the first raised part, the second raised part and the third raised part on the base substrate The lines connecting the centers of the projections form a triangle.
  • the first raised portion is located between four adjacent pixel opening areas, and the second raised portion and the third raised portion are respectively located between two adjacent pixel opening areas. between; the area of the orthographic projection of the first raised portion on the base substrate is respectively greater than the area of the orthographic projection of the second raised portion on the base substrate and the area of the third raised portion The area of the orthographic projection on the base substrate.
  • the display substrate further includes a third conductive layer located on a side of the first conductive layer close to the base substrate, and the display substrate further includes a plurality of sub-pixels located on the base substrate, The plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction being different from the second direction;
  • the third conductive layer includes a shielding electrode and The first capacitive electrode, the shielding electrode includes a portion extending along the first direction, and a portion extending toward the first capacitive electrode of the sub-pixel where the shielding electrode is located.
  • the display substrate further includes a third conductive layer located on the side of the first conductive layer close to the base substrate, wherein the display substrate further includes a plurality of sub-layers located on the base substrate. Pixels, the plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, the first direction is different from the second direction; the first conductive layer includes A first reset voltage line extending in the second direction, the third conductive layer includes a second reset voltage line extending in the first direction, the first reset voltage line is electrically connected to the second reset voltage line connection; the display substrate further includes a semiconductor layer located on the side of the third conductive layer close to the base substrate, the semiconductor layer includes a connection portion; the connection portion connects the first reset voltage line to the sub-pixel The first pole of the reset transistor is electrically connected; the orthographic projection of the connection part on the substrate is the orthographic projection of the first reset voltage line on the substrate and the first pole of the reset transistor is
  • the display substrate further includes a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, The first direction is different from the second direction; the display substrate further includes a first gate reset voltage line and a first pixel electrode reset voltage line extending along the first direction, and Extended second gate reset voltage line and second pixel electrode reset voltage line; the first gate reset voltage line is electrically connected to the second gate reset voltage line through a second via hole, and the first pixel The electrode reset voltage line is electrically connected to the second pixel electrode reset voltage line through a third via hole; the first gate reset voltage line and the second gate reset voltage line are used to provide Reset voltage signal, the first pixel electrode reset voltage line and the second pixel electrode reset voltage line are used to provide reset voltage signal to the pixel electrode.
  • the second pixel electrode reset voltage line is electrically connected to the first electrode of the pixel electrode reset transistor through a fourth via hole, and the fourth via hole is connected to the third via hole on the base substrate.
  • the orthographic projections on are separated from each other.
  • the second gate reset voltage line is electrically connected to the first electrode of the gate reset transistor through a fifth via hole, and the fifth via hole is connected to the second via hole on the base substrate.
  • the orthographic projections on are separated from each other.
  • the display substrate further includes a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged as a plurality of pixel rows along a first direction and a plurality of pixel columns along a second direction, The first direction is different from the second direction; each sub-pixel includes a first capacitive electrode, and the display substrate further includes a plurality of data lines extending along the second direction; adjacent in the first direction The first capacitive electrodes of the two sub-pixels are connected through a connection part, and the plurality of data lines respectively overlap with the plurality of connection parts in a direction perpendicular to the base substrate; the connection part includes a corresponding data line There is a first portion that overlaps and a second portion that does not overlap with the corresponding data line; the size of the first portion in the second direction is larger than the size of the second portion in the second direction; The display substrate further includes a reset voltage line extending along the second direction, and the second part overlaps with the reset voltage line in a direction per
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer sequentially disposed on the base substrate;
  • the display substrate further includes adjacent first subpixels and second subpixels located on the base substrate in a first direction, the first subpixel has a first pixel circuit, and the second subpixel has a first pixel circuit.
  • Two pixel circuits; the first pixel circuit and the second pixel circuit respectively include capacitors, and the capacitors include a first capacitor electrode located on the second metal layer and a second capacitor electrode located on the first metal layer, and the first capacitor electrode is located on the first metal layer.
  • the first capacitive electrode of a pixel circuit and the first capacitive electrode of the second pixel circuit are connected to each other as an integral capacitive electrode block, the capacitive electrode block has a first opening and a second opening, and the first opening is in the
  • the orthographic projection on the base substrate overlaps with the orthographic projection of the second capacitive electrode of the first pixel circuit on the base substrate, and the orthographic projection of the second opening on the base substrate overlaps with the The orthographic projection of the second capacitive electrode of the second pixel circuit on the substrate overlaps, and the orthographic projection area of the first opening on the substrate is the same as that of the second opening on the substrate.
  • the area of the orthographic projection on the substrate is different.
  • the second conductive layer includes a reset voltage line, a first data line, a second data line, a first power line, and a second power line extending along a second direction, and the first direction is consistent with the The second direction is different; each of the first pixel circuit and the second pixel circuit includes a driving transistor and a data writing transistor; the reset voltage line is configured to provide the first pixel circuit and the second pixel The pixel electrode of the circuit or the gate of the driving transistor provides a reset voltage, and the first data line and the second data line are configured to provide data writing transistors of the first pixel circuit and the second pixel circuit respectively.
  • Data voltage, the first power supply line and the second power supply line are respectively configured to provide power supply voltages to the driving transistors of the first pixel circuit and the second pixel circuit; the reset voltage line is located at the first between the data line and the second data line; the first data line and the second data line are located between the first power line and the second power line; the first power line and the Each of the second power lines has a closed hollow area.
  • the orthographic projection of the pixel electrode of the first subpixel on the base substrate is connected to the reset voltage line, the first data line, the second data line, and the first power supply line. overlap with the orthographic projection of the second power line on the base substrate.
  • the display substrate further includes a plurality of sub-pixels, the plurality of sub-pixels are located on the base substrate and arranged in a plurality of pixel rows and a plurality of pixel columns along the first direction and the second direction, The first direction is different from the second direction;
  • the first conductive layer further includes a plurality of connection electrodes, and the plurality of connection electrodes are connected to the plurality of sub-pixels in one-to-one correspondence to provide a power supply voltage;
  • a sub-pixel includes a first sub-pixel, the display substrate further includes a reset voltage line extending along the second direction, the reset voltage line is connected to the first sub-pixel to provide a reset voltage, and the first protruding portion
  • the orthographic projection on the base substrate is located between the orthographic projection of the connection electrode correspondingly connected to the first sub-pixel on the base substrate and the orthographic projection of the reset voltage line on the base substrate .
  • the distance between the first protrusion and the reset voltage line is smaller than the distance between the first protrusion and the connection electrode.
  • the connecting electrode includes a main body and an extension extending along the first direction, the extension having a size in the second direction smaller than the main body in the second direction ; In the second direction, the first conductive structure at least partially overlaps with the extension portion of the connecting electrode.
  • the second conductive layer includes a plurality of power supply electrodes, the plurality of power supply electrodes are connected to the plurality of connection electrodes in one-to-one correspondence to provide the power supply voltage, and the power supply electrodes corresponding to each pixel column are connected to each other connected as an integral structure to form a plurality of power lines extending along the second direction.
  • the second conductive layer further includes a plurality of data lines extending along the second direction, and the plurality of data lines are respectively connected to the plurality of pixel columns in a one-to-one correspondence to provide data signals;
  • the plurality of data lines are divided into multiple data line groups, each data line group includes two data lines; a data line group is arranged between every two adjacent pixel columns, and the interval between adjacent data line groups is Two power cords.
  • the display substrate further includes a plurality of reset voltage lines extending along the second direction, and the plurality of reset voltage lines include first reset voltage lines and second reset voltage lines alternately arranged in the first direction.
  • Two reset voltage lines, the first reset voltage line and the second reset voltage line are respectively configured to provide a first reset voltage and a second reset voltage; the adjacent first reset voltage line and the second reset line are spaced apart There are two pixel columns.
  • the plurality of reset voltage lines are located on the first conductive layer, and a first reset voltage line or a second reset voltage line is provided between two power lines between adjacent data line groups;
  • the orthographic projection of any one of the multiple reset voltage lines on the base substrate is separated from the orthographic projection of any one of the multiple power supply lines on the base substrate.
  • the multiple reset voltage lines are located on the second conductive layer, and are arranged in one-to-one correspondence with multiple data line groups, and each reset voltage line is located between two data lines in the corresponding data line group between.
  • two power supply lines between adjacent data line groups are connected to each other as an integral structure, so that two power supply electrodes adjacent to each other in the first direction in the two power supply lines are connected to each other as An integrated power supply electrode group;
  • the display substrate includes a plurality of second conductive structures, and the plurality of second conductive structures are arranged in one-to-one correspondence with the plurality of power supply electrodes;
  • the power supply electrode group includes a hollowed out area, and the hollowed out The region is provided with two second conductive structures.
  • the second conductive layer further includes a connection line, and the connection line extends along the second direction to separate the hollowed out area into two hollowed out sub-areas; the two second conductive structures are respectively It is arranged in the two hollowed-out sub-regions and respectively located on both sides of the connection line.
  • the display substrate further includes a third conductive layer on the side of the first conductive layer close to the base substrate, and a semiconductor layer between the third conductive layer and the second metal layer. layer, wherein the second metal layer is located on the side of the third conductive layer close to the base substrate;
  • the sub-pixel includes a reset transistor configured to connect to the first electrode of the light emitting element reset, the reset transistor includes an active layer located in the semiconductor layer;
  • the display substrate includes a first reset control line located in the second metal layer and a second reset control line located in the third conductive layer control line, the first reset control line and the second reset control line are respectively configured to control the gate voltage of the reset transistor, and the first reset control line and the second reset control line are connected between the
  • the orthographic projections on the substrate substrate are at least partially overlapping.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a plurality of sub-pixels located on the base substrate, each of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit is used to drive The light-emitting element emits light; the plurality of pixel circuits of the plurality of sub-pixels are arranged as a plurality of pixel rows extending in a first direction and a plurality of pixel columns extending in a second direction, and the first direction is different from the second direction;
  • the pixel circuit includes a driving transistor and a storage capacitor, the driving transistor is configured to be connected to the light emitting element and control a driving current flowing through the light emitting element;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode, The first capacitor electrode is configured to receive a first power supply voltage; the plurality of sub-pixels includes a first sub-pixel, and the first sub-pixel further includes a shielding electrode, and the shielding electrode is connected to the
  • the capacitive electrodes are arranged in the same layer and have an integral structure, the shielding electrode includes a first shielding portion and a second shielding portion, the second shielding portion extends from the first capacitive electrode along the second direction, the shielding electrode The first shielding portion extends from the second shielding portion along the first direction; the display substrate further includes a semiconductor pattern, the semiconductor pattern is located in the same semiconductor layer as the active layer of the driving transistor, and is perpendicular to the In the direction of the base substrate, the first shielding portion at least partially overlaps with the semiconductor pattern.
  • the pixel circuit further includes another transistor, and the other transistor includes a gate, a first pole, and a second pole, and the first pole and the second pole of the other transistor are respectively connected to the driver
  • the second pole of the transistor is connected to the gate; the semiconductor pattern is configured as at least part of an active layer of another transistor.
  • the another transistor includes a first gate and a second gate
  • the active layer of the other transistor includes a first portion, a second portion, and a third portion
  • the first portion is formed on the substrate
  • the orthographic projection on the base substrate overlaps with the orthographic projection of the first grid on the base substrate
  • the orthographic projection of the second part on the base substrate overlaps with the orthographic projection of the second grid on the base substrate.
  • the orthographic projections of the base substrates overlap, the third portion is located between the first portion and the second portion and connects the first portion and the second portion, and the semiconductor pattern is configured as the other The third part of the active layer of a transistor.
  • the first shielding portion includes a first subsection and a second subsection, and the orthographic projection of the first subsection on the base substrate is the same as that of the semiconductor pattern on the base substrate.
  • the orthographic projection of the second subsection overlaps, the orthographic projection of the second subsection on the base substrate does not overlap the orthographic projection of the semiconductor pattern on the base substrate, and the first subsection is in the A dimension in the second direction is larger than a dimension of the second subsection in the second direction.
  • the display substrate further includes a power line located on the side of the first capacitive electrode away from the base substrate, wherein the power line is configured to be connected to the first capacitive electrode of the first sub-pixel electrically connected to provide the first supply voltage.
  • the first sub-pixel further includes a connection electrode, and the connection electrode is used to electrically connect the gate of the driving transistor of the first sub-pixel to the second electrode of another transistor; the first The orthographic projection of the connecting electrode of the sub-pixel on the base substrate and the orthographic projection of the second shielding portion of the shielding electrode of the first sub-pixel on the base substrate at least partially intersect in the first direction. stack.
  • the orthographic projection of the connection electrode of the first subpixel on the base substrate is located in the integral body formed by the first capacitive electrode and the shielding electrode of the first subpixel in the second direction.
  • the structure is within the scope of the orthographic projection on the substrate substrate.
  • the pixel circuit further includes a data writing transistor connected to the driving transistor, and the display substrate further includes a data line configured to be connected to the data writing transistor.
  • the first electrode of the transistor is electrically connected to provide the data signal, and the orthographic projection of the second shielding part of the first subpixel on the substrate is located at the connection electrode of the first subpixel on the substrate Between the orthographic projection on the substrate and the orthographic projection of the data line on the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate provided in any one of the above embodiments.
  • FIG. 1 is a schematic diagram of a display substrate
  • FIG. 2 is one of the schematic diagrams of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5A;
  • FIG. 5C is a timing signal diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 6A is a fourth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 6B is a cross-sectional view of Figure 6A along the section line A-A';
  • FIG. 7 is a fifth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8A is a sixth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8B is a seventh schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8C is an eighth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9A is a ninth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9B is a tenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9C is an eleventh schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9D is the twelveth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10A is a thirteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10B is a fourteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10C is a fifteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a sixteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12A is a seventeenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12B is an eighteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12C is a nineteenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 13A is a schematic diagram No. 20 of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 13B is a cross-sectional view of Figure 13A along the section line B-B';
  • FIG. 14 is a twenty-first schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a twenty-second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 16A is a twenty-third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 16B is a twenty-fourth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 16C is the twenty-fifth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 17A is a twenty-sixth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 17B is a twenty-seventh schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 18A is a twenty-eighth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 18B is a twenty-ninth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 18C is a thirtyth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 19A is a thirty-first schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 19B is a thirty-second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 19C is a thirty-third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of a touch display panel provided by at least one embodiment of the present disclosure.
  • Fig. 22 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of a display substrate.
  • the display substrate includes a first insulating layer 301', a first conductive layer 201', a second insulating layer 302' and a second conductive layer 202' sequentially disposed on a base substrate (not shown).
  • a via hole V1' is formed in the second insulating layer 302', and the second conductive layer 202' is electrically connected to the first conductive layer 201' through the via hole V1'.
  • the second conductive layer 202' only overlaps the upper surface of the first conductive layer 201', the overlapping area is limited, and the contact resistance is relatively large, which is not conducive to the rapid transmission of electrical signals.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer sequentially disposed on the base substrate.
  • the first insulating layer includes a first recess structure
  • the first conductive layer includes a first conductive structure
  • the first conductive structure includes a bottom surface close to the base substrate and a top surface far away from the base substrate and a first side surface between the bottom surface and the top surface
  • the second insulating layer includes a first via hole
  • the second conductive layer includes a second conductive structure, and the second conductive structure passes through
  • a first via hole is in contact with the first conductive structure, and an orthographic projection of the first via hole on the base substrate at least partially overlaps an orthographic projection of the first recessed structure on the base substrate;
  • the first via exposes at least a portion of the first side surface of the first conductive structure, and the second conductive structure is in contact with the at least
  • the display substrate provided by at least one embodiment of the present disclosure, at least part of the first side surface of the first conductive structure is exposed by setting the first via hole, so that the second conductive structure not only contacts the upper surface of the first conductive structure, but also Contact with the first side surface of the first conductive structure effectively increases the contact area between the first conductive structure and the second conductive structure, not only reduces the contact resistance, improves the transmission efficiency of electrical signals, but also can
  • the side surface of the second conductive structure plays a protective role, such as protecting the side surface from being corroded by water vapor; in addition, this setting also increases the cross-sectional area of the second conductive structure in the longitudinal direction (the direction perpendicular to the base substrate), which can not only effectively shield the second conductive structure
  • the interference of a conductive structure to other conductive structures in its substrate can also reduce the mutual interference between the signal lines on both sides of the second conductive structure.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate, a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer sequentially disposed on the base substrate.
  • the display substrate further includes a plurality of sub-pixels, the plurality of sub-pixels are located on the base substrate and arranged in a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, the first direction and the The second direction described above is different.
  • the first conductive layer includes a first conductive structure spaced apart from each other, a first signal line, and a second signal line, and the first signal line and the second signal line extend along the second direction;
  • the second The conductive layer includes a second conductive structure;
  • the first conductive structure includes a bottom surface close to the base substrate, a top surface far away from the base substrate, and a first conductive structure between the bottom surface and the top surface.
  • the second insulating layer includes a first via hole, and the second conductive structure is in contact with the first conductive structure through the first via hole;
  • the second conductive structure includes a first protrusion, and The first via hole exposes at least part of the first side surface of the first conductive structure, and the first protrusion is in contact with the at least part of the first side surface of the first conductive structure;
  • the first The orthographic projection of the protrusion on the base substrate is located between the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure not only increases the contact area between the first conductive structure and the second conductive structure by disposing the first protrusion of the second conductive structure in contact with the first side surface of the first conductive structure. , reducing the contact resistance between the two, and effectively increasing the longitudinal cross-sectional area of the second conductive structure, which can effectively shield the interference of the first conductive structure to other conductive structures in the substrate, and at the same time set the first protrusion on the Between the first signal line and the second signal line, mutual interference between the first signal line and the second signal line can also be reduced.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the base substrate, and a The second conductive layer is away from the pixel electrode on the side of the base substrate, the pixel electrode is configured as a first electrode of a light-emitting element, and the pixel electrode is electrically connected to the second conductive structure.
  • the first insulating layer includes a first recess structure, the first conductive layer includes a first conductive structure, and the second conductive layer includes a second conductive structure;
  • the first conductive structure includes a a bottom surface, a top surface away from the base substrate, and a first side surface between the bottom surface and the top surface;
  • the second insulating layer includes a first via hole, and the second conductive structure passes through
  • the first via hole is in contact with the first conductive structure, and the orthographic projection of the first via hole on the base substrate is at least partly the same as the orthographic projection of the first recessed structure on the base substrate Overlap;
  • the second conductive structure includes a first protrusion, the first via exposes at least part of the first side surface of the first conductive structure, the first protrusion and the first conductive structure The at least part of the first side surface is in contact.
  • the display substrate provided by at least one embodiment of the present disclosure effectively improves the contact between the first conductive structure and the second conductive structure by arranging the first protruding portion of the second conductive structure in contact with the first side surface of the first conductive structure. area, which reduces the contact resistance and improves the transmission efficiency of electrical signals; in addition, because this setting also increases the cross-sectional area of the second conductive structure in the longitudinal direction (perpendicular to the substrate), it can not only effectively shield the first conductive structure
  • the interference of the structure to other conductive structures in its substrate can also reduce the mutual interference between the signal lines located on both sides of the second conductive structure.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the base substrate.
  • the first insulating layer includes a first recess structure
  • the first conductive layer includes a first conductive structure
  • the first conductive structure includes a bottom surface close to the base substrate and a top surface far away from the base substrate and a first side surface between the bottom surface and the top surface
  • the second insulating layer includes a first via hole
  • the second conductive layer includes a second conductive structure
  • the first via hole is in The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the first recessed structure on the base substrate
  • the first via hole exposes at least a portion of the first side surface of the first conductive structure part
  • the second conductive structure is in contact with the at least part of the first side surface of the first conductive structure
  • the display substrate provided by at least one embodiment of the present disclosure can not only effectively increase the contact area between the first conductive structure and the second conductive structure, reduce the contact resistance, but also ease the contact between the second conductive structure and the first side through the above configuration.
  • the slope of the portion where the surfaces are overlapped makes the second conductive structure not too steep to break.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer sequentially disposed on the base substrate.
  • the first conductive layer includes a first conductive structure;
  • the second conductive layer includes a second conductive structure;
  • the first conductive structure includes a bottom surface close to the base substrate and a top surface away from the base substrate and a first side surface between the bottom surface and the top surface;
  • the second insulating layer includes a first via hole, and the second conductive structure communicates with the first conductive structure through the first via hole Structural contact;
  • the second conductive structure includes a first protrusion, the first via exposes at least part of the first side surface of the first conductive structure, the first protrusion is in contact with the first conductive structure The at least part of the first side surface is in contact;
  • the first insulating layer includes a first recessed structure and a second
  • the contact relationship between the second insulating layer and the two sides of the first conductive structure is similar, and the balance of force on both sides of the first conductive structure is maintained, preventing the second insulating layer from contacting the two sides of the first conductive structure.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer sequentially disposed on the base substrate.
  • the display substrate further includes adjacent first sub-pixels and second sub-pixels located on the base substrate in the first direction, the first sub-pixel has a first pixel circuit, and the second sub-pixel There is a second pixel circuit; the first pixel circuit and the second pixel circuit respectively include capacitors, and the capacitors include a first capacitor electrode located on the second metal layer and a second capacitor electrode located on the first metal layer, so
  • the first capacitive electrode of the first pixel circuit and the first capacitive electrode of the second pixel circuit are connected to each other as an integral capacitive electrode block, the capacitive electrode block has a first opening and a second opening, and the first opening
  • the orthographic projection on the base substrate overlaps the orthographic projection of the second capacitive electrode of the first pixel circuit on the base substrate
  • the driving circuit needs to be adjusted to balance the charging speed of the two, thereby improving the uniformity of the display;
  • the opening sizes of the capacitive electrodes are set differently, that is, the two sub-pixels have different capacitive electrodes and storage capacitors, and thus have different charging speeds, thereby helping to improve display uniformity.
  • the orthographic area of the first opening on the base substrate is smaller than the orthographic area of the second opening on the base substrate.
  • the side surface in the present disclosure may be formed by recessing the top surface, that is, may be continuous with the top surface.
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate and a plurality of sub-pixels located on the base substrate.
  • Each sub-pixel of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit is used to drive a light-emitting element to emit light; the plurality of pixel circuits of the plurality of sub-pixels are arranged in a plurality of pixel rows and a plurality of pixels along the first direction and the second direction.
  • the pixel circuit includes a driving transistor and a storage capacitor, and the driving transistor is configured to be connected to the light emitting element and control the drive flowing through the light emitting element current;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is configured to receive a first power supply voltage, the plurality of sub-pixels includes a first sub-pixel, and the first sub-pixel also includes A shielding electrode, the shielding electrode is provided on the same layer as the first capacitive electrode of the first sub-pixel and has an integral structure, the shielding electrode includes a first shielding part and a second shielding part, and the second shielding part is formed from The first capacitor electrode extends along the second direction, and the first shielding portion extends from the second shielding portion along the first direction;
  • the display substrate further includes a semiconductor pattern, and the semiconductor pattern
  • the active layer of the driving transistor is located in the same semiconductor layer, and in a direction perpendicular to the base substrate, the first shielding portion at least partially
  • the properties of the semiconductor layer are easy to change under light and become unstable, and the stability of the semiconductor pattern can be improved by setting the first shielding part to shield the semiconductor pattern.
  • the semiconductor pattern may be a part of the active layer of the transistor, such as the semiconductor region or the conductorized region of the active layer. In this case, the above arrangement can effectively improve the stability of the transistor.
  • FIG. 2 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 20 includes a base substrate 100 , a first insulating layer 301 , a first conductive layer 201 , a second insulating layer 302 and a second conductive layer 202 sequentially disposed on the base substrate 100 .
  • the first insulating layer 101 is directly on the base substrate 100 , this is not a limitation of the present disclosure.
  • other film layers such as other insulating layers or conductive layers, may also be disposed between the first insulating layer 101 and the base substrate 100 .
  • the first insulating layer 301 includes a recessed structure G1 (an example of a first recessed structure in the present disclosure), and the recessed structure G1 may or may not pass through the first insulating layer 301 .
  • the recessed structure G1 may be a via hole; in other examples, the recessed structure G1 may also be a groove.
  • the present disclosure does not limit the specific structure of the concave structure G1.
  • the first conductive layer 201 includes a first conductive structure 21, and the first conductive structure 21 includes a recess structure G2.
  • the recessed structure G2 is formed because the first conductive structure 21 covers the recessed structure G1 , and the first conductive structure 21 fills the first recessed structure G1 to form the recessed structure G2 .
  • the recessed structure G1 and the recessed structure G2 at least partially overlap.
  • the first conductive structure 21 includes a bottom surface 21 a close to the base substrate 100 , a top surface 21 b away from the base substrate 100 , and a first side surface 21 c between the bottom surface 21 a and the top surface 21 b.
  • the first side surface 21c is formed due to the downward depression of the first conductive structure 21 .
  • the first side surface 21c may be a sidewall of the recessed structure G2, and the part of the first side surface 21c in contact with the second conductive structure 22 is located on the upper surface of the first insulating layer 301 away from side of the base substrate.
  • the first side surface 21c and the top surface 21b are located on the same side of the first conductive structure 21 and are directly connected to each other.
  • the first side surface 21c and the bottom surface 21a are respectively located on two sides of the first conductive structure 21 .
  • the second insulating layer 302 includes a via hole V1 (an example of a first via hole in the present disclosure), the second conductive layer 202 includes a second conductive structure 22, and the second conductive structure 22 is connected to the first conductive structure through the via hole V1.
  • the second conductive structure 22 is in contact with at least part of the first side surface 21 c of the first conductive structure 21 .
  • the second conductive structure 22 is not only in contact with the upper surface 21b of the first conductive structure 21, but also contacts with the first conductive structure 21.
  • the first side surface 21c of the structure 21 is in contact, which effectively increases the contact area between the first conductive structure 21 and the second conductive structure 22, reduces the contact resistance, and improves the transmission efficiency of electrical signals; in addition, this setting also improves the second
  • the cross-sectional area of the conductive structure 22 in the longitudinal direction (the direction perpendicular to the base substrate) can not only effectively shield the interference of the first conductive structure to other conductive structures in the substrate, but also reduce the interference on both sides of the second conductive structure. Mutual interference between signal lines.
  • the orthographic projection of the recessed structure G1 on the substrate and the orthographic projection of the via hole V1 on the substrate at least partially overlap, so that the overlapping part of the second insulating layer 302 and the recessed structure G1 is under the Concave, exposing the first side surface 21c of the first conductive structure 21, so that the second conductive structure 22 is not only in contact with the top surface 21b of the first conductive structure 21, but also in contact with the first side surface 21c.
  • the second conductive structure 22 includes a protruding portion 220 (an example of the first protruding portion of the present disclosure), and the protruding portion 220 protrudes downward, that is, protrudes toward the base substrate 100 .
  • the orthographic projection on the base substrate 100 is located within the orthographic projection of the recessed structure G1 on the base substrate; the protrusion 220 is in contact with at least part of the first side surface 21 c of the first conductive structure 21 .
  • the protrusion 220 effectively increases the cross-sectional area of the second conductive structure 22 in the longitudinal direction.
  • the first side surface 21c of the first conductive structure 21 includes a protruding curved surface 21d, and the protruding portion 220 of the second conductive structure 22 covers at least part of the protruding curved surface.
  • the first conductive structure 21 includes a connecting portion 21f located in the first recessed structure G1 and connected to the protruding curved surface 21d; Relative to the connecting portion 21f, it protrudes towards the middle of the first recessed structure G1.
  • the contact area be further increased, but also the overlap between the second conductive structure 22 and the first side surface 21c can be eased.
  • the slope of the connected part makes the protruding part 220 not too steep and breaks.
  • the included angle between the tangent of the protruding curved surface and the top surface 21b of the first conductive structure 21 is greater than 70 degrees, and gradually increases from top to bottom. get smaller.
  • the first conductive structure 21 includes a contact portion 211 located on the side of the first insulating layer 301 away from the substrate and in contact with the second conductive structure 22.
  • the contact portion 211 can be regarded as the first conductive structure, for example.
  • the contact portion 211 includes a protruding portion 210 (an example of the second protruding portion of the present disclosure) facing the recessed structure G1, and the orthographic projection of the protruding portion 210 on the substrate is located at the position of the recessed structure G1.
  • the protruding portion 210 is an end portion of the contact portion 211 close to the concave structure G1 , and is a portion of the top surface of the contact portion 211 protruding toward the concave structure G1 relative to the bottom surface.
  • the surface of the protruding portion 210 facing the recessed structure G1 is a part of the first side surface 21c.
  • the maximum dimension of the protruding portion 210 is greater than that of the portion of the first conductive structure 21 covering the side surface (side wall) of the recessed structure G1. Maximum thickness.
  • one side surface of the contact portion 211 close to the recessed structure G1 is a part of the first side surface 21c, that is, the first side surface 21c is located on the upper surface of the first insulating layer 301 away from the substrate.
  • a portion of one side of the substrate, this portion is referred to as a first side surface portion.
  • the first conductive structure 21 also includes a second side surface 21d away from the recessed structure G1; the size of the first side surface portion in the direction perpendicular to the base substrate is larger than that of the second side surface 21d in the direction perpendicular to the base substrate. Dimensions in the direction.
  • the second side surface 21 d is not in contact with the second conductive structure 22 .
  • at least a portion of the top surface 21b of the first conductive structure 21 connected to the second side surface 21 is separated from the second conductive layer 202.
  • first side surface part is in contact with the second conductive structure 22 and the second side surface 21d is not in contact with the second conductive structure 22, setting the longitudinal dimension of the first side surface part to be larger helps to improve the second conductive structure 22.
  • the flatness of the portion in contact with the top surface 21b of the first conductive structure 21 improves the yield of the subsequent manufacturing process.
  • the maximum dimension of the protruding portion 210 is larger than the portion of the first conductive layer 21 covering the side surface of the recessed structure G1 (that is, the side of the recessed structure G2 located in the recessed structure G1
  • the maximum thickness of the wall is parallel to the plate surface of the substrate substrate. This arrangement facilitates the overlapping of the protruding portion 220 and the protruding portion 210 .
  • the display substrate 20 has a first cross section, that is, the cross section shown in FIG. In the cross section, the dimension of the overlapping region of the via hole V1 and the recessed structure G1 along the reference direction F is c.
  • the distance between the lowest points of the recessed structure or via structure in the first section is taken as the recessed structure or The scope of the via hole structure; the following embodiments are the same as this and will not be repeated.
  • the dimension of the portion of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 in the direction perpendicular to the base substrate 100 is d, and the contact portion 211 of the first conductive structure 21 is perpendicular to the The dimension of the base substrate direction is e.
  • the dimension (n-d) of the portion of the first side surface 21c not covered by the second conductive structure 22 along the direction perpendicular to the base substrate is larger than that of the second side surface 21d along the direction perpendicular to the base substrate.
  • the ratio r1 of the size of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 to the size of the first side surface 21c and the overlapping size of the via hole V1 and the recessed structure G1 and the The ratio r2 of the size of the recessed structure G1 is positively correlated, that is, the larger the overlapping ratio r2 of the via hole V1 and the recessed structure G1 is, the larger the covering size of the first side surface 21c of the first conductive structure 21 by the second conductive structure 22 is. bigger.
  • the second conductive structure 22 can effectively cover the side surface of the first conductive structure 21, thereby effectively reducing the contact resistance between the two.
  • the material of the second conductive layer 202 is different from that of the first conductive layer 201 .
  • the second conductive layer 202 includes a stacked structure of ITO/AG/ITO
  • the first conductive layer 201 includes a stacked structure of TI/AL/TI.
  • c/b is greater than 0.15 and d/e is less than 0.8.
  • c/b is less than 0.19 and d/e is less than 0.5.
  • the second conductive structure 22 is configured as a pixel electrode (such as an anode) of a light-emitting element
  • the performance of the light-emitting material will be affected by the second conductive structure 22 Influenced by the flatness of the surface, if the flatness of the second conductive structure 22 is too low, the luminous efficiency of the light emitting element will be reduced.
  • Making the overlapping size of the via hole V1 and the recessed structure G1 as small as possible within a certain range can help to improve the flatness of the second conductive structure 22 , thereby improving the display performance of the display substrate.
  • the maximum depth of the recessed structure G1 is i
  • the angle between one side of the recessed structure G1 in the first section and the plate surface of the base substrate is is j
  • the dimension of the portion of the second conductive structure 22 in contact with the first conductive structure 21 in a direction perpendicular to the base substrate is k.
  • the shape of the concave structure G1 in the first section is an inverted trapezoid.
  • the side is a side of the recessed structure G1 close to the protruding portion 210 .
  • the covered size of the first side surface 21c is positively related to the depth of the recessed structure G1 and the bottom angle of the recessed structure G1, and negatively related to the thickness of the second conductive layer 202.
  • d/e or c/b can be reduced Small, the overlap between the via hole V1 and the recessed structure G1 can be reduced, so that the size of the downward protrusion 220 of the second conductive structure 22 can be reduced, and the flatness of the second conductive layer 22 can be improved.
  • the dimension of the first side surface 21c in the direction perpendicular to the base substrate is n
  • the dimension of the second side surface portion in the direction perpendicular to the base substrate 100 is e.
  • n/e the ratio of the size of the first side surface 21c to the size of the second side surface 21d
  • the larger the area to be covered that is, n/e is proportional to d/n
  • the concave structure G1 The larger the bottom angle of , the larger the slope of the corresponding sidewall of the recessed structure G1 is, the less likely water vapor will remain on the surface, and the less it needs to be covered, that is, sin(j) is inversely proportional to d/n.
  • the value of d/n is adjusted, so that the exposed side surface of the first conductive structure is sufficiently protected, the corrosion of water vapor is reduced, and the working life of the first conductive structure is improved.
  • the covered size of the first side surface 21 c can be made smaller, thereby improving the flatness of the second conductive structure 22 .
  • b 2.821um
  • c 0.599um
  • c/b 0.212
  • d 0.3339um
  • e 0.5872um
  • d/e 0.569.
  • b 2.816um
  • c 0.6465
  • c/b 0.2296
  • d 0.5603um
  • e 0.8477
  • d/e 0.661um.
  • FIG. 3 is a schematic diagram of a display substrate provided by other embodiments of the present disclosure.
  • the first insulating layer 301 further includes a recessed structure G3 (an example of a second recessed structure in the present disclosure) spaced apart from the recessed structure G1 , and the recessed structure G2 may or may not penetrate the first insulating layer 301 .
  • the recessed structure G2 may be a via hole; in other examples, the recessed structure G2 may also be a groove.
  • the present disclosure does not limit the specific structure of the recessed structure G2.
  • the first conductive structure 21 further includes a recess structure G4 .
  • the recessed structure G4 is formed because the first conductive structure 21 covers the recessed structure G3, and the first conductive structure 21 fills the first recessed structure G3 to form the recessed structure G4.
  • the recessed structure G3 at least partially overlaps with the recessed structure G4 .
  • the first conductive structure 21 further includes a second side surface 21 e located between the bottom surface 21 a and the top surface 21 b thereof, and the second side surface 21 e is opposite to the first side surface 21 c.
  • the second side surface 21e and the first side surface 21c are connected by the top surface 21b.
  • the orthographic projection of the second side surface 21e on the base substrate at least partially overlaps with the orthographic projection of the recessed structure G3 on the base substrate.
  • the first via hole V1 also exposes at least a portion of the second side surface 21 e
  • the second conductive structure 22 also covers at least a portion of the second side surface 21 e of the first conductive structure 21 .
  • the recessed structure G1 and the recessed structure G3 are located on both sides of the via hole V1 respectively, and at least partially overlap with the via hole V1 in a direction perpendicular to the base substrate, so that the second insulating layer 302 is recessed to expose the via hole V1 respectively.
  • a part of the first side surface 21c and the second side surface 21e, that is, the first conductive structure 21 has an upwardly convex shape in the via hole V1, and the second conductive structure 23 is connected to the top of the first conductive structure.
  • the surface 21b, the first side surface 21c and the second side surface 21e are all in contact, so that the contact area is further increased, the contact resistance is reduced, and the shielding and protection capabilities are improved.
  • the size of the portion of the first side surface 21c of the first conductive structure 21 covered by the second conductive structure 22 is the same as the size of the portion of the second side surface 21e covered by the second conductive structure 22. Dimensions vary.
  • the overlapping area of the orthographic projection of the via hole V1 on the substrate and the orthographic projection of the recessed structure G1 on the substrate and the orthographic projection of the via hole V1 on the substrate is different.
  • the overlapping of the orthographic projection of the via hole V1 on the substrate and the orthographic projection of the recessed structure G1 on the substrate are different.
  • FIG. 4 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the cross-sectional structures shown in FIGS. 2 and 3 may be, for example, the cross-sectional structure of the display substrate shown in FIG. 4 .
  • the display substrate 20 includes a display area 110 and a non-display area 103 outside the display area 110 .
  • the non-display area 103 is located in the peripheral area of the display area 110 .
  • the display substrate 20 includes a plurality of sub-pixels P located in the display area 110 .
  • the plurality of sub-pixels are arranged in an array, for example, a plurality of pixel rows and a plurality of pixel columns are arranged along the first direction D1 and the second direction D2.
  • the first direction D1 and the second direction D2 are different, for example, they are orthogonal.
  • the pixel row and the pixel column do not necessarily extend strictly along a straight line, but may also extend along a curve (such as a broken line), and the curve generally extends along the first direction D1 or the second direction D2 respectively.
  • Each sub-pixel includes a pixel circuit for driving a light-emitting element to emit light, and a plurality of pixel circuits are arranged in an array along the first direction D1 and the second direction D2.
  • sub-pixels form pixel units in a traditional RGB manner to achieve full-color display, and the present disclosure does not limit the arrangement of sub-pixels and the way to achieve full-color display.
  • the display substrate 20 further includes conducting wires (such as gate lines 11 ) extending along the first direction D1 and a plurality of conducting wires (such as data lines 12 ) extending along the second direction D2 in the display area 110 . ), the plurality of horizontal wires and the plurality of vertical wires intersect each other to define a plurality of pixel areas in the display area 110 , and one sub-pixel 100 is correspondingly arranged in each pixel area.
  • FIG. 2 only shows the approximate positional relationship of the gate lines 11 , the data lines 12 and the sub-images 100 in the display substrate, which can be designed according to actual needs.
  • the pixel circuit is, for example, a 2T1C (that is, two transistors and a capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, etc. nTmC (n, m are positive integer) pixel circuits.
  • the pixel circuit may further include a compensation sub-circuit, the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc. as required.
  • the display substrate may further include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area.
  • the gate driving circuit 13 is connected to the pixel circuit through the gate line 11 to provide various scanning signals
  • the data driving circuit 14 is connected to the pixel circuit through the data line 12 to provide data signals.
  • the gate driving circuit 13 and the data driving circuit 14 shown in FIG. 4 , and the positional relationship between the gate line 11 and the data line 12 in the display substrate are just examples, and the actual arrangement positions can be designed according to requirements.
  • the display substrate 20 may further include a control circuit (not shown).
  • the control circuit is configured to control the data driving circuit 14 to apply the data signal, and control the gate driving circuit to apply the scan signal.
  • One example of the control circuit is a timing control circuit (T-con).
  • the control circuit can be in various forms, for example, it includes a processor and a memory, the memory includes executable code, and the processor runs the executable code to execute the above detection method.
  • a processor may be a central processing unit (CPU) or other forms of processing devices with data processing capabilities and/or instruction execution capabilities, such as microprocessors, programmable logic controllers (PLCs), and the like.
  • CPU central processing unit
  • PLCs programmable logic controllers
  • a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory.
  • the volatile memory may include random access memory (RAM) and/or cache memory (cache), etc., for example.
  • Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions can be stored on the computer-readable storage medium, and the processor can execute the desired functions of the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit, and may also include a light emission control sub-circuit, a reset circuit, etc. as required.
  • FIG. 5A shows a schematic diagram of a pixel circuit.
  • the pixel circuit includes a driving subcircuit 122 , a data writing subcircuit 126 and a compensation subcircuit 128 .
  • the driving sub-circuit 122 includes a control terminal (that is, a control electrode) 122a, a first terminal 122b and a second terminal 122c, and is configured to be connected to the light-emitting element 120 and configured to control the driving circuit according to the voltage on the control electrode.
  • the control terminal 122a of the driving subcircuit 122 is connected to the first node N1, the first terminal 122b of the driving subcircuit 122 is connected to the second node N2, and the second terminal 122c of the driving subcircuit 122 is connected to the third node N3.
  • the data writing sub-circuit 126 is connected to the driving sub-circuit 122 and configured to write a data signal into the first end 122b of the driving sub-circuit 122 in response to the first scanning signal.
  • the data circuit 126 includes a control terminal 126a, a first terminal 126b and a second terminal 126c, the control terminal 126a is configured to receive the first scanning signal Ga1, and the first terminal 126b is configured to receive the data signal Vd , the second terminal 126c is connected to the first terminal 122b of the driving sub-circuit 122 (that is, the second node N2).
  • the data writing sub-circuit 126 is configured to write the data signal Vd into the first end 122b of the driving sub-circuit 122 in response to the first scanning signal Ga1.
  • the first end 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd
  • the control end 126a is connected to the gate line 11 as a scan line to receive the first scan signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written into the first end 122b (second node N2) of the driving sub-circuit 122, And the data signal is stored, so that the driving current for driving the light-emitting element 120 to emit light can be generated according to the data signal during, for example, the light-emitting phase.
  • the compensation sub-circuit 128 is connected to the driving sub-circuit 122 and is configured to compensate the driving sub-circuit 122 in response to a second scan signal, which may be the same as or different from the first scan signal.
  • the compensation subcircuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c.
  • the control terminal 128a of the compensation subcircuit 128 is configured to receive the second scanning signal Ga2, and the compensation subcircuit 128
  • the first end 128b and the second end 128c are electrically connected to the second end 122c and the control end 122a of the driving sub-circuit 122 respectively, and the compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scanning signal Ga2 .
  • the pixel circuit further includes a storage subcircuit 127 , a first light emission control subcircuit 123 , a second light emission control subcircuit 124 , and a first reset subcircuit 125 and a second reset subcircuit 129 .
  • the first scan signal Ga1 may be the same as the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to the same signal output terminal.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through the same scan line.
  • the first scan signal Ga1 may also be different from the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines.
  • the storage sub-circuit 127 includes a first end (also called a first storage electrode) 127a and a second end (also called a second storage electrode) 127b, the first end 127a of the storage sub-circuit is configured to receive a first power supply voltage VDD, store The second terminal 127b of the subcircuit is electrically connected to the control terminal 122a of the driving subcircuit.
  • the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127;
  • the compensation subcircuit 128 can electrically connect the control terminal 122a of the driving subcircuit 122 to the second terminal 122c, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be correspondingly stored in the storage subcircuit, so that, for example, in In the light-emitting phase, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122, so that the output of the driving sub-circuit 122 is compensated.
  • the storage sub-circuit 127 is electrically connected to the control terminal 122 a of the driving sub-circuit 122 and the first voltage terminal VDD, and configured to store the data signal written by the data writing sub-circuit 126 .
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127 .
  • the compensation subcircuit 128 can electrically connect the control terminal 122a of the driving subcircuit 122 to the second terminal 122c, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be stored accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting phase, so that the output of the driving sub-circuit 122 is compensated.
  • the first light emission control subcircuit 123 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122 and the first voltage terminal VDD, and is configured to switch the first voltage terminal VDD to the first voltage terminal VDD in response to the first light emission control signal EM1
  • the first power supply voltage is applied to the first end 122b of the driving sub-circuit 122 .
  • the first light emission control sub-circuit 123 is connected to the first light emission control terminal EM1 , the first voltage terminal VDD and the second node N2 .
  • the second light emission control subcircuit 124 is connected to the second light emission control terminal EM2, the first terminal 134 of the light emitting element 120, and the second terminal 122c of the driving subcircuit 122, and is configured to make the driving current respond to the second light emission control signal. can be applied to the light emitting element 122 .
  • the second light-emitting control subcircuit 123 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can communicate with the light-emitting element 120 through the second light-emitting control subcircuit 123.
  • the second light-emitting control sub-circuit 123 is turned off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting element 120 and causing the It emits light, which can improve the contrast of the corresponding display device.
  • the second light emission control sub-circuit 124 can also be turned on in response to the second light emission control signal, so that the reset circuit can be combined to reset the driving sub-circuit 122 and the light emitting element 120 .
  • the second light emission control signal EM2 may be the same as the first light emission control signal EM1, for example, the second light emission control signal EM2 may be connected to the same signal output terminal as the first light emission control signal EM, for example, the second light emission control signal EM2 may It is transmitted through the same light emission control line as the first light emission control signal EM.
  • the second light emission control signal EM2 may be different from the first light emission control signal EM1 .
  • the second light emission control signal EM2 and the first light emission control signal EM1 may be respectively connected to different signal output terminals.
  • the second light emission control signal EM2 and the first light emission control signal EM1 may be respectively transmitted through different light emission control lines.
  • the first reset subcircuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the driving subcircuit 122, and is configured to apply the first reset voltage Vinit1 in response to the first reset control signal Rst1 to the control terminal 122a of the driving sub-circuit 122.
  • the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 122b (fourth node N4) of the light emitting element 122, and is configured to apply the second reset voltage Vinit2 in response to the second reset control signal Rst2 to the first end 134 of the light emitting element 120 .
  • the first reset voltage Vinit1 and the second reset voltage Vinit2 may be the same voltage signal or different voltage signals.
  • the first reset voltage terminal Vinit1 and the second reset voltage terminal Vinit2 are connected to the same reset voltage source terminal (eg located in the non-display area) to receive the same reset voltage.
  • the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2 respectively, so that the second reset voltage Vinit2 can be applied to the first node respectively.
  • N1 and the first reset voltage Vinit1 are applied to the first terminal 134 of the light-emitting element 120 , so that the driving sub-circuit 122 , the compensation sub-circuit 128 and the light-emitting element 120 can be reset to eliminate the influence of the previous light-emitting stage.
  • the second reset control signal Rst2 of each row of subpixels may be the same signal as the first scan signal Ga1 of the row of subpixels, and both may be transmitted through the same gate line 11 .
  • the first reset control signal Rst1 of each row of sub-pixels and the first scan signal Ga1 of the previous row of sub-pixels can be transmitted through the same gate line 11 .
  • the light emitting element 120 includes a first end (also referred to as a first electrode or a pixel electrode) 134 and a second end (also referred to as a second electrode) 135, the first end 134 of the light emitting element 120 is connected to the fourth node, and emits light.
  • the second terminal 135 of the element 120 is configured to be connected to the second voltage terminal VSS.
  • the second terminal 122c of the driving subcircuit 122 can be connected to the fourth node N4 through the second light emission control subcircuit 124 .
  • Embodiments of the present disclosure include, but are not limited to, this scenario.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent the actual components, but represent the relevant circuit connections in the circuit diagram. meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scanning signal and the second scanning signal.
  • the signal can also represent the first scanning signal terminal and the second scanning signal terminal, Rst1 and Rst2 can represent both the reset control terminal and the reset control signal, and the symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage
  • the terminal can also represent the first reset voltage and the second reset voltage
  • the symbol VDD can represent both the first voltage terminal and the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5A .
  • the pixel circuit includes: first to seventh transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 and a storage capacitor Cst.
  • the driving sub-circuit 122 can be implemented as a first transistor T1 (ie, a driving transistor).
  • the gate of the first transistor T1 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the first transistor T1 serves as the second terminal 122c of the driving sub-circuit 122, and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first pole of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal , the second pole of the second transistor T2 is connected to the first terminal 122b (second node N2 ) of the driving sub-circuit 122 .
  • the compensation sub-circuit 128 may be implemented as a third transistor T3 (ie, a compensation transistor).
  • the gate, the first pole and the second pole of the third transistor T3 serve as the control terminal 128a, the first terminal 128b and the second terminal 128c of the compensation sub-circuit respectively.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (second scan signal terminal Ga2) to receive the second scan signal, and the first pole of the third transistor T3 is connected to the second terminal 122c of the driving sub-circuit 122 (the second terminal 122c of the driving sub-circuit 122 ).
  • the storage sub-circuit 127 can be implemented as a storage capacitor Cst, the storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb, the first capacitor electrode Ca is connected to the first voltage terminal VDD, The second capacitive electrode Cb is connected to the control terminal 122 a of the driving sub-circuit 122 .
  • the first light emission control sub-circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first light emission control line (the first light emission control terminal EM1) to receive the first light emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, the second pole of the fourth transistor T4 is connected to the first terminal 122b (second node N2 ) of the driving sub-circuit 122 .
  • the light emitting element 120 is embodied as a light emitting diode (LED), such as an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED) or an inorganic light emitting diode, such as a micro light emitting diode (Micro LED) or a micro OLED.
  • LED light emitting diode
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • an inorganic light emitting diode such as a micro light emitting diode (Micro LED) or a micro OLED.
  • the light emitting element 120 may be a top emission structure, a bottom emission structure or a double-side emission junction.
  • the light emitting element 120 can emit red light, green light, blue light or white light and the like.
  • the embodiments of the present disclosure do not limit the specific structure of the light emitting element.
  • the light-emitting element 120 includes a first electrode 134, a second electrode 135, and an organic functional layer sandwiched between the first electrode 134 and the second electrode 135.
  • the organic functional layer includes a light-emitting layer.
  • Layers may also include hole injection layers, hole transport layers, electron injection layers, electron transport layers, and the like.
  • the first electrode 134 also called pixel electrode, such as an anode
  • the first electrode 134 also called pixel electrode, such as an anode
  • the second electrode 135 (for example, cathode) of 120 is configured to be connected to the second voltage terminal VSS to receive the second power supply voltage VSS, and the circuit flowing from the second terminal 122c of the driving sub-circuit 122 into the light emitting element 120 determines the brightness of the light emitting element.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second voltage supply voltage VSS may be a negative voltage.
  • the second light emission control sub-circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second light emission control line (the second light emission control terminal EM2) to receive the second light emission control signal, and the first pole of the fifth transistor T5 is connected to the second terminal 122c of the driving sub-circuit 122 (the second light emission control terminal EM2).
  • the three nodes N3) are connected, and the second pole of the fifth transistor T5 is connected to the first end 134 of the light emitting element 120 (the fourth node N4).
  • the first reset sub-circuit 125 can be implemented as a sixth transistor T6, and the second reset sub-circuit can be implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, and the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1,
  • the second pole of the sixth transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2,
  • the second pole of the seventh transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage )
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage voltage).
  • the first to seventh transistors T1 - T7 are all P-type transistors, such as low temperature polysilicon thin film transistors.
  • the embodiment of the present disclosure does not limit the type of the transistor, and when the type of the transistor changes, it is only necessary to adjust the connection relationship in the circuit accordingly.
  • the display process of each frame of image includes three stages, which are initialization stage 1 , data writing and compensation stage 2 and light emitting stage 3 .
  • the first scan signal Ga1 and the second scan signal Ga2 use the same signal
  • the first light emission control signal EM1 and the second light emission control signal EM2 use the same signal
  • the waveforms of Rst2 and the first scanning signal Ga1/second scanning signal Ga2 are the same, that is, the second reset control signal Rst2, the first scanning signal Ga1/second scanning signal Ga2 can use the same signal; the first reset of the sub-pixels in this row
  • the waveform of the signal Rst1 is the same as that of the first scanning signal Ga1/second scanning signal Ga2 of the sub-pixels in the previous row, that is, the same signal is used.
  • this is not a limitation to the present disclosure.
  • different signals may be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, respectively.
  • Different signals are used as the first light emission control signal EM1 and the second light emission control signal EM2 respectively.
  • the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.
  • the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vd is written into the second node by the second transistor T2 N2, and charge the first node N1 through the first transistor T1 and the third transistor T3, until the potential of the first node N1 changes to Vd+Vth, the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1.
  • the potential of the first node N1 is stored and maintained in the storage capacitor Cst, that is to say, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide gray display data and compensate the threshold voltage of the first transistor T1 itself.
  • the second reset control signal Rst2 can also be input to turn on the seventh transistor T7, and apply the second reset voltage Vinit2 to the fourth node N4, thereby resetting the fourth node N4.
  • the reset of the fourth node N4 can also be performed in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 can be the same. Embodiments of the present disclosure do not limit this.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5 and the first transistor T1, and the fifth transistor T5 applies a driving current to the OLED to make it emit light .
  • the value of the driving current I flowing through the OLED can be obtained according to the following formula:
  • Vth represents the threshold voltage of the first transistor T1
  • VGS represents the voltage between the gate and the source (here, the first pole) of the first transistor T1
  • K is a value related to the first transistor T1 itself. constant value.
  • the structure of the display substrate provided by at least one embodiment of the present disclosure is exemplarily described below by taking the pixel circuit shown in FIG. 5B as an example and in conjunction with FIGS. 6A-6B, 7, 8A-8C, 9A-9C and 10A. .
  • FIG. 6A is a schematic diagram of a display substrate 20 provided by at least one embodiment of the present disclosure
  • FIG. 6B is a cross-sectional view of FIG. 6A along the section line A-A'. It should be noted that, for the sake of clarity, FIG. 6B omits some structures that do not have a direct electrical connection relationship at the cross-hatching; for the convenience of comparison, the position of the cross-hatching line A-A' is also shown in FIGS. 8B and 9B.
  • the display substrate 20 includes a base substrate 100 on which a plurality of sub-pixels P are located.
  • the pixel circuits of the plurality of sub-pixels P are arranged as a pixel circuit array, for example, the row direction of the pixel circuit array is the first direction D1, and the column direction is the second direction D2.
  • the pixel circuits of each sub-pixel may have exactly the same structure, that is, the pixel circuits are repeatedly arranged in the row and column directions.
  • the arrangement rule of the pixel circuit of the sub-pixel and the arrangement rule of the pixel electrode above it may be the same or different.
  • the arrangement rule of the sub-pixel here is The description refers to the arrangement rules of the pixel circuits, and the description of the relative positional relationship of the sub-pixels refers to the relative positions of the pixel circuits of the sub-pixels, for example, adjacent sub-pixels refer to sub-pixels adjacent to the pixel circuits. The following embodiments are the same as this and will not be repeated here.
  • the semiconductor layer 102, the insulating layer 401, the conductive layer 501, the insulating layer 402, the conductive layer 502, the insulating layer 403, the conductive layer 503, the insulating layer 404, and the conductive layer 504 are sequentially arranged on the base substrate 100. , so as to form the structure of the display substrate as shown in FIG. 6A .
  • Fig. 7 corresponds to Fig. 6A and schematically shows the semiconductor layer 102 and the conductive layer 501
  • Fig. 8A and Fig. 8C show the pattern of the conductive layer 502
  • Fig. 8B shows the conductive layer 502 on the basis of Fig. 7
  • Fig. 9A shows 9B shows the conductive layer 503 on the basis of FIG. 8B
  • FIG. 10A shows the conductive layer 504 .
  • Tng, Tns, Tnd, and Tna are respectively used to denote the gate, first electrode, second electrode and channel region of the nth transistor Tn in the following description, wherein n is 1-7.
  • the “same-layer arrangement” referred to in this disclosure means that two (or more than two) structures are formed through the same deposition process and patterned through the same patterning process, and are not necessarily located same level; their materials may be the same or different.
  • the "integrated structure” in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process to form interconnected structures, and their materials may be the same or different .
  • the conductive layer 501 includes the gate of each transistor and some scan lines and control lines.
  • the semiconductor layer 102 includes active layers T1a-T7a of the first to seventh transistors T1-T7. As shown in FIG. 7, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integral structure.
  • the semiconductor layer 102 in each column of sub-pixels is an integral structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.
  • the conductive layer 501 includes gates T1g-T7g of the first to seventh transistors T1-T7.
  • the display substrate 20 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to perform conductorization treatment (such as doping treatment) on the semiconductor layer 102, so that the semiconductor layer 102 is not covered by the first conductive layer 201
  • the covered part is conductorized, so that the parts of the active layer of each transistor located on both sides of the channel region are conductorized to form the first pole and the second pole of the transistor respectively.
  • the third transistor T3 and the sixth transistor T6 respectively adopt a double-gate structure, including a first gate and a second gate, which can improve the gate control capability of the transistors and reduce leakage current. Since both the third transistor T3 and the sixth transistor T6 are transistors directly connected to the gate (ie, the first node N1) of the first transistor T1 (ie, the driving transistor), the third transistor T3 and the sixth transistor The stability of T6 directly affects the stability of the gate (N1 node) voltage of the first transistor T1.
  • the double-gate structure is used to improve the gate control capability of the third transistor T3 and the sixth transistor T6, which helps to reduce the leakage current of the transistors and thus helps to maintain the voltage of the N1 node, so that in the compensation stage, the threshold voltage of the first transistor T1 has a certain value. Helps to get full compensation, and then improves the display uniformity of the display substrate in the light-emitting stage.
  • the third transistor T3 includes a first gate T3g1 and a second gate T3g2, and a first channel region and a second channel respectively corresponding to the first gate g1 and the second gate T3g2 area; that is, the active layer of the third transistor includes a first part, a second part and a third part, and the orthographic projection of the first part on the base substrate is the same as the orthographic projection of the first gate T3g1 on the base substrate Overlapping, the orthographic projection of the second portion on the base substrate overlaps with the orthographic projection of the second grid T3g1 on the base substrate.
  • the first gate T3g1 is located on the main body of the scan line 220 controlling the third transistor T3, and the second gate T3g2 is a protrusion protruding from the main body of the scan line 220 along the second direction D2.
  • the active layer of the third transistor T3 also includes a third portion (an example of the disclosed semiconductor pattern), the third portion is located between the first portion and the second portion of the active layer and connects the first portion and the second portion , the third portion is located between the first gate T3g1 and the second gate T3g2, and is conductorized into a conductive region T3c because it is not shielded by the gate pattern.
  • the conductive region T3c is separated from the first pole T3s of the third transistor T3 by the first channel region of the third transistor T3, and the conductive region T3c is separated from the second pole T3d of the third transistor T3 by the third transistor T3
  • the second channel region of the third transistor T3 is spaced apart from each other, and the conductive region T3c is integrated with the first channel region and the second channel region of the third transistor T3, for example, they all include polysilicon material.
  • the sixth transistor T6 also includes a conductive region T6c located between the first gate T6g1 and the second gate T2g.
  • the first conductive layer 201 further includes a plurality of scan lines 210 , a plurality of reset control lines 220 and a plurality of light emission control lines 230 which are insulated from each other. These signal lines can all be examples of the gate lines 11 shown in FIG. 4 .
  • the scanning line 210 is electrically connected to the gate T2g of the second transistor T2 in the corresponding row of sub-pixels (or an integrated structure) to provide the first scanning signal Ga1, and the reset control line 220 is connected to the sixth transistor T6 in the corresponding row of sub-pixels.
  • the gate T6g of the sub-pixel is electrically connected to provide the first reset control signal Rst1
  • the emission control line 230 is electrically connected to the gate T4g of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide the second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 may be the same signal;
  • the control line 230 is also electrically connected to the gate T5g of the fifth transistor T5 to provide a second light emission control signal EM2, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal.
  • the first gate T3g1 extends along the first direction D1 and is a part of the scan line 210 .
  • the second gate T3g2 extends along the second direction D2 and is an extension of the scan line 210 extending along the second direction D2.
  • the gate of the seventh transistor T7 of the pixel circuit in this row is connected to the pixel circuit in the next row (that is, according to the scanning order of the scanning lines, the pixel circuit row where the scanning lines that are sequentially turned on after the scanning lines in this row are located) ) corresponding to the reset control line 220 is electrically connected to receive the second reset control signal Rst2.
  • the conductive layer 502 includes a first capacitive electrode Ca.
  • the first capacitor electrode Ca overlaps the gate T1g of the first transistor T1 in a direction perpendicular to the base substrate 100 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the first storage capacitor Cst.
  • the first capacitive electrode Ca includes an opening 222 , and the opening 222 exposes at least part of the gate T1g of the first transistor T1 , so as to facilitate the electrical connection of the gate T1g to other structures.
  • the first capacitive electrodes Ca of sub-pixels located in the same pixel row are connected to each other as an integral structure.
  • the conductive layer 502 may further include a plurality of reset voltage lines 240 extending along the first direction D1, and the plurality of reset voltage lines 240 are connected to multiple rows of sub-pixels in one-to-one correspondence.
  • the reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in a corresponding row of sub-pixels to provide a first reset voltage Vinit1.
  • the first electrode of the seventh transistor T7 in this row of sub-pixels is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels to receive the second reset voltage Vinit2 .
  • the reset voltage line 240 corresponding to the next row of sub-pixels to receive the second reset voltage Vinit2 .
  • the conductive layer 502 may further include a shielding electrode 221 .
  • the shielding electrode 221 overlaps the first terminal T2s of the second transistor T2 in a direction perpendicular to the base substrate 100 so as to protect the signal in the first terminal T2s of the second transistor T2 from being interfered by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display gray scale of the sub-pixel, the shielding electrode 221 improves the stability of the data signal, thereby improving the display quality. performance.
  • the shielding electrode 221 also at least partially overlaps with the second pole T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 100, so as to improve the stability of the signal on the second pole T6d. Therefore, the stability of the sixth transistor T6 is improved, and the gate voltage of the first transistor T1 is further stabilized.
  • the shielding electrode 221 also extends to the subpixel adjacent to the subpixel to which the shielding electrode 211 belongs in the first direction D1 and is electrically conductive with the third transistor T3 in the adjacent subpixel.
  • the region T3c at least partially overlaps in a direction perpendicular to the base substrate 100 to improve the stability of the signal in the conductive region T3c, thereby improving the stability of the third transistor T3 and further stabilizing the gate voltage of the first transistor T1.
  • the first shielding portion 221a of the shielding electrode 221 includes a first sub-portion a1 and a second sub-portion a2, and the orthographic projection of the first sub-portion a1 on the base substrate is the same as that of the second sub-pixel of the adjacent sub-pixel.
  • the orthographic projections of the conductive region T3c of the three transistors on the substrate overlap, the orthographic projection of the second sub-part a2 on the substrate does not overlap with the orthographic projection of the conductive region T3c on the substrate, the first The size of the sub-portion conductive region T31 in the second direction D2 is larger than the size of the second sub-portion a2 in the second direction. This setting can contribute to the shielding area and shielding effect of the first subsection a1.
  • the shielding electrode 221 forms a stable capacitor with the first pole T2s of the second transistor T2 and the second pole T6d of the sixth transistor T6 facing (overlapping) it.
  • the shielding electrode 221 is configured to load a fixed voltage. Since the voltage difference across the capacitor cannot change abruptly, the first pole T2s of the second transistor T2, the conductive region T3c of the third transistor T3, and the second pole T6d of the sixth transistor T6 are improved.
  • the stability of the upper voltage For example, the shielding electrode 221 is electrically connected to the power line 250 in the conductive layer 503 to be loaded with the first power voltage VDD.
  • the shielding electrode 221 is L-shaped, V-shaped or T-shaped. As shown in FIG. 8A , the shielding electrode 221 is L-shaped and includes a first shielding portion 221a and a second shielding portion 221b extending in different directions.
  • the second shielding portion 221b at least partially overlaps with the second pole T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 100; the first shielding portion 221a is respectively connected to the first pole T2s and adjacent
  • the conductive region T3c of the third transistor T3 in the sub-pixel at least partially overlaps in a direction perpendicular to the base substrate 100 so as to form a shield on the conductive region T3 to improve the stability of the transistor.
  • the second shielding portion 221b extends along the second direction D2, and the first shielding portion 221a extends along the first direction D1.
  • FIG. 8C is a schematic plan view of another example of the conductive layer 502 .
  • the second shielding portion 221b of the shielding electrode 221 extends from the first capacitive electrode Ca along the second direction D2, and the first shielding portion 221a extends from the second shielding portion 221b along the first direction D1.
  • the second shielding portion 221b extends downward to the first capacitive electrode Ca and is integrally connected with the first capacitive electrode Ca.
  • the position where the first shielding part is connected to the second shielding part is located in the middle of the second shielding part in the second direction, that is, the shielding electrode is T-shaped.
  • the conductive layer 503 includes a plurality of power supply lines 250 extending along the second direction D2 , and the plurality of power supply lines 250 are connected to the first voltage terminal VDD to transmit the first power supply voltage VDD.
  • the plurality of power supply lines 250 are electrically connected to the columns of sub-pixels in one-to-one correspondence to provide the first power supply voltage VDD.
  • the power line 250 is electrically connected to the first capacitor electrode Ca in a corresponding column of sub-pixels through the via hole 342 , and is electrically connected to the first electrode T4s of the fourth transistor T4 through the via hole 343 .
  • the power line 250 is also electrically connected to the shielding electrode 221 through the via hole 341 , so that the shielding electrode 221 has a fixed potential and improves the shielding ability of the shielding electrode.
  • the via hole 342 and the via hole 341 both penetrate the third insulating layer 303
  • the via hole 343 penetrates the insulating layer 401 , the insulating layer 402 and the insulating layer 403 .
  • the conductive layer 503 further includes a plurality of data lines 12 extending along the second direction D2.
  • the multiple data lines 12 are electrically connected to multiple columns of sub-pixels in one-to-one correspondence to provide the data signal Vd.
  • the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in a corresponding column of sub-pixels through the via hole 346 to provide the data signal.
  • the via hole 346 runs through the insulating layer 401 , the insulating layer 402 and the insulating layer 403 . For example, as shown in FIGS.
  • the conductive layer 503 further includes a connection electrode 231, and one end of the connection electrode 231 passes through the opening 222 in the first capacitor electrode Ca and the via hole 344 in the insulating layer and
  • the gate T1g of the first transistor T1 is electrically connected to the second capacitor electrode Cb, and the other end is electrically connected to the second pole T3d of the third transistor T3 through the via hole 345, so that the second capacitor electrode Cb is connected to the second capacitor electrode Cb.
  • the second poles T3d of the three transistors T3 are electrically connected.
  • the via hole 344 runs through the insulating layer 402 and the insulating layer 403 .
  • the via hole 345 runs through the insulating layer 401 , the insulating layer 402 and the insulating layer 403 .
  • the orthographic projection of the connection electrode 231 on the base substrate and the orthographic projection of the second shielding portion 221b of the shielding electrode 221 on the base substrate at least partially overlap in the first direction D1, that is, along the Viewed from the first direction D1, the orthographic projection of the connecting electrode 231 and the orthographic projection of the second shielding portion 221b at least partially overlap.
  • the shielding and protection effect of the second shielding portion on the connection electrode 231 can be effectively improved, for example, part of the abrupt signal can be shielded, so as to prevent the sudden signal from affecting the potential of the connecting electrode 231 and further affecting the potential of the gate of the driving transistor.
  • the orthographic projection of the second shielding portion 221b on the base substrate is located between the orthographic projection of the connection electrode 231 on the base substrate and the orthographic projection of the data line 12 on the base substrate, so that The second shielding portion 221b can shield the sudden signal of the data line 12 and reduce the impact of the sudden signal on the potential of the connecting electrode 231 .
  • the orthographic projection of the connection electrode 231 on the base substrate is located in the second direction D2 on the orthographic projection of the integrated structure formed by the first capacitive electrode Ca and the shielding electrode 221 on the base substrate. within the range.
  • the shielding electrode 221 has the structure shown in FIG. 8C
  • the shielding electrode 221 and the first capacitive electrode Ca together form a shielding wall, which can effectively improve the signal shielding and protection of the connection electrode 231 .
  • the conductive layer 503 further includes a connecting electrode 232, which is electrically connected to the second pole T5d of the fifth transistor T5 through the via hole 349, and is used to connect the The second electrode T5d of the fifth transistor T5 is electrically connected to the pixel electrode 134 of the light emitting element through the via hole 350 .
  • the via hole 349 runs through the insulating layer 401 , the insulating layer 402 and the insulating layer 403 .
  • the conductive layer 503 further includes a connection electrode 233, one end of the connection electrode 233 is electrically connected to the reset voltage line 240 through the via hole 348, and the other end is connected to the sixth transistor T6 through the via hole 347.
  • the first pole T6s is electrically connected so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240 .
  • the via hole 348 penetrates through the insulating layer 403 .
  • the via hole 347 penetrates through the insulating layer 401 , the insulating layer 402 and the insulating layer 403 .
  • the semiconductor layer 102 includes a connecting portion 104, which becomes a conductor after being conductorized, and the connecting portion connects the reset voltage line 240 (an example of the first reset voltage line in the present disclosure) It is electrically connected with the first pole T6s of the reset transistor (that is, the sixth transistor T6) in the sub-pixel.
  • This arrangement can eliminate the arrangement of the connecting electrodes 232 and the via holes 347 , thereby simplifying the design.
  • the orthographic projection of the connecting portion on the base substrate overlaps the orthographic projection of the reset voltage line 240 on the base substrate and the orthographic projection of the first pole T6s of the reset transistor on the base substrate.
  • the first electrode of the seventh transistor T7 in the upper row of sub-pixels is electrically connected to the first electrode of the sixth transistor T6 in the current row of sub-pixels, and corresponds to the first electrode of the current row of sub-pixels.
  • the reset voltage line 240 (that is, the uppermost reset voltage line 240 in FIG. 9B ) is electrically connected to receive the second reset voltage Vinit2, and the first electrode of the seventh transistor T7 in this row of sub-pixels is connected to the next row of sub-pixels
  • the first electrode of the sixth transistor T6 is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels (that is, the reset voltage line 240 in the middle of FIG. 9B ) to receive the second reset voltage Vinit2.
  • the conductive layer 503 further includes a plurality of reset voltage lines 260 extending along the second direction D2. As shown in FIG. 9B, each reset voltage line 260 is electrically connected to the reset voltage line 240 in the conductive layer 502 through the via hole 351, thereby forming a horizontal and vertical meshed conductive structure, which can reduce resistance, thereby Reducing the voltage drop helps to uniformly transmit the reduced reset voltage to each sub-pixel on the substrate.
  • the reset voltage lines 260 are not arranged in one-to-one correspondence with sub-pixel columns, which can reduce wiring density.
  • the reset voltage line 260 and the power supply line 250 are respectively directly adjacent to the data line 12, and are respectively located on both sides of the data line 12.
  • the reset voltage line 260 Located on the side of the data line 12 away from the sub-pixel column electrically connected to the data line 12 .
  • the conductive layer 504 includes the first electrode (that is, the pixel electrode) 134 of the light emitting element.
  • the first electrode 134 of the light emitting element of each sub-pixel is electrically connected to the connection electrode 232 in the sub-pixel through the via hole 350 , and thus is electrically connected to the second electrode T5d of the fifth transistor T5 through the connection electrode 233 .
  • the via hole 350 penetrates through the insulating layer 504 , for example.
  • FIG. 10A schematically shows the contact area of the first electrode 134 in contact with the via hole 350 with a circle.
  • the display substrate 20 may further include a pixel defining layer 405 on the first electrode of the light emitting element.
  • An opening is formed in the pixel defining layer 405 to expose at least part of the pixel electrode 134 to define the pixel opening area (ie, the effective light emitting area) 600 of each sub-pixel of the display substrate.
  • the organic functional layer 136 of the light emitting element 120 is formed at least in the opening, and the second electrode 135 is formed on the organic functional layer 136 to form the light emitting element 120 .
  • the second electrode 135 is a common electrode, and is arranged on the entire surface of the display substrate 20 .
  • the first electrode 134 is the anode of the light emitting element
  • the second electrode 135 is the cathode of the light emitting element.
  • FIG. 10A schematically shows the pixel opening area 600 of each sub-pixel with a rectangle, but this is not intended to limit the present disclosure.
  • the conductive layer 504 may further include a plurality of reset voltage lines 270 extending along the first direction D1.
  • the reset voltage lines 270 are, for example, in a zigzag structure, such as Z-shaped extending along the first direction D1. The purpose is to match the shape of the first electrode 134 so as to facilitate wiring.
  • the reset voltage line 270 is connected in parallel with the reset voltage line 260 and/or the reset voltage line 240 to further reduce the resistance of the reset voltage line so as to reduce the voltage drop on the reset voltage line.
  • the reset voltage line 270 is electrically connected to the reset voltage line 260 and/or the reset voltage line 240 in the non-display area.
  • the reset voltage line 270 is not essential.
  • FIG. 10B is a distribution diagram of the first electrode 134 of the light emitting element provided by other embodiments of the present disclosure
  • FIG. 10C shows the connection relationship between the first electrode and the underlying pixel circuit.
  • every four first electrodes 134 form an electrode group, and the four first electrodes 134 in the electrode group respectively correspond to 1 blue pixel, 1 red pixel and 2 green pixels, and the 2 green pixels
  • the pixels are arranged oppositely in the first direction, and the blue pixel and the red pixel are arranged oppositely in the second direction.
  • the via hole 350 of the red pixel does not overlap with the corresponding via hole 349 in a direction perpendicular to the base substrate.
  • the two green pixels have the same shape and area, and the blue, green, and red pixels have different areas.
  • the least efficient blue subpixel has the largest area and the most efficient red subpixel has the smallest area for better color intensity and image clarity.
  • each conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and combinations of the above metals. Alloy materials; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.; or a multilayer metal stack structure; or metal Laminated structure with conductive metal oxides.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the conductive layer 504 includes a stack structure of TI/AL/TI.
  • the material of the conductive layer 505 is a transparent conductive material, such as a metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO) and the like.
  • a metal oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO) and the like.
  • the conductive layer 505 includes a stacked structure of ITO/AG/ITO.
  • the light emitting element 120 has a top emission structure
  • the first electrode (ie, the pixel electrode) 134 is reflective
  • the second electrode 135 is transmissive or semi-transmissive.
  • the first electrode 134 is an anode
  • the second electrode 135 is a cathode.
  • the first electrode 134 is an ITO/Ag/ITO laminated structure
  • the transparent conductive material ITO is a material with a high work function, and direct contact with the luminescent material can improve the hole injection rate
  • the metal material Ag helps to improve the first electrode.
  • Reflectivity
  • the second electrode 135 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag/Mg alloy material.
  • each insulating layer is, for example, an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • Metal oxynitride insulating material such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • Metal oxynitride insulating material such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • the material of the pixel defining layer 405 is an organic material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • organic material such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • the base substrate 100 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC) etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polysulfone
  • the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , polythiophene, etc.).
  • the display substrate 20 includes the structure shown in FIG. 2.
  • the connection structure shown in FIG. This is not intended as a limitation of the present disclosure.
  • connection electrode 232 (an example of the first conductive structure of the present disclosure) includes a bottom surface 232a close to the base substrate, a top surface 232b away from the base substrate, and a top surface 232b located on the bottom surface 232a and the top surface 232b. between the first side surface 232c.
  • the connecting electrode 232 is electrically connected to the first electrode 314 of the light emitting element (an example of the second conductive structure in the present disclosure) through the via hole 350 (an example of the first via hole in the present disclosure).
  • the via hole 350 and the via hole 349 at least partially overlap in a direction perpendicular to the base substrate, so that the insulating layer 404 (an example of the second insulating layer in the present disclosure) is recessed downward,
  • the via hole 350 exposes at least part of the first side surface 232c of the connection electrode 232, and makes the first electrode 314 of the light emitting element recess downward and includes a protrusion 314a (an example of a first protrusion in the present disclosure), which 314 a is in contact with at least a portion of the first side surface 232 c, covering the portion of the first side surface 232 c exposed by the via hole 350 .
  • connection electrode 232 and the portion of the first electrode 134 in direct contact with the connection electrode 232 are located between the signal lines on both sides.
  • the protruding portion 314a is located between the signal lines on both sides of the pixel column where the sub-pixel is located (an example of the first pixel column in the present disclosure), that is, the first signal line on the left side.
  • the first signal line is, for example, the data line 12 or the power line 250 connected to the sub-pixel
  • the second signal line is, for example, the reset voltage line 260 on the right
  • the data line 12 or the power supply line 250, the data line 12 and the power supply line 250 on the right side are connected to the pixel column adjacent to the pixel column (an example of the second pixel column in the present disclosure)
  • the orthographic projection on 100 is located between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate.
  • the orthographic projection of the first electrode 134 of the light-emitting element of the first pixel column on the base substrate is respectively the orthographic projection of the power line 250 on the left and the data line on the right.
  • the orthographic projections of 12 on the substrate substrate are at least partially overlapping.
  • the orthographic projection of the electrodes of the light-emitting elements of the first pixel column on the side of the base substrate close to the base substrate is the same as that of the first signal line on the base substrate.
  • the orthographic projection of and the orthographic projection of the second signal line on the base substrate are at least partially overlapped respectively.
  • the protruding portion 134a of the first electrode 134 By setting the protruding portion 134a of the first electrode 134 in contact with the first side surface 232c of the connection electrode 232, not only the contact area between the first electrode 134 and the connection electrode 232 is increased, the contact resistance between the two is reduced, and the contact resistance between the two is effectively improved.
  • the longitudinal cross-sectional area of the first electrode 134 is reduced, and the protruding portion 134a is disposed between the first signal line and the second signal line, and the mutual interference between the first signal line and the second signal line can also be reduced.
  • the protrusion 134a can reduce the interference of the data line 12 on one side to the signal in the signal line (such as data line, power line, reset voltage line, etc.) on the other side.
  • the structure shown in FIG. 2 can be regarded as a part of the cross-sectional structure of the substrate 20 along the section line AA', that is, the structure encircled by a dotted line in FIG. 6B, and the structure shown in FIG. 6B
  • the connection electrode 232, the first electrode 134, the protruding portion 134a, the via hole 350, and the via hole 349 can be regarded as the first conductive structure 21, the second conductive structure 22, the protruding portion 220, the via hole V1, and the depression in FIG. 2, respectively.
  • Structure G1 The description of FIG. 2 is also applicable to FIG. 6B , and details are not repeated here.
  • connection electrode 232 includes a protruding portion 232t facing the via hole 349 , and the orthographic projection of the protruding portion 232t on the base substrate is located within the orthographic projection of the via hole 349 on the base substrate.
  • the orthographic projection of the protruding portion 134a on the base substrate and the orthographic projection of the left power line 250 (an example of the first signal line in the present disclosure) on the base substrate are in the reference direction F (for example, The distance in the first direction D1) is l, and the reference direction F is parallel to the board surface of the base substrate, for example, parallel to the first direction D1.
  • the lowest point of the protruding portion 134a may be taken for measurement during measurement.
  • the distance between the orthographic projection of the right data line 12 (an example of the second signal line of the present disclosure) on the substrate and the orthographic projection of the power line 250 on the substrate in the first reference direction F is m.
  • the dimension of the connection electrode 232 located on the side of the insulating layer 403 away from the base substrate in the direction perpendicular to the base substrate is e, and the first side surface 232c is covered by the protruding portion
  • the portion 134a clad has a dimension d in a direction perpendicular to the base substrate. For example, l/m>0.9(d/e). For example, l/m>1.2*(d/e).
  • the orthographic projections of the plurality of pixel opening regions 600 on the base substrate are separated from the orthographic projections of the protrusions 134a on the base substrate, that is, they do not overlap, thereby avoiding the protrusion 134a
  • the disposition of the luminescent material in the effective luminescent area causes unevenness of the luminescent material, resulting in display defects such as color shift.
  • Fig. 11 is a schematic diagram of a display substrate provided by another embodiment of the present disclosure, which shows the orthographic projections of the conductive layer 504, the via holes 349, and the via holes 350 on the base substrate, which are schematically shown by hollow circles. Out of via 350, via 349 is shown with a solid circle.
  • the insulating layer 403 includes a plurality of via holes 349 corresponding to a plurality of sub-pixels, and the plurality of via holes 349 are arranged in a plurality along the first direction D1 and the second direction D2. Via rows and multiple via columns.
  • the insulating layer 404 includes a plurality of via holes 350 , the plurality of via holes 350 correspond to the plurality of sub-pixels, and are arranged in a one-to-one correspondence with the plurality of via holes 349 .
  • the plurality of via holes 349 are arranged in a plurality of via hole rows and a plurality of via hole columns along the first direction D1 and the second direction D2.
  • the overlapping conditions of the via 349 and the via 350 are different in each sub-pixel.
  • the orthographic projections of the via hole 349 and the via hole 350 on the base substrate do not overlap, so the structure shown in FIG. 2 or FIG. 6B cannot be formed.
  • each row of sub-pixels there are three consecutive adjacent sub-pixels with the structure shown in Figure 2 or Figure 6B for every other sub-pixel; There are 3 continuous via holes 350, and each of the 3 via holes 350 overlaps with the corresponding via hole 349 in a direction perpendicular to the base substrate, and forms a structure as shown in FIG. 2 or FIG. 6B; the 1 Each via hole 350 does not overlap with the corresponding via hole 349 in the direction perpendicular to the base substrate.
  • the 1 via corresponds to a red pixel.
  • multiple columns of sub-pixels include a pixel column, and each sub-pixel in the pixel column has a structure as shown in FIG. 2 or FIG. 6B (the first, third, fourth, and fifth columns of sub-pixels as shown in FIG. Or every other sub-pixel has a sub-pixel with the structure shown in FIG. 2 or FIG. 6B; that is, there is a column of via holes 350, and each via hole 350 and the corresponding via hole 349 are in a direction perpendicular to the substrate. 2 or 6B; or every other via hole 350, there is a via hole 350 overlapping with the corresponding via hole 349 in the direction perpendicular to the base substrate, and forming The structure shown in Figure 2 or Figure 6B.
  • FIGS. 12A-12C are schematic diagrams of display substrates provided by other embodiments of the present disclosure, in which the orthographic projections of the conductive layer 504, the pixel defining layer 405, the via holes 349, and the via holes 350 on the base substrate are shown. Vias 350 are schematically shown with open circles and vias 349 are shown with solid circles.
  • the pixel defining layer 405 includes a plurality of pixel opening regions 600 and non-opening regions. thickness.
  • the raised portion 405a can support the mask plate during evaporation. In some examples, the raised portion is also referred to as a spacer.
  • the raised portion is tapered, and the bottom and top of the raised portion 405a are schematically shown on the substrate substrate with a hollow ellipse and a solid ellipse, respectively, in Figures 12A-12C orthographic projection of .
  • the orthographic projection of the via hole 350 on the base substrate is separated from the orthographic projection of the part of the pixel defining layer with the maximum thickness on the base substrate (that is, the orthographic projection of the top of the raised portion 405a), that is, Do not overlap.
  • This arrangement can prevent the arrangement of the via hole 350 from adversely affecting its supporting function caused by the unevenness of the top of the raised portion 405a.
  • the unevenness of the protruding portion 405a may cause the mask plate to tilt, thereby affecting the unevenness of the organic functional layer (including the light emitting layer) formed by evaporation.
  • the protrusions 405a can have different disposition densities. For example, one (as shown in FIG. 12A ), two (as shown in FIG. 12B ) or three (as shown in FIG. 12C ) protrusions 405 a may be provided around one pixel opening region 600 .
  • the arrangement density of the protrusions can be determined according to the gap between the first electrodes 134 , and a higher density can improve the support stability of the mask.
  • three raised portions 405a are provided around the pixel opening area 600, which are the first raised portion 405a1, the second raised portion 405a2, and the third raised portion 405a3.
  • the first raised portion 405a1, the second protruding portion 405a2 and the third protruding portion 405a3 are arranged around the pixel opening area 600, and the line connecting the center of the orthographic projection on the base substrate forms a triangle.
  • the first raised portion 405a1 is located between four adjacent pixel opening regions 600, and the second raised portion 405a2 and the third raised portion 405a3 are respectively located between two adjacent pixel openings. between districts.
  • the area of the orthographic projection of the first protruding portion 405a1 on the base substrate is larger than the area of the orthographic projection of the second protruding portion 405a2 on the base substrate and the orthographic area of the third protruding portion 405a3 on the base substrate. projected area.
  • the display substrate also includes a dummy area (dummy area), such as the first column of sub-pixels from the left in FIG. 9D.
  • the setting of the pixel structure in the dummy area is basically the same as that of the display area.
  • the main difference is that No light-emitting element is set in the virtual area, and there is no first electrode 134 (that is, the second conductive structure), that is, in this column of sub-pixels, the orthographic projection of the first conductive structure on the base substrate is the same as the first electrode 134 on the base substrate.
  • the orthographic projection of the two conductive layers on the base substrate is separated.
  • the setting of the virtual area is to improve the uniformity of the process.
  • connection electrode 232 ie, the first conductive structure in the dummy area is arranged in the same way as in the effective display area, and the connection method of the connection electrode 232 is also the same as in the effective display area, and will not be repeated here.
  • the data line (one of the third signal line of the present disclosure) correspondingly connected to the subpixel column in the virtual area (an example of the third pixel column in the present disclosure, the first column of subpixels from the left in FIG. 9D ) example) and the power line (an example of the fourth signal line in the present disclosure) are electrically connected to each other, that is, the two signal lines provide the same signal, such as a power supply voltage signal, and are located on the same side of the pixel column. Since there is no signal interference problem in the dummy area, there is no need to set the protrusion of the first electrode 134 for shielding.
  • the following uses the pixel circuit shown in FIG. 5B as an example, and in combination with FIGS.
  • the structure of the display substrate is exemplified.
  • FIG. 13A is a schematic diagram of a display substrate 20 provided by other embodiments of the present disclosure
  • FIG. 13B is a cross-sectional view of FIG. 13A along the section line B-B'. It should be noted that, for the sake of clarity, FIG. 13B omits some structures that do not have a direct electrical connection relationship at the section lines.
  • the display substrate 20 includes a base substrate 100 on which a plurality of sub-pixels are located.
  • the pixel circuits of the plurality of sub-pixels P are arranged as a pixel circuit array, for example, the row direction of the pixel circuit array is the first direction D1, and the column direction is the second direction D2.
  • the pixel circuits of each sub-pixel may have exactly the same structure, that is, the pixel circuits are repeatedly arranged in the row and column directions.
  • the arrangement rule of the pixel circuit of the sub-pixel and the arrangement rule of the pixel electrode above it may be the same or different.
  • the arrangement rule of the sub-pixel here is The description refers to the arrangement rules of the pixel circuits, and the description of the relative positional relationship of the sub-pixels refers to the relative positions of the pixel circuits of the sub-pixels, for example, adjacent sub-pixels refer to sub-pixels adjacent to the pixel circuits. The following embodiments are the same as this and will not be repeated here.
  • the display substrate 20 includes a semiconductor layer 105, an insulating layer 601, a conductive layer 711, an insulating layer 602, a conductive layer 712, an insulating layer 603, and a semiconductor layer 106 that are sequentially stacked on the base substrate 100. , insulating layer 604 , conductive layer 713 , insulating layer 605 , conductive layer 714 , insulating layer 606 , conductive layer 715 , insulating layer 607 and conductive layer 716 .
  • Figure 14 corresponds to Figure 13A and schematically shows the semiconductor layer 105 and the conductive layer 711 (an example of the first metal layer of the present disclosure), and Figure 15 shows the pattern of the conductive layer 712 on the basis of Figure 14, and Figure 16A is shown in Figure 15
  • the pattern of the semiconductor layer 106 and the conductive layer 713 is shown on the basis of FIG. 17A shows the conductive layer 714, and FIG. 17B shows the conductive layer 714 on the basis of FIG. 16A;
  • FIG. 18A shows the conductive layer 715, FIG. 18B shows the conductive layer 715 on the basis of FIG. 17B.
  • Tng, Tns, Tnd, and Tna are respectively used to denote the gate, first electrode, second electrode and channel region of the nth transistor Tn in the following description, wherein n is 1-7.
  • the “same-layer arrangement” referred to in this disclosure means that two (or more than two) structures are formed through the same deposition process and patterned through the same patterning process, and are not necessarily located same level; their materials may be the same or different.
  • the "integrated structure” in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process to form interconnected structures, and their materials may be the same or different .
  • the semiconductor layer 105 includes channel regions (T1a, T2a, T4a, T5a, T1a, T2a, T4a, T5a, T7a) and the first pole (T1s, T2s, T4s, T5s, T7s), the second pole (T1d, T2d, T4d, T5d, T7d).
  • the display substrate 20 adopts a self-alignment process, and uses the conductive layer 711 as a mask to conduct conductorization treatment (such as doping treatment) on the semiconductor layer 105, so that the part of the semiconductor layer 105 not covered by the conductive layer 711 is covered with conducting, so that the parts of the semiconductor layer located on both sides of the channel region of each transistor are conductorized to form the first pole and the second pole of the transistor respectively.
  • the material of the semiconductor layer 105 is a low temperature polysilicon material.
  • the conductive layer 711 further includes a scan line 710 , a reset control line 720 and a light emission control line 730 which are insulated from each other.
  • These signal lines can all be examples of the gate lines 11 shown in FIG. 4 .
  • the scanning line 710 is electrically connected to the gate T2g of the second transistor T2 in the corresponding row of sub-pixels (or an integral structure) to provide the first scanning signal Ga1, and the reset control line 720 is connected to the sixth transistor T6 in the corresponding row of sub-pixels.
  • the gate T6g of the sub-pixel is electrically connected to provide the first reset control signal Rst1
  • the emission control line 730 is electrically connected to the gate T4g of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scanning line 710 of the sub-pixels in the current row can be used as the reset control line 720 of the sub-pixels in the next row.
  • the light emission control line 730 is also electrically connected to the gate T5g of the fifth transistor T5 to provide the second light emission control signal EM2, that is, the first light emission control signal EM1 and the second light emission control signal EM2 for the same signal.
  • the conductive layer 712 (an example of the second metal layer in the present disclosure) includes a first capacitive electrode Ca.
  • the first capacitor electrode Ca overlaps the gate T1g of the first transistor T1 in a direction perpendicular to the base substrate 100 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the first storage capacitor Cst.
  • the first capacitive electrode Ca includes an opening 722 , and the opening 722 exposes at least part of the gate T1g of the first transistor T1 , so as to facilitate the electrical connection of the gate T1g to other structures.
  • the first capacitive electrodes Ca of sub-pixels located in the same pixel row are connected to each other as an integral structure.
  • the sizes of the openings 722 in adjacent sub-pixels in the first direction D1 are inconsistent, for example, a sub-pixel with a larger opening 722 is a green pixel, and a sub-pixel with a smaller opening 722 is a red pixel. or blue pixels.
  • the lighting voltage and data signal of the green pixel are different from those of the red and blue pixels. It is necessary to adjust the driving circuit of the green pixel to increase the charging speed of the green pixel, thereby improving the uniformity of display.
  • the area of the first capacitive electrode Ca can be reduced, so that the green pixel has a smaller capacitive storage Cst, thereby increasing the charging speed.
  • the storage capacitance of the green pixel can also be reduced in other ways, such as reducing the area of the second capacitor electrode Cb, adjusting the width-to-length ratio of the driving transistor, and the like.
  • the conductive layer 712 may further include a first auxiliary control line 721, a second auxiliary control line 725, and a reset voltage line 723, 724 extending along the first direction D1, which will be discussed later in conjunction with FIG. 16A and FIGS. 17A-17B. Be specific.
  • the semiconductor layer 106 includes the channel regions (T3a, T6a) of the third transistor T3 and the sixth transistor T6, the first electrodes (T3s, T6s) of the third transistor T3 and the sixth transistor T6, the third The second poles (T3d, T6d) of the transistor T3 and the sixth transistor T6.
  • the conductive layer 713 includes scan lines 740 and reset control lines 750 extending along the first direction D1.
  • the material of the semiconductor layer 106 is an oxide semiconductor, such as IGZO, ZnO, AZO, IZTO and other materials.
  • Oxide thin film transistors have the advantage of small leakage current. Since both the third transistor T3 and the sixth transistor T6 are transistors directly connected to the gate of the first transistor T1 (that is, the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the stability of the first transistor T1. Stability of the gate (N1 node) voltage of a transistor T1.
  • the third transistor T3 and the sixth transistor are N-type metal oxide thin film transistors, which help to reduce the leakage current of the transistors and help to maintain the voltage of the N1 node, so that in the compensation stage, the threshold voltage of the first transistor T1 has Helps to get full compensation, and then improves the display uniformity of the display substrate in the light-emitting stage.
  • the display substrate 20 adopts a self-alignment process, and uses the conductive layer 713 as a mask to conduct conductive treatment (such as doping treatment) on the semiconductor layer 106, so that the part of the semiconductor layer 106 not covered by the conductive layer 713 is covered with conductorization, so that the parts of the semiconductor layer 106 located on both sides of the channel regions of the third transistor T3 and the sixth transistor T6 are conductorized to form the first pole and the second pole of the third transistor T3 and the sixth transistor T6 respectively.
  • conductive treatment such as doping treatment
  • the scan line 740 at least partially overlaps with the first auxiliary control line 721; for example, the third transistor T3 is located below the scan line 740
  • the orthographic projection of the channel region T3a on the substrate is located within the orthographic projection of the first auxiliary control line 721 on the substrate.
  • the first auxiliary control line 721 can be used as a light-shielding layer to prevent light from entering the channel region from the back of the channel region of the third transistor T3 to adversely affect the characteristics of the third transistor T3.
  • the oxide semiconductor material is relatively sensitive to light.
  • the third transistor T3 uses the oxide semiconductor material as a channel region, light incident on the channel region will easily cause a threshold shift of the third transistor T3.
  • the stability of the third transistor T3 can be improved by setting the first auxiliary control line 721 , further stabilizing the gate voltage of the first transistor T1 .
  • the scanning line 740 and the first auxiliary control line 721 are configured to receive the same scanning signal, so that the third transistor T3 forms a double-sided gate structure, thereby improving the gate control capability of the third transistor T3 and further stabilizing the third transistor T3.
  • the reset control line 750 at least partially overlaps; for example, the channel of the sixth transistor T6 located below the reset control line 750
  • the orthographic projection of the region T6a on the base substrate is located within the orthographic projection of the second auxiliary control line 725 on the base substrate.
  • the second auxiliary control line 725 can be used as a light-shielding layer to prevent light from entering the channel region from the back of the channel region of the sixth transistor T6 to adversely affect the characteristics of the sixth transistor T6.
  • the oxide semiconductor material is more sensitive to light.
  • the sixth transistor T6 uses the oxide semiconductor material as a channel region, light incident on the channel region will easily cause the threshold value shift of the sixth transistor T6.
  • the stability of the sixth transistor T6 can be improved, further stabilizing the gate voltage of the first transistor T1.
  • the reset control line 750 and the second auxiliary control line 725 are configured to receive the same scan signal, so that the sixth transistor T6 forms a double-sided gate structure, thereby improving the gate control capability of the sixth transistor T6 and further stabilizing The gate voltage of the first transistor T1.
  • the active layer of the seventh transistor T7 may also be disposed in the semiconductor layer 106 , for example, an oxide semiconductor material is used. Since the first transistor T7 is directly electrically connected to the first electrode 134 of the light emitting element 120, this arrangement can reduce the leakage current of the seventh transistor T7, improve the stability of the potential of the first electrode 134, and thus improve the stability of light emission.
  • the conductive layer 712 also includes an auxiliary control line 810 (an example of the first reset control line in the present disclosure), and the conductive layer 713 also includes a reset control line 820 (the second reset control line in the present disclosure).
  • An example of a control line) the reset control line 820 and the auxiliary control line 810 are configured to provide gate voltage control for the seventh transistor T7.
  • the reset control line 820 and the auxiliary control line 810 are configured to receive the same scan signal, so that the seventh transistor T7 forms a double-sided gate structure, thereby improving the gate control capability of the seventh transistor T7 and further stabilizing the first The voltage of electrode 134.
  • the reset control line 820 overlaps at least partially with the auxiliary control line 810; for example, the orthographic projection of the channel region of the seventh transistor T7 below the reset control line 820 on the base substrate It is located in the orthographic projection of the auxiliary control line 810 on the base substrate.
  • connection mode of the seventh transistor T7 needs to be adjusted adaptively.
  • the second pole T7d of the seventh transistor T7 and the second pole T5d of the fifth transistor T5 are no longer directly electrically connected in the semiconductor layer 105, but need to be electrically connected through a via hole, which will not be repeated here.
  • FIG. 16C shows a schematic diagram of a display substrate provided in some other examples of the present disclosure.
  • the display substrate further includes a light-shielding layer LS on the side of the semiconductor layer 105 close to the base substrate 100, and the light-shielding layer LS is used for The channel region of the transistor is shielded, so as to prevent threshold shift of the transistor caused by incident light (for example, from the back or side) to the channel region.
  • the light-shielding layer LS includes a first light-shielding pattern LS1, which is set corresponding to the channel region T1a of the first transistor, and the orthographic projection of the channel region T1a on the base substrate falls into the first light-shielding pattern LS1. In the pattern LS1, the channel region of the first transistor is blocked, and the stability of the first node N1 is improved.
  • the light-shielding layer LS may further include a second light-shielding pattern LS2, the second light-shielding pattern LS2 is set corresponding to the channel regions of the third transistor T3 and the sixth transistor T6, and the channel regions of the third transistor T3 and the sixth transistor T6
  • the orthographic projection of the channel region on the substrate falls into the second light-shielding pattern LS2, thereby shielding the channel regions of the third transistor T3 and the sixth transistor T6, effectively reducing the
  • the leakage current further improves the stability of the first node N1.
  • the material of the light-shielding layer LS may be a metal material, or an organic or inorganic insulating light-shielding material.
  • the conductive layer 714 includes a connection electrode 701, one end of the connection electrode 701 is connected to the first capacitive electrode Ca through the opening 722 and the via hole 901 in the insulating layer.
  • the gate T1g of the transistor T1 is electrically connected to the second capacitor electrode Cb, and the other end is electrically connected to the second pole T3d of the third transistor T3 through the via hole 902, so that the second capacitor electrode Cb is connected to the third transistor T3
  • the second pole T3d is electrically connected.
  • the conductive layer 714 further includes a connection electrode 703, and the connection electrode 703 is connected to the first electrode T3s and the fifth electrode of the third transistor T3 through the via hole 904 and the via hole 914 respectively.
  • the first pole T5s of the transistor T5 is electrically connected, thereby electrically connecting the first pole T3s of the third transistor T3 and the first pole T5s of the fifth transistor T5.
  • the conductive layer 714 further includes a connection electrode 704, the connection electrode 704 is electrically connected to the second pole T5d of the fifth transistor T5 and the second pole T7d of the seventh transistor T7 through the via hole 905, so that the fifth transistor T5
  • the second pole T5d of the seventh transistor T7 and the second pole T7d of the seventh transistor T7 are electrically connected to the first electrode 134 of the light emitting element 120 .
  • the conductive layer 714 further includes a connection electrode 708 configured to load the first power supply voltage VDD.
  • the connection electrode 708 is electrically connected to the first pole T4s of the fourth transistor T4 and the first capacitor electrode Ca through the via hole 909 and the via hole 915 respectively.
  • the conductive layer 714 further includes a connection electrode 709 , and the connection electrode 709 is electrically connected to the first pole T2s of the second transistor T2 through the via hole 908 .
  • the conductive layer 714 also includes a connection electrode 702, for example, the connection electrode 702 is connected to the sixth transistor through the via hole 903 (an example of the fifth via hole in the present disclosure) and the via hole 913 respectively.
  • the first pole T6s of T6 (an example of the gate reset transistor of the present disclosure) is electrically connected to the reset voltage line 724 (an example of the first gate reset voltage line of the present disclosure), so that the first pole of the sixth transistor T6 T6s is electrically connected to the reset voltage line 724 , so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 724 .
  • the conductive layer 714 further includes a connecting electrode 707, and the connecting electrode 707 is respectively connected to the seventh transistor T7 (
  • the first pole T7s of the disclosed pixel electrode reset transistor) is electrically connected to the reset voltage line 723 (an example of the disclosed first pixel electrode reset voltage line), so that the first pole T7s of the seventh transistor T7 is connected to
  • the reset voltage line 723 is electrically connected, so that the first terminal T7s of the seventh transistor T7 can receive the second reset voltage Vinit2 from the reset voltage line 723 .
  • the conductive layer 714 further includes reset voltage lines 760 , 780 extending along the second direction D2 .
  • reset voltage lines 760 and reset voltage lines 780 are arranged alternately, and there are two columns of sub-pixels between adjacent reset voltage lines 760 and reset voltage lines 780, and the connecting electrodes 708 in the two columns of sub-pixels are, for example, One structure. Every two adjacent columns of sub-pixels share one reset voltage line 760 or one reset voltage line 780 .
  • the reset voltage line 760 is configured to provide the second reset voltage Vinit2, and the reset voltage line 780 is configured to provide the first reset voltage Vinit1.
  • the reset voltage line 760 (an example of the reset voltage line for the second pixel electrode in the present disclosure) is electrically connected to the connection electrode 707 in the adjacent sub-pixel, for example, it is connected in one structure, so as to be connected with
  • the horizontal reset voltage lines 723 are electrically connected, thereby forming a horizontal and vertical mesh conductive structure, which can reduce resistance, thereby reducing voltage drop, and helps to uniformly transmit the second reset voltage Vinit2 to the substrate of each sub-pixel.
  • the reset voltage line 780 (an example of the second gate reset voltage line in the present disclosure) is electrically connected to the connection electrode 702 in the adjacent sub-pixel, for example, it is connected in one structure, so as to be connected with
  • the horizontal reset voltage lines 724 are electrically connected, thereby forming a horizontal and vertical mesh conductive structure, which can reduce resistance, thereby reducing voltage drop, and helps to uniformly transmit the first reset voltage Vinit1 to the substrate of each sub-pixel.
  • the conductive layer 715 includes the data lines 12 extending along the second direction D2.
  • the plurality of data lines 12 are electrically connected to multiple columns of sub-pixels in one-to-one correspondence to provide a data signal Vd
  • each data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in a corresponding column of sub-pixels to provide The data signal Vd.
  • the data line 12 is electrically connected to the connection electrode 709 through the via hole 913, thereby being connected to the first pole T2s of the second transistor T2.
  • the conductive layer 715 further includes a plurality of power supply electrodes 920, and the plurality of power supply electrodes 920 are arranged in one-to-one correspondence with the plurality of sub-pixels to provide the first power supply voltage VDD.
  • the power supply electrode 920 includes a recessed structure, which is used to arrange other conductive structures (such as the connection electrode 910 mentioned later).
  • the power supply electrodes 920 corresponding to a column of sub-pixels are connected to each other as an integral structure, thereby forming the power supply line 770 extending along the second direction D2.
  • each power supply line 770 is electrically connected to the connection electrode 708 in the corresponding column of sub-pixels through the via hole 914, so that the first power supply voltage VDD is delivered to the first power supply voltage VDD of the fourth transistor T4 through the connection electrode 708.
  • One pole T4s and the first capacitive electrode Ca are electrically connected to the connection electrode 708 in the corresponding column of sub-pixels through the via hole 914, so that the first power supply voltage VDD is delivered to the first power supply voltage VDD of the fourth transistor T4 through the connection electrode 708.
  • a data line group is provided between every two adjacent columns of subpixels, and the data line group includes two data lines 12 , and the two data lines 12 respectively provide data signals for the two columns of subpixels.
  • Two columns of sub-pixels are spaced between two adjacent data line groups.
  • the orthographic projections of the two data lines 12 on the base substrate 100 and the orthographic projections of the reset voltage lines 760 and 780 on the base substrate do not overlap, thereby avoiding generation of parasitic capacitance.
  • Adjacent power lines 770 are spaced apart from each other. For example, as shown in FIGS. 18A-18B , a data line group is provided between every two adjacent power lines 770 , and two power lines 770 are spaced between adjacent data line groups. The two power supply lines between two adjacent data line groups are spaced apart from each other, in order to avoid overlapping with the lower reset voltage line 780 or reset voltage line 760 to generate parasitic capacitance. In other words, the reset voltage line 780 and the reset voltage line 760 are arranged corresponding to the gap between two adjacent power lines 770 .
  • the conductive layer 715 also includes a connection electrode 910, the connection electrode 910 is electrically connected to the connection electrode 704 through the via hole 911, so that the connection electrode 704 and the first light emitting element 120 The electrodes 134 are electrically connected. As shown in FIGS. 13A-13B , the connection electrode 910 is electrically connected to the first electrode 134 of the light emitting element 120 through the via hole 912 .
  • connection electrodes 910 and 704 are used as transfer electrodes to lead out the first electrode of the lower transistor to be electrically connected to the upper light-emitting element.
  • This arrangement can avoid the direct penetration of the via hole in the direction perpendicular to the base substrate, resulting in If the filling depth of the conductive material is too deep, it will lead to poor connection, disconnection or unevenness.
  • the transfer electrode By setting the transfer electrode, the depth of the via hole is reduced and the contact yield is improved.
  • FIG. 18C is a schematic diagram of a display substrate provided by other embodiments of the present disclosure.
  • the reset voltage line 780 can be vertically moved upward into the conductive layer 715 and located between two adjacent power lines 770 .
  • 19A and 19B are schematic diagrams of display substrates provided by some other embodiments of the present disclosure.
  • the main difference from the embodiment shown in FIGS. 18A-18B is that, in this embodiment, the reset voltage lines 760, 780 are changed.
  • the reset voltage lines 760, 780 are not located in the conductive layer 714, but It is located in the conductive layer 715 and between the two data lines 12 in the data line group.
  • the reset voltage line 780 is electrically connected to the reset voltage line 724 through the via hole 918 (an example of the second via hole in the present disclosure), thereby forming a horizontal and vertical mesh reset voltage line structure.
  • the reset voltage line 760 is electrically connected to the reset voltage line 723 through the via hole 919 (an example of the third via hole in the present disclosure), thereby forming a horizontal and vertical mesh reset voltage line structure.
  • reset voltage lines 760 and reset voltage lines 780 are arranged alternately, and alternately located between two data lines 12 in the data line group.
  • the two power lines 770 between adjacent data line groups are connected into one structure. Since the gap between the two power lines 770 is no longer correspondingly provided with the reset voltage line 760 or the reset voltage line 780 , the structure of connecting the two power lines 770 into one body will not cause parasitic capacitance.
  • every two adjacent power supply electrodes 920 in the first direction D1 are connected to each other as an integrated power supply electrode group 777, and the power supply electrode group 777 includes a hollowed out area 771, which is used to set The connection electrodes 910 in the sub-pixels corresponding to the two power supply electrodes 920 .
  • the conductive layer 715 further includes a connecting line 772, which extends along the second direction D2 and is located in the middle of each hollowed out area 771, and divides one hollowed out area into two hollowed out sub-areas, and the two hollowed out areas 771
  • the two connection electrodes 910 are respectively located in the two hollowed-out sub-regions, and are respectively located on both sides of the connection line 772 .
  • the setting of the connection line 772 helps to further reduce the resistance of the power line 770 .
  • the conductive layer 206 includes the first electrode 134 of the light emitting element 120 .
  • the display substrate 20 may further include a pixel defining layer 608 on the first electrode 134 of the light emitting element.
  • An opening is formed in the pixel defining layer 308 to expose at least part of the pixel electrode 134 to define the opening area (ie, the effective light emitting area) 800 of each sub-pixel of the display substrate.
  • the light-emitting layer 136 of the light-emitting element 120 is formed at least in the opening (the light-emitting layer 136 can also cover part of the surface of the pixel defining layer on the side away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form The light emitting element 120 .
  • the second electrode 135 is a common electrode, and is arranged on the entire surface of the display substrate 20 .
  • the pixel electrode 134 is the anode of the light emitting element
  • the second electrode 135 is the cathode of the light emitting element.
  • the distribution of the first electrodes of the light-emitting elements of the display substrate provided by the embodiments of the present disclosure is not limited to the situation shown in FIG. 13A , but is also applicable to the distribution of other pixel electrodes.
  • the distribution diagram of the first electrodes 134 of the light emitting element shown in FIG. 10B is also applicable to the display substrate provided in this embodiment.
  • each conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and combinations of the above metals. Alloy materials; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.; or a multilayer metal stack structure; or metal Laminated structure with conductive metal oxides.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the light emitting element 120 has a top emission structure
  • the first electrode (ie, the pixel electrode) 134 is reflective
  • the second electrode 135 is transmissive or semi-transmissive.
  • the first electrode 134 is an anode
  • the second electrode 135 is a cathode.
  • the first electrode 134 is an ITO/Ag/ITO laminated structure
  • the transparent conductive material ITO is a material with a high work function, and direct contact with the luminescent material can improve the hole injection rate
  • the metal material Ag helps to improve the first electrode. Reflectivity.
  • the second electrode 135 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or a metal alloy material, such as an Ag/Mg alloy material.
  • each insulating layer is, for example, an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • Metal oxynitride insulating material such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • Metal oxynitride insulating material such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc.
  • the material of the pixel defining layer 608 is an organic material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • organic material such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • the base substrate 100 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC) etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polysulfone
  • the materials of the semiconductor layers 105, 106 include but are not limited to silicon-based materials (a-Si, polysilicon, p-Si, etc.), oxides such as metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) Semiconductor materials and organic materials (hexathiophene, polythiophene, etc.).
  • the display substrate 20 includes the structure shown in FIG. 2.
  • the connection structure shown in FIG. It is not intended to limit the disclosure.
  • connection electrode 704 (an example of the first conductive structure of the present disclosure) includes a bottom surface 704a close to the base substrate, a top surface 704b away from the base substrate, and a top surface 704b located on the bottom surface 704a and the top surface 704b. between the first side surface 704c.
  • the connecting electrode 704 is electrically connected to the connecting electrode 910 (an example of the second conductive structure in the present disclosure) through a via hole 911 (an example of a first via hole in the present disclosure).
  • the via hole 911 and the via hole 905 at least partially overlap in a direction perpendicular to the base substrate, so that the insulating layer 606 (an example of the second insulating layer in the present disclosure) is recessed downward,
  • the via hole 911 exposes at least part of the first side surface 704c of the connection electrode 704, and makes the connection electrode 910 recessed downward and includes a protrusion 910a (another example of the first protrusion of the present disclosure), which is connected to the protrusion 910a.
  • At least part of the first side surface 704c is in contact, covering the portion of the first side surface 704c exposed by the via hole 911 .
  • the structure shown in Fig. 2 can be regarded as a part of the sectional structure showing the substrate 20 along the section line BB', that is, the structure encircled by a dotted line in Fig. 13B, and the structure in Fig. 13B
  • the connection electrode 704, the connection electrode 910, the protruding portion 910a, the via hole 911, and the via hole 905 can be regarded as the first conductive structure 21, the second conductive structure 22, the protruding portion 220, the via hole V1, and the recessed structure G1 in FIG. 2, respectively.
  • the description of FIG. 2 is also applicable to FIG. 13B , and details are not repeated here.
  • connection electrode 704 includes a protruding portion 704 t facing the via hole 905 , and the orthographic projection of the protruding portion 704 t on the base substrate is located within the orthographic projection of the via hole 905 on the base substrate.
  • the size of the via hole 905 along the reference direction F is b, and the reference direction F is parallel to the board surface of the base substrate, such as the second direction D2; the via hole 911 and the via hole
  • the dimension of the overlapping area of 905 along the reference direction F is c, and the dimension of the portion of the first side surface 704c of the connection electrode 704 covered by the connection electrode 910 in the direction perpendicular to the base substrate is d.
  • connection electrode 704 includes a contact portion 724 located on the side of the insulating layer 605 away from the substrate and in contact with the connection electrode 910 .
  • the dimension of the first side surface 704c in a direction perpendicular to the base substrate is n.
  • the maximum depth of the via hole 905 is i
  • the angle formed between one side of the via hole 905 and the board surface of the base substrate is j
  • the connection electrode 910 and the The dimension of the portion contacted by the connecting electrode 704 in the direction perpendicular to the base substrate is k.
  • c/b is greater than 0.1; d/e is greater than 0.3.
  • c/b is greater than 0.28.
  • d/n is greater than 0.6.
  • the size of the first side surface 704c covered is positively related to the depth of the via hole 905 and the bottom angle of the via hole 905, and negatively related to the thickness of the connecting electrode 910, and d/e or c/b is reduced within a certain range,
  • the overlapping of the via hole 911 and the via hole 905 can be reduced, thereby reducing the size of the downward protruding portion 910a of the connection electrode 910, improving the flatness of the connection electrode 910, and further improving the flatness of the upper pixel electrode. Display quality.
  • the above setting can increase the overlapping area of the connection electrode 910 and the connection electrode 704 in the vertical direction, thereby helping to reduce the plane area of the via hole 911 and the via hole 905. Since the pixel opening area 800 needs to avoid contact with the via hole 911 or the via hole 905 overlap to improve flatness, so this setting can effectively increase the aperture ratio of the display substrate.
  • the average thickness of the protrusion 910 a is smaller than the average thickness of the portion of the connection electrode 910 that is in contact with the top surface 704 b of the connection electrode 704 .
  • the protrusion 910a is located between the reset voltage line 760/780 connected to the sub-pixel and the connection electrode 708; that is, the orthographic projection of the protrusion 910a on the base substrate 100 is located at the reset voltage Between the orthographic projection of the line 760/780 on the base substrate and the orthographic projection of the connection electrode 708 on the base substrate. Since the connection electrode 708 is loaded with the first power supply voltage VDD, this setting helps to reduce signal interference between the reset voltage line 760 / 780 and the connection electrode 708 .
  • the protrusion 910 a is located between the reset voltage line 760 connected to the sub-pixel in this column and the connection electrode 708 .
  • the distance between the orthographic projection of the protrusion 910a on the base substrate and the orthographic projection of the reset voltage line 760 on the base substrate in the reference direction F (such as the first direction D1) is s1.
  • the distance between the orthographic projection of the portion 910a on the base substrate and the orthographic projection of the connection electrode 708 on the base substrate in the reference direction F is s2.
  • s1 is smaller than s2. This arrangement can better shield the reset voltage line 70 .
  • connection electrode 708 includes an extension portion 708a whose main body extends along the first direction D1, the extension portion 708a protrudes toward the reset voltage line 706, and the dimension of the extension portion 708a in the second direction D2 is smaller than the Dimension D2 of the main body in the second direction.
  • connection electrode 704 at least partially overlaps with the extension portion 708a of the connection electrode 708 . This arrangement helps to further improve the effect of shielding the power voltage signal in the connection electrode 708 from interfering with the reset voltage line 706 .
  • At least one embodiment of the present disclosure further provides a display panel including any one of the above display substrates 20 .
  • the display panel is an OLED display panel, and accordingly the display substrate 20 it includes is an OLED display substrate.
  • the display substrate 20 may or may not include a light emitting element, that is, the light emitting element may be formed in a panel factory after the display substrate 20 is completed.
  • the display panel provided by the embodiment of the present disclosure further includes a light-emitting element in addition to the display substrate 20 .
  • the display panel 30 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20.
  • the encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture. The penetration of gas and oxygen into the light-emitting element and the driving sub-circuit causes damage to the device.
  • the encapsulation layer 801 includes an organic thin film or a structure in which an inorganic thin film, an organic thin film, and an inorganic thin film are alternately laminated.
  • a water-absorbing layer (not shown) may also be provided between the encapsulation layer 801 and the display substrate 20 , configured to absorb water vapor or sol remaining in the early-stage manufacturing process of the light-emitting element.
  • the cover 802 is, for example, a glass cover or a flexible cover.
  • the cover plate 802 and the encapsulation layer 801 may be an integrated structure.
  • At least one embodiment of the present disclosure further provides a touch display panel, which includes any one of the above display substrates 20 .
  • the touch display panel provided by at least one embodiment of the present disclosure will be exemplarily described below with reference to FIG. 21 and taking the touch display panel including the display substrate shown in FIGS. 6A-6B as an example.
  • the touch display panel 50 includes a stacked display substrate 20 and a touch structure 520 , and also includes an insulating layer 406 between the display substrate 20 and the touch structure 520 .
  • the insulating layer 406 includes an encapsulation layer 406, and the encapsulation layer 406 is configured to seal the light-emitting element 120, so as to prevent external moisture and oxygen from penetrating into the light-emitting element and the driving circuit, causing damage to, for example, the light-emitting element 120, etc. damage to the device.
  • the encapsulation layer 406 may be a single-layer structure or a multi-layer structure, such as including an organic thin film, an inorganic thin film, or a multi-layer structure including alternately stacked organic thin films and inorganic thin films.
  • the touch display panel further includes a buffer layer (not shown) between the encapsulation layer 406 and the touch structure 520 .
  • the buffer layer is used to improve the adhesion between the touch structure 520 and the display substrate 20 .
  • the touch control structure 520 includes a touch control electrode 521 , and the touch control electrode 521 is, for example, a block electrode or a metal grid electrode.
  • the protrusion of the second conductive structure in the display substrate does not overlap with the touch electrode; that is, the protrusion of the second conductive structure (such as the protrusion 314a in FIG.
  • the orthographic projection on the substrate is separated from the orthographic projection of the touch electrode on the base substrate. This arrangement is helpful to avoid defects caused by the protruding portion affecting the flatness of the touch electrode.
  • the first conductive structure in the display substrate (such as the connection electrode 232 in FIG. 21 ) does not overlap with the touch electrode; Orthographic separation of the control electrode on the base substrate.
  • At least one embodiment of the present disclosure also provides a display device 40.
  • Display As shown in FIG. : Display, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Any product or component with display function.

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Abstract

一种显示基板(20)及显示装置(40)。该显示基板(20)包括衬底基板(100)、依次层叠的第一绝缘层(301)、第一导电层(201)、第二绝缘层(302)和第二导电层(202)。该第一绝缘层(301)包括第一凹陷结构(G1)，该第一导电层(201)包括第一导电结构(21)，该第一导电结构(21)包括靠近该衬底基板(100)的底表面(21a)、远离该衬底基板(100)的顶表面(21b)以及位于该底表面(21a)和该顶表面(21b)之间的第一侧表面(21c)；该第二绝缘层(302)包括第一过孔(V1)，该第二导电层(202)包括第二导电结构(22)，该第一过孔(V1)在该衬底基板(100)上的正投影与该第一凹陷结构(G1)在该衬底基板(100)上的正投影至少部分重叠；该第一过孔(V1)暴露该第一导电结构(21)的第一侧表面(21c)的至少部分，该第二导电结构(22)与该第一导电结构(21)的第一侧表面(21c)的至少部分接触，该第一导电结构(21)的第一侧表面(21c)包括突出曲面(21d)，该第二导电结构(22)包覆该突出曲面(21d)的至少部分；该第一导电结构(21)包括位于该第一凹陷结构(G1)中且与该突出曲面(21d)连接的连接部(21f)；沿平行于衬底基板(100)的板面的方向，该突出曲面(21d)相对于该连接部(21f)朝向该第一凹陷结构(G1)的中部突出。该显示基板(20)可以有效提高显示性能。

Description

显示基板及显示装置
本申请要求于2021年10月20日递交的中国专利申请第202111220749.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode,OLED)显示器具有主动发光、对比度高、响应速度快、轻薄等诸多优点，成为主要的新一代显示器之一。随着高分辨率产品的快速发展，对显示器的显示基板的结构设计，例如像素和信号线的排布等都提出了更高的要求。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层。所述第一绝缘层包括第一凹陷结构，所述第一导电层包括第一导电结构，所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电层包括第二导电结构；所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影至少部分重叠；所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第二导电结构与所述第一导电结构的第一侧表面的所述至少部分接触；所述第一导电结构的第一侧表面包括突出曲面，所述第二导电结构包覆所述突出曲面的至少部分；所述第一导电结构包括位于所述第一凹陷结构中且与所述突出曲面连接的连接部；沿平行于所述衬底基板的板面的方向，所述突出曲面相对于所述连接部朝向所述第一凹陷结构的中部突出。
在一些示例中，所述第二导电结构包括第一突出部，所述第一突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的 正投影内；所述第一突出部与所述第一导电结构的第一侧表面的至少部分接触。
在一些示例中，所述第一凹陷结构在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠。
在一些示例中，所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，所述第一侧表面在垂直于所述衬底基板的方向上的尺寸大于所述第二侧表面在垂直于所述衬底基板的方向上的尺寸。
在一些示例中，所述第一侧表面包括位于所述第一绝缘层远离所述衬底基板一侧的第一侧表面部分；所述第一侧表面部分未被所述第二导电结构覆盖的部分沿垂直于所述衬底基板的方向上的尺寸大于所述第二侧表面沿垂直于所述衬底基板的方向上的尺寸。
在一些示例中，所述第一导电结构的顶表面与所述第一侧表面直接连接的至少部分与所述第二导电层分离。
在一些示例中，所述显示基板具有第一截面，所述第一凹陷结构在所述第一截面内并沿参考方向的尺寸为b，所述参考方向与所述衬底基板的板面平行；在所述第一截面内，所述第一过孔与所述第一凹陷结构的重叠区域沿所述参考方向的尺寸为c，所述第一导电结构的第一侧表面被所述第二导电结构覆盖的部分在垂直于衬底基板的方向上的尺寸为d；所述第一导电结构包括位于所述第一绝缘层的远离所述衬底基板一侧且与所述第二导电结构接触的接触部在垂直于所述衬底基板方向的尺寸为e；c/b大于0.1；d/e大于0.3。
在一些示例中，c/b大于0.15，d/e小于0.8。
在一些示例中，c/b小于0.19，d/e小于0.5。
在一些示例中，在所述第一截面内，所述第一凹陷结构的最大深度为i，所述第一凹陷结构在所述第一截面内的一个侧边与所述衬底基板的板面所成的夹角为j，所述第二导电结构与所述第一导电结构接触的部分在垂直于所述衬底基板方向上的厚度为k；d/e<0.0273*i*sin(j)/k。
在一些示例中，c/b<0.0102*i*sin(j)/k。
在一些示例中，所述第一侧表面在垂直于所述衬底基板的方向上的尺寸为n，所述第二侧表面在垂直于所述衬底基板的方向上的尺寸为e； 0.1*(n/e)/sin(j)>(d/n)。
在一些示例中，0.08*(n/e)/sin(j)>d/n。
在一些示例中，所述接触部包括朝向所述第一凹陷结构的第二突出部，所述第二突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的正投影内；在所述第一截面内，所述第二突出部在垂直于所述衬底基板的方向上的尺寸大于所述第一导电层位于所述第一凹陷结构的侧表面的部分在垂直于所述第一凹陷结构的所述侧表面的方向上的尺寸。
在一些示例中，第一绝缘层还包括与第一凹陷结构间隔的第二凹陷结构，所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，所述第二侧表面在所述衬底基板上的正投影与所述第二凹陷结构在所述衬底基板上的正投影至少部分重叠；所述第一过孔还暴露所述第二侧表面的至少部分，所述第二导电结构包覆所述第一导电结构的第二侧表面的至少部分。
在一些示例中，在垂直于所述衬底基板的方向上，所述第一导电结构的第一侧表面被所述第二导电结构覆盖的部分的尺寸与所述第二侧表面被所述第二导电结构覆盖的部分的尺寸不同。
在一些示例中，所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影的重叠尺寸和所述第一过孔在所述衬底基板上的正投影与所述第二凹陷结构在所述衬底基板上的正投影的重叠尺寸不同。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层；所述第一导电层包括第一导电结构；所述第二导电层包括第二导电结构；所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电结构通过所述第一过孔与所述第一导电结构接触；所述第二导电结构包括第一突出部，所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第一突出部与所述第一导电结构的第一侧表面的所述至少部分接触；所述第一绝缘层包括彼此间隔的第一凹陷结构和第二凹陷结构，所述第一导电结构还包括位于所述底表 面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，所述第一导电结构的至少部分分别位于所述第一凹陷结构和所述第二凹陷结构中。
在一些示例中，所述第一导电结构包括朝向所述第一凹陷结构的第二突出部，所述第二突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的正投影内。
在一些示例中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；所述第一导电层还包括与所述第一导电结构间隔的第一信号线和第二信号线，所述第一信号线和所述第二信号线沿所述第二方向延伸；所述第一突出部在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影在所述第一方向上的距离为l，所述第二信号线在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影在所述第一方向上的距离m，所述显示基板包括垂直于所述衬底基板的第一截面，在所述第一截面内，所述第一导电结构位于所述第一绝缘层的远离所述衬底基板一侧的部分在垂直于所述衬底基板的方向上的尺寸为e，所述第一侧表面被所述第一突出部包覆的部分在垂直于所述衬底基板的方向上的尺寸为d，l/m>0.9(d/e)。
在一些示例中，l/m>1.2*(d/e)。
在一些示例中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；所述第二绝缘层包括多个过孔，所述多个过孔沿所述第一方向和所述第二方向排列为多个过孔行和多个过孔列，所述多个过孔包括多个所述第一过孔；所述多个过孔行包括第一过孔行，在所述第一过孔行中，每隔1个过孔存在3个连续的所述第一过孔。
在一些示例中，所述多个过孔列包括第一过孔列，在所述第一过孔列中，每个过孔都是所述第一过孔，或者每隔1个过孔存在一个所述第一过孔。
在一些示例中，所述多个像素列包括在所述第一方向上相邻的第一像素列和第二像素列，所述第一信号线与所述第一像素列的子像素连接以提 供第一信号，所述第二信号线与所述第二像素列的子像素连接以提供第二信号，所述第一像素列的发光元件靠近所述衬底基板一侧的电极在所述衬底基板上的正投影分别与所述第一信号线在所述衬底基板上的正投影及所述第二信号线在所述衬底基板上的正投影至少部分重叠。
在一些示例中，所述显示基板还包括位于所述像素电极远离所述衬底基板一侧的像素界定层，所述像素界定层包括多个像素开口区，所述多个像素开口区与所述多个子像素一一对应，所述多个像素开口区在所述衬底基板上的正投影与所述第一突出部在所述衬底基板上的正投影分离。
在一些示例中，所述像素界定层包括多个凸起部，所述多个凸起部位于所述多个像素开口区之间；所述多个凸起部包括围绕同一像素开口区设置的第一凸起部、第二凸起部和第三凸起部，所述第一凸起部、所述第二凸起部和所述第三凸起部在所述衬底基板上的正投影的中心的连线构成一个三角形。
在一些示例中，所述第一凸起部位于相邻的四个像素开口区之间，所述第二凸起部和所述第三凸起部分别位于相邻的两个像素开口区之间；所述第一凸起部在所述衬底基板上的正投影的面积分别大于所述第二凸起部在所述衬底基板上的正投影的面积以及所述第三凸起部在所述衬底基板上的正投影的面积。
在一些示例中，所述显示基板还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；所述第三导电层包括屏蔽电极和第一电容电极，所述屏蔽电极包括沿所述第一方向延伸的部分，以及朝向所述屏蔽电极所在子像素的所述第一电容电极延伸的部分。
在一些示例中，所述显示基板还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；所述第一导电层包括沿所述第二方向延伸的第一复位电压线，所述第三导电层包括沿所述第一方向延伸的第二复位电压线，所述第一复位电压线与所述第二复位电压线电连接；所述显示基板还包括位于所述第三导电层靠近所述衬底基 板一侧的半导体层，所述半导体层包括连接部；所述连接部将所述第一复位电压线与子像素中的复位晶体管的第一极电连接；所述连接部在所述衬底基板上的正投影与所述第一复位电压线在所述衬底基板上的正投影以及所述复位晶体管的第一极在所述衬底基板的正投影均交叠。
在一些示例中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；所述显示基板还包括沿所述第一方向延伸的第一栅极复位电压线和第一像素电极复位电压线，以及沿所述第二方向延伸的第二栅极复位电压线和第二像素电极复位电压线；所述第一栅极复位电压线与所述第二栅极复位电压线通过第二过孔电连接，所述第一像素电极复位电压线与所述第二像素电极复位电压线通过第三过孔电连接；所述第一栅极复位电压线和所述第二栅极复位电压线用于给驱动晶体管的栅极提供复位电压信号，所述第一像素电极复位电压线和第二像素电极复位电压线用于给像素电极提供复位电压信号。
在一些示例中，所述第二像素电极复位电压线通过第四过孔与像素电极复位晶体管的第一极电连接，所述第四过孔与所述第三过孔在所述衬底基板上的正投影彼此分离。
在一些示例中，所述第二栅极复位电压线通过第五过孔与栅极复位晶体管的第一极电连接，所述第五过孔与所述第二过孔在所述衬底基板上的正投影彼此分离。
在一些示例中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；每个子像素包括第一电容电极，所述显示基板还包括沿所述第二方向延伸的多条数据线；在所述第一方向上相邻的两个子像素的第一电容电极通过连接部连接，所述多条数据线分别与多个连接部在垂直于所述衬底基板的方向上交叠；所述连接部包括与对应的数据线存在交叠的第一部分和与所述对应的数据线不交叠的第二部分；所述第一部分在所述第二方向的尺寸大于所述第二部分在所述第二方向的尺寸；所述显示基板还包括沿所述第二方向延伸的复位电压线，所述第二部分与所述复位电压线在垂直于所述衬底基板的方向上重叠。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一金属层、第二金属层、第一导电层和第二导电层；所述显示基板还包括位于所述衬底基板上在第一方向上的相邻的第一子像素和第二子像素，所述第一子像素具有第一像素电路，所述第二子像素具有第二像素电路；所述第一像素电路和第二像素电路分别包括电容，所述电容包括位于所述第二金属层的第一电容电极和位于第一金属层的第二电容电极，所述第一像素电路的第一电容电极和所述第二像素电路的第一电容电极彼此连接为一体的电容电极块，所述电容电极块具有第一开口和第二开口，所述第一开口在所述衬底基板上的正投影与所述第一像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第二开口在所述衬底基板上的正投影与所述第二像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第一开口在所述衬底基板上的正投影面积与所述第二开口在所述衬底基板上的正投影面积不同。
在一些示例中，所述第二导电层包括沿第二方向延伸的复位电压线、第一数据线、第二数据线、第一电源线和第二电源线，所述第一方向与所述第二方向不同；所述第一像素电路和所述第二像素电路的每个包括驱动晶体管和数据写入晶体管；所述复位电压线配置为给所述第一像素电路和所述第二像素电路的像素电极或驱动晶体管的栅极提供复位电压，所述第一数据线和所述第二数据线分别配置为给所述第一像素电路和所述第二像素电路的数据写入晶体管提供数据电压，所述第一电源线和所述第二电源线分别配置为给所述第一像素电路和所述第二像素电路的驱动晶体管提供电源电压；所述复位电压线位于所述第一数据线和所述第二数据线之间；所述第一数据线和第二数据线均位于所述第一电源线和所述第二电源线之间；所述第一电源线和所述第二电源线均具有封闭的镂空区。
在一些示例中，所述第一子像素的像素电极在所述衬底基板的正投影与所述复位电压线、所述第一数据线、所述第二数据线、所述第一电源线和所述第二电源线在所述衬底基板上的正投影均交叠。
在一些示例中，所述显示基板还包括多个子像素，所述多个子像素位于所述衬底基板上并沿所述第一方向和第二方向排列为多个像素行和多个像素列，所述第一方向与所述第二方向不同；所述第一导电层还包括多个连接电极，所述多个连接电极与所述多个子像素一一对应连接以提供电 源电压；所述多个子像素包括第一子像素，所述显示基板还包括沿所述第二方向延伸的复位电压线，所述复位电压线与所述第一子像素连接以提供复位电压，所述第一突出部在所述衬底基板上的正投影位于所述第一子像素对应连接的连接电极在所述衬底基板上的正投影和所述复位电压线在所述衬底基板上的正投影之间。
在一些示例中，沿所述第一方向，所述第一突出部与所述复位电压线的距离小于所述第一突出部与所述连接电极的距离。
在一些示例中，所述连接电极包括主体部和沿所述第一方向延伸的延伸部，所述延伸部在所述第二方向的尺寸小于所述主体部在所述第二方向上的尺寸；在所述第二方向上，所述第一导电结构与所述连接电极的延伸部至少部分重叠。
在一些示例中，所述第二导电层包括多个电源电极，所述多个电源电极与所述多个连接电极一一对应连接以提供所述电源电压，每个像素列对应的电源电极彼此连接为一体的结构，从而形成沿所述第二方向延伸的多条电源线。
在一些示例中，所述第二导电层还包括沿所述第二方向延伸的多条数据线，所述多条数据线分别与所述多个像素列一一对应连接以提供数据信号；所述多条数据线划分为多个数据线组，每个数据线组包括两条数据线；每相邻两个像素列之间设置有一个数据线组，相邻的数据线组之间间隔有两条电源线。
在一些示例中，所述显示基板还包括沿所述第二方向延伸的多条复位电压线，所述多条复位电压线包括在所述第一方向上交替设置的第一复位电压线和第二复位电压线，所述第一复位电压线和所述第二复位电压线分别配置为提供第一复位电压和第二复位电压；相邻的第一复位电压线和第二复位线之间间隔有两个像素列。
在一些示例中，所述多条复位电压线位于所述第一导电层，相邻的数据线组之间的两条电源线之间提供一条第一复位电压线或第二复位电压线；所述多条复位电压线中的任一条在所述衬底基板上的正投影与所述多条电源线中的任一条在所述衬底基板上的正投影分离。
在一些示例中，所述多条复位电压线位于所述第二导电层，并与多个数据线组一一对应设置，每条复位电压线位于对应的数据线组中的两条数 据线之间。
在一些示例中，相邻的数据线组之间的两条电源线彼此连接为一体的结构，使得所述两条电源线中在所述第一方向上相邻的两个电源电极彼此连接为一体的电源电极组；所述显示基板包括多个第二导电结构，所述多个第二导电结构与所述多个电源电极一一对应设置；所述电源电极组包括镂空区，所述镂空区设置有两个第二导电结构。
在一些示例中，所述第二导电层还包括连接线，所述连接线沿所述第二方向延伸，将所述镂空区分离为两个镂空子区；所述两个第二导电结构分别设置在所述两个镂空子区内，并分别位于所述连接线的两侧。
在一些示例中，所述显示基板还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层以及位于所述第三导电层和所述第二金属层之间的半导体层，其中，所述第二金属层位于所述第三导电层靠近所述衬底基板的一侧；所述子像素包括复位晶体管，所述复位晶体管配置为对所述发光元件的第一电极进行复位，所述复位晶体管包括位于所述半导体层中的有源层；所述显示基板包括分别位于所述第二金属层的第一复位控制线和位于所述第三导电层的第二复位控制线，所述第一复位控制线和所述第二复位控制线分别配置为对所述复位晶体管进行栅压控制，且所述第一复位控制线与所述第二复位控制线在所述衬底基板上的正投影至少部分重叠。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及位于所述衬底基板上的多个子像素，所述多个子像素的每个子像素包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路排列为沿第一方向延伸的多个像素行和第二方向延伸的多个像素列，所述第一方向与所述第二方向不同；所述像素电路包括驱动晶体管和存储电容，所述驱动晶体管配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极配置为接收第一电源电压；所述多个子像素包括第一子像素，所述第一子像素还包括屏蔽电极，所述屏蔽电极与所述第一子像素的第一电容电极同层设置且为一体的结构，所述屏蔽电极包括第一遮挡部和第二遮挡部，所述第二遮挡部从所述第一电容电极沿所述第二方向延伸出来，所述第一遮挡部从所述第二遮挡部沿所述第一方向延伸出来；所述显示基 板还包括半导体图案，所述半导体图案与所述驱动晶体管的有源层位于同一半导体层，在垂直于所述衬底基板的方向上，所述第一遮挡部与所述半导体图案至少部分重叠。
在一些示例中，所述像素电路还包括另一晶体管，所述另一晶体管包括栅极、第一极和第二极，所述另一晶体管的第一极和第二极分别与所述驱动晶体管的第二极和栅极连接；所述半导体图案配置为另一晶体管的有源层的至少部分。
在一些示例中，所述另一晶体管包括第一栅极和第二栅极，所述另一晶体管的有源层包括第一部分、第二部分和第三部分，所述第一部分在所述衬底基板上的正投影与所述第一栅极在所述衬底基板的正投影交叠，所述第二部分在所述衬底基板上的正投影与所述第二栅极在所述衬底基板的正投影交叠，所述第三部分位于所述第一部分和所述第二部分之间且将所述第一部分和所述第二部分连接，所述半导体图案配置为所述另一晶体管的有源层的第三部分。
在一些示例中，所述第一遮挡部包括第一子部和第二子部，所述第一子部在所述衬底基板上的正投影与所述半导体图案在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述半导体图案在所述衬底基板上的正投影不交叠，所述第一子部在所述第二方向上的尺寸大于所述第二子部在所述第二方向上的尺寸。
在一些示例中，所述显示基板还包括位于所述第一电容电极远离所述衬底基板一侧的电源线，其中，所述电源线配置为与所述第一子像素的第一电容电极电连接以提供所述第一电源电压。
在一些示例中，所述第一子像素还包括连接电极，所述连接电极用于将所述第一子像素的驱动晶体管的栅极和另一晶体管的第二极电连接；所述第一子像素的连接电极在所述衬底基板上的正投影与所述第一子像素的屏蔽电极的第二遮挡部在所述衬底基板上的正投影在所述第一方向上至少部分交叠。
在一些示例中，所述第一子像素的连接电极在所述衬底基板上的正投影在所述第二方向上位于所述第一子像素的第一电容电极和屏蔽电极所构成的一体结构在所述衬底基板上的正投影的范围之内。
在一些示例中，所述像素电路还包括数据写入晶体管，所述数据写入 晶体管与所述驱动晶体管连接，所述显示基板还包括数据线，所述数据线配置为与所述数据写入晶体管的第一极电连接以提供所述数据信号，所述第一子像素的第二遮挡部在所述衬底基板上的正投影位于所述第一子像素的连接电极在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
本公开至少一实施例还提供一种显示装置，包括如以上任一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的示意图；
图2为本公开至少一实施例提供的显示基板的示意图之一；
图3为本公开至少一实施例提供的显示基板的示意图之二；
图4为本公开至少一实施例提供的显示基板的示意图之三；
图5A为本公开至少一实施例提供的像素电路的示意图；
图5B为图5A所示像素电路的一种具体实现示例的电路图；
图5C为本公开至少一实施例提供的像素电路的时序信号图；
图6A为本公开至少一实施例提供的显示基板的示意图之四；
图6B为图6A沿剖面线A-A’的剖视图；
图7为本公开至少一实施例提供的显示基板的示意图之五；
图8A为本公开至少一实施例提供的显示基板的示意图之六；
图8B为本公开至少一实施例提供的显示基板的示意图之七；
图8C为本公开至少一实施例提供的显示基板的示意图之八；
图9A为本公开至少一实施例提供的显示基板的示意图之九；
图9B为本公开至少一实施例提供的显示基板的示意图之十；
图9C为本公开至少一实施例提供的显示基板的示意图之十一；
图9D为本公开至少一实施例提供的显示基板的示意图之十二；
图10A为本公开至少一实施例提供的显示基板的示意图之十三；
图10B为本公开至少一实施例提供的显示基板的示意图之十四；
图10C为本公开至少一实施例提供的显示基板的示意图之十五；
图11为本公开至少一实施例提供的显示基板的示意图之十六；
图12A为本公开至少一实施例提供的显示基板的示意图之十七；
图12B为本公开至少一实施例提供的显示基板的示意图之十八；
图12C为本公开至少一实施例提供的显示基板的示意图之十九；
图13A为本公开至少一实施例提供的显示基板的示意图之二十；
图13B为图13A沿剖面线B-B’的剖视图；
图14为本公开至少一实施例提供的显示基板的示意图之二十一；
图15为本公开至少一实施例提供的显示基板的示意图之二十二；
图16A为本公开至少一实施例提供的显示基板的示意图之二十三；
图16B为本公开至少一实施例提供的显示基板的示意图之二十四；
图16C为本公开至少一实施例提供的显示基板的示意图之二十五；
图17A为本公开至少一实施例提供的显示基板的示意图之二十六；
图17B为本公开至少一实施例提供的显示基板的示意图之二十七；
图18A为本公开至少一实施例提供的显示基板的示意图之二十八；
图18B为本公开至少一实施例提供的显示基板的示意图之二十九；
图18C为本公开至少一实施例提供的显示基板的示意图之三十；
图19A为本公开至少一实施例提供的显示基板的示意图之三十一；
图19B为本公开至少一实施例提供的显示基板的示意图之三十二；
图19C为本公开至少一实施例提供的显示基板的示意图之三十三；
图20为本公开至少一实施例提供的显示面板的示意图；
图21为本公开至少一实施例提供的触控显示面板的示意图；以及
图22为本公开至少一实施例提供的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种显示基板的结构示意图。如图1所示，该显示基板包括依次设置于衬底基板(未示出)上的第一绝缘层301’、第一导电层201’、第二绝缘层302’和第二导电层202’。该第二绝缘层302’中形成有过孔V1’，该第二导电层202’通过该过孔V1’与该第一导电层201’电连接。
如图1所示，该第二导电层202’只与第一导电层201’的上表面搭接，搭接面积有限，接触电阻较大，不利于电信号的快速传递。
本公开至少一实施例提供一种显示基板，包括衬底基板、依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层和第二导电层。所述第一绝缘层包括第一凹陷结构，所述第一导电层包括第一导电结构，所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电层包括第二导电结构，所述第二导电结构通过第一过孔与所述第一导电结构接触，所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影至少部分重叠；所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第二导电结构与所述第一导电结构的第一侧表面的所述至少部分接触。
本公开至少一实施例提供的显示基板通过设置第一过孔暴露所述第一导电结构的第一侧表面的至少部分，使得第二导电结构除了与第一导电结构的上表面接触外，还与第一导电结构的第一侧表面接触，有效提高了第一导电结构和第二导电结构的接触面积，不仅降低了接触电阻，提高了电信号的传输效率，还可以对该第一导电结构的侧表面起到保护作用，例如保护该侧表面不被水汽侵蚀；此外，该设置还提高了第二导电结构在纵向(垂直于衬底基板的方向) 上的截面积，不仅可以有效屏蔽第一导电结构对其基板中的其它导电结构的干扰，还可以降低位于该第二导电结构两侧的信号线之间的互相干扰。
本公开至少一实施例还提供一种显示基板，包括衬底基板、依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层和第二导电层。所述显示基板还包括多个子像素，所述多个子像素位于所述衬底基板上并沿第一方向和第二方向排列为多个像素行和多个像素列，所述第一方向与所述第二方向不同。所述第一导电层包括彼此间隔的第一导电结构、第一信号线和第二信号线，所述第一信号线和所述第二信号线沿所述第二方向延伸；所述第二导电层包括第二导电结构；所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电结构通过所述第一过孔与所述第一导电结构接触；所述第二导电结构包括第一突出部，所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第一突出部与所述第一导电结构的第一侧表面的所述至少部分接触；所述第一突出部在所述衬底基板上的正投影位于所述第一信号线在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影之间。
本公开至少一实施例提供的显示基板通过将第二导电结构的第一突出部设置为与第一导电结构的第一侧表面接触，不仅提高了第一导电结构与第二导电结构的接触面积，降低了二者的接触电阻，还有效提高了该第二导电结构的纵向截面积，可以有效屏蔽第一导电结构对其基板中的其它导电结构的干扰，同时将该第一突出部设置在第一信号线与第二信号线之间，还可以降低第一信号线与第二信号线之间的互相干扰。
本公开至少一实施例还提供一种显示基板，包括衬底基板、依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层和第二导电层、以及位于所述第二导电层远离所述衬底基板一侧的像素电极，所述像素电极配置为发光元件的第一电极，所述像素电极与所述第二导电结构电连接。所述第一绝缘层包括第一凹陷结构，所述第一导电层包括第一导电结构，所述第二导电层包括第二导电结构；所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电结构通过所述第一过孔与所述第一导电结构接触，所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构 在所述衬底基板上的正投影至少部分重叠；所述第二导电结构包括第一突出部，所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第一突出部与所述第一导电结构的第一侧表面的所述至少部分接触。
本公开至少一实施例提供的显示基板通过将将第二导电结构的第一突出部设置为与第一导电结构的第一侧表面接触，有效提高了第一导电结构和第二导电结构的接触面积，降低了接触电阻，提高了电信号的传输效率；此外，由于该设置还提高了第二导电结构在纵向(垂直于衬底基板的方向)上的截面积，不仅可以有效屏蔽第一导电结构对其基板中的其它导电结构的干扰，还可以降低位于该第二导电结构两侧的信号线之间的互相干扰。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层。所述第一绝缘层包括第一凹陷结构，所述第一导电层包括第一导电结构，所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔，所述第二导电层包括第二导电结构；所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影至少部分重叠；所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第二导电结构与所述第一导电结构的第一侧表面的所述至少部分接触；所述第一导电结构的第一侧表面包括突出曲面，所述第二导电结构包覆所述突出曲面的至少部分；所述第一导电结构包括位于所述第一凹陷结构中且与所述突出曲面连接的连接部；沿平行于所述衬底基板的板面的方向，所述突出曲面相对于所述连接部朝向所述第一凹陷结构的中部突出。
本公开至少一实施例提供的显示基板，通过上述设置，不仅可以有效增大第一导电结构与第二导电结构的接触面积，降低接触电阻，还可以缓和该第二导电结构与该第一侧表面搭接的部分的坡度，使得该第二导电结构不至于太陡峭而发生断裂。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层。所述第一导电层包括第一导电结构；所述第二导电层包括第二导电结构；所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；所述第二绝缘层包括第一过孔， 所述第二导电结构通过所述第一过孔与所述第一导电结构接触；所述第二导电结构包括第一突出部，所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第一突出部与所述第一导电结构的第一侧表面的所述至少部分接触；所述第一绝缘层包括彼此间隔的第一凹陷结构和第二凹陷结构，所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，所述第一导电结构的至少部分分别位于所述第一凹陷结构和所述第二凹陷结构中。
本公开至少一实施例提供的显示基板，通过上述设置，使第二绝缘层与第一导电结构两侧的接触关系类似，保持第一导电结构两侧的受力均衡，避免第二绝缘层与第一导电结构的分离；同时使第一导电结构的至少部分位于第一凹陷结构和第二凹陷结构，可提高第一导电结构与第一绝缘层的连接强度，避免膜层分离。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的第一金属层、第二金属层、第一导电层和第二导电层。所述显示基板还包括位于所述衬底基板上在第一方向上的相邻的第一子像素和第二子像素，所述第一子像素具有第一像素电路，所述第二子像素具有第二像素电路；所述第一像素电路和第二像素电路分别包括电容，所述电容包括位于所述第二金属层的第一电容电极和位于第一金属层的第二电容电极，所述第一像素电路的第一电容电极和所述第二像素电路的第一电容电极彼此连接为一体的电容电极块，所述电容电极块具有第一开口和第二开口，所述第一开口在所述衬底基板上的正投影与所述第一像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第二开口在所述衬底基板上的正投影与所述第二像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第一开口在所述衬底基板上的正投影面积与所述第二开口在所述衬底基板上的正投影面积不同。
由于在第一方向上的相邻的子像素的颜色通常不同，起亮电压和数据信号均不同，需要对驱动电路进行调整以平衡二者的充电速度，从而提高显示的均一性；将二者的电容电极的开口大小设置得不同，也即使得两个子像素具有不同的电容电极和存储电容，从而具有不同的充电速度，从而有助于提高显示的均一性。
例如，所述第一开口在所述衬底基板上的正投影面积小于所述第二开口在所述衬底基板上的正投影面积。
需要说明的是，本公开中的侧表面可以是顶表面凹陷而形成的，也即可以是与顶表面连续的。
本公开至少一实施例还提供一种显示基板，包括衬底基板以及位于所述衬底基板上的多个子像素。所述多个子像素的每个子像素包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路沿第一方向和第二方向排列为多个像素行和多个像素列，所述第一方向与所述第二方向不同；所述像素电路包括驱动晶体管和存储电容，所述驱动晶体管配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极配置为接收第一电源电压，所述多个子像素包括第一子像素，所述第一子像素还包括屏蔽电极，所述屏蔽电极与所述第一子像素的第一电容电极同层设置且为一体的结构，所述屏蔽电极包括第一遮挡部和第二遮挡部，所述第二遮挡部从所述第一电容电极沿所述第二方向延伸出来，所述第一遮挡部从所述第二遮挡部沿所述第一方向延伸出来；所述显示基板还包括半导体图案，所述半导体图案与所述驱动晶体管的有源层位于同一半导体层，在垂直于所述衬底基板的方向上，所述第一遮挡部与所述半导体图案至少部分重叠。
半导体层的性质容易在光照下发生变化而变得不稳定，通过设置第一遮挡部对半导体图案进行遮挡，可以提高该半导体图案的稳定性。例如，该半导体图案可以为晶体管有源层的一部分，例如该有源层的半导体区或者导体化区，在这种情形，上述设置可以有效提高晶体管的稳定性。
图2为本公开至少一实施例提供的显示基板的示意图。如图2所示，该显示基板20包括衬底基板100、依次设置于所述衬底基板100上的第一绝缘层301、第一导电层201、第二绝缘层302和第二导电层202。虽然图2中示出了第一绝缘层101直接位于衬底基板100上，然而这并不作为对本公开的限制。在其它示例中，第一绝缘层101与衬底基板100之间也可以设置有其它膜层，例如其它绝缘层或导电层。
如图2所示，该第一绝缘层301包括凹陷结构G1(本公开第一凹陷结构的一个示例)，该凹陷结构G1可以贯穿或者不贯穿该第一绝缘层301。例如，如图2所示，该凹陷结构G1可以是过孔；在另一些示例中，该凹陷结构G1还可以是凹槽。本公开对于该凹陷结构G1的具体结构不作限制。
该第一导电层201包括第一导电结构21，该第一导电结构21包括凹陷结 构G2。例如，如图2所示，该凹陷结构G2因该第一导电结构21覆盖该凹陷结构G1而形成，该第一导电结构21填充入该第凹陷结构G1而形成该凹陷结构G2。在垂直于衬底基板100的方向上，凹陷结构G1与凹陷结构G2至少部分重叠。
该第一导电结构21包括靠近衬底基板100的底表面21a、远离衬底基板100的顶表面21b以及位于该底表面21a和顶表面21b之间的第一侧表面21c。该第一侧表面21c因该第一导电结构21向下凹陷而形成。如图2所示，该第一侧表面21c可以是该凹陷结构G2的一个侧壁，该第一侧表面21c与该第二导电结构22接触的部分位于该第一绝缘层301的上表面远离衬底基板的一侧。该第一侧表面21c与该顶表面21b位于该第一导电结构21的同侧并直接连接，该第一侧表面21c与该底表面21a分别位于该第一导电结构21的两侧。
该第二绝缘层302包括过孔V1(本公开第一过孔的一个示例)，该第二导电层202包括第二导电结构22，该第二导电结构22通过过孔V1与第一导电结构21接触，该过孔V1在衬底基板上的正投影与该凹陷结构G1在衬底基板上的正投影至少部分重叠；该过孔V1暴露该第一导电结构21的第一侧表面21c的至少部分，该第二导电结构22与该第一导电结构21的第一侧表面21c的至少部分接触。
通过设置该过孔V1暴露该第一导电结构21的第一侧表面21c的至少部分，使得该第二导电结构22除了与该第一导电结构21的上表面21b接触外，还与第一导电结构21的第一侧表面21c接触，有效提高了第一导电结构21和第二导电结构22的接触面积，降低了接触电阻，提高了电信号的传输效率；此外，该设置还提高了第二导电结构22在纵向(垂直于衬底基板的方向)上的截面积，不仅可以有效屏蔽第一导电结构对其基板中的其它导电结构的干扰，还可以降低位于该第二导电结构两侧的信号线之间的互相干扰。
例如，如图2所示，凹陷结构G1在衬底基板上的正投影与过孔V1在衬底基板上的正投影至少部分重叠，使得第二绝缘层302与凹陷结构G1交叠的部分下凹，暴露出该第一导电结构21的第一侧表面21c，从而第二导电结构22不仅与该第一导电结构21的顶表面21b接触，还与其第一侧表面21c接触。
如图2所示，该第二导电结构22包括突出部220(本公开第一突出部的一个示例)，该突出部220向下突出，也即朝向衬底基板100突出，该突出部220在衬底基板100上的正投影位于该凹陷结构G1在衬底基板上的正投影内；该 突出部220与该第一导电结构21的第一侧表面21c的至少部分接触。该突出部220有效提高了该第二导电结构22在纵向上的截面积。
如图2所示，该第一导电结构21的第一侧表面21c包括突出曲面21d，该第二导电结构22的突出部220包覆该突出曲面的至少部分。
如图2所示，该第一导电结构21包括位于该第一凹陷结构G1中且与该突出曲面21d连接的连接部21f；沿平行于衬底基板100的板面的方向，该突出曲面21d相对于该连接部21f朝向该第一凹陷结构G1的中部突出。
通过将该第一侧表面21c与该第二导电结构22接触的至少部分设置为突出的曲面，不仅可以进一步增大接触面积，还可以缓和该第二导电结构22与该第一侧表面21c搭接的部分的坡度，使得该突出部220不至于太陡峭而发生断裂。
例如，在图2所示的截面(本公开第一截面的一个示例)内，该突出曲面的切线与该第一导电结构21的顶表面21b的夹角大于70度，且从上到下逐渐变小。
如图2所示，该第一导电结构21包括位于第一绝缘层301远离衬底基板一侧且与第二导电结构22接触的接触部211，该接触部211例如可以看作该第一导电结构21在与该第二导电结构22接触范围内的纵向截段。
如图2所示，该接触部211包括朝向该凹陷结构G1的突出部210(本公开第二突出部的一个示例)，该突出部210在衬底基板上的正投影位于该凹陷结构G1在衬底基板上的正投影内。例如，如图2所示，该突出部210为该接触部211靠近该凹陷结构G1的一个端部，且为该接触部211的顶表面相对于底表面朝向凹陷结构G1突出的部分。如图2所示，该突出部210的朝向凹陷结构G1的表面为该第一侧表面21c的一部分。
例如，如图2所示，沿平行于衬底基板板面的参考方向F，该突出部210的最大尺寸大于该第一导电结构21覆盖该凹陷结构G1的侧表面(侧壁)的部分的最大厚度。
如图2所示，该接触部211靠近凹陷结构G1的一个侧表面为该第一侧表面21c的一部分，也即为该第一侧表面21c位于该第一绝缘层301的上表面远离衬底基板的一侧的部分，该部分称作第一侧表面部分。该第一导电结构21还包括远离凹陷结构G1的第二侧表面21d；该第一侧表面部分在垂直于衬底基板的方向上的尺寸大于该第二侧表面21d在垂直于衬底基板的方向上的尺寸。如图2所示，该第二侧表面21d与第二导电结构22不接触。例如，该第一导电 结构21的顶表面21b的与第二侧表面21连接的至少部分与该第二导电层202分离。
由于第一侧表面部分与第二导电结构22接触而第二侧表面21d与第二导电结构22不接触，将第一侧表面部分的纵向尺寸设置得较大有助于提高第二导结构22与该第一导电结构21的顶表面21b接触的部分的平坦度，从而提高后续制作工艺的良率。
在图2所示的截面内且沿参考方向F，突出部210的最大尺寸大于该第一导电层21覆盖该凹陷结构G1的侧表面的部分(也即凹陷结构G2位于凹陷结构G1内的侧壁)的最大厚度，该参考方向F与衬底基板的板面平行。这种设置便于该突出部220与突出部210的搭接。
例如，如图2所示，该显示基板20具有第一截面，也即图2所示的截面，该凹陷结构G1在该第一截面内并沿参考方向F的尺寸为b，在该第一截面内，该过孔V1与凹陷结构G1的重叠区域沿该参考方向F的尺寸为c。例如，如图2所示，在计算凹陷结构或过孔结构与其它结构的重叠区域时，取该凹陷结构或过孔结构在该第一截面内的最低点之间的距离为该凹陷结构或过孔结构的范围；以下各实施例与此相同，不再赘述。
该第一导电结构21的第一侧表面21c被第二导电结构22覆盖的部分在垂直于衬底基板100的方向上的尺寸为d，该第一导电结构21的接触部211在垂直于所述衬底基板方向的尺寸为e。
例如，该第一侧表面21c未被该第二导电结构22覆盖的部分沿垂直于所述衬底基板的方向上的尺寸(n-d)大于该第二侧表面21d在垂直于所述衬底基板的方向上的尺寸e。
例如，c/b大于0.1；d/e大于0.3。
该第一导电结构21的第一侧表面21c被该第二导电结构22包覆的尺寸与该第一侧表面21c的尺寸的比值r1和该过孔V1与凹陷结构G1的交叠尺寸与该凹陷结构G1尺寸的比值r2是正相关的关系，即过孔V1与凹陷结构G1的交叠比例r2越大，则第二导电结构22对第一导电结构21的第一侧表面21c的包覆尺寸越大。通过上述设置可以使得第二导电结构22对第一导电结构21的侧表面进行有效包覆，从而有效降低二者的接触电阻。
例如，第二导电层202与第一导电层201的材不同。例如，第二导电层202包括ITO/AG/ITO的叠层结构，第一导电层201包括TI/AL/TI的叠层结构。
例如，c/b大于0.15，d/e小于0.8。
例如，c/b小于0.19，d/e小于0.5。
例如，当该第二导电结构22配置为发光元件的像素电极(例如为阳极)时，由于该第二导电结构22的表面形成有发光材料，该发光材料的性能会受到该第二导电结构22表面平坦度的影响，该第二导电结构22的平坦度过低会降低发光元件的发光效率。在一定范围内使过孔V1与凹陷结构G1的交叠尺寸尽可能的小，可以有助于提高第二导电结构22的平坦度，从而提高显示基板的显示性能。
例如，如图2所示，在该第一截面内，凹陷结构G1的最大深度为i，该凹陷结构G1在该第一截面内的一个侧边与衬底基板的板面所成的夹角为j，该第二导电结构22与该第一导电结构21接触的部分在垂直于所述衬底基板方向上的尺寸为k。如图2所示，该凹陷结构G1在该第一截面内的形状为倒梯形。例如，该侧边为该凹陷结构G1靠近该突出部210一侧的侧边。
例如，d/e<0.0273*i*sin(j)/k。
例如，c/b<0.0102*i*sin(j)/k。
该第一侧表面21c被包覆的尺寸与凹陷结构G1深度、凹陷结构G1的底角正相关，与第二导电层202的厚度负相关，在一定范围内使d/e或c/b减小，可以使得过孔V1与凹陷结构G1的交叠减小，从而使得第二导结构22的向下的突出部220的尺寸减小，提高第二导电层22的平坦度。
例如，第一侧表面21c在垂直于衬底基板的方向上的尺寸为n，该第二侧表面部分在垂直于衬底基板100的方向上的尺寸为e。例如，0.1*(n/e)/sin(j)>(d/n)。
第一侧表面21c的尺寸相较于第二侧表面21d的尺寸的比值(n/e)越大，则需要覆盖的面积越大，即n/e与d/n成正比；该凹陷结构G1的底角越大，则该凹陷结构G1的相应侧壁的坡度越大，水汽不容易存留在表面，越不需要覆盖，即sin(j)与d/n成反比。根据n/e和sin(j)的数值，调整d/n的数值，使得第一导电结构裸露的侧表面得到足够的保护，减少水汽的腐蚀，提高第一导电结构的工作寿命。
例如，0.08*(n/e)/sin(j)>d/n。
通过上述设置，可以使得第一侧表面21c被包覆的尺寸更小，从而提高第二导电结构22的平坦度。
在一个示例中，b＝2.821um，c＝0.599um，c/b＝0.212，d＝0.3339um，e＝0.5872um，d/e＝0.569。
在另一个示例中，b＝2.816um，c＝0.6465，c/b＝0.2296，d＝0.5603um，e＝0.8477，d/e＝0.661um。
图3为本公开另一些实施例提供的显示基板的示意图。如图3所示，第一绝缘层301还包括与凹陷结构G1间隔的凹陷结构G3(本公开第二凹陷结构的一个示例)，该凹陷结构G2可以贯穿或者不贯穿该第一绝缘层301。例如，如图3所示，该凹陷结构G2可以是过孔；在另一些示例中，该凹陷结构G2还可以是凹槽。本公开对于该凹陷结构G2的具体结构不作限制。
如图3所示，例如，该第一导电结构21还包括凹陷结构G4。例如，该凹陷结构G4因该第一导电结构21覆盖该凹陷结构G3而形成，该第一导电结构21填充入该第凹陷结构G3而形成该凹陷结构G4。在垂直于衬底基板100的方向上，凹陷结构G3与凹陷结构G4至少部分重叠。
如图3所示，该第一导电结构21还包括位于其底表面21a和顶表面21b之间的第二侧表面21e，该第二侧表面21e与该第一侧表面21c相对。例如，该第二侧表面21e与该第一侧表面21c由该顶表面21b连接。
例如，该第二侧表面21e在衬底基板上的正投影与凹陷结构G3在衬底基板上的正投影至少部分重叠。该第一过孔V1还暴露第二侧表面21e的至少部分，该第二导电结构22还包覆该第一导电结构21的第二侧表面21e的至少部分。
该凹陷结构G1和凹陷结构G3分别位于该过孔V1的两侧，且均与该过孔V1在垂直于衬底基板的方向上至少部分重叠，使得第二绝缘层302下凹分别暴露出该第一侧表面21c和第二侧表面21e的一部分，也即该第一导电结构21在该过孔V1中呈向上凸起的形貌，该第二导电结构23与该第一导电结构的顶表面21b、第一侧表面21c和第二侧表面21e均接触，从而进一步提高了接触面积，降低了接触电阻并提高了屏蔽能力和保护能力。
例如，在图3所示的截面内，第一导电结构21的第一侧表面21c被第二导电结构22覆盖的部分的尺寸与其第二侧表面21e被该第二导电结构22覆盖的部分的尺寸不同。
例如，如图3所示，该过孔V1在衬底基板上的正投影与该凹陷结构G1在在衬底基板上的正投影的重叠面积和该过孔V1在衬底基板上的正投影与该 凹陷结构G2在衬底基板上的正投影的重叠面积不同。
例如，如图3所示，在平行与衬底基板板面的参考方向F上，该过孔V1在衬底基板上的正投影与该凹陷结构G1在在衬底基板上的正投影的重叠尺寸c1和该过孔V1在衬底基板上的正投影与该凹陷结构G2在衬底基板上的正投影的重叠尺寸c2不同。
图4为本公开至少一实施例提供的显示基板的平面示意图，图2和图3所示的剖面结构例如可以为图4所示显示基板的剖面结构。
如图4所示，该显示基板20包括显示区110和显示区110外的非显示区103。例如，非显示区103位于显示区110的外围区域。该显示基板20包括位于显示区110中的多个子像素P。例如，该多个子像素成阵列排布，例如沿第一方向D1和第二方向D2排列多个像素行和多个像素列。该第一方向D1和第二方向D2不同，例如二者正交。例如，该像素行和像素列并不一定严格地沿直线延伸，也可以沿着曲线(例如折线)延伸，该曲线总体上分别沿着第一方向D1或第二方向D2延伸。
每个子像素包括驱动发光元件发光的像素电路，多个像素电路沿第一方向D1和第二方向D2排列为阵列。例如，子像素按照传统的RGB的方式构成像素单元以实现全彩显示，本公开对子像素的排列方式及其实现全彩显示的方式不作限制。
例如，如图4所示，该显示基板20还包括位于显示区110中的沿第一方向D1延伸的导线(例如栅线11)和沿第二方向D2延伸的多条导线(例如数据线12)，该多条横向导线和多条纵向导线彼此交叉，在显示区110中定义出多个像素区，每个像素区中对应设置一个子像素100。图2中只是示意出了栅线11、数据线12以及子像100在显示基板中的大致的位置关系，具体可以根据实际需要进行设计。
该像素电路例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路。并且不同的实施例中，该像素电路还可以进一步包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示基板还可以包括位于非显示区中的栅极驱动电路13和数据驱动电路14。该栅极驱动电路13通过栅线11与像素电路连接以提供各种扫描信号，该数据 驱动电路14通过数据线12与像素电路连接以提供数据信号。图4中示出的栅极驱动电路13和数据驱动电路14，栅线11和数据线12在显示基板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
例如，显示基板20还可以包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动电路14施加该数据信号，以及控制栅极驱动电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。图5A示出了一种像素电路的示意图。
如图5A所示，该像素电路包括驱动子电路122、数据写入子电路126和补偿子电路128。
例如，该驱动子电路122包括控制端(也即控制电极)122a、第一端122b和第二端122c，且配置为与发光元件120连接并且配置为根据该控制电极上的电压控制用于驱动发光元件120的驱动电流。驱动子电路122的控制端122a和第一节点N1连接，驱动子电路122的第一端122b和第二节点N2连接，驱动子电路122的第二端122c和第三节点N3连接。
例如，数据写入子电路126与驱动子电路122连接并配置为响应于第一扫描信号将数据信号写入驱动子电路122的第一端122b。例如，如图5A所示，该数据电路126包括控制端126a、第一端126b和第二端126c，该控制端126a 配置为接收第一扫描信号Ga1，第一端126b配置为接收数据信号Vd，第二端126c与驱动子电路122的第一端122b(也即第二节点N2)连接。该数据写入子电路126配置为响应于该第一扫描信号Ga1将该数据信号Vd写入驱动子电路122的第一端122b。例如，数据写入子电路126的第一端126b与数据线12连接以接收该数据信号Vd，控制端126a与作为扫描线的栅线11连接以接收该第一扫描信号Ga1。例如，在数据写入及补偿阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端122b(第二节点N2)，并将数据信号存储，以在例如发光阶段时可以根据该数据信号生成驱动发光元件120发光的驱动电流。
例如，补偿子电路128与驱动子电路122连接并配置为响应于第二扫描信号对驱动子电路122进行补偿，该第二扫描信号可以与第一扫描信号相同或者不同。例如，如图5A所示，该补偿子电路128包括控制端128a、第一端128b和第二端128c，补偿子电路128的控制端128a配置为接收第二扫描信号Ga2，补偿子电路128的第一端128b和第二端128c分别与驱动子电路122的第二端122c和控制端122a电连接，补偿子电路128配置为响应于该第二扫描信号Ga2对该驱动子电路122进行阈值补偿。
例如，该像素电路还包括存储子电路127、第一发光控制子电路123、第二发光控制子电路124及第一复位子电路125和第二复位子电路129。
例如，第一扫描信号Ga1可以与第二扫描信号Ga2相同。例如第一扫描信号Ga1可以与第二扫描信号Ga2连接到相同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2通过相同的扫描线传输。
在另一些示例中，第一扫描信号Ga1也可以与第二扫描信号Ga2不同。例如，第一扫描信号Ga1可以与第二扫描信号Ga2连接到不同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2分别通过不同的扫描线传输。
存储子电路127包括第一端(也称第一存储电极)127a和第二端(也称第二存储电极)127b，该存储子电路的第一端127a配置为接收第一电源电压VDD，存储子电路的第二端127b与驱动子电路的控制端122a电连接。例如，在数据写入及补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中；同时，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储 子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，存储子电路127与驱动子电路122的控制端122a及第一电压端VDD电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端122b(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号EM1将第一电压端VDD的第一电源电压施加至驱动子电路122的第一端122b。例如，如图5A所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光元件120的第一端134以及驱动子电路122的第二端122c连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光元件122。
例如，在发光阶段，第二发光控制子电路123响应于第二发光控制端EM2提供的第二发光控制信号EM2而开启，从而驱动子电路122可以通过第二发光控制子电路123与发光元件120电连接，从而驱动发光元件120在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路123响应于第二发光控制信号EM2而截止，从而避免有电流流过发光元件120而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动子电路122以及发光元件120进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同，例如第二发光控制信号EM2可以与第一发光控制信号EM连接到相同的信号输出端，例如，第二发光控制信号EM2可以与第一发光控制信号EM通过相同的 发光控制线传输。
在另一些示例中，第二发光控制信号EM2可以与第一发光控制信号EM1不同。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别连接到不同的信号输出端。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别通过不同的发光控制线传输。
例如，第一复位子电路125与第一复位电压端Vinit1以及驱动子电路122的控制端122a(第一节点N1)连接，且配置为响应于第一复位控制信号Rst1将第一复位电压Vinit1施加至驱动子电路122的控制端122a。
例如，第二复位子电路129与第二复位电压端Vinit2以及发光元件122的第一端122b(第四节点N4)连接，且配置为响应于第二复位控制信号Rst2将第二复位电压Vinit2施加至发光元件120的第一端134。例如，该第一复位电压Vinit1与该第二复位电压Vinit2可以是相同的电压信号或者不同的电压信号。例如，该第一复位电压端Vinit1和第二复位电压端Vinit2连接到同一个复位电压源端(例如位于非显示区)以接收相同的复位电压。
例如，第一复位子电路125和第二复位子电路129可以分别响应于第一复位控制信号Rst1和第二复位控制信号Rst2而开启，从而可以将分别将第二复位电压Vinit2施加至第一节点N1以及将第一复位电压Vinit1施加至发光元件120的第一端134，从而可以对驱动子电路122、补偿子电路128以及发光元件120进行复位操作，消除之前的发光阶段的影响。
例如，每行子像素的第二复位控制信号Rst2可以与该行子像素的第一扫描信号Ga1为相同的信号，二者可以通过同一栅线11传输。例如，每行子像素的第一复位控制信号Rst1可以与上一行子像素的第一扫描信号Ga1，二者可以通过同一栅线11传输。
例如，发光元件120包括第一端(也称作第一电极或像素电极)134和第二端(也称作第二电极)135，发光元件120的第一端134与第四节点连接，发光元件120的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图5A所示，驱动子电路122的第二端122c可以通过第二发光控制子电路124连接至第四节点N4。本公开的实施例包括但不限于此情形。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst1、Rst2既可以表示复位控制端又可以表示复位控制信号，符号Vinit1、Vinit2既可以表示第一复位电压端和第二复位电压端又可以表示第一复位电压和第二复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图5B为图5A所示的像素电路的一种具体实现示例的电路图。如图5B所示，该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。
例如，如图5B所示，驱动子电路122可以实现为第一晶体管T1(也即驱动晶体管)。第一晶体管T1的栅极作为驱动子电路122的控制端122a，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端122b，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端122c，和第三节点N3连接。
例如，如图5B所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，如图5B所示，补偿子电路128可以实现为第三晶体管T3(也即补偿晶体管)。第三晶体管T3的栅极、第一极和第二极分别作为该补偿子电路的控制端128a、第一端128b和第二端128c。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第三晶体管T3的第二极和驱动子电路122的控制端122a(第一节点N1)连接。例如，如图5B所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极Ca和第二电容电极Cb，该第一电容电极Ca和第一电压端VDD连接，该第二电容电极Cb和驱动子电路122的控制端122a连接。
例如，如图5B所示，第一发光控制子电路123可以实现为第四晶体管T4。 第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，发光元件120具体实现为发光二极管(LED)，例如可以是有机发光二极管(OLED)、量子点发光二极管(QLED)或者无机发光二极管，例如可以是微型发光二极管(Micro LED)或者微型OLED。例如，发光元件120可以为顶发射结构、底发射结构或双面发射结。该发光元件120可以发红光、绿光、蓝光或白光等。本公开的实施例对发光元件的具体结构不作限制。
例如，该发光元件120包括第一电极134、第二电极135以及夹设于第一电极134和第二电极135之间的有机功能层，该有机功能层包括发光层，根据需要，该有机功能层还可以包括空穴注入层、空穴传输层、电子注入层、电子传输层等。
例如，发光元件120的第一电极134(也称像素电极，例如为阳极)和第四节点N4连接配置为通过第二发光控制子电路124连接到驱动子电路122的第二端122c，发光元件120的第二电极135(例如为阴极)配置为和第二电压端VSS连接以接收第二电源电压VSS，从驱动子电路122的第二端122c流入发光元件120的电路决定发光元件的亮度。例如第二电压端可以接地，即VSS可以为0V。例如，第二电压电源电压VSS可以为负电压。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第五晶体管T5的第二极和发光元件120的第一端134(第四节点N4)连接。
例如，第一复位子电路125可以实现为第六晶体管T6，第二复位子电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位控制信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位控制信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点 N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。例如，如图5B所示，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本公开实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系即可。
以下结合图5C所示的信号时序图，对图5B所示的像素电路的工作原理进行说明。如图5C所示，每一帧图像的显示过程包括三个阶段，分别为初始化阶段1、数据写入及补偿阶段2和发光阶段3。
如图5C所示，在本实施例中，第一扫描信号Ga1和第二扫描信号Ga2采用同一信号，第一发光控制信号EM1和第二发光控制信号EM2采用同一信号；且第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即第二复位控制信号Rst2、第一扫描信号Ga1/第二扫描信号Ga2可以采用同一信号；本行子像素的第一复位信号Rst1与上一行子像素的第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即采用同一信号。然而，这并不作为对本公开的限制，在其它实施例中，可以采用不同的信号分别作为第一扫描信号Ga1、第二扫描信号Ga2、第一复位控制信号Rst1、第二复位控制信号Rst2，采用不同的信号分别作为第一发光控制信号EM1和第二发光控制信号EM2。
在初始化阶段1，输入第一复位控制信号Rst1以开启第六晶体管T6，将第一复位电压Vinit1施加至第一晶体管T1的栅极，从而对该第一节点N1复位。
在数据写入及补偿阶段2，输入第一扫描信号Ga1、第二扫描信号Ga2以及数据信号Vd，第二晶体管T2和第三晶体管T3开启，数据信号Vd由第二晶体管T2写入第二节点N2，并经过第一晶体管T1和第三晶体管T3对第一节点 N1充电，直至第一节点N1的电位变化至Vd+Vth时第一晶体管T1截止，其中Vth为第一晶体管T1的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在数据写入及补偿阶段2，还可以输入第二复位控制信号Rst2以开启第七晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Rst1和第二复位控制信号Rst2可以相同。本公开实施例对此不作限制。
在发光阶段3，输入第一发光控制信号EM1和第二发光控制信号EM2以开启第四晶体管T4、第五晶体管T5和第一晶体管T1，第五晶体管T5将驱动电流施加至OLED以使其发光。流经OLED的驱动电流I的值可以根据下述公式得出：
I＝K(VGS-Vth) 2＝K[(Vdata+Vth-VDD)-Vth] 2＝K(Vdata-VDD) 2，其中，K为第一晶体管的导电系数。
在上述公式中，Vth表示第一晶体管T1的阈值电压，VGS表示第一晶体管T1的栅极和源极(这里为第一极)之间的电压，K为与第一晶体管T1本身相关的一常数值。从上述I的计算公式可以看出，流经OLED的驱动电流I不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I的影响，从而可以改善采用其的显示装置的显示效果。
以下以图5B所示像素电路为例、并结合图6A-6B、图7、图8A-图8C、图9A-9C和图10A对本公开至少一实施例提供的显示基板的结构进行示例性说明。
图6A为本公开至少一个实施例提供的显示基板20的示意图,图6B为图6A沿剖面线A-A’的剖视图。需要说明的是，为了清楚起见，图6B省略了一些在剖面线处不存在直接电连接关系的结构；为了方便对照，图8B和9B中也示出了剖面线A-A’的位置。
如图6A所示，该显示基板20包括衬底基板100，多个子像素P位于该衬 底基板100上。多个子像素P的像素电路布置为像素电路阵列，例如，该像素电路阵列的行方向为第一方向D1，列方向为第二方向D2。在一些实施例中，各子像素的像素电路可以具有完全相同的结构，即像素电路在行和列方向重复排列。
为了方便说明，图6A中示例性地示出了两行五列子像素。例如，如图6A所示，子像素的像素电路的排列规则与其上方的像素电极(也即发光元件的第一电极)的排列规则可以相同也可以不同，为了方便说明，这里子像素的排列的描述参照像素电路的排列规则，子像素的相对位置关系的描述参照该子像素的像素电路的相对位置，例如，相邻的子像素是指像素电路相邻的子像素。以下各实施例与此相同，不再赘述。
结合图6A-6B可知，半导体层102、绝缘层401、导电层501、绝缘层402、导电层502、绝缘层403、导电层503、绝缘层404、导电层504依次设置于衬底基板100上，从而形成如图6A所示的显示基板的结构。
图7对应于图6A示意出了半导体层102和导电层501，图8A和图8C示出了导电层502的图案，图8B在图7的基础上示出了该导电层502；图9A示出了导电层503，图9B在图8B的基础上示出了该导电层503；图10A示出了导电层504。
为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和沟道区，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成，而并不一定位于同一水平面；它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，如图7所示，该导电层501包括每个晶体管的栅极以及一些扫描线和控制线。该半导体层102包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图7所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层102为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔。
例如，如图7所示，该导电层501包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，该显示基板20采用自对准工艺，利用第一导电层201作为掩 膜对该半导体层102进行导体化处理(例如掺杂处理)，使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。
例如，如图7所示，第三晶体管T3和第六晶体管T6分别采用双栅结构，包括第一栅极和第二栅极，这样可以提高晶体管的栅控能力，降低漏电流。由于第三晶体管T3和第六晶体管T6都是与第一晶体管T1(也即驱动晶体管)的栅极(也即第一节点N1)直接连接的晶体管，因此，该第三晶体管T3和第六晶体管T6的稳定性直接影响着第一晶体管T1的栅极(N1节点)电压的稳定性。采用双栅结构提高第三晶体管T3和第六晶体管T6的栅控能力，有助于降低晶体管的漏电流从而有助于保持N1节点的电压，从而在补偿阶段，第一晶体管T1的阈值电压有助于得到充分补偿，进而提高发光阶段显示基板的显示均一性。
如图7所示，该第三晶体管T3包括第一栅极T3g1和第二栅极T3g2以及分别对应于该第一栅极g1和第二栅极T3g2的第一沟道区和第二沟道区；也就是说，该第三晶体管的有源层包括第一部分、第二部分和第三部分，该第一部分在衬底基板上的正投影与第一栅极T3g1在衬底基板的正投影交叠，第二部分在衬底基板上的正投影与第二栅极T3g1在衬底基板的正投影交叠。例如，该第一栅极T3g1位于控制该第三晶体管T3的扫描线220的主体部上，该第二栅极T3g2为从该扫描线220的主体部沿第二方向D2突出的突出部。该第三晶体管T3的有源层还包括第三部分(本公开半导体图案的一个示例)，第三部分位于该有源层的第一部分和第二部分之间且将第一部分和第二部分连接，该第三部分位于该第一栅极T3g1和第二栅极T3g2之间，由于未被栅极图案遮挡而被导体化成为导电区T3c。该导电区T3c与该第三晶体管T3的第一极T3s被该第三晶体管T3的第一沟道区间隔，该导电区T3c与该第三晶体管T3的第二极T3d被该第三晶体管T3的第二沟道区间隔，该导电区T3c与该第三晶体管T3的第一沟道区、第二沟道区为一体的结构，例如均包括多晶硅材料。类似地，第六晶体管T6也包括位于第一栅极T6g1和第二栅极T2g之间的导电区T6c。
例如，该第一导电层201还包括彼此绝缘的多条扫描线210、多条复位控制线220和多条发光控制线230。这些信号线均可以作为图4所示的栅线11的示例。
扫描线210与对应一行子像素中的第二晶体管T2的栅极T2g电连接(或 为一体的结构)以提供第一扫描信号Ga1，复位控制线220与对应一行子像素中的第六晶体管T6的栅极T6g电连接以提供第一复位控制信号Rst1，发光控制线230与对应一行子像素中的第四晶体管T4的的栅极T4g电连接以提供第一发光控制信号EM1。
例如，如图7所示，该扫描线210还与第三晶体管T3的栅极电连接以提供第二扫描信号Ga2，即第一扫描信号Ga1和第二扫描信号Ga2可以为同一信号；该发光控制线230还与第五晶体管T5的栅极T5g电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，例如该第一栅极T3g1沿第一方向D1延伸，为扫描线210的一部分。该第二栅极T3g2沿第二方向D2延伸，为扫描线210沿第二方向D2延伸的延伸部。
例如，如图7所示，本行像素电路的第七晶体管T7的栅极与下一行像素电路(即按照扫描线的扫描顺序，在本行扫描线之后顺序开启的扫描线所在的像素电路行)所对应的复位控制线220电连接以接收第二复位控制信号Rst2。
例如，如图8A所示，该导电层502包括第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板100的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括开口222，该开口222暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。例如，位于同一像素行的子像素的第一电容电极Ca彼此连接为一体的结构。
例如，该导电层502还可以包括沿第一方向D1延伸的多条复位电压线240，该多条复位电压线240与多行子像素一一对应连接。该复位电压线240与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，如图8B所示，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应的的复位电压线240电连接以接收第二复位电压Vinit2。后文将结合图9B对此进行详细描述。
例如，如图8A-8B所示，该导电层502还可以包括屏蔽电极221。例如，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底基板100的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。由于该第二晶体管T2的第一极T2s配置为接收数据信号Vd，而该数据 信号Vd决定了该子像素的显示灰阶，因此该屏蔽电极221提高了数据信号的稳定性，从而提高了显示性能。
例如，结合参考图8B和图6B，该屏蔽电极221还与第六晶体管T6的第二极T6d在垂直于衬底基板100的方向上至少部分重叠，以提高该第二极T6d上信号的稳定性，从而提高第六晶体管T6的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，如图8B所示，该屏蔽电极221还延伸至在第一方向D1上与该屏蔽电极211所属的子像素相邻的子像素并与相邻的子像素中的第三晶体管T3的导电区T3c在垂直于衬底基板100的方向上至少部分重叠，以提高该导电区T3c中信号的稳定性，从而提高第三晶体管T3的稳定性，进一步稳定了第一晶体管T1的栅极电压。
如图8B所示，该屏蔽电极221的第一遮挡部221a包括第一子部a1和第二子部a2，该第一子部a1在衬底基板上的正投影与相邻子像素的第三晶体管的导电区T3c在衬底基板上的正投影交叠，第二子部a2在衬底基板上的正投影与该导电区T3c在衬底基板上的正投影不交叠，该第一子部导电区T31在第二方向D2上的尺寸大于第二子部a2在第二方向上的尺寸。这种设置可以有助于该第一子部a1的的遮挡面积和遮挡效果。
例如，该屏蔽电极221和与之正对(重叠)的第二晶体管T2的第一极T2s及第六晶体管T6的第二极T6d形成稳定电容。该屏蔽电极221配置为加载固定电压，由于电容两端的压差不能突变，因此提高了第二晶体管T2的第一极T2s、第三晶体管T3的导电区T3c及第六晶体管T6的第二极T6d上电压的稳定性。例如，该屏蔽电极221与导电层503中的电源线250电连接以加载第一电源电压VDD。
例如，该屏蔽电极221为L形、V形或者T形，如图8A所示，该屏蔽电极221为L形，包括延伸方向不同的第一遮挡部221a和第二遮挡部221b。该第二遮挡部221b与第六晶体管T6的第二极T6d在垂直于衬底基板100的方向上至少部分重叠；该第一遮挡部221a分别与第二晶体管T2的第一极T2s以及相邻的子像素中的第三晶体管T3的导电区T3c在垂直于衬底基板100的方向上至少部分重叠从而对该导电区T3形成遮挡以提高晶体管的稳定性。例如，该第二遮挡部221b沿第二方向D2延伸，该第一遮挡部221a沿第一方向D1延伸。
图8C为导电层502的另一个示例的平面示意图。图8C所示实施例与图8A所示实施例的主要不同之处在于其屏蔽电极221与第一电容电极Ca彼此连接为一体的结构。如图8C所示，该屏蔽电极221的第二遮挡部221b从第一电容电极Ca沿第二方向D2延伸出来，第一遮挡部221a从第二遮挡部221b沿第一方向D1延伸出来，该第二遮挡部221b向下延伸至第一电容电极Ca并与第一电容电极Ca连接为一体的结构。所述第一遮挡部与第二遮挡部连接的位置位于所述第二遮挡部在第二方向的中间位置，也即该屏蔽电极为T形。
由于第一电容电极Ca配置为与电源线250电连接，上述设置使得屏蔽电极221通过同层的第一电容电极Ca连接到电源线250，从而避免了过孔341的设置，简化了设计。例如，如图9A-9B所示，导电层503包括沿第二方向D2延伸的多条电源线250，该多条电源线250与第一电压端VDD连接以传输第一电源电压VDD。例如，该多条电源线250与多列子像素一一对应电连接以提供第一电源电压VDD。该电源线250通过过孔342与所对应的一列子像素中的第一电容电极Ca电连接，通过过孔343与第四晶体管T4的第一极T4s电连接。例如，该电源线250还通过过孔341与屏蔽电极221电连接，从而使得屏蔽电极221具有固定电位，提高了该屏蔽电极的屏蔽能力。例如，该过孔342和过孔341均贯穿第三绝缘层303，该过孔343贯穿绝缘层401、绝缘层402和绝缘层403。
例如，该导电层503还包括沿第二方向D2延伸的多条数据线12。例如，该多条数据线12与多列子像素一一对应电连接以提供数据信号Vd。例如，该数据线12与所对应的一列子像素中的第二晶体管T2的第一极T2s通过过孔346电连接以提供该数据信号。例如，该过孔346贯穿绝缘层401、绝缘层402和绝缘层403。例如，结合图6A-6B、图9A-9B所示，该导电层503还包括连接电极231，该连接电极231的一端通过第一电容电极Ca中的开口222以及绝缘层中的过孔344与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔345与该第三晶体管T3的第二极T3d电连接，从而将该第二电容电极Cb与该第三晶体管T3的第二极T3d电连接。例如，该过孔344贯穿绝缘层402和绝缘层403。例如，该过孔345贯穿绝缘层401、绝缘层402和绝缘层403。
如图9B所示，连接电极231在衬底基板上的正投影与屏蔽电极221的第二遮挡部221b在衬底基板上的正投影在第一方向D1上至少部分交叠，也即沿 着第一方向D1看过去，该连接电极231的正投影与该第二遮挡部221b的正投影至少部分交叠。
如图9B所示，该连接电极231与其两侧的屏蔽电极221的第二遮挡部221b均存在这种交叠关系。
通过上述设置，可以有效提高第二遮挡部对连接电极231的屏蔽保护作用，例如可屏蔽部分突变信号，避免突变信号影响连接电极231的电位而进而影响到驱动晶体管栅极的电位。
例如，如图9B所示，第二遮挡部221b在衬底基板上的正投影位于连接电极231在衬底基板上的正投影和数据线12在衬底基板上的正投影之间，从而第二遮挡部221b可屏蔽数据线12的突变信号，降低突变信号对连接电极231的电位的影响。
例如，结合参考图8C和图9B，连接电极231在衬底基板上的正投影在第二方向D2上位于第一电容电极Ca和屏蔽电极221所构成的一体结构在衬底基板上的正投影的范围之内。如此一来，当该屏蔽电极221为图8C所示构造时，该屏蔽电极221和第一电容电极Ca共同构成一道屏蔽墙，可以有效提高对连接电极231的信号屏蔽及保护作用。例如，结合图6A-6B、图9A-9B所示，该导电层503还包括连接电极232，该连接电极232通过过孔349与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d通过过孔350与发光元件的像素电极134电连接。例如，该过孔349贯穿绝缘层401、绝缘层402和绝缘层403。
例如，如图9A-9B所示，该导电层503还包括连接电极233，该连接电极233的一端通过过孔348与复位电压线240电连接，另一端通过过孔347与第六晶体管T6的第一极T6s电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔348贯穿绝缘层403。例如该过孔347贯穿绝缘层401、绝缘层402和绝缘层403。
在另一些示例中，如图9C所示，半导体层102包括连接部104，该连接部104经导体化后成为导体，连接部将复位电压线240(本公开第一复位电压线的一个示例)与子像素中的复位晶体管(也即第六晶体管T6)的第一极T6s电连接。这种设置可以免去连接电极232和过孔347的设置，从而简化设计。
例如，所述连接部在所述衬底基板上的正投影与复位电压线240在衬底基板上的正投影以及该复位晶体管的第一极T6s在衬底基板的正投影均交叠。
例如，如图9B-9C所示，上一行子像素中的第七晶体管T7的第一极与本行子像素中的第六晶体管T6的第一极电连接，并与本行子像素所对应的复位电压线240(也即图9B中最上方的那条复位电压线240)电连接以接收第二复位电压Vinit2，本行子像素中的第七晶体管T7的第一极与下一行子像素中的第六晶体管T6的第一极电连接，并与下一行子像素所对应的复位电压线240(也即图9B中间的那条复位电压线240)电连接以接收第二复位电压Vinit2。
如图9A-9B所示，该导电层503还包括沿第二方向D2延伸的多条复位电压线260。如图9B所示，每条复位电压线260通过过孔351与导电层502中的复位电压线240电连接，从而形成横纵交织的网状导电结构，该网状导电结构可以降低电阻，从而降低电压降，有助于降复位电压均一地传递到基板上的各个子像素。
例如，如图9B所示，每两条相邻的复位电压线260之间间隔两列子像素，也即该复位电压线260与子像素列并非一一对应设置，这样可以降低布线密度。例如，在相邻两列子像素之间的一组信号线中，该复位电压线260和电源线250分别与数据线12直接相邻，并分别位于该数据线12的两侧，复位电压线260位于该数据线12远离与该数据线12电连接的子像素列的一侧。
结合图6A-6B和图10A所示，导电层504包括发光元件的第一电极(也即像素电极)134。各子像素的发光元件的第一电极134通过过孔350与该子像素中的连接电极232电连接，从而通过该连接电极233与第五晶体管T5的第二极T5d电连接。该过孔350例如贯穿绝缘层504。图10A中用圆形示意性地示出了该第一电极134中与过孔350接触的接触区。
例如，参考图6A-6B，该显示基板20还可以包括位于发光元件的第一电极上的像素界定层405。像素界定层405中形成开口暴露出像素电极134的至少部分从而界定显示基板各个子像素的像素开口区(即有效发光区)600。发光元件120的有机功能层136至少形成于该开口内，第二电极135形成于有机功能层136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如第一电极134为发光元件的阳极，第二电极135为发光元件的阴极。图10A中用矩形示意性地示出了各子像素的像素开口区600，然而这并不作为对本公开的限制。
如图10A所示，该导电层504还可以包括沿第一方向D1延伸的多条复位电压线270，该复位电压线270例如为折线结构，例如为沿第一方向D1延伸的 Z状，这是为了与第一电极134的形状相匹配从而便于布线。
例如，该复位电压线270与复位电压线260和/或复位电压线240并联，进一步降低复位电压线的电阻从而降低复位电压线上的电压降。例如，该复位电压线270与复位电压线260和/或复位电压线240在非显示区电连接。该复位电压线270不是必须的。
需要说明的是，本公开实施例提供的显示基板的发光元件的第一电极的分布并不限于图10A所示的情形，而同样适用于其它的像素电极的分布。图10B为本公开另一些实施例提供的发光元件的第一电极134的分布图，图10C示出了该第一电极与下方像素电路的连接关系。
如图10B所示，每四个第一电极134构成一个电极组，该电极组中的四个第一电极134分别对应1个蓝像素、1个红像素和2个绿像素，该2个绿像素在第一方向上相对设置，该蓝像素和红像素在第二方向上相对设置。例如，如图10B所示，红像素的过孔350与对应的过孔349在垂直于衬底基板的方向不重叠。
该2个绿像素具有相同的形状和面积，并且蓝像素、绿像素和红像素的面积各不相同。例如，效率最低的蓝色子像素的面积最大，效率最高的红色子像素面积最小，以实现更好的色彩强度和图像清晰度。
例如，各导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等；或者多层金属的叠层结构；或者金属与导电金属氧化物的叠层结构。
例如，导电层504包括TI/AL/TI的叠层结构。
例如，导电层505的材料为透明导电材料，例如为金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。例如，导电层505包括ITO/AG/ITO的叠层结构。
例如，该发光元件120为顶发射结构，第一电极(即像素电极)134具有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为阳极，第二电极135为阴极。例如，第一电极134为ITO/Ag/ITO叠层结构,透明导电材料ITO为高功函数的材料，与发光材料直接接触可以提高空穴注入率；金属材料Ag有助于提高第一电极的反射率。例如；第二电极135为低功函数的材 料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，各绝缘层的材料例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。
例如，像素界定层405的材料为有机材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。
例如，衬底基板100可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层102的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该显示基板20包括图2所示的结构，在本实施例中，以将图2所示的连接结构设置在第一电极134与连接电极232的连接处为例进行示例性说明，然而这并不作为对本公开的限制。
结合参考图6A-6B，该连接电极232(本公开第一导电结构的一个示例)包括靠近衬底基板的底表面232a、远离衬底基板的顶表面232b以及位于该底表面232a和顶表面232b之间的第一侧表面232c。连接电极232通过过孔350(本公开第一过孔的一个示例)与发光元件的第一电极314(本公开第二导电结构的一个示例)电连接。过孔350与过孔349(本公开第一凹陷结构的一个示例)在垂直于衬底基板的方向上至少部分重叠，使得绝缘层404(本公开第二绝缘层的一个示例)向下凹陷，过孔350暴露该连接电极232的第一侧表面232c的至少部分，并使得发光元件的第一电极314向下凹陷并包括突出部314a(本公开第一突出部的一个示例)，该突出部314a与该第一侧表面232c的至少部分接触，覆盖该第一侧表面232c被该过孔350暴露的部分。
如图6A-6B所示，该连接电极232以及该第一电极134与该连接电极232直接接触的部分均位于两侧的信号线之间。
如图6A-6B所示，该突出部314a位于所述的子像素所在的像素列(本公 开第一像素列的一个示例)两侧的信号线之间，也即位于左侧的第一信号线和右侧的第二信号线之间，该第一信号线例如为与该子像素连接的数据线12或电源线250，该第二信号线例如为右侧的复位电压线260、数据线12或电源线250，该右侧的数据线12和电源线250和与该像素列相邻的像素列(本公开第二像素列的一个示例)连接；也即该突出部314a在衬底基板100上的正投影位于该第一信号线与在该衬底基板上的正投影与该第二信号线在该衬底基板上的正投影之间。
如图6A所示，该第一像素列的发光元件的第一电极134在衬底基板上的正投影分别与其左侧的电源线250在衬底基板上的正投影及其右侧的数据线12在衬底基板上的正投影至少部分重叠。
如图6B所示，所述第一像素列的发光元件靠近所述衬底基板一侧的电极在所述衬底基板上的正投影分别与所述第一信号线在所述衬底基板上的正投影及所述第二信号线在所述衬底基板上的正投影分别至少部分重叠。
通过将第一电极134的突出部134a设置为与连接电极232的第一侧表面232c接触，不仅提高了第一电极134与连接电极232的接触面积，降低了二者的接触电阻，还有效提高了该第一电极134的纵向截面积，同时将该突出部134a设置在第一信号线与第二信号线之间，还可以降低第一信号线与第二信号线之间的互相干扰。例如，由于数据线中传输的为高频信号，容易对其它信号线中的信号造成干扰。例如，该突出部134a可以降低一侧的数据线12对另一侧的信号线(如数据线、电源线、复位电压线等)中信号的干扰。
参照图2和图6A-6B，图2所示的结构可以看作显示基板20沿剖面线A-A’的剖面结构的一部分，也即图6B中用虚线圈出的结构，图6B中的连连接电极232、第一电极134、突出部134a、过孔350、过孔349可以分别看作图2中的第一导电结构21、第二导电结构22、突出部220、过孔V1以及凹陷结构G1。对于图2的描述同样适用于图6B，此处不再赘述。
例如，如图6A-6B所示，该连接电极232包括朝向过孔349的突出部232t，该突出部232t在衬底基板上的正投影位于过孔349在衬底基板上的正投影内。
如图6A所示，该突出部134a在衬底基板上的正投影与左侧的电源线250(本公开第一信号线的一个示例)衬底基板上的正投影在参考方向F(例如为第一方向D1)上的距离为l，该参考方向F与衬底基板的板面平行，例如与第一方向D1平行。例如，测量的时候可以取该突出部134a的最低点进行测量。 右侧的数据线12(本公开第二信号线的一个示例)在衬底基板上的正投影与该电源线250在衬底基板上的正投影在该第参考方向F上的距离为m。
在图6B所示的截面内，该连接电极232位于绝缘层403的远离衬底基板一侧的部分在垂直于衬底基板的方向上的尺寸为e，该第一侧表面232c被该突出部134a包覆的部分在垂直于衬底基板的方向上的尺寸为d。例如，l/m>0.9(d/e)。例如，l/m>1.2*(d/e)。
突出部134a相对于电源线250的距离越远，则屏蔽右侧数据线12对该左侧电源线250的效果越差，则需要更多地对该第一侧表面232c进行覆盖。通过上述设置，可以保证该突出部134a可以较好地屏蔽数据线12对电源线250上信号的干扰。
例如，如图6A-6B所示，多个像素开口区600在衬底基板上的正投影与与突出部134a在衬底基板上的正投影分离，也即不重叠，从而避免了突出部134a的设置引起有效发光区(也即像素开口区)中发光材料的不平坦而导致的色偏等显示不良现象。
图11为本公开另一些实施例提供的显示基板的示意图，图中示出了导电层504以及过孔349、过孔350在衬底基板上的正投影，图中示意性地用空心圆示出了过孔350、用实心圆示出了过孔349。
如图11所示，绝缘层403包括多个过孔349，该多个过孔349与多个子像素一一对应，该多个过孔349沿第一方向D1和第二方向D2排列为多个过孔行和多个过孔列。绝缘层404包括多个过孔350，该多个过孔350与多个子像素一一对应，并与多个过孔349一一对应设置。多个过孔349沿第一方向D1和第二方向D2排列为多个过孔行和多个过孔列。
例如，在每个子像素中过孔349和过孔350的重叠情形不同。如图11所示，子像素P1所在像素列中，过孔349和过孔350在衬底基板上的正投影不重叠，因此不能形成图2或图6B所示的结构。
例如，对于每行子像素，每隔1个子像素存在3个连续相邻的子像素具有如图2或图6B所示的结构；也即对于每行过孔350，每隔一个过孔350则存在3个连续的过孔350，该3个过孔350的每个与对应的过孔349在垂直于衬底基板的方向上重叠，并形成如图2或图6B所示的结构；该1个过孔350与对应的过孔349在垂直于衬底基板的方向不重叠。例如，该1个过孔对应于红色像素。
例如，多列子像素包括一个像素列，该第像素列中的每个子像素均具有如图2或图6B所示的结构(如图11所示的第1、3、4、5列子像素)，或者每隔1个子像素存在1个子像素具有如图2或图6B所示的结构；也即存在一个过孔350列，每个过孔350与对应的过孔349在垂直于衬底基板的方向上重叠，并形成如图2或图6B所示的结构；或者每隔1个过孔350，存在1个过孔350与对应的过孔349在垂直于衬底基板的方向上重叠，并形成如图2或图6B所示的结构。
图12A-12C为本公开另一些实施例提供的显示基板的示意图，图中示出了导电层504、像素界定层405以及过孔349、过孔350在衬底基板上的正投影，图中示意性地用空心圆示出了过孔350、用实心圆示出了过孔349。
该像素界定层405包括多个像素开口区600以及非开口区，例如，该像素界定层405在非开口区又形成了多个间隔的凸起部405a，也即像素界定层405具有不均一的厚度。凸起部405a可以在蒸镀的时候对掩膜板起到支撑作用。在一些示例中，该凸起部也称作隔垫物(spacer)。
如图12A-12C所示，例如，该凸起部为锥状，图12A-12C中示意性地分别用空心椭圆和实心椭圆示出了该凸起部405a的底部和顶部在衬底基板上的正投影。
例如，过孔350在衬底基板上的正投影与像素界定层的最大厚度的部分在所述衬底基板上的正投影(也即该凸起部405a的顶部的正投影)分离，也即不重叠。这种设置可以避免过孔350的设置造成该凸起部405a的顶部的不平坦对其支撑功能造成的不利影响。例如，凸起部405a的不平坦可能导致掩膜板倾斜，从而影响蒸镀形成的有机功能层(包括发光层)的不平。
如图12A-12C所示，该凸起部405a可以有不同的设置密度。例如，1个像素开口区600的周边可以设置1个(如图12A所示)、2个(如图12B所示)或3个(如图12C所示)凸起部405a。可以根据第一电极134之间的空隙确定凸起部的设置密度，密度较大可以提高对掩膜板的支撑稳定性。
如图12C所示，像素开口区600的周边设置有3个凸起部405a，分别是第一凸起部405a1、第二凸起部405a2和第三凸起部405a3，该第一凸起部405a1、第二凸起部405a2和第三凸起部405a3围绕该像素开口区600设置，且在衬底基板上的正投影的中心的连线构成一个三角形。
例如，如图12C所示，该第一凸起部405a1位于相邻的四个像素开口区600 之间，第二凸起部405a2和第三凸起部405a3分别位于相邻的两个像素开口区之间。例如，第一凸起部405a1在衬底基板上的正投影的面积分别大于第二凸起部405a2在衬底基板上的正投影的面积以及第三凸起部405a3在衬底基板上的正投影的面积。
例如，如图9D所示，该显示基板还包括虚拟区(dummy area)，如图9D中左起第一列子像素，该虚拟区中像素结构的设置与显示区的设置基本一致，主要区别在于虚拟区中并不设置有发光元件，也并不存在第一电极134(即第二导电结构)，也即在该列子像素中，第一导电结构在所述衬底基板上的正投影与第二导电层在所述衬底基板上的正投影分离。该虚拟区的设置是为了提高工艺的均一性。
如图9D所示，虚拟区中连接电极232(即第一导电结构)的设置方式与有效显示区中相同，该连接电极232的连接方式也与有效显示区中相同，这里不再赘述。
例如，在这种情形，虚拟区中的子像素列(本公开第三像素列的一个示例，图9D中左起第一列子像素)所对应连接的数据线(本公开第三信号线的一个示例)和电源线(本公开第四信号线的一个示例)彼此电连接，也即该两条信号线中提供相同的信号，例如为电源电压信号，且位于该像素列的同一侧。由于虚拟区并不存在信号彼此干扰的问题，也无需设置该第一电极134的突起部进行屏蔽。
以下以图5B所示像素电路为例、并结合图13A-13B、图14、图15、图16A-16C、图17A-17B、图18A-18C及图19A-19C对本公开另一些实施例提供的显示基板的结构进行示例性说明。
图13A为本公开另一些实施例提供的显示基板20的示意图,图13B为图13A沿剖面线B-B’的剖视图。需要说明的是，为了清楚起见，图13B省略了一些在剖面线处不存在直接电连接关系的结构。
如图13A所示，该显示基板20包括衬底基板100，多个子像素位于该衬底基板100上。多个子像素P的像素电路布置为像素电路阵列，例如，该像素电路阵列的行方向为第一方向D1，列方向为第二方向D2。在一些实施例中，各子像素的像素电路可以具有完全相同的结构，即像素电路在行和列方向重复排列。
为了方便说明，图13A中示例性地示出了四列子像素。例如，如图13A所 示，子像素的像素电路的排列规则与其上方的像素电极(也即发光元件的第一电极)的排列规则可以相同也可以不同，为了方便说明，这里子像素的排列的描述参照像素电路的排列规则，子像素的相对位置关系的描述参照该子像素的像素电路的相对位置，例如，相邻的子像素是指像素电路相邻的子像素。以下各实施例与此相同，不再赘述。
例如，如图13A-13B，该显示基板20包括依次层叠设置于衬底基板100上的半导体层105、绝缘层601、导电层711、绝缘层602、导电层712、绝缘层603、半导体层106、绝缘层604、导电层713、绝缘层605、导电层714、绝缘层606、导电层715、绝缘层607及导电层716。
图14对应于图13A示意出了半导体层105和导电层711(本公开第一金属层的一个示例)，图15在图14的基础上示出了导电层712的图案，图16A在图15的基础上示出了半导体层106和导电层713的图案；图17A示出了导电层714，图17B在图16A的基础上示出了该导电层714；图18A示出了导电层715，图18B在图17B的基础上示出了该导电层715。
为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和沟道区，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成，而并不一定位于同一水平面；它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，如图14所示，该半导体层105包括第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第七晶体管T7的沟道区(T1a、T2a、T4a、T5a、T7a)以及第一极(T1s、T2s、T4s、T5s、T7s)、第二极(T1d、T2d、T4d、T5d、T7d)。
例如，该显示基板20采用自对准工艺，利用导电层711作为掩膜对该半导体层105进行导体化处理(例如掺杂处理)，使得该半导体层105未被该导电层711覆盖的部分被导体化，从而半导体层位于各晶体管的沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。例如，半导体层105的材料为低温多晶硅材料。
例如，如图14所示，该导电层711还包括彼此绝缘的扫描线710、复位控 制线720和发光控制线730。这些信号线均可以作为图4所示的栅线11的示例。
扫描线710与对应一行子像素中的第二晶体管T2的栅极T2g电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线720与对应一行子像素中的第六晶体管T6的栅极T6g电连接以提供第一复位控制信号Rst1，发光控制线730与对应一行子像素中的第四晶体管T4的栅极T4g电连接以提供第一发光控制信号EM1。例如，本行子像素的扫描线710可以作为下一行子像素的复位控制线720。
例如，如图14所示，该发光控制线730还与第五晶体管T5的栅极T5g电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，如图15所示，该导电层712(本公开第二金属层的一个示例)包括第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板100的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括开口722，该开口722暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。例如，位于同一像素行的子像素的第一电容电极Ca彼此连接为一体的结构。
如图15所示，在第一方向D1上相邻的子像素中的开口722的大小不一致，例如，具有较大开口722的子像素为绿像素，具有较小开口722的子像素为红像素或蓝像素。
绿像素与红、蓝像素的起亮电压与数据信号均不同，需要调整绿像素的驱动电路提高该绿像素的充电速度，从而提高显示的均一性。通过设置较大开口722可以降低第一电容电极Ca的面积，使得绿像素具有较小的电容存储Cst，从而提高充电速度。在另一些实施例中，还可以通过其它方式降低绿像素的存储电容，例如降低第二电容电极Cb面积、调节该驱动晶体管的宽长比等。
例如，该导电层712还可以包括沿第一方向D1延伸的第一辅助控制线721、第二辅助控制线725、复位电压线723、724，后文将结合图16A和图17A-17B对此进行具体说明。
如图16A所示，半导体层106包括第三晶体管T3和第六晶体管T6的沟道区(T3a、T6a)、第三晶体管T3和第六晶体管T6的第一极(T3s、T6s)、第三晶体管T3和第六晶体管T6的第二极(T3d、T6d)。导电层713包括沿第一方 向D1延伸的扫描线740和复位控制线750。
例如，半导体层106的材料为氧化物半导体，例如为IGZO，ZnO，AZO，IZTO等材料。
氧化物薄膜晶体管具有漏电流小的优点。由于第三晶体管T3和第六晶体管T6都是与第一晶体管T1(也即驱动晶体管)的栅极直接连接的晶体管，因此，该第三晶体管T3和第六晶体管T6的稳定性直接影响着第一晶体管T1的栅极(N1节点)电压的稳定性。将第三晶体管T3和第六晶体管采用N型的金属氧化物薄膜晶体管，有助于降低晶体管的漏电流从而有助于保持N1节点的电压，从而在补偿阶段，第一晶体管T1的阈值电压有助于得到充分补偿，进而提高发光阶段显示基板的显示均一性。
例如，该显示基板20采用自对准工艺，利用导电层713作为掩膜对该半导体层106进行导体化处理(例如掺杂处理)，使得该半导体层106未被该导电层713覆盖的部分被导体化，从而半导体层106位于第三晶体管T3和第六晶体管T6的沟道区两侧的部分被导体化而形成分别该第三晶体管T3和第六晶体管T6的第一极和第二极。
例如，结合参考图13A-13B和图16A，在垂直于衬底基板的方向上，扫描线740与第一辅助控制线721至少部分重叠；例如，该第三晶体管T3的位于该扫描线740下方的沟道区T3a在衬底基板上的正投影位于该第一辅助控制线721在衬底基板上的正投影内。
如此，该第一辅助控制线721可以作为遮光层，防止光线从该第三晶体管T3的沟道区背面入射至该沟道区从而对第三晶体管T3的特性造成不良的影响。例如，氧化物半导体材料对于光线比较敏感，当该第三晶体管T3采用该氧化物半导体材料作为沟道区，光线入射至该沟道区容易引起第三晶体管T3的阈值漂移。通过设置该第一辅助控制线721可以提高该第三晶体管T3的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，该扫描线740与第一辅助控制线721配置为接收相同的扫描信号，从而该第三晶体管T3形成双面栅极结构，从而提高了第三晶体管T3的栅控能力，进一步稳定了第一晶体管T1的栅极电压。
例如，结合参考图13A-13B和图16A，在垂直于衬底基板的方向上，该复位控制线750与至少部分重叠；例如，该第六晶体管T6的位于该复位控制线750下方的沟道区T6a在衬底基板上的正投影位于该第二辅助控制线725在衬 底基板上的正投影内。
如此，该第二辅助控制线725可以作为遮光层，防止光线从该第六晶体管T6的沟道区背面入射至该沟道区从而对第六晶体管T6的特性造成不良的影响。例如，氧化物半导体材料对于光线比较敏感，当该第六晶体管T6采用该氧化物半导体材料作为沟道区，光线入射至该沟道区容易引起第六晶体管T6的阈值漂移。通过设置该第二辅助控制线725可以提高该第六晶体管T6的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，该复位控制线750与第二辅助控制线725配置为接收相同的扫描信号，从而该第六晶体管T6形成双面栅极结构，从而提高了第六晶体管T6的栅控能力，进一步稳定了第一晶体管T1的栅极电压。
在另一些示例中，第七晶体管T7的有源层也可以设置在半导体层106中，例如采用氧化物半导体材料。由于第一晶体管T7直接与发光元件120的第一电极134电连接，通过这种设置可以降低第七晶体管T7的漏电流，提高第一电极134电位的稳定性，从而提高发光的稳定性。
如图16B所示，在这种情形，该导电层712还包括辅助控制线810(本公开第一复位控制线的一个示例)，该导电层713还包括复位控制线820(本公开第二复位控制线的一个示例)，该复位控制线820和辅助控制线810配置为对第七晶体管T7提供栅压控制。例如，该复位控制线820与辅助控制线810配置为接收相同的扫描信号，从而该第七晶体管T7形成双面栅极结构，从而提高了第七晶体管T7的栅控能力，进一步稳定了第一电极134的电压。
在垂直于衬底基板的方向上，复位控制线820与辅助控制线810至少部分重叠；例如，该第七晶体管T7的位于该复位控制线820下方的沟道区在衬底基板上的正投影位于该辅助控制线810在衬底基板上的正投影内。
在这种情形，第七晶体管T7的连接方式需要进行适应性调整。例如，第七晶体管T7的第二极T7d与第五晶体管T5的第二极T5d不再在半导体层105中直接电连接，而需要通过过孔进行电连接，此处不再赘述。
图16C示出了本公开又一些示例提供的显示基板的示意图，如图16C所示，该显示基板还包括位于半导体层105靠近衬底基板100一侧的遮光层LS，该遮光层LS用于遮挡晶体管的沟道区，从而防止光线(例如从背面或者侧面)入射至沟道区引起的晶体管的阈值漂移。例如，该遮光层LS包括第一遮光图案LS1，该第一遮光图案LS1与第一晶体管的沟道区T1a对应设置，该沟道区T1a 在衬底基板上的正投影落入该第一遮光图案LS1内，从而对第一晶体管的沟道区进行遮挡，提高第一节点N1的稳定性。
例如，该遮光层LS还可以包括第二遮光图案LS2，该第二遮光图案LS2与第三晶体管T3和第六晶体管T6的沟道区对应设置，该第三晶体管T3和第六晶体管T6的沟道区在衬底基板上的正投影落入该第二遮光图案LS2内，从而对第三晶体管T3和第六晶体管T6的沟道区进行遮挡，有效降低了第三晶体管T3和第六晶体管T6的漏电流，进一步提高了第一节点N1的稳定性。
例如，该遮光层LS的材料例如可以是金属材料，或者有机或无机的绝缘遮光材料。
例如，结合参考图13A-13B以及图17A-17B，导电层714包括连接电极701，该连接电极701的一端通过第一电容电极Ca中的开口722以及绝缘层中的过孔901与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔902与该第三晶体管T3的第二极T3d电连接，从而将该第二电容电极Cb与该第三晶体管T3的第二极T3d电连接。
例如，结合参考图13A-13B以及图17A-17B，该导电层714还包括连接电极703，该连接电极703分别通过过孔904和过孔914与第三晶体管T3的第一极T3s以及第五晶体管T5的第一极T5s电连接，从而将第三晶体管T3的第一极T3s与第五晶体管T5的第一极T5s电连接。
例如，该导电层714还包括连接电极704，该连接电极704通过过孔905与第五晶体管T5的第二极T5d以及第七晶体管T7的第二极T7d电连接，以将该第五晶体管T5的第二极T5d以及第七晶体管T7的第二极T7d与发光元件120的第一电极134电连接。
例如，该导电层714还包括连接电极708，该连接电极708配置为加载第一电源电压VDD。该连接电极708分别通过过孔909和过孔915与第四晶体管T4的第一极T4s以及第一电容电极Ca电连接。
例如，该导电层714还包括连接电极709，该连接电极709通过过孔908与第二晶体管T2的第一极T2s电连接。
例如，如图17A-17B所示，该导电层714还包括连接电极702，例如，该连接电极702分别通过过孔903(本公开第五过孔的一个示例)和过孔913与第六晶体管T6(本公开栅极复位晶体管的一个示例)的第一极T6s以及复位电压线724(本公开第一栅极复位电压线的一个示例)电连接，从而将该第六晶 体管T6的第一极T6s与复位电压线724电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线724接收第一复位电压Vinit1。
例如，如图17A-17B所示，该导电层714还包括连接电极707，该连接电极707分别通过过孔906(本公开第四过孔的一个示例)和过孔907与第七晶体管T7(本公开像素电极复位晶体管的一个示例)的第一极T7s和复位电压线723(本公开第一像素电极复位电压线的一个示例)电连接，从而将该第七晶体管T7的第一极T7s与复位电压线723电连接，使得该第七晶体管T7的第一极T7s可以从该复位电压线723接收第二复位电压Vinit2。
例如，如图17A-17B所示，该导电层714还包括沿第二方向D2延伸的复位电压线760、780。在第一方向D1上，复位电压线760和复位电压线780交替设置，相邻的复位电压线760和复位电压线780之间间隔有两列子像素，该两列子像素中的连接电极708例如为一体的结构。每相邻的两列子像素共用一条复位电压线760或一条复位电压线780。该复位电压线760配置为提供第二复位电压Vinit2，该复位电压线780配置为提供第一复位电压Vinit1。
如图17A-17B所示，该复位电压线760(本公开第二像素电极复位电压线的一个示例)与相邻的子像素中的连接电极707电连接，例如连接为一体的结构，从而与横向的复位电压线723电连接，由此形成横纵交织的网状导电结构，该网状导电结构可以降低电阻，从而降低电压降，有助于降第二复位电压Vinit2均一地传递到基板上的各个子像素。
如图17A-17B所示，该复位电压线780(本公开第二栅极复位电压线的一个示例)与相邻的子像素中的连接电极702电连接，例如连接为一体的结构，从而与横向的复位电压线724电连接，由此形成横纵交织的网状导电结构，该网状导电结构可以降低电阻，从而降低电压降，有助于降第一复位电压Vinit1均一地传递到基板上的各个子像素。
例如，该导电层715包括沿第二方向D2延伸的数据线12。例如，该多条数据线12与多列子像素一一对应电连接以提供数据信号Vd，每条数据线12与所对应的一列子像素中的第二晶体管T2的第一极T2s电连接以提供该数据信号Vd。
结合参考图18A-18B，该数据线12通过过孔913与该连接电极709电连接，从而连接到第二晶体管T2的第一极T2s。
例如，该导电层715还包括多个电源电极920，多个电源电极920与多个 子像素一一对应设置以提供第一电源电压VDD。该电源电极920包括凹陷结构，该凹陷结构用于设置其它导电结构(如后文提到的连接电极910)。一列子像素所对应的电源电极920彼此连接为一体的结构，从而形成沿第二方向D2延伸的电源线770。
结合参考图18A-18B，每条电源线770通过过孔914与所对应的一列子像素中的连接电极708电连接，从而通过连接电极708将第一电源电压VDD输送至第四晶体管T4的第一极T4s以及第一电容电极Ca。
例如，如图18B所示，每相邻两列子像素之间设置有一个数据线组，该数据线组包括两条数据线12，该两条数据线12分别为该两列子像素提供数据信号。相邻的两个数据线组之间间隔有两列子像素。
该两条数据线12在衬底基板100上的正投影与复位电压线760、780在衬底基板上的正投影均不重叠，从而避免产生寄生电容。
相邻的电源线770彼此间隔设置。例如，如图18A-18B所示，每相邻两条电源线770之间设置有一个数据线组，相邻的数据线组之间间隔有两条电源线770。相邻的两个数据线组之间的两条电源线彼此间隔，这是为了避免与下方的复位电压线780或复位电压线760发生交叠而产生寄生电容。换言之，复位电压线780及复位电压线760分别对应于相邻两条电源线770的间隙设置。
结合参考图13A-13B以及图18A-18B，该导电层715还包括连接电极910，该连接电极910通过过孔911与连接电极704电连接，以将该连接电极704与发光元件120的第一电极134电连接。如图13A-13B所示，该连接电极910通过过孔912与发光元件120的第一电极134电连接。
上述连接电极910和704作为转接电极，将位于下方的晶体管的第一极引出从而与上方的发光元件电连接，这种设置可以避免在垂直于衬底基板的方向上，过孔直接贯通导致导电材料的填充深度过深导致连接不良、断线或不平坦，通过设置转接电极降低了过孔的深度，提高了接触良率。
图18C为本公开另一些实施例提供的显示基板的示意图。如图18C所示，在该实施例中，复位电压线780可以垂直向上平移至到导电层715中，位于相邻的两条电源线770之间。图19A和图19B为本公开又一些实施例提供的显示基板的示意图。与图18A-18B所示实施例的主要区别在于，在该实施例中，复位电压线760、780的设置位置发生了变化，该复位电压线760、780并不位于导电层714中，而是位于导电层715中，并且位于数据线组中的两条数据线12 之间。
如图19B所示，复位电压线780通过过孔918(本公开第二过孔的一个示例)与复位电压线724电连接，从而形成横纵交织的网状复位电压线结构。复位电压线760通过过孔919(本公开第三过孔的一个示例)与复位电压线723电连接，从而形成横纵交织的网状复位电压线结构。
如图19A所示，在第一方向上，复位电压线760和复位电压线780交替设置，且交替位于数据线组中的两条数据线12之间。相邻的数据线组之间的两条电源线770连接为一体的结构。由于该两条电源线770的间隙不再对应设置有复位电压线760或复位电压线780，因此，将该两条电源线770连接为一体的结构不会引起寄生电容。
例如，如图19A所示，在第一方向D1上每相邻的两个电源电极920彼此连接为一体的电源电极组777，该电源电极组777包括镂空区771，该镂空区771用于设置该两个电源电极920所对应的子像素中的连接电极910。例如，导电层715还包括连接线772，该连接线772沿第二方向D2延伸并位于每个镂空区771的中间，将一个镂空区分割为两个镂空子区，该镂空区771中的两个连接电极910分别位于该两个镂空子区内，并分别位于该连接线772的两侧。连接线772的设置有助于进一步降低电源线770的电阻。
参考图13A-13B，导电层206包括发光元件120的第一电极134。该显示基板20还可以包括位于发光元件的第一电极134上的像素界定层608。像素界定层308中形成开口暴露出像素电极134的至少部分从而界定显示基板各个子像素的开口区(即有效发光区)800。发光元件120的发光层136至少形成于该开口内(发光层136还可以覆盖部分的像素界定层远离发光元件的第一电极一侧的表面)，第二电极135形成于发光层136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如像素电极134为发光元件的阳极，第二电极135为发光元件的阴极。
需要说明的是，本公开实施例提供的显示基板的发光元件的第一电极的分布并不限于图13A所示的情形，而同样适用于其它的像素电极的分布。如图19C所示，图10B所示的发光元件的第一电极134的分布图同样适用于本实施例提供的显示基板。
例如，各导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电 金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等；或者多层金属的叠层结构；或者金属与导电金属氧化物的叠层结构。
例如，该发光元件120为顶发射结构，第一电极(即像素电极)134具有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为阳极，第二电极135为阴极。例如，第一电极134为ITO/Ag/ITO叠层结构,透明导电材料ITO为高功函数的材料，与发光材料直接接触可以提高空穴注入率；金属材料Ag有助于提高第一电极的反射率。例如；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，各绝缘层的材料例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。
例如，像素界定层608的材料为有机材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。
例如，衬底基板100可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层105、106的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、诸如金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)等氧化物半导体材料以及有机物材料(六噻吩，聚噻吩等)。
例如，该显示基板20包括图2所示的结构，在本实施例中，以将图2所示的连接结构设置在连接电极704与连接电极910的连接处为例进行示例性说明，然而这并不作为对本公开的限制。
结合参考图13A-13B，该连接电极704(本公开第一导电结构的一个示例)包括靠近衬底基板的底表面704a、远离衬底基板的顶表面704b以及位于该底表面704a和顶表面704b之间的第一侧表面704c。
连接电极704通过过孔911(本公开第一过孔的一个示例)与连接电极910(本公开第二导电结构的一个示例)电连接。过孔911与过孔905(本公开第 一凹陷结构的一个示例)在垂直于衬底基板的方向上至少部分重叠，使得绝缘层606(本公开第二绝缘层的一个示例)向下凹陷，过孔911暴露该连接电极704的第一侧表面704c的至少部分，并使得连接电极910向下凹陷并包括突出部910a(本公开第一突出部的另一个示例)，该突出部910a与该第一侧表面704c的至少部分接触，覆盖该第一侧表面704c被该过孔911暴露的部分。
参照图2和图13A-13B，图2所示的结构可以看作显示基板20沿剖面线B-B’的剖面结构的一部分，也即图13B中用虚线圈出的结构，图13B中的连接电极704、连接电极910、突出部910a、过孔911、过孔905可以分别看作图2中的第一导电结构21、第二导电结构22、突出部220、过孔V1以及凹陷结构G1。对于图2的描述同样适用于图13B，此处不再赘述。
例如，如图13A-13B所示，该连接电极704包括朝向过孔905的突出部704t，该突出部704t在衬底基板上的正投影位于过孔905在衬底基板上的正投影内。
例如，在图13B所示的截面内，该过孔905沿参考方向F的尺寸为b，该参考方向F与衬底基板的板面平行，例如为第二方向D2；过孔911与过孔905的重叠区域沿参考方向F的尺寸为c，连接电极704的第一侧表面704c被连接电极910覆盖的部分在垂直于衬底基板的方向上的尺寸为d。
如图13B所示，该连接电极704包括位于绝缘层605远离衬底基板一侧且与连接电极910接触的接触部724，该接触部724例如可以看作该连接电极704在与该连接电极910接触范围内的纵向截段；该接触部724在垂直于衬底基板方向的尺寸为e。第一侧表面704c在垂直于衬底基板的方向上的尺寸为n。
例如，在图13B所示的截面内，该过孔905的最大深度为i，该过孔905的一个侧边与衬底基板的板面所成的夹角为j，该连接电极910与该连接电极704接触的部分在垂直于所述衬底基板方向上的尺寸为k。例如，d/e>2.1*i*sin(j)/k。
例如，c/b大于0.1；d/e大于0.3。例如，c/b大于0.28。
例如，d/n大于0.6。
该第一侧表面704c被包覆的尺寸与过孔905深度、过孔905的底角正相关，与连接电极910的厚度负相关，在一定范围内使d/e或c/b减小，可以使得过孔911与过孔905的交叠减小，从而使得连接电极910的向下的突出部910a的尺寸减小，提高连接电极910的平坦度，进而提高上方像素电极的平坦度，提高显示质量。
例如，d/e>2.5*i*sin(j)/k。
上述设置可以提高纵向上连接电极910与连接电极704的交叠面积，从而有助于降低过孔911和过孔905的平面面积，由于像素开口区800需要尽量避免与过孔911或过孔905重叠以提高平坦度，因此该设置可以有效提高显示基板的开口率。
在一个示例中，b＝56.8um,c＝8.1um，c/b＝0.143，d＝2.9um，e＝14.1um，d/e＝0.206。
在另一个示例中，b＝33.2um,c＝5.1um，c/b＝0.154，d＝3.1um，e＝9.1um，d/e＝0.341。
在又一个示例中，b＝99.1um,c＝26.0um，c/b＝0.262，d＝12.8um，e＝22.5um，d/e＝0.569。
例如，突出部910a的平均厚度小于连接电极910的与连接电极704的顶表面704b接触的部分的平均厚度。
例如，对于每个子像素，该突出部910a位于与该子像素连接的复位电压线760/780与连接电极708之间；也即该突出部910a在衬底基板100上的正投影位于该复位电压线760/780在该衬底基板上的正投影与该连接电极708在该衬底基板上的正投影之间。由于连接电极708上加载是第一电源电压VDD，这种设置有助于降低复位电压线760/780与连接电极708之间的信号干扰。
结合参考图13A-13B所示，对于图中左起第一个子像素，突出部910a位于与该列子像素连接的复位电压线760与连接电极708之间。如图13A所示，该突出部910a在衬底基板上的正投影与复位电压线760在衬底基板上的正投影在参考方向F(如第一方向D1)上的距离为s1，该突出部910a在衬底基板上的正投影与连接电极708在衬底基板上的正投影在参考方向F上的距离为s2。例如，s1小于s2。这种设置可以对复位电压线70起到较好的屏蔽作用。
例如，如图17B所示，连接电极708包括主体部沿第一方向延伸D1的延伸部708a，该延伸部708a朝向该复位电压线706突出，该延伸部708a在第二方向D2的尺寸小于该主体部在第二方向上D2的尺寸。在第二方向D2上，连接电极704与连接电极708的延伸部708a至少部分重叠。这种设置有助于进一步提高屏蔽连接电极708中的电源电压信号对复位电压线706的干扰的效果。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板20。例如，该显示面板为OLED显示面板，相应地其包括的显示基板20为OLED显 示基板。该显示基板20可以包括发光元件，也可以不包括发光元件，也即该发光元件可以在显示基板20完成后在面板厂形成。在该显示基板20本身不包括发光元件的情形下，本公开实施例提供的显示面板除了包括显示基板20之外，还进一步包括发光元件。
如图20所示，例如，该显示面板30还包括设置于显示基板20上的封装层801和盖板802，该封装层801配置为对显示基板20上的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动子电路的渗透而造成对器件的损坏。例如，封装层801包括有机薄膜或者包括无机薄膜、有机薄膜、无机薄膜交替层叠的结构。例如，该封装层801与显示基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板802例如为玻璃盖板或柔性盖板。例如，盖板802和封装层801可以为一体的结构。
本公开至少一实施例还提供一种触控显示面板，该触控显示面板包括以上任一显示基板20。以下将结合图21、并以该触控显示面板包括图6A-6B所示的显示基板为例对本公开至少一实施例提供的触控显示面板进行示例性说明。
如图21所示，该触控显示面板50包括层叠设置的显示基板20和触控结构520，还包括位于显示基板20和触控结构520之间的绝缘层406。例如，该绝缘层406包括封装层406，该封装层406配置为对发光元件120进行密封，以防止外界的湿气和氧向该发光元件及驱动电路的渗透，而造成对例如发光元件120等器件的损坏。例如，封装层406可以是单层结构或多层结构，例如包括有机薄膜、无机薄膜或者包括有机薄膜及无机薄膜交替层叠的多层结构。例如，该触控显示面板还包括位于封装层406与触控结构520之间的缓冲层(未示出)。该缓冲层用于提高触控结构520和显示基板20之间的粘合力。
如图21所示，该触控结构520包括触控电极521，该触控电极521例如为块状电极或者金属网格电极。
在垂直于衬底基板的方向上，显示基板中的第二导电结构的突出部与触控电极不重叠；也即第二导电结构的突出部(例如图21中的突出部314a)在衬底基板上的正投影与触控电极在衬底基板上的正投影分离。这种设置有助于避免该突出部影响触控电极的平坦度而导致的不良。
例如，衬底基板的方向上，显示基板中的第一导电结构(例如图21中的连接电极232)与触控电极不重叠；也即第一导电结构在衬底基板上的正投影与触控电极在衬底基板上的正投影分离。
本公开的至少一实施例还提供一种显示装置40，如图22所示，该显示装置40包括上述任一显示基板20或显示面板或触控显示面板，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (56)

  1. 一种显示基板，包括：
    衬底基板；
    依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层；
    其中，所述第一绝缘层包括第一凹陷结构，所述第一导电层包括第一导电结构，所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；
    所述第二绝缘层包括第一过孔，所述第二导电层包括第二导电结构；
    所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影至少部分重叠；
    所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第二导电结构与所述第一导电结构的第一侧表面的所述至少部分接触；
    所述第一导电结构的第一侧表面包括突出曲面，所述第二导电结构包覆所述突出曲面的至少部分；
    所述第一导电结构包括位于所述第一凹陷结构中且与所述突出曲面连接的连接部；沿平行于所述衬底基板的板面的方向，所述突出曲面相对于所述连接部朝向所述第一凹陷结构的中部突出。
  2. 如权利要求1所述的显示基板，其中，所述第二导电结构包括第一突出部，所述第一突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的正投影内；
    所述第一突出部与所述第一导电结构的第一侧表面的至少部分接触。
  3. 如权利要求1或2所述的显示基板，其中，所述第一凹陷结构在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠。
  4. 如权利要求1-3任一所述的显示基板，其中，所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，
    所述第一侧表面在垂直于所述衬底基板的方向上的尺寸大于所述第二侧表面在垂直于所述衬底基板的方向上的尺寸。
  5. 如权利要求4所述的显示基板，其中，所述第一侧表面包括位于所述第一绝缘层远离所述衬底基板一侧的第一侧表面部分；
    所述第一侧表面部分未被所述第二导电结构覆盖的部分沿垂直于所述衬底基板的方向上的尺寸大于所述第二侧表面沿垂直于所述衬底基板的方向上的尺寸。
  6. 如权利要求4或5所述的显示基板，其中，所述第一导电结构的顶表面与所述第一侧表面直接连接的至少部分与所述第二导电层分离。
  7. 如权利要求4-6任一所述的显示基板，其中，所述显示基板具有第一截面，所述第一凹陷结构在所述第一截面内并沿参考方向的尺寸为b，所述参考方向与所述衬底基板的板面平行；
    在所述第一截面内，所述第一过孔与所述第一凹陷结构的重叠区域沿所述参考方向的尺寸为c，所述第一导电结构的第一侧表面被所述第二导电结构覆盖的部分在垂直于衬底基板的方向上的尺寸为d；所述第一导电结构包括位于所述第一绝缘层的远离所述衬底基板一侧且与所述第二导电结构接触的接触部在垂直于所述衬底基板方向的尺寸为e；
    c/b大于0.1；
    d/e大于0.3。
  8. 如权利要求7所述的显示基板，其中，c/b大于0.15，d/e小于0.8。
  9. 如权利要求7或8所述的显示基板，其中，c/b小于0.19，d/e小于0.5。
  10. 如权利要求7-9任一所述的显示基板，其中，在所述第一截面内，所述第一凹陷结构的最大深度为i，所述第一凹陷结构在所述第一截面内的一个侧边与所述衬底基板的板面所成的夹角为j，所述第二导电结构与所述第一导电结构接触的部分在垂直于所述衬底基板方向上的厚度为k；
    d/e<0.0273*i*sin(j)/k。
  11. 如权利要求10所述的显示基板，其中，c/b<0.0102*i*sin(j)/k。
  12. 如权利要求10或11所述的显示基板，其中，所述第一侧表面在垂直于所述衬底基板的方向上的尺寸为n，所述第二侧表面在垂直于所述衬底基板的方向上的尺寸为e；
    0.1*(n/e)/sin(j)>(d/n)。
  13. 如权利要求11或12所述的显示基板，其中，0.08*(n/e)/sin(j)>d/n。
  14. 如权利要求7-13任一所述的显示基板，其中，所述接触部包括朝向所述第一凹陷结构的第二突出部，所述第二突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的正投影内；
    在所述第一截面内，所述第二突出部在垂直于所述衬底基板的方向上的尺寸大于所述第一导电层位于所述第一凹陷结构的侧表面的部分在垂直于所述第一凹陷结构的所述侧表面的方向上的尺寸。
  15. 如权利要求1-14任一所述的显示基板，其中，第一绝缘层还包括与第一凹陷结构间隔的第二凹陷结构，
    所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，
    所述第二侧表面在所述衬底基板上的正投影与所述第二凹陷结构在所述衬底基板上的正投影至少部分重叠；
    所述第一过孔还暴露所述第二侧表面的至少部分，所述第二导电结构包覆所述第一导电结构的第二侧表面的至少部分。
  16. 如权利要求15所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述第一导电结构的第一侧表面被所述第二导电结构覆盖的部分的尺寸与所述第二侧表面被所述第二导电结构覆盖的部分的尺寸不同。
  17. 如权利要求15或16所述的显示基板，其中，所述第一过孔在所述衬底基板上的正投影与所述第一凹陷结构在所述衬底基板上的正投影的重叠尺寸和所述第一过孔在所述衬底基板上的正投影与所述第二凹陷结构在所述衬底基板上的正投影的重叠尺寸不同。
  18. 一种显示基板，包括：
    衬底基板；
    依次设置于所述衬底基板上的第一绝缘层、第一导电层、第二绝缘层、第二导电层；
    其中，所述第一导电层包括第一导电结构；所述第二导电层包括第二导电结构；
    所述第一导电结构包括靠近所述衬底基板的底表面、远离所述衬底基板的顶表面以及位于所述底表面和所述顶表面之间的第一侧表面；
    所述第二绝缘层包括第一过孔，所述第二导电结构通过所述第一过孔与所述第一导电结构接触；
    所述第二导电结构包括第一突出部，所述第一过孔暴露所述第一导电结构的第一侧表面的至少部分，所述第一突出部与所述第一导电结构的第一侧表面的所述至少部分接触；
    所述第一绝缘层包括彼此间隔的第一凹陷结构和第二凹陷结构，所述第一导电结构还包括位于所述底表面和所述顶表面之间的第二侧表面，所述第一侧表面与所述第二侧表面相对，所述第一导电结构的至少部分分别位于所述第一凹陷结构和所述第二凹陷结构中。
  19. 如权利要求18所述的显示基板，其中，
    所述第一导电结构包括朝向所述第一凹陷结构的第二突出部，所述第二突出部在所述衬底基板上的正投影位于所述第一凹陷结构在所述衬底基板上的正投影内。
  20. 如权利要求18或19所述的显示基板，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    所述第一导电层还包括与所述第一导电结构间隔的第一信号线和第二信号线，所述第一信号线和所述第二信号线沿所述第二方向延伸；
    所述第一突出部在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影在所述第一方向上的距离为l，所述第二信号线在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影在所述第一方向上的距离m，
    所述显示基板包括垂直于所述衬底基板的第一截面，在所述第一截面内，所述第一导电结构位于所述第一绝缘层的远离所述衬底基板一侧的部分在垂直于所述衬底基板的方向上的尺寸为e，所述第一侧表面被所述第一突出部包覆的部分在垂直于所述衬底基板的方向上的尺寸为d，
    l/m>0.9(d/e)。
  21. 如权利要求20所述的显示基板，其中，l/m>1.2*(d/e)。
  22. 如权利要求18-21任一所述的显示基板，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    所述第二绝缘层包括多个过孔，所述多个过孔沿所述第一方向和所述第二方向排列为多个过孔行和多个过孔列，所述多个过孔包括多个所述第一过孔；
    所述多个过孔行包括第一过孔行，在所述第一过孔行中，每隔1个过孔存在3个连续的所述第一过孔。
  23. 如权利要求22所述的显示基板，其中，所述多个过孔列包括第一过孔 列，在所述第一过孔列中，每个过孔都是所述第一过孔，或者每隔1个过孔存在一个所述第一过孔。
  24. 如权利要求18-23任一所述的显示基板，其中，所述多个像素列包括在所述第一方向上相邻的第一像素列和第二像素列，
    所述第一信号线与所述第一像素列的子像素连接以提供第一信号，所述第二信号线与所述第二像素列的子像素连接以提供第二信号，
    所述第一像素列的发光元件靠近所述衬底基板一侧的电极在所述衬底基板上的正投影分别与所述第一信号线在所述衬底基板上的正投影及所述第二信号线在所述衬底基板上的正投影至少部分重叠。
  25. 如权利要求18-24任一所述的显示基板，其中，
    所述显示基板还包括位于所述像素电极远离所述衬底基板一侧的像素界定层，所述像素界定层包括多个像素开口区，所述多个像素开口区与所述多个子像素一一对应，
    所述多个像素开口区在所述衬底基板上的正投影与所述第一突出部在所述衬底基板上的正投影分离。
  26. 如权利要求25所述的显示基板，其中，所述像素界定层包括多个凸起部，所述多个凸起部位于所述多个像素开口区之间；
    所述多个凸起部包括围绕同一像素开口区设置的第一凸起部、第二凸起部和第三凸起部，所述第一凸起部、所述第二凸起部和所述第三凸起部在所述衬底基板上的正投影的中心的连线构成一个三角形。
  27. 如权利要求26所述的显示基板，其中，所述第一凸起部位于相邻的四个像素开口区之间，所述第二凸起部和所述第三凸起部分别位于相邻的两个像素开口区之间；
    所述第一凸起部在所述衬底基板上的正投影的面积分别大于所述第二凸起部在所述衬底基板上的正投影的面积以及所述第三凸起部在所述衬底基板上的正投影的面积。
  28. 如权利要求18-27任一所述的显示基板，还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层，
    其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    所述第三导电层包括屏蔽电极和第一电容电极，所述屏蔽电极包括沿所述第一方向延伸的部分，以及朝向所述屏蔽电极所在子像素的所述第一电容电极延伸的部分。
  29. 如权利要求28所述的显示基板，还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    所述第一导电层包括沿所述第二方向延伸的第一复位电压线，所述第三导电层包括沿所述第一方向延伸的第二复位电压线，所述第一复位电压线与所述第二复位电压线电连接；
    所述显示基板还包括位于所述第三导电层靠近所述衬底基板一侧的半导体层，所述半导体层包括连接部；所述连接部将所述第一复位电压线与子像素中的复位晶体管的第一极电连接；
    所述连接部在所述衬底基板上的正投影与所述第一复位电压线在所述衬底基板上的正投影以及所述复位晶体管的第一极在所述衬底基板的正投影均交叠。
  30. 如权利要求18-29任一所述的显示基板，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    所述显示基板还包括沿所述第一方向延伸的第一栅极复位电压线和第一像素电极复位电压线，以及沿所述第二方向延伸的第二栅极复位电压线和第二像素电极复位电压线；
    所述第一栅极复位电压线与所述第二栅极复位电压线通过第二过孔电连接，所述第一像素电极复位电压线与所述第二像素电极复位电压线通过第三过孔电连接；
    所述第一栅极复位电压线和所述第二栅极复位电压线用于给驱动晶体管的栅极提供复位电压信号，所述第一像素电极复位电压线和第二像素电极复位电压线用于给像素电极提供复位电压信号。
  31. 如权利要求30所述的显示基板，其中，所述第二像素电极复位电压线通过第四过孔与像素电极复位晶体管的第一极电连接，所述第四过孔与所述第三过孔在所述衬底基板上的正投影彼此分离。
  32. 如权利要求30或31所述的显示基板，其中，所述第二栅极复位电压线通过第五过孔与栅极复位晶体管的第一极电连接，所述第五过孔与所述第二过孔在所述衬底基板上的正投影彼此分离。
  33. 如权利要求18-32任一所述的显示基板，其中，所述显示基板还包括位于所述衬底基板上的多个子像素，所述多个子像素排列为沿第一方向的多个像素行和沿第二方向的多个像素列，所述第一方向与所述第二方向不同；
    每个子像素包括第一电容电极，所述显示基板还包括沿所述第二方向延伸的多条数据线；
    在所述第一方向上相邻的两个子像素的第一电容电极通过连接部连接，所述多条数据线分别与多个连接部在垂直于所述衬底基板的方向上交叠；
    所述连接部包括与对应的数据线存在交叠的第一部分和与所述对应的数据线不交叠的第二部分；
    所述第一部分在所述第二方向的尺寸大于所述第二部分在所述第二方向的尺寸；
    所述显示基板还包括沿所述第二方向延伸的复位电压线，所述第二部分与所述复位电压线在垂直于所述衬底基板的方向上重叠。
  34. 一种显示基板，包括：
    衬底基板；以及
    依次设置于所述衬底基板上的第一金属层、第二金属层、第一导电层和第二导电层；
    其中，所述显示基板还包括位于所述衬底基板上在第一方向上的相邻的第一子像素和第二子像素，所述第一子像素具有第一像素电路，所述第二子像素具有第二像素电路；所述第一像素电路和第二像素电路分别包括电容，所述电容包括位于所述第二金属层的第一电容电极和位于第一金属层的第二电容电极，
    所述第一像素电路的第一电容电极和所述第二像素电路的第一电容电极彼此连接为一体的电容电极块，
    所述电容电极块具有第一开口和第二开口，所述第一开口在所述衬底基板上的正投影与所述第一像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第二开口在所述衬底基板上的正投影与所述第二像素电路的第二电容电极在所述衬底基板上的正投影交叠，所述第一开口在所述衬底基板上的正投 影面积与所述第二开口在所述衬底基板上的正投影面积不同。
  35. 如权利要求34所述的显示基板，其中，所述第二导电层包括沿第二方向延伸的复位电压线、第一数据线、第二数据线、第一电源线和第二电源线，所述第一方向与所述第二方向不同；
    所述第一像素电路和所述第二像素电路的每个包括驱动晶体管和数据写入晶体管；
    所述复位电压线配置为给所述第一像素电路和所述第二像素电路的像素电极或驱动晶体管的栅极提供复位电压，所述第一数据线和所述第二数据线分别配置为给所述第一像素电路和所述第二像素电路的数据写入晶体管提供数据电压，
    所述第一电源线和所述第二电源线分别配置为给所述第一像素电路和所述第二像素电路的驱动晶体管提供电源电压；
    所述复位电压线位于所述第一数据线和所述第二数据线之间；
    所述第一数据线和第二数据线均位于所述第一电源线和所述第二电源线之间；
    所述第一电源线和所述第二电源线均具有封闭的镂空区。
  36. 如权利要求35所述显示基板，其中，所述第一子像素的像素电极在所述衬底基板的正投影与所述复位电压线、所述第一数据线、所述第二数据线、所述第一电源线和所述第二电源线在所述衬底基板上的正投影均交叠。
  37. 如权利要求34-36任一所述的显示基板，还包括多个子像素，所述多个子像素位于所述衬底基板上并沿所述第一方向和第二方向排列为多个像素行和多个像素列，所述第一方向与所述第二方向不同；
    所述第一导电层还包括多个连接电极，所述多个连接电极与所述多个子像素一一对应连接以提供电源电压；
    所述多个子像素包括第一子像素，所述显示基板还包括沿所述第二方向延伸的复位电压线，所述复位电压线与所述第一子像素连接以提供复位电压，
    所述第一突出部在所述衬底基板上的正投影位于所述第一子像素对应连接的连接电极在所述衬底基板上的正投影和所述复位电压线在所述衬底基板上的正投影之间。
  38. 如权利要求37所述的显示基板，其中，沿所述第一方向，所述第一突出部与所述复位电压线的距离小于所述第一突出部与所述连接电极的距离。
  39. 如权利要求38所述的显示基板，其中，所述连接电极包括主体部和沿所述第一方向延伸的延伸部，所述延伸部在所述第二方向的尺寸小于所述主体部在所述第二方向上的尺寸；
    在所述第二方向上，所述第一导电结构与所述连接电极的延伸部至少部分重叠。
  40. 如权利要求37-39任一所述的显示基板，其中，所述第二导电层包括多个电源电极，所述多个电源电极与所述多个连接电极一一对应连接以提供所述电源电压，
    每个像素列对应的电源电极彼此连接为一体的结构，从而形成沿所述第二方向延伸的多条电源线。
  41. 如权利要求40所述的显示基板，其中，所述第二导电层还包括沿所述第二方向延伸的多条数据线，所述多条数据线分别与所述多个像素列一一对应连接以提供数据信号；
    所述多条数据线划分为多个数据线组，每个数据线组包括两条数据线；
    每相邻两个像素列之间设置有一个数据线组，相邻的数据线组之间间隔有两条电源线。
  42. 如权利要求41所述的显示基板，包括沿所述第二方向延伸的多条复位电压线，
    其中，所述多条复位电压线包括在所述第一方向上交替设置的第一复位电压线和第二复位电压线，所述第一复位电压线和所述第二复位电压线分别配置为提供第一复位电压和第二复位电压；
    相邻的第一复位电压线和第二复位线之间间隔有两个像素列。
  43. 如权利要求35-42任一所述的显示基板，其中，所述多条复位电压线位于所述第一导电层，
    相邻的数据线组之间的两条电源线之间提供一条第一复位电压线或第二复位电压线；
    所述多条复位电压线中的任一条在所述衬底基板上的正投影与所述多条电源线中的任一条在所述衬底基板上的正投影分离。
  44. 如权利要求42或43所述的显示基板，其中，所述多条复位电压线位于所述第二导电层，并与多个数据线组一一对应设置，每条复位电压线位于对应的数据线组中的两条数据线之间。
  45. 如权利要求44所述的显示基板，其中，相邻的数据线组之间的两条电源线彼此连接为一体的结构，使得所述两条电源线中在所述第一方向上相邻的两个电源电极彼此连接为一体的电源电极组；
    所述显示基板包括多个第二导电结构，所述多个第二导电结构与所述多个电源电极一一对应设置；
    所述电源电极组包括镂空区，所述镂空区设置有两个第二导电结构。
  46. 如权利要求45所述的显示基板，其中，所述第二导电层还包括连接线，所述连接线沿所述第二方向延伸，将所述镂空区分离为两个镂空子区；
    所述两个第二导电结构分别设置在所述两个镂空子区内，并分别位于所述连接线的两侧。
  47. 如权利要求37-46任一所述的显示基板，还包括位于所述第一导电层靠近所述衬底基板一侧的第三导电层以及位于所述第三导电层和所述第二金属层之间的半导体层，其中，所述第二金属层位于所述第三导电层靠近所述衬底基板的一侧；
    所述子像素包括复位晶体管，所述复位晶体管配置为对所述发光元件的第一电极进行复位，所述复位晶体管包括位于所述半导体层中的有源层；
    所述显示基板包括分别位于所述第二金属层的第一复位控制线和位于所述第三导电层的第二复位控制线，所述第一复位控制线和所述第二复位控制线分别配置为对所述复位晶体管进行栅压控制，且所述第一复位控制线与所述第二复位控制线在所述衬底基板上的正投影至少部分重叠。
  48. 一种显示基板，包括：
    衬底基板；
    多个子像素，位于所述衬底基板上；
    其中，所述多个子像素的每个子像素包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路排列为沿第一方向延伸的多个像素行和第二方向延伸的多个像素列，所述第一方向与所述第二方向不同；
    所述像素电路包括驱动晶体管和存储电容，所述驱动晶体管配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；
    所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极配置为接收第一电源电压；
    所述多个子像素包括第一子像素，所述第一子像素还包括屏蔽电极，所述 屏蔽电极与所述第一子像素的第一电容电极同层设置且为一体的结构，所述屏蔽电极包括第一遮挡部和第二遮挡部，所述第二遮挡部从所述第一电容电极沿所述第二方向延伸出来，所述第一遮挡部从所述第二遮挡部沿所述第一方向延伸出来；
    所述显示基板还包括半导体图案，所述半导体图案与所述驱动晶体管的有源层位于同一半导体层，在垂直于所述衬底基板的方向上，所述第一遮挡部与所述半导体图案至少部分重叠。
  49. 如权利要求48所述的显示基板，其中，所述像素电路还包括另一晶体管，所述另一晶体管包括栅极、第一极和第二极，所述另一晶体管的第一极和第二极分别与所述驱动晶体管的第二极和栅极连接；
    所述半导体图案配置为另一晶体管的有源层的至少部分。
  50. 如权利要求49所述的显示基板，其中，所述另一晶体管包括第一栅极和第二栅极，所述另一晶体管的有源层包括第一部分、第二部分和第三部分，所述第一部分在所述衬底基板上的正投影与所述第一栅极在所述衬底基板的正投影交叠，所述第二部分在所述衬底基板上的正投影与所述第二栅极在所述衬底基板的正投影交叠，所述第三部分位于所述第一部分和所述第二部分之间且将所述第一部分和所述第二部分连接，
    所述半导体图案配置为所述另一晶体管的有源层的第三部分。
  51. 如权利要求50所述的显示基板，其中，所述第一遮挡部包括第一子部和第二子部，所述第一子部在所述衬底基板上的正投影与所述半导体图案在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述半导体图案在所述衬底基板上的正投影不交叠，
    所述第一子部在所述第二方向上的尺寸大于所述第二子部在所述第二方向上的尺寸。
  52. 如权利要求49-51任一所述的显示基板，还包括位于所述第一电容电极远离所述衬底基板一侧的电源线，其中，所述电源线配置为与所述第一子像素的第一电容电极电连接以提供所述第一电源电压。
  53. 如权利要求52所述的显示基板，其中，所述第一子像素还包括连接电极，所述连接电极用于将所述第一子像素的驱动晶体管的栅极和另一晶体管的第二极电连接；
    所述第一子像素的连接电极在所述衬底基板上的正投影与所述第一子像素 的屏蔽电极的第二遮挡部在所述衬底基板上的正投影在所述第一方向上至少部分交叠。
  54. 如权利要求53所述的显示基板，其中，所述第一子像素的连接电极在所述衬底基板上的正投影在所述第二方向上位于所述第一子像素的第一电容电极和屏蔽电极所构成的一体结构在所述衬底基板上的正投影的范围之内。
  55. 如权利要求53或54所述的显示基板，其中，所述像素电路还包括数据写入晶体管，所述数据写入晶体管与所述驱动晶体管连接，
    所述显示基板还包括数据线，所述数据线配置为与所述数据写入晶体管的第一极电连接以提供所述数据信号，
    所述第一子像素的第二遮挡部在所述衬底基板上的正投影位于所述第一子像素的连接电极在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
  56. 一种显示装置，包括如权利要求1-55任一所述的显示基板。
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CN118120352A (zh) * 2022-09-30 2024-05-31 京东方科技集团股份有限公司 阵列基板和显示装置
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