WO2021238486A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021238486A1
WO2021238486A1 PCT/CN2021/087459 CN2021087459W WO2021238486A1 WO 2021238486 A1 WO2021238486 A1 WO 2021238486A1 CN 2021087459 W CN2021087459 W CN 2021087459W WO 2021238486 A1 WO2021238486 A1 WO 2021238486A1
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WIPO (PCT)
Prior art keywords
sub
pixel
electrode
circuit
light
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PCT/CN2021/087459
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English (en)
French (fr)
Inventor
屈忆
尚庭华
杨路路
张猛
王思雨
姜晓峰
和玉鹏
李慧君
张鑫
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/427,194 priority Critical patent/US11844251B2/en
Priority to EP21755883.2A priority patent/EP4002478A4/en
Publication of WO2021238486A1 publication Critical patent/WO2021238486A1/zh
Priority to US18/497,437 priority patent/US20240065061A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a plurality of sub-pixels distributed on the base substrate in an array.
  • Each of the plurality of sub-pixels includes a pixel circuit and a light-emitting element.
  • the pixel circuit is used to drive the light-emitting element to emit light.
  • the plurality of sub-pixels are arranged in a first direction and a second direction.
  • the pixel circuit includes a driving sub-circuit and a compensation sub-circuit
  • the driving sub-circuit includes a control electrode, a first end and a second end, and is configured to be connected to the light-emitting element and control the flow through the The driving current of the light-emitting element
  • the compensation sub-circuit includes a control electrode, a first electrode and a second electrode, the control electrode of the compensation sub-circuit is configured to receive a scan signal, the first electrode and the second electrode of the compensation sub-circuit Respectively connected to the control electrode and the second end of the driving sub-circuit, the compensation sub-circuit is configured to perform threshold compensation on the driving sub-circuit in response to the scan signal
  • the light-emitting element includes first An electrode, a light-emitting layer and a second electrode, the first electrode of the light-emitting element is located on the side of the light-emitting layer close to the base substrate
  • the compensation sub-circuit further includes a first electrode and a The connecting portion
  • a main body portion includes a first side parallel to a certain direction, the first protruding portion protrudes from the first side of the first main body portion, the first protruding portion and the compensation sub-circuit of the first sub-pixel
  • the first side of the first main body portion is a straight side and parallel to the first direction, and the protruding portion protrudes from the first side of the first main body portion in the second direction.
  • the connecting portion includes a first semiconductor region, a conductive region, and a second semiconductor region
  • the first semiconductor region separates the first electrode of the compensation sub-circuit from the conductive region
  • the second semiconductor region The semiconductor region separates the second electrode of the compensation sub-circuit from the conductive region; the first semiconductor region, the second semiconductor region, the conductive region, the first electrode, and the second electrode of the compensation sub-circuit are located on the same semiconductor layer and As a one-piece structure.
  • the first driving electrode of the light-emitting element of the first sub-pixel and the first semiconductor region of the compensation sub-circuit of the first sub-pixel at least partially overlap in a direction perpendicular to the base substrate.
  • the ratio to the area of the first semiconductor region is 50%-100%.
  • the first protrusion and the conductive region of the compensation sub-circuit of the first sub-pixel at least partially overlap in a direction perpendicular to the base substrate.
  • the display substrate further includes a shielding electrode located on a side of the compensation sub-circuit of the first sub-pixel away from the base substrate, and the shielding electrode is connected to the compensation sub-circuit of the first sub-pixel.
  • the conductive area of the first sub-pixel overlaps at least partially in the direction perpendicular to the base substrate; in the direction perpendicular to the base substrate, the conductive area of the compensation sub-circuit of the first sub-pixel and the first protrusion
  • the overlapping area of is smaller than the overlapping area of the conductive area of the compensation sub-circuit of the first sub-pixel and the shielding electrode.
  • the conductive region is L-shaped and includes a first branch and a second branch, and the first branch extends along the second direction and is directly connected to the first semiconductor region of the compensation sub-circuit;
  • the second branch extends along the first direction and is directly connected to the second semiconductor region of the compensation sub-circuit.
  • the compensation sub-circuit includes a compensation transistor, and a gate, a first electrode, and a second electrode of the compensation transistor serve as a control electrode, a first electrode, and a second electrode of the compensation sub-circuit, respectively;
  • the gate of the compensation transistor includes a first gate and a second gate, and the orthographic projection of the first semiconductor region on the base substrate is located within the orthographic projection of the first gate on the base substrate, The orthographic projection of the second semiconductor region on the base substrate is located within the orthographic projection of the second gate on the base substrate, and the conductive region is connected to the first gate and the second gate.
  • the poles do not overlap in the direction perpendicular to the base substrate.
  • the size of the first protrusion is smaller than the size of the first gate of the compensation sub-circuit.
  • the orthographic projection of the first drive electrode of the light-emitting element on the base substrate includes that the first gate of the compensation sub-circuit is located on the base substrate in the second direction.
  • the maximum size of the first protrusion is 1/8-1/3 of the maximum size of the first driving electrode of the light-emitting element.
  • the largest dimension of the first protrusion is less than 3 microns.
  • the plurality of sub-pixels further include a second sub-pixel, and the first driving electrode of the light-emitting element of the second sub-pixel and the first driving electrode of the light-emitting element of the first sub-pixel are in the first sub-pixel.
  • the first driving electrode of the light-emitting element of the second sub-pixel includes a first side parallel to and opposite to the first side of the first body portion of the first driving electrode of the light-emitting element of the first sub-pixel. Two sides.
  • the maximum dimension of the first protrusion of the compensation sub-circuit of the first sub-pixel in the second direction is less than 1/3 of the distance between the first side and the second side.
  • the first semiconductor region of the compensation sub-circuit of the second sub-pixel and the first electrode of the light-emitting element of the second sub-pixel do not overlap in a direction perpendicular to the base substrate.
  • the first driving electrode of the light-emitting element of the second sub-pixel and the control electrode of the driving sub-circuit of the second sub-pixel at least partially overlap in a direction perpendicular to the base substrate.
  • the pixel circuit of the first sub-pixel and the pixel circuit of the second sub-pixel are arranged side by side in the second direction.
  • the pixel circuit further includes a first light-emission control sub-circuit, the first light-emission control sub-circuit is connected to the first terminal and the first voltage terminal of the driving sub-circuit, and is configured to respond to the first The light emission control signal applies the first power supply voltage from the first voltage terminal to the first terminal of the driving sub-circuit.
  • the display substrate further includes a scan line and a light-emitting control line, wherein the scan line and the light-emitting control line both extend along the first direction, and the scan line and the first sub-pixel
  • the control electrode of the compensation sub-circuit is electrically connected to provide the scan signal
  • the light-emission control line is connected to the first light-emission control sub-circuit of the first sub-pixel to provide the first light-emission control signal.
  • the first center point of the orthographic projection of the first drive electrode of the light-emitting element of the first sub-pixel on the base substrate is located between the orthographic projection of the scan line on the base substrate and The light emission control line is between the orthographic projections on the base substrate.
  • the first center point of the orthographic projection of the first drive electrode of the light-emitting element of the first sub-pixel on the base substrate and the first drive electrode of the light-emitting element of the second sub-pixel are at The second center points of the orthographic projection on the base substrate are respectively located on both sides of the orthographic projection of the scan line on the base substrate in the second direction, and the first center points are relatively The second center point is closer to the orthographic projection of the scan line on the base substrate.
  • the plurality of sub-pixels further includes a third sub-pixel
  • the first driving electrode of the light-emitting element of the third sub-pixel includes a second body portion and a second protrusion portion
  • the third sub-pixel emits light.
  • the second main body portion of the first driving electrode of the element includes a third side parallel to the second direction, the protruding portion protrudes from the third side along the first direction, and the light-emitting element of the third sub-pixel
  • the second protrusion of the first driving electrode and the conductive area of the compensation sub-circuit of the third sub-pixel at least partially overlap in a direction perpendicular to the base substrate.
  • the plurality of sub-pixels further include a fourth sub-pixel, and the fourth sub-pixel and the third sub-pixel are adjacent in the first direction and located at the same level as the light-emitting element of the third sub-pixel.
  • the first driving electrode of the light-emitting element of the third sub-pixel and the conductive area of the compensation sub-circuit of the fourth sub-pixel are perpendicular to each other. At least partially overlap in the direction of the base substrate.
  • the display substrate further includes a scan line extending along the first direction, and the scan line is electrically connected to the control electrode of the compensation sub-circuit of the first sub-pixel to provide the scan signal;
  • the display substrate further includes a pixel defining layer located on a side of the first driving electrode of the light-emitting element away from the base substrate, the pixel defining layer includes a plurality of openings to define the opening regions of the plurality of sub-pixels, each At least part of the light-emitting layer of the light-emitting element of each sub-pixel is located in the opening corresponding to each sub-pixel; the first sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged along the first direction; In a direction perpendicular to the base substrate, the scan line overlaps with the opening area of the third sub-pixel and the opening area of the fourth sub-pixel.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate provided in any of the foregoing embodiments.
  • FIG. 1A is one of the schematic diagrams of the display substrate provided by at least one embodiment of the present disclosure.
  • 1B is one of the pixel circuit diagrams in the display substrate provided by at least one embodiment of the present disclosure
  • 2A is the second circuit diagram of a pixel in a display substrate provided by at least one embodiment of the present disclosure
  • 2B is a timing signal diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • 3A is a second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Fig. 3B is a cross-sectional view of Fig. 3A along the section line I-I';
  • 4A is the third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 4B is the fourth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure.
  • 5A is a sixth diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 5B is a seventh schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 5C is an enlarged schematic diagram of area A in FIG. 3A;
  • FIG. 5D is another enlarged schematic diagram of area A in FIG. 3A;
  • 6A is the eighth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure.
  • 6B is a ninth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7A is a tenth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7B is an eleventh diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • higher requirements are placed on the structural design of the display substrate, such as the arrangement of pixels and signal lines.
  • OLED display device with a resolution of 4K an OLED display device with a large size and a resolution of 8K has doubled the number of sub-pixel units that need to be installed, and the pixel density has doubled accordingly.
  • the signal line The line width of the signal line becomes smaller, which causes the signal line's own resistance to become larger; on the other hand, the overlap between the signal lines becomes more, which causes the parasitic capacitance of the signal line to become larger, which causes the resistance-capacitance load of the signal line to become larger.
  • the signal delay (RC delay), the voltage drop (IR drop), and the voltage rise (IR rise) caused by the RC load will also become serious. These phenomena will seriously affect the display quality of the display product.
  • a pixel circuit with compensation function can be used to drive the light-emitting element to eliminate the influence of the unevenness of the threshold voltage of the driving transistor on the light-emitting current.
  • the gate voltage of the driving transistor will be under-compensated during the threshold compensation stage, that is, the threshold voltage of the driving transistor cannot be fully compensated, so the driving current in the light-emitting stage is still It is related to the threshold voltage Vth of the driving transistor, which causes the uniformity of the brightness of the display device to decrease.
  • the voltage stability of the gate of the driving transistor is not only related to the stability of the driving transistor itself, but also related to the stability of the circuit (or transistor) directly connected to the gate. For example, when the transistor directly connected to the gate is unstable, a charge leakage path may be formed, resulting in insufficient compensation of the driving transistor, resulting in uneven display.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a plurality of sub-pixels distributed on the base substrate in an array.
  • Each of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, the pixel circuit is used to drive the light-emitting element to emit light, and the plurality of pixel circuits are arranged in a first direction and a second direction; each of the plurality of pixel circuits It includes a driving sub-circuit and a compensation sub-circuit;
  • the driving sub-circuit includes a control electrode, a first end and a second end, and is configured to be connected to the light-emitting element and control the driving current flowing through the light-emitting element;
  • the compensation The sub-circuit includes a control electrode, a first electrode and a second electrode, the control electrode of the compensation sub-circuit is configured to receive a second scan signal, and the first electrode and the second electrode of the compensation sub-circuit are respectively connected to the driving
  • the plurality of sub-pixels includes a first sub-pixel
  • the first driving electrode of the light-emitting element of the first sub-pixel includes a first body portion and a first protruding portion, the first body portion It includes a first side parallel to a certain direction, the first protruding portion protrudes from the first side of the main body portion, and the connecting portion of the first protruding portion and the compensation sub-circuit of the first sub-pixel is perpendicular to At least partially overlap in the direction of the base substrate; the first sub-pixel is configured to emit green light.
  • the sensitivity of the human eye to the green sub-pixel is much higher than that of the blue sub-pixel and the red sub-pixel.
  • the first driving electrode of the light-emitting element of the green sub-pixel (first sub-pixel) is provided with the first driving electrode of the compensation sub-circuit connected to the control electrode of the driving sub-pixel.
  • the connection part between the one electrode and the second electrode is shielded to prevent the compensation sub-circuit from being unstable due to light exposure to the threshold value drift, thereby improving the stability of the voltage on the control electrode of the driving sub-circuit, and thereby The display uniformity of the display substrate is improved.
  • the display substrate 20 includes a display area 110 and a non-display area 103 outside the display area 110.
  • the non-display area 103 is located in the peripheral area of the display area 110.
  • the display substrate 20 includes a plurality of sub-pixels 100 located in the display area 110.
  • the plurality of sub-pixels are arranged in an array, for example, a plurality of pixel rows and a plurality of pixel columns are arranged along the first direction D1 and the second direction D2.
  • the first direction D1 and the second direction D2 are different, for example, they are orthogonal.
  • the pixel row and the pixel column do not necessarily extend strictly along a straight line, but may also extend along a curve (for example, a broken line), and the curve generally extends along the first direction D1 or the second direction D2, respectively.
  • Each sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light.
  • a plurality of pixel circuits are arranged in an array along the first direction D1 and the second direction D2.
  • the sub-pixels can form pixel units in a traditional RGB manner or a sub-pixel sharing manner (such as pentile) to achieve full-color display.
  • the present disclosure does not limit the arrangement of sub-pixels and the manner in which full-color display is achieved.
  • the display substrate 20 further includes a plurality of gate lines 11 and a plurality of data lines 12 and a plurality of pixel areas located in the display area 110, and each pixel area is correspondingly provided with a sub-pixel 100.
  • the gate line 11 extends in a first direction D1
  • the data line 12 extends in a second direction D2.
  • FIG. 1A only illustrates the approximate positional relationship of the gate line 11, the data line 12, and the sub-image 100 in the display substrate, which can be specifically designed according to actual needs.
  • the pixel circuit is, for example, a 2T1C (that is, two transistors and one capacitor) pixel circuit, 4T2C, 5T1C, 7T1C, and other nTmC (n, m are positive integers) pixel circuits.
  • the pixel circuit may further include a compensation sub-circuit, the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, and the like.
  • the display substrate may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area.
  • the gate driving sub-circuit 13 is connected to the pixel circuit through the gate line 11 to provide various scanning signals
  • the data driving sub-circuit 14 is connected to the pixel circuit through the data line 12 to provide data signals.
  • the gate driving sub-circuit 13 and the data driving sub-circuit 14 shown in FIG. 1A, and the positional relationship of the gate line 11 and the data line 12 in the display substrate are just examples, and the actual arrangement position can be designed according to needs.
  • the display substrate 20 may further include a control circuit (not shown).
  • the control circuit is configured to control the data driving sub-circuit 14 to apply the data signal and the gate driving sub-circuit to apply the scan signal.
  • An example of this control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, for example, including a processor and a memory.
  • the memory includes executable code, and the processor runs the executable code to execute the foregoing detection method.
  • the processor may be a central processing unit (CPU) or other form of processing device with data processing capability and/or instruction execution capability, and may include, for example, a microprocessor, a programmable logic controller (PLC), and the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • the storage device may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory.
  • Volatile memory may include random access memory (RAM) and/or cache memory (cache), for example.
  • the non-volatile memory may include read-only memory (ROM), hard disk, flash memory, etc., for example.
  • One or more computer program instructions can be stored on a computer-readable storage medium, and the processor can execute functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit, and may also include a light-emitting control sub-circuit, a reset circuit, etc., as required.
  • FIG. 1B shows a schematic diagram of a pixel circuit.
  • the pixel circuit includes a driving sub-circuit 122 and a compensation sub-circuit 128.
  • the driving sub-circuit 122 includes a control terminal (control electrode) 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light-emitting element 120 and control the driving current flowing through the light-emitting element 120.
  • the control terminal 122a of the driving sub-circuit 122 is connected to the first node N1
  • the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2
  • the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.
  • the compensation sub-circuit 128 includes a control terminal (control electrode) 128a, a first terminal (first electrode) 128b, and a second terminal (second electrode) 128c, and the control terminal 128a of the compensation sub-circuit 128 is configured to receive the second scan signal Ga2, the first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively, and the compensation sub-circuit 128 is configured to respond to the second scan signal Ga2.
  • the driving sub-circuit 122 performs threshold compensation.
  • the compensation sub-circuit 128 further includes a connecting portion located between the first electrode 128b and the second electrode 128c of the compensation sub-circuit and connecting the first electrode 128b and the second electrode 128c.
  • the protrusion of the first driving electrode of the light-emitting element of one sub-pixel at least partially overlaps in a direction perpendicular to the base substrate.
  • the connecting portion and the first electrode and the second electrode of the compensation sub-circuit are located on the same side of the control electrode of the compensation sub-circuit with respect to the base substrate.
  • the connecting portion includes at least one semiconductor region. This will be described in detail later in conjunction with the specific structure of the display substrate.
  • the pixel circuit further includes a data writing sub-circuit 126, a storage sub-circuit 127, a first light-emission control sub-circuit 123, a second light-emission control sub-circuit 124, and a first reset sub-circuit 125 and a second reset sub-circuit 129.
  • the data writing sub-circuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c.
  • the control terminal 126a is configured to receive the first scan signal Ga1
  • the first terminal 126b is configured to receive the data signal Vd
  • the second terminal 126c is configured to receive the data signal Vd.
  • the first terminal 122b (that is, the second node N2) of the driving sub-circuit 122 is connected.
  • the data writing sub-circuit 126 is configured to write the data signal Vd into the first terminal 122 b of the driving sub-circuit 122 in response to the first scan signal Ga1.
  • the first terminal 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scan line to receive the first scan signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written into the first terminal 122b (the second node N2) of the driving sub-circuit 122,
  • the data signal is stored in the storage sub-circuit 127, so that a driving current for driving the light-emitting element 120 to emit light can be generated according to the data signal during the light-emitting phase, for example.
  • the first scan signal Ga1 may be the same as the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to the same signal output terminal.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through the same scan line.
  • the first scan signal Ga1 may also be different from the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines, respectively.
  • the storage sub-circuit 127 includes a first terminal (also called a first storage electrode) 127a and a second terminal (also called a second storage electrode) 127b.
  • the first terminal 127a of the storage sub-circuit is configured to receive the first power supply voltage VDD and store
  • the second terminal 127b of the sub-circuit is electrically connected to the control terminal 122a of the driving sub-circuit.
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127; at the same time;
  • the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the threshold voltage related information of the driving sub-circuit 122 can be correspondingly stored in the storage sub-circuit, for example,
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 so that the output of the driving sub-circuit 122 is compensated.
  • the storage sub-circuit 127 is electrically connected to the control terminal 122 a and the first voltage terminal VDD of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126.
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127.
  • the compensation sub-circuit 128 may electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the threshold voltage related information of the driving sub-circuit 122 can be stored accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting phase, so that the output of the driving sub-circuit 122 is compensated.
  • the first light-emitting control sub-circuit 123 is connected to the first terminal 122b (the second node N2) of the driving sub-circuit 122 and the first voltage terminal VDD, and is configured to turn the first voltage terminal VDD in response to the first light-emitting control signal EM1
  • the first power supply voltage of is applied to the first terminal 122b of the driving sub-circuit 122.
  • the first light emission control sub-circuit 123 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.
  • the second light-emitting control sub-circuit 124 and the second light-emitting control terminal EM2 are connected, and are configured to drive current in response to the second light-emitting control signal. It can be applied to the light emitting element 122.
  • the second light-emission control sub-circuit 123 is turned on in response to the second light-emission control signal EM2 provided by the second light-emission control terminal EM2, so that the driving sub-circuit 122 can interact with the light-emitting element 120 through the second light-emission control sub-circuit 123 Are electrically connected to drive the light-emitting element 120 to emit light under the control of the driving current; and in the non-light-emitting phase, the second light-emission control sub-circuit 123 is turned off in response to the second light-emission control signal EM2, so as to avoid current flowing through the light-emitting element 120. It emits light and can improve the contrast of the corresponding display device.
  • the second light-emitting control sub-circuit 124 may also be turned on in response to the second light-emitting control signal, so that the reset circuit may be combined with the reset circuit to perform a reset operation on the driving sub-circuit 122 and the light-emitting element 120.
  • the second lighting control signal EM2 may be the same as the first lighting control signal EM1, for example, the second lighting control signal EM2 may be connected to the same signal output terminal as the first lighting control signal EM, for example, the second lighting control signal EM2 may be The first emission control signal EM is transmitted through the same emission control line.
  • the second light emission control signal EM2 may be different from the first light emission control signal EM1.
  • the second light emission control signal EM2 and the first light emission control signal EM1 may be connected to different signal output terminals, respectively.
  • the second light emission control signal EM2 and the first light emission control signal EM1 may be respectively transmitted through different light emission control lines.
  • the first reset sub-circuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the driving sub-circuit 122, and is configured to apply the first reset voltage Vinit1 in response to the first reset control signal Rst1 To the control terminal 122a of the driving sub-circuit 122.
  • the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 122b (fourth node N4) of the light emitting element 122, and is configured to apply the second reset voltage Vinit2 in response to the second reset control signal Rst2 To the first end 134 of the light-emitting element 120.
  • the first reset sub-circuit 125 and the second reset sub-circuit 129 may be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 may be applied to the first node, respectively.
  • N1 and the first reset voltage Vinit1 is applied to the first end 134 of the light-emitting element 120, so that the driving sub-circuit 122, the compensation sub-circuit 128, and the light-emitting element 120 can be reset to eliminate the influence of the previous light-emitting stage.
  • the second reset control signal Rst2 of each row of sub-pixels may be the same signal as the first scan signal Ga1 of the row of sub-pixels, and the two may be transmitted through the same gate line 11.
  • the first reset control signal Rst1 of each row of sub-pixels and the first scan signal Ga1 of the previous row of sub-pixels may be transmitted through the same gate line 11.
  • the light-emitting element 120 includes a first end (also referred to as a first electrode or a first driving electrode) 134 and a second end (also referred to as a second electrode or a second driving electrode) 135, and the first end 134 of the light-emitting element 120 It is configured to be connected to the second terminal 122c of the driving sub-circuit 122, and the second terminal 135 of the light emitting element 120 is configured to be connected to the second voltage terminal VSS.
  • the first end 134 of the light-emitting element 120 may be connected to the fourth node N4 through the second light-emitting control sub-circuit 124.
  • the embodiments of the present disclosure include but are not limited to this situation.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but represent the connections of related circuits in the circuit diagram. Meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal.
  • the signal can also represent the first scan signal terminal and the second scan signal terminal.
  • Rst can represent both the reset control terminal and the reset control signal.
  • the symbols Vinit1 and Vinit2 can both represent the first reset voltage terminal and the second reset voltage terminal. It can represent the first reset voltage and the second reset voltage.
  • the symbol VDD can represent both the first voltage terminal and the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 2A is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 1B.
  • the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving sub-circuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the first transistor T1 serves as the second terminal 122c of the driving sub-circuit 122 and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal ,
  • the second pole of the second transistor T2 is connected to the first terminal 122b (the second node N2) of the driving sub-circuit 122.
  • the compensation sub-circuit 128 may be implemented as a third transistor T3.
  • the gate, first electrode, and second electrode of the third transistor T3 serve as the control electrode 128a, the first electrode 128b, and the second electrode 128c of the compensation sub-circuit, respectively.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal.
  • the first electrode of the third transistor T3 and the second terminal 122c (the first The three nodes N3) are connected, and the second pole of the third transistor T3 is connected to the control terminal 122a (first node N1) of the driving sub-circuit 122.
  • the storage sub-circuit 127 may be implemented as a storage capacitor Cst.
  • the storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb.
  • the first capacitor electrode Ca is coupled to the first voltage terminal VDD.
  • the second capacitor electrode Cb and the control terminal 122a of the driving sub-circuit 122 are coupled, such as electrical connection.
  • the first light emission control sub-circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first emission control line (first emission control terminal EM1) to receive the first emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply Voltage, the second pole of the fourth transistor T4 is connected to the first terminal 122b (the second node N2) of the driving sub-circuit 122.
  • the light emitting element 120 is specifically implemented as a light emitting diode (LED), such as an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or an inorganic light emitting diode, for example, a micro light emitting diode (Micro LED) or a micro OLED.
  • LED light emitting diode
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light emitting element 120 may be a top emission structure, a bottom emission structure, or a double-sided emission junction.
  • the light-emitting element 120 can emit red light, green light, blue light, or white light.
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first electrode 134 (for example, the anode) of the light-emitting element 120 is connected to the fourth node N4 and configured to be connected to the second end 122c of the driving sub-circuit 122 through the second light-emitting control sub-circuit 124, and the second electrode of the light-emitting element 120 135 (for example, the cathode) is configured to be connected to the second voltage terminal VSS to receive the second power supply voltage VSS, and the circuit flowing from the second terminal 122c of the driving sub-circuit 122 into the light-emitting element 120 determines the brightness of the light-emitting element.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second voltage power supply voltage VSS may be a negative voltage.
  • the second light emission control sub-circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second emission control line (the second emission control terminal EM2) to receive the second emission control signal, and the first pole of the fifth transistor T5 is connected to the second terminal 122c (the first The three nodes N3) are connected, and the second electrode of the fifth transistor T5 is connected to the first end 134 (fourth node N4) of the light-emitting element 120.
  • the first reset sub-circuit 125 may be implemented as a sixth transistor T6, and the second reset sub-circuit is implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, and the first pole of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1,
  • the second pole of the sixth transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, and the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2,
  • the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the first to seventh transistors T1-T7 are all P-type transistors, such as low-temperature polysilicon thin film transistors.
  • the embodiments of the present disclosure do not limit the types of transistors. When the types of transistors are changed, the connection relationship in the circuit can be adjusted accordingly.
  • the display process of each frame of image includes three stages, namely the initialization stage 1, the data writing and compensation stage 2, and the light emitting stage 3.
  • the first scan signal Ga1 and the second scan signal Ga2 use the same signal
  • the first light emission control signal EM1 and the second light emission control signal EM2 use the same signal
  • the waveforms of Rst2 and the first scan signal Ga1/the second scan signal Ga2 are the same, that is, the second reset control signal Rst2, the first scan signal Ga1/the second scan signal Ga2 can use the same signal; the first reset of the sub-pixels in this row
  • the signal Rst1 has the same waveform as the first scan signal Ga1/second scan signal Ga2 of the sub-pixels in the previous row, that is, the same signal is used.
  • this is not a limitation of the present disclosure.
  • different signals may be used as the first scan signal Ga1, the second scan signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, respectively.
  • Different signals are used as the first light emission control signal EM1 and the second light emission control signal EM2, respectively.
  • the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.
  • the first scan signal Ga1, the second scan signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vd is written into the second node by the second transistor T2 N2, and charge the first node N1 through the first transistor T1 and the third transistor T3, until the potential of the first node N1 changes to Vd+Vth, the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1.
  • the potential of the first node N1 is stored in the storage capacitor Cst to be maintained, that is to say, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst for subsequent use in the light-emitting phase to provide gray Display data and compensate the threshold voltage of the first transistor T1 itself.
  • the second reset control signal Rst2 can also be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4, thereby resetting the fourth node N4.
  • the reset of the fourth node N4 may also be performed in the initialization phase 1.
  • the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiment of the present disclosure does not limit this.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5, and the first transistor T1, and the fifth transistor T5 applies a driving current to the OLED to make it emit light .
  • the value of the driving current I flowing through the OLED can be obtained according to the following formula:
  • Vth represents the threshold voltage of the first transistor T1
  • VGS represents the voltage between the gate and source (here, the first electrode) of the first transistor T1
  • K is a value related to the first transistor T1 itself. Constant value. It can be seen from the above calculation formula of I that the driving current I flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1, which can realize the compensation of the pixel circuit and solve the problem of the driving transistor (in the present disclosure).
  • the first transistor T1) causes the problem of threshold voltage drift due to the process and long-term operation, and eliminates its influence on the driving current I, so that the display effect of the display device using it can be improved.
  • FIG. 2A The following takes the pixel circuit shown in FIG. 2A as an example, combined with FIGS. 3A-3B, FIGS. 4A-4B, FIGS. 5A-5D, FIGS. 6A-6B, and FIGS.
  • the structure is exemplified.
  • FIG. 3A is a schematic diagram of a display substrate 20 provided by at least one embodiment of the present disclosure
  • FIG. 3B is a cross-sectional view of FIG. 5A along the section line I-I'. It should be noted that, for the sake of clarity, FIG. 3B omits some structures that do not have a direct electrical connection relationship at the section line.
  • the display substrate 20 includes a base substrate 101 on which a plurality of sub-pixels 100 are located.
  • the pixel circuits of the plurality of sub-pixels 100 are arranged as a pixel circuit array.
  • the column direction of the pixel circuit array is the first direction D1, the row direction is the second direction D2, and the first direction D1 and the second direction D2 cross, for example, orthogonally.
  • the first direction D1 may also be a row direction
  • the second direction D2 may also be a column direction.
  • the pixel circuit of each sub-pixel may have exactly the same structure except for the connection structure with the light-emitting element, that is, the pixel circuit is repeatedly arranged in the row and column directions, and the connection structure of the different sub-pixels with the light-emitting element is based on The arrangement shape and position of the electrode of the light emitting structure of each sub-pixel may be different.
  • the general frame of the pixel circuit of the sub-pixels of different colors for example, the shape and position of each signal line is basically the same, and the relative positional relationship of each transistor is also basically the same.
  • the width and shape Or some transistors, such as channel size and shape, or connecting lines or via positions for connecting with light-emitting elements of different sub-pixels may be different, which can be adjusted according to each layout structure and sub-pixel arrangement.
  • FIG. 3A exemplarily shows four sub-pixels (ie, the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d) directly adjacent to each other in a row of sub-pixels.
  • the embodiment is not limited to this layout.
  • the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d are configured to emit green light, green light, blue light, and red light, respectively.
  • the first sub-pixel 100 a, the second sub-pixel 100 b, the third sub-pixel 100 c, and the fourth sub-pixel 100 d constitute a repeating unit of the display substrate 20.
  • the layer 304 and the fourth conductive layer 204 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 3A.
  • FIG. 4A corresponds to FIG. 3A and illustrates the semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 in the four sub-pixels 100
  • FIG. 5A shows the second conductive layer 202
  • FIG. 5B is shown in FIG.
  • the second conductive layer 202 is shown on the basis of 4A
  • Fig. 6A shows the third conductive layer 203
  • Fig. 6B shows the third conductive layer 203 on the basis of Fig. 5B
  • Fig. 7A shows the fourth conductive layer 203.
  • the conductive layer 204, FIG. 7B shows the semiconductor layer 102, the first conductive layer 201, and the fourth conductive layer 204.
  • Tng, Tns, Tnd, and Tna are used to denote the gate, the first electrode, the second electrode, and the channel region of the n-th transistor Tn, where n is 1-7.
  • the “same-layer arrangement” mentioned in the present disclosure refers to a structure formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different.
  • the “integrated structure” in the present disclosure refers to two (or more than two) structures that are formed by the same deposition process and patterned by the same patterning process, and their materials can be the same or different. .
  • the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines.
  • a large dashed frame shows the area where the pixel circuit of each sub-pixel 100 is located, and a small dashed frame shows the gates T1g-T7g of the first to seventh transistors T1-T7 in one sub-pixel 100.
  • the semiconductor layer 102 includes the active layers T1a-T7a of the first to seventh transistors T1-T7. As shown in FIG. 3A, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integral structure.
  • the semiconductor layer 20 in each column of sub-pixels is an integrated structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.
  • the first conductive layer 201 includes the gates T1g-T7g of the first to seventh transistors T1-T7.
  • the display substrate 20 adopts a self-aligning process and uses the first conductive layer 201 as a mask to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102, so that the semiconductor layer 102 is not covered by the first conductive layer 201.
  • the covered part is made conductive, so that the part of the active layer of each transistor located on both sides of the channel region is made conductive to form the first electrode and the second electrode of the transistor, respectively.
  • FIG. 4B shows an enlarged schematic diagram of the area A of the first sub-pixel 100a in FIG. 3A.
  • the first driving electrode 134a of the light-emitting element of the first sub-pixel 100a includes a first main body portion 141 and a first protruding portion 142.
  • the first body portion includes a first side 141a parallel to a certain direction, for example, the first side 141a is a straight side parallel to the first direction D1.
  • the first protrusion 142 protrudes from the first side 141a of the first main body 141.
  • the compensation sub-circuit of the first sub-pixel 100a further includes its first electrode (that is, the first electrode T3s of the third transistor T3) and its second electrode (that is, the third transistor T3).
  • the connecting portion 128d between the second electrode T3d) and connecting the first electrode and the second electrode, the first protrusion 142 and the connecting portion 128d of the compensation sub-circuit of the first sub-pixel 100a are perpendicular to the substrate The direction of the substrate 101 at least partially overlaps.
  • the connecting portion 128d includes a first semiconductor region T3a1, a conductive region T3c, and a second semiconductor region T3a2.
  • the first semiconductor region T3a1 separates the first electrode of the compensation sub-circuit from the conductive region T3c.
  • the second semiconductor region T3a2 separates the second electrode of the compensation sub-circuit from the conductive region T3a2, that is, the first electrode T3s of the third transistor T3, the first semiconductor region T3a1, the conductive region T3c, the second The semiconductor region T3a2 and the second pole T3d are sequentially connected.
  • the connecting portion, the first electrode, and the second electrode of the compensation sub-circuit are located on the same semiconductor layer 102 and form an integrated structure, that is, the first electrode T3s and the second electrode of the third transistor T3
  • a semiconductor region T3a1, a conductive region T3c, a second semiconductor region T3a2, and a second electrode T3d are integral structures located in the same semiconductor layer 102, for example, all include polysilicon material.
  • the third transistor T3 and the sixth transistor T6 adopt a double-gate structure, which can improve the gate control capability of the transistor and reduce the leakage current. Since the third transistor T3 and the sixth transistor T6 are transistors directly connected to the gate of the first transistor T1 (that is, the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the first transistor T1 (that is, the driving transistor).
  • the double-gate structure is adopted to improve the gate control capability of the third transistor T3 and the sixth transistor T6, which helps to reduce the leakage current of the transistor and thus helps maintain the voltage of the N1 node.
  • the threshold voltage of the first transistor T1 is It helps to obtain sufficient compensation, thereby improving the display uniformity of the display substrate in the light-emitting stage.
  • the gate of the third transistor T3 includes a first gate T3g1 and a second gate T3g2.
  • the first semiconductor region T3a1, the second semiconductor region T3a2, the conductive region T3c, the first electrode T3s, and the second electrode T3d are located in the same semiconductor layer 102 and are integrally formed, and are formed by selective conductive treatment (such as ion implantation) Different electrical conductivity.
  • the first semiconductor region and the second semiconductor region are respectively shielded by the first gate T3g1 and the second gate T3g2 and therefore are not shown in FIG. 4A; that is, the first semiconductor region T3a1 is on the base substrate 101
  • the orthographic projection is located within the orthographic projection of the first grid T3g1 on the base substrate 101, and the orthographic projection of the second semiconductor region T3a2 on the base substrate 101 is located on the orthographic projection of the second grid T3g2 on the base substrate 101 Inside.
  • the conductive region T3c does not overlap with the first gate T3g1 and the second gate T3g2 in a direction perpendicular to the base substrate.
  • the first semiconductor region T3a1 of the third transistor T3 and at least part of the first gate T3g1 are perpendicular to the first electrode of the light-emitting element thereof.
  • the direction of the substrate 101 is at least partially overlapped, that is, in the direction perpendicular to the base substrate 101, at least a portion of the first gate electrode T3g1 that overlaps the first semiconductor region T3a1 of the third transistor T3 is covered by the light-emitting element
  • the first electrode is shielded. This will be described in detail later when introducing the fourth conductive layer where the first electrode of the light-emitting element is located.
  • the first electrode of the light-emitting element of the first sub-pixel is arranged to block at least part of the gate of the third transistor (compensation transistor), thereby improving the stability of the compensation transistor, thereby improving display uniformity .
  • the first semiconductor region T3a1 of the compensation sub-circuit of the first sub-pixel overlaps with the first electrode 134 of the light-emitting element 120 of the first sub-pixel in a direction perpendicular to the base substrate 101.
  • the ratio of the area of the first semiconductor region T3a1 to the area of the first semiconductor region T3a1 is 50%-100%; that is, the first electrode 134 of the light-emitting element 120 may completely cover the first semiconductor region T3a1.
  • the first protrusion 142 of the first electrode 134 of the light-emitting element 120 and the conductive region T3c and the first semiconductor region T3a1 of the compensation sub-circuit are at least in a direction perpendicular to the base substrate 101, respectively. Partially overlapped.
  • the first protrusion 142 of the first electrode 134 of the light-emitting element 120 may only overlap with the first semiconductor region T3a1 and overlap with the conductive region T3c. Does not overlap.
  • the first protrusion 142 of the first electrode 134 of the light-emitting element 120 may not overlap with the first semiconductor region T3a1 of the compensation sub-circuit in a direction perpendicular to the base substrate 101; in this way
  • the main body portion 141 of the first electrode 134 completely covers the first semiconductor region T3a1 of the compensation sub-circuit.
  • the projections of the first side 141a of the main body portion 141 of the first electrode 134 and the side of the first gate T3g1 adjacent to the conductive area T3c on the base substrate 101 coincide.
  • the maximum y1 size of the first protrusion 142 is smaller than the average size of the first gate T3g1 of the compensation sub-circuit.
  • the maximum y1 size of the first protrusion 142 is less than 3 micrometers, for example, less than 2 micrometers, for example, between 1 micrometer and 2 micrometers.
  • the first protrusion 142 is located between the first gate T3g1 and the second gate T3g2, and does not overlap with the second gate T3g2 in a direction perpendicular to the base substrate.
  • the orthographic projection of the first electrode 134 of the light-emitting element on the base substrate 101 is divided into two parts by the orthographic projection of the first grid T3g1 on the base substrate 101, that is, the The orthographic projection of the first electrode 134 of the light-emitting element on the base substrate 101 includes a first portion and a second portion located on both sides of the orthographic projection of the first gate T3g1 on the base substrate 101 in the second direction D2 , wherein the first portion and the orthographic projection of the conductive area T3c of the compensation sub-circuit on the base substrate at least partially overlap, and the area S1 of the first portion is smaller than the orthographic projection of the first electrode of the light-emitting element on the base substrate 101 1/10 of the total area of S2, for example, S1 is less than 1/20 of S2. For example, when the first protrusion 142 does not overlap the conductive region T3c, the area S1 of the first portion may be zero.
  • the maximum dimension x1 of the first protrusion 142 is 1/8-1/3 of the maximum dimension x2 of the first electrode 134 of the light-emitting element, for example, 1. /6-1/4.
  • the maximum dimension x1 of the first protrusion 142 is between 5 ⁇ m and 10 ⁇ m, for example, 6 ⁇ m.
  • the conductive region T3c is L-shaped and includes a first branch T3c1 and a second branch T3c2.
  • the first branch T3c1 extends along the second direction D2 and is connected to the first semiconductor region of the compensation sub-circuit.
  • T3a1 is directly connected;
  • the second branch T3c2 extends along the first direction D1 and is directly connected to the second electrode of the compensation sub-circuit, that is, the second semiconductor region T3a2 of the third transistor T3.
  • the first conductive layer 104 further includes a plurality of gate lines 11 insulated from each other.
  • the gate lines 11 include, for example, a plurality of scan lines 210, a plurality of reset control lines 220, and a plurality of light-emitting control lines 230.
  • the gate line 11 refers to a signal line directly connected to the gate of the transistor to provide a scan signal or a control signal.
  • each row of sub-pixels is respectively connected to one scan line 210, two reset control lines 220, and one light emission control line 230.
  • the scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide the first scan signal Ga1, and the reset control line 220 is connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels.
  • the gate is electrically connected to provide the first reset control signal Rst1
  • the emission control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 may be the same signal;
  • the control line 230 is also electrically connected to the gate of the fifth transistor T5 to provide a second light emission control signal EM2, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal.
  • the first gate T3g1 extends along the first direction D1 and is a part of the scan line 210.
  • the second gate T3g2 extends along the second direction D2 and is an extension of the scan line 210 along the second direction D2.
  • the gate of the seventh transistor T7 of the pixel circuit of the current row and the pixel circuit of the next row (that is, according to the scanning order of the scan line, the pixel circuit row where the scan line is sequentially turned on after the scan line of the current row is located )
  • the corresponding reset control line 220 is electrically connected to receive the second reset control signal Rst2.
  • the second conductive layer 202 includes a first capacitor electrode Ca.
  • the first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in the direction perpendicular to the base substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the first transistor of the storage capacitor Cst.
  • the first capacitor electrode Ca includes an opening 222 that exposes at least part of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.
  • the first capacitor electrodes Ca of the sub-pixels located in the same pixel row are connected to each other as an integral structure.
  • the second conductive layer 202 may further include a plurality of reset voltage lines 240 extending along the first direction D1, and the plurality of reset voltage lines 240 are connected to a plurality of rows of sub-pixels in a one-to-one correspondence.
  • the reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1.
  • the first pole of the seventh transistor T7 in the sub-pixels in the current row is electrically connected to the reset voltage line 240 corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2. This will be described in detail later in conjunction with FIG. 6B.
  • the second conductive layer 202 may further include a shield electrode 221.
  • the shielding electrode 221 overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 to protect the signal in the first electrode T2s of the second transistor T2 from interference by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display gray scale of the sub-pixel, the shield electrode 221 improves the stability of the data signal, thereby improving the display performance.
  • the shielding electrode 221 also at least partially overlaps the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 101 to improve the stability of the signal in the second electrode T6d. Therefore, the stability of the sixth transistor T6 is improved, and the gate voltage of the first transistor T1 is further stabilized.
  • the shielding electrode 221 also extends to the adjacent sub-pixel and is at least in a direction perpendicular to the base substrate 101 with the conductive region T3c of the third transistor T3 in the adjacent sub-pixel. Partially overlapped to improve the stability of the signal in the conductive region T3c, thereby improving the stability of the third transistor T3, and further stabilizing the gate voltage of the first transistor T1.
  • the overlapping area of the conductive area T3c of the compensation sub-circuit of the first sub-pixel and the first protrusion 142 is smaller than that of the compensation sub-circuit of the first sub-pixel.
  • the shielding electrode 221 and the first electrode T2s of the second transistor T2 or the conductive region T3c of the third transistor T3 or the second electrode T6d of the sixth transistor T6 directly opposite (overlapped) therewith form a stable capacitance.
  • the shielding electrode 221 is configured to be loaded with a fixed voltage. Since the voltage difference across the capacitor cannot change suddenly, the first pole T2s of the second transistor T2, the conductive area T3c of the third transistor T3, and the second pole T6d of the sixth transistor T6 are increased. The stability of the upper voltage.
  • the shield electrode 221 is electrically connected to the power line 250 in the third conductive layer to load the first power voltage VDD.
  • the shielding electrode 221 is L-shaped and includes a first branch 221a and a second branch 221b that extend in different directions.
  • the first branch 221a and the second electrode T6d of the sixth transistor T6 at least partially overlap in a direction perpendicular to the base substrate 101;
  • the second branch 221b is respectively overlapped with the first electrode T2s of the second transistor T2 and the adjacent sub-
  • the conductive region T3c of the third transistor T3 in the pixel at least partially overlaps in the direction perpendicular to the base substrate 101.
  • the first branch 221a extends along the second direction D2
  • the second branch 221b extends along the first direction D1; that is, in a direction perpendicular to the base substrate, it is electrically connected to the compensation sub-circuit of the first sub-pixel 100a.
  • the shielding electrode 121 overlapping the region T3c is the shielding electrode in the sub-pixel adjacent to the first sub-pixel 100a in the first direction D1 and close to the side of the compensation sub-circuit.
  • FIG. 5C shows an example of an enlarged schematic diagram of area A in FIG. 3A. As shown in FIG. The two gates T3g2 do not overlap, so as to avoid the influence of the parasitic capacitance on the gate signal.
  • the shield electrode 221 and the light-emitting element 134 of the first sub-pixel 100a at least partially overlap, and the average size d1 of the overlap in the second direction D2 is 0.1 micrometer to 1 micrometer, for example, 0.1 micrometer to 0.5 micrometer.
  • FIG. 5D shows another example of an enlarged schematic view of the area A in FIG. 3A.
  • the shielding electrode 221 does not overlap the light-emitting element 134 of the first sub-pixel 100a.
  • the third conductive layer 203 includes a plurality of power lines 250 extending along the second direction D2.
  • the multiple power lines 250 are electrically connected to multiple columns of sub-pixels in a one-to-one correspondence to provide the first power voltage VDD.
  • the power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via hole 342, and is electrically connected to the first electrode of the fourth transistor T4 through the via hole 343.
  • the power line 250 is also electrically connected to the shield electrode 221 through the via 341, so that the shield electrode 221 has a fixed potential, which improves the shielding ability of the shield electrode.
  • the via hole 342 and the via hole 341 both penetrate the third insulating layer 303, and the via hole 343 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.
  • the third conductive layer 203 further includes a plurality of data lines 12 extending along the second direction D2.
  • the multiple data lines 12 are electrically connected to multiple columns of sub-pixels in a one-to-one correspondence to provide data signals.
  • the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in the corresponding column of sub-pixels through the via 346 to provide the data signal.
  • the via 346 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.
  • the third conductive layer 203 further includes a first connecting electrode 231, one end of the first connecting electrode 231 passes through the opening 222 in the first capacitor electrode Ca and the insulating layer
  • the via hole 344 in the first transistor T1 is electrically connected to the gate T1g of the first transistor T1, that is, the second capacitor electrode Cb, and the other end is electrically connected to the first electrode of the third transistor T3 through the via hole 345, thereby the second capacitor
  • the electrode Cb is electrically connected to the first electrode T3s of the third transistor T3.
  • the via hole 344 penetrates the second insulating layer 302 and the third insulating layer 303.
  • the via 345 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.
  • the third conductive layer 203 further includes a second connecting electrode 232, and the second connecting electrode 233 is electrically connected to the second electrode T5d of the fifth transistor T5 through the via 349. Is connected and used to electrically connect the second electrode T5d of the fifth transistor T5 with the first electrode 134 of the light-emitting element.
  • the via 349 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303. This will be explained in detail later.
  • the third conductive layer 203 further includes a third connection electrode 233.
  • One end of the third connection electrode 233 is electrically connected to the reset voltage line through a via hole 348, and the other end is electrically connected to the reset voltage line through a via hole 347.
  • the sixth transistor T6 is electrically connected so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240.
  • the via hole 348 penetrates the third insulating layer 303.
  • the via 404 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.
  • the first pole of the seventh transistor T7 in the sub-pixels in the previous row is electrically connected to the reset voltage line 240 corresponding to the sub-pixels in the current row to receive the second reset voltage Vinit2.
  • the first electrode of the seventh transistor T7 is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels to receive the second reset voltage Vinit2.
  • FIG. 7A shows a schematic diagram of the fourth conductive layer 204; in order to facilitate the description of the relative positional relationship between the first electrode of the light-emitting element and the gate and channel regions of each transistor in the embodiment of the present disclosure, FIG. 7B shows the semiconductor layer 102 , The first conductive layer 201 and the fourth conductive layer 204.
  • the fourth conductive layer 204 includes the first electrode 134 of the light-emitting element, for example, includes the first electrode 134a of the first sub-pixel 100a and the first electrode 134b of the second sub-pixel 100b. , The first electrode 134c of the third sub-pixel 100c and the first electrode 134d of the fourth sub-pixel 100d.
  • the first electrode 134 of each sub-pixel is electrically connected to the second connection electrode 232 in the sub-pixel through the via 340, and thus is electrically connected to the second electrode T5d of the fifth transistor T5 through the second connection electrode 233.
  • the via 340 penetrates the fourth insulating layer 304, for example.
  • the display substrate 20 may further include a pixel defining layer 305 on the first electrode of the light-emitting element.
  • An opening formed in the pixel defining layer 305 exposes at least a part of the first electrode 134 so as to define an opening area (ie, an effective light-emitting area) 600 of each sub-pixel of the display substrate.
  • the light-emitting layer 136 of the light-emitting element 120 is formed at least in the opening (the light-emitting layer 136 may also cover part of the surface of the pixel defining layer away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form The light-emitting element 120.
  • the second electrode 135 is a common electrode, and the entire surface is arranged in the display substrate 20.
  • the first electrode 134 is the anode of the light-emitting element
  • the second electrode 135 is the cathode of the light-emitting element.
  • FIG. 7A shows the position of the opening area 600 on the first electrode of the light-emitting element of each sub-pixel, and shows the position of the via hole 340 of the pixel electrode relative to each first electrode 134.
  • the orthographic projection of the via 340 and the opening area 600 on the base substrate 101 does not overlap, that is, the orthographic projection of the via 340 on the base substrate 101 is outside the opening area 600. Since the via 340 is closer to the light-emitting layer 136 in the direction perpendicular to the base substrate 101, this arrangement prevents the via 340 from affecting the flatness of the light-emitting layer in the opening area and thereby affecting the light-emitting quality.
  • the vias 349 and the vias 340 partially overlap but not completely overlap or do not overlap in the direction perpendicular to the base substrate 101, so as to prevent the via stacking in the direction perpendicular to the substrate from causing the vias.
  • the location is prone to poor connection, disconnection or unevenness.
  • the via 349 and the via 340 do not overlap in the direction perpendicular to the base substrate 101.
  • the via hole penetrating a certain layer may be formed such that the size on one surface of the film layer is larger than the size on the opposite surface, and the range of the via hole may be the largest size formed in the corresponding film layer.
  • the first semiconductor region T3a1 of the compensation sub-circuit that is, the third transistor T3 of the first sub-pixel 100a and the first electrode 134a of the light-emitting element of the first sub-pixel are perpendicular to the substrate.
  • the direction of the base substrate 101 at least partially overlaps.
  • the area of the first semiconductor region T3a1 that overlaps the first electrode 134a in the direction perpendicular to the base substrate 101 and the total area of the first semiconductor region T3a1 occupy a range of 20%-100%, for example It is 50%-100%.
  • the first electrode 134a of the light-emitting element of the first sub-pixel is also connected to the conductive region T3c of the third transistor T3 of the first sub-pixel. At least partially overlap, so as to maximize the area of the first gate T3g1 of the third transistor T3 that is blocked by the first electrode 134a.
  • the orthographic projection of the first gate T3g1 on the base substrate 101 is located within the orthographic projection of the first electrode 134a on the base substrate 101.
  • the first gate T3g1 here refers to a portion of the scan line 210 that overlaps the first semiconductor region T3a1 in a direction perpendicular to the base substrate 101.
  • the orthographic projection of the first protrusion 142 of the first sub-pixel 100a on the base substrate 101 and the via 340 corresponding to the first sub-pixel 100a are respectively located
  • the control electrodes T1g of the driving sub-circuit of the first sub-pixel 100a are on both sides of the orthographic projection on the base substrate 101.
  • the first electrode 134a of the light-emitting element of the first sub-pixel includes a first body portion 141 and a first protruding portion 142, and the first body portion 141 includes a portion parallel to the first direction D1.
  • the first protrusion 142 protrudes or extends from the first side along the second direction D2.
  • the first protrusion 142 and the conductive region T3c of the third transistor T3 at least partially overlap in a direction perpendicular to the base substrate; that is, the first protrusion 142 is disposed corresponding to the conductive region T3c.
  • the first electrode 134b of the light-emitting element of the second sub-pixel 100b and the first electrode 134a of the light-emitting element of the first sub-pixel 100a are arranged side by side in the second direction D2, and the light-emitting element of the second sub-pixel
  • the first electrode 134b includes a second side 141b substantially parallel to and opposite to the first side 141a.
  • the first side 141a is the approximately straight part of the side of the first electrode 134a close to the first electrode 134b of the light-emitting element of the second sub-pixel, that is, the part of the protrusion and the second side 141b of the first electrode 134b are not parallel. of.
  • the maximum dimension y1 of the first protrusion 142 of the compensation sub-circuit of the first sub-pixel in the second direction D2 is smaller than the distance between the first side 141a and the second side 141b 1/3 of y2 to leave enough process margin to ensure that the first electrode of the first sub-pixel and the first electrode of the second sub-pixel are insulated from each other.
  • the pixel circuits of the first sub-pixel 100a and the pixel circuits of the second sub-pixel 100b are arranged side by side in the second direction D2, that is, they are located in different rows.
  • the opening area 600 of the first sub-pixel 100a and the opening area 600 of the second sub-pixel 100b are approximately symmetrical with respect to the symmetry axis along the first direction D1.
  • the first semiconductor region T3a1 of the compensation sub-circuit of the second sub-pixel 100b and the first electrode 134b of the light-emitting element of the second sub-pixel 100b do not overlap in the direction perpendicular to the base substrate 101 .
  • the first electrode 134b of the light-emitting element of the second sub-pixel 100b extends to at least partially overlap with the control electrode T1g of the driving sub-circuit of the second sub-pixel in the direction perpendicular to the base substrate.
  • the scan line 210 connected to the second sub-pixel does not overlap in the direction perpendicular to the base substrate.
  • the first center point H1 of the orthographic projection of the first electrode 134a of the light-emitting element of the first sub-pixel 100a on the base substrate is located on the scan line 210 connected to the first sub-pixel 100a.
  • the orthographic projection on the base substrate and the light emission control line 230 connected to the first sub-pixel 100a are between the orthographic projection on the base substrate.
  • the first center point H1 of the orthographic projection of the first electrode 134a of the light-emitting element of the first sub-pixel 100a on the base substrate and the first electrode 134b of the light-emitting element of the second sub-pixel 100b are at The second center point H2 of the orthographic projection on the base substrate is respectively located on both sides of the orthographic projection of the scan line 210 connected to the first sub-pixel on the base substrate in the second direction D2, and the first center point H1 is closer to the orthographic projection of the scan line 210 on the base substrate than the second center point H2.
  • the first central point H1 here refers to the geometric center of the orthographic projection of the first electrode 134a of the light-emitting element of the first sub-pixel 100a on the base substrate
  • the second central point H2 refers to the geometric center of the light-emitting element of the second sub-pixel 100b.
  • the scan line 210 connected to the first sub-pixel 100a It is not connected to the second sub-pixel 100b.
  • the scan line 210 connected to the first sub-pixel 100a and the opening area 600 and the first sub-pixel 100c in line with the first sub-pixel are The opening regions 600 of the four sub-pixels 100d all overlap.
  • the design rule is related to the process capability of the device, the manufacturing process, the depth of the via hole, and the thickness of the material layer.
  • the distance between the first side 141a and the second side 141b is the minimum size that meets the design rule of the display substrate 20, thereby effectively increasing the pixel density.
  • the protrusion 142 is selectively arranged corresponding to the conductive region T3c, which can ensure the process margin as much as possible and improve the process yield.
  • the protrusion 142 and the second semiconductor region T3a2 of the third transistor of the first sub-pixel do not overlap in a direction perpendicular to the base substrate.
  • the second gate T3g2 of the third transistor T3 extends from the first side 210a of the scan line 210 parallel to the first direction D12 along the second direction D2.
  • the first side 141a of the first electrode 134b and the first side 210a of the scan line 210 overlap in a direction perpendicular to the base substrate 101, and the protrusion 142 and the second gate T3g2 are located on the scan line 210.
  • the size of the protrusion 142 is smaller than the size of the second gate T3g2.
  • the maximum dimension of the protrusion 134 is 1/5-1/3 of the distance between the first side 141a and the second side 141b; the maximum dimension of the protrusion 134 is the 1/20-1/10 of the largest dimension of the first electrode 134a.
  • the first electrode 134c of the light-emitting element of the third sub-pixel 100c includes a second body portion 143 and a second protruding portion 144, and the body portion 143 includes a third side 143a parallel to the second direction D2.
  • the second protrusion 144 protrudes from the third side 143a along the first direction D1, and the second protrusion 144 is perpendicular to the conductive region T3c of the compensation sub-circuit (that is, the third transistor T3) of the third sub-pixel 100c. At least partially overlap in the direction of the base substrate 101.
  • the first protrusion 142 of the first sub-pixel 100a and the second protrusion 144 of the adjacent third sub-pixel 100c at least partially overlap in the first direction D1, that is, there is an edge
  • a virtual straight line L1 extending in the first direction D1 overlaps the first protrusion 142 and the second protrusion 144 at the same time.
  • the virtual straight line L1 overlaps the second gate T3g2 of the compensation sub-circuit of the first sub-pixel in a direction perpendicular to the base substrate.
  • the first electrode 134 of the light-emitting element of the third sub-pixel 100c and the conductive area T3c of the compensation sub-circuit (that is, the third transistor T3) of the second sub-pixel 100b are at least in a direction perpendicular to the base substrate 101. Partially overlapped.
  • the second sub-pixel 100b and the third sub-pixel 100c are adjacent to each other in the first direction D1. As shown in FIG. 7B, in the first direction D1, the first sub-pixel 100a and the second sub-pixel 100b are respectively located on opposite sides of the third sub-pixel 100c. For example, as shown in FIG.
  • the orthographic projection of the opening area 600 of the first sub-pixel 100a on the base substrate 101 is located between two power lines 250 (respectively the first power line and the second power line), and The first power line and the second power line do not overlap or only partially overlap in the direction perpendicular to the base substrate 101.
  • This arrangement prevents the power line 250 from affecting the flatness of the light-emitting layer in the opening area of the first sub-pixel, thereby affecting the light-emitting quality (for example, causing color shift).
  • the opening area 600 of the third sub-pixel 100c is aligned on the base substrate 101 along the center line of the second direction D2 (passing through the midpoint of the largest dimension in the first direction D2).
  • the projection is located in the orthographic projection of the power cord 250 on the base substrate 101.
  • the first electrode 134b of the light-emitting element of the second sub-pixel 100b and the control electrode of the driving sub-circuit of the second sub-pixel are perpendicular to each other.
  • the direction of the base substrate at least partially overlaps.
  • the first electrode 134b includes a main body portion 145, a connecting portion 146, and an extending portion 147.
  • the main body portion 145 is mainly used to drive the light-emitting layer 136 to emit light
  • the connecting portion 146 is mainly used to connect to a corresponding pixel circuit.
  • the orthographic projection of the main body 145 on the base substrate 101 covers the orthographic projection of the opening area 600 on the base substrate 101.
  • the orthographic projection of the connection portion 146 on the base substrate 101 covers the orthographic projection of the second connection electrode 232 on the base substrate 101.
  • the extension 147 and the gate T1g of the first transistor T1 at least partially overlap in a direction perpendicular to the base substrate. For example, in the second direction D2, the main body portion 145, the connection portion 146, and the extension portion 147 are arranged in sequence, and the extension portion 147 is farther away from the main body portion 145 than the connection portion 146.
  • the first electrode 134b of the light-emitting element of the second sub-pixel 100b is intentionally extended to form a parasitic capacitance with the gate T1g of the first transistor T1. This is due to the fact that the first sub-pixel and the third sub-pixel The first electrodes of the light-emitting elements of the pixel and the fourth sub-pixel at least partially overlap with the gate electrode T1g of the corresponding first transistor T1 in a direction perpendicular to the base substrate. Therefore, by similarly disposing the second sub-pixels, the uniformity of the display substrate can be improved.
  • the average sizes of the main body portion 145, the connecting portion 146, and the extension portion 147 are sequentially reduced.
  • the extension 147 is located between the first electrode 134c of the light-emitting element of the third sub-pixel and the first electrode 134d of the light-emitting element of the fourth sub-pixel adjacent in the first direction.
  • the extension 147 The size of the 147 in the first direction D1 is reduced to be effectively insulated from the first electrodes 134c and 134d.
  • the extending portion 147 is approximately equal to the gap between the first electrode 134c of the light-emitting element of the third sub-pixel and the first electrode 134d of the light-emitting element of the fourth sub-pixel located on both sides.
  • the gap is less than 4 microns. In some examples, the gap is less than 3.5 microns. In some examples, the gap is less than 3 microns. In some examples, the gap is smaller than the gap between the first electrodes of the light-emitting elements of the two green sub-pixels.
  • each red sub-pixel and each blue sub-pixel can be shared by at least two pixel units, and each pixel unit can independently have a green sub-pixel. Since the blue sub-pixel and the red sub-pixel in each pixel are shared by adjacent pixel units, the pixels in the embodiments of the present invention are not pixels in a strict sense, and can be called virtual pixel units.
  • the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d constitute a repeating unit of the display substrate 20.
  • the light-emitting elements of the first sub-pixel 100a and the second sub-pixel 100b are both green sub-pixels.
  • the third sub-pixel 100c may be a blue sub-pixel
  • the fourth sub-pixel 100d may be a red sub-pixel.
  • the opening areas of the third sub-pixel 100c and the fourth sub-pixel 100d are alternately arranged; the opening areas 600 of the first sub-pixel 100a and the second sub-pixel 100b are in the second direction.
  • the upper part is arranged in a pair in parallel, and is located between the opening area 600 of the third sub-pixel 100c and the opening area 600 of the fourth sub-pixel 100d in the first direction.
  • the four sub-pixels in each repeating unit may form two dummy pixels, and the third sub-pixel 100c and the fourth sub-pixel 100d in the repeating unit are respectively shared by the two dummy pixels.
  • the fourth sub-pixel 100d and the first sub-pixel 100a located on its right side and adjacent to it constitute a virtual pixel
  • the third sub-pixel 100c in the adjacent (right) virtual pixel is borrowed.
  • a pixel unit is formed; the third sub-pixel 100c and the second sub-pixel 100b located on the right side thereof and adjacent thereto constitute a virtual pixel, and the adjacent fourth sub-pixel 100d (not shown on the right) is used to form the pixel unit.
  • the sub-pixels in a plurality of repeating units form a pixel array.
  • the sub-pixel density is 1.5 times the virtual pixel density
  • the column direction of the pixel array such as the second direction
  • the sub-pixel density is 1.5 times the virtual pixel density.
  • each pixel unit independently has a green sub-pixel, the density of the green sub-pixel is the highest, and the opening area of the green sub-pixel is set to be relatively small to achieve a high-density pixel distribution. In this case, the area of the pixel electrode of the green sub-pixel will also be relatively small.
  • the first electrode (ie, the pixel electrode) of the light-emitting element of the green sub-pixel is set to shield the channel region of the compensation sub-circuit and the control electrode corresponding to the channel region, While realizing high-resolution display, the stability of the compensation sub-circuit is improved, thereby improving the display uniformity of the display substrate.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET) ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC) and so on.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polys
  • the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , Polythiophene, etc.).
  • the material of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and the above Alloy materials made of combinations of metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • Au gold
  • silver Ag
  • Cu copper
  • Al aluminum
  • Mo molybdenum
  • Mo magnesium
  • W tungsten
  • conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the light-emitting element 120 has a top-emitting structure
  • the first electrode 134 has reflectivity
  • the second electrode 135 has transmissive or semi-transmissive properties.
  • the first electrode 134 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminate structure
  • the second electrode 135 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303 are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrides. Oxides, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • the fourth insulating layer 304 and the pixel defining layer 305 are respectively organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethylmethacrylate (PMMA) and other organic insulating materials.
  • the fourth insulating layer 304 is a planarization layer.
  • At least one embodiment of the present disclosure also provides a display panel including any of the above display substrates 20.
  • the display panel is an OLED display panel, and accordingly the display substrate 20 included therein is an OLED display substrate.
  • the display panel 30 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20.
  • the encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture. The penetration of gas and oxygen into the light-emitting element and the driving sub-circuit causes damage to the device.
  • the encapsulation layer 801 includes an organic thin film or a structure in which an inorganic thin film, an organic thin film, and an inorganic thin film are alternately stacked.
  • a water absorption layer (not shown) may be further provided between the encapsulation layer 801 and the display substrate 20, configured to absorb residual water vapor or sol in the preliminary manufacturing process of the light-emitting element.
  • the cover 802 is, for example, a glass cover or a flexible cover.
  • the cover plate 802 and the encapsulation layer 801 may be an integral structure.
  • At least one embodiment of the present disclosure further provides a display device 40.
  • the display device 40 includes any of the above-mentioned display substrate 20 or display panel 30.
  • the display device in this embodiment may be: a display, an OLED Panels, OLED TVs, electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and other products or components with display functions.

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Abstract

一种显示基板(20)以及显示装置(40)。该显示基板(20)包括衬底基板(101)及位于该衬底基板(101)上的多个子像素(100)，每个子像素(100)包括像素电路。该多个子像素(100)包括第一子像素(100a)，该第一子像素(100a)的补偿子电路(128)包括第一电极(128b)、第二电极(128c)以及位于第一电极(128b)和第二电极(128c)之间的连接部(128d)，该第一子像素(100a)的发光元件(120)的第一驱动电极(134)包括第一主体部(141)和第一突出部(142)，该第一主体部(141)包括与某一方向平行的第一边(141a)，该第一突出部(142)从该第一主体部(141)的第一边(141a)突出，该第一突出部(142)与该第一子像素(100a)的补偿子电路(128)的连接部(128d)在垂直于该衬底基板(101)的方向上至少部分重叠；该第一子像素(100a)的发光元件(120)配置为发绿光。该显示基板(20)可以有效提高显示均一性。

Description

显示基板及显示装置
本申请要求于2020年5月29日递交的中国专利申请第202010479764.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板及显示装置。
背景技术
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示领域，随着高分辨率产品的快速发展，对显示基板的结构设计，例如像素和信号线的排布等都提出了更高的要求。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板和成阵列分布于所述衬底基板上的多个子像素。所述多个子像素每个包括像素电路和发光元件，所述像素电路用于驱动所述发光元件发光，所述多个子像素沿第一方向和第二方向排列，所述第一方向和所述第二方向不同；所述像素电路包括驱动子电路和补偿子电路；所述驱动子电路包括控制电极、第一端和第二端，且配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；所述补偿子电路包括控制电极、第一电极和第二电极，所述补偿子电路的控制电极配置为接收扫描信号，所述补偿子电路的第一电极和第二电极分别与所述驱动子电路的控制电极和第二端连接，所述补偿子电路配置为响应于所述扫描信号对所述驱动子电路进行阈值补偿；所述发光元件包括依次层叠设置的第一电极、发光层和第二电极，所述发光元件的第一电极位于所述发光层靠近所述衬底基板的一侧；所述补偿子电路还包括位于所述补偿子电路的第一电极和所述第二电极之间且将所述第一电极和所述第二电极连接的连接部；所述第一电极、所述第二电极和所述连接部均位于所述补偿子电路的控制电极相对所述衬底基板的同一侧；所述多个子像素包括第一子像素，所述第一子像素的发光元件的第一驱动电极包括第一主体部和第一突出部，所述第一主体部包括与某一方向平行的第一边，所述第一突出部从所述第一主体部的第一边突出，所述第一突出部与所述第一子像素的补偿子电路的连接部在垂直于所述衬底基板的方向上至少部分重叠；所述第一子像素的发光元件配置为发绿光。
在一些示例中，所述第一主体部的第一边为直边且与所述第一方向平行，所述突出部从所述第一主体部的第一边沿所述第二方向突出。
在一些示例中，所述连接部包括第一半导体区、导电区和第二半导体区，所述第一半导体区将所述补偿子电路的第一电极和所述导电区间隔，所述第二半导体区将所述补偿子电路的第二电极与所述导电区间隔；所述补偿子电路的第一半导体区、第二半导体区、导电区、第一电极和第二电极位于同一半导体层且为一体的结构。
在一些示例中，所述第一子像素的发光元件的第一驱动电极与所述第一子像素的补偿子 电路的第一半导体区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述第一子像素的补偿子电路的第一半导体区的与所述第一子像素的发光元件的第一驱动电极在垂直于所述衬底基板的方向上重叠的面积与所述第一半导体区的面积的比为50％-100％。
在一些示例中，所述第一突出部与所述第一子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述显示基板还包括位于所述第一子像素的补偿子电路的控制电极远离衬底基板一侧的屏蔽电极，所述屏蔽电极与所述第一子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠；在垂直于所述衬底基板的方向上，所述第一子像素的补偿子电路的导电区与所述第一突出部的重叠面积小于所述第一子像素的补偿子电路的导电区与所述屏蔽电极的重叠面积。
在一些示例中，所述导电区为L型，包括第一分支和第二分支，所述第一分支沿所述第二方向延伸并与所述补偿子电路的第一半导体区直接连接；所述第二分支沿所述第一方向延伸并与所述补偿子电路的第二半导体区直接连接。
在一些示例中，所述补偿子电路包括补偿晶体管，所述补偿晶体管的栅极、第一极和第二极分别作为所述补偿子电路的控制电极、第一电极和第二电极；所述补偿晶体管的栅极包括第一栅极和第二栅极，所述第一半导体区在所述衬底基板上的正投影位于所述第一栅极在所述衬底基板的正投影内，所述第二半导体区在所述衬底基板的正投影位于所述第二栅极在所述衬底基板的正投影内，所述导电区与所述第一栅极、所述第二栅极在垂直于所述衬底基板的方向均不重叠。
在一些示例中，在所述第二方向上，所述第一突出部的尺寸小于所述补偿子电路的第一栅极的尺寸。
在一些示例中，所述发光元件的第一驱动电极在所述衬底基板上的正投影包括在所述第二方向上位于所述补偿子电路的第一栅极在所述衬底基板上的正投影的两侧的第一部分和第二部分，其中所述第一部分与所述补偿子电路的导电区在所述衬底基板上的正投影至少部分重叠；所述第一部分的面积小于所述发光元件的第一驱动电极在所述衬底基板上的正投影的总面积的1/10。
在一些示例中，在所述第一方向上，所述第一突出部的最大尺寸为所述发光元件的第一驱动电极的最大尺寸的1/8-1/3。
在一些示例中，在所述第二方向上，所述第一突出部的最大尺寸小于3微米。
在一些示例中，所述多个子像素还包括第二子像素，所述第二子像素的发光元件的第一驱动电极与所述第一子像素的发光元件的第一驱动电极在所述第二方向上并列设置，所述第二子像素的发光元件的第一驱动电极包括与所述第一子像素的发光元件的第一驱动电极的第一主体部的第一边平行且相对的第二边。
在一些示例中，所述第一子像素的补偿子电路的第一突出部在所述第二方向上的最大尺 寸小于所述第一边和所述第二边之间间距的1/3。
在一些示例中，所述第二子像素的补偿子电路的第一半导体区与所述第二子像素的发光元件的第一电极在垂直于所述衬底基板的方向上不重叠。
在一些示例中，所述第二子像素的发光元件的第一驱动电极与所述第二子像素的驱动子电路的控制电极在垂直于衬底基板的方向上至少部分重叠。
在一些示例中，所述第一子像素的像素电路与所述第二子像素的像素电路在所述第二方向并列设置。
在一些示例中，所述像素电路还包括第一发光控制子电路，所述第一发光控制子电路与所述驱动子电路的第一端以及第一电压端连接，且配置为响应于第一发光控制信号将来自所述第一电压端的第一电源电压施加至所述驱动子电路的第一端。
在一些示例中，所述显示基板还包括扫描线和发光控制线，其中，所述扫描线和所述发光控制线均沿所述第一方向延伸，所述扫描线与所述第一子像素的补偿子电路的控制电极电连接以提供所述扫描信号，所述发光控制线与所述第一子像素的第一发光控制子电路连接以提供所述第一发光控制信号。
在一些示例中，所述第一子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第一中心点位于所述扫描线在所述衬底基板上的正投影与所述发光控制线在所述衬底基板上的正投影之间。
在一些示例中，所述第一子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第一中心点和所述第二子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第二中心点在所述第二方向上分别位于所述扫描线在所述衬底基板上的正投影的两侧，且所述第一中心点相较于所述第二中心点更靠近所述扫描线在所述衬底基板上的正投影。
在一些示例中，所述多个子像素还包括第三子像素，所述第三子像素的发光元件的第一驱动电极包括第二主体部和第二突出部，所述第三子像素的发光元件的第一驱动电极的第二主体部包括与所述第二方向平行的第三边，所述突出部从所述第三边沿所述第一方向突出，所述第三子像素的发光元件的第一驱动电极的第二突出部与所述第三子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述多个子像素还包括第四子像素，所述第四子像素与所述第三子像素在所述第一方向上相邻且位于与所述第三子像素的发光元件的第一驱动电极的第二主体部的第三边的相对一侧，所述第三子像素的发光元件的第一驱动电极与所述第四子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠。
在一些示例中，所述显示基板还包括沿所述第一方向延伸的扫描线，所述扫描线与所述第一子像素的补偿子电路的控制电极电连接以提供所述扫描信号；所述显示基板还包括位于所述发光元件的第一驱动电极远离所述衬底基板一侧的像素界定层，所述像素界定层包括多个开口以分别定义所述多个子像素的开口区，每个子像素的发光元件的发光层的至少部分位于所述每个子像素对应的开口中；所述第一子像素、所述第三子像素和所述第四子像素沿所 述第一方向排列；在垂直于所述衬底基板的方向上，所述扫描线与所述第三子像素的开口区及所述第四子像素的开口区均重叠。
本公开至少一实施例还提供一种显示装置，包括上述任一实施例提供的显示基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为本公开至少一实施例提供的显示基板的示意图之一；
图1B为本公开至少一实施例提供的显示基板中的像素电路图之一；
图2A为本公开至少一实施例提供的显示基板中的像素电路图之二；
图2B为本公开至少一实施例提供的像素电路的时序信号图；
图3A为本公开至少一实施例提供的显示基板的示意图之二；
图3B为图3A沿剖面线I-I’的剖视图；
图4A为本公开至少一实施例提供的显示基板的示意图之三；
图4B为本公开至少一实施例提供的显示基板的示意图之四；
图5A为本公开至少一实施例提供的显示基板的示意图之六；
图5B为本公开至少一实施例提供的显示基板的示意图之七；
图5C为图3A中区域A的放大示意图；
图5D为图3A中区域A的另一种放大示意图；
图6A为本公开至少一实施例提供的显示基板的示意图之八；
图6B为本公开至少一实施例提供的显示基板的示意图之九；
图7A为本公开至少一实施例提供的显示基板的示意图之十；
图7B为本公开至少一实施例提供的显示基板的示意图之十一；
图8为本公开至少一实施例提供的显示面板的示意图；以及
图9为本公开至少一实施例提供的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、 “一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示领域，随着高分辨率产品的快速发展，对显示基板的结构设计，例如像素和信号线的排布等都提出了更高的要求。例如，相对于分辨率为4K的OLED显示装置，大尺寸、分辨率为8K的OLED显示装置由于需要设置的子像素单元的个数成倍增加，像素密度相应地成倍增大，一方面信号线的线宽也相应变小，导致信号线的自身电阻变大；另一方面信号线之间的交叠情形变多，导致信号线的寄生电容变大，这些导致信号线的阻容负载变大。相应地，阻容负载引起的信号延迟(RC delay)以及电压降(IR drop)、电压升(IR rise)等现象也会变得严重。这些现象会严重影响显示产品的显示品质。
另一方面，为了提高显示面板的显示均一性，可以对采用具有补偿功能的像素电路对发光元件进行驱动，以消除驱动晶体管的阈值电压的不均对于发光电流的影响。发明人发现，在一种带有补偿功能的像素电路中，驱动晶体管的栅极电压的稳定性对于显示基板的显示均一性有重要影响。例如，如果驱动晶体管的栅极漏电现象严重，则会造成驱动晶体管的栅极电压在阈值补偿阶段补偿不足，也即该驱动晶体管的阈值电压得不到完全补偿，从而在发光阶段的驱动电流仍然与该驱动晶体管的阈值电压Vth有关，造成显示装置的亮度的均一性下降。
发明人还发现，驱动晶体管的栅极的电压稳定性除了与该驱动晶体管自身的稳定性有关，还和与该栅极直接连接的电路(或晶体管)的稳定性有关。例如，当与该栅极直接连接的晶体管发生不稳定，则可形成电荷泄露路径，造成驱动晶体管补偿不足，从而造成显示不均。
本公开至少一实施例提供一种显示基板，包括衬底基板以及成阵列分布在衬底基板上的多个子像素。所述多个子像素每个包括像素电路和发光元件，所述像素电路用于驱动所述发光元件发光，多个像素电路沿第一方向和第二方向排列；所述多个像素电路的每个包括驱动子电路和补偿子电路；所述驱动子电路包括控制电极、第一端和第二端，且配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；所述补偿子电路包括控制电极、第一电极和第二电极，所述补偿子电路的控制电极配置为接收第二扫描信号，所述补偿子电路的第一电极和第二电极分别与所述驱动子电路的控制电极和第二端连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；所述发光元件包括依次层叠设置的第一驱动电极、发光层和第二驱动电极，所述第一驱动电极位于所述发光层靠近所述衬底基板的一侧；所述补偿子电路还包括位于所述补偿子电路的第一电极和所述第二电极之间的连 接部，所述连接部包括第一半导体区和导电区，所述第一半导体区将所述补偿子电路的第一电极和所述导电区间隔；所述第一电极、所述第二电极和所述连接部均位于所述补偿子电路的控制电极相对所述衬底基板的同一侧，所述第一半导体区在所述衬底基板的正投影位于所述控制电极在所述衬底基板的正投影内；所述多个子像素包括第一子像素，所述第一子像素的发光元件的第一驱动电极包括第一主体部和第一突出部，所述第一主体部包括与某一方向平行的第一边，所述第一突出部从所述主体部的第一边突出，所述第一突出部与所述第一子像素的补偿子电路的连接部在垂直于所述衬底基板的方向上至少部分重叠；所述第一子像素配置为发绿光。
根据人眼的生理结构，人眼对绿色子像素的敏感度远高于蓝色子像素和红色子像素。本公开至少一实施例提供的显示基板通过设置绿色子像素(第一子像素)的发光元件的第一驱动电极对该绿色子像素中与该驱动子电路的控制电极连接的补偿子电路的第一电极和第二电极之间的连接部进行遮挡，避免该补偿子电路因该连接部受到光照而发生阈值漂移等不稳定，从而提高了驱动子电路的控制电极上的电压的稳定性，进而提高了显示基板的显示均一性。
如图1A所示，该显示基板20包括显示区110和显示区110外的非显示区103。例如，非显示区103位于显示区110的外围区域。该显示基板20包括位于显示区110中的多个子像素100。例如，该多个子像素成阵列排布，例如沿第一方向D1和第二方向D2排列多个像素行和多个像素列。该第一方向D1和第二方向D2不同，例如二者正交。例如，该像素行和像素列并不一定严格地沿直线延伸，也可以沿着曲线(例如折线)延伸，该曲线总体上分别沿着第一方向D1或第二方向D2延伸。
每个子像素包括发光元件和驱动发光元件发光的像素电路。例如，多个像素电路沿第一方向D1和第二方向D2排列为阵列。例如，子像素可以按照传统的RGB的方式或者子像素共享的方式(例如pentile)构成像素单元以实现全彩显示，本公开对子像素的排列方式及其实现全彩显示的方式不作限制。
例如，如图1A所示，该显示基板20还包括位于显示区110中的多条栅线11和多条数据线12以及多个像素区，每个像素区中对应设置一个子像素100。例如，该栅线11沿第一方向D1延伸，该数据线12沿第二方向D2延伸。图1A中只是示意出了栅线11、数据线12以及子像100在显示基板中的大致的位置关系，具体可以根据实际需要进行设计。
该像素电路例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路。并且不同的实施例中，该像素电路还可以进一步包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示基板还可以包括位于非显示区中的栅极驱动子电路13和数据驱动子电路14。该栅极驱动子电路13通过栅线11与像素电路连接以提供各种扫描信号，该数据驱动子电路14通过数据线12与像素电路连接以提供数据信号。其中，图1A中示出 的栅极驱动子电路13和数据驱动子电路14，栅线11和数据线12在显示基板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
例如，显示基板20还可以包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动子电路14施加该数据信号，以及控制栅极驱动子电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。图1B示出了一种像素电路的示意图。
如图1B所示，该像素电路包括驱动子电路122和补偿子电路128。
例如，该驱动子电路122包括控制端(控制电极)122a、第一端122b和第二端122c，且配置为与发光元件120连接并且控制流经发光元件120的驱动电流。驱动子电路122的控制端122a和第一节点N1连接，驱动子电路122的第一端122b和第二节点N2连接，驱动子电路122的第二端122c和第三节点N3连接。
例如，补偿子电路128包括控制端(控制电极)128a、第一端(第一电极)128b和第二端(第二电极)128c，补偿子电路128的控制端128a配置为接收第二扫描信号Ga2，补偿子电路128的第一端128b和第二端128c分别与驱动子电路122的第二端122c和控制端122a电连接，补偿子电路128配置为响应于该第二扫描信号Ga2对该驱动子电路122进行阈值补偿。
例如，补偿子电路128还包括位于补偿子电路的第一电极128b和第二电极128c之间并将该第一电极128b和第二电极128c连接的连接部，该补偿子电路的连接部与第一子像素的发光元件的第一驱动电极的突出部在垂直于衬底基板的方向上至少部分重叠。例如，该连接部与该补偿子电路的第一电极和第二电极位于该补偿子电路的控制电极相对于衬底基板的同一侧。例如，该连接部包括至少一个半导体区。后文将结合具体的显示基板的结构对此进行详细描述。
例如，该像素电路还包括数据写入子电路126、存储子电路127、第一发光控制子电路123、第二发光控制子电路124及第一复位子电路125和第二复位子电路129。
数据写入子电路126包括控制端126a、第一端126b和第二端126c，该控制端126a配 置为接收第一扫描信号Ga1，第一端126b配置为接收数据信号Vd，第二端126c与驱动子电路122的第一端122b(也即第二节点N2)连接。该数据写入子电路126配置为响应于该第一扫描信号Ga1将该数据信号Vd写入驱动子电路122的第一端122b。例如，数据写入子电路126的第一端126b与数据线12连接以接收该数据信号Vd，控制端126a与作为扫描线的栅线11连接以接收该第一扫描信号Ga1。例如，在数据写入及补偿阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端122b(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件120发光的驱动电流。
例如，第一扫描信号Ga1可以与第二扫描信号Ga2相同。例如第一扫描信号Ga1可以与第二扫描信号Ga2连接到相同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2通过相同的扫描线传输。
在另一些示例中，第一扫描信号Ga1也可以与第二扫描信号Ga2不同。例如，第一扫描信号Ga1可以与第二扫描信号Ga2连接到不同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2分别通过不同的扫描线传输。
存储子电路127包括第一端(也称第一存储电极)127a和第二端(也称第二存储电极)127b，该存储子电路的第一端127a配置为接收第一电源电压VDD，存储子电路的第二端127b与驱动子电路的控制端122a电连接。例如，在数据写入及补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中；同时，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，存储子电路127与驱动子电路122的控制端122a及第一电压端VDD电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端122b(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号EM1将第一电压端VDD的第一电源电压施加至驱动子电路122的第一端122b。例如，如图1B所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光元件120的第一端134以及驱动子电路122的第二端122c连接，且配置为响应于第二发光控制信号使得驱动电流 可被施加至发光元件122。
例如，在发光阶段，第二发光控制子电路123响应于第二发光控制端EM2提供的第二发光控制信号EM2而开启，从而驱动子电路122可以通过第二发光控制子电路123与发光元件120电连接，从而驱动发光元件120在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路123响应于第二发光控制信号EM2而截止，从而避免有电流流过发光元件120而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动子电路122以及发光元件120进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同，例如第二发光控制信号EM2可以与第一发光控制信号EM连接到相同的信号输出端，例如，第二发光控制信号EM2可以与第一发光控制信号EM通过相同的发光控制线传输。
在另一些示例中，第二发光控制信号EM2可以与第一发光控制信号EM1不同。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别连接到不同的信号输出端。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别通过不同的发光控制线传输。
例如，第一复位子电路125与第一复位电压端Vinit1以及驱动子电路122的控制端122a(第一节点N1)连接，且配置为响应于第一复位控制信号Rst1将第一复位电压Vinit1施加至驱动子电路122的控制端122a。
例如，第二复位子电路129与第二复位电压端Vinit2以及发光元件122的第一端122b(第四节点N4)连接，且配置为响应于第二复位控制信号Rst2将第二复位电压Vinit2施加至发光元件120的第一端134。
例如，第一复位子电路125和第二复位子电路129可以分别响应于第一复位控制信号Rst1和第二复位控制信号Rst2而开启，从而可以将分别将第二复位电压Vinit2施加至第一节点N1以及将第一复位电压Vinit1施加至发光元件120的第一端134，从而可以对驱动子电路122、补偿子电路128以及发光元件120进行复位操作，消除之前的发光阶段的影响。
例如，每行子像素的第二复位控制信号Rst2可以与该行子像素的第一扫描信号Ga1为相同的信号，二者可以通过同一栅线11传输。例如，每行子像素的第一复位控制信号Rst1可以与上一行子像素的第一扫描信号Ga1，二者可以通过同一栅线11传输。
例如，发光元件120包括第一端(也称作第一电极或第一驱动电极)134和第二端(也称作第二电极或第二驱动电极)135，发光元件120的第一端134配置为与驱动子电路122的第二端122c连接，发光元件120的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图1B所示，发光元件120的第一端134可以通过第二发光控制子电路124连接至第四节点N4。本公开的实施例包括但不限于此情形。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表 示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位控制信号，符号Vinit1、Vinit2既可以表示第一复位电压端和第二复位电压端又可以表示第一复位电压和第二复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图2A为图1B所示的像素电路的一种具体实现示例的电路图。如图2A所示，该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图2A所示，驱动子电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动子电路122的控制端122a，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端122b，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端122c，和第三节点N3连接。
例如，如图2A所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，如图2A所示，补偿子电路128可以实现为第三晶体管T3。第三晶体管T3的栅极、第一极和第二极分别作为该补偿子电路的控制电极128a、第一电极128b和第二电极128c。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第三晶体管T3的第二极和驱动子电路122的控制端122a(第一节点N1)连接。例如，如图2A所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极Ca和第二电容电极Cb，该第一电容电极Ca和第一电压端VDD耦接，例如电连接，该第二电容电极Cb和驱动子电路122的控制端122a耦接，例如电连接。
例如，如图2A所示，第一发光控制子电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，发光元件120具体实现为发光二极管(LED)，例如可以是有机发光二极管(OLED)、量子点发光二极管(QLED)或者无机发光二极管，例如可以是微型发光二极管(Micro LED)或者微型OLED。例如，发光元件120可以为顶发射结构、底发射结构或双面发射结。该发光元件120可以发红光、绿光、蓝光或白光等。本公开的实施例对发光元件的具体结构不作限制。
例如，发光元件120的第一电极134(例如为阳极)和第四节点N4连接配置为通过第 二发光控制子电路124连接到驱动子电路122的第二端122c，发光元件120的第二电极135(例如为阴极)配置为和第二电压端VSS连接以接收第二电源电压VSS，从驱动子电路122的第二端122c流入发光元件120的电路决定发光元件的亮度。例如第二电压端可以接地，即VSS可以为0V。例如，第二电压电源电压VSS可以为负电压。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第五晶体管T5的第二极和发光元件120的第一端134(第四节点N4)连接。
例如，第一复位子电路125可以实现为第六晶体管T6，第二复位子电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位控制信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位控制信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。例如，如图1B所示，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本公开实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系即可。
以下结合图2B所示的信号时序图，对图2A所示的像素电路的工作原理进行说明。如图2B所示，每一帧图像的显示过程包括三个阶段，分别为初始化阶段1、数据写入及补偿阶段2、和发光阶段3。
如图2B所示，在本实施例中，第一扫描信号Ga1和第二扫描信号Ga2采用同一信号，第一发光控制信号EM1和第二发光控制信号EM2采用同一信号；且第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即第二复位控制信号Rst2、第一扫描信号Ga1/第二扫描信号Ga2可以采用同一信号；本行子像素的第一复位信号Rst1与上一行子像素的第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即采用同一信号。然而， 这并不作为对本公开的限制，在其它实施例中，可以采用不同的信号分别作为第一扫描信号Ga1、第二扫描信号Ga2、第一复位控制信号Rst1、第二复位控制信号Rst2，采用不同的信号分别作为第一发光控制信号EM1和第二发光控制信号EM2。
在初始化阶段1，输入第一复位控制信号Rst1以开启第六晶体管T6，将第一复位电压Vinit1施加至第一晶体管T1的栅极，从而对该第一节点N1复位。
在数据写入及补偿阶段2，输入第一扫描信号Ga1、第二扫描信号Ga2以及数据信号Vd，第二晶体管T2和第三晶体管T3开启，数据信号Vd由第二晶体管T2写入第二节点N2，并经过第一晶体管T1和第三晶体管T3对第一节点N1充电，直至第一节点N1的电位变化至Vd+Vth时第一晶体管T1截止，其中Vth为第一晶体管T1的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在数据写入极补偿阶段2，还可以输入第二复位控制信号Rst2以开启第七晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Rst1和第二复位控制信号Rst2可以相同。本公开实施例对此不作限制。
在发光阶段3，输入第一发光控制信号EM1和第二发光控制信号EM2以开启第四晶体管T4、第五晶体管T5和第一晶体管T1，第五晶体管T5将驱动电流施加至OLED以使其发光。流经OLED的驱动电流I的值可以根据下述公式得出：
I＝K(VGS-Vth)2＝K[(Vdata+Vth-VDD)-Vth]2＝K(Vdata-VDD)2，其中，K为第一晶体管的导电系数。
在上述公式中，Vth表示第一晶体管T1的阈值电压，VGS表示第一晶体管T1的栅极和源极(这里为第一极)之间的电压，K为与第一晶体管T1本身相关的一常数值。从上述I的计算公式可以看出，流经OLED的驱动电流I不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I的影响，从而可以改善采用其的显示装置的显示效果。
以下以图2A所示像素电路为例、并结合图3A-3B、图4A-4B、图5A-图5D、图6A-图6B、图7A-7B对本公开至少一实施例提供的显示基板的结构进行示例性说明。
图3A为本公开至少一个实施例提供的显示基板20的示意图,图3B为图5A沿剖面线I-I’的剖视图。需要说明的是，为了清楚起见，图3B省略了一些在剖面线处不存在直接电连接关系的结构。
如图3A所示，该显示基板20包括衬底基板101，多个子像素100位于该衬底基板101上。多个子像素100的像素电路布置为像素电路阵列，该像素电路阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。在一些实施例中， 所述第一方向D1也可以为行方向，第二方向D2也可以为列方向。在一些实施例中，各子像素的像素电路除与发光元件的连接结构外，可以具有完全相同的结构，即像素电路在行和列方向重复排列，不同子像素的与发光元件的连接结构根据各个子像素的发光结构的电极的布置形状和位置可以不同。在一些实施例中，不同颜色子像素的像素电路的大致框架例如各个信号线的形状和位置基本相同，各个晶体管的相对位置关系也基本相同，但对于有些信号线或连接线的宽度、形状，或者某些晶体管的例如沟道尺寸、形状，或者用于与不同子像素的发光元件连接的连接线或者过孔位置等可以有不同，可以根据各个布局结构以及子像素排列进行调整。
图3A中示例性地示出了一行子像素中直接相邻的四个子像素(即第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d)，本公开的实施例不限于此布局。
例如，该第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d分别配置为发绿光、绿光、蓝光和红光。该第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d构成该显示基板20的一个重复单元。结合图3A-3B可知，半导体层102、第一绝缘层301、第一导电层201、第二绝缘层302、第二导电层202、第三绝缘层303、第三导电层203、第四绝缘层304、第四导电层204依次设置于衬底基板101上，从而形成如图3A所示的显示基板的结构。
图4A对应于图3A示意出了该四个子像素100中晶体管T1-T7的半导体层102和第一导电层(栅极层)201，图5A示出了第二导电层202，图5B在图4A的基础上示出了该第二导电层202；图6A示出了第三导电层203，图6B在图5B的基础上示出了该第三导电层203；图7A示出了第四导电层204，图7B示出了半导体层102、第一导电层201和第四导电层204。
为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和沟道区，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，如图4A所示，该第一导电层201包括每个晶体管的栅极以及一些扫描线和控制线。图4A中用大虚线框示出了每个子像素100的像素电路所在的区域，用小虚线框示出了一个子像素100中第一到第七晶体管T1-T7的栅极T1g-T7g。
该半导体层102包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图3A所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层20为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔。
例如，如图4A所示，该第一导电层201包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，该显示基板20采用自对准工艺，利用第一导电层201作为掩膜对该半导体层102进 行导体化处理(例如掺杂处理)，使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。
图4B示出了图3A中第一子像素100a的区域A的放大示意图。如图4B所示，该第一子像素100a的发光元件的第一驱动电极134a包括第一主体部141和第一突出部142，图4B中用虚线示出了该第一主体部141和第一突出部142的分界线。该第一主体部包括与某一方向平行的第一边141a，例如该第一边141a为平行于该第一方向D1的直边。该第一突出部142从该第一主体部的141第一边141a突出。
如图4A-4B所示，该第一子像素100a的补偿子电路还包括位于其第一电极(也即第三晶体管T3的第一极T3s)与其第二电极(也即第三晶体管T3的第二极T3d)之间并将该第一电极和该第二电极连接的连接部128d，该第一突出部142与该第一子像素100a的补偿子电路的连接部128d在垂直于衬底基板101的方向上至少部分重叠。
例如，如图4B所示，该连接部128d包括第一半导体区T3a1、导电区T3c和第二半导体区T3a2，该第一半导体区T3a1将该补偿子电路的第一电极和该导电区间隔T3c，该第二半导体区T3a2将该补偿子电路的第二电极与该导电区T3a2间隔，也即也即该第三晶体管T3的第一极T3s、第一半导体区T3a1、导电区T3c、第二半导体区T3a2和第二极T3d依次连接。
例如，如图4A-4B所示，该补偿子电路的连接部、第一电极和第二电极位于同一半导体层102且为一体的结构，也即该第三晶体管T3的第一极T3s、第一半导体区T3a1、导电区T3c、第二半导体区T3a2和第二极T3d为位于同一半导体层102中的一体的结构，例如均包括多晶硅材料。
例如，第三晶体管T3和第六晶体管T6采用双栅结构，这样可以提高晶体管的栅控能力，降低漏电流。由于第三晶体管T3和第六晶体管T6都是与第一晶体管T1(也即驱动晶体管)的栅极直接连接的晶体管，因此，该第三晶体管T3和第六晶体管T6的稳定性直接影响着第一晶体管T1的栅极(N1节点)电压的稳定性。采用双栅结构提高第三晶体管T3和第六晶体管T6的栅控能力，有助于降低晶体管的漏电流从而有助于保持N1节点的电压，从而在补偿阶段，第一晶体管T1的阈值电压有助于得到充分补偿，进而提高发光阶段显示基板的显示均一性。
例如，如图4A-4B和图3A-3B所示，第三晶体管T3的栅极包括第一栅极T3g1和第二栅极T3g2。该第一半导体区T3a1、第二半导体区T3a2、导电区T3c、第一极T3s和第二极T3d位于同一半导体层102中并一体成型，通过选择性的导体化处理(例如离子注入)而具有不同的导电性能。
该第一半导体区和第二半导体区分别被第一栅极T3g1和第二栅极T3g2所遮挡因此未在图4A中示出；也即，该第一半导体区T3a1在衬底基板101上的正投影位于该第一栅极T3g1在衬底基板101的正投影内，该第二半导体区T3a2在衬底基板101上的正投影位于该第二 栅极T3g2在该衬底基板101的正投影内。该导电区T3c与该第一栅极T3g1、第二栅极T3g2在垂直于衬底基板的方向均不重叠。
例如，如图4B所示，对于该第一子像素100a，其第三晶体管T3的第一半导体区T3a1以及该第一栅极T3g1的至少部分均与其发光元件的第一电极在垂直于衬底基板101的方向上至少部分重叠，也即在垂直于衬底基板101的方向上，该第一栅极T3g1的与该第三晶体管T3的第一半导体区T3a1重叠的至少部分被该发光元件的第一电极遮挡。后文将在介绍发光元件的第一电极所在的第四导电层时对此进行详细说明。
发明人发现，当光照射到晶体管的栅极上时，晶体管的阈值电压会发生偏移。本公开实施例通过设置该第一子像素的发光元件的第一电极遮挡住该第三晶体管(补偿晶体管)的栅极的至少部分，提高了该补偿晶体管的稳定性，从而提高了显示均一性。
例如，如图4B所示，该第一子像素的补偿子电路的第一半导体区T3a1的与该第一子像素的发光元件120的第一电极134在垂直于衬底基板101的方向上重叠的面积与该第一半导体区T3a1的面积的比为50％-100％；也即，该发光元件120的第一电极134可以完全覆盖该第一半导体区T3a1。
例如，如图4B所示，该发光元件120的第一电极134的第一突出部142与该补偿子电路的导电区T3c和第一半导体区T3a1在垂直于衬底基板101的方向上分别至少部分重叠。
在另一些示例中，在垂直于衬底基板101的方向上，该发光元件120的第一电极134的第一突出部142也可以仅与该第一半导体区T3a1重叠，而与该导电区T3c不重叠。
在另一些示例中，该发光元件120的第一电极134的第一突出部142也可以与该补偿子电路的第一半导体区T3a1在垂直于衬底基板101的方向上不重叠；在这种情形，例如，该第一电极134的主体部141完全覆盖该补偿子电路的第一半导体区T3a1。例如，该第一电极134的主体部141的第一边141a与该第一栅极T3g1临近该导电区T3c的侧边在衬底基板101上的投影重合。
例如，在该第二方向D2上，该第一突出部142的最大y1尺寸小于该补偿子电路的第一栅极T3g1的平均尺寸。
例如，在该第二方向D2上，该第一突出部142的最大y1尺寸小于3微米，例如小于2微米，例如在1微米到2微米之间。
例如，该第一突出部142位于该第一栅极T3g1与该第二栅极T3g2之间，且与该第二栅极T3g2在垂直于衬底基板的方向上不重叠。
例如，如图4B所示，该发光元件的第一电极134在衬底基板101上的正投影被该第一栅极T3g1在衬底基板101上的正投影划分为两个部分，也即该发光元件的第一电极134在衬底基板101上的正投影包括在第二方向D2上位于该第一栅极T3g1在该衬底基板101上的正投影的两侧的第一部分和第二部分，其中该第一部分与该补偿子电路的导电区T3c在该衬底基板上的正投影至少部分重叠，该第一部分的面积S1小于该发光元件的第一电极在衬底基板101上的正投影S2的总面积的1/10，例如，S1小于S2的1/20。例如，当该第一突 出部142与该导电区T3c不重叠时，该第一部分的面积S1可以是0。
例如，如图4B所示，在第一方向D1上，该第一突出部142的最大尺寸x1为该发光元件的第一电极134的最大尺寸x2的1/8-1/3，例如为1/6-1/4。例如，在第一方向D1上，该第一突出部142的最大尺寸x1为5微米到10微米之间，例如为6微米。
例如，如图4A-4B所示，导电区T3c为L型，包括第一分支T3c1和第二分支T3c2，该第一分支T3c1沿第二方向D2延伸并与该补偿子电路的第一半导体区T3a1直接连接；该第二分支T3c2沿第一方向D1延伸并与该补偿子电路的第二电极，也即第三晶体管T3的第二半导体区T3a2直接连接。
例如，该第一导电层104还包括彼此绝缘的多条栅线11，该栅线11例如包括多条扫描线210、多条复位控制线220和多条发光控制线230。这里栅线11是指与晶体管的栅极直接连接以提供扫描信号或控制信号的信号线。例如，每行子像素分别对应连接一条扫描线210、两条复位控制线220和一条发光控制线230。
扫描线210与对应一行子像素中的第二晶体管T2的栅极电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线220与对应一行子像素中的第六晶体管T6的栅极电连接以提供第一复位控制信号Rst1，发光控制线230与对应一行子像素中的第四晶体管T4的的栅极电连接以提供第一发光控制信号EM1。
例如，如图4A所示，该扫描线210还与第三晶体管T3的栅极电连接以提供第二扫描信号Ga2，即第一扫描信号Ga1和第二扫描信号Ga2可以为同一信号；该发光控制线230还与第五晶体管T5的栅极电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，例如该第一栅极T3g1沿第一方向D1延伸，为扫描线210的一部分。该第二栅极T3g2沿第二方向D2延伸，为扫描线210沿第二方向D2延伸的延伸部。
例如，如图4A所示，本行像素电路的第七晶体管T7的栅极与下一行像素电路(即按照扫描线的扫描顺序，在本行扫描线之后顺序开启的扫描线所在的像素电路行)所对应的复位控制线220电连接以接收第二复位控制信号Rst2。
例如，如图5A-5B所示，该第二导电层202包括第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板101的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括开口222，该开口222暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。例如，位于同一像素行的子像素的第一电容电极Ca彼此连接为一体的结构。
例如，该第二导电层202还可以包括沿第一方向D1延伸的多条复位电压线240，该多条复位电压线240与多行子像素一一对应连接。该复位电压线240与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，如图5B所示，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应 的的复位电压线240电连接以接收第二复位电压Vinit2。后文将结合图6B对此进行详细描述。
例如，如图5B所示，该第二导电层202还可以包括屏蔽电极221。例如，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。由于该第二晶体管T2的第一极T2s配置为接收数据信号Vd，而该数据信号Vd决定了该子像素的显示灰阶，因此该屏蔽电极221提高了数据信号的稳定性，从而提高了显示性能。
例如，结合参考图5B和图4A，该屏蔽电极221还与第六晶体管T6的第二极T6d在垂直于衬底基板101的方向上至少部分重叠，以提高该第二极T6d中信号的稳定性，从而提高第六晶体管T6的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，结合参照图5B与图4A，该屏蔽电极221还延伸至相邻的子像素并与相邻的子像素中的第三晶体管T3的导电区T3c在垂直于衬底基板101的方向上至少部分重叠，以提高该导电区T3c中信号的稳定性，从而提高第三晶体管T3的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，可以参考图4B，在垂直于衬底基板101的方向上，该第一子像素的补偿子电路的导电区T3c与该第一突出部142的重叠面积小于该第一子像素的补偿子电路的导电区T3c与该屏蔽电极221的重叠面积。
例如，该屏蔽电极221和与之正对(重叠)的第二晶体管T2的第一极T2s或第三晶体管T3的导电区T3c或第六晶体管T6的第二极T6d形成稳定电容。该屏蔽电极221配置为加载固定电压，由于电容两端的压差不能突变，因此提高了第二晶体管T2的第一极T2s、第三晶体管T3的导电区T3c及第六晶体管T6的第二极T6d上电压的稳定性。例如，该屏蔽电极221与第三导电层中的电源线250电连接以加载第一电源电压VDD。
例如，如图5A-5B所示，该屏蔽电极221为L形，包括延伸方向不同的第一分支221a和第二分支221b。该第一分支221a与第六晶体管T6的第二极T6d在垂直于衬底基板101的方向上至少部分重叠；该第二分支221b分别与第二晶体管T2的第一极T2s以及相邻的子像素中的第三晶体管T3的导电区T3c在垂直于衬底基板101的方向上至少部分重叠。例如，该第一分支221a沿第二方向D2延伸，该第二分支221b沿第一方向D1延伸；也即在垂直于衬底基板的方向上与该第一子像素100a的补偿子电路的导电区T3c重叠的屏蔽电极121为与该第一子像素100a在第一方向D1上相邻且靠近其补偿子电路一侧的子像素中的屏蔽电极。
图5C示出了图3A中区域A的放大示意图的一种示例，如图5C所示，在垂直于衬底基板的方向上，屏蔽电极221与第三晶体管T3的第一栅极T3g1和第二栅极T3g2均不重叠，从而避免产生寄生电容对栅极信号造成影响。
例如，如图5C所示，在垂直于衬底基板的方向上，屏蔽电极221与该第一子像素100a的发光元件134至少部分重叠，在第二方向D2上二者重叠的平均尺寸d1为0.1微米-1微米， 例如为0.1微米-0.5微米。
图5D示出了图3A中区域A的放大示意图的另一个示例，如图5D所示，在垂直于衬底基板的方向上，屏蔽电极221与该第一子像素100a的发光元件134不重叠并存在间隙，该间隙在第二方向D2上的平均尺寸d2为0.1微米-1微米，例如为0.1微米-0.5微米。
例如，如图6A-6B所示，该第三导电层203包括沿第二方向D2延伸的多条电源线250。例如，该多条电源线250与多列子像素一一对应电连接以提供第一电源电压VDD。该电源线250通过过孔342与所对应的一列子像素中的第一电容电极Ca电连接，通过过孔343与第四晶体管T4的第一极电连接。例如，该电源线250还通过过孔341与屏蔽电极221电连接，从而使得屏蔽电极221具有固定电位，提高了该屏蔽电极的屏蔽能力。例如，该过孔342和过孔341均贯穿第三绝缘层303，该过孔343贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，该第三导电层203还包括沿第二方向D2延伸的多条数据线12。例如，该多条数据线12与多列子像素一一对应电连接以提供数据信号。例如，该数据线12与所对应的的一列子像素中的第二晶体管T2的第一极T2s通过过孔346电连接以提供该数据信号。例如，该过孔346贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，结合图3A-3B、图6A-6B所示，该第三导电层203还包括第一连接电极231，该第一连接电极231的一端通过第一电容电极Ca中的开口222以及绝缘层中的过孔344与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔345与该第三晶体管T3的第一极电连接，从而将该第二电容电极Cb与该第三晶体管T3的第一极T3s电连接。例如，该过孔344贯穿第二绝缘层302和第三绝缘层303。例如，该过孔345贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，结合图3A-3B、图6A-6B所示，该第三导电层203还包括第二连接电极232，该第二连接电极233通过过孔349与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接。例如，该过孔349贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。后文将对此详细说明。
例如，如图6A-6B所示，该第三导电层203还包括第三连接电极233，该第三连接电极233的一端通过过孔348与复位电压线电连接，另一端通过过孔347与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔348贯穿第三绝缘层303。例如该过孔404贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，如图6B所示，上一行子像素中的第七晶体管T7的第一极与本行子像素所对应的的复位电压线240电连接以接收第二复位电压Vinit2，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应的的复位电压线240电连接以接收第二复位电压Vinit2。
图7A示出了第四导电层204的示意图；为了便于说明本公开实施例中发光元件的第一电极与各晶体管的栅极、沟道区的相对位置关系，图7B示出了半导体层102、第一导电层 201和第四导电层204。
结合图3A-3B和图7A-7B所示，第四导电层204包括发光元件的第一电极134，例如包括第一子像素100a的第一电极134a、第二子像素100b的第一电极134b、第三子像素100c的第一电极134c和第四子像素100d的第一电极134d。各子像素的第一电极134通过过孔340与该子像素中的第二连接电极232电连接，从而通过该第二连接电极233与第五晶体管T5的第二极T5d电连接。该过孔340例如贯穿第四绝缘层304。
例如，参考图3A-3B，该显示基板20还可以包括位于发光元件的第一电极上的像素界定层305。像素界定层305中形成开口暴露出第一电极134的至少部分从而界定显示基板各个子像素的开口区(即有效发光区)600。发光元件120的发光层136至少形成于该开口内(发光层136还可以覆盖部分的像素界定层远离发光元件的第一电极一侧的表面)，第二电极135形成于发光层136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如第一电极134为发光元件的阳极，第二电极135为发光元件的阴极。
图7A在各子像素的发光元件的第一电极上示出了该开口区600的位置，并示出了像素电极的过孔340相对于各第一电极134的位置。如图7A所示，该过孔340与开口区600在衬底基板101上的正投影不重叠，也即该过孔340在衬底基板101上的正投影位于开口区600之外。由于在垂直于衬底基板101的方向上，过孔340距离发光层136较近，这种设置避免了过孔340影响开口区内的发光层的平整度从而影响发光品质。
例如，如图3B所示，过孔349和过孔340在垂直于衬底基板101的方向上部分重叠而不完全重叠或者完全不交叠，避免在垂直基板方向上，过孔堆叠导致过孔所在位置容易产生连接不良、断线或不平坦。在另一些示例中，过孔349和过孔340在垂直于衬底基板101的方向上不重叠。在一些示例中，贯穿某层的过孔可以形成为在该膜层一个表面的尺寸大于相对另一表面上到尺寸，过孔的范围可以为在对应膜层中的形成的最大尺寸。
结合图3B和图7B所示，第一子像素100a的补偿子电路(也即第三晶体管T3)的第一半导体区T3a1与该第一子像素的发光元件的第一电极134a在垂直于衬底基板101的方向上至少部分重叠。通过设置该第一电极134a对该第一半导体区T3a1在垂直于衬底基板101的方向上进行遮挡，使得该第一半导体区T3a1上方的第一栅极T3g1的至少部分得以被该第一电极134a遮挡，避免该第三晶体管T3因该第一半导体区及第一栅极受到光照而发生阈值漂移等不稳定，从而提高了驱动子电路的控制电极上的电压的稳定性，进而提高了显示基板的显示均一性。
例如，该第一半导体区T3a1的与该第一电极134a在垂直于衬底基板101的方向上重叠的面积与该第一半导体区T3a1的总面积的占比范围为20％-100％，例如为50％-100％。
例如，如图3B和7B所示，在垂直于衬底基板101的方向上，该第一子像素的发光元件的第一电极134a还与该第一子像素的第三晶体管T3的导电区T3c至少部分重叠，从而尽量增大该第三晶体管T3的第一栅极T3g1被该第一电极134a所遮挡的面积。例如，该第一 栅极T3g1在衬底基板101上的正投影位于该第一电极134a在衬底基板101的正投影内。例如，这里第一栅极T3g1是指扫描线210的与该第一半导体区T3a1在垂直于衬底基板101的方向上重合的部分。
例如，如图7B所示，在第二方向D2上，该第一子像素100a的第一突出部142在衬底基板101上的正投影与该第一子像素100a对应的过孔340分别位于该第一子像素100a的驱动子电路的控制电极T1g在衬底基板101上的正投影的两侧。
例如，如图7A-7B所示，该第一子像素的发光元件的第一电极134a包括第一主体部141和第一突出部142，该第一主体部141包括与第一方向D1平行的第一边141a，该第一突出部142从该第一边沿第二方向D2突出或延伸。例如，该第一突出部142与第三晶体管T3的导电区T3c在垂直于衬底基板的方向上至少部分重叠；也即该第一突出部142对应与该导电区T3c设置。
例如，参考图7A，第二子像素100b的发光元件的第一电极134b与第一子像素100a的发光元件的第一电极134a在第二方向D2上并列设置，该第二子像素的发光元件的第一电极134b包括与该第一边141a大致平行且相对的第二边141b。其中，第一边141a为第一电极134a靠近第二子像素的发光元件的第一电极134b的边中近似直线的部分，即突起部的部分与第一电极134b的第二边141b是不平行的。
例如，结合参考图4B和图7A，该第一子像素的补偿子电路的第一突出部142在第二方向D2上的最大尺寸y1小于该第一边141a和该第二边141b之间间距y2的1/3，以留有足够的工艺余量从而确保该第一子像素的第一电极与该第二子像素的第一电极彼此绝缘。
该第一子像素100a的像素电路与该第二子像素100b的像素电路在第二方向D2并列设置，也即位于不同行。例如，第一子像素100a的开口区600和第二子像素100b的开口区600相对于沿第一方向D1的对称轴大致对称。
例如，如图7B所示，该第二子像素100b的补偿子电路的第一半导体区T3a1与第二子像素100b的发光元件的第一电极134b在垂直于衬底基板101的方向上不重叠。例如，如图7B所示，该第二子像素100b的发光元件的第一电极134b延伸至与该第二子像素的驱动子电路的控制电极T1g在垂直于衬底基板的方向上至少部分重叠，并与该第二子像素连接的扫描线210在垂直于衬底基板的方向上不重叠。
例如，如图7B所示，第一子像素100a的发光元件的第一电极134a在衬底基板上的正投影的第一中心点H1位于与该第一子像素100a连接的扫描线210在衬底基板上的正投影和与该第一子像素100a连接的发光控制线230在衬底基板上的正投影之间。
例如，如图7B所示，第一子像素100a的发光元件的第一电极134a在衬底基板上的正投影的第一中心点H1和第二子像素100b的发光元件的第一电极134b在衬底基板上的正投影的第二中心点H2在第二方向D2上分别位于与该第一子像素连接的扫描线210在衬底基板上的正投影的两侧，且该第一中心点H1相较于该第二中心点H2更靠近该扫描线210在衬底基板上的正投影。
这里的第一中心点H1是指第一子像素100a的发光元件的第一电极134a在衬底基板上的正投影的几何中心，第二中心点H2是指第二子像素100b的发光元件的第一电极134b在衬底基板上的正投影的几何中心。
如图7B所示，由于这里的第一子像素100a与第二子像素100b并不位于同一像素行，而是位于相邻的的像素行，因此与该第一子像素100a连接的扫描线210不与该第二子像素100b连接。
例如，如图3A所示，在垂直于衬底基板的方向上，与该第一子像素100a连接的扫描线210和与该第一子像素同行的第三子像素100c的开口区600及第四子像素100d的开口区600均重叠。
由于设备或工艺能力有限，需要在走线或过孔之间预留一定的工艺余量(margin)以保证工艺的可靠性，例如，相邻的走线或电极之间的间距需要大于或等于满足该显示基板20制作工艺中的设计规则(Design Rule)的最小尺寸从而可以保证工艺良率。该设计规则与设备的工艺能力、制作工艺、过孔的深度及材料层的厚度等相关。
例如，该第一边141a与该第二边141b之间的距离为满足该显示基板20的设计规则(Design Rule)的最小尺寸从而有效提高像素密度。
由此，将突起142选择性地对应与该导电区T3c设置，可以尽量保证工艺余量而提高工艺良率。例如，如图7B所示，该突起142与该第一子像素的第三晶体管的第二半导体区T3a2在垂直于衬底基板的方向上不重叠。
例如，如图7B所示，该第三晶体管T3的第二栅极T3g2从扫描线210的平行于第一方向D12的第一侧边210a沿第二方向D2延伸。例如，该第一电极134b的第一边141a与扫描线210的该第一侧边210a在垂直于衬底基板101的方向上重合，该突起142与该第二栅极T3g2位于该扫描线210的同一侧，且在第二方向D2上，突起142的尺寸小于第二栅极T3g2的尺寸。例如，在第二方向D2上，该突起的134的最大尺寸为该第一边141a与该第二边141b之间的距离的1/5-1/3；该突起的134的最大尺寸为该第一电极134a的最大尺寸的1/20-1/10。
例如，结合图7A-7B，第三子像素100c的发光元件的第一电极134c包括第二主体部143和第二突出部144，该主体部143包括与第二方向D2平行的第三边143a，该第二突出部144从该第三边143a沿第一方向D1突出，该第二突出部144与第三子像素100c的补偿子电路(也即第三晶体管T3)的导电区T3c在垂直于衬底基板101的方向上至少部分重叠。
例如，如图7B所示，该第一子像素100a的第一突出部142与相邻的第三子像素100c的第二突出部144在第一方向D1上至少部分重叠，也即存在一条沿第一方向D1延伸的虚拟直线L1同时与该第一突出部142和该第二突出部144交叠。例如，该虚拟直线L1在垂直于衬底基板的方向上与该第一子像素的补偿子电路的第二栅极T3g2重叠。
例如，该第三子像素100c的发光元件的第一电极134还与第二子像素100b的补偿子电路(也即第三晶体管T3)的导电区T3c在垂直于衬底基板101的方向上至少部分重叠。该 第二子像素100b与第三子像素100c在第一方向D1上相邻。如图7B所示，在第一方向D1上，该第一子像素100a和该第二子像素100b分别位于第三子像素100c的相对两侧。例如，如图3A所示，第一子像素100a的开口区600在衬底基板101上的正投影位于两条电源线250(分别为第一电源线和第二电源线)之间，且与该第一电源线和第二电源线在垂直于衬底基板101的方向上均不重叠或仅部分重叠。这种设置避免了电源线250影响第一子像素的开口区内的发光层的平整度从而影响发光品质(例如引起色偏)。
例如，如图3A所示，第三子像素100c的开口区600沿第二方向D2的中心线(穿过在第一方向D2上的最大尺寸处的中点)在衬底基板101上的正投影位于电源线250在衬底基板101的上的正投影内。这种设置使得该电源线相对于该开口区600的位置相对居中，因此避免了该开口区600内的发光层因该电源线250的设置而朝向一方倾斜导致的色偏等问题。
例如，如图3A和7B所示，第二子像素100b的发光元件的第一电极134b与第二子像素的驱动子电路的控制电极(也即第一晶体管T1的栅极T1g)在垂直于衬底基板的方向上至少部分重叠。例如，该第一电极134b包括主体部145、连接部146和延伸部147，主体部145主要用于驱动发光层136发光，连接部146主要用于与相应的像素电路进行连接。例如，主体部145在衬底基板101上的正投影覆盖开口区600在衬底基板101上的正投影。连接部146在衬底基板101上的正投影覆盖第二连接电极232在衬底基板101上的正投影。该延伸部147与第一晶体管T1的栅极T1g在垂直于衬底基板的方向上至少部分重叠。例如，在第二方向D2上，主体部145、连接部146和延伸部147依次布置，延伸部147相较于连接部146更远离主体部145。
在本公开实施例中，有意地将该第二子像素100b的发光元件的第一电极134b延长以与第一晶体管T1的栅极T1g形成寄生电容，这是由于第一子像素、第三子像素和第四子像素的发光元件的第一电极均与各自对应的第一晶体管T1的栅极T1g在垂直于衬底基板的方向上至少部分重叠。因此，通过对第二子像素进行类似地设置，可以提高显示基板的均一性。
例如，如图7B所示，在第一方向D1上，主体部145、连接部146和延伸部147的平均尺寸依次减小。例如，延伸部147位于在第一方向上相邻的第三子像素的发光元件的第一电极134c和第四子像素的发光元件的第一电极134d之间，为了保证工艺余量，延伸部147在第一方向D1上的尺寸有所缩减以与第一电极134c及134d有效绝缘。例如，在第一方向D1上，延伸部147与分别位于两侧的第三子像素的发光元件的第一电极134c和第四子像素的发光元件的第一电极134d之间的间隙大致相等。在一些示例中，该间隙小于4微米。在一些示例中，该间隙小于3.5微米。在一些示例中，该间隙小于3微米。在一些示例中，该间隙小于两个绿色子像素的发光元件的第一电极之间的间隙。
例如，为了提高显示分辨率，可以改变常规的红、绿、蓝三色子像素定义一个发出全彩光的像素单元的模式，用相对较少的子像素数，模拟实现相同的像素分辨率表现能力，从而降低制作工艺的难度和制作成本。例如，可以利用人眼对不同色彩子像素的分辨率的差异，通过不同的像素间共享某些位置分辨率不敏感颜色的子像素。由于人眼对绿色最为敏感，例 如，可以使得每个红色子像素和每个蓝色子像素为至少两个像素单元共用，并使得每个像素单元独立拥有一个绿色子像素。由于每个像素中的蓝色子像素和红色子像素是被相邻的像素单元共享的，因而本发明实施例中的像素并不是严格意义上的像素，可以称之为虚拟像素单元。
例如，第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d构成该显示基板20的一个重复单元。
例如，该第一子像素100a和第二子像素100b的发光元件均为绿色子像素。例如，第三子像素100c可以为蓝色子像素，第四子像素100d可以为红色子像素。
例如，如图3A所示，在第一方向上，第三子像素100c和第四子像素100d的开口区交替排列；第一子像素100a和第二子像素100b的开口区600在第二方向上成对并列设置，且在第一方向上位于第三子像素100c的开口区600和第四子像素100d的开口区600之间。
例如，每个重复单元中的四个子像素可以形成两个虚拟像素，重复单元中的第三子像素100c和第四子像素100d分别被所述两个虚拟像素共用。例如，如图3A所示，第四子像素100d与位于其右侧并与其相邻的第一子像素100a构成一个虚拟像素，并借用相邻(右侧)虚拟像素中的第三子像素100c形成像素单元；第三子像素100c和位于其右侧并与其相邻的第二子像素100b构成一个虚拟像素，并借用相邻(右侧未示出)的第四子像素100d形成像素单元。多个重复单元中的子像素形成像素阵列，在像素阵列的行方向(如第一方向)上，子像素密度是虚拟像素密度的1.5倍，在像素阵列的列方向(如第二方向)上，子像素密度是虚拟像素密度的1.5倍。相较于传统的RGB排列，本公开实施例提供的像素排列方式有效提高了像素密度。
由于每个像素单元独立拥有一个绿色子像素，因此绿色子像素的密度最高，绿色子像素的开口区会设置得相对较小以实现高密度的像素分布。在这种情形，绿色子像素的像素电极的面积也会相对较小。
本公开实施例在有限的面积内，将绿色子像素的发光元件的第一电极(也即像素电极)设置为对该补偿子电路的沟道区及对应该沟道区的控制电极进行遮挡，在实现高分辨率的显示的同时，提高了该补偿子电路的稳定性，进而提高了显示基板的显示均一性。
例如，衬底基板101可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层102的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该第一到第四导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材 料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该发光元件120为顶发射结构，第一电极具134有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，第一绝缘层301、第二绝缘层302、第三绝缘层303例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，第四绝缘层304和像素界定层305分别为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层304为平坦化层。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板20。例如，该显示面板为OLED显示面板，相应地其包括的显示基板20为OLED显示基板。如图8所示，例如，该显示面板30还包括设置于显示基板20上的封装层801和盖板802，该封装层801配置为对显示基板20上的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动子电路的渗透而造成对器件的损坏。例如，封装层801包括有机薄膜或者包括无机薄膜、有机薄膜、无机薄膜交替层叠的结构。例如，该封装层801与显示基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板802例如为玻璃盖板或柔性盖板。例如，盖板802和封装层801可以为一体的结构。
本公开的至少一实施例还提供一种显示装置40，如图9所示，该显示装置40包括上述任一显示基板20或显示面板30，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (26)

  1. 一种显示基板，包括：
    衬底基板；
    多个子像素，成阵列分布于所述衬底基板上；
    其中，所述多个子像素每个包括像素电路和发光元件，所述像素电路用于驱动所述发光元件发光，所述多个子像素的像素电路沿第一方向和第二方向排列，所述第一方向和所述第二方向不同；
    所述像素电路包括驱动子电路和补偿子电路；
    所述驱动子电路包括控制电极、第一端和第二端，且配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；
    所述补偿子电路包括控制电极、第一电极和第二电极，所述补偿子电路的控制电极配置为接收扫描信号，所述补偿子电路的第一电极和第二电极分别与所述驱动子电路的第二端和控制电极连接，所述补偿子电路配置为响应于所述扫描信号对所述驱动子电路进行阈值补偿；
    所述发光元件包括依次层叠设置的第一驱动电极、发光层和第二驱动电极，所述发光元件的第一驱动电极位于所述发光层靠近所述衬底基板的一侧；
    所述补偿子电路还包括位于所述补偿子电路的第一电极和所述第二电极之间且将所述第一电极和所述第二电极连接的连接部；所述第一电极、所述第二电极和所述连接部均位于所述补偿子电路的控制电极相对所述衬底基板的同一侧；
    所述多个子像素包括第一子像素，所述第一子像素的发光元件的第一驱动电极包括第一主体部和第一突出部，所述第一主体部包括与某一方向平行的第一边，所述第一突出部从所述第一主体部的第一边突出，所述第一突出部与所述第一子像素的补偿子电路的连接部在垂直于所述衬底基板的方向上至少部分重叠；所述第一子像素的发光元件配置为发绿光。
  2. 如权利要求1所述的显示基板，其中，所述第一主体部的第一边为直边且与所述第一方向平行，所述突出部从所述第一主体部的第一边沿所述第二方向突出。
  3. 如权利要求1或2所述的显示基板，其中，所述连接部包括第一半导体区、导电区和第二半导体区，所述第一半导体区将所述补偿子电路的第一电极和所述导电区间隔，所述第二半导体区将所述补偿子电路的第二电极与所述导电区间隔；
    所述补偿子电路的第一半导体区、第二半导体区、导电区、第一电极和第二电极位于同一半导体层且为一体的结构。
  4. 如权利要求3所述的显示基板，其中，所述第一子像素的发光元件的第一驱动电极与所述第一子像素的补偿子电路的第一半导体区在垂直于所述衬底基板的方向上至少部分重叠。
  5. 如权利要求4所述的显示基板，其中，所述第一子像素的补偿子电路的第一半导体区的与所述第一子像素的发光元件的第一驱动电极在垂直于所述衬底基板的方向上重叠的 面积与所述第一半导体区的面积的比为50％-100％。
  6. 如权利要求3-5任一所述的显示基板，其中，所述第一突出部与所述第一子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠。
  7. 如权利要求6所述的显示基板，还包括位于所述第一子像素的补偿子电路的控制电极远离衬底基板一侧的屏蔽电极，
    其中，所述屏蔽电极与所述第一子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠；
    在垂直于所述衬底基板的方向上，所述第一子像素的补偿子电路的导电区与所述第一突出部的重叠面积小于所述第一子像素的补偿子电路的导电区与所述屏蔽电极的重叠面积。
  8. 如权利要求3-7任一所述的显示基板，其中，所述导电区为L型，包括第一分支和第二分支，
    所述第一分支沿所述第二方向延伸并与所述补偿子电路的第一半导体区直接连接；
    所述第二分支沿所述第一方向延伸并与所述补偿子电路的第二半导体区直接连接。
  9. 如权利要求3-8任一所述的显示基板，其中，所述补偿子电路包括补偿晶体管，所述补偿晶体管的栅极、第一极和第二极分别作为所述补偿子电路的控制电极、第一电极和第二电极；
    所述补偿晶体管的栅极包括第一栅极和第二栅极，所述第一半导体区在所述衬底基板上的正投影位于所述第一栅极在所述衬底基板的正投影内，所述第二半导体区在所述衬底基板的正投影位于所述第二栅极在所述衬底基板的正投影内，所述导电区与所述第一栅极、所述第二栅极在垂直于所述衬底基板的方向均不重叠。
  10. 如权利要求9所述的显示基板，其中，在所述第二方向上，所述第一突出部的尺寸小于所述补偿子电路的第一栅极的尺寸。
  11. 如权利要求9或10所述的显示基板，其中，所述发光元件的第一驱动电极在所述衬底基板上的正投影包括在所述第二方向上位于所述补偿子电路的第一栅极在所述衬底基板上的正投影的两侧的第一部分和第二部分，其中所述第一部分与所述补偿子电路的导电区在所述衬底基板上的正投影至少部分重叠；
    所述第一部分的面积小于所述发光元件的第一驱动电极在所述衬底基板上的正投影的总面积的1/10。
  12. 如权利要求1所述的显示基板，其中，在所述第一方向上，所述第一突出部的最大尺寸为所述发光元件的第一驱动电极的最大尺寸的1/8-1/3。
  13. 如权利要求1所述的显示基板，其中，在所述第二方向上，所述第一突出部的最大尺寸小于3微米。
  14. 如权利要求1所述的显示基板，其中，所述多个子像素还包括第二子像素，所述第二子像素的发光元件的第一驱动电极与所述第一子像素的发光元件的第一驱动电极在所述第二方向上并列设置，所述第二子像素的发光元件的第一驱动电极包括与所述第一子像素的 发光元件的第一驱动电极的第一主体部的第一边平行且相对的第二边。
  15. 如权利要求14所述的显示基板，其中，所述第一子像素的补偿子电路的第一突出部在所述第二方向上的最大尺寸小于所述第一边和所述第二边之间间距的1/3。
  16. 如权利要求14或15所述的显示基板，其中，所述第二子像素的补偿子电路的第一半导体区与所述第二子像素的发光元件的第一电极在垂直于所述衬底基板的方向上不重叠。
  17. 如权利要求14-16任一所述的显示基板，其中，所述第二子像素的发光元件的第一驱动电极与所述第二子像素的驱动子电路的控制电极在垂直于衬底基板的方向上至少部分重叠。
  18. 如权利要求14-17任一所述的显示基板，其中，所述第一子像素的像素电路与所述第二子像素的像素电路在所述第二方向并列设置。
  19. 如权利要求13-18任一所述的显示基板，其中，所述像素电路还包括第一发光控制子电路，所述第一发光控制子电路与所述驱动子电路的第一端以及第一电压端连接，且配置为响应于第一发光控制信号将来自所述第一电压端的第一电源电压施加至所述驱动子电路的第一端。
  20. 如权利要求19所述的显示基板，还包括扫描线和发光控制线，
    其中，所述扫描线和所述发光控制线均沿所述第一方向延伸，
    所述扫描线与所述第一子像素的补偿子电路的控制电极电连接以提供所述扫描信号，所述发光控制线与所述第一子像素的第一发光控制子电路连接以提供所述第一发光控制信号。
  21. 如权利要求20所述的显示基板，其中，所述第一子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第一中心点位于所述扫描线在所述衬底基板上的正投影与所述发光控制线在所述衬底基板上的正投影之间。
  22. 如权利要求20或21所述的显示基板，其中，所述第一子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第一中心点和所述第二子像素的发光元件的第一驱动电极在所述衬底基板上的正投影的第二中心点在所述第二方向上分别位于所述扫描线在所述衬底基板上的正投影的两侧，且所述第一中心点相较于所述第二中心点更靠近所述扫描线在所述衬底基板上的正投影。
  23. 如权利要求1-22任一所述的显示基板，其中，所述多个子像素还包括第三子像素，所述第三子像素的发光元件的第一驱动电极包括第二主体部和第二突出部，所述第三子像素的发光元件的第一驱动电极的第二主体部包括与所述第二方向平行的第三边，所述突出部从所述第三边沿所述第一方向突出，所述第三子像素的发光元件的第一驱动电极的第二突出部与所述第三子像素的补偿子电路的导电区在垂直于所述衬底基板的方向上至少部分重叠。
  24. 如权利要求23所述的显示基板，其中，所述多个子像素还包括第四子像素，所述第四子像素与所述第三子像素在所述第一方向上相邻且位于与所述第三子像素的发光元件的第一驱动电极的第二主体部的第三边的相对一侧，
    所述第三子像素的发光元件的第一驱动电极与所述第四子像素的补偿子电路的导电区 在垂直于所述衬底基板的方向上至少部分重叠。
  25. 如权利要求24所述的显示基板，还包括沿所述第一方向延伸的扫描线，
    其中，所述扫描线与所述第一子像素的补偿子电路的控制电极电连接以提供所述扫描信号；
    所述显示基板还包括位于所述发光元件的第一驱动电极远离所述衬底基板一侧的像素界定层，所述像素界定层包括多个开口以分别定义所述多个子像素的开口区，每个子像素的发光元件的发光层的至少部分位于所述每个子像素对应的开口中；
    所述第一子像素、所述第三子像素和所述第四子像素沿所述第一方向排列；在垂直于所述衬底基板的方向上，所述扫描线与所述第三子像素的开口区及所述第四子像素的开口区均重叠。
  26. 一种显示装置，包括如权利要求1-25任一所述的显示基板。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023206129A1 (zh) * 2022-04-27 2023-11-02 京东方科技集团股份有限公司 显示基板和显示装置
CN117859415A (zh) * 2022-08-08 2024-04-09 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124754A1 (en) * 2012-11-02 2014-05-08 Kyung-Min Park Organic light emitting diode display
CN103872080A (zh) * 2012-12-13 2014-06-18 乐金显示有限公司 有机发光二极管显示装置
CN107492567A (zh) * 2017-08-30 2017-12-19 上海天马有机发光显示技术有限公司 一种显示基板及显示装置
CN107681063A (zh) * 2017-10-11 2018-02-09 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
US20190288055A1 (en) * 2017-09-29 2019-09-19 Sharp Kabushiki Kaisha Display device
CN110299384A (zh) * 2019-06-10 2019-10-01 昆山国显光电有限公司 一种显示面板
CN110610684A (zh) * 2019-10-29 2019-12-24 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN210403734U (zh) * 2019-11-28 2020-04-24 京东方科技集团股份有限公司 一种显示基板、显示装置
CN111429843A (zh) * 2020-04-30 2020-07-17 京东方科技集团股份有限公司 显示基板、显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200641774A (en) * 2005-04-28 2006-12-01 Sanyo Electric Co Electroluminescense display device and data line driving circuit
JP4476903B2 (ja) 2005-08-24 2010-06-09 株式会社東芝 薄膜圧電共振器およびフィルタ回路
KR20080001941A (ko) * 2006-06-30 2008-01-04 삼성전자주식회사 표시패널
CN104600081A (zh) 2014-12-31 2015-05-06 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
KR102491117B1 (ko) * 2015-07-07 2023-01-20 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102402605B1 (ko) * 2015-07-28 2022-05-27 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102550604B1 (ko) * 2016-08-03 2023-07-05 삼성디스플레이 주식회사 반도체장치 및 그 제조방법
KR102556020B1 (ko) * 2018-01-31 2023-07-17 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 유기발광표시장치
KR102571354B1 (ko) 2018-05-16 2023-08-28 엘지디스플레이 주식회사 전계발광 표시장치
KR102497286B1 (ko) * 2018-07-09 2023-02-08 삼성디스플레이 주식회사 디스플레이 장치
CN109300995B (zh) * 2018-09-27 2021-12-28 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板
CN110690360B (zh) * 2019-09-26 2022-06-17 武汉天马微电子有限公司 一种显示面板和显示装置
CN111128080B (zh) * 2020-03-30 2020-08-04 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124754A1 (en) * 2012-11-02 2014-05-08 Kyung-Min Park Organic light emitting diode display
CN103872080A (zh) * 2012-12-13 2014-06-18 乐金显示有限公司 有机发光二极管显示装置
CN107492567A (zh) * 2017-08-30 2017-12-19 上海天马有机发光显示技术有限公司 一种显示基板及显示装置
US20190288055A1 (en) * 2017-09-29 2019-09-19 Sharp Kabushiki Kaisha Display device
CN107681063A (zh) * 2017-10-11 2018-02-09 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN110299384A (zh) * 2019-06-10 2019-10-01 昆山国显光电有限公司 一种显示面板
CN110610684A (zh) * 2019-10-29 2019-12-24 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN210403734U (zh) * 2019-11-28 2020-04-24 京东方科技集团股份有限公司 一种显示基板、显示装置
CN111429843A (zh) * 2020-04-30 2020-07-17 京东方科技集团股份有限公司 显示基板、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4002478A4

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