WO2022027177A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022027177A1
WO2022027177A1 PCT/CN2020/106576 CN2020106576W WO2022027177A1 WO 2022027177 A1 WO2022027177 A1 WO 2022027177A1 CN 2020106576 W CN2020106576 W CN 2020106576W WO 2022027177 A1 WO2022027177 A1 WO 2022027177A1
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WIPO (PCT)
Prior art keywords
sub
signal line
signal
circuit
voltage
Prior art date
Application number
PCT/CN2020/106576
Other languages
English (en)
French (fr)
Inventor
李�根
杨慧娟
顾品超
庞玉乾
张竞文
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080001424.3A priority Critical patent/CN114616614B/zh
Priority to US17/413,063 priority patent/US12058905B2/en
Priority to PCT/CN2020/106576 priority patent/WO2022027177A1/zh
Publication of WO2022027177A1 publication Critical patent/WO2022027177A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • the display screen of the display device is developing in the direction of large screen and full screen.
  • a display device such as a mobile phone, a tablet computer, etc.
  • a camera device or an imaging device
  • the camera device is usually arranged on a side outside the display area of the display screen.
  • the camera device can be combined with the display area of the display screen, and a position is reserved for the camera device in the display area to maximize the display area of the display screen.
  • At least one embodiment of the present disclosure provides a display substrate including a display area and a transparent area
  • the display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate and located in the display area, the plurality of sub-pixels Pixels are distributed into a plurality of pixel rows and a plurality of pixel columns along a first direction and a second direction, the first direction and the second direction are different;
  • the plurality of pixel rows include a plurality of pixel rows separated by the transparent area a first pixel row;
  • the display substrate further includes a voltage bus, the voltage bus is located in the peripheral area, the voltage bus at least partially surrounds the transparent area, and is configured to be connected with the plurality of first pixel rows
  • the sub-pixels are connected to provide a first voltage;
  • the display substrate further includes a plurality of first signal lines extending along the first direction, and the plurality of first signal lines are respectively connected with the sub-pixels of the plurality of first pixel rows
  • the pixels are
  • the display area includes a first display area and a second display area that are separated by the transparent area and are opposite in the first direction
  • the plurality of pixel rows include a plurality of pixel rows that are separated by the transparent area
  • a plurality of first pixel rows, the sub-pixels in the plurality of first pixel rows are separated from the first display area and the second display area by the transparent area
  • the display substrate further includes A plurality of first voltage lines and a plurality of second voltage lines extending in one direction, the plurality of first voltage lines and the plurality of second voltage lines are all electrically connected to the voltage bus;
  • the voltage lines are located in the first display area and are respectively connected with the sub-pixels in the plurality of first pixel rows located in the first display area to provide the first voltage;
  • the plurality of second voltages The lines are located in the second display area, and are respectively connected with the sub-pixels in the plurality of rows of the first pixel rows located in the second display area to provide the first voltage.
  • each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light;
  • the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, and a reset sub-circuit;
  • the driving sub-circuit includes a control terminal, a first terminal and a second terminal, and is configured to be connected to the light-emitting element and control the driving current flowing through the light-emitting element;
  • the data writing sub-circuit is connected to the The first terminal of the driving sub-circuit is connected and configured to write a data signal into the first terminal of the driving sub-circuit in response to the first scan signal;
  • the compensation sub-circuit includes a control terminal, a first terminal and a second terminal terminal, the control terminal of the compensation sub-circuit is configured to receive the second scanning signal, the first terminal and the second terminal of the compensation sub-circuit are respectively electrically
  • the light-emitting element includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, the first electrode being closer to the light-emitting layer than the light-emitting layer In the base substrate, the voltage bus and the first electrode of the light-emitting element are provided in the same layer and insulated from each other.
  • the storage sub-circuit includes a storage capacitor
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode
  • the first capacitor electrode and the second capacitor electrode are respectively used as the storage sub-circuit.
  • a first end and a second end; the second capacitor electrode is located on the side of the first capacitor electrode close to the base substrate, and both the first voltage line and the second voltage line are the same as the first capacitor electrode of the storage capacitor.
  • the layers are insulated and located on a side of the voltage bus close to the base substrate.
  • the plurality of first signal lines are respectively connected to the data writing subcircuits of the sub-pixels of the plurality of first pixel rows in a one-to-one correspondence to provide the first scan signal; the plurality of first signal lines
  • Each of the first signal line portions of a signal line includes a first signal line sub-section located in the first display area and a second signal line sub-section located in the second display area, and each of the first signal lines
  • the second signal line part of the first signal line part electrically connects the first signal line sub-section and the second signal line sub-section; the first signal line sub-section and the second signal line sub-section of each first signal line
  • the first signal line sub-sections are connected to the sub-pixels located in the first display area in the first pixel row corresponding to the first signal line, and the second signal line sub-sections extend along the first direction.
  • the line sub-section is connected to the sub-pixel located in the second display area in the first pixel row corresponding to the first signal line.
  • the first signal line sub-section and the second signal line sub-section of the first signal line are disposed in the same layer, and are located in the second signal line part of the first signal line close to the base substrate side.
  • the display substrate further includes first connection electrodes, and the plurality of first connection electrodes are located on a side of the second signal line portion of the plurality of first signal lines away from the base substrate; the The first signal line sub-section and the second signal line part of each of the plurality of first signal lines are respectively electrically connected through the first connection electrode; the first connection electrode is connected to the corresponding first connection electrode through the first via hole.
  • the first signal line sub-portion of a signal line is electrically connected, and is electrically connected with the corresponding second signal line portion of the first signal line through the second via hole.
  • both the first via hole and the second via hole are located on a side of the voltage bus line away from the transparent region, and are arranged side by side in the second direction.
  • the second signal line portion of the first signal line further includes a first extension portion and a second extension portion located on both sides of the bent portion and electrically connected to the bent portion; the first extension portion and the second extension portion are electrically connected to the bent portion. Both an extension portion and the second extension portion extend along the first direction and are electrically connected to the first signal line sub-section and the second signal line sub-section, respectively.
  • the voltage bus overlaps with the first extension portion and the second extension portion of the second signal line portion of the first signal line in a direction perpendicular to the base substrate, and overlaps with the bent portion There is no overlap in the direction perpendicular to the base substrate.
  • the display substrate further includes a plurality of third signal line sub-sections located in the first display area and extending along the first direction, the plurality of third signal line sub-sections being respectively connected with the The control terminals of the reset sub-circuits of the sub-pixels of the plurality of first pixel rows located in the first display area are connected in a one-to-one correspondence to provide the reset control signal; the plurality of third signal line sub-sections Each of the first signal lines connected to its corresponding row of sub-pixels is electrically connected to each other; each of the third signal line sub-sections is in the same layer as the first signal line sub-section of the corresponding first signal line set up.
  • the display substrate further includes a plurality of fourth signal line sub-sections located in the peripheral region, and the plurality of fourth signal line sub-sections are in one-to-one correspondence with the plurality of third signal line sub-sections Electrically connected, each of the plurality of fourth signal line sub-sections is electrically connected to the bent portion of the second signal line portion of the first signal line that is connected to the sub-pixel to which the corresponding third signal line sub-section is connected connect.
  • one end of each of the plurality of fourth signal line sub-sections is electrically connected to the corresponding third signal line sub-section, and the other end is electrically connected to the bent portion; In the direction of the base substrate, the voltage bus line overlaps with each of the plurality of fourth signal line subsections.
  • the first signal line parts of the plurality of first signal lines and the first capacitor electrodes are disposed in the same layer as insulation, and the second signal line parts of the plurality of first signal lines are insulated from the second signal line parts of the first signal lines.
  • the capacitor electrodes are insulated on the same layer.
  • the display substrate further includes a plurality of second signal lines extending along the second direction, each of the plurality of second signal lines including a first signal line portion located in the display area and a second signal line part located in the peripheral area; the second signal line part of each second signal line includes a first signal line sub-section, a second signal line sub-section and a third signal line sub-section connected in sequence , the first signal line sub-section and the third signal line sub-section of each second signal line are linear structures, and the second signal line sub-section of each second signal line includes a curved structure; the The plurality of second signal lines are power lines.
  • the display substrate further includes a plurality of second connection electrodes, wherein the plurality of second connection electrodes and the plurality of second signal lines are provided with insulation in the same layer, and the plurality of first voltage lines are electrically connected to the voltage bus through the plurality of second connection electrodes, respectively.
  • the display substrate further includes a dummy electrode disposed at least partially around the transparent region and closest to the transparent region compared to other wires.
  • the display substrate further includes a plurality of first compensation electrodes located in the peripheral region, and the plurality of first compensation electrodes are respectively arranged in a one-to-one correspondence with the plurality of first signal lines;
  • a plurality of first compensation electrodes are located on the side of the third signal line segment of the plurality of first signal lines away from the base substrate; each of the plurality of first compensation electrodes corresponds to the corresponding first signal line
  • the bent portions of the two signal line portions overlap in a direction perpendicular to the base substrate to form a compensation capacitor; the plurality of first compensation electrodes are located on a side of the voltage bus line close to the transparent region.
  • At least one embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device further includes a sensor disposed on a side of the base substrate away from the plurality of sub-pixels and configured to receive and detect light transmitted through the transparent region.
  • FIG. 1A is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • 1B is a second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 1C is a third schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2A is an enlarged schematic view of area A in FIG. 1C;
  • FIG. 2B is a partial enlarged schematic view of FIG. 2A;
  • Figure 2C is a cross-sectional view of Figure 2B along section line I-I';
  • FIG. 3 is a fourth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Fig. 4 is the enlarged schematic diagram of area B in Fig. 1C;
  • 5A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5A;
  • 5C is a timing signal diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • 6A is a fifth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6B is a cross-sectional view of FIG. 1A along section line II-II';
  • Figure 6C is a cross-sectional view of Figure 1A along section line III-III';
  • FIG. 7 is a sixth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8A is a seventh schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 8B is an eighth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a ninth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10A is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • Fig. 10B is a cross-sectional view of Fig. 10A along section line IV-IV'.
  • arranging the imaging element in the display area of the display device helps to increase the ratio of the display screen, for example, to realize full-screen display. Since the display device is fabricated in the display area, the light transmittance of the imaging element will be affected. For example, the light-emitting element and the light-tight wiring in the sub-pixel may block the light captured by the imaging element, thereby affecting the imaging quality.
  • the light transmittance of the area can be improved by not arranging sub-pixels and signal lines in the display area provided with the imaging element, but this arrangement will affect the connection and distribution of the signal lines around the area, and will also make some
  • the lack of pixels in pixel rows that is, the number of sub-pixels in different rows is different, leads to different loads of signal lines connecting sub-pixels in different rows, and further, the signal lines transmit signals at different speeds, resulting in uneven display.
  • FIG. 1A shows a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 20 includes a display area 21 and a transparent area 22 .
  • the display area 21 is an area where sub-pixels are arranged, and no sub-pixels are arranged in the transparent area 22.
  • the transparent area 22 is not provided with pixel circuits or even wirings, so that the light transmittance is relatively high and approximately transparent.
  • the display substrate further includes a peripheral area 23 located between the display area 21 and the transparent area 22 , and the peripheral area 23 is, for example, an annular area arranged around the transparent area 22 . When the signal line passes through the transparent area 22, it will extend around the transparent area 22 to avoid blocking the transparent area.
  • the peripheral area 23 is also not provided with pixel circuits, and the peripheral area 23 provides the space around the transparent area 22 for the lines. .
  • the display area 21 includes a first display area A1 and a second display area A2 which are separated by the transparent area 22 and are opposite to each other in the first direction D1.
  • the transparent area 22 is located in the display area 21, and the display area 21 further includes a third display area A3 and a fourth display area A4 which are separated by the transparent area 22 and opposite in the second direction D2.
  • the transparent area 22 may also be located outside the display area 21 in the second direction D2, that is, there is a concave area in the display area 21, and the transparent area 22 is disposed in the concave area.
  • the relative positional relationship between the transparent area 22 and the display area 21 is not limited.
  • the display substrate 20 includes a plurality of sub-pixels located in the display area 21, and the plurality of sub-pixels are respectively a plurality of pixel rows and a plurality of pixel columns along the first direction D1 and the second direction D2.
  • the first direction D1 and the second direction D2 are different, for example, orthogonal to each other.
  • the plurality of pixel rows include a plurality of first pixel rows separated by the transparent area, and the sub-pixels in the plurality of first pixel rows are separated from the first display area A1 and the second display area A2 by the transparent area 22, that is,
  • the first display area A1 includes multiple rows of sub-pixels, and the second display area A2 also includes multiple rows of sub-pixels on corresponding pixel rows.
  • the number of sub-pixels in the plurality of first pixel rows is higher than that in the display area 21 except the area of the first display area A1 and the second display area A2 (for example, the third display area A3 and the second display area A2).
  • the number of sub-pixels in a row of sub-pixels in the four display areas A4) is small.
  • Sub-pixels are omitted in FIG. 1A , and only the distribution of some signal lines is schematically shown.
  • the signal line will extend around the transparent area 22 when passing through the transparent area 22 to avoid blocking the transparent area.
  • Such wiring makes the wiring in the peripheral region 23 around the transparent region 22 denser, which not only imposes higher requirements on the process but also affects the yield of the product.
  • FIG. 1B shows an example of an enlarged schematic view of the transparent area and the peripheral area.
  • the display substrate 20 further includes a voltage bus 210 located in the peripheral area 23 between the display area 21 and the transparent area 22 .
  • the voltage bus 210 is disposed at least partially around the transparent region 22 and is configured to be connected to the sub-pixels in the plurality of first pixel rows to provide a first voltage.
  • the first voltage may be a power supply voltage (VDD or VSS) or a reset voltage (VINT) or other fixed voltage signals; correspondingly, the voltage bus 210 may be a power supply voltage bus or a reset voltage bus or the like.
  • the sub-pixels in the plurality of first pixel rows receive the same first voltage because they are connected to the same voltage bus 210, and due to the existence of the voltage drop on the signal line, the sub-pixels in different positions receive the first voltage.
  • the value of a voltage may vary, which is not intended to limit the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure provides voltages to sub-pixels in a plurality of pixel rows (ie, first pixel rows) separated by the transparent region 22 by setting the voltage bus lines 210 .
  • the sub-pixels located in the first display area A1 and the second display area A2 are connected, so that the sub-pixels located in the same first pixel row have the same load (because they are all connected to the voltage bus 210), which improves the display uniformity;
  • the voltage bus 210 is simultaneously connected to a plurality of sub-pixels of the first pixel row to provide voltage signals, which simplifies the wiring of the peripheral area, thereby optimizing the process and improving the yield of the product.
  • the display substrate 10 further includes a plurality of first voltage lines 211 and a plurality of second voltage lines 212 extending along the first direction D1 , the plurality of first voltage lines 211 and the plurality of second voltage lines 212 .
  • the voltage lines 212 are all electrically connected to the voltage bus 210 .
  • the plurality of first voltage lines 211 are located in the first display area A1 , and are respectively connected to a plurality of rows of sub-pixels located in the first display area A1 among the plurality of first pixel rows to provide a first voltage.
  • the plurality of second voltage lines 212 are located in the second display area A2 and are respectively connected to the plurality of rows of sub-pixels located in the second display area A2 among the plurality of first pixel rows to provide the first voltage.
  • the first voltage line 211 located in the first display area A1 and the second voltage line 212 located in the second display area A2 do not need to be electrically connected through wiring, but only need to be connected to the voltage bus.
  • the corresponding side is electrically connected to the voltage bus.
  • the voltage bus 210 is annular and completely surrounds the transparent area 22 ; in other examples, the voltage bus 210 can also partially surround the transparent area 22 or have other shapes, as long as the The voltage bus 210 may be electrically connected to the first voltage line 211 and the second voltage line 212 on both sides.
  • the display substrate 20 further includes a plurality of first signal lines 31 , and the plurality of first signal lines 31 are respectively connected to the sub-pixels of the plurality of first pixel rows in one-to-one correspondence to provide the first signal lines 31 .
  • the first signal line 31 may be, for example, a scan line or a control line
  • the first signal may be, for example, a scan signal or a control signal (for example, a reset control signal or a light-emitting control signal).
  • Each of the first signal lines 31 includes a first signal line part 31a located in the display area 21 and a second signal line part 31b located in the peripheral area 23, the first signal line part 31a and the second signal line part 31b being electrically connected to each other .
  • the first signal line portion 31a includes a first signal line sub-section 318 located in the first display area A1 and a second signal line sub-section 319 located in the second display area A2.
  • Each first signal line The second signal line portion 31b of 31 is located between the first signal line sub-section 318 and the second signal line sub-section 319 thereof, and electrically connects the first signal line sub-section 318 and the second signal line sub-section 319 .
  • the first signal line sub-section 318 and the second signal line sub-section 319 are both linear structures and extend along the first direction D1, the first signal line sub-section 318 and the first signal line to which it belongs
  • the sub-pixels located in the first display area A1 in the first pixel row corresponding to 31 are connected, and the second signal line sub-section 319 is connected with the sub-pixels located in the second display area A2 in the corresponding first pixel row.
  • FIG. 1B only shows the second signal line portion 31 b of the first signal line 31 .
  • the second signal line portion 31 b includes a bent portion 313 extending along the transparent region 22 .
  • the bent portion 313 is arc-shaped and extends around the transparent area 22; for example, as shown in FIG. 1B , the bent portion 313 is a part of the arc, but this is not a limitation to the present disclosure, in other cases
  • the bent portion 313 may include a plurality of sections that are connected in sections and have different shapes.
  • the bent portions 313 in the second signal line portions 31 b of the plurality of first signal lines 31 are all located on the side of the voltage bus line 210 close to the transparent region 22 .
  • This arrangement enables the voltage bus 210 to avoid the wire-intensive winding area, which facilitates the electrical connection between the voltage bus 210 and the first voltage line 211 or the second voltage line 212 .
  • the second signal line portion 31b further includes a first extension portion 311 and a second extension portion 312 located on both sides of the bent portion 313 , the first extension portion 311 and the second extension portion 312 are respectively It is electrically connected to both ends of the bent portion 313 .
  • the first extension portion 311 extends along the first direction D1 to the first display area A1 and is electrically connected to the corresponding first signal line sub-portion 318
  • the second extension portion 312 extends along the first direction D1 to the second display area A2 and is electrically connected to the corresponding second signal line sub-section 319 .
  • the first extension portion 311 and the second extension portion 312 are both linear structures.
  • the number of sub-pixels in the plurality of first pixel rows is higher than that in the display area 21 except the area of the first display area A1 and the second display area A2 (for example, the third display area A3 and the number of sub-pixels in a row of sub-pixels in the fourth display area A4) is small, and the load of the signal lines (such as scan lines) correspondingly connected to the first pixel row will be smaller than those located in the third display area A3 or the fourth display area A4.
  • a load of signal lines connected to a complete pixel row is small, and the load of the signal lines (such as scan lines) correspondingly connected to the first pixel row.
  • load compensation may be performed on the first signal line, so as to narrow the difference between the load of the first signal line and the load of other signal lines, for example, to make the load of the first signal line substantially the same as the load of other signal lines.
  • One compensation method is to form a compensation capacitor on the signal line, thereby increasing the resistance-capacitance load of the signal line.
  • the capacitance value of the compensation capacitor can be designed according to the number of missing sub-pixels in the first pixel row corresponding to the first signal line.
  • the wiring portion of the signal line that is not directly connected to the sub-pixels in the peripheral region can be selected to form the compensation capacitor.
  • the bent portion of the first signal line is in the shape of an arc as a whole, which is inconvenient to calculate the electrode area for forming the capacitor, and therefore inconvenient to design the compensation capacitor.
  • a display substrate provided by at least one embodiment of the present disclosure includes a first signal line extending along the first direction; the first signal line includes a first signal line part located in the display area and a first signal line part located in the peripheral area The second signal line part, the first signal line part and the second signal line part are electrically connected to each other; the second signal line part of the first signal line includes a first sub-section and a second sub-section connected in sequence and a third sub-section, the first sub-section and the third sub-section both include a curved structure, the second sub-section is a linear structure; the display substrate further includes a first sub-section located in the peripheral area a compensation electrode, the first compensation electrode at least partially overlaps with the second subsection of the second signal line portion of the first signal line in a direction perpendicular to the base substrate to form a compensation capacitance.
  • a linear structure is designed in the winding portion of the first signal line, thereby facilitating the design of the capacitance value of the compensation capacitor.
  • FIG. 1C shows another example of an enlarged schematic view of the transparent area and the peripheral area of FIG. 1A .
  • the display substrate 20 includes a first compensation region 231 located between the display region 21 and the transparent region 22 .
  • the first compensation region 23 is a part of the peripheral region 23 .
  • the bent portion 313 of the second signal line portion 31b of the first signal line 31 includes a first sub-portion 313a, a second sub-portion 313b and a third sub-portion 313c which are connected in sequence, that is, the second sub-portion 313b is located in The first sub-section 313a and the third sub-section 313c are electrically connected between them.
  • the first sub-section 313a is located on the side of the first compensation area 231 close to the first display area A1 and extends around the transparent area 22, and the third sub-section 313c is located at the side of the first compensation area 231 close to the second display area A2 One side and extending around the transparent area 22 .
  • Both the first sub-section 313a and the third sub-section 313c include curvilinear structures, that is, at least part or all of the first sub-section 313a and the third sub-section 313c are curvilinear structures; the second sub-section 313b is a straight line type structure. At least part of the second sub-section 313b is located in the first compensation region 231 for coupling with the first compensation electrode to form a compensation capacitance.
  • the extending direction of the second sub-portion 313b is parallel to the first direction D1.
  • the first sub-section 313 a and the third sub-section 313 c are arc-shaped structures respectively.
  • the first compensation electrode may be a part of a signal line that overlaps with the second subsection 313b in a direction perpendicular to the base substrate, or may be an additional compensation electrode, which is not limited in this embodiment of the present disclosure.
  • the first sub-section 313 a and the third sub-section 313 c are respectively directly electrically connected to both ends of the second sub-section 313 b along the first direction D1 , and the first sub-section 313 a is in the first sub-section 313 a
  • the angle ⁇ 1 between the tangent at the connection point of the part 313a and the second sub-portion 313b and the straight line where the second sub-portion 313b is located is an acute angle
  • the included angle between the tangent at the connection point of the two sub-portions 313b and the straight line where the second sub-portion 313b is located is an acute angle.
  • FIG. 2A shows an enlarged schematic view of the region A in FIG. 1C , in which a partial outline of the first compensation area 231 is shown by a dotted line.
  • the display substrate 20 includes a first compensation electrode 315 for forming a compensation capacitance, and the first compensation electrode 23 is located in the first compensation region 231 .
  • the first compensation electrode 315 overlaps with a second subsection of the second signal line portion of at least one of the plurality of first signal lines 31 in a direction perpendicular to the base substrate to form a compensation capacitance.
  • the display substrate 20 includes a plurality of first compensation electrodes 315, and the plurality of first compensation electrodes 315 are respectively arranged in a one-to-one correspondence with the plurality of first signal lines 31, and each first compensation electrode 315 corresponds to a corresponding first signal line
  • the portion of the second sub-section 313b of the second signal line portion 31b of 31 located in the first compensation region 231 overlaps in a direction perpendicular to the base substrate to form a compensation capacitance.
  • the first compensation electrode 315 is located on the side of the second signal line portion 31b away from the base substrate 200 .
  • the capacitance value to be compensated on the first signal line 31 can be calculated according to the number of missing sub-pixels in the first pixel row corresponding to the first signal line 31 , thereby determining the total area of the first compensation electrode 315 .
  • FIG. 2B shows a partially enlarged schematic view of Fig. 2A
  • Fig. 2C shows a cross-sectional view of Fig. 2B along the section line I-I'. Due to space limitations, for each first signal line 31, FIG. 2B and FIG. 2C only show the situation where the second sub-section 313b of the second signal line part 31b is close to the side of the first sub-section 313a.
  • the average line width (the average dimension along the second direction D2 in FIG. 2A ) of the second sub-portion 313b of the second signal line portion 31b is larger than that of the first sub-portion 313a or the third sub-portion 313c . Since the second sub-portion 313b is used as a capacitor electrode of the compensation capacitor, increasing the line width of the second sub-portion 313b is beneficial to increase the area of the compensation capacitor, thereby obtaining a larger compensation capacitor.
  • the second sub-section 313b includes a first part located in the first compensation region 231 for forming the compensation capacitance and a second part located outside the first compensation region 231 , and the average line width of the first part is larger than the average line width of the second part Line width, the average line width of the second portion can be consistent with the average line width of the first sub-portion 313a; that is, the first compensation electrode 315 only partially overlaps with the second sub-portion 313b to form a compensation capacitance, the The overlapping area of the second subsection with the first compensation electrode can be determined according to the calculated capacitance value to be compensated.
  • each first compensation electrode 315 is divided into a plurality of compensation electrode parts 315a spaced apart from each other, because for each first signal line 31, the corresponding first compensation electrode 315 may not be continuously arranged, for example, by other spaced by the signal lines.
  • dividing each first compensation electrode 315 into a plurality of compensation electrode parts 315a is beneficial to compensation design.
  • each compensation capacitance includes a plurality of compensation sub-capacitors connected in parallel with each other.
  • the capacitance value to be compensated on the first signal line 31 and the capacitance value of each compensation sub-capacitor can be calculated according to the number of missing sub-pixels in the first pixel row corresponding to the first signal line 31 to determine the first signal line. 31
  • a fixed voltage may be loaded on the first compensation electrode 315, so as to improve the stability of the compensation capacitance.
  • the plurality of compensation electrode parts in the plurality of first compensation electrodes are arranged in an array along the first direction D1 and the second direction D2.
  • the compensation electrode parts located in the same column may be connected to each other as a whole. structure, which can reduce the difficulty of the process.
  • the plurality of compensation electrode portions 315a corresponding to each second subsection 313b are electrically connected to each other, thereby ensuring that the plurality of compensation subcapacitors formed on the second subsection 313b can be connected in parallel with each other. Since the plurality of compensation electrode parts 315a are spaced apart from each other, there is no direct electrical connection, and the electrical connection may be formed by other structures.
  • the display substrate 20 further includes a second compensation electrode 317 .
  • the second compensation electrode 317 and the first compensation electrode 315 are respectively located on the side of the first signal line 31 .
  • Two sides of the second signal line portion 31b are electrically connected to each other, thereby forming a parallel capacitor structure, which is beneficial to increase the capacitance value of the compensation capacitor in a limited space.
  • the second compensation electrode 317 is located on the side of the second signal line portion 31b close to the base substrate, and the first compensation electrode 315 is located on the side of the second signal line portion 31b away from the base substrate.
  • the second compensation electrode 317 includes a semiconductor material, which is a conductive semiconductor material, such as a heavily doped semiconductor material.
  • the second compensation electrode 317 and the active layer of the transistor in the pixel circuit are disposed in the same layer and integrally formed.
  • the first compensation electrode 315 and the second sub-section 313b constitute a first capacitor C1
  • the second sub-section 313b and the second compensation electrode 317 constitute a second capacitance C2
  • each compensation electrode section 315a passes through
  • the via hole 350 is electrically connected to the second compensation electrode 317 .
  • the display substrate 20 includes a plurality of second compensation electrodes 317 , and the plurality of second compensation electrodes are arranged in a one-to-one correspondence with the second sub-portions 313 b of the second signal line portions 31 b of the plurality of first signal lines 31 , that is, They are arranged in a one-to-one correspondence with the plurality of first compensation electrodes 315 .
  • a plurality of second compensation electrodes 317 are integrated into a structure, so that a plurality of compensation electrode parts 315a electrically connected to the second compensation electrodes 317 are electrically connected to each other, so that a plurality of compensation elements formed on each second sub-part 313b Capacitors can be formed in parallel with each other.
  • the transparent area 22 is a circular area
  • the number of missing sub-pixels in the plurality of first pixel rows separated by the transparent area 22 is different.
  • the first pixel row set corresponding to the diameter of the circular area has the most missing sub-pixels.
  • FIG. 3 shows a schematic diagram of the area layout of the display substrate around the transparent area 22 .
  • the signal lines are only schematically shown, and the blank area around the figure represents the display area 21 .
  • the display substrate 20 further includes a second compensation region 232 located between the display region 21 and the transparent region 22 , the first compensation region 231 and the second compensation region 232 are respectively located in the transparent region in the second direction D2 Opposite sides of 22 are, for example, arranged symmetrically with respect to the geometric center of the transparent region 22 .
  • the arrangement of the compensation electrodes in the second compensation area is similar to that of the first compensation area, and details are not described herein again.
  • the first compensation area and the second compensation area are both located on the side of the voltage bus 210 close to the transparent area 22 , that is, the plurality of first compensation electrodes are located on the side of the voltage bus 210 close to the transparent area 22 .
  • the plurality of first pixel rows separated by the transparent regions 22 are divided into a first part and a second part with substantially the same number of rows in the second direction D2 (for example, divided along the dotted line in FIG. 3 ), for example, in FIG.
  • the upper half and the lower half separated by the dotted line, the first signal line connected to the first part is compensated by the compensation area on the same side as the first part, such as the first compensation area 231 on the upper side in FIG.
  • the first signal line corresponding to the second part is compensated by the compensation area on the same side as the second part, such as the second compensation area 232 on the lower side as shown in FIG. 3 .
  • the number of missing sub-pixels in the second direction D2 changes monotonically, so the area of the first compensation electrode 315 corresponding to each pixel row is set
  • the monotonous change for example, the number of the compensation electrode portions 315a corresponding to each first pixel row changes monotonically. For example, in the direction F shown in FIG.
  • the number of missing sub-pixels in multiple first pixel rows to be compensated by the first compensation region 231 monotonically changes monotonically decreases, and the number of the sub-pixels corresponding to each first pixel row is set
  • the area of a compensation electrode 315 decreases monotonically, and the number of compensation electrode portions 315a corresponding to each first pixel row decreases monotonically, thus forming a semicircular first compensation area 231 as shown in FIG. 3 .
  • the second compensation area 232 is also a semi-circular area, which is not repeated here.
  • the plurality of compensation electrode portions 315a corresponding to the plurality of first signal lines 31 are arranged in an array along the first direction D1 and the second direction D2, and in the second direction D2, located in the first direction
  • the number of compensation electrode portions 315a in each row on D1 changes monotonically.
  • the display substrate 20 further includes a plurality of second signal lines 32 extending along the second direction D2, and each second signal line 32 includes a The first signal line part and the second signal line part located in the peripheral area; for example, the first signal line part and the second signal line part are arranged in the same layer and connected as an integral structure.
  • the second signal line part includes the first signal lines connected in sequence
  • the sub-section 321, the second signal wire sub-section 322 and the third signal wire sub-section 323, the first signal wire sub-section 321 and the third signal wire sub-section 323 are linear structures
  • the second signal wire sub-section 322 includes Curved structure, for example, the second signal line sub-portion 322 is an arc-shaped structure extending around the transparent region 22 .
  • the first signal line sub-portion 321 and the second signal line sub-portion 323 of the second signal line 32 located in the compensation area are designed as linear structures to facilitate the design of compensation capacitors.
  • the plurality of first signal line sub-sections 321 of the plurality of second signal lines 32 are provided in a one-to-one correspondence with the plurality of columns of compensation electrode sections 315a.
  • each column of the compensation electrode part 315 a and the first signal line sub-part 321 of the corresponding one of the second signal lines 32 are electrically connected to each other.
  • a plurality of second signal lines 32 and the first compensation electrodes 315 are disposed in the same layer, and each second signal line 32 is integrated with a corresponding column of compensation electrode portions 315a.
  • the plurality of second signal lines 32 are power lines and are configured to be connected to the same power supply voltage terminal. Therefore, by being electrically connected to the corresponding second signal lines 32, the plurality of compensation electrode portions 315a are electrically connected. Thus, a plurality of compensation sub-capacitors in a row are connected in parallel. In addition, by being electrically connected to the second signal line 32, a fixed voltage is loaded on the first compensation electrode, thereby improving the stability of the compensation capacitance.
  • the first signal line part of the second signal line 32 is separated by the transparent area into two parts respectively located in the third display area A3 and the fourth display area A4, and the same second signal line Two parts of 32 are connected to sub-pixels in the same column but separated by transparent regions to provide supply voltages.
  • the display substrate 20 further includes a plurality of third signal lines 33 extending along the second direction D2 , the third signal lines 33 include The first signal line portion and the second signal line portion located in the peripheral area.
  • the second signal line portion of the third signal line 33 includes a first signal line sub-section 331 , a second signal line sub-section 332 and a third signal line sub-section 333 which are connected in sequence.
  • the first signal line sub-section 331 and the second signal line sub-section 332 are both linear structures, and the second signal line portion 333 extends around the transparent area 22 .
  • first signal line sub-portion 331 , the second signal line sub-portion 332 and the second signal line portion 333 of each third signal line 33 are disposed on the same layer and integrally formed.
  • the first signal line sub-section 331 and the second signal line sub-section 332 of the third signal line are respectively located in the third display area A3 and the fourth display area A4 and are located in the same column of sub-pixels (No. A pixel column) is connected to provide electrical signals.
  • the plurality of third signal lines are respectively connected to the sub-pixels of the plurality of first pixel columns in a one-to-one correspondence, and the first signal line portion of each third signal line 33 is electrically connected to the corresponding sub-pixels of the first pixel column.
  • the third signal line 33 is a data line.
  • the plurality of second signal lines 32 , the plurality of third signal lines 33 and the first compensation electrodes 315 are all provided in the same layer. Since the third signal line 33 needs to be insulated from the first compensation electrode 315 , separating the first compensation electrode 315 into a plurality of spaced compensation electrode portions 315b in the first direction D1 is beneficial for wiring.
  • FIG. 4 shows an enlarged schematic view of area B in FIG. 1C .
  • each sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit, and may also include a light-emitting control sub-circuit, a reset circuit and the like as required.
  • FIG. 4 shows one pixel circuit 100 in the first display area A1.
  • FIG. 5A shows a schematic circuit diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit includes a driving sub-circuit 122, a compensation sub-circuit 128, a data writing sub-circuit 126, a storage sub-circuit 127, a first light-emitting control sub-circuit 123, a second light-emitting control sub-circuit 124, and a first light-emitting control sub-circuit 124.
  • Reset subcircuit 125 and second reset subcircuit 129 are examples of the pixel circuit.
  • the driving sub-circuit 122 includes a control terminal 122a, a first terminal 122b and a second terminal 122c, and is configured to be connected to the light-emitting element 121 and to control the driving current flowing through the light-emitting element 121 .
  • the control terminal 122a of the driving sub-circuit 122 is connected to the first node N1
  • the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2 and configured to receive the first power supply voltage VDD
  • the second terminal 122c of the driving sub-circuit 122 and
  • the third node N3 is connected.
  • the data writing sub-circuit 126 includes a control terminal 126a, a first terminal 126b and a second terminal 126c.
  • the control terminal 126a is configured to receive the first scanning signal Ga1
  • the first terminal 126b is configured to receive the data signal Vd
  • the second terminal 126b is configured to receive the data signal Vd.
  • the terminal 126c is connected to the first terminal 122b of the driving sub-circuit 122 (ie, the second node N2).
  • the data writing sub-circuit 126 is configured to write the data signal Vd to the first end 122b of the driving sub-circuit 122 in response to the first scanning signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written into the first end 122b (the second node N2) of the driving sub-circuit 122,
  • the data signal is stored in the storage sub-circuit 127, so that the driving current for driving the light-emitting element 121 to emit light can be generated according to the data signal in the light-emitting stage, for example.
  • the compensation sub-circuit 128 includes a control end 128a, a first end 128b and a second end 128c, the control end 128a of the compensation sub-circuit 128 is configured to receive the second scan signal Ga2, and the first end 128b and the second end 128b of the compensation sub-circuit 128
  • the terminal 128c is electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively.
  • the compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scanning signal Ga2.
  • the first scan signal Ga1 may be the same as the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to the same signal output terminal.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through the same scan line.
  • the first scan signal Ga1 may also be different from the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines respectively.
  • the storage sub-circuit 127 includes a first terminal 127a and a second terminal 127b, the first terminal 127a of the storage sub-circuit is configured to receive the first power supply voltage VDD, the second terminal 127b of the storage sub-circuit and the control terminal of the driving sub-circuit 122a is electrically connected.
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127; , the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the relevant information of the threshold voltage of the driving sub-circuit 122 can also be correspondingly stored in the storage sub-circuit, so that, for example, in the storage sub-circuit In the light-emitting stage, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122, so that the output of the driving sub-circuit 122 can be compensated.
  • the storage sub-circuit 127 is electrically connected to the control terminal 122 a of the driving sub-circuit 122 and the first power supply voltage terminal VDD, and is configured to store the data signal written by the data writing sub-circuit 126 .
  • the first power supply voltage terminal VDD is the first power supply voltage terminal 103 ;
  • the first power supply voltage terminal VDD is the second power supply voltage terminal 104 .
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127.
  • the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the relevant information of the threshold voltage of the driving sub-circuit 122 can also be stored accordingly
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 in the light-emitting phase, so that the output of the driving sub-circuit 122 is compensated.
  • the first lighting control sub-circuit 123 is connected to the first terminal 122b (the second node N2 ) of the driving sub-circuit 122 and the first voltage terminal VDD, and is configured to connect the first voltage terminal VDD in response to the first lighting control signal EM1
  • the first power supply voltage is applied to the first terminal 122 b of the driving sub-circuit 122 .
  • the first lighting control sub-circuit 123 is connected to the first lighting control terminal EM1 , the first voltage terminal VDD and the second node N2 .
  • the second lighting control sub-circuit 124 is connected to the second lighting control terminal EM2, the first terminal 134 of the lighting element 121 and the second terminal 122c of the driving sub-circuit 122, and is configured to cause the driving current in response to the second lighting control signal can be applied to the light emitting element 122 .
  • the second light-emitting control sub-circuit 123 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can communicate with the light-emitting element 121 through the second light-emitting control sub-circuit 123 Electrical connection, so as to drive the light-emitting element 121 to emit light under the control of the driving current; and in the non-light-emitting stage, the second light-emitting control sub-circuit 123 is turned off in response to the second light-emitting control signal EM2, so as to avoid current flowing through the light-emitting element 121 and causing the It emits light, which can improve the contrast ratio of the corresponding display device.
  • the second lighting control sub-circuit 124 can also be turned on in response to the second lighting control signal EM2, so that the reset circuit can be combined to perform a reset operation on the driving sub-circuit 122 and the light-emitting element 121.
  • the second lighting control signal EM2 may be the same as the first lighting control signal EM1, for example, the second lighting control signal EM2 may be connected to the same signal output terminal as the first lighting control signal EM, for example, the second lighting control signal EM2 may The first light emission control signal EM1 is transmitted through the same light emission control line.
  • the second lighting control signal EM2 may be different from the first lighting control signal EM1.
  • the second lighting control signal EM2 and the first lighting control signal EM1 may be respectively connected to different signal output terminals.
  • the second lighting control signal EM2 and the first lighting control signal EM1 may be respectively transmitted through different lighting control lines.
  • the first reset sub-circuit 125 includes a first terminal 125a, a second terminal 125b and a third terminal 125c, the first terminal 125a is configured to receive the first reset control signal Rst1, the second terminal 125b and the first reset voltage terminal Vinit1 connected, the third terminal 125c is connected to the control terminal 122a (first node N1) of the driving sub-circuit 122, the first reset sub-circuit 125 is configured to apply the first reset voltage Vinit1 to the driving sub-circuit 125 in response to the first reset control signal Rst1 The control terminal 122a of the sub-circuit 122.
  • the second reset sub-circuit 129 (an example of the reset sub-circuit of the present disclosure) includes a first terminal 129a, a second terminal 129b, and a third terminal 129c, the first terminal 129a being configured to receive the second reset control signal Rst2 (the present An example of the reset control signal is disclosed), the second terminal 129b is connected to the second reset voltage terminal Vinit1, the third terminal 129c is connected to the first terminal 122b (the fourth node N4) of the light-emitting element 122, the second reset sub-circuit The 129 is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light emitting element 121 in response to the second reset control signal Rst2.
  • the first reset subcircuit 125 and the second reset subcircuit 129 may be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 may be applied to the first node, respectively N1 and the first reset voltage Vinit1 are applied to the first terminal 134 of the light-emitting element 121, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting element 121 can be reset to eliminate the influence of the previous light-emitting stage.
  • the second reset control signal Rst2 of each row of sub-pixels may be the same signal as the first scan signal Ga1 of the row of sub-pixels.
  • the first reset control signal Rst1 of each row of sub-pixels may be the same as the first scan signal Ga1 or the second reset control signal Rst2 of the sub-pixels of the previous row.
  • the light-emitting element 121 includes a first end 134 and a second end 135, the first end 134 of the light-emitting element 121 is configured to be connected to the second end 122c of the driving sub-circuit 122, and the second end 135 of the light-emitting element 121 is configured to be connected to the second end 122c of the driving sub-circuit 122.
  • the two voltage terminals are connected to VSS.
  • the first end 134 of the light-emitting element 121 may be connected to the fourth node N4 through the second light-emitting control sub-circuit 124 .
  • Embodiments of the present disclosure include, but are not limited to, this situation.
  • the first node N1 , the second node N2 , the third node N3 and the fourth node N4 do not necessarily represent actual components, but represent related circuit connections in the circuit diagram. meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal.
  • the signal can also represent the first scan signal terminal and the second scan signal terminal, Rst can represent both the reset control terminal and the reset control signal, and the symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal.
  • the first reset voltage and the second reset voltage can be represented, the symbol VDD can represent both the first power supply voltage and the first power supply voltage terminal, and the symbol VSS can represent both the second power supply voltage terminal and the second power supply voltage.
  • FIG. 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5A .
  • the pixel circuit includes first to seventh transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 and includes a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving sub-circuit 122 may be implemented as the first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the first transistor T1 serves as the second terminal 122c of the driving sub-circuit 122, and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as the second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (the first scan signal terminal Ga1) to receive the first scan signal, and the first electrode of the second transistor T2 is connected to the data line (the data signal terminal Vd) to receive the data signal , the second pole of the second transistor T2 is connected to the first end 122b (the second node N2 ) of the driving sub-circuit 122 .
  • the compensation sub-circuit 128 may be implemented as a third transistor T3.
  • the gate, first and second electrodes of the third transistor T3 serve as the control electrode 128a, the first electrode 128b and the second electrode 128c of the compensation sub-circuit, respectively.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode T3s of the third transistor T3 and the second electrode T1d of the first transistor T1 ( The third node N3) is connected, and the second electrode T3d of the third transistor T3 is electrically connected to the gate T1g (first node N1) of the first transistor T1.
  • the gate T1g first node N1
  • the storage sub-circuit 127 may be implemented as a storage capacitor Cst, the storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb, the first capacitor electrode Ca and the first power supply voltage terminal VDD are electrically
  • the second capacitor electrode Cb is electrically connected to the gate T1g (first node N1) of the first transistor T1.
  • the first light emission control sub-circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first light-emitting control line (the first light-emitting control terminal EM1 ) to receive the first light-emitting control signal, and the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, the second pole of the fourth transistor T4 is connected to the first terminal 122b (the second node N2 ) of the driving sub-circuit 122 .
  • the light emitting element 121 is embodied as a light emitting diode (LED), such as an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or an inorganic light emitting diode, such as a micro light emitting diode (Micro LED) or a micro OLED.
  • LED light emitting diode
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • an inorganic light emitting diode such as a micro light emitting diode (Micro LED) or a micro OLED.
  • the light emitting element 121 may be a top emission structure, a bottom emission structure, or a double-sided emission junction.
  • the light emitting element 121 can emit red light, green light, blue light or white light, etc.
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first electrode 134 (eg, the anode) of the light-emitting element 121 and the fourth node N4 are configured to be connected to the second terminal 122 c of the driving sub-circuit 122 through the second light-emitting control sub-circuit 124
  • the second electrode of the light-emitting element 121 135 eg, a cathode
  • the circuit flowing into the light-emitting element 121 from the second terminal 122c of the driving sub-circuit 122 determines the brightness of the light-emitting element.
  • the second power supply voltage terminal VSS may be grounded, that is, VSS may be 0V.
  • the second power supply voltage VSS may be a negative voltage.
  • the second lighting control sub-circuit 124 may be implemented as the fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second light-emitting control line (the second light-emitting control terminal EM2) to receive the second light-emitting control signal.
  • the three nodes N3) are connected, and the second pole of the fifth transistor T5 is connected to the first end 134 (fourth node N4) of the light emitting element 121.
  • the first reset subcircuit 125 may be implemented as the sixth transistor T6, and the second reset subcircuit may be implemented as the seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, and the first pole of the sixth transistor T6 to be connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1,
  • the second pole of the sixth transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, and the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2,
  • the second pole of the seventh transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are used as examples for description in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltages)
  • the turn-off voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (eg, 0V, -5V, -10V or other suitable voltages) voltage).
  • the first to seventh transistors T1 - T7 are all P-type transistors, such as low temperature polysilicon thin film transistors.
  • the embodiment of the present disclosure does not limit the type of the transistor, and when the type of the transistor changes, the connection relationship in the circuit can be adjusted accordingly.
  • the display process of each frame of image includes three stages, which are initialization stage 1 , data writing and compensation stage 2 , and light-emitting stage 3 .
  • the first scan signal Ga1 and the second scan signal Ga2 use the same signal
  • the first light emission control signal EM1 and the second light emission control signal EM2 use the same signal
  • the waveforms of Rst2 and the first scan signal Ga1/second scan signal Ga2 are the same, that is, the second reset control signal Rst2, the first scan signal Ga1/second scan signal Ga2 can use the same signal
  • the signal Rst1 has the same waveform as the first scanning signal Ga1/second scanning signal Ga2 of the sub-pixels in the previous row, that is, the same signal is used.
  • this is not a limitation of the present disclosure.
  • different signals may be used as the first scan signal Ga1, the second scan signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, respectively.
  • Different signals are used as the first lighting control signal EM1 and the second lighting control signal EM2 respectively.
  • the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.
  • the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vd is written into the second node by the second transistor T2 N2, and charges the first node N1 through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth when the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1.
  • the potential of the first node N1 is stored in the storage capacitor Cst and kept, that is to say, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to be used to provide grayscale during the subsequent light-emitting stage. Display data and compensate for the threshold voltage of the first transistor T1 itself.
  • the second reset control signal Rst2 may also be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4, thereby resetting the fourth node N4.
  • the reset of the fourth node N4 may also be performed in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. This embodiment of the present disclosure does not limit this.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5 and the first transistor T1, and the fifth transistor T5 applies a driving current to the OLED to emit light .
  • the value of the driving current Id flowing through the OLED can be obtained according to the following formula:
  • Vth represents the threshold voltage of the first transistor T1
  • VGS represents the voltage between the gate and the source (here, the first electrode) of the first transistor T1
  • K is a voltage related to the first transistor T1 itself. constant value.
  • the voltage bus 210 is used as a reset voltage bus and is configured to be connected with the reset sub-circuits of the sub-pixels in the first pixel row to provide the reset voltage as an example to illustrate the display substrate provided by the embodiment of the present disclosure.
  • the present disclosure will The embodiment does not limit this.
  • the first voltage line 211 or the second voltage line 212 is respectively configured to be connected to the first end of the second reset sub-circuit in the sub-pixels in the first pixel row to provide the second reset voltage Vinit2.
  • the first reset voltage Vinit1 and the second reset voltage Vinit2 are the same voltage
  • the reset voltage line 210 is configured to respectively provide the first reset voltage Vinit1 for the first reset sub-circuit in the sub-pixels in the first pixel row and for the first reset sub-circuit
  • the second reset subcircuit in the subpixels in a pixel row provides the second reset voltage Vinit2.
  • the embodiments of the present disclosure are not limited thereto.
  • the following takes the pixel circuit shown in FIG. 5B as an example, and in conjunction with FIGS. 6A-6C , 7 , 5 , 6A-6C , 7 , 8A-8C and 9 , the display substrate provided by at least one embodiment of the present disclosure is described below.
  • the structure is exemplified.
  • FIG. 6A shows a schematic diagram of a pixel circuit 100 of a sub-pixel of a display substrate 20 provided by at least one embodiment of the present disclosure
  • FIG. 6B shows a cross-sectional view of FIG. 1A along a section line II-II'
  • FIG. 6C shows a 1A is a cross-sectional view along the section line III-III', and some structures that do not have a direct electrical connection relationship at the section line are omitted in Figures 6B and 6C
  • Figure 4 and Figure 6A correspondingly show the section lines II-II' and The position of III-III', that is, Fig. 6B also shows the cross-sectional view of Fig. 4 and Fig. 6A along the section line II-II'
  • Fig. 6C also shows the cross-sectional view of Fig. 4 and Fig. 6A along the section line III-III'. sectional view.
  • the display substrate 20 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a Three insulating layers 303 and a third conductive layer 203 .
  • FIG. 7 schematically shows the semiconductors of the transistors T1-T7 in the four adjacent pixel circuits in the first direction D1.
  • FIG. 8A shows the second conductive layer 202 corresponding to FIG. 6A, and
  • FIG. 8B shows the semiconductor layer 107, the first conductive layer 201 and the second conductive layer corresponding to FIG. 6A layer 202;
  • FIG. 9 shows a third conductive layer 203 corresponding to FIG. 6A.
  • Tng, Tns, and Tnd are used to represent the gate, the first pole, and the second pole of the nth transistor Tn, respectively, where n is 1-7.
  • the “same layer arrangement” referred to in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Can be the same or different.
  • the “integrated structure” in the present disclosure refers to a structure in which two (or more than two) structures are connected to each other by patterning the same film layer through the same patterning process, and their materials may be the same or different.
  • the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines.
  • the region where each pixel circuit is located is shown by a large dashed box, and the gates T1g-T7g of the first to seventh transistors T1-T7 in one pixel circuit are shown by a small dashed box.
  • the semiconductor layer 107 includes active layers T1a-T7a of the first to seventh transistors T1-T7. As shown in FIG. 7, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other in an integrated structure. For example, the semiconductor layer 107 in each column of sub-pixels is an integral structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.
  • the first conductive layer 201 includes gates T1g-T7g of the first to seventh transistors T1-T7.
  • the display substrate 20 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to conduct conductorization treatment (eg, doping treatment) on the semiconductor layer 107, so that the semiconductor layer 107 is not covered by the first conductive layer 201.
  • the covered portion is conductorized, so that portions of the active layer of each transistor located on both sides of the channel region are conductorized to form the first and second electrodes of the transistor, respectively.
  • the first conductive layer 201 further includes a plurality of scan lines 310 , a plurality of reset control lines 320 and a plurality of light emission control lines 330 which are insulated from each other.
  • each row of sub-pixels is respectively connected to one scan line 310 , one reset control line 320 and one light emission control line 330 .
  • the scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or an integrated structure) to provide the first scan signal Ga1, and the reset control line 320 is connected to the sixth transistor in the corresponding row of sub-pixels.
  • the gate of T6 is electrically connected to provide the first reset control signal Rst1
  • the emission control line 330 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the gate of the seventh transistor T7 of the pixel circuit of the current row is connected to the pixel circuit row of the pixel circuit of the next row of pixel circuits (that is, according to the scanning sequence of the scan lines, the row of pixel circuits where the scan lines that are sequentially turned on after the scan lines of the current row are located).
  • the reset control line 320 is electrically connected to receive the second reset control signal Rst2.
  • the first scan signal Ga1 and the second reset control signal Rst2 may be the same signal. Therefore, the scan line 310 correspondingly connected to the pixel circuit in the current row may be connected to the same signal line 320 corresponding to the reset control line 320 connected to the pixel circuit in the next row. line or the same signal terminal, which will be described in detail later.
  • the scan line 310 is also electrically connected to the gate of the third transistor T3 to provide the second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 may be the same signal; the light emission
  • the control line 330 is also electrically connected to the gate of the fifth transistor T5 to provide the second lighting control signal EM2, that is, the first lighting control signal EM1 and the second lighting control signal EM2 are the same signal.
  • the second conductive layer 202 includes a first capacitor electrode Ca.
  • the first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in the direction perpendicular to the base substrate 200 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the third gate of the storage capacitor Cst Two capacitor electrodes Cb.
  • the first capacitor electrode Ca includes an opening 221, and the opening 221 exposes at least part of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.
  • the second conductive layer 202 may further include a plurality of reset voltage lines 340 extending along the first direction D1, and the plurality of reset voltage lines 340 are connected to the plurality of rows of sub-pixels in a one-to-one correspondence.
  • the reset voltage line 340 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1.
  • the first electrode of the seventh transistor T7 in the sub-pixels in the current row is electrically connected to the reset voltage line 340 corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2 . This will be described in detail later.
  • the second conductive layer 202 may further include a shield electrode 224 .
  • the shielding electrode 224 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 200 so as to protect the signal in the first electrode T2s of the second transistor T2 from being interfered by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display gray scale of the sub-pixel, the shielding electrode 224 improves the stability of the data signal, thereby improving the display performance.
  • the shielding electrode 224 also at least partially overlaps the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the base substrate 200, so as to improve the signal in the second electrode T6d The stability of the sixth transistor T6 is improved, and the gate voltage of the first transistor T1 is further stabilized.
  • the shielding electrode 224 includes a portion 224 a that also extends to the adjacent pixel circuit, and the portion 224 a is perpendicular to the base substrate 200 with the active layer of the third transistor T3 in the adjacent pixel circuit. At least partially overlap in the direction of , so as to improve the stability of the third transistor T3, and further stabilize the gate voltage of the first transistor T1.
  • the shield electrode 224 is configured to be loaded with a fixed voltage; for example, the shield electrode 224 is electrically connected to a power supply line in the third conductive layer to load the pixel power supply voltage VDD, which will be described in detail later with reference to FIGS. 7 and 3 . .
  • the third conductive layer 203 includes a plurality of power lines 270 extending along the second direction D2.
  • the plurality of power supply lines 210 are electrically connected to the plurality of columns of pixel circuits in one-to-one correspondence to provide the first power supply voltage VDD.
  • the power supply line 210 is electrically connected to the first capacitor electrode Ca in the corresponding column of pixel circuits 100 through the via hole 341 , and the power supply line 270 is also connected to the first electrode T4s of the fourth transistor T4 through the via hole 343 .
  • Electrical connection; the power line 270 is also electrically connected to the shielding electrode 224 through the via hole 344, so that the shielding electrode 224 has a fixed potential and the shielding ability of the shielding electrode is improved.
  • the via hole 341 and the via hole 344 both penetrate the third insulating layer 303
  • the via hole 343 penetrates the first insulating layer 301 , the second insulating layer 302 and the third insulating layer 303 .
  • the third conductive layer 303 further includes a plurality of data lines 260 extending along the second direction D2 , for example, the plurality of data lines 260 are electrically connected to the sub-pixels in a one-to-one correspondence.
  • the data line 260 is electrically connected to the first electrode T2s of the second transistor T2 through the via hole 354 .
  • the third conductive layer 203 further includes a connection electrode 231, and one end of the connection electrode 231 is connected to the connection electrode 231 through the opening 221 in the first capacitor electrode Ca and the via hole 346 in the insulating layer.
  • the gate T1g of the first transistor T1, that is, the second capacitor electrode Cb, is electrically connected, and the other end is electrically connected to the second electrode T3d of the third transistor T3 through the via hole 347, so that the second capacitor electrode Cb is electrically connected to the third transistor T3.
  • the second pole T3d of the transistor T3 is electrically connected.
  • the via hole 346 penetrates through the second insulating layer 302 and the third insulating layer 303 .
  • the via hole 347 penetrates through the first insulating layer 301 , the second insulating layer 302 and the third insulating layer 303 .
  • the third conductive layer 203 further includes a connection electrode 232, the connection electrode 232 is electrically connected to the second electrode T5d of the fifth transistor T5 through the via hole 348, and is used to connect the second electrode T5d of the fifth transistor T5.
  • the second electrode T5d of the five transistors T5 is electrically connected to the first electrode 134 of the light-emitting element.
  • the via hole 348 penetrates through the first insulating layer 301 , the second insulating layer 302 and the third insulating layer 303 .
  • the third conductive layer 203 further includes a connection electrode 233, one end of the connection electrode 233 is electrically connected to the reset voltage line 340 through the via hole 351, and the other end is electrically connected to the sixth via hole 352.
  • the first pole T6s of the transistor T6 is electrically connected so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 340 .
  • the via hole 351 penetrates through the third insulating layer 303 .
  • the via hole 352 penetrates through the first insulating layer 301 , the second insulating layer 302 and the third insulating layer 303 .
  • the first pole of the seventh transistor T7 in the sub-pixels in the previous row is electrically connected to the reset voltage line 340 corresponding to the sub-pixels in this row to receive the second reset voltage Vinit2,
  • the first pole of the seventh transistor T7 is electrically connected to the reset voltage line 340 corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2; that is, the first reset sub-circuit of the current row (that is, the sixth transistor T6 )
  • the reset voltage is received through the same reset voltage line 340 as the second reset sub-circuit (ie, the seventh transistor T7 ) of the previous row.
  • the display substrate 20 may further include a fourth insulating layer 304 and a fourth conductive layer 204 that are sequentially located on the third conductive layer 203 .
  • the fifth conductive layer 205 includes the first electrode 134 of the light emitting element 121 .
  • the display substrate 20 further includes a connection electrode 234 located in the third conductive layer 203 , and the connection electrode 234 is located in the peripheral region 23 .
  • the fourth conductive layer 204 also includes the voltage bus 210 .
  • the connection electrode 234 is electrically connected to the reset voltage line 340 through the via hole 353, and is electrically connected to the voltage bus 210 through the via hole 354, so as to electrically connect the reset voltage line 340 to the voltage bus 210; that is, in the first display In the area A1 or the second display area A2, the reset voltage line 340 is separated into two parts, and the two parts are the first voltage line 211 in the first display area A1 and the second voltage line 212 in the second display area A2 respectively. Two parts of the reset voltage line 340 are electrically connected to the voltage bus 210, respectively. For example, in the third display area A3 and the fourth display area A4, the reset voltage line 340 extends continuously in one row.
  • the fourth conductive layer 204 is mainly used to form the first electrode of the light-emitting element, and the wiring density is low, arranging the voltage bus 210 on the fourth conductive layer can facilitate wiring.
  • the display substrate 20 may further include a pixel defining layer 306 on a side of the first electrode 134 of the light-emitting element away from the base substrate 200 . Openings are formed in the pixel defining layer 306 to expose at least part of the first electrodes 134 so as to define opening regions (ie, light emitting regions) 600 of the respective sub-pixels of the display substrate.
  • the light-emitting layer 136 of the light-emitting element 121 is formed at least in the opening (the light-emitting layer 136 may also cover part of the surface of the pixel defining layer on the side away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form The light-emitting element 121 .
  • the second electrode 135 is a common electrode, and the entire surface is arranged in the display substrate 20 .
  • the first electrode 134 is the anode of the light-emitting element
  • the second electrode 135 is the cathode of the light-emitting element.
  • the base substrate 200 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC) ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET) ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetate cellulose (TAC), cyclic olefin polymers (COP) and cyclic olefin copolymers (COC) etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • PET polyacrylate
  • polyarylate polyetherimide
  • PES polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • the materials of the semiconductor layer 107 include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, etc.) , polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, etc.
  • materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and the above Alloy material composed of metals; or transparent conductive metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the light-emitting element 121 has a top emission structure, the first electrode 134 is reflective and the second electrode 135 is transmissive or semi-transmissive.
  • the first electrode 134 is a high work function material to act as an anode, such as an ITO/Ag/ITO stack structure;
  • the second electrode 135 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303 are inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrides. Oxides, or aluminum oxide, titanium nitride, etc., include metal oxynitride insulating materials.
  • the fourth insulating layer 304 and the pixel defining layer 306 may be organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • the fourth insulating layer 304 is a planarization layer. This embodiment of the present disclosure does not limit this.
  • the portion of the first signal line 31 located in the display area, that is, the first signal line sub-section 318 and the second signal line sub-section 319 are the scan lines 310 .
  • the part of the second signal line 32 located in the display area that is, the first signal line sub-section 321 or the second signal line sub-section 322 is the above-mentioned power line 270, that is, the second signal line is configured to provide the first Supply voltage VDD.
  • the part of the third signal line 33 located in the display area that is, the first signal line sub-section 331 or the second signal line sub-section 332 is located in the above-mentioned data line 260, that is, the third signal line is configured to provide data signals Vd.
  • the second signal line 21 and the third signal line 33 are both located in the third conductive layer 203 and insulated from each other.
  • the first signal line sub-section 318 and the second signal line sub-section 319 are respectively connected with the control terminal (ie the gate T2g of the second transistor T2 ) and the compensation sub-circuit of the data writing sub-circuit of the corresponding row of sub-pixels.
  • the control terminal of the sub-circuit ie, the gate T3g of the third transistor T3 is electrically connected.
  • the first signal line sub-section 318 and the second signal line sub-section 319 are respectively associated with the control terminal (ie the gate T2g of the second transistor T2 ) and the compensation sub-circuit of the data writing sub-circuit of the corresponding row of sub-pixels.
  • the control terminal of the sub-circuit ie, the gate T3g of the third transistor T3 is electrically connected.
  • the first signal line sub-section 318 and the second signal line sub-section 319 of the first signal line 31 are both located in the first conductive layer 201 and located with the second signal line part 31b different layers.
  • the first signal line sub-section 318 and the second signal line sub-section 319 are located on the side of the second signal line portion 31b close to the base substrate 200 .
  • the first signal line sub-section 318 and the second signal line sub-section 319 are configured as the scan lines of the display area, for example, they are integrally formed with the gates of the transistors in the display area, and the gate process affects the channel width to length ratio of the transistors, so The adjustment of the gate process has a great influence on the performance of the transistor.
  • the process adjustment of the second signal line portion 31b can be made more flexible. The adjustment of the process of the signal line portion 31 b does not affect the processes of the first signal line sub-section 318 and the second signal line sub-section 319 .
  • the scan lines 310 are formed continuously.
  • the process parameters of the first signal line sub-section 318 and the second signal line sub-section 319 are consistent with the process parameters of the scan lines 310 in the third display area A3 and the fourth display area A4.
  • the second signal line portion 31 b is located in the second conductive layer 202 , that is, the same layer as the reset voltage line 340 is insulated and provided.
  • the display substrate 20 further includes a connection electrode 235 (an example of the first connection electrode of the present disclosure), which is located in the third conductive layer 203 , for example.
  • the connection electrode 235 is electrically connected to the first signal line sub-portion 318 or the second signal line sub-portion 319 (that is, the scan line 310 ) of the first signal line 31 through a via hole 355 (an example of the first via hole in the present disclosure).
  • a via hole 355 an example of the first via hole in the present disclosure
  • the second signal line portion 31 b the first extension portion 311 in FIG. 4
  • the first signal line 31 through the via hole 356 (an example of the second via hole of the present disclosure).
  • the first signal line portion 31 a and the second signal line portion 31 b are connected by arranging the connection electrode 235 , that is, the first signal line portion 31 a and the second signal line portion 31 b are not directly electrically connected through the via hole penetrating the second insulating layer 302 . connection, thereby saving a patterning process for the second insulating layer 302 .
  • the vias 355 and 356 are located on the side of the voltage bus 210 away from the transparent area 22 , that is, on the side close to the display area 21 , and are arranged side by side in the second direction D2 .
  • the voltage bus 210 is located on the side of the bent portion 313 of the second signal line portion 31b away from the transparent region 22 , and the voltage bus 210 and the first extension 311 of the second signal line portion 31b are perpendicular to the substrate. It overlaps in the direction of the base substrate and does not overlap with the bent portion 313 of the second signal line portion 31b in the direction perpendicular to the base substrate. This arrangement enables the voltage bus 210 to avoid the wire-intensive winding area, which facilitates the electrical connection between the voltage bus 210 and the first voltage line 211 or the second voltage line 212 .
  • the display substrate further includes a connection electrode 236 located in the third conductive layer 203 , and the display substrate further includes a signal line sub-section 316 located in the peripheral region 23 (the fourth signal line sub-section of the present disclosure).
  • the connection electrode 236 is located on the side of the signal line sub-section 316 away from the transparent area, and is used for connecting the signal line sub-section 316 with the reset control line 320 in the display area (one of the third signal line sub-section of the present disclosure). Example) electrical connection.
  • the signal line sub-section 316 is located in the third conductive layer 203 , and the connection electrode 236 has a similar effect as the connection electrode 235 , which can save a patterning process for the second insulating layer 302 .
  • the connection electrode 236 partially overlaps the voltage bus 210 in a direction perpendicular to the base substrate.
  • the reset control line 320 and the signal line sub-section 316 in the display area are not arranged in the same layer, which can facilitate the adjustment of the process of the signal line sub-section 316 without affecting the process of the transistors in the display area.
  • the scanning signal Ga1/Ga2 received by the pixel circuit of the current row and the second reset control signal Rst2 received by the pixel circuit of the current row may be the same signal, and the first reset signal is correspondingly connected to the pixel circuit of the next row.
  • the control signal Rst1 is the same signal. Therefore, the scan line 320 corresponding to the pixel circuit in this row is connected to the reset control line 320 corresponding to the second reset sub-circuit in this row (that is, the corresponding connection of the first reset sub-circuit in the next row).
  • the reset control line 320) is connected to the same signal terminal.
  • the scan line 310 ie, the first signal line sub-section 318 or the second signal line sub-section 319 ) correspondingly connected to the pixel circuit of this row is correspondingly connected to the second reset sub-circuit
  • the reset control line 320 is connected to the same winding (ie, the bent portion 313 ), that is, the two share one winding, which can reduce the winding density in the peripheral region 23 and improve the process yield. As shown in FIG.
  • the scan line 310 is connected to the bent portion 313 via the first extension portion 311 of the second signal line portion 31b
  • the reset control line 320 is connected to the bent portion 313 via the signal line sub-portion 316, that is, One end of the signal line sub-portion 316 is electrically connected to the reset control line 320 , and the other end is electrically connected to the corresponding bending portion 313 .
  • the signal line sub-portion 316 is disposed in parallel with the first extension portion 311 and is directly electrically connected to the bending portion 313 .
  • the bent portion 313 includes portions located at the connection point C1 and the connection point C2.
  • the display substrate 20 includes a plurality of signal line sub-sections 316 extending along the first direction D1, and the plurality of signal line sub-sections 316 are respectively electrically connected to the plurality of reset control lines 320 corresponding to the plurality of first pixel rows in one-to-one correspondence.
  • each signal line subsection 316 overlaps the voltage bus 210 in a direction perpendicular to the base substrate.
  • the second signal line 32 (power line 270 ) and the third signal line 33 (data line 260 ) connected to the same sub-pixel are directly adjacent in the second direction D2 and form a pair settings.
  • the plurality of second signal lines 32 and the plurality of third signal lines 33 are alternately arranged in the first direction.
  • the average line width of the first signal line portion of the second signal line 32 is greater than the average line width of the second signal line portion of the second signal line 31 ; that is, the second signal line 32 runs from the display area to the peripheral area. Narrow design.
  • the average line width of the first signal line portion of the second signal line 32 is greater than the average line width of the second signal line sub-section 322 of the second signal line portion.
  • Designing the second signal line 32 wider in the display area helps to reduce the resistance of the second signal line 32, thereby reducing the voltage drop of the power supply voltage on the second signal line 32, thereby improving the display uniformity; and
  • the line width of the second signal line portion of the second signal line is designed to be narrower when the wiring is performed in the peripheral area.
  • the average line width of the second signal line sub-section 322 of the second signal line part of the second signal line is the same as the average line width of the second signal line sub-section 332 of the second signal line part of the third signal line, thereby reducing the difficulty of the process .
  • the display substrate further includes a dummy electrode 220 , and the dummy electrode 220 is a floating electrode, that is, no electrical signal is loaded.
  • the dummy electrode 220 is disposed around the transparent area 22 and is closest to the transparent area 22 compared to other wires, that is, the side of the dummy electrode close to the transparent area 22 is not provided with traces, or the dummy electrode is The conductive structures in the peripheral region 23 that are closest to the transparent region 22 .
  • the dummy electrode 220 can shield the interference of the photoelectric signals in the transparent area 22 to the electric signals on the signal lines in the display area 21 and the peripheral area 23 .
  • the transparent region 22 is configured to allow light from the display side of the display substrate to be transmitted to the opposite side of the display side for sensing, eg the light is visible light or infrared light; the dummy electrode 220 can shield the light passing through the transparent The light from the region 22 interferes with the electrical signal outside the dummy electrode.
  • the dummy electrode may be annular, all surrounding the transparent region 22 .
  • the dummy electrode 220 can be located in the third conductive layer 203. Since the data line 260 is located in the third conductive layer, the dummy electrode 220 is located in the third conductive layer 203, which can shorten the distance between the dummy electrode 220 and the data line 260, The data signals in the data lines 260 are protected from interference. However, the embodiments of the present disclosure do not limit this. In other examples, the dummy electrode 220 may also be located in the second conductive layer 202 or the fourth conductive layer 204 .
  • the above-mentioned first to fourth insulating layers can be fully or partially retained in the transparent area 22, and the thickness of the insulating layer in the transparent area can be adjusted by adjusting the thickness of the insulating layer in the transparent area 22.
  • the optical path of the light which can be adjusted according to actual needs.
  • FIG. 10A shows a schematic structural diagram of a display device 40 according to some embodiments of the present disclosure
  • FIG. 10B is a cross-sectional view of FIG. 10A along IV-IV'.
  • the sensor 401 is correspondingly disposed in the third display area 23 of the display substrate 20 and disposed on the side of the display substrate opposite to the display side, for example, disposed on the side of the base substrate 200 away from the light-emitting element .
  • the sensor 401 is, for example, a photosensor configured to receive light from the first side of the display substrate and convert the light into electrical signals for forming an image.
  • the light reaches the sensor from the display side through the transparent area 22, for example, the light is visible light or infrared light.
  • the display device 40 further includes an encapsulation layer 207 and a cover plate 208 disposed on the display substrate 20, and the encapsulation 207 is configured to seal the light-emitting element in the display substrate 20 to prevent external moisture and oxygen from entering the light-emitting element And the penetration of the drive circuit will cause damage to the device.
  • the encapsulation layer 207 includes an organic thin film or a structure in which organic thin films and inorganic thin films are alternately stacked.
  • a water absorption layer (not shown) may also be disposed between the encapsulation layer 207 and the display substrate 20, and is configured to absorb water vapor or sol remaining in the pre-fabrication process of the light-emitting element.
  • the cover plate 208 is, for example, a glass cover plate.
  • the cover plate 208 and the encapsulation layer 207 may be an integral structure.
  • the senor 401 may be attached to the back surface (the side opposite to the display surface) of the display substrate 20 .
  • the imaging element 401 is attached to the side of the base substrate 200 away from the second electrode 135 of the light-emitting element.
  • the sensor 401 can be implemented as a camera, for example.
  • the display device can be a product or component with any display function, such as a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a monitor, a notebook computer, a navigator, and the like.

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Abstract

一种显示基板(20)及显示装置(40)。显示基板(20)包括显示区(21)、透明区(22)以及位于显示区(21)和透明区(22)之间的周边区(23)，显示基板(20)还包括位于周边区(23)的电压总线(210)，电压总线(210)至少部分环绕透明区(22)，并配置为与多个像素行中的子像素连接以提供第一电压；显示基板(20)还包括沿第一方向(D1)延伸的多条第一信号线(31)，多条第一信号线(31)的每条包括位于显示区(21)的第一信号线部分(31a)和位于周边区(23)的第二信号线部分(31b)，第一信号线部分(31a)和第二信号线部分(31b)彼此电连接，第二信号线部分(31b)包括沿透明区(22)延伸的弯折部(313)，多条第一信号线(31)的第二信号线部分(31b)的弯折部(313)均位于电压总线(210)靠近透明区(22)的一侧。显示基板(20)可以优化布线。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
目前，显示器件的显示屏正往大屏化、全屏化方向发展。通常，显示器件(例如手机、平板电脑等)具有摄像装置(或成像装置)，该摄像装置通常设置在显示屏显示区域外的一侧。但是，由于摄像装置的安装需要一定的位置，因此不利于显示屏的全屏化、窄边框设计。例如，可以将摄像装置与显示屏的显示区域结合在一起，在显示区域中为摄像装置预留位置，以获得显示屏显示区域的最大化。
发明内容
本公开至少一实施例提供一种显示基板，包括显示区和透明区，所述显示基板包括衬底基板以及位于所述衬底基板上且位于所述显示区的多个子像素，所述多个子像素沿第一方向和第二方向分布为多个像素行和多个像素列，所述第一方向和所述第二方向不同；所述多个像素行包括被所述透明区间隔的多个第一像素行；所述显示基板还包括电压总线，所述电压总线位于所述周边区，所述电压总线至少部分环绕所述透明区，并配置为与所述多个第一像素行中的子像素连接以提供第一电压；所述显示基板还包括沿所述第一方向延伸的多条第一信号线，所述多条第一信号线分别与所述多个第一像素行的子像素一一对应连接；所述多条第一信号线的每条包括位于所述显示区的第一信号线部分和位于所述周边区的第二信号线部分，所述第一信号线部分和所述第二信号线部分彼此电连接，所述第二信号线部分包括沿所述透明区延伸的弯折部，所述多条第一信号线的第二信号线部分的弯折部均位于所述电压总线靠近所述透明区的一侧。
在一些示例中，所述显示区包括被所述透明区间隔且在所述第一方向上相对的第一显示区和第二显示区，所述多个像素行包括被所述透明区间隔的多个第一像素行，所述多个第一像素行中的子像素被所述透明区间隔在所述第一显示区和所述第二显示区；所述显示基板还包括沿所述第一方向延伸的多条第一 电压线和多条第二电压线，所述多条第一电压线和所述多条第二电压线均与所述电压总线电连接；所述多条第一电压线位于所述第一显示区，并分别与所述多个第一像素行中位于所述第一显示区的多行子像素连接以提供所述第一电压；所述多条第二电压线位于所述第二显示区，并分别与所述多个第一像素行中位于所述第二显示区的多行子像素连接以提供所述第一电压。
在一些示例中，所述多个子像素的每个包括发光元件和驱动所述发光元件发光的像素电路；所述像素电路包括驱动子电路、数据写入子电路、补偿子电路、存储子电路和复位子电路；所述驱动子电路包括控制端、第一端和第二端，且配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；所述数据写入子电路与所述驱动子电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动子电路的第一端；所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；所述存储子电路包括第一端和第二端，所述存储子电路的第一端配置为接收第一电源电压，所述存储子电路的第二端与所述驱动子电路的控制端电连接；所述复位子电路包括控制端、第一端和第二端，所述复位子电路的控制端配置为接收复位控制信号，所述复位子电路的第一端与相应的第一电压线或第二电压线连接以接收所述第一电压，所述复位子电路的第二端与所述发光元件连接。
在一些示例中，所述发光元件包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的发光层，所述第一电极相较于所述发光层更靠近所述衬底基板，所述电压总线与所述发光元件的第一电极同层绝缘设置。
在一些示例中，所述存储子电路包括存储电容，所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极和所述第二电容电极分别作为所述存储子电路的第一端和第二端；所述第二电容电极位于第一电容电极靠近衬底基板的一侧，所述第一电压线和所述第二电压线均与存储电容的第一电容电极同层绝缘设置，并位于所述电压总线靠近所述衬底基板的一侧。
在一些示例中，所述多条第一信号线分别与所述多个第一像素行的子像素的数据写入子电路一一对应连接以提供所述第一扫描信号；所述多条第一信号线的第一信号线部分每条包括位于所述第一显示区的第一信号线子部和位于所述第二显示区的第二信号线子部，所述每条第一信号线的第二信号线部分将 所述第一信号线子部和所述第二信号线子部电连接；所述每条第一信号线的第一信号线子部和所述第二信号线子部均沿所述第一方向延伸，所述第一信号线子部与所述第一信号线所对应的第一像素行中位于所述第一显示区的子像素连接，所述第二信号线子部与所述第一信号线所对应的第一像素行中位于所述第二显示区的子像素连接。
在一些示例中，所述第一信号线的第一信号线子部和第二信号线子部同层设置，并位于所述第一信号线的第二信号线部分靠近所述衬底基板的一侧。
在一些示例中，所述显示基板还包括第一连接电极，所述多个第一连接电极位于所述多条第一信号线的第二信号线部分远离所述衬底基板的一侧；所述多条第一信号线的每条的第一信号线子部和第二信号线部分分别通过所述第一连接电极电连接；所述第一连接电极通过第一过孔与所对应的第一信号线的第一信号线子部电连接，并通过第二过孔与所对应的第一信号线的第二信号线部分电连接。
在一些示例中，所述第一过孔和所述第二过孔均位于所述电压总线远离所述透明区的一侧，并在所述第二方向上并列排布。
在一些示例中，所述第一信号线的第二信号线部分还包括位于所述弯折部两侧并与所述弯折部电连接的第一延伸部和第二延伸部；所述第一延伸部和所述第二延伸部均沿所述第一方向延伸，并分别与所述第一信号线子部和所述第二信号线子部电连接。
在一些示例中，所述电压总线与第一信号线的第二信号线部分的第一延伸部和第二延伸部在垂直于所述衬底基板的方向上重叠，并与所述弯折部在垂直于所述衬底基板的方向上不重叠。
在一些示例中，所述显示基板还包括位于所述第一显示区并沿所述第一方向延伸的多个第三信号线子部，所述多个第三信号线子部分别与所述多个第一像素行位于所述第一显示区中的多行子像素的复位子电路的控制端一一对应连接以提供所述复位控制信号；所述多个第三信号线子部中的每个和其所对应连接的一行子像素所对应连接的第一信号线彼此电连接；所述每个第三信号线子部与所对应的第一信号线的第一信号线子部同层设置。
在一些示例中，所述显示基板还包括位于所述周边区的多个第四信号线子部，所述多个第四信号线子部与所述多个第三信号线子部一一对应电连接，所述多个第四信号线子部的每个与所对应的第三信号线子部所对应连接的子像 素所连接的第一信号线的第二信号线部分的弯折部电连接。
在一些示例中，所述多个第四信号线子部的每个的一端与所对应的第三信号线子部电连接，另一端与所述弯折部电连接；在垂直于所述衬底基板的方向上，所述电压总线与所述多个第四信号线子部的每个均重叠。
在一些示例中，所述多条第一信号线的第一信号线部分与所述第一电容电极同层绝缘设置，所述多条第一信号线的第二信号线部分与所述第二电容电极同层绝缘设置。
在一些示例中，所述显示基板还包括沿所述第二方向延伸的多条第二信号线，所述多条第二信号线的每条包括位于所述显示区的第一信号线部分和位于所述周边区的第二信号线部分；所述每条第二信号线的第二信号线部分包括依次连接的第一信号线子部、第二信号线子部和第三信号线子部，所述每条第二信号线的第一信号线子部和第三信号线子部为直线型结构，所述每条第二信号线的第二信号线子部包括曲线型结构；所述多条第二信号线为电源线。
在一些示例中，所述显示基板还包括多个第二连接电极，其中，所述多个第二连接电极与所述多条第二信号线同层绝缘设置，所述多条第一电压线分别通过所述多个第二连接电极与所述电压总线电连接。
在一些示例中，所述显示基板还包括虚拟电极，所述虚拟电极至少部分围绕透明区设置且相较于其它导线最靠近所述透明区。
在一些示例中，所述显示基板还包括位于所述周边区的多个第一补偿电极，所述多个第一补偿电极分别与所述多条第一信号线一一对应设置；所述多个第一补偿电极位于所述多条第一信号线的第三信号线段远离所述衬底基板的一侧；所述多个第一补偿电极的每个与所对应的第一信号线的第二信号线部分的弯折部在垂直于所述衬底基板的方向上重叠以形成补偿电容；所述多个第一补偿电极位于所述电压总线靠近所述透明区的一侧。
本公开至少一实施例还提供一种显示装置，包括上述显示基板。
在一些示例中，所述显示装置还包括传感器，所述传感器设置于所述衬底基板远离所述多个子像素的一侧，且配置为接收并检测透过所述透明区的光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而 非对本公开的限制。
图1A是本公开至少一实施例提供的显示基板的示意图之一；
图1B是本公开至少一实施例提供的显示基板的示意图之二；
图1C是本公开至少一实施例提供的显示基板的示意图之三；
图2A为图1C中区域A的放大示意图；
图2B为图2A的局部放大示意图；
图2C为图2B沿剖面线I-I’的剖视图；
图3为本公开至少一实施例提供的显示基板的示意图之四；
图4为图1C中区域B的放大示意图；
图5A为本公开至少一实施例提供的像素电路的示意图；
图5B为图5A所示的像素电路的一种具体实现示例的电路图；
图5C为本公开至少一实施例提供的像素电路的时序信号图；
图6A为本公开至少一实施例提供的显示基板的示意图之五；
图6B为图1A沿剖面线II-II’的剖视图；
图6C为图1A沿剖面线III-III’的剖视图；
图7为本公开至少一实施例提供的显示基板的示意图之六；
图8A为本公开至少一实施例提供的显示基板的示意图之七；
图8B为本公开至少一实施例提供的显示基板的示意图之八；
图9为本公开至少一实施例提供的显示基板的示意图之九；
图10A为本公开至少一实施例提供的显示装置的示意图；以及
图10B为图10A沿剖面线IV-IV’的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的 组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
在集成有成像元件的显示装置中，将成像元件设置于显示装置的显示区，有助于提高显示屏占比，例如实现全面屏显示。由于显示区中制作有显示器件，会影响成像元件的光透过率，例如，子像素中的发光元件、不透光走线等都可能对成像元件摄取光线形成阻挡从而影响成像品质。例如，可以通过在设置有成像元件的显示区中不设置子像素以及信号线从而提高该区域的透光性，但是这种设置会影响该区域周边的信号线的连接和分布，还会使得一些像素行存在像素的缺失，也即位于不同行的子像素的数量不同，导致连接不同行子像素的信号线的负载不同，进而这些信号线传输信号的速度不同，造成显示不均。
图1A示出了本公开至少一实施例提供的显示基板的平面示意图。如图1A所示，该显示基板20包括显示区21和透明区22。该显示区21为设置子像素的区域，透明区22中并不设置子像素，例如该透明区22中不设置有像素电路，甚至不设置走线，从而透光率较高，近似透明。该显示基板还包括位于显示区21和透明区22之间的周边区23，该周边区23例如为围绕透明区22设置的环状区域。信号线在经过透明区22时会绕着该透明区22延伸以避免对该透明区进行遮挡，该周边区23中也不设置像素电路，该周边区23提供该透明区22周围绕线的空间。
该显示区21包括被该透明区22间隔且在第一方向D1上相对的第一显示区A1和第二显示区A2。例如，该透明区22位于该显示区21中，该显示区21还包括被该透明区22间隔且在第二方向D2上相对的第三显示区A3和第四显示区A4。在另一些示例中，该透明区22也可以在第二方向D2上位于显示区21的外侧，也即显示区21中存在一个凹状区域，该透明区22设置于该凹状区域中，本公开该透明区22与显示区21的相对位置关系不作限制。
该显示基板20包括位于显示区21中的多个子像素，该多个子像素沿第一方向D1和第二方向D2分别为多个像素行和多个像素列。该第一方向D1和第二方向D2不同，例如彼此正交。多个像素行包括被该透明区间隔的多个第一像素行，多个第一像素行中的子像素被该透明区22间隔在该第一显示区A1 和第二显示区A2，也即该第一显示区A1包括多行子像素，该第二显示区A2中在对应的像素行上也包括多行子像素。由于该透明区22的存在，该多个第一像素行中的子像素的数量比显示区21中除该第一显示区A1和第二显示区A2的区域(例如第三显示区A3和第四显示区A4)的一行子像素的子像素数量少。
图1A中省略了子像素，仅示意性地示出了一些信号线的分布。如图1A所示，为了提高透明区22的透光率，信号线在经过透明区22时会绕着该透明区22延伸以避免对该透明区进行遮挡。这种绕线使得透明区22周边的周边区23中布线较为密集，不仅对工艺要求较高而且对产品的良率造成了影响。
图1B示出了透明区以及周边区的放大示意图的一种示例。如图1B所示，该显示基板20还包括电压总线210，该电压总线210位于显示区21与透明区22之间的周边区23。该电压总线210至少部分环绕该透明区22设置，并配置为与多个第一像素行中的子像素连接以提供第一电压。例如，该第一电压可以是电源电压(VDD或VSS)或者复位电压(VINT)或其它固定电压信号；相应地，该电压总线210可以是电源电压总线或复位电压总线等。可以理解地，该多个第一像素行中的子像素由于与同一电压总线210连接因而接收相同的第一电压，而由于信号线上电压降的存在，不同位置的子像素所接收到的第一电压的数值可能存在差别，这并不作为对本公开的限制。
本公开实施例提供的显示基板通过设置电压总线210对被该透明区22间隔的多个像素行(也即第一像素行)中的子像素提供电压，不仅将位于同一第一像素行但分别位于第一显示区A1和第二显示区A2的子像素实现连通，从而使得位于同一第一像素行的子像素的负载相同(由于均与电压总线210连接)，提高了显示的均一性；此外，该电压总线210同时与多个第一像素行的子像素连接提供电压信号，简化了周边区的布线，从而对工艺进行了优化，并可以提高产品的良率。
例如，如图1B所示，该显示基板10还包括沿第一方向D1延伸的多条第一电压线211和多条第二电压线212，该多条第一电压线211和多条第二电压线212均与该电压总线210电连接。该多条第一电压线211位于所述第一显示区A1，并分别与多个第一像素行中位于第一显示区A1的多行子像素连接以提供第一电压。该多条第二电压线212位于第二显示区A2，并分别与多个第一像素行中位于第二显示区A2的多行子像素连接以提供该第一电压。
由于该电压总线210的存在，位于第一显示区A1的第一电压线211和位于第二显示区A2的第二电压线212不需要通过绕线实现电连接，而只需要在该电压总线的对应边与该电压总线进行电连接。
例如，如图1A-1B所示，该电压总线210为环状并全部包围该透明区22；在另一些示例中，该电压总线210也可以部分包围该透明区22或者为其它形状，只要该电压总线210可以与两侧的第一电压线211和第二电压线212电连接即可。
例如，如图1A-1B所示，该显示基板20还包括多条第一信号线31，多条第一信号线31分别与多个第一像素行的子像素一一对应连接以提供第一信号，该第一信号线31例如可以是扫描线或控制线，该第一信号例如可以是扫描信号或控制信号(例如复位控制信号或发光控制信号)。
每条第一信号线31包括位于显示区21的第一信号线部分31a和位于周边区23的第二信号线部分31b，该第一信号线部分31a和该第二信号线部分31b彼此电连接。
如图1A所示，该第一信号线部分31a包括位于第一显示区A1的第一信号线子部318以及位于第二显示区A2的第二信号线子部319，每条第一信号线31的第二信号线部分31b位于其第一信号线子部318与第二信号线子部319之间，并将该第一信号线子部318和第二信号线子部319电连接。
如图1B所示，该第一信号线子部318和第二信号线子部319均为直线型结构并沿第一方向D1延伸，该第一信号线子部318与其所属的第一信号线31所对应的第一像素行中位于第一显示区A1的子像素连接，第二信号线子部319与对应的第一像素行中位于第二显示区A2的子像素连接。
图1B仅示出了该第一信号线31的第二信号线部分31b，如图1B所示，该第二信号线部分31b包括沿该透明区22延伸的弯折部313。例如，该弯折部313为弧线状，绕透明区22延伸；例如，如图1B所示，该弯折部313为圆弧的一部分，然而这并不作为对本开的限制，在另一些示例中，该弯折部313可以包括分段连接且形状不同的多个部分。
如图1A和1B所示，多条第一信号线31的第二信号线部分31b中的弯折部313均位于该电压总线210靠近透明区22的一侧。这种设置使得电压总线210避开线路密集的绕线区域，便于电压总线210与第一电压线211或第二电压线212的电连接。
例如，如图1B所示，该第二信号线部分31b还包括位于弯折部313两侧的第一延伸部311和第二延伸部312，该第一延伸部311和第二延伸部312分别与该弯折部313的两端电连接。该第一延伸部311沿第一方向D1延伸至第一显示区A1并与对应的第一信号线子部318电连接，该第二延伸部312沿第一方向D1延伸至第二显示区A2并与对应的第二信号线子部319电连接。例如，该第一延伸部311和第二延伸部312均为直线型结构。
例如，由于该透明区22的存在，该多个第一像素行中的子像素的数量比显示区21中除该第一显示区A1和第二显示区A2的区域(例如第三显示区A3和第四显示区A4)的一行子像素的子像素数量少，与该第一像素行对应连接的信号线(如扫描线)的负载会小于位于第三显示区A3或第四显示区A4中与一个完整的像素行连接的信号线的负载。
例如，可以对于该第一信号线进行负载补偿，从而拉近其负载与其它信号线负载中的差距，例如使得其负载与其它信号线的负载基本相同。一种补偿方式是在该信号线上形成补偿电容，从而提高该信号线的阻容负载。例如，可以根据该第一信号线所对应的第一像素行所缺失的子像素的数目设计补偿电容的电容值。例如，可以选择该信号线的位于周边区的不与子像素直接连接的绕线部分形成该补偿电容。在图1B所示的情形，该第一信号线的弯折部整体为弧线状，不便于计算形成电容的电极面积，因此不便于进行补偿电容的设计。
本公开至少一实施例提供的显示基板，包括沿所述第一方向延伸的第一信号线；所述第一信号线包括位于所述显示区的第一信号线部分和位于所述周边区的第二信号线部分，所述第一信号线部分和所述第二信号线部分彼此电连接；所述第一信号线的第二信号线部分包括依次连接的第一子部、第二子部和第三子部，所述第一子部和所述第三子部均包括曲线型结构，所述第二子部为直线型结构；所述显示基板还包括位于所述周边区的第一补偿电极，所述第一补偿电极与所述第一信号线的第二信号线部分的第二子部在垂直于所述衬底基板的方向上至少部分重叠以形成补偿电容。
本公开实施例提供的显示基板通过在该第一信号线的绕线部分设计直线结构，从而便于设计补偿电容的电容值。
图1C示出了图1A透明区以及周边区的放大示意图的另一种示例。如图1C所示，显示基板20包括位于显示区21与透明区22之间的第一补偿区231，例如，该第一补偿区23为该周边区23的一部分。例如，第一信号线31的第 二信号线部分31b的弯折部313包括依次连接的第一子部313a、第二子部313b和第三子部313c，也即该第二子部313b位于该第一子部313a和第三子部313c之间并将二者电连接。该第一子部313a位于该第一补偿区231靠近第一显示区A1的一侧并绕该透明区22延伸，该第三子部313c位于该第一补偿区231靠近第二显示区A2的一侧并绕透明区22延伸。该第一子部313a和第三子部313c均包括曲线型结构，也即该第一子部313a和第三子部313c的至少部分或全部为曲线型结构；该第二子部313b为直线型结构。该第二子部313b的至少部分位于第一补偿区231中用于与第一补偿电极耦合形成补偿电容。例如，第二子部313b的延伸方向与第一方向D1平行。如图1C所示，该第一子部313a和第三子部313c分别为弧线型结构。
例如，该第一补偿电极可以为与该第二子部313b在垂直于衬底基板的方向上重叠的信号线的一部分，也可以是额外设置的补偿电极，本公开实施例对此不作限制。
例如，如图1B所示，第一子部313a和第三子部313c分别与该第二子部313b沿第一方向D1的两端直接电连接，该第一子部313a在该第一子部313a与该第二子部313b的连接点处的切线与该第二子部313b所在的直线的夹角α1为锐角；该第三子部313c在该第二第三子部313c与该第二子部313b的连接点处的切线与该第二子部313b所在的直线的夹角为锐角。
图2A示出了图1C在区域A的放大示意图，图中用虚线示出了第一补偿区231的部分轮廓。如图2A所示，该显示基板20包括用于形成补偿电容的第一补偿电极315，该第一补偿电极23位于该第一补偿区231中。该第一补偿电极315与多条第一信号线31中的至少一条第一信号线的第二信号线部分的第二子部在垂直于衬底基板的方向上重叠以形成补偿电容。
例如，该显示基板20包括多个第一补偿电极315，多个第一补偿电极315分别与多条第一信号线31一一对应设置，每个第一补偿电极315与对应的第一信号线31的第二信号线部分31b的第二子部313b位于第一补偿区231的部分在垂直于衬底基板的方向上重叠以形成补偿电容。例如，该第一补偿电极315位于该第二信号线部分31b远离衬底基板200的一侧。例如，可以根据该第一信号线31所对应的第一像素行缺失的子像素的数量计算出该第一信号线31上需要补偿的电容值，从而确定该第一补偿电极315的总面积。
图2B示出了图2A中的局部放大示意图，图2C示出了图2B沿剖面线I-I’ 的剖视图。由于篇幅所限，对于每条第一信号线31，图2B和图2C仅示出了第二信号线部分31b的第二子部313b靠近第一子部313a一侧的情形。
如图2A-2B所示，该第二信号线部分31b的第二子部313b的平均线宽(图2A中沿第二方向D2的平均尺寸)大于第一子部313a或第三子部313c。由于该第二子部313b作为补偿电容的一个电容电极，增大该第二子部313b的线宽有利于增大补偿电容的面积，从而获得较大的补偿电容。例如，该第二子部313b包括位于第一补偿区231用于形成补偿电容的第一部分和位于第一补偿区231外的第二部分，该第一部分的平均线宽大于该第二部分的平均线宽，该第二部分的平均线宽例如可以与该第一子部313a的平均线宽一致；也即该第一补偿电极315仅与该第二子部313b部分重叠以形成补偿电容，该第二子部与该第一补偿电极重叠的面积可以根据计算出的需要补偿的电容值确定。
例如，每个第一补偿电极315被划分为彼此间隔的多个补偿电极部315a，这是由于对于每条第一信号线31，其对应的第一补偿电极315可能不能连续设置，例如被其它信号线所间隔。另一方面，将每个第一补偿电极315分隔成多个补偿电极部315a有利于补偿设计。
例如，如图2B-2C所示，每个补偿电极部315a的面积可以相同或基本相同，每个补偿电极部315a和第二子部313b的与该补偿电极部315a重叠的部分分别构成补偿子电容，也即每个补偿电容包括彼此并联的多个补偿子电容。可以根据该第一信号线31所对应的第一像素行缺失的子像素的数量计算出该第一信号线31上需要补偿的电容值以及每个补偿子电容的电容值确定该第一信号线31所需要对应设置的补偿电极部315的数目并进行相应的设置。
例如，该第一补偿电极315上可以加载固定电压，从而有利于提高补偿电容的稳定性。
例如，多个第一补偿电极中的多个补偿电极部沿第一方向D1和第二方向D2排列为阵列，例如，如图2B所示，位于同一列的补偿电极部可以彼此连接为一体的结构，这样可以降低工艺难度。
在第一方向D1上，每个第二子部313b所对应的多个补偿电极部315a彼此电连接，从而保证该第二子部313b上形成的多个补偿子电容可以彼此并联。由于多个补偿电极部315a彼此间隔设置，没有直接电连接，可以借助其它结构形成电连接。
例如，如图2C所示，该显示基板20还包括第二补偿电极317，在垂直于 衬底基板的方向上，该第二补偿电极317与第一补偿电极315分别位于第一信号线31的第二信号线部分31b的两侧且彼此电连接，从而形成并联电容的结构，有利于在有限的空间增大该补偿电容的电容值。例如，该第二补偿电极317位于该第二信号线部分31b靠近衬底基板的一侧，该第一补偿电极315位于该第二信号线部分31b远离衬底基板的一侧。
例如，该二补偿电极317包括半导体材料，为导体化的半导体材料，例如重掺杂的半导体材料。例如，该第二补偿电极317与像素电路中的晶体管的有源层同层设置且一体成型。
例如，如图2C所示，第一补偿电极315和第二子部313b构成第一电容C1，第二子部313b与第二补偿电极317构成第二电容C2，每个补偿电极部315a均通过过孔350与该第二补偿电极317电连接。
例如，该显示基板20包括多个第二补偿电极317，该多个第二补偿电极与多条第一信号线31的第二信号线部分31b的第二子部313b一一对应设置，也即与多个第一补偿电极315一一对应设置。
例如，多个第二补偿电极317为一体的结构，从而与该第二补偿电极317电连接的多个补偿电极部315a彼此电连接，使得每个第二子部313b上形成的多个补偿子电容可以彼此形成并联。
例如，透明区22为圆形区域，那么被该透明区22间隔的多个第一像素行中所缺失的子像素的数量存在不同。例如，对应于该圆形区域的直径设置的第一像素行所缺失的子像素最多。
图3示出了该显示基板在透明区22周边的区域布局示意图，为了便于说明，图中信号线仅进行了示意，并且图中四周的空白区域表示显示区21。结合参考图1B，该显示基板20还包括位于显示区21和透明区22之间的第二补偿区232，该第一补偿区231和第二补偿区232在第二方向D2上分别位于透明区22的相对两侧，例如，相对于该透明区22的几何中心对称设置。
该第二补偿区中补偿电极的设置与该第一补偿区类似，此处不再赘述。
如图3所示，第一补偿区和第二补偿区均位于电压总线210靠近透明区22的一侧，也即多个第一补偿电极均位于电压总线210靠近透明区22的一侧。
例如，将被透明区22间隔的多个第一像素行在第二方向D2上分为行数基本相同的第一部分和第二部分(例如沿图3中虚线进行划分)，例如图3中被虚线分离的上半部分和下半部分，该第一部分所对应连接的第一信号线由与该 第一部分同侧的补偿区，如图3中位于上侧的第一补偿区231进行补偿，该第二部分所对应连接的第一信号线由与该第二部分同侧的补偿区，如图3中位于下侧的第二补偿区232进行补偿。通过在上下两个区域分别设置第一补偿区和第二补偿区，可以避免布线过于集中，从而优化布线和基板的版图布局。
例如，对于第一补偿区231所要补偿的多个第一像素行，在第二方向D2上所缺失的子像素的数目单调变化，因此每个像素行所对应设置的第一补偿电极315的面积单调变化，例如每个第一像素行所对应设置的补偿电极部315a的数目单调变化。例如，在图3所示的方向F上，第一补偿区231所要补偿的多个第一像素行所缺失的子像素的数目时单调变化单调递减，每个第一像素行所对应设置的第一补偿电极315的面积单调递减，每个第一像素行所对应设置的补偿电极部315a的数目单调递减，因此形成如图3所示的半圆形的第一补偿区231。类似地，第二补偿区232也为半圆形区域，此处不再赘述。
例如，在每个补偿区，多条第一信号线31所对应设置的多个补偿电极部315a沿第一方向D1和第二方向D2排列为阵列，在第二方向D2上，位于第一方向D1上每行中的补偿电极部315a的数目单调变化。
结合参考图1A-1C、图2A-2B和图3所示，该显示基板20还包括沿第二方向D2延伸的多条第二信号线32，每条第二信号线32包括位于显示区的第一信号线部分和位于周边区的第二信号线部分；例如，该第一信号线部分和该第二信号线部分同层设置并连接为一体的结构。
图1B-1C和图3中仅示出了该第二信号线32的第二信号线部分，如图1B-1C和图3所示，该第二信号线部分包括依次连接的第一信号线子部321、第二信号线子部322和第三信号线子部323，该第一信号线子部321和第三信号线子部323为直线型结构，该第二信号线子部322包括曲线型结构，例如，该第二信号线子部322为绕透明区22延伸的弧线形结构。将该第二信号线32位于补偿区的第一信号线子部321和第二信号线子部323设计为直线结构便于补偿电容的设计。
例如，该多条第二信号线32的多个第一信号线子部321与多列补偿电极部315a一一对应设置。例如，每列补偿电极部315a与对应的一条第二信号线32的第一信号线子部321彼此电连接。例如，多条第二信号线32与第一补偿电极315同层设置，每条第二信号线32与对应的一列补偿电极部315a为一体的结构。
例如，该多条第二信号线32为电源线，并配置为连接到同一电源电压端，因此，通过与各自对应的第二信号线32电连接，多个补偿电极部315a实现了电连接，从而将一行中的多个补偿子电容进行并联。此外，通过与该第二信号线32电连接，该第一补偿电极上加载了固定的电压，从而提高了补偿电容的稳定性。
例如，如图1A所示，该第二信号线32的第一信号线部分被该透明区间隔为分别位于第三显示区A3和第四显示区A4的两个部分，同一条第二信号线32的两个部分与位于同一列但被透明区间隔的子像素连接以提供电源电压。
结合参考图1A-1C、图2A-2B和图3所示，例如，显示基板20还包括沿第二方向D2延伸的多条第三信号线33，该第三信号线33包括位于显示区的第一信号线部分和位于周边区的第二信号线部分。该第三信号线33的第二信号线部分包括依次连接的第一信号线子部331、第二信号线子部332和第三信号线子部333。如图3所示，该第一信号线子部331和第二信号线子部332均为直线型结构，该第二信号线部分333绕透明区22延伸。
例如，每条第三信号线33的第一信号线子部331、第二信号线子部332和第二信号线部分333同层设置并一体成型。
如图3所示，该第三信号线的第一信号线子部331和第二信号线子部332分别与位于第三显示区A3和第四显示区A4且位于同一列的子像素(第一像素列)连接以提供电信号。例如，多条第三信号线分别与多个第一像素列的子像素一一对应连接，每条第三信号线33的第一信号线部分与对应的第一像素列的子像素电连接。例如，该第三信号线33为数据线。
例如，多条第二信号线32和多条第三信号线33以及第一补偿电极315均同层设置。由于第三信号线33需要与第一补偿电极315绝缘，因此，将第一补偿电极315在第一方向D1上分离为多个间隔的补偿电极部315b有利于布线。
图4示出了图1C中区域B的放大示意图。例如，每个子像素包括发光元件和驱动该发光元件发光的像素电路。例如，该像素电路可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。图4示出了第一显示区A1中的一个像素电路100。
图5A示出了本公开至少一实施例提供的像素电路的电路示意图。如图5A所示，该像素电路包括驱动子电路122、补偿子电路128、数据写入子电路126、 存储子电路127、第一发光控制子电路123、第二发光控制子电路124及第一复位子电路125和第二复位子电路129。
例如，该驱动子电路122包括控制端122a、第一端122b和第二端122c，且配置为与发光元件121连接并且控制流经发光元件121的驱动电流。驱动子电路122的控制端122a和第一节点N1连接，驱动子电路122的第一端122b和第二节点N2连接并配置为接收第一电源电压VDD，驱动子电路122的第二端122c和第三节点N3连接。
例如，该数据写入子电路126包括控制端126a、第一端126b和第二端126c，该控制端126a配置为接收第一扫描信号Ga1，第一端126b配置为接收数据信号Vd，第二端126c与驱动子电路122的第一端122b(也即第二节点N2)连接。该数据写入子电路126配置为响应于该第一扫描信号Ga1将该数据信号Vd写入驱动子电路122的第一端122b。例如，在数据写入及补偿阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端122b(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件121发光的驱动电流。
例如，补偿子电路128包括控制端128a、第一端128b和第二端128c，补偿子电路128的控制端128a配置为接收第二扫描信号Ga2，补偿子电路128的第一端128b和第二端128c分别与驱动子电路122的第二端122c和控制端122a电连接，补偿子电路128配置为响应于该第二扫描信号Ga2对该驱动子电路122进行阈值补偿。
例如，第一扫描信号Ga1可以与第二扫描信号Ga2相同。例如第一扫描信号Ga1可以与第二扫描信号Ga2连接到相同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2通过相同的扫描线传输。
在另一些示例中，第一扫描信号Ga1也可以与第二扫描信号Ga2不同。例如，第一扫描信号Ga1可以与第二扫描信号Ga2连接到不同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2分别通过不同的扫描线传输。
例如，存储子电路127包括第一端127a和第二端127b，该存储子电路的第一端127a配置为接收第一电源电压VDD，存储子电路的第二端127b与驱动子电路的控制端122a电连接。例如，在数据写入及补偿阶段，补偿子电路 128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中；同时，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，存储子电路127与驱动子电路122的控制端122a及第一电源电压端VDD电连接，配置为存储数据写入子电路126写入的数据信号。对于位于第一显示区21中的第一像素电路110的像素电路，该第一电源电压端VDD为第一电源电压端103；对于位于第二显示区22中的第二像素电路120的像素电路，该第一电源电压端VDD为第二电源电压端104。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端122b(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号EM1将第一电压端VDD的第一电源电压施加至驱动子电路122的第一端122b。例如，如图1B所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光元件121的第一端134以及驱动子电路122的第二端122c连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光元件122。
例如，在发光阶段，第二发光控制子电路123响应于第二发光控制端EM2提供的第二发光控制信号EM2而开启，从而驱动子电路122可以通过第二发光控制子电路123与发光元件121电连接，从而驱动发光元件121在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路123响应于第二发光控制信号EM2而截止，从而避免有电流流过发光元件121而使其发光，可以提高 相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号EM2而开启，从而可以结合复位电路以对驱动子电路122以及发光元件121进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同，例如第二发光控制信号EM2可以与第一发光控制信号EM连接到相同的信号输出端，例如，第二发光控制信号EM2可以与第一发光控制信号EM1通过相同的发光控制线传输。
在另一些示例中，第二发光控制信号EM2可以与第一发光控制信号EM1不同。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别连接到不同的信号输出端。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别通过不同的发光控制线传输。
例如，第一复位子电路125包括第一端125a、第二端125b和第三端125c，该第一端125a配置为接收第一复位控制信号Rst1，第二端125b与第一复位电压端Vinit1连接，该第三端125c与驱动子电路122的控制端122a(第一节点N1)连接，该第一复位子电路125配置为响应于第一复位控制信号Rst1将第一复位电压Vinit1施加至驱动子电路122的控制端122a。
例如，第二复位子电路129(本公开复位子电路的一个示例)包括第一端129a、第二端129b和第三端129c，该第一端129a配置为接收第二复位控制信号Rst2(本公开复位控制信号的一个示例)，第二端129b与第二复位电压端Vinit1连接，该第三端129c与发光元件122的第一端122b(第四节点N4)连接，该第二复位子电路129配置为响应于第二复位控制信号Rst2将第二复位电压Vinit2施加至发光元件121的第一端134。
例如，第一复位子电路125和第二复位子电路129可以分别响应于第一复位控制信号Rst1和第二复位控制信号Rst2而开启，从而可以将分别将第二复位电压Vinit2施加至第一节点N1以及将第一复位电压Vinit1施加至发光元件121的第一端134，从而可以对驱动子电路122、补偿子电路128以及发光元件121进行复位操作，消除之前的发光阶段的影响。
例如，每行子像素的第二复位控制信号Rst2可以与该行子像素的第一扫描信号Ga1为相同的信号。例如，每行子像素的第一复位控制信号Rst1可以与上一行子像素的第一扫描信号Ga1或第二复位控制信号Rst2相同。
例如，发光元件121包括第一端134和第二端135，发光元件121的第一端134配置为与驱动子电路122的第二端122c连接，发光元件121的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图2A所示，发光元件121的第一端134可以通过第二发光控制子电路124连接至第四节点N4。本公开的实施例包括但不限于此情形。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位控制信号，符号Vinit1、Vinit2既可以表示第一复位电压端和第二复位电压端又可以表示第一复位电压和第二复位电压，符号VDD既可以表示第一电源电压又可以表示第一电源电压端，符号VSS既可以表示第二电源电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图5B为图5A所示的像素电路的一种具体实现示例的电路图。如图5B所示，该像素电路包括第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图5B所示，驱动子电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动子电路122的控制端122a，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端122b，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端122c，和第三节点N3连接。
例如，如图5B所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，如图5B所示，补偿子电路128可以实现为第三晶体管T3。第三晶 体管T3的栅极、第一极和第二极分别作为该补偿子电路的控制电极128a、第一电极128b和第二电极128c。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极T3s和第一晶体管T1的第二极T1d(第三节点N3)连接，第三晶体管T3的第二极T3d和第一晶体管T1的栅极T1g(第一节点N1)电连接。例如，如图2B所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极Ca和第二电容电极Cb，该第一电容电极Ca和第一电源电压端VDD电连接，该第二电容电极Cb和第一晶体管T1的栅极T1g(第一节点N1)电连接。
例如，如图5B所示，第一发光控制子电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，发光元件121具体实现为发光二极管(LED)，例如可以是有机发光二极管(OLED)、量子点发光二极管(QLED)或者无机发光二极管，例如可以是微型发光二极管(Micro LED)或者微型OLED。例如，发光元件121可以为顶发射结构、底发射结构或双面发射结。该发光元件121可以发红光、绿光、蓝光或白光等。本公开的实施例对发光元件的具体结构不作限制。
例如，发光元件121的第一电极134(例如为阳极)和第四节点N4连接配置为通过第二发光控制子电路124连接到驱动子电路122的第二端122c，发光元件121的第二电极135(例如为阴极)配置为和第二电源电压端VSS连接以接收第二电源电压VSS，从驱动子电路122的第二端122c流入发光元件121的电路决定发光元件的亮度。例如第二电源电压端VSS可以接地，即VSS可以为0V。例如，第二电源电压VSS可以为负电压。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第五晶体管T5的第二极和发光元件121的第一端134(第四节点N4)连接。
例如，第一复位子电路125可以实现为第六晶体管T6，第二复位子电路 实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位控制信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位控制信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。例如，如图5B所示，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本公开实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系即可。
以下结合图5C所示的信号时序图，对图5B所示的像素电路的工作原理进行说明。如图5C所示，每一帧图像的显示过程包括三个阶段，分别为初始化阶段1、数据写入及补偿阶段2、和发光阶段3。
如图5C所示，在本实施例中，第一扫描信号Ga1和第二扫描信号Ga2采用同一信号，第一发光控制信号EM1和第二发光控制信号EM2采用同一信号；且第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即第二复位控制信号Rst2、第一扫描信号Ga1/第二扫描信号Ga2可以采用同一信号；本行子像素的第一复位信号Rst1与上一行子像素的第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即采用同一信号。然而，这并不作为对本公开的限制，在其它实施例中，可以采用不同的信号分别作为第一扫描信号Ga1、第二扫描信号Ga2、第一复位控制信号Rst1、第二复位控制信号Rst2， 采用不同的信号分别作为第一发光控制信号EM1和第二发光控制信号EM2。
在初始化阶段1，输入第一复位控制信号Rst1以开启第六晶体管T6，将第一复位电压Vinit1施加至第一晶体管T1的栅极，从而对该第一节点N1复位。
在数据写入及补偿阶段2，输入第一扫描信号Ga1、第二扫描信号Ga2以及数据信号Vd，第二晶体管T2和第三晶体管T3开启，数据信号Vd由第二晶体管T2写入第二节点N2，并经过第一晶体管T1和第三晶体管T3对第一节点N1充电，直至第一节点N1的电位变化至Vd+Vth时第一晶体管T1截止，其中Vth为第一晶体管T1的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在数据写入及补偿阶段2，还可以输入第二复位控制信号Rst2以开启第七晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Rst1和第二复位控制信号Rst2可以相同。本公开实施例对此不作限制。
在发光阶段3，输入第一发光控制信号EM1和第二发光控制信号EM2以开启第四晶体管T4、第五晶体管T5和第一晶体管T1，第五晶体管T5将驱动电流施加至OLED以使其发光。流经OLED的驱动电流Id的值可以根据下述公式得出：
Id＝K(VGS-Vth) 2＝K[(Vdata+Vth-VDD)-Vth] 2＝K(Vdata-VDD) 2，其中，K为第一晶体管的导电系数。
在上述公式中，Vth表示第一晶体管T1的阈值电压，VGS表示第一晶体管T1的栅极和源极(这里为第一极)之间的电压，K为与第一晶体管T1本身相关的一常数值。从上述Id的计算公式可以看出，流经OLED的驱动电流Id不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流Id的影响，从而可以改善采用其的显示装置的显示效果。
以下以该电压总线210为复位电压总线，并配置为与第一像素行中的子像 素的复位子电路连接以提供复位电压为例对本公开实施例提供的显示基板进行示例性说明，然而本公开实施例对此不作限制。
例如，该第一电压线211或第二电压线212分别配置为与第一像素行中的子像素中的第二复位子电路的第一端连接以提供第二复位电压Vinit2。例如，第一复位电压Vinit1与第二复位电压Vinit2为同一电压，该复位电压线210配置为分别为第一像素行中的子像素中的第一复位子电路提供第一复位电压Vinit1以及为第一像素行中的子像素中的第二复位子电路提供第二复位电压Vinit2。然而本公开实施例并不限于此。
以下以图5B所示像素电路为例、并结合图6A-6C、图7、图5、图6A-图6C、图7、图8A-8C和图9对本公开至少一实施例提供的显示基板的结构进行示例性说明。
图6A示出了本公开至少一个实施例提供的显示基板20的一个子像素的像素电路100的示意图，图6B示出了图1A沿剖面线II-II’的剖视图，图6C示出了图1A沿剖面线III-III’的剖视图，图6B和图6C中省略了一些在剖面线处不存在直接电连接关系的结构；图4和图6A中对应示出了剖面线II-II’和III-III’的位置，也即图6B同时也示出了图4和图6A沿剖面线II-II’的剖视图，图6C同时也示出了图4和图6A沿剖面线III-III’的剖视图。
结合图6A-6C可知，该显示基板20包括依次设置于衬底基板200上的半导体层107、第一绝缘层301、第一导电层201、第二绝缘层302、第二导电层202、第三绝缘层303、第三导电层203。
每个像素电路中的半导体层的图案及第一导电层的图案都是相同的，图7示意性地示出了在第一方向D1上相邻的四个像素电路中晶体管T1-T7的半导体层107和第一导电层(栅极层)201；图8A对应图6A示出了第二导电层202，图8B对应图6A示出了半导体层107、第一导电层201以及该第二导电层202；图9对应图6A示出了第三导电层203。
为了方便说明，在以下的描述中用Tng、Tns、Tnd分别表示第n晶体管Tn的栅极、第一极、第二极，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构由同一膜层经同一道构图工艺得以图案化而形成的彼此连接的结构， 它们的材料可以相同或不同。
例如，如图7所示，该第一导电层201包括每个晶体管的栅极以及一些扫描线和控制线。图5中用大虚线框示出了每个像素电路所在的区域，用小虚线框示出了一个像素电路中第一到第七晶体管T1-T7的栅极T1g-T7g。
该半导体层107包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图7所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层107为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔。
例如，如图7所示，该第一导电层201包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，该显示基板20采用自对准工艺，利用第一导电层201作为掩膜对该半导体层107进行导体化处理(例如掺杂处理)，使得该半导体层107未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而分别形成该晶体管的第一极和第二极。
例如，该第一导电层201还包括彼此绝缘的多条扫描线310、多条复位控制线320和多条发光控制线330。例如，每行子像素分别对应连接一条扫描线310、一条复位控制线320和一条发光控制线330。
扫描线210与对应的一行子像素中的第二晶体管T2的栅极电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线320与对应的一行子像素中的第六晶体管T6的栅极电连接以提供第一复位控制信号Rst1，发光控制线330与对应一行子像素中的第四晶体管T4的的栅极电连接以提供第一发光控制信号EM1。
例如，如图7所示，本行像素电路的第七晶体管T7的栅极与下一行像素电路(即按照扫描线的扫描顺序，在本行扫描线之后顺序开启的扫描线所在的像素电路行)所对应的复位控制线320电连接以接收第二复位控制信号Rst2。
例如，该第一扫描信号Ga1和第二复位控制信号Rst2可以是同一信号，因此，本行像素电路对应连接的扫描线310可以和下一行像素电路对应连接的复位控制线320连接到同一信号走线或同一信号端，后文将对此进行详细描述。
例如，如图7所示，该扫描线310还与第三晶体管T3的栅极电连接以提供第二扫描信号Ga2，即第一扫描信号Ga1和第二扫描信号Ga2可以为同一信号；该发光控制线330还与第五晶体管T5的栅极电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信 号。
例如，如图8A-8B所示，该第二导电层202包括第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板200的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括开口221，该开口221暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。
例如，如图8A-8B所示，该第二导电层202还可以包括沿第一方向D1延伸的多条复位电压线340，该多条复位电压线340与多行子像素一一对应连接。该复位电压线340与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，如图8B所示，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应的复位电压线340电连接以接收第二复位电压Vinit2。后文将对此进行详细描述。
例如，如图8A-8B所示，该第二导电层202还可以包括屏蔽电极224。例如，该屏蔽电极224与第二晶体管T2的第一极T2s在垂直于衬底基板200的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。由于该第二晶体管T2的第一极T2s配置为接收数据信号Vd，而该数据信号Vd决定了该子像素的显示灰阶，因此该屏蔽电极224提高了数据信号的稳定性，从而提高了显示性能。
例如，结合参考图8B和图6A-6B，该屏蔽电极224还与第六晶体管T6的第二极T6d在垂直于衬底基板200的方向上至少部分重叠，以提高该第二极T6d中信号的稳定性，从而提高第六晶体管T6的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，结合参照图6A，该屏蔽电极224包括还延伸至相邻的像素电路的部分224a，该部分224a与相邻的像素电路中的第三晶体管T3的有源层在垂直于衬底基板200的方向上至少部分重叠，以提高第三晶体管T3的稳定性，进一步稳定了第一晶体管T1的栅极电压。
例如，该屏蔽电极224配置为加载固定电压；例如，该屏蔽电极224与第三导电层中的电源线电连接以加载像素电源电压VDD，后文将结合图7和图3对此进行详细描述。
例如，如图9所示，该第三导电层203包括沿第二方向D2延伸的多条电源线270。例如，该多条电源线210与多列像素电路一一对应电连接以提供第一电源电压VDD。
结合参考图6A，该电源线210通过过孔341与所对应的一列像素电路100中的第一电容电极Ca电连接，该电源线270还通过过孔343与第四晶体管T4的第一极T4s电连接；该电源线270还通过过孔344与屏蔽电极224电连接，从而使得屏蔽电极224具有固定电位，提高了该屏蔽电极的屏蔽能力。例如，该过孔341和过孔344均贯穿第三绝缘层303，该过孔343贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，结合参考图6A和图6C，该第三导电层303还包括沿第二方向D2延伸的多条数据线260，例如，多条数据线260与多列子像素一一对应电连接。例如，数据线260通过过孔354与第二晶体管T2的第一极T2s电连接。
例如，结合参考图9和图6A-6C，该第三导电层203还包括连接电极231，该连接电极231的一端通过第一电容电极Ca中的开口221以及绝缘层中的过孔346与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔347与该第三晶体管T3的第二极T3d电连接，从而将该第二电容电极Cb与该第三晶体管T3的第二极T3d电连接。例如，该过孔346贯穿第二绝缘层302和第三绝缘层303。例如，该过孔347贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，结合参考图9和图6A-6C，该第三导电层203还包括连接电极232，该连接电极232通过过孔348与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接。例如，该过孔348贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，结合参考8C和图6A-6B，该第三导电层203还包括连接电极233，该连接电极233的一端通过过孔351与复位电压线340电连接，另一端通过过孔352与第六晶体管T6的第一极T6s电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线340接收第一复位电压Vinit1。例如，该过孔351贯穿第三绝缘层303。例如该过孔352贯穿第一绝缘层301、第二绝缘层302和第三绝缘层303。
例如，如图6A所示，上一行子像素中的第七晶体管T7的第一极与本行子像素所对应的复位电压线340电连接以接收第二复位电压Vinit2，本行子像 素中的第七晶体管T7的第一极与下一行子像素所对应的的复位电压线340电连接以接收第二复位电压Vinit2；也即本行的该第一复位子电路(也即第六晶体管T6)与上一行的第二复位子电路(也即第七晶体管T7)通过同一复位电压线340接收复位电压。
例如，如图6B-6C所示，该显示基板20还可以包括依次位于第三导电层203上的第四绝缘层304和第四导电层204。例如，该第五导电层205包括发光元件121的第一电极134。
例如，结合参考图4和图6B，该显示基板20还包括位于第三导电层203中的连接电极234，该连接电极234位于周边区23中。该第四导电层204还包括该电压总线210。该连接电极234通过过孔353与复位电压线340电连接，并通过过孔354与该电压总线210电连接，从而将复位电压线340与电压总线210电连接；也就是说，在第一显示区A1或第二显示区A2，复位电压线340分离为两部分，该两部分分别作为位于第一显示区A1的第一电压线211和位于第二显示区A2的第二电压线212，该复位电压线340的两部分分别与电压总线210电连接。例如，在第三显示区A3和第四显示区A4，该复位电压线340在一行中连续延伸。
由于第四导电层204主要用于形成发光元件的第一电极，走线密度较低，将电压总线210设置在第四导电层可以便于布线。
例如，参考图6B-6C，该显示基板20还可以包括位于发光元件的第一电极134远离衬底基板200一侧的像素界定层306。像素界定层306中形成开口暴露出第一电极134的至少部分从而界定显示基板各个子像素的开口区(即发光区)600。发光元件121的发光层136至少形成于该开口内(发光层136还可以覆盖部分的像素界定层远离发光元件的第一电极一侧的表面)，第二电极135形成于发光层136上从而形成该发光元件121。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如第一电极134为发光元件的阳极，第二电极135为发光元件的阴极。
例如，衬底基板200可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯 烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层107的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该第一到第四导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者透明导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该发光元件121为顶发射结构，第一电极具134有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，第一绝缘层301、第二绝缘层302、第三绝缘层303例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，第四绝缘层304与像素界定层306例如可以为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层304为平坦化层。本公开实施例对此不作限制。
例如，上述第一信号线31位于显示区的部分，也即第一信号线子部318和第二信号线子部319为该扫描线310。
例如，该第二信号线32位于显示区的部分，也即该第一信号线子部321或第二信号线子部322为上述电源线270，也即该第二信号线配置为提供第一电源电压VDD。
例如，该第三信号线33位于显示区的部分，也即该第一信号线子部331或第二信号线子部332位上述数据线260，也即该第三信号线配置为提供数据信号Vd。例如，该第二信号线21与该第三信号线33均位于第三导电层203并彼此绝缘。
参考图7，该第一信号线子部318和第二信号线子部319分别与对应的一行子像素的数据写入子电路的控制端(也即第二晶体管T2的栅极T2g)以及补偿子电路的控制端(也即第三晶体管T3的栅极T3g)电连接。
参考图5，该第一信号线子部318和第二信号线子部319分别与对应的一 行子像素的数据写入子电路的控制端(也即第二晶体管T2的栅极T2g)以及补偿子电路的控制端(也即第三晶体管T3的栅极T3g)电连接。
例如，如图4和图6C所示，第一信号线31的第一信号线子部318和第二信号线子部319均位于第一导电层201中，并与第二信号线部分31b位于不同层。例如，第一信号线子部318和第二信号线子部319位于第二信号线部分31b靠近衬底基板200的一侧。
由于第一信号线子部318和第二信号线子部319配置为显示区的扫描线，例如与显示区的晶体管的栅极一体成型，而栅极工艺影响晶体管的沟道宽长比，因此该栅极工艺的调整对晶体管的性能影响较大。通过将第二信号线部分31b设置于与第一信号线子部318和第二信号线子部319不同的导电层中，可以使得第二信号线部分31b的工艺调整更为灵活，该第二信号线部分31b的工艺的调整不会影响到第一信号线子部318和第二信号线子部319的工艺。例如，在第三显示区A3和第四显示区A4，扫描线310连续形成。例如，第一信号线子部318和第二信号线子部319的工艺参数与第三显示区A3和第四显示区A4中扫描线310的工艺参数一致。
例如，如图6C所示，第二信号线部分31b位于第二导电层202中，也即与复位电压线340同层绝缘设置。
例如，结合参考图4和图6C所示，显示基板20还包括连接电极235(本公开第一连接电极的一个示例)，该连接电极235例如位于第三导电层203中。该连接电极235通过过孔355(本公开第一过孔的一个示例)与第一信号线31的第一信号线子部318或第二信号线子部319(也即扫描线310)电连接，并通过过孔356(本公开第二过孔的一个示例)与该第一信号线31的第二信号线部分31b(图4中第一延伸部311)电连接。通过设置连接电极235连接第一信号线部分31a和第二信号线部分31b，也即该第一信号线部分31a和第二信号线部分31b并不直接通过贯穿第二绝缘层302的过孔电连接，从而节省一道对第二绝缘层302的构图工艺。
例如，如图4所示，过孔355和过孔356位于电压总线210远离透明区22的一侧，也即靠近显示区21的一侧，且在第二方向D2上并列排布。
如图4所示，电压总线210位于第二信号线部分31b的弯折部313远离透明区22的一侧，电压总线210与该第二信号线部分31b的第一延伸部311在垂直于衬底基板的方向上重叠，并与该第二信号线部分31b的弯折部313在垂 直于衬底基板的方向上不重叠。这种设置使得电压总线210避开线路密集的绕线区域，便于电压总线210与第一电压线211或第二电压线212的电连接。
例如，如图4所示，该显示基板还包括位于第三导电层203中的连接电极236，该显示基板还包括位于周边区23的信号线子部316(本公开第四信号线子部的一个示例)，该连接电极236位于该信号线子部316远离透明区的一侧，用于将该信号线子部316与显示区中复位控制线320(本公开第三信号线子部的一个示例)电连接。例如，该信号线子部316位于第三导电层203，该连接电极236的设置与连接电极235的效果类似，可以节省一道对第二绝缘层302的构图工艺。例如，如图4所示，在垂直于衬底基板的方向上，该连接电极236与电压总线210部分重叠。
类似地，将显示区中的复位控制线320与信号线子部316不设置在同一层中，可以便于对信号线子部316的工艺进行调整，而避免对显示区中晶体管的工艺造成影响。
例如，如图2C所示，本行像素电路所接收的扫描信号Ga1/Ga2与本行像素电路所接收的第二复位控制信号Rst2可以是同一信号，并与下一行像素电路对应连接第一复位控制信号Rst1是同一信号，因此，本行像素电路所对应连接的扫描线320与本行第二复位子电路所对应连接的复位控制线320(也即下一行第一复位子电路所对应连接的复位控制线320)连接到同一信号端。
结合参考图4，对于第一像素行，本行像素电路所对应连接的扫描线310(也即第一信号线子部318或第二信号线子部319)与第二复位子电路所对应连接的复位控制线320连接到同一绕线(也即弯折部313)，也即二者共用一条绕线，这样可以降低周边区23的绕线密度，提高工艺良率。如图4所示，扫描线310经第二信号线部分31b的第一延伸部311连接到其弯折部313，复位控制线320经信号线子部316连接到该弯折部313，也即该信号线子部316的一端与该复位控制线320电连接，另一端与对应的弯折部部313电连接。该信号线子部316与该第一延伸部311同层平行设置，并与弯折部313直接电连接。图4分别示出了该第一信号线的第二信号线部分的第一延伸部311与弯折部313的连接点C1以及该信号线子部316与该弯折部313的连接点C2。该弯折部313包括位于该连接点C1和该连接点C2的部分。
例如，显示基板20包括沿第一方向D1延伸的多个信号线子部316，多条信号线子部316分别与多个第一像素行对应的多条复位控制线320一一对应电 连接。
如图4所示，在垂直于衬底基板的方向上，每个信号线子部316均与电压总线210重叠。
例如，如图4和图6A所示，与同一子像素连接的第二信号线32(电源线270)和第三信号线33(数据线260)在第二方向D2上直接相邻，并成对设置。
例如，在显示区和周边区，多条第二信号线32和多条第三信号线33在第一方向上均交替排布。
例如，该第二信号线32的第一信号线部分的平均线宽大于该第二信号线31第二信号线部分的平均线宽；也即该第二信号线32从显示区到周边区进行了收窄设计。例如，该第二信号线32的第一信号线部分的平均线宽大于该第二信号线部分的第二信号线子部322的平均线宽。在显示区中将该第二信号线32设计得较宽有助于降低该第二信号线32的电阻从而降低电源电压在该第二信号线32上的电压降，从而提高显示均一性；而在周边区进行绕线时为了节省空间则将该第二信号线的第二信号线部分的线宽设计得较窄。例如，该第二信号线的第二信号线部分的第二信号线子部322与第三信号线的第二信号线部分的第二信号线子部332的平均线宽相同，从而降低工艺难度。
例如，如图1A-1C所示，该显示基板还包括虚拟电极220，该虚拟电极220为浮置(floating)电极，也即并不加载电信号。例如，该虚拟电极220的至少部分围绕透明区22设置且相较于其它导线最靠近该透明区22，也即该虚拟电极靠近透明区22的一侧没有设置走线，或者说该虚拟电极为该周边区23中最靠近透明区22的导电结构。该虚拟电极220可以屏蔽透明区22中的光电信号对显示区21和周边区23中信号线上的电信号的干扰。例如，该透明区22配置为允许来自显示基板的显示侧的光透射到该显示侧的相对一侧以用于感测，例如该光线为可见光或红外光；该虚拟电极220可以屏蔽经过该透明区22的光线对该虚拟电极外侧的电信号的干扰。例如，该虚拟电极可以为环状，全部包围该透明区22。
例如，该虚拟电极220可以位于第三导电层203，由于数据线260位于第三导电层，将该虚拟电极220设置在第三导电层203，可以拉近虚拟电极220与数据线260的距离，保护数据线260中的数据信号不受干扰。然而，本公开实施例对此不作限制。在另一些示例中，该虚拟电极220也可以位于第二导电层202或者第四导电层204。
例如，该透明区22并不存在导电结构，上述第一到第四绝缘层在该透明区22可以全部保留或部分保留，通过调节该透明区中绝缘层的厚度可以调节经过该透明区22的光线的光程，这可以根据实际需要进行调节。
本公开的至少一实施例还提供一种显示装置，该显示装置包括上述任一显示基板20以及传感器。图10A示出了本公开一些实施例提供的显示装置40的结构示意图，图10B为图10A沿IV-IV’的剖视图。
如图10A-10B所示，该传感器401对应设置于显示基板20的第三显示区23并设置于显示基板的与显示侧相对的一侧，例如设置于衬底基板200远离发光元件的一侧。该传感器401例如为光电传感器，配置为接收来自所述显示基板的第一侧的光并将该光线转换成电信号并用于形成图像。例如，该光线从显示侧经该透明区22到达传感器，例如该光线为可见光或红外光。
例如，该显示装置40还包括设置于显示基板20上的封装层207和盖板208，该封装207配置为对显示基板20中的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动电路的渗透而造成对器件的损坏。例如，封装层207包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层207与显示基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板208例如为玻璃盖板。例如，盖板208和封装层207可以为一体的结构。
例如，传感器401可以贴附于显示基板20的背面(与显示面相对的一面)。如图10B所示，成像元件401贴附在衬底基板200远离发光元件的第二电极135的一侧。该传感器401例如可以实现为摄像头。
该显示装置例如可以数码相框、智能手环、智能手表、手机、平板电脑、显示器、笔记本电脑、导航仪等具有任何显示功能的产品或者部件。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种显示基板，包括显示区、透明区以及位于所述显示区和所述透明区之间的周边区，
    其中，所述显示基板包括衬底基板以及位于所述衬底基板上且位于所述显示区的多个子像素，所述多个子像素沿第一方向和第二方向分布为多个像素行和多个像素列，所述第一方向和所述第二方向不同；所述多个像素行包括被所述透明区间隔的多个第一像素行；
    所述显示基板还包括电压总线，所述电压总线位于所述周边区，所述电压总线至少部分环绕所述透明区，并配置为与所述多个第一像素行中的子像素连接以提供第一电压；
    所述显示基板还包括沿所述第一方向延伸的多条第一信号线，所述多条第一信号线分别与所述多个第一像素行一一对应连接；
    所述多条第一信号线的每条包括位于所述显示区的第一信号线部分和位于所述周边区的第二信号线部分，所述第一信号线部分和所述第二信号线部分彼此电连接，所述第二信号线部分包括沿所述透明区延伸的弯折部，
    所述多条第一信号线的第二信号线部分的弯折部均位于所述电压总线靠近所述透明区的一侧。
  2. 如权利要求1所述的显示基板，其中，
    所述显示区包括被所述透明区间隔且在所述第一方向上相对的第一显示区和第二显示区，所述多个第一像素行中的子像素被所述透明区间隔在所述第一显示区和所述第二显示区；
    所述显示基板还包括沿所述第一方向延伸的多条第一电压线和多条第二电压线，所述多条第一电压线和所述多条第二电压线均与所述电压总线电连接；
    所述多条第一电压线位于所述第一显示区，并分别与所述多个第一像素行中位于所述第一显示区的多行子像素连接以提供所述第一电压；
    所述多条第二电压线位于所述第二显示区，并分别与所述多个第一像素行中位于所述第二显示区的多行子像素连接以提供所述第一电压。
  3. 如权利要求2所述的显示基板，其中，所述多个子像素的每个包括发光元件和驱动所述发光元件发光的像素电路；
    所述像素电路包括驱动子电路、数据写入子电路、补偿子电路、存储子电 路和复位子电路；
    所述驱动子电路包括控制端、第一端和第二端，且配置为与所述发光元件连接并且控制流经所述发光元件的驱动电流；
    所述数据写入子电路与所述驱动子电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动子电路的第一端；
    所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；
    所述存储子电路包括第一端和第二端，所述存储子电路的第一端配置为接收第一电源电压，所述存储子电路的第二端与所述驱动子电路的控制端电连接；
    所述复位子电路包括控制端、第一端和第二端，所述复位子电路的控制端配置为接收复位控制信号，所述复位子电路的第一端与相应的第一电压线或第二电压线连接以接收所述第一电压，所述复位子电路的第二端与所述发光元件连接。
  4. 如权利要求3所述的显示基板，其中，所述发光元件包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的发光层，所述第一电极相较于所述发光层更靠近所述衬底基板，所述电压总线与所述发光元件的第一电极同层绝缘设置。
  5. 如权利要求3或4所述的显示基板，其中，所述存储子电路包括存储电容，所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极和所述第二电容电极分别作为所述存储子电路的第一端和第二端；
    所述第二电容电极位于第一电容电极靠近衬底基板的一侧，所述第一电压线和所述第二电压线均与存储电容的第一电容电极同层绝缘设置，并位于所述电压总线靠近所述衬底基板的一侧。
  6. 如权利要求5所述的显示基板，其中，所述多条第一信号线分别与所述多个第一像素行的子像素的数据写入子电路一一对应连接以提供所述第一扫描信号；
    所述多条第一信号线的第一信号线部分每条包括位于所述第一显示区的第一信号线子部和位于所述第二显示区的第二信号线子部，所述每条第一信号 线的第二信号线部分将所述第一信号线子部和所述第二信号线子部电连接；
    所述每条第一信号线的第一信号线子部和所述第二信号线子部均沿所述第一方向延伸，所述第一信号线子部与所述第一信号线所对应的第一像素行中位于所述第一显示区的子像素连接，所述第二信号线子部与所述第一信号线所对应的第一像素行中位于所述第二显示区的子像素连接。
  7. 如权利要求6所述的显示基板，其中，所述第一信号线的第一信号线子部和第二信号线子部同层设置，并位于所述第一信号线的第二信号线部分靠近所述衬底基板的一侧。
  8. 如权利要求7所述的显示基板，还包括第一连接电极，其中，
    所述多个第一连接电极位于所述多条第一信号线的第二信号线部分远离所述衬底基板的一侧；
    所述多条第一信号线的每条的第一信号线子部和第二信号线部分分别通过所述第一连接电极电连接；
    所述第一连接电极通过第一过孔与所对应的第一信号线的第一信号线子部电连接，并通过第二过孔与所对应的第一信号线的第二信号线部分电连接。
  9. 如权利要求8所述的显示基板，其中，所述第一过孔和所述第二过孔均位于所述电压总线远离所述透明区的一侧，并在所述第二方向上并列排布。
  10. 如权利要求6-9任一所述的显示基板，其中，所述第一信号线的第二信号线部分还包括位于所述弯折部两侧并与所述弯折部电连接的第一延伸部和第二延伸部；
    所述第一延伸部和所述第二延伸部均沿所述第一方向延伸，并分别与所述第一信号线子部和所述第二信号线子部电连接。
  11. 如权利要求10所述的显示基板，其中，
    所述电压总线与第一信号线的第二信号线部分的第一延伸部和第二延伸部在垂直于所述衬底基板的方向上重叠，并与所述弯折部在垂直于所述衬底基板的方向上不重叠。
  12. 如权利要求10或11所述的显示基板，还包括位于所述第一显示区并沿所述第一方向延伸的多个第三信号线子部，
    其中，所述多个第三信号线子部分别与所述多个第一像素行位于所述第一显示区中的多行子像素的复位子电路的控制端一一对应连接以提供所述复位控制信号。
  13. 如权利要求12所述的显示基板，还包括位于所述周边区的多个第四信号线子部，
    其中，所述多个第四信号线子部与所述多个第三信号线子部一一对应电连接，
    所述多个第四信号线子部的每个与所对应的第三信号线子部所对应连接的子像素所连接的第一信号线的第二信号线部分的弯折部电连接。
  14. 如权利要求13所述的显示基板，其中，所述多个第四信号线子部的每个的一端与所对应的第三信号线子部电连接，另一端与所述弯折部电连接；
    在垂直于所述衬底基板的方向上，所述电压总线与所述多个第四信号线子部的每个均重叠。
  15. 如权利要求3-14任一所述的显示基板，其中，所述多条第一信号线的第一信号线部分与所述第一电容电极同层绝缘设置，
    所述多条第一信号线的第二信号线部分与所述第二电容电极同层绝缘设置。
  16. 如权利要求1-14任一所述的显示基板，其中，所述显示基板还包括沿所述第二方向延伸的多条第二信号线，所述多条第二信号线的每条包括位于所述显示区的第一信号线部分和位于所述周边区的第二信号线部分；
    所述每条第二信号线的第二信号线部分包括依次连接的第一信号线子部、第二信号线子部和第三信号线子部，所述每条第二信号线的第一信号线子部和第三信号线子部为直线型结构，所述每条第二信号线的第二信号线子部包括曲线型结构；
    所述多条第二信号线为电源线。
  17. 如权利要求16所述的显示基板，还包括多个第二连接电极，
    其中，所述多个第二连接电极与所述多条第二信号线同层绝缘设置，所述多条第一电压线分别通过所述多个第二连接电极与所述电压总线电连接。
  18. 如权利要求1-17任一所述的显示基板，还包括虚拟电极，其中，所述虚拟电极至少部分围绕透明区设置且相较于其它导线最靠近所述透明区。
  19. 如权利要求1-18任一所述的显示基板，其中，所述显示基板还包括位于所述周边区的多个第一补偿电极，所述多个第一补偿电极分别与所述多条第一信号线一一对应设置；所述多个第一补偿电极位于所述多条第一信号线的第三信号线段远离所述衬底基板的一侧；
    所述多个第一补偿电极的每个与所对应的第一信号线的第二信号线部分的弯折部在垂直于所述衬底基板的方向上重叠以形成补偿电容；
    所述多个第一补偿电极位于所述电压总线靠近所述透明区的一侧。
  20. 一种显示装置，包括如权利要求1-19任一所述的显示基板。
  21. 如权利要求20所述的显示装置，还包括传感器，
    其中，所述传感器设置于所述衬底基板远离所述多个子像素的一侧，且配置为接收并检测透过所述透明区的光。
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