WO2022178670A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022178670A1
WO2022178670A1 PCT/CN2021/077488 CN2021077488W WO2022178670A1 WO 2022178670 A1 WO2022178670 A1 WO 2022178670A1 CN 2021077488 W CN2021077488 W CN 2021077488W WO 2022178670 A1 WO2022178670 A1 WO 2022178670A1
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WIPO (PCT)
Prior art keywords
electrode
sub
data writing
circuit
transistor
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PCT/CN2021/077488
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English (en)
French (fr)
Inventor
吴谦
范龙飞
卢鹏程
陈小川
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/628,671 priority Critical patent/US20220344428A1/en
Priority to PCT/CN2021/077488 priority patent/WO2022178670A1/zh
Priority to CN202180000281.9A priority patent/CN115298730A/zh
Priority to EP21927117.8A priority patent/EP4131239A4/en
Publication of WO2022178670A1 publication Critical patent/WO2022178670A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • Micro OLED (Micro OLED) display involves the combination of organic light-emitting diode (OLED) technology and CMOS technology, and is related to the cross-integration of optoelectronics industry and microelectronics industry, which promotes the development of a new generation of microdisplay technology and also promotes organic electronics on silicon. , and even the research and development of molecular electronics on silicon.
  • OLED organic light-emitting diode
  • Micro OLED (Micro OLED) displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption, etc., and have broad development prospects.
  • Some embodiments of the present disclosure provide a display panel including a base substrate and a sub-pixel on the base substrate, wherein the sub-pixel includes a pixel circuit and a light-emitting element, and the pixel circuit includes data Write sub-circuit, storage sub-circuit, drive sub-circuit:
  • the data writing subcircuit is configured to transmit a data signal to the storage subcircuit in response to a control signal
  • the driving sub-circuit includes a control electrode, a first electrode and a second electrode, the control electrode of the driving sub-circuit is coupled to the storage sub-circuit, and the first electrode of the driving sub-circuit is configured to receive a first power supply voltage , the second electrode of the driving sub-circuit is coupled to the first electrode of the light-emitting element, and the driving sub-circuit is configured such that the driving sub-circuit is configured to drive the driving sub-circuit in response to the voltage of the control electrode of the driving sub-circuit light-emitting element emits light,
  • the storage sub-circuit includes a storage capacitor
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode arranged oppositely, and the first capacitor electrode and the second capacitor electrode are respectively used as the first capacitor electrode of the storage sub-circuit.
  • terminal and a second terminal the second capacitor electrode is located between the base substrate and the first capacitor electrode
  • the second capacitor electrode includes first regions arranged in sequence along the short side direction of the sub-pixels , a second region and a third region, the carrier mobility of the second region is different from the carrier mobility of the first region and the third region, and the area of the second region is larger than the first region and the third region. area
  • control electrode of the driving sub-circuit and the first capacitor electrode are an integral structure provided in the same layer.
  • the pixel circuit further includes a resistor, the resistor is connected in series between the second electrode of the driving sub-circuit and the first electrode of the light-emitting element, the resistor is connected to the
  • the control electrodes of the driving sub-circuit are in the same layer and are arranged separately, and the resistivity of the resistor is higher than that of the control electrodes of the driving sub-circuit.
  • the data writing subcircuit includes a transfer gate circuit including a first data writing transistor and a second data writing transistor, the first data writing transistor and the second data writing transistor
  • the write transistors each include a gate, a first pole and a second pole
  • the control signal includes a first control signal and a second control signal
  • the gate of the first data writing transistor is configured to receive the first control signal
  • the gate of the second data writing transistor is configured to receive the second control signal
  • the first data writing transistor The first pole of the second data writing transistor is coupled to the first pole of the second data writing transistor, and both are coupled to the first end of the storage sub-circuit and the control electrode of the driving sub-circuit, and the first data writing transistor
  • the second pole of the second data writing transistor is coupled to the second pole of the second data writing transistor, and both are configured to receive the data signal.
  • the driving sub-circuit includes a driving transistor, and the gate, the first electrode and the second electrode of the driving transistor serve as the control electrode, the first electrode and the second electrode of the driving sub-circuit, respectively.
  • the first data writing transistor and the driving transistor are both N-type metal-oxide semiconductor field effect transistors
  • the second data writing transistor is a P-type metal-oxide semiconductor field effect transistor.
  • the transmission gate circuit and the driving transistor are located on two sides of the storage capacitor, respectively.
  • the resistor and the driving transistor are located on the same side of the storage capacitor in a first direction parallel to the base substrate.
  • the shortest distance between the channel of the drive transistor and the first data write transistor is greater than the shortest distance between the channel of the drive transistor and the second data write transistor.
  • the shortest distance between the resistor and the first data write transistor is less than the shortest distance between the resistor and the second data write transistor.
  • the second data writing transistors and the first data writing transistors are arranged in sequence, the The driving transistors and the resistors are arranged in sequence, and the second direction is the short side direction of the sub-pixels.
  • the resistor is a long strip extending along the first direction, and the resistor is located on a side of the second pole of the driving transistor away from the first pole of the driving transistor.
  • the width of the resistor is smaller than the width of one of the gate of the first data writing transistor, the gate of the second data writing transistor, and the gate of the drive transistor.
  • the gate of the driving transistor, the gate of the first data writing transistor, the gate of the second data writing transistor, the first capacitor electrode and the resistor are the same Layer settings.
  • the storage capacitor further includes a third capacitor electrode, and in a direction perpendicular to the base substrate, the third capacitor electrode is located at a distance from the first capacitor electrode away from the second capacitor electrode. one side, and is coupled with the first region of the second capacitor electrode through the first via hole.
  • the orthographic projection of the third capacitor electrode on the base substrate falls within the orthographic projection of the second capacitor electrode on the base substrate, and the third capacitor electrode is on the base substrate
  • the orthographic projection of the first capacitor electrode partially overlaps the orthographic projection of the first capacitor electrode on the base substrate.
  • the display panel further includes a ground line configured to couple the first area and the third area of the second capacitive electrode, and connect the first area and the third area of the second capacitive electrode Connect to the ground voltage, in the direction perpendicular to the base substrate, the ground wire is located on the side of the third capacitor electrode away from the second capacitor electrode, and the ground wire is on the positive side of the base substrate.
  • the projection partially overlaps with the orthographic projection of the third capacitor electrode on the base substrate.
  • the second data writing transistor and the first data writing transistor are arranged side by side along the second direction and are symmetrical about an axis of symmetry along the first direction.
  • the display panel further includes four sub-pixels, the four sub-pixels form a pixel unit group, wherein the four sub-pixels are arranged in an array along the first direction and the second direction, The first direction and the second direction are perpendicular to each other, and the second data writing transistors of the four sub-pixels are located in the same N-type well region in the base substrate in the orthographic projection of the base substrate.
  • the resistors of adjacent sub-pixels in the first direction are symmetric about an axis of symmetry along the second direction, and the resistors of adjacent sub-pixels in the second direction are symmetric with respect to the axis of symmetry along the second direction
  • the axis of symmetry of the first direction is symmetrical.
  • the transfer gates of the two sub-pixels adjacent in the first direction are symmetrical about the symmetry axis along the second direction, and the transfer gates of the two sub-pixels adjacent in the second direction are about the axis of symmetry along the second direction.
  • the axis of symmetry of the first direction is symmetrical.
  • the driving transistors of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction
  • the driving transistors of two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the second direction.
  • the symmetry axis of the first direction is symmetrical.
  • the first capacitive electrodes of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the first capacitance electrodes of adjacent sub-pixels in the second direction The capacitive electrodes are symmetrical about an axis of symmetry along the first direction.
  • the first capacitor electrodes in the four sub-pixels are located outside the N-type well region in the orthographic projection of the base substrate, and are arranged around the N-type well region.
  • the width of the portion of the third capacitor electrode close to the first region of the second capacitor electrode in the first direction is greater than that of the portion of the third capacitor electrode close to the third region of the second capacitor electrode in the first direction up width.
  • the sub-pixel further includes an anode via hole for connecting the pixel circuit and the light-emitting element, the orthographic projection of the anode via hole on the base substrate and the first capacitor electrode on the base substrate The orthographic projections of , at least partially overlap.
  • the sub-pixel further includes an anode via hole for connecting the pixel circuit and the light-emitting element, and the anode via hole is orthographically projected on the base substrate with the third capacitor electrode on the base substrate The orthographic projections overlap at least partially.
  • the pixel circuit further includes:
  • connection electrode is coupled to the first capacitor electrode through a second via hole, and the distance between the second via hole and the first region is smaller than that between the second via hole and the third region the distance.
  • the distance between the first via hole and the driving transistor is smaller than the distance between the first via hole and the data writing subcircuit.
  • the orthographic projection of the first capacitive electrode on the base substrate and the orthographic projection of the second capacitive electrode on the base substrate have an overlapping area, and the overlapping area includes A first protrusion protruding toward the driving transistor and a second protrusion protruding toward the first data writing transistor.
  • Embodiments of the present disclosure provide a display device including the aforementioned display panel.
  • FIG. 1 is a block diagram of a display panel provided by some embodiments of the present disclosure
  • FIG. 2A is a schematic diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • 2B is a schematic diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 2C is an equivalent circuit diagram of FIG. 2B;
  • FIG. 2D shows a signal timing diagram of the pixel circuit shown in FIG. 2B;
  • 3A is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • Figure 3B is a cross-sectional view of Figure 3A along section line I-I';
  • FIG. 4A is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 4B is a schematic diagram of a sub-pixel in FIG. 4A;
  • 5A-5H show the manufacturing steps of the display panel shown in FIG. 4A;
  • 6A-6B are schematic diagrams of a first conductive layer of a display panel according to some embodiments of the present disclosure.
  • FIGS. 7A-7B are schematic diagrams of a second conductive layer of a display panel according to some embodiments of the present disclosure.
  • FIGS. 8A-8B are schematic diagrams of a third conductive layer of a display panel according to some embodiments of the present disclosure.
  • FIGS. 9A-9B are schematic diagrams of a fourth conductive layer of a display panel according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the expressions “located on the same layer” and “disposed on the same layer” generally mean that the first part and the second part may use the same material and may be formed by the same patterning process.
  • the expressions “located on different layers”, “disposed of different layers” generally mean that the first part and the second part are formed by different patterning processes.
  • first part and a second part are “coupled” to mean that there is a physical connection between the first part and the second part, so that there is a signal therebetween, such as an electrical signal, a magnetic signal
  • a signal therebetween such as an electrical signal, a magnetic signal
  • the specific implementation of the interaction may include direct electrical connection, and may also include connection through other electronic components.
  • OLED Organic Light-Emitting Diode, Organic Light Emitting Diode
  • higher requirements have been placed on the structural design of display panels, such as the arrangement of pixels and signal lines.
  • OLED display device with a resolution of 4K the OLED display device with a large size and a resolution of 8K doubles the number of sub-pixel units that need to be set, and the pixel density increases accordingly.
  • the signal line The line width of the signal line also becomes smaller, which leads to the increase of the resistance of the signal line; on the other hand, the overlap between the signal lines increases, which leads to the increase of the parasitic capacitance of the signal line, which leads to the increase of the resistance-capacitance load of the signal line.
  • the phenomenon of signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) caused by RC load will also become serious. These phenomena will seriously affect the display quality of display products.
  • Micro OLED (Micro OLED) displays usually have a size of less than 100 microns, such as a size of less than 50 microns, etc., involving the combination of organic light emitting diode (OLED) technology and CMOS technology, and OLED arrays are prepared on silicon substrates including CMOS circuits. .
  • OLED organic light emitting diode
  • Micro OLED is widely used in AR and VR fields. With the continuous development of technology, it requires higher resolution. Therefore, higher requirements are placed on the structural design of the display panel, such as the arrangement of pixels and signal lines.
  • the display panel provided by at least one embodiment of the present disclosure can achieve a sub-pixel area of 5.45um ⁇ 13.6um through optimized layout and wiring design processing in the design, and realize high resolution (PPI) and optimization of pixel circuit arrays. arrangement, and has a better display effect.
  • PPI high resolution
  • FIG. 1 is a block diagram of a display panel provided by some embodiments of the present disclosure.
  • the display panel 10 includes a plurality of sub-pixels 100 , a plurality of scan lines 11 and a plurality of data lines 12 distributed in an array.
  • Each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element.
  • a plurality of scan lines 11 and a plurality of data lines 12 cross each other to define a plurality of pixel regions distributed in an array in the display region, and a pixel circuit of a sub-pixel 100 is arranged in each pixel region.
  • the display panel may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area.
  • the gate driving sub-circuit 13 is connected to the pixel circuit through the scan line 11 to provide various control signals, such as scan signals
  • the data driving sub-circuit 14 is connected to the pixel circuit through the data line 12 to provide data signals.
  • the positional relationship between the gate driving sub-circuit 13 and the data driving sub-circuit 14, the scan line 11 and the data line 12 in the display panel shown in FIG. 1 is just an example, and the actual arrangement position can be designed as required.
  • the display panel 10 may further include a control circuit.
  • the control circuit is configured to control the data driving sub-circuit 14 to apply the data signal, and to control the gate driving sub-circuit to apply the scan signal.
  • An example of the control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, including, for example, a processor and a memory, the memory including executable code that the processor executes to execute the detection method described above.
  • a processor may be a central processing unit (CPU) or other form of processing device having data processing capabilities and/or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), or the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory, among others.
  • Non-volatile memory may include, for example, read only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may execute the functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, and a storage sub-circuit as required, and may also include a compensation sub-circuit, a light-emitting control sub-circuit, a reset circuit, and the like as required.
  • FIG. 2A is a schematic diagram of a pixel circuit provided by some embodiments of the present disclosure. As shown in FIG. 2A , the pixel circuit includes a data writing sub-circuit 111 , a driving sub-circuit 112 and a storage sub-circuit 113 .
  • the output terminal of the data writing sub-circuit 111 is electrically connected to the first terminal of the storage sub-circuit 113, and is configured to transmit the data signal Vd to the storage sub-circuit in response to the control signal (including the first control signal SEL and the second control signal SEL_B).
  • the first end of circuit 113 is, for example, configured to be electrically connected to the ground voltage GND.
  • the driving sub-circuit 112 includes a control electrode (control terminal) 150 , a first electrode (first terminal) 151 and a second electrode (second terminal) 152 , and the control electrode 150 of the driving sub-circuit is electrically connected to the first terminal of the storage sub-circuit 113 .
  • the first electrode 151 of the driving sub-circuit 112 is configured to receive the first power supply voltage VDD
  • the second electrode 152 of the driving sub-circuit 112 is connected to the first electrode 121 of the light emitting element 120 .
  • the driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage of the first terminal of the storage sub-circuit 113 .
  • the second electrode 122 of the light-emitting element 120 is, for example, configured to receive the second power supply voltage VSS.
  • the first power supply voltage VDD is, for example, a high voltage
  • the second power supply voltage VSS is, for example, a low voltage.
  • At least one of the data writing sub-circuit 111 , the driving sub-circuit 112 and the storage sub-circuit 113 is implemented by a transistor, and the transistors used may all be thin film transistors or field effect transistors or other switching devices with the same characteristics , in the embodiments of the present disclosure, a metal-oxide semiconductor field effect transistor is used as an example for description.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • in order to distinguish the two poles of the transistor except the gate it is directly described that one pole is the first pole and the other pole is the second pole.
  • the drain is used as the first pole and the source is used as the second pole. second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltages)
  • the turn-off voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (eg, 0V, -5V, 30-10V, or other suitable voltage).
  • the display panel provided by the embodiments of the present disclosure may adopt a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate, etc. (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetate cellulose (TAC), cyclic olefin polymers (COP) and cyclic olefins Copolymer (COC) etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene glycol terephthalate
  • PE polyethylene
  • the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), that is, the pixel circuit is fabricated on a single crystal silicon substrate.
  • CMOS circuit complementary metal oxide semiconductor circuit
  • the silicon-based process can achieve high precision (for example, PPI can reach 6500 or even more than 10,000).
  • the data writing sub-circuit 111 may include a transmission gate circuit composed of two complementary transistors in parallel with each other; the control signal includes two control signals in opposite phases.
  • the data writing sub-circuit 111 adopts a circuit with a transmission gate structure, which can help to transmit the data signal to the first end of the storage sub-circuit 113 without loss.
  • the data writing subcircuit includes a first control electrode, a second control electrode, a first terminal, such as a signal input terminal, and a second terminal, such as a signal output terminal, and the first control electrode of the data writing subcircuit and
  • the second control electrodes are respectively configured to receive the first control signal and the second control signal
  • the first end of the data writing subcircuit is configured to receive the data signal
  • the second end of the data writing subcircuit and the first end of the storage subcircuit is electrically connected and configured to transmit the data signal to a first end of the storage subcircuit in response to the first control signal and the second control signal.
  • FIG. 2B is a schematic circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 2A .
  • the data writing sub-circuit 111 includes a transfer gate circuit, and the data writing sub-circuit 111 includes a first data writing transistor N1 and a second data writing transistor P1 connected in parallel with each other.
  • the first data writing transistor N1 and the second data writing transistor P1 are N-type metal-oxide semiconductor field effect transistors (NMOS) and P-type metal-oxide semiconductor field effect transistors (PMOS), respectively.
  • NMOS N-type metal-oxide semiconductor field effect transistors
  • PMOS P-type metal-oxide semiconductor field effect transistors
  • the control signal includes a first control signal SEL and a second control signal SEL_B that are mutually inverse, and the gate N1G of the first data writing transistor N1 serves as the first control electrode of the data writing sub-circuit 111 and is configured as Receiving the first control signal SEL, the gate P1G of the second data writing transistor P1 serves as a second control electrode of the data writing sub-circuit, and is configured to receive the second control signal SEL_B.
  • the first pole P1D of the first data writing transistor P1 and the first pole N1D of the first data writing transistor N1 are electrically connected as the first end of the data writing sub-circuit, and are configured to receive the data signal Vd;
  • the second The second pole P1S of the data writing transistor P1 is electrically connected to the second pole N1S of the first data writing transistor N1 as the second end of the data writing sub-circuit, and is electrically connected to the control electrode 150 of the driving sub-circuit 112 .
  • the first data writing transistor N1 and the second data writing transistor P1 have the same size and have the same channel width to length ratio.
  • the data writing sub-circuit 111 utilizes the complementary electrical characteristics of transistors, and has a low on-state resistance regardless of whether it transmits a high level or a low level, so as to have the advantage of the integrity of electrical signal transmission, and can transmit the data signal Vd without is transmitted to the first end of the storage sub-circuit 113 at a loss.
  • the driving sub-circuit 112 includes a driving transistor N2 , for example, the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS).
  • NMOS N-type metal-oxide semiconductor field effect transistor
  • the gate N2G, the first electrode N2D and the second electrode N2S of the driving transistor N2 serve as the control electrode, the first electrode and the second electrode of the driving sub-circuit 112, respectively.
  • the gate N2G of the driving transistor N2 is electrically connected to the second terminal of the data writing sub-circuit 111 and the first terminal of the storage sub-circuit 113 , the first pole N2D of the driving transistor N2 receives the first power supply voltage VDD, and the driving transistor The second end N2S of N2 is connected to the first electrode 121 of the light emitting element 120 .
  • the storage sub-circuit includes a storage transistor N3, such as an N-type metal-oxide semiconductor field effect transistor (NMOS), the storage transistor N3 includes a gate N3G, a first electrode N3D, a second electrode N3S and In the active region between the first electrode and the second electrode, the storage transistor N3 serves as the storage capacitor Cst, the gate N3G of the storage transistor N3 serves as the first capacitor electrode 141 of the storage capacitor, and the The first electrode N3D and the second electrode N3S of the storage transistor are electrically connected. The first electrode, the second electrode and the active region of the storage transistor N3 together serve as the second capacitor electrode 142 of the storage capacitor.
  • NMOS N-type metal-oxide semiconductor field effect transistor
  • the first region, the active region and the second electrode respectively serve as the first region, the second region and the third region of the second capacitor electrode 142.
  • the first region and the third region have the same carrier mobility, and the second region and the third region have the same carrier mobility.
  • the region differs in carrier mobility from the first region and the third region.
  • the first capacitor electrode 141 and the second capacitor electrode 142 serve as the first terminal and the second terminal of the storage sub-circuit 113, respectively.
  • FIG. 2C is an equivalent circuit diagram of FIG. 2B , in which the storage transistor N3 is directly shown in the form of the storage capacitor Cst.
  • the storage transistor N3, the first data writing transistor N1 and the driving transistor N2 are all N-type metal-oxide semiconductor field effect transistors (NMOS), and can be formed by the same process, so that the first data writing transistor N1 can be formed after the first data writing transistor N1 is formed.
  • the storage capacitor Cst is formed synchronously when the transistor N2 is driven, which avoids additionally introducing other electrode layers to form the storage capacitor, thereby reducing the difficulty of the process and saving the cost.
  • the pixel circuit further includes a resistor R, the first end 131 of the resistor R is electrically connected to the second electrode 152 of the driving sub-circuit 112 , and the second end 132 is connected to the first electrode of the light-emitting element 120 121 is electrically connected, that is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor R.
  • the electronic device R By arranging the electronic device R, defects such as dark lines on the display panel caused by the short circuit between the first electrode 121 and the second electrode 122 of the light emitting element 120 in the sub-pixel due to process fluctuations can be avoided.
  • the resistor R is a constant resistance or a variable resistance, and it can also be an equivalent resistance formed by other devices (such as transistors).
  • the resistor R is insulated from the control electrode 150 of the driving sub-circuit 112, that is, the gate N2G of the driving transistor N2, and the resistivity of the resistor R is higher than that of the control electrode of the driving sub-circuit. , that is, the conductivity of the control electrode of the driving sub-circuit is higher than that of the resistor.
  • the resistivity of the resistor is more than ten times the resistivity of the control electrode.
  • the “same layer arrangement” referred to in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Can be the same or different.
  • the materials for forming the precursors of various structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • the "integrated structure” in the present disclosure refers to a structure in which two (or more than two) structures are formed by the same deposition process and patterned by the same patterning process and are connected to each other, and their materials may be the same or different. .
  • control electrodes of the driving sub-circuit and the resistors can be formed in the same patterning process, thereby saving the process.
  • the materials of the resistor and the control electrode of the driving sub-circuit are both polysilicon materials, and the doping concentration of the resistor is lower than that of the control electrode, so the resistor has a higher resistance than the control electrode Rate.
  • the resistors may be intrinsic polysilicon or lightly doped polysilicon and the control electrodes may be heavily doped polysilicon.
  • the materials of the control electrodes and resistors may be different.
  • the materials of the control electrode and the resistor may respectively include a metal and a corresponding metal oxide of the metal.
  • the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials formed by combining the above metals.
  • the light emitting element 120 is embodied as an organic light emitting diode (OLED).
  • the light emitting element 120 may be an OLED with a top emission structure, which may emit red light, green light, blue light, or white light, and the like.
  • the light-emitting element 120 is a Micro OLED (Micro OLED).
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first electrode 121 of the light-emitting element 120 is the anode of the OLED
  • the second electrode 122 is the cathode of the OLED, that is, the pixel circuit has a common cathode structure.
  • the embodiment of the present disclosure does not limit this, and according to the change of the circuit structure, the pixel circuit may also be a common anode structure.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbol SEL can represent both the first control signal and the first control signal.
  • the symbol SEL_B can represent both the second control signal and the second control signal terminal.
  • the symbol GND can represent both the ground voltage and the ground terminal;
  • the symbol VDD can represent both the first power supply voltage terminal and the first power supply voltage, and
  • the symbol VSS can represent both the second power supply voltage terminal and the second power supply voltage.
  • FIG. 2D shows a signal timing diagram of the pixel circuit shown in FIG. 2B .
  • the operation principle of the pixel circuit shown in FIG. 2D will be described below with reference to the signal timing diagram shown in FIG. 2B .
  • the first data writing transistor and the driving transistor are N-type transistors
  • the second data writing transistor is a P-type transistor, but this is not limited in the embodiment of the present disclosure.
  • the data signal Vd is a high grayscale voltage in the display period T1 and a low grayscale voltage in the display period T2.
  • the display process of each frame of image includes a data writing stage 1 and a light-emitting stage 2 .
  • a working process of the pixel circuit includes: in the data writing stage 1, the first control signal SEL and the second control signal SEL_B are both turn-on signals, and the first data writing transistor N1 and the second data writing transistor P1 are turned on , the data signal Vd is transmitted to the gate of the driving transistor N2 through the first data writing transistor N1 and/or the second data writing transistor P1; in the light-emitting stage 2, the first control signal SEL and the second control signal SEL_B are both turned off For the signal, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the driving transistor N2 operates in a saturated state with a constant current, and drives the light-emitting element 120 to emit light.
  • the first control signal SEL and the second control signal SEL_B are differential complementary signals with the same amplitude and opposite phases. This helps to improve the anti-interference performance of the circuit.
  • the first control signal SEL and the second control signal SEL_B may be output by the same gate driving circuit unit (eg, GOA unit), thereby simplifying the circuit.
  • the display panel 10 may further include a data driving circuit 13 and a scan driving circuit 14 .
  • the data driving circuit 13 is configured to send out a data signal, such as the above-mentioned data signal Vd, as required (eg, an image signal input to the display device).
  • the scan driving circuit 14 is configured to output various scan signals, for example, including the above-mentioned first control signal SEL and second control signal SEL_B, which are, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display panel. ).
  • the display panel adopts a silicon substrate as the base substrate 101, and the pixel circuit, the data driving circuit 13 and the scanning driving circuit 14 can all be integrated on the silicon substrate.
  • the data driving circuit 13 and the scanning driving circuit 14 can also be formed in the area corresponding to the display area of the display panel, for example, and not necessarily located in the non-display area. Area.
  • the display panel 10 further includes a control circuit.
  • the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd, and to control the gate driving circuit 13 to apply various scan signals.
  • An example of the control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, including, for example, a processor and a memory, the memory including executable code that the processor executes to execute the detection method described above.
  • the processor may be a central processing unit (CPU) or other form of processing device having data processing capabilities and/or instruction execution capabilities, such as may include a microprocessor, programmable logic controller (PLC), etc. .
  • CPU central processing unit
  • PLC programmable logic controller
  • a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory, among others.
  • Non-volatile memory may include, for example, read only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may execute the functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium, for example, the electrical characteristic parameters obtained in the above detection method, and the like.
  • FIG. 2B and FIG. 2C uses the pixel circuit shown in FIG. 2B and FIG. 2C as an example to illustrate the display panel provided by at least one embodiment of the present disclosure, but the embodiment of the present disclosure is not limited thereto.
  • FIG. 3A is a schematic diagram of a display panel according to some embodiments of the present disclosure.
  • the display panel 10 includes a base substrate 101 on which a plurality of sub-pixels 100 are located.
  • the plurality of subpixels 100 are arranged in a subpixel array, the column direction of the subpixel array is a first direction D1, and the row direction is a second direction D2, the first direction D1 and the second direction D2 intersect, for example, perpendicular to each other.
  • FIG. 3A exemplarily shows two rows and six columns of sub-pixels, that is, two pixel rows and six pixel columns, and the regions of three pixel columns spaced apart from each other are respectively shown by dashed boxes.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC) ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET) ), polyethylene (PE), 5 polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetate cellulose (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer material (COC), etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • PET polyacrylate
  • polyarylate polyetherimide
  • PES polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polyacrylate
  • the base substrate 101 includes single crystal silicon or high-purity silicon.
  • the pixel circuit is formed on the base substrate 101 by a CMOS semiconductor process, for example, an active region of a transistor (including a channel region of the transistor), a first electrode and a second electrode are formed in the base substrate 101 by a doping process, and Each insulating layer is formed by a silicon oxidation process or a chemical vapor deposition process (CVD), and a plurality of conductive layers are formed by a sputtering process to form a wiring structure and the like.
  • the active region of each transistor is located inside the base substrate 101 .
  • Figure 3B shows a cross-sectional view of Figure 3A along section line I-I'. For the sake of clarity, some traces or electrode structures that have no direct connection relationship are omitted in FIG. 3B .
  • the display panel 10 includes a base substrate 101 , a first insulating layer 201 , a polysilicon layer 102 , a second insulating layer 202 , a first conductive layer 301 , a third insulating layer 201 and a third The insulating layer 203 , the second conductive layer 302 , the fourth insulating layer 204 , the third conductive layer 303 , the fifth insulating layer 205 and the fourth conductive layer 304 .
  • the structure in the display panel 10 will be described in layers below, and FIG. 3B will be described together as a reference.
  • FIG. 4A shows the part of the display panel 10 below the first conductive layer 301, that is, the base substrate 101 and the first insulating layer 201 and the polysilicon layer 102 thereon, including the transistors ( P1, N1, N2), storage capacitor Cst (that is, storage transistor N3), and resistor R;
  • FIG. 4B shows a sub-pixel 100 in FIG. 4A, for example, an enlarged schematic view of the sub-pixel at the lower right in FIG. 4A; for clarity
  • the section line II' in FIG. 3A is also correspondingly shown in FIG. 4A .
  • the transmission gate circuit including the first data writing transistor N1 and the second data writing transistor P1 and the driving transistor N2 are located in the storage capacitor Cst
  • the opposite sides of the storage capacitor Cst are located on the opposite sides of the storage capacitor Cst in the first direction D1.
  • the storage transistor N3 serves as the storage capacitor Cst, and the storage transistor N3 includes a gate N3G, a first electrode N3D, a second electrode N3S, and an active region N3a located between the first electrode and the second electrode,
  • the gate N3G of the storage transistor N3 serves as the first capacitor electrode 141 of the storage capacitor Cst, the first electrode N3D and the second electrode N3S of the storage transistor N3 are electrically connected, and the first electrode, The second electrode and the active region N3a together serve as the second capacitor electrode 142 of the storage capacitor.
  • the first region, the second region and the third region, the carrier mobility of the first region and the third region is the same, and the carrier mobility of the second region is different from that of the first region and the third region, as shown in the figure
  • the first region, the second region and the third region of the second capacitor electrode 142 are arranged in sequence along the short side direction of the sub-pixel, that is, the second direction D2, and the carrier mobility of the first region and the third region is Similarly, the carrier mobility of the second region is different from that of the first region and the third region, and the area of the second region is larger than that of the first region and the third region.
  • the material of the active region N3a of the memory transistor N3 is a semiconductor material.
  • the base substrate 101 is a P-type silicon-based substrate, the material of the base substrate 101 is, for example, P-type single crystal silicon, and the active region N3a of the memory transistor N3 is on the P-type silicon-based substrate It is formed by performing N-type light doping, the N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron element.
  • the active region N3a of the storage transistor N3 becomes a conductor, so that the first electrode N3D, the second electrode N3S and the active region N3a of the storage transistor N3 form a conductor structure, serving as the storage capacitor Cst the second capacitive electrode 142 .
  • the resistor R and the driving transistor N2 are located on the same side of the storage capacitor Cst. It can be known from FIGS. 2B and 2C that the second electrode N2S of the driving transistor N2 is connected to the first electrode 121 of the light emitting device 120 through the resistor R, for example, an anode.
  • the resistor R and the drive transistor N2 are located on the same side of the storage capacitor Cst, which can make the distance between the resistor R and the drive transistor N2, especially the first end 131 of the resistor R and the drive transistor N2
  • the distance between the second poles N2S of the N2 is reduced as much as possible, thereby reducing the size of the wiring between the first end of the connecting resistor R and the second pole N2S of the driving transistor N2.
  • the driving transistor N2 and the resistor R are arranged in sequence, and the resistor R is located at the second pole N2S of the driving transistor N2 away from the driving transistor The first pole N2D side of N2.
  • the resistor R is substantially in the shape of an elongated strip extending along the first direction D1, and at the first end 131 and the second end 132 of the resistor R, the resistor R further includes a protrusion toward the driving transistor N2 along the second direction part, which is used to set the contact hole area described later.
  • the first end 131 of the resistor R is provided with a contact hole region 133 for electrically connecting with the second pole N2S of the driving transistor N2.
  • the second end 132 of the resistor R is provided with a contact hole region 134 for electrically connecting with the first electrode 121 of the light emitting element 120 . As shown in FIG. 4B , the first end 131 of the resistor R is closer to the driving transistor N2 than the second end 132 of the resistor R.
  • the transfer gate circuit includes a first data writing transistor N1 and a second data writing transistor P1 , and the second data writing transistor P1 and the first data writing transistor N1 are in the second They are arranged side by side in the direction D2 and are symmetrical about an axis of symmetry along the first direction D1.
  • the gate N1G of the first data writing transistor N1 and the gate P1G of the second data writing transistor P1 are arranged side by side in the second direction D2 and are symmetrical about the symmetry axis along the first direction D1;
  • the first pole N1D of the input transistor N1 and the first pole P1D of the second data writing transistor P1 are arranged side by side in the second direction D2 and are symmetrical about the symmetry axis along the first direction D1;
  • the diode N1S and the second electrode P1S of the second data writing transistor P1 are arranged side by side in the second direction D2 and are symmetrical about the symmetry axis along the first direction D1.
  • the active region N1a of the first data writing transistor N1 and the first The active regions P1a of the two data writing transistors P1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1.
  • the first capacitor electrode 141 of the storage capacitor Cst are insulated in the same layer, and both include polysilicon material; the polysilicon material is doped to form the electrode of the storage capacitor Cst.
  • the first capacitive electrode 141 and the resistor R The doping concentration of the first capacitor electrode 141 of the storage capacitor Cst is higher than that of the resistor R.
  • the conductivity of the resistor R is made lower than that of the first capacitor electrode 141 of the storage capacitor Cst, that is, the resistivity of the resistor R is higher than that of the first capacitor electrode 141 of the storage capacitor Cst.
  • the shortest distance between the channel of the driving transistor N2 and the first data writing transistor N1 is greater than the shortest distance between the channel of the driving transistor N2 and the second data writing transistor N1
  • the shortest distance between the writing transistors P1 that is, the shortest distance between the overlapping portion of the gate and active layer of the driving transistor N2 and the first data writing transistor N1 is greater than the driving transistor N2
  • the shortest distance between the resistor R and the first data writing transistor N1 is smaller than that between the resistor R and the second data writing transistor P1 the shortest distance.
  • the shortest distance between two parts refers to the smallest distance among the distances between any point on one part and any point on the other part.
  • the width of the resistor R is smaller than the gate N1G of the first data writing transistor N1 , the gate P1G of the second data writing transistor P1 and the driving transistor
  • the width of one of the gates N2G of N2, wherein the gate N1G of the first data writing transistor N1, the gate P1G of the second data writing transistor P1 and the gate N2G of the driving transistor N2 are in the second direction D2 extends, and the resistor R extends along the first direction D1.
  • the gates P1G, N1G, N2G, and N3G of the transistors P1, N1-N3 are all disposed in the same layer, all include polysilicon material, and are formed by the same doping process.
  • the gate N3G of the driving transistor N2 and the first capacitor electrode 141 that is, the gate N3G of the storage transistor N3 are connected to each other as an integral structure.
  • the sub-pixel includes a first region 401 and a second region 402 , wherein the second region 402 is an N-type well region formed by N-type heavy doping in the P-type base substrate 101 , the first region 401 is the remaining region in the sub-pixel 100 from which the N-type well region is removed.
  • the second data writing transistor P2 is formed in the second region 402 .
  • a first data writing transistor N1, a driving transistor N2, a storage transistor N3, and a resistor R are formed in the first region 401.
  • FIG. 4B also shows the active regions P1a, N1a, N2a, N3a of each transistor P1, N1-N3.
  • the active regions N1a, N2a, and N3a of the first data writing transistor N1, the driving transistor N2 and the storage transistor N3 are all formed on the P-type substrate 101 by using an N-type light doping process, and they can use the same doping process Synchronized formation.
  • the active region P1a of the second data writing transistor P1 is formed in the second region 402 by a P-type light doping process.
  • the area of the active region N2a of the driving transistor N2 is larger than that of the active region N1a of the first data writing transistor N1 and the active region P1a of the second data writing transistor P1, so that it is possible to obtain
  • the larger aspect ratio helps to improve the driving capability of the driving transistor N2, thereby improving the display effect.
  • the area of the active region N3a of the storage transistor N3 is significantly larger than that of other transistors. Therefore, when the storage transistor N3 is used as the storage capacitor Cst, the capacitance value of the storage capacitor of the sub-pixel can be guaranteed to ensure the display Effect.
  • the first electrodes P1D, N1D, N2D, N3D and the second electrodes P1S, N1S, N2S, and N3S of the transistors P1, N1-N3 are all made by re-doping a portion of their corresponding active regions.
  • the doping process is performed by using the corresponding gate electrode formed subsequently as a mask.
  • the first data writing transistor N1, the driving transistor N2 and the first electrodes N1D, N2D, N3D and the second electrodes N1S, N2S, and N3S of the storage transistor N3 are all N-type heavily doped processes in the first region 401 . formed, they can be formed simultaneously using the same doping process.
  • the first electrode P1D and the second electrode P1S of the second data writing transistor P1 are formed in the second region 402 by a P-type heavy doping process.
  • FIG. 4B also shows the gate contact region 161 , the first electrode contact region 162 and the second electrode contact region 163 of the first data writing transistor N1 , the gate contact region 171 , the first electrode contact region 171 of the second data writing transistor P1 , the first electrode contact region 162 and the second electrode contact region 163 .
  • Each first pole contact area is an area corresponding to the first pole for forming electrical contact
  • each second pole contact area is an area corresponding to the second pole for forming electrical contact
  • each gate contact area is a corresponding gate in the area where electrical contact is made.
  • FIG. 4B also shows contact hole regions 411, 400a, 400b.
  • the contact hole region 411 is located in the second region 402, and is configured to be electrically connected to the first power supply voltage VDD to perform high voltage bias on the N-type substrate where the second data writing transistor P1 is located.
  • the contact hole regions 400a and 400b are located in the first region 401 and are respectively located on both sides of the storage capacitor Cst in the first direction D1.
  • the P-type substrate where N3 is located is biased at low voltage.
  • the contact hole regions 400a and 400b are formed by a P-type heavy doping process, and can be formed synchronously with the first electrode P1D and the second electrode P1S of the second data writing transistor P1.
  • the contact hole region 411 is formed by an N-type heavy doping process, and can be formed in synchronization with the first electrode N1D and the second electrode N1S of the first data writing transistor N1.
  • the two adjacent sub-pixels 100 in the first direction D1 are symmetrical about the symmetry axis along the second direction D2, and the two adjacent sub-pixels 100 in the second direction D2 are symmetrical about the symmetry along the first direction D1 Axisymmetric.
  • the distributions of the transistors for example, including the shape, size, etc. of each transistor
  • storage capacitors for example, the shape, size, etc. of each transistor
  • resistors are symmetrical about the symmetry axis along the second direction D2
  • the corresponding structures in the two sub-pixels are respectively symmetrical about the symmetry axis along the second direction D2.
  • the distributions of transistors, storage capacitors, and resistors in two adjacent sub-pixels 100 in the second direction D2 are symmetrical about the symmetry axis along the first direction D1.
  • This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display panel.
  • this symmetrical arrangement enables some structures in the substrate that are arranged on the same layer and can be connected to each other to be integrally formed. Compared with separate arrangements, the pixel layout can be made more compact, the space utilization rate can be improved, and the resolution of the display panel can be improved. .
  • the second region 402 of the two adjacent sub-pixels 100 in the first direction D1 is an integral structure, and the second region 402 of the two adjacent sub-pixels 100 in the second direction D2
  • the two regions 402 have an integrated structure, that is, the second regions of the adjacent four sub-pixels 100 form an N-type well region 402N.
  • the second data writing transistors P1 of the adjacent four sub-pixels 100 are located in the same N-type well region 402N.
  • the four adjacent sub-pixels 100 form a pixel group 420 .
  • this arrangement can make the arrangement of the pixels more compact under the premise of satisfying the design rules, which helps to improve the resolution of the display panel.
  • the adjacent four sub-pixels 100 share the same contact hole region 411 , and the contact hole region 411 is located at the center of the N-type well region 402N of the pixel group 420 .
  • the above-mentioned two adjacent sub-pixels share the second pole P1S.
  • the above-mentioned two adjacent sub-pixels share the second pole N1S.
  • the gates N1G of the first data writing transistors N1 or the gates P1G of the second data writing transistors P1 of two adjacent sub-pixels 100 in the second direction D2 are mutually connected structure.
  • the gates of the first data writing transistors N1 are configured to receive the same first control signal SEL, and the gates of the second data writing transistors P1 are configured to receive the same second control signal SEL_B.
  • the transistors of the adjacent two sub-pixels in the second direction D2 are mirror-symmetrical, the situation in which the first data writing transistors N1 of the two sub-pixels are adjacent in the second direction D2 alternately is the same as that of the second data writing transistor P1. adjacent situation. Therefore, the gates of the adjacent two first data writing transistors N1 can be directly connected into an integrated structure to form the first control electrode group 191, and the gates of the adjacent second data writing transistors P1 can be directly connected into an integrated structure. structure to form the second control electrode group 192 . This arrangement can make the arrangement of pixels more compact under the premise of satisfying the design rules, which helps to improve the resolution of the display panel.
  • the display panel includes a plurality of pixel unit groups 420 arranged along the first direction D1 and the second direction D2.
  • a silicon-based base substrate 101 is provided, for example, the material of which is P-type single crystal silicon.
  • N-type transistors (such as driving transistors) can be directly fabricated on the P-type silicon substrate, that is, directly doped on the P-type substrate to form the channel region of the N-type transistor, which is conducive to the high-speed performance of NMOS devices. Advantages, improve circuit performance.
  • FIG. 5A shows an N-type well region formed on a base substrate.
  • N-type heavy doping is performed on a P-type silicon substrate to form an N-type well region 402N, including the second region 402 of the sub-pixel, for writing the second data.
  • the second regions 402 of two sub-pixels adjacent in the first direction D1 may be connected to each other, and the second regions 402 of two sub-pixels adjacent in the second direction D2 may be connected to each other.
  • the second regions 402 of four sub-pixels in a pixel group 420 are connected into an integral structure to form an N-type well region 402N of the pixel group 420 , and the N-type well regions of three adjacent pixel groups are shown in FIG. 5A .
  • the undoped region on the base substrate 101 is shielded.
  • FIG. 5B shows the active area pattern on the base substrate
  • the lower figure in FIG. 5C shows the active area pattern formed on the substrate structure shown in FIG. 5A
  • the active region pattern can be obtained by lightly doping the base substrate.
  • an active region pattern of the second data writing transistor P1 is formed in the N-type well region by P-type light doping, which is configured to be subsequently used to form the second data writing transistor P1
  • the first pole P1D, the second pole P1S, and the active region P1a serving as a channel.
  • the active region patterns of the first data writing transistor N1, the driving transistor N2 and the storage transistor N3, the first data writing transistor N1, the driving transistor N2 and the storage transistor are formed by N-type light doping.
  • the active region pattern of N3 is configured to be used to form the first electrodes N1D, N2D, N3D, the second electrodes N1S, N2S, and N3S of the first data writing transistor N1, the driving transistor N2, and the storage transistor N3, and the second electrodes N1S, N2S, and N3S, which are subsequently used as channels, respectively.
  • active regions N1a, N2a, N3a are subsequently used as channels, respectively.
  • N-type doping and P-type doping are required, respectively.
  • a barrier layer needs to be formed to shield the region where the N-type doping is not performed;
  • a barrier layer needs to be formed to shield the region where the P-type doping is not performed.
  • FIG. 5D shows the polysilicon layer pattern on the base substrate
  • the lower figure in FIG. 5E shows the polysilicon layer pattern formed on the substrate structure shown in FIG. 5C .
  • a first insulating layer 201 is formed on the base substrate 101 , and then a polysilicon layer 102 is formed on the first insulating layer 201 . It can be understood by those skilled in the art that, in order to clearly show the relationship between the various film layers, the transparent first insulating layer 201 is omitted in FIG. 4B and FIG. 5E .
  • the first insulating layer 201 includes the gate insulating layer of each transistor, and also includes the dielectric layer 104 of the storage capacitor Cst.
  • the polysilicon layer 102 is configured to form the first capacitor electrode 141, that is, the gate N3G of the memory transistor N3, the resistor R, and the gates P1G, N1G, N2G of the transistors (P1, N1, N2).
  • the gate P1G of the second data writing transistor P1 is located in the second region 402 .
  • the first data writing transistor N1, the gate N2G of the driving transistor N2, the first capacitor electrode 141 and the resistor R are formed on the first region 401 outside the N-type well region.
  • the orthographic projection of the first capacitive electrodes 141 of the four sub-pixels in each pixel unit group on the base substrate is located in the N area formed by the second regions 402 of the four sub-pixels. outside the N-type well region and surrounding the N-type well region.
  • the N-type well region is a rectangle
  • the orthographic projection of the first capacitor electrode 141 of each sub-pixel on the base substrate surrounds one corner of the rectangle; for example, each first capacitor electrode 141 includes a concave structure, the concave
  • the profile of the recessed structure is roughly L-shaped, and one corner of the rectangle protrudes into the orthographic projection of the recessed structure to match the L-shaped profile.
  • the patterns of the polysilicon layers in the two adjacent sub-pixels in the first direction D1 are symmetrical about the symmetry axis along the second direction D2; in the two adjacent sub-pixels in the second direction D2
  • the pattern of the polysilicon layer is symmetrical about the symmetry axis along the first direction D1, that is, the pattern of the polysilicon layer is a symmetrical pattern.
  • the resistors of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction in which they are adjacent.
  • the resistors of the sub-pixels are symmetric about an axis of symmetry along the first direction.
  • the first capacitive electrodes of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and the first capacitance electrodes of adjacent sub-pixels in the second direction The capacitive electrodes are symmetrical about an axis of symmetry along the first direction.
  • the gates of the first data writing transistor N1 and the second data writing transistor P1 of two adjacent sub-pixels in the second direction D2 are respectively symmetrical about the symmetry axis along the first direction D1 .
  • the gates of the first data writing transistor N1 or the second data writing transistor P1 of two adjacent sub-pixels in the second direction D2 are integrally formed.
  • the gates of the first data writing transistor N1 and the second data writing transistor P1 of two adjacent sub-pixels in the first direction D1 are respectively symmetrical about the symmetry axis along the second direction D2 .
  • the first insulating layer 201 is formed on the base substrate by a thermal oxidation method.
  • the material of the first insulating layer is silicon nitride, oxide or oxynitride.
  • a polysilicon material layer is formed on the first insulating layer by a chemical vapor deposition (PVD) process, and then a photolithography process is performed on the polysilicon material layer to form the polysilicon layer 102 .
  • PVD chemical vapor deposition
  • Fig. 5F shows the N-type heavily doped window region of the base substrate
  • Fig. 5G shows the P-type heavily doped window region of the base substrate
  • Fig. 5H shows the N-type heavily doped window region completed on the substrate structure shown in Fig. 5E Schematic diagram of the substrate structure after doping and P-type doping heavily.
  • N-type heavy doping is performed using an N-type heavily doped window region
  • P-type heavy doping is performed using a P-type heavily doped window region on the base substrate on which the polysilicon layer 102 is formed to form Contact hole area for electrical connection.
  • the doped window region includes the source region and the drain region of each transistor, thereby forming a first electrode, such as a drain electrode, and a second electrode, such as a source electrode, of each transistor.
  • the doping window region further includes each contact hole region of the substrate and the contact hole region of the resistor R, for example, including the contact hole regions 400a, 400b, 411, 133, and 134 shown in FIG. 4B.
  • the gate of the transistor is formed of polysilicon material, the polysilicon gate also needs to be doped. During doping, a blocking layer can be formed as required to shield the undoped regions, and only expose the corresponding doped window regions.
  • FIG. 5F and FIG. 5G only illustrate each doping window area.
  • the corresponding barrier layer/mask layer is set to expose the corresponding doping window area and the polysilicon area for doping. Miscellaneous can be.
  • the material of the barrier/mask layer may be a photoresist or an oxide material.
  • a barrier layer 135 is formed corresponding to the resistor R.
  • the resistor R In order to protect the resistance value of the resistor R, the resistor R needs to be shielded during the N-type doping process to prevent the resistor R from being damaged due to doping.
  • the blocking layer 135 shields the main body of the resistor R, and only exposes the contact hole regions 133 and 134 at both ends of the resistor R.
  • 5H only shows the shielding layer 135 in a pair of adjacent sub-pixels that shields the main body of the resistor R, and those skilled in the art can understand that for other sub-pixels, a blocking layer is also required to shield the main body of the resistor R.
  • the blocking layer 135 may be silicon nitride, oxide or oxynitride, or may be a photoresist material. After the doping process is completed, the blocking layer 135 may remain in the display panel or may be removed.
  • the barrier layer 135 of the resistor R may also be formed together with the barrier layers/mask layers in other regions during doping, which is not limited in the embodiments of the present disclosure.
  • N-type doping and P-type heavy doping for example, distribution to form the source and drain regions of the N-type transistor and the source region of the P-type transistor. and drain region.
  • a barrier layer can be formed to shield the region where the N-type heavy doping is not performed; when the P-type heavy doping process is performed, a barrier layer can be formed to shield the region where the P-type heavy doping is not performed.
  • gates, first and second electrodes of transistors N1 - N3 , and contact hole regions 411 , 133 , 134 may be formed through the N-type heavy doping process.
  • the N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron.
  • the gate electrode, the first electrode and the second electrode of the transistor P1 and the contact hole regions 400a and 400b can be formed through the P-type heavy doping process.
  • the P-type doping process may be, for example, an ion implantation process, and the doping element may be phosphorus, for example.
  • the polysilicon pattern can serve as a mask, so that the implantation of ions into the silicon-based substrate occurs on both sides of the polysilicon, thereby forming the first electrode and the second electrode of each transistor. pole, self-alignment is achieved.
  • the resistivity of polysilicon with originally relatively high resistance is reduced through the doping process, and the gates of the transistors and the first capacitor electrode can be formed. Therefore, using polysilicon material as the resistor and gate material has various beneficial effects and saves the process cost.
  • the structure of the display panel shown in FIG. 4A is formed, including each transistor P1 , N1 , N2 , a resistor R, and a storage capacitor Cst.
  • the corresponding transistors, resistors and storage capacitors Cst in two adjacent sub-pixels in the first direction D1 are respectively symmetrical about the symmetry axis along the second direction D2;
  • Corresponding transistors, resistors and storage capacitors Cst in the two sub-pixels are respectively symmetrical about the symmetry axis along the first direction D1.
  • the storage capacitor Cst is the storage transistor T3 as the capacitor.
  • the electrode N3S and the active region N3a between them serve as the second capacitor electrode 142.
  • the region of the base substrate 101 located under the first capacitor electrode 1411 generates inversion charges, so that the The first electrode N3D, the second electrode N3S and the active region N3a between them of the storage transistor N3 form a conductor structure.
  • the orthographic projection of the first capacitive electrode 141 on the base substrate 101 and the orthographic projection of the second capacitive electrode 142 on the base substrate 101 have overlapping regions, the The overlapping area includes a first protrusion protruding toward the driving transistor and a second protrusion protruding toward the first data writing transistor N1.
  • a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, and a fifth insulating layer are sequentially formed on the substrate shown in FIG. 4A 205 and the fourth conductive layer 304, the display panel shown in FIG. 3A is formed.
  • FIG. 6A and 6B respectively show the pattern of the first conductive layer 301 and the situation in which the first conductive layer 301 is disposed on the substrate structure shown in FIG. 4A , and FIG.
  • the via holes correspond to the contact areas in FIG. 4B one-to-one, and are used to electrically connect the contact hole areas with the patterns in the first conductive layer 301 .
  • FIG. 6B also shows the area where the section line II' in FIG. 3A is located. Location.
  • the pattern of the first conductive layer in the two adjacent sub-pixels in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; in the two adjacent sub-pixels in the second direction D2
  • the pattern of the first conductive layer is symmetric about the axis of symmetry along the first direction D1.
  • the pattern of the first conductive layer will be exemplarily described below by taking a sub-pixel as an example.
  • the first conductive layer 301 includes a connection electrode 313 for electrically connecting the first end 131 of the resistor R with the second electrode N2S of the driving transistor N2 .
  • connection electrode 313 is L-shaped as a whole, which includes a first portion extending along the first direction D1 and a second portion extending from the first portion along the second direction D2 toward the resistor R,
  • the free end of the second part of the connection electrode 313 is electrically connected to the first end 131 of the resistor R through the via hole 225 in the second insulating layer 202 ;
  • the hole 226 is electrically connected to the second pole N2S of the driving transistor N2.
  • the orthographic projection of the connection electrode 313 on the base substrate 101 falls within the orthographic projection of the second electrode N2S of the driving transistor N2 on the base substrate 101 .
  • one or more vias 226 may be provided, as shown in FIG. 6B , such as two, to reduce contact resistance.
  • the first conductive layer 301 further includes a connection electrode 314 , the connection electrode 314 is connected to the second end 132 of the resistor R through the via hole 229 in the second insulating layer 202
  • the connection electrode 314 is used for electrical connection with the first electrode 121 of the light-emitting element 120 .
  • the connection electrode 314 is L-shaped, one branch of which is electrically connected to the second end 132 of the resistor R, and the other branch is used to electrically connect to the first electrode 121 of the light-emitting element 120 .
  • the first conductive layer 301 further includes a third capacitor electrode 315 , and the third capacitor electrode 315 is perpendicular to the first capacitor electrode 141 and the second capacitor electrode 142 .
  • the direction of the base substrate 101 overlaps.
  • the third capacitor electrode 315 is located on the side of the first capacitor electrode 141 away from the second capacitor electrode 142, and is configured to be electrically connected to the second capacitor electrode 142; that is, in the direction perpendicular to the base substrate,
  • the second capacitor electrode 142 and the third capacitor electrode 315 are respectively located on both sides of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel capacitor structure and increasing the capacitance value of the storage capacitor Cst.
  • the third capacitor electrode 315 is electrically connected to the first electrode N3D of the storage transistor N3 through the via hole 228 in the second insulating layer 202 to connect with the second capacitor electrode 142 is electrically connected, and the third capacitor electrode 315 is substantially L-shaped and includes a first portion extending along the first direction D1 and a second portion extending from the first portion along the second direction D2 toward the second pole N3S of the storage transistor N3.
  • the width of the portion of the third capacitor electrode 315 close to the first region of the second capacitor electrode 142 in the first direction D1 is greater than that of the third capacitor electrode 315 close to the second capacitor electrode.
  • the via hole 228 in the first direction D1, the via hole 228 is closer to the driving transistor N2, and further away from the data writing sub-circuit, that is, the distance between the via hole 228 and the driving transistor N2 is the first
  • the orthographic projection on the direction D1 is smaller than the orthographic projection of the distance between the via hole 228 and the data writing sub-circuit on the first direction D1. Thereby, the voltage of the driving transistor can be better maintained.
  • the third capacitance electrodes 315 of the two adjacent sub-pixels in the first direction D1 are symmetrical about the symmetry axis along the second direction D2; the third capacitances of the two adjacent sub-pixels in the second direction D2
  • the electrode 315 is symmetric about an axis of symmetry along the first direction D1.
  • their third capacitor electrodes 315 have an integrated structure, that is, the first parts of their third capacitor electrodes 315 are connected as a whole.
  • the first conductive layer 301 further includes a connection electrode 317, the connection electrode 317 is used to electrically connect the second end of the data writing sub-circuit and the first end of the storage sub-circuit, that is, the first data
  • the first electrode N1D of the writing transistor N1 and the first electrode P1G of the second data writing transistor P1 are electrically connected to the first capacitor electrode 141 .
  • connection electrode 317 is, for example, an h-shaped structure, including a first part and a second part extending in parallel along the second direction D2 and a third part connecting the first part and the second part, and the third part is along the
  • the first direction D1 extends and connects the middle part of the first part and one end part of the second part.
  • the first end of the first part of the connection electrode 317 is electrically connected to the first electrode N1D of the first data writing transistor N1 through the via hole 261a in the second insulating layer 202 , and the second end of the first part of the connection electrode 317 passes through
  • the via hole 261b in the second insulating layer 202 is electrically connected to the second electrode P1D of the second data writing transistor P1, and the second part of the connection electrode 317 is connected to the first capacitor electrode through the via hole 261c in the second insulating layer 202 141 is electrically connected.
  • one or more vias 261c may be provided, as shown in FIG. 6B , for example, two vias to reduce contact resistance.
  • the via hole 261c in the second direction D2, is closer to the first region of the second capacitor electrode 142, and further away from the third region of the second capacitor electrode, that is, the via hole 261c and the The distance between the first regions is smaller than the distance between the via hole 261c and the third region.
  • the first conductive layer 301 further includes a first scan line connection part 311 and a second scan line connection part 312, the first scan line connection part 311 is used for electrical connection with the first scan line to The gate of the first data writing transistor N1 is made to receive the first control signal SEL.
  • the second scan line connecting portion 312 is used for electrically connecting with the second scan line so that the gate of the second data writing transistor P1 receives the first control signal SEL_B.
  • the first scan line connecting portion 311 is electrically connected to the gate N1G of the first data writing transistor N1 through the via hole 221 a in the second insulating layer 202
  • the second scan line connecting portion 312 is electrically connected to the gate N1G of the first data writing transistor N1 through the second
  • the via hole 221b in the insulating layer 202 is electrically connected to the gate P1G of the second data writing transistor P1.
  • adjacent sub-pixels in the second direction D1 share the first scan line connection portion 311 or the second scan line connection portion 312 .
  • the first conductive layer 301 further includes a data line connecting portion 316, and the data line connecting portion 316 is used for electrical connection with the data line, so that the second pole N1S of the first data writing transistor N1 and the The second pole P1S of the second data writing transistor P1 receives the data signal Vd transmitted by the data line.
  • the data line connecting portion 316 is in the shape of a strip extending along the second direction D2 , and the first end of the data line connecting portion 316 is connected to the first data writing transistor through the via hole 222 a in the second insulating layer 202 .
  • the second pole N1S of N1 is electrically connected, and the second terminal is electrically connected to the second pole P1S of the second data writing transistor P1 through the hole 222b in the second insulating layer 202 .
  • a plurality of data line connection parts 316 are arranged at intervals in the second direction D2, for example, located at the boundary of two sub-pixel rows. For example, two adjacent sub-pixels in the first direction D1 share one data line connecting portion 316 .
  • the first conductive layer 301 further includes a connection electrode 318, the connection electrode 318 is electrically connected to the first electrode N2D of the driving transistor N2 through the via hole 223 in the second insulating layer 202, and the connection electrode 318 It is configured to introduce the first power supply voltage VDD into the first pole N2D of the driving transistor N2.
  • the first conductive layer 301 further includes a connection electrode 319 .
  • the connection electrode 319 is L-shaped and includes a first portion extending along the first direction D1 and a second portion extending along the second direction D2 .
  • the first portion of the connection electrode 319 includes a first segment and a second segment with different widths, wherein two ends of the second segment are respectively connected to the first segment and the second portion, and the width of the first segment is wider than that of the second segment.
  • the first segment of the first portion of the connection electrode 319 is electrically connected to the second pole N3S of the storage transistor N3 through the via 223a in the second insulating layer 202, and is configured to introduce the ground voltage GND to the second pole N3S of the storage transistor N3.
  • the corner of the L-shaped connection electrode 319 is electrically connected to the contact hole region 400a on the P-type substrate through the via hole 223b in the second insulating layer 202, for connecting the P-type substrate to the ground voltage GND, and connecting the P-type substrate to the ground voltage GND.
  • the substrate bias is low voltage.
  • the second portion of the connection electrode 319 is connected as a single structure.
  • the first direction D1 when the adjacent two sub-pixels are located in different pixel groups, they share the second portion of the connection electrode 319.
  • the second direction D2 when the adjacent two sub-pixels are located in different pixel groups, they share the first part of the connection electrode 319.
  • the first conductive layer 301 further includes connection electrodes 319a and 319b, which are all provided for biasing the substrate of the transistor, for example, for connecting the N-type substrate to the first
  • the power supply voltage terminal is used to receive the first power supply voltage VDD (high voltage), or used to connect the P-type substrate to the ground voltage terminal to receive the ground voltage GND (low voltage), thereby avoiding parasitic effects such as offset effect, improving circuit stability.
  • connection electrodes 319a, 319b are respectively electrically connected to the contact hole regions 400b, 411 in the base substrate 101 through the via holes 224a, 224b in the second insulating layer 202, and the connection electrodes 319a are used to connect to the ground voltage GND to bias the P-type substrate where the first data writing transistor N1 is located.
  • the connection electrode 319b is used to connect to the first power supply voltage VDD to bias the N-type substrate of the second data writing transistor P1.
  • FIG. 7A shows a schematic diagram of the second conductive layer 302
  • FIG. 7B shows the second conductive layer 302 on the basis of the first conductive layer 301
  • FIG. 7B also shows the via hole in the third insulating layer 203
  • the via hole in the third insulating layer 203 is used to connect the pattern in the first conductive layer 301 and the pattern in the second conductive layer 302 .
  • FIG. 7B shows only two rows and six columns of sub-pixels are shown in the figure, and a region of one sub-pixel 100 is shown with a dashed box.
  • each layer structure before the formation of the first conductive layer 301 is omitted in FIG. 7B .
  • the pattern of the second conductive layer in the two adjacent sub-pixels in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; in the two adjacent sub-pixels in the second direction D2
  • the pattern of the second conductive layer is symmetric about a symmetry axis along the first direction D1.
  • the pattern of the second conductive layer will be exemplarily described below by taking a sub-pixel as an example.
  • the second conductive layer 302 includes a connection electrode 324 that is electrically connected to the connection electrode 314 in the first conductive layer 301 through the via hole 239 in the third insulating layer 203 , the connection electrode 324 is used for electrical connection with the first electrode 121 of the light emitting element 120 .
  • the connection electrode 324 has a long strip shape extending along the first direction D1.
  • one or more vias 239 may be provided, as shown in FIG. 7B , for example, two vias to reduce contact resistance.
  • the orthographic projection of the connection electrode 324 on the base substrate 101 substantially falls within the orthographic projection of the connection electrode 314 on the base substrate 101 .
  • the orthographic projection of the connection electrode 324 on the base substrate 101 substantially coincides with the orthographic projection of the branch of the connection electrode 314 extending along the first direction D1 on the base substrate 101 .
  • the second conductive layer 302 includes a first scan line 321, a second scan line 322, a ground line 325, and a power line 328 extending along the second direction D2 .
  • the first scan line 321 is configured to transmit the first scan signal SEL
  • the second scan line 322 is configured to transmit the second scan signal SEL_B
  • the ground line 325 is configured to transmit the ground voltage GND
  • the power line 328 is configured to transmit the first voltage signal VDD.
  • the first scan line 321 , the second scan line 322 , the ground line 325 , and the power supply line 328 are located far from the center of each N-type well region of the row of sub-pixels in the first direction D1 in sequence.
  • each of their first scan line 321 , second scan line 322 , ground line 325 , and power supply line 328 is relative to the direction along the second direction D2 Symmetric on the axis of symmetry.
  • the first scan line 321 is electrically connected to the first scan line connection portion 311 in the first electrode layer 301 through the via hole 231 in the third insulating layer 203, and is used for writing the first data to the first scan line 311.
  • the gate N1G of the transistor N1 provides the first scan signal SEL.
  • the second scan line 322 is electrically connected to the second scan line connection portion 312 in the first electrode layer 301 through the via hole 232 in the third insulating layer 203, and is used for providing the second scan line with the gate P1G of the second data writing transistor P1.
  • a scan signal SEL_B is electrically connected to the second scan line connection portion 312 in the first electrode layer 301 through the via hole 232 in the third insulating layer 203, and is used for providing the second scan line with the gate P1G of the second data writing transistor P1.
  • Both the first scan line 321 and the second scan line 322 meander along the second direction D2, and in the same row of sub-pixels, the first scan line 321 and the second scan line 322 are relative to the symmetry axis along the second direction D2 symmetry.
  • the two adjacent sub-pixels in the second direction D2 For two adjacent sub-pixels in the second direction D2, if the adjacent two sub-pixels are located in the same pixel group, the part of the two sub-pixels where the first scan line 321 and the second scan line 322 are parallel to each other the same distance. If the two adjacent sub-pixels are located in different pixel groups, the distances between the portions of the two sub-pixels where the first scan line 321 and the second scan line 322 are parallel to each other are different.
  • the ground wire 325 is electrically connected to the third capacitor electrode 315 in the first electrode layer 301 through the via hole 233 in the third insulating layer 203 , and is electrically connected to the third capacitor electrode 315 in the first electrode layer 301 through the via hole 234 in the third insulating layer 203 .
  • the first portion of the connection electrode 319 in the first electrode layer 301 extending along the first direction D1 is electrically connected, so that the first electrode N3D and the second electrode N3S of the storage transistor N3 are electrically connected, and both are connected to the ground voltage GND.
  • the ground line 235 is substantially L-shaped and includes a first portion extending along the first direction D1 and a second portion extending from the first portion along the second direction D2 toward the second pole N3S of the storage transistor N3 part two.
  • the orthographic projection of the ground wire 325 on the base substrate 101 partially overlaps with the orthographic projection of the third capacitor electrode 315 on the base substrate 101 .
  • the first part of the ground wire 325 is on the base substrate 101
  • the projection falls within the orthographic projection of the first portion of the third capacitive electrode 315 on the base substrate 101
  • the orthographic projection of the second portion of the grounding line 325 on the base substrate 101 covers the second portion of the third capacitive electrode 315 on the substrate. in the orthographic projection on the base substrate 101 .
  • the power line 328 is electrically connected to the connection electrode 318 in the first conductive layer 301 through the via hole 235 in the third insulating layer 203, and is used to connect to the first electrode of the driving transistor N2 through the connection electrode 318.
  • the N2D provides the first voltage signal VDD.
  • the orthographic projection of the power supply line 328 on the base substrate covers the orthographic projection of the driving transistor N2 on the base substrate 101, so that the driving transistor N2 can be shielded from external interference and ensure the normal operation of the driving transistor N2. Work.
  • the power lines 328 are elongated structures extending along the second direction D2.
  • the second conductive layer 302 further includes a data line connection part 326 , the data line connection part 326 is used for electrical connection with the data line, and is connected to the first through the via hole 236 in the third insulating layer 203
  • the data line connection portion 316 in the conductive layer 301 is electrically connected, so that the second pole N1S of the first data writing transistor N1 and the second pole P1S of the second data writing transistor P1 receive the data signal Vd transmitted by the data line.
  • the data line connecting portion 326 is in the shape of a strip extending along the second direction D2 , and the orthographic projection of the data line connecting portion 326 on the base substrate 101 falls into the projection of the data line connecting portion 316 on the base substrate 101 . in the orthographic projection.
  • the second conductive layer 302 further includes connection electrodes 329 a and 329 b, which are all provided for biasing the substrate of the transistor. For example, for connecting the N-type substrate to the first power supply voltage terminal to receive the first power supply voltage VDD (high voltage), or for connecting the P-type substrate to the ground voltage terminal to receive the ground voltage GND (low voltage), Thereby, parasitic effects such as offset effect can be avoided, and the stability of the circuit can be improved.
  • connection electrodes 329a, 329b are electrically connected to the connection electrodes 319a, 319b in the first conductive layer through the via holes 237, 238 in the third insulating layer 203, respectively, and then are respectively connected to the base substrate
  • the contact hole regions 400b and 411 in 101 are electrically connected, and the connection electrode 329a is used for connecting to the ground voltage GND to bias the P-type substrate where the first data writing transistor N1 is located.
  • the connection electrode 329b is used to connect to the first power supply voltage VDD to bias the N-type substrate of the second data writing transistor P1.
  • FIG. 8A shows a schematic diagram of the third conductive layer 303
  • FIG. 8B shows the third conductive layer 303 based on the second conductive layer 302
  • FIG. 7B also shows the via holes in the fourth insulating layer 204
  • the vias in the fourth insulating layer 204 are used to connect the patterns in the second conductive layer 302 and the patterns in the third conductive layer 303 .
  • only two rows and six columns of sub-pixels are shown in the figure, and a region of one sub-pixel 100 is shown with a dashed box.
  • each layer structure before forming the first conductive layer 301 is omitted in FIG. 8B .
  • the third conductive layer 303 includes a connection electrode 334 that is electrically connected to the connection electrode 324 in the second conductive layer 302 through the via hole 249 in the fourth insulating layer 204 , the connection electrode 334 is used for electrical connection with the first electrode 121 of the light emitting element 120 .
  • the connection electrode 334 has a long strip shape extending along the first direction D1.
  • the orthographic projection of the connection electrode 334 on the base substrate 101 partially overlaps the orthographic projection of the connection electrode 324 on the base substrate 101 .
  • one or more vias 249 may be provided, as shown in FIG. 8B , for example, two vias to reduce contact resistance.
  • the third conductive layer 303 includes a plurality of power lines 338, a plurality of data lines 336, and a plurality of ground lines 335 extending along the first direction D1.
  • a plurality of power lines 338, a plurality of data lines 336, and a plurality of ground lines 335 are alternately arranged along the second direction D2.
  • the ground line 335 is configured to transmit the ground voltage GND
  • the power line 338 is configured to transmit the first voltage signal VDD
  • the data line 336 is configured to transmit the data line signal Vd.
  • each column of sub-pixels corresponds to a data line 336, a power line 338 and a ground line 335.
  • the data line 336 runs through the corresponding column of sub-pixels along the first direction D1
  • the power line 338 and the connection line 335 are respectively disposed on both sides of the data line 336 .
  • the data line 336 is electrically connected to the data line connection portion 326 in the second conductive layer 302 through the via hole 246 in the fourth insulating layer 204, so that the first data is written to the second of the transistor N1.
  • the pole N1S and the second pole P1S of the second data writing transistor P1 receive the data signal Vd transmitted by the data line.
  • the data lines 336 meander along the first direction D1, so that a predetermined distance is maintained between the data lines 336 and the power lines 338, the ground lines 335 and the connection electrodes 334 provided on the same layer, so as to avoid the data lines 336
  • the distance from any one of the power line 338 , the ground line 335 and the connection electrode 334 provided on the same layer is too close, which will adversely affect the transmission of the data signal Vd.
  • the power supply line 338 is electrically connected to the connection electrode 329b in the second conductive layer 302 through the via hole 241 in the fourth insulating layer 204, for introducing the first power supply voltage VDD to write the second data
  • the N-type substrate of the input transistor P1 is biased.
  • the power lines 338 are also electrically connected to the power lines 328 in the second conductive layer 302 through the vias 242 in the fourth insulating layer 204 .
  • one or more vias 242 may be provided, as shown in FIG. 8B , for example, three vias to reduce contact resistance.
  • the power supply lines 338 in the third electrode layer 303 and the power supply lines 328 in the second electrode layer 302 are electrically connected to each other, and the plurality of power supply lines 328 extending along the first direction D1 and the power supply lines 328 extending along the second direction D2 are electrically connected to each other.
  • the plurality of power supply lines 328 formed in a mesh structure provide the first power supply voltage VDD for each sub-pixel.
  • the ground line 335 is electrically connected to the connection electrode 329a in the second conductive layer 302 through the via hole 243 in the fourth insulating layer 204, for introducing the ground voltage GND to the first data writing transistor
  • the P-type substrate of N1 is biased.
  • the ground wire 335 is also electrically connected to the ground wire 325 in the second conductive layer 302 through the via hole 244 in the fourth insulating layer 204 .
  • one or more vias 244 may be provided, as shown in FIG. 8B , for example, two vias to reduce contact resistance.
  • the ground wires 335 in the third electrode layer 303 and the ground wires 325 in the second electrode layer 302 are electrically connected to each other, and the plurality of ground wires 335 extending along the first direction D1 are connected to the ground wires 335 extending along the second direction D2
  • the plurality of grounding lines 325 formed in the network form a mesh structure, and provide the grounding voltage GND for each sub-pixel.
  • FIG. 9A shows a schematic diagram of the fourth conductive layer 304
  • FIG. 9B shows the fourth conductive layer 304 based on the third conductive layer 303
  • FIG. 9B also shows the via holes in the fifth insulating layer 205
  • the vias in the fifth insulating layer 205 are used to connect the patterns in the third conductive layer 303 and the patterns in the fourth conductive layer 304 .
  • only two rows and six columns of sub-pixels are shown in the figure, and a region of one sub-pixel 100 is shown with a dashed box.
  • each layer structure before forming the first conductive layer 301 is omitted in FIG. 9B .
  • the fourth conductive layer 304 includes a connection electrode 344 that is electrically connected to the connection electrode 334 in the third conductive layer 303 through the via hole 259 in the fifth insulating layer 205 , the connection electrode 344 is used for electrical connection with the first electrode 121 of the light emitting element 120 .
  • one or more vias 249 may be provided, as shown in FIG. 9B , for example, two vias to reduce contact resistance.
  • the fourth conductive layer 304 includes a connection electrode 345 and a connection electrode 346 , and the connection electrode 345 and the connection electrode 346 are connected to the third electrode layer through the via holes 255 and 256 in the fifth insulating layer 205 , respectively.
  • Power line 338 in 303 is electrically connected. Both the connection electrode 345 and the connection electrode 346 are connected in parallel with the power supply line 338 in the third electrode layer 303, thereby reducing the transmission resistance of the power supply line 338 and facilitating the transmission of the first power supply voltage VDD.
  • connection electrodes 345 and the connection electrodes 346 are both strip-shaped extending along the first direction D1.
  • each of the via holes 255 and the via holes 256 may be provided as one or more, as shown in FIG. 9B , for example, two, to reduce the contact resistance.
  • the fourth conductive layer 304 further includes a connection electrode 347 and a connection electrode 348 .
  • the connection electrode 347 and the connection electrode 348 are electrically connected to the ground line 335 in the third electrode layer 303 through the via hole 257 and the via hole 258 in the fifth insulating layer 205, respectively.
  • Both the connection electrode 347 and the connection electrode 348 are connected in parallel with the ground wire 335 in the third electrode layer 303 , thereby reducing the transmission resistance of the ground wire 335 and facilitating the transmission of the first power supply voltage VDD.
  • connection electrodes 347 and the connection electrodes 348 are both strip-shaped extending along the first direction D1.
  • each of the via holes 257 and the via holes 258 may be provided as one or more, as shown in FIG. 9B , such as two, to reduce the contact resistance.
  • each via can be electrically conductive by being additionally filled with a conductive material such as tungsten.
  • FIG. 9B also shows the contact hole area 349 of the connection electrode 344 , and the contact hole area 349 is used for electrical connection with the first electrode 121 of the light emitting element 120 .
  • the display panel 10 further includes a sixth insulating layer 206 , and a via hole 267 is formed in the sixth insulating layer 206 corresponding to the contact hole region 349 of the connecting electrode 344 for electrically connecting the subsequent light-emitting elements 120
  • the first electrode 121 is, for example, an anode
  • the via hole 267 is also called an anode via hole 267.
  • the via hole 267 is filled with a conductive material (such as tungsten), and then undergoes a polishing process (such as chemical mechanical polishing) to form a flat surface, for forming the light emitting element 120 .
  • the orthographic projection of the anode via 267 on the base substrate 101 at least partially overlaps with the orthographic projection of the first capacitor electrode 141 on the base substrate 101 .
  • the orthographic projection of the anode via hole 267 on the base substrate 101 at least partially overlaps the orthographic projection of the third capacitor electrode 315 on the base substrate 101 .
  • the number of the vias 267 is at least two.
  • the number of contact hole regions for electrical connection on the connection electrodes 314 , 324 , 334 , and 344 connected to the first electrode 121 of the light emitting element 120 can be one or more, which reduces the number of connection electrodes
  • the contact resistance between the resistor R and the first electrode 121 of the light-emitting element 120 is reduced, thereby reducing the voltage on the transmission path of the data signal from the resistor R to the first electrode 121 It can alleviate the problems of color shift and display unevenness caused by the loss of anode potential (gray scale loss) caused by the voltage drop, and improve the display effect.
  • the light-emitting element 120 includes a first electrode 121 , a light-emitting layer 123 and a second electrode 122 sequentially disposed on the sixth insulating layer 206 .
  • the first electrode 121 and the second electrode 122 are the anode and the cathode of the OLED, respectively.
  • the plurality of first electrodes 121 are arranged in the same layer and spaced apart, and correspond to the plurality of sub-pixels one-to-one.
  • the second electrode 122 is a common electrode, and the entire surface is arranged in the display panel 10 .
  • the display panel further includes a first encapsulation layer 124 , a color filter layer 125 , a cover plate 126 and the like located on the side of the light-emitting element 120 away from the base substrate 101 .
  • the first encapsulation layer 124 is configured to seal the light-emitting element to prevent damage to the device caused by the penetration of external moisture and oxygen into the light-emitting element and the pixel circuit.
  • the encapsulation layer 124 includes organic thin films or a structure in which organic thin films and inorganic thin films are alternately stacked.
  • a water absorption layer may also be disposed between the encapsulation layer 124 and the light-emitting element, which is configured to absorb the light-emitting element produced in the early stage.
  • the display panel may further include a second encapsulation layer 127 located between the color filter layer 125 and the cover plate 126 , and the second encapsulation layer 127 may be used for the color filter layer 125 form protection.
  • the light-emitting element 120 is configured to emit white light, and combined with the color filter layer 124 to realize full-color display.
  • the light-emitting element 120 is configured to emit light of three primary colors, and the color filter layer 124 is not necessary at this time.
  • the embodiments of the present disclosure do not limit the manner in which the display panel 10 realizes full-color display.
  • the materials of the first to fourth conductive layers are metal materials, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg) ), tungsten (W) and alloy materials composed of the above metals.
  • the materials of the first to fourth conductive layers may also be conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), and the like.
  • the materials of the first insulating layer to the sixth insulating layer are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon oxynitrides. , or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • the light-emitting element 120 is a top emission structure
  • the first electrode 121 is reflective and the second electrode 122 is transmissive or semi-transmissive.
  • the first electrode 121 is a high work function material to act as an anode, such as an ITO/Ag/ITO stack structure
  • the second electrode 122 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the display device 40 includes any of the above-mentioned display panels 10.
  • the display device in this embodiment may be: a display, an OLED panel, an OLED TV, Electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and any other product or component with display function.

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Abstract

一种显示面板（10）和显示装置（40），显示面板（10）包括衬底基板（101）以及在衬底基板（101）上的子像素（100），其中，子像素（100）包括像素电路和发光元件，像素电路包括数据写入子电路（111）、存储子电路（113）、驱动子电路（112）。其中，存储子电路（113）包括存储电容（Cst），存储电容（Cst）包括相对设置的第一电容电极（141）和第二电容电极（142），第二电容电极（142）位于衬底基板（101）和第一电容电极（141）之间，第二电容电极（142）包括沿子像素（100）的短边方向依次排列的第一区域、第二区域和第三区域，第二区域载流子迁移率不同于第一区域和第三区域载流子迁移率，第二区域的面积大于第一区域和第三区域的面积，其中驱动子电路（112）的控制电极（150）与第一电容电极（141）为同层设置的一体结构。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
微型OLED(Micro OLED)显示器涉及有机发光二极管(OLED)技术和CMOS技术的结合，与光电子产业和微电子产业的交叉集成相关，促进了新一代微型显示技术的发展，也推进了硅上有机电子、甚至是硅上分子电子的研究和发展。
微型OLED(Micro OLED)显示器具有优秀的显示特性，例如分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等，具有广阔的发展前景。
公开内容
本公开一些实施例提供一种显示面板，所述显示面板包括衬底基板以及在所述衬底基板上的子像素，其中，所述子像素包括像素电路和发光元件，所述像素电路包括数据写入子电路、存储子电路、驱动子电路：
所述数据写入子电路配置为响应于控制信号将数据信号传输至所述存储子电路，
所述驱动子电路包括控制电极、第一电极和第二电极，所述驱动子电路的控制电极与所述存储子电路耦接，所述驱动子电路的第一电极配置为接收第一电源电压，所述驱动子电路的第二电极与发光元件的第一电极耦接，所述驱动子电路配置为，所述驱动子电路配置为响应于所述驱动子电路的控制电极的电压驱动所述发光元件发光，
其中，所述存储子电路包括存储电容，所述存储电容包括相对设置的第一电容电极和第二电容电极，所述第一电容电极和第二电容电极分别作为所述存储子电路的第一端和第二端，所述第二电容电极位于所述衬底基板和所述第一电容电极之间，所述第二电容电极包括沿所述子像素的短边方向依次排列的第一区域、第二区域和第三区域，所述第二区域载流子迁移率不同于第一区域和第三区域载 流子迁移率，所述第二区域的面积大于第一区域和第三区域的面积，
其中所述驱动子电路的控制电极与所述第一电容电极为同层设置的一体结构。
在一些实施例中，所述像素电路还包括电阻器，所述电阻器串接在所述驱动子电路的第二电极和所述发光元件的第一电极之间，所述电阻器与所述驱动子电路的控制电极同层且分离设置，且所述电阻器的电阻率高于所述驱动子电路的控制电极的电阻率。
在一些实施例中，所述数据写入子电路包括传输门电路，所述传输门电路包括第一数据写入晶体管和第二数据写入晶体管，所述第一数据写入晶体管和第二数据写晶体管均包括栅极、第一极和第二极，所述控制信号包括第一控制信号和第二控制信号，
所述第一数据写入晶体管的栅极配置为接收所述第一控制信号，所述第二数据写入晶体管的栅极配置为接收所述第二控制信号，所述第一数据写入晶体管的第一极和所述第二数据写入晶体管的第一极耦接，且均与所述存储子电路的第一端以及驱动子电路的控制电极耦接，所述第一数据写入晶体管的第二极和所述第二数据写入晶体管的第二极耦接，均配置为接收所述数据信号。
在一些实施例中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极、第一极和第二极分别作为所述驱动子电路的控制电极、第一电极和第二电极。
在一些实施例中，所述第一数据写入晶体管以及驱动晶体管均为N型金属-氧化物半导体场效应晶体管，所述第二数据写入晶体管为P型金属-氧化物半导体场效应晶体管。
在一些实施例中，在平行于所述衬底基板的第一方向上，所述传输门电路和所述驱动晶体管分别位于所述存储电容的两侧。
在一些实施例中，在平行于所述衬底基板的第一方向上，所述电阻器和所述驱动晶体管位于所述存储电容的同侧。
在一些实施例中，所述驱动晶体管的沟道与所述第一数据写入晶体管之间的最短距离大于所述驱动晶体管的沟道与所述第二数据写入晶体管之间的最短距离。
在一些实施例中，所述电阻器与所述第一数据写入晶体管之间的最短距离小 于所述电阻器与所述第二数据写入晶体管之间的最短距离。
在一些实施例中，在平行于所述衬底基板且垂直于所述第一方向的第二方向上，所述第二数据写入晶体管和所述第一数据写入晶体管依次排列，所述驱动晶体管与所述电阻器依次排列，所述第二方向为所述子像素的短边方向。
在一些实施例中，所述电阻器为沿第一方向延伸的长条形，所述电阻器位于所述驱动晶体管的第二极远离所述驱动晶体管的第一极一侧。
在一些实施例中，所述电阻器的宽度小于所述第一数据写入晶体管的栅极、所述第二数据写入晶体管的栅极以及驱动晶体管的栅极中的一个的宽度。
在一些实施例中，所述驱动晶体管的栅极、所述第一数据写入晶体管的栅极、所述第二数据写入晶体管的栅极、所述第一电容电极以及所述电阻器同层设置。
在一些实施例中，所述存储电容还包括第三电容电极，在垂直于所述衬底基板的方向上，所述第三电容电极位于所述第一电容电极远离所述第二电容电极的一侧，并通过第一过孔与所述第二电容电极的第一区域耦接。
在一些实施例中，所述第三电容电极在衬底基板上的正投影落入所述第二电容电极在在衬底基板上的正投影内，且所述第三电容电极在衬底基板上的正投影与所述第一电容电极在衬底基板上的正投影部分重叠。
在一些实施例中，所述显示面板还包括接地线，配置为耦接所述第二电容电极的第一区域和第三区域，并将所述第二电容电极的第一区域和第三区域接入接地电压，在垂直于所述衬底基板的方向上，所述接地线位于所述第三电容电极远离所述第二电容电极的一侧，所述接地线在衬底基板上的正投影与所述述第三电容电极在衬底基板上的正投影部分重叠。
在一些实施例中，第二数据写入晶体管和所述第一数据写入晶体管沿所述第二方向并排设置，且关于沿所述第一方向的对称轴对称。
在一些实施例中，所述的显示面板还包括4个所述子像素，所述4个子像素构成一个像素单元组，其中，所述4个子像素沿第一方向和第二方向排为阵列，所述第一方向与所述第二方向相互垂直，所述4个子像素的第二数据写入晶体管在所述衬底基板的正投影位于所述衬底基板中的同一N型阱区内。
在一些实施例中，在所述第一方向上相邻的子像素的电阻器关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的电阻器关于沿所述第一方 向的对称轴对称。
在一些实施例中，在第一方向上相邻的两个子像素的传输门电路关于沿所述第二方向的对称轴对称，在第二方向上相邻的两个子像素的传输门电路关于沿所述第一方向的对称轴对称。
在一些实施例中，在第一方向上相邻的两个子像素的驱动晶体管关于沿所述第二方向的对称轴对称，在第二方向上相邻的两个子像素的驱动晶体管关于沿所述第一方向的对称轴对称。
在一些实施例中，在所述第一方向上相邻的子像素的第一电容电极关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的第一电容电极关于沿所述第一方向的对称轴对称。
在一些实施例中，所述4个子像素中的第一电容电极在所述衬底基板的正投影位于所述N型阱区外，且环绕所述N型阱区设置。
在一些实施例中，所述第三电容电极靠近第二电容电极第一区域的部分在第一方向上的宽度大于所述第三电容电极靠近第二电容电极第三区域的部分在第一方向上的宽度。
在一些实施例中，所述子像素还包括用于连接像素电路和发光元件的阳极过孔，所述阳极过孔在衬底基板上的正投影与所述第一电容电极在衬底基板上的正投影至少部分重叠。
在一些实施例中，所述子像素还包括用于连接像素电路和发光元件的阳极过孔，所述阳极过孔在衬底基板上正投影与所述第三电容电极在衬底基板上的正投影至少部分重叠。
在一些实施例中，所述像素电路还包括：
连接电极，配置耦接所述数据写入子电路和所述存储电容的第一电容电极，
所述连接电极通过第二过孔与所述第一电容电极耦接，所述第二过孔与所述第一区域之间的距离小于所述第二过孔与所述第三区域之间的距离。
在一些实施例中，所述第一过孔与所述驱动晶体管之间的距离小于所述第一过孔与所述数据写入子电路之间的距离。
在一些实施例中，所述第一电容电极在所述衬底基板上的正投影和所述第二电容电极在所述衬底基板上的正投影具有交叠区域，所述交叠区域包括朝向所述 驱动晶体管凸出的第一突出部和朝向所述第一数据写入晶体管凸出的第二突出部。
本公开实施例提供一种显示装置，包括前述的显示面板。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1是本公开一些实施例提供的显示面板的框图；
图2A为本公开一些实施例提供的像素电路的示意图；
图2B为本公开一些实施例提供的像素电路的示意图；
[根据细则91更正 27.05.2021]　
图2C为图2B的等效电路图；
[根据细则91更正 27.05.2021]　
图2D示出了图2B所示像素电路的信号时序图；
图3A为本公开一些实施例提供的显示面板的示意图；
图3B为图3A沿剖面线I-I’的剖视图；
图4A为本公开一些实施例提供的显示面板的示意图；
图4B为图4A中一个子像素的示意图；
图5A-图5H示出了图4A所示显示面板的制作步骤图；
图6A-6B为本公开一些实施例提供的显示面板的第一导电层的示意图；
图7A-7B为本公开一些实施例提供的显示面板的第二导电层的示意图；
图8A-8B为本公开一些实施例提供的显示面板的第三导电层的示意图；
图9A-9B为本公开一些实施例提供的显示面板的第四导电层的示意图；
图10为本公开一实施例提供的显示装置的示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节 的情况下也可以被实施。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似地，第二元件可以被命名为第一元件。如在这里使用的术语“和/或”包括一个或多个相关所列的项目的任意组合和所有组合。
应该理解的是，当元件或层被称作“形成在”另一元件或层“上”时，该元件或层可以直接地或间接地形成在另一元件或层上。也就是，例如，可以存在中间元件或中间层。相反，当元件或层被称作“直接形成在”另一元件或层“上”时，不存在中间元件或中间层。应当以类似的方式来解释其它用于描述元件或层之间的关系的词语(例如，“在...之间”与“直接在…之间”、“相邻的”与“直接相邻的”等)。
本文中使用的术语仅是为了描述特定实施例的目的，而不意图限制实施例。如本文中所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，当在此使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组合。
在本文中，如无特别说明，表述“位于同一层”、“同层设置”一般表示的是：第一部件和第二部件可以使用相同的材料并且可以通过同一构图工艺形成。表述“位于不同层”、“不同层设置”一般表示的是：第一部件和第二部件通过不同构图工艺形成。
本文中，如无特别说明，第一部件和第二部件“耦接”指的是第一部件和第二部件之间存在物理连接，以在两者之间存在信号，例如电信号、磁信号等的交互，其具体实现方式可以包括直接电连接，还可以包括通过其他电子元件进行连接。
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示领域，随着高分辨率产品的快速发展，对显示面板的结构设计，例如像素和信号线的排布等都提出了更高的要求。例如，相对于分辨率为4K的OLED显示装置，大尺寸、分辨率为8K的OLED显示装置由于需要设置的子像素单元的个数成倍增加，像素密度相应地成倍增大，一方面信号线的线宽也相应变小，导致信号线的自身电阻变大；另一方面信号线之间的交叠情形变多，导致信号线的寄生电容变大，这 些导致信号线的阻容负载变大。相应地，阻容负载引起的信号延迟(RC delay)以及电压降(IR drop)、电压升(IR rise)等现象也会变得严重。这些现象会严重影响显示产品的显示品质。
微型OLED(Micro OLED)显示器通常具有小于100微米的尺寸，例如小于50微米的尺寸等，涉及有机发光二极管(OLED)技术和CMOS技术的结合，将OLED阵列制备在包括CMOS电路的硅基基板上。
微型OLED广泛运用于AR，VR领域，随着技术不断发展其要求实现更高的分辨率，因此对显示面板的结构设计，例如像素和信号线的排布等都提出了更高的要求。
本公开至少一个实施例提供的显示面板，通过设计中的优化的布图布线设计处理，可以实现5.45um×13.6um的亚像素面积，实现了高的分辨率(PPI)和像素电路阵列的优化排布，并具有较好的显示效果。
图1是本公开一些实施例提供的显示面板的框图。如图1所示，该显示面板10包括阵列分布的多个子像素100、多条扫描线11和多条数据线12。每个子像素100包括发光元件和驱动该发光元件的像素电路。多条扫描线11和多条数据线12彼此交叉在显示区中定义出阵列分布的多个像素区，每个像素区中设置一个子像素100的像素电路。
如图1所示，该显示面板还可以包括位于非显示区中的栅极驱动子电路13和数据驱动子电路14。该栅极驱动子电路13通过扫描线11与像素电路连接以提供各种控制信号，例如扫描信号，该数据驱动子电路14通过数据线12与像素电路连接以提供数据信号。其中，图1中示出的栅极驱动子电路13和数据驱动子电路14，扫描线11和数据线12在显示面板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
在一些实施例中，显示面板10还可以包括控制电路。例如，该控制电路配置为控制数据驱动子电路14施加该数据信号，以及控制栅极驱动子电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令 执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易20失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路根据需要可以包括驱动子电路、数据写入子电路、和存储子电路，根据需要还可以包括补偿子电路、发光控制子电路、复位电路等。
图2A为本公开一些实施例提供的像素电路的示意图。如图2A所示，该像素电路包括数据写入子电路111、驱动子电路112和存储子电路113。
数据写入子电路111的输出端与存储子电路113的第一端电连接，并配置为响应于控制信号(包括第一控制信号SEL和第二控制信号SEL_B)将数据信号Vd传输至存储子电路113的第一端。存储子电路113的第二端例如配置为电连接接地电压GND。
驱动子电路112包括控制电极(控制端)150、第一电极(第一端)151和第二电极(第二端)152，驱动子电路的控制电极150与存储子电路113的第一端电连接，驱动子电路112的第一电极151配置为接收第一电源电压VDD，驱动子电路112的第二电极152与发光元件120的第一电极121连接。驱动子电路112配置为响应于存储子电路113的第一端的电压驱动发光元件120发光。该发光元件120的第二电极122例如配置为接收第二电源电压VSS。在一些实施例中，第一电源电压VDD例如为高电压，第二电源电压VSS例如为低电压。
本公开的实施例中数据写入子电路111、驱动子电路112和存储子电路113中的至少一个采用晶体管来实现，采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以金属-氧化物半导体场效应晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了 区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，例如为将漏极作为第一极，将源极作为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、30-10V或其他合适的电压)。
本公开实施例提供的显示面板可以采用刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。本公开的实施例均以硅基板为例进行说明，也即像素结构制备于硅基板上，然而，本公开实施例对此不作限制。
在一实施例中，该像素电路包括互补型金属氧化物半导体电路(CMOS电路)，也即该像素电路制备于单晶硅衬底基板上。有赖于成熟的CMOS集成电路技术，硅基工艺可以实现较高的精度(例如PPI可以达到6500甚至一万以上)。
在本公开一些实施例中，该数据写入子电路111可以包括由互补的两个晶体管彼此并联构成的传输门电路；该控制信号包括反相的两个控制信号。该数据写入子电路111采用传输门结构的电路可以有助于使数据信号没有损失地传输到存储子电路113的第一端。具体地，数据写入子电路包括第一控制电极、第二控制电极、第一端，例如为信号输入端和第二端，例如为信号输出端，数据写入子电路的第一控制电极和第二控制电极分别配置为接收第一控制信号和第二控制信号，数据写入子电路的第一端配置为接收数据信号，数据写入子电路的第二端与存储子电路的第一端电连接，并配置为响应于所述第一控制信号和所述第二控制信号将所述数据信号传输至所述存储子电路的第一端。
图2B为图2A所示像素电路的一种具体实现示例的电路示意图。如图2B所示，数据写入子电路111包括传输门电路，该数据写入子电路111包括彼此并联的第一数据写入晶体管N1和第二数据写入晶体管P1。该第一数据写入晶体管 N1和第二数据写入晶体管P1分别为N型金属-氧化物半导体场效应晶体管(NMOS)和P型金属-氧化物半导体场效应晶体管(PMOS)。该控制信号包括互为反相的第一控制信号SEL和第二控制信号SEL_B，该第一数据写入晶体管N1的栅极N1G作为该数据写入子电路111的第一控制电极，并配置为接收该第一控制信号SEL，该第二数据写入晶体管P1的栅极P1G作为该数据写入子电路的第二控制电极，并配置为接收该第二控制信号SEL_B。该第一数据写入晶体管P1的第一极P1D和第一数据写入晶体管N1的第一极N1D电连接作为该数据写入子电路的第一端，并配置为接收数据信号Vd；第二数据写入晶体管P1的第二极P1S与第一数据写入晶体管N1的第二极N1S电连接作为该数据写入子电路的第二端，并与驱动子电路112的控制电极150电连接。
在一些实施例中，该第一数据写入晶体管N1和第二数据写入晶体管P1大小相同，具有相同的沟道宽长比。
该数据写入子电路111利用了晶体管互补的电学特性，无论传输高电平还是低电平，都具有较低的开态电阻，从而具有电学信号传输完整性的优势，可以将数据信号Vd没有损失地传输至存储子电路113的第一端。
如图2B所示，该驱动子电路112包括驱动晶体管N2，例如，该驱动晶体管N2为N型金属-氧化物半导体场效应晶体管(NMOS)。该驱动晶体管N2的栅极N2G、第一极N2D和第二极N2S分别作为驱动子电路112的控制电极、第一电极和第二电极。具体地，驱动晶体管N2的栅极N2G与数据写入子电路111的第二端以及存储子电路113的第一端电连接，驱动晶体管N2的第一极N2D接收第一电源电压VDD，驱动晶体管N2的第二端N2S与发光元件120的第一电极121连接。
如图2B所示，存储子电路包括存储晶体管N3，例如为N型金属-氧化物半导体场效应晶体管(NMOS)，所述存储晶体管N3包括栅极N3G，第一极N3D，第二极N3S以及位于所述第一极和第二极之间的有源区，所述存储晶体管N3作为存储电容Cst，所述存储晶体管N3的栅极N3G作为所述存储电容的第一电容电极141，所述存储晶体管的第一极N3D和第二极N3S电连接，所述存储晶体管N3的第一极、第二极以及有源区共同作为存储电容的第二电容电极142，所述存储晶体管N3的第一极、有源区以及第二极分别作为第二电容电极142的第 一区域，第二区域和第三区域，所述第一区域和第三区域载流子迁移率相同，所述第二区域与第一区域和第三区域载流子迁移率不同。所述第一电容电极141和第二电容电极142分别作为所述存储子电路113的第一端和第二端。具体可以参加图2C，图2C为图2B的等效电路图，其中将存储晶体管N3直接以存储电容Cst的形式示出。
存储晶体管N3与第一数据写入晶体管N1以及驱动晶体管N2均为N型金属-氧化物半导体场效应晶体管(NMOS)，可以采用相同的工艺形成，由此可以在形成第一数据写入晶体管N1以及驱动晶体管N2时同步形成存储电容Cst，避免了额外引入其他电极层来形成存储电容，由此可以降低工艺难度，节约成本。
如图2B和2C所示，该像素电路还包括电阻器R，电阻器R的第一端131与驱动子电路112的第二电极152电连接，第二端132与发光元件120的第一电极121电连接，也即驱动子电路112的第二电极152通过电阻器R与发光元件120的第一电极121电连接。通过设置电子器R可以避免由于工艺波动导致子像素中的发光元件120的第一电极121与第二电极122发生短路而造成的显示面板出现暗线等不良。
例如，该电阻器R为恒定电阻或可变电阻，也可以是其它器件(如晶体管)形成的等效电阻。
例如，该电阻器R与驱动子电路112的控制电极150，即驱动晶体管N2的栅极N2G同层绝缘设置，且所述电阻器R的电阻率高于所述驱动子电路的控制电极的电阻率，也即该驱动子电路的控制电极的导电率高于该电阻器的导电率。例如，电阻器的电阻率为该控制电极的电阻率的十倍以上。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
通过这种设置，可以使得驱动子电路控制电极与电阻器在同一构图工艺中形成，从而节省工艺。
在一些实施例中，电阻器和所述驱动子电路的控制电极的材料均为多晶硅材料，且电阻器的掺杂浓度低于控制电极的掺杂浓度，因此电阻器具有比控制电极高的电阻率。例如，电阻器可以是本征多晶硅或轻掺杂多晶硅，控制电极为重掺杂多晶硅。
在另一些实施例中，控制电极和电阻器的材料可以不同。例如，控制电极和电阻器的材料可以分别包括金属以及该金属对应的金属氧化物。例如，该金属可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料。
在一些实施例中，如图2B和2C所示，发光元件120具体实现为有机发光二极管(OLED)。例如，发光元件120可以为顶发射结构的OLED，可以发红光、绿光、蓝光或白光等。例如，该发光元件120为微型OLED(Micro OLED)。本公开的实施例对发光元件的具体结构不作限制。例如，该发光元件120的第一电极121为OLED的阳极，第二电极122为OLED的阴极，也即该像素电路为共阴极结构。然而，本公开实施例对此不作限制，根据电路结构的变化，该像素电路也可以是共阳极结构。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号SEL既可以表示第一控制信号，也可以表示第一控制信号端，符号SEL_B既可以表示第二控制信号，也可以表示第二控制信号端。符号GND既可以表示接地电压，也可以表示接地端；符号VDD既可以表示第一电源电压端又可以表示第一电源电压，符号VSS既可以表示第二电源电压端又可以表示第二电源电压。
图2D示出了图2B所示像素电路的信号时序图，以下将结合图2B所示的信号时序图对图2D所示的像素电路的工作原理进行说明。例如，第一数据写入晶体管、驱动晶体管为N型晶体管，第二数据写入晶体管为P型管，然而本公开实施例对此不做限制。
图2D示出了各信号在连续两个显示周期T1和T2中的波形图，例如该数据信号Vd在显示周期T1为高灰阶电压，在显示周期T2为低灰阶电压。
例如，如图2C所示，每一帧图像的显示过程包括数据写入阶段1以及发光阶段2。该像素电路的一种工作过程包括：在数据写入阶段1，第一控制信号SEL 和第二控制信号SEL_B均为开启信号，第一数据写入晶体管N1和第二数据写入晶体管P1导通，数据信号Vd经第一数据写入晶体管N1和/或第二数据写入晶体管P1传输至驱动晶体管N2的栅极；在发光阶段2，第一控制信号SEL和第二控制信号SEL_B均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，驱动晶体管N2工作在饱和状态且电流不变，并驱动发光元件120发光。
在一些实施例中，第一控制信号SEL和第二控制信号SEL_B为差分互补信号，振幅相同，相位相反。这样有助于提高电路的抗干扰性能。例如，该第一控制信号SEL和第二控制信号SEL_B可以由同一栅驱动电路单元(如GOA单元)输出，从而简化电路。
例如，如图1所示，显示面板10还可以包括数据驱动电路13和扫描驱动电路14。数据驱动电路13配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号Vd。扫描驱动电路14配置为输出各种扫描信号，例如包括上述第一控制信号SEL和第二控制信号SEL_B，其例如为集成电路芯片(IC)或者为直接制备在显示面板上的栅驱动电路(GOA)。
在一些实施例中，该显示面板采用硅基板作为衬底基板101，该像素电路、数据驱动电路13和扫描驱动电路14都可以集成于该硅基板上。在此情形下，由于硅基电路可以实现较高的精度，该数据驱动电路13和扫描驱动电路14例如也可以形成于对应于该显示面板的显示区的区域中，而并不一定位于非显示区。
在一些实施例中，显示面板10还包括控制电路。例如，该控制电路配置为控制数据驱动电路13施加该数据信号Vd，以及控制栅极驱动电路13施加各种扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
在一些实施例中，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
在一些实施例中，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非 易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
以下以采用图2B和图2C所示像素电路为例对本公开至少一实施例提供的显示面板进行示例性说明，然而本公开实施例并不限于此。
图3A为本公开一些实施例提供的显示面板的示意图。例如，如图3A所示，该显示面板10包括衬底基板101，多个子像素100位于该衬底基板101上。多个子像素100布置为子像素阵列，该子像素阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如相互垂直。图3A中示例性地示出了两行六列子像素，也即两个像素行和六个像素列，并用虚线框分别示出了彼此间隔的三个像素列的区域。
例如，衬底基板101可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、5聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。本公开实施例均以该衬底基板101为硅基板为例进行说明，然而本公开实施例并不限于此。
例如，该衬底基板101包括单晶硅或者高纯度硅。像素电路通过CMOS半导体工艺形成于衬底基板101上，例如，通过掺杂工艺在衬底基板101中形成晶体管的有源区(包括晶体管的沟道区)、第一极和第二极，并通过硅氧化工艺或者化学气相淀积工艺(CVD)形成各绝缘层、以及通过溅射工艺形成多个导电层从而形成走线结构等。各晶体管的有源区位于衬底基板101的内部。
图3B示出了图3A沿剖面线I-I’的剖视图。为了清楚起见，图3B中省略了一些没有直接连接关系的走线或电极结构。
例如，如图3B所示，该显示面板10包括衬底基板101、依次位于衬底基板101上的第一绝缘层201、多晶硅层102、第二绝缘层202、第一导电层301、第 三绝缘层203、第二导电层302、第四绝缘层204、第三导电层303、第五绝缘层205和第四导电层304。以下将对该显示面板10中的结构分层次进行说明，图3B将作为一个参照并一并得到说明。
为了清楚起见并方便说明，图4A示出了该显示面板10位于第一导电层301以下的部分，也即衬底基板101以及其上的第一绝缘层201和多晶硅层102，包括各晶体管(P1、N1、N2)、存储电容Cst(即存储晶体管N3)以及电阻器R；图4B示出了图4A中一个子像素100，例如为图4A中右下方的子像素的放大示意图；为了清楚起见，在图4A中还对应示出了图3A中剖面线I-I’。
如图4B所示，例如，在平行于衬底基板101的板面的方向上，包括第一数据写入晶体管N1和第二数据写入晶体管P1的传输门电路与驱动晶体管N2位于存储电容Cst的相对两侧，例如，在第一方向D1上位于该存储电容Cst的相对两侧。
在一些实施例中，存储晶体管N3作为存储电容Cst，存储晶体管N3包括栅极N3G，第一极N3D，第二极N3S以及位于所述第一极和第二极之间的有源区N3a，所述存储晶体管N3的栅极N3G作为所述存储电容Cst的第一电容电极141，所述存储晶体管N3的第一极N3D和第二极N3S电连接，所述存储晶体管N3的第一极、第二极以及有源区N3a共同作为存储电容的第二电容电极142，具体地，所述存储晶体管N3的第一极N3D、有源区N3a以及第二极N3S分别作为第二电容电极142的第一区域，第二区域和第三区域，所述第一区域和第三区域载流子迁移率相同，所述第二区域与第一区域和第三区域载流子迁移率不同，如图4B所示，第二电容电极142的第一区域、第二区域以及第三区域沿子像素的短边方向即第二方向D2依次排列，所述第一区域和第三区域载流子迁移率相同，所述第二区域与第一区域和第三区域载流子迁移率不同，所述第二区域的面积大于第一区域和第三区域的面积。
存储晶体管N3的有源区N3a的材料为半导体材料。在一些实施例中，该衬底基板101为P型硅基衬底，衬底基板101的材料例如为P型单晶硅，存储晶体管N3的有源区N3a为在P型硅基衬底上进行N型轻掺杂而形成的，该N型掺杂工艺可例如可以为离子注入工艺，掺杂元素例如可以是硼元素。当第一电容电极141上施加电压，存储晶体管N3的有源区N3a变为导体，使得存储晶体管 N3的第一极N3D、第二极N3S以及有源区N3a构成一导体结构，作为存储电容Cst的第二电容电极142。
在一些实施例中，如图4B所示，在平行于所述衬底基板的第一方向D1上，电阻器R和所述驱动晶体管N2位于所述存储电容Cst的同侧。由图2B和2C可知，驱动晶体管N2的第二极N2S通过电阻器R连接至发光器件120的第一电极121，例如为阳极。由此，电阻器R和所述驱动晶体管N2位于所述存储电容Cst的同侧，可以使得电阻R与所述驱动晶体管N2之间的距离，尤其是电阻器R第一端131与驱动晶体管N2的第二极N2S之间的距离尽量减小，从而减小连接电阻R的第一端与所述驱动晶体管N2的第二极N2S之间的布线的尺寸。
在一些实施例中，如图4B所示，在第二方向D2上，驱动晶体管N2与所述电阻器R依次排列，电阻器R位于所述驱动晶体管N2的第二极N2S远离所述驱动晶体管N2的第一极N2D一侧。电阻器R基本上呈沿第一方向D1延伸的长条形，并在电阻器R的第一端131和第二端132处，电阻器R还包括沿第二方向朝向驱动晶体管N2的凸起部，用于设置后续描述的接触孔区。具体地，电阻器R的第一端131处设置有接触孔区133，用于与驱动晶体管N2的第二极N2S电连接。电阻器R的第二端132处设置有接触孔区134，用于与发光元件120的第一电极121电连接。如图4B所示，电阻器R的第一端131相较于电阻器R的第二端132更加靠近驱动晶体管N2。
在一些实施例中，如图4B所示，传输门电路包括第一数据写入晶体管N1和第二数据写入晶体管P1，第二数据写入晶体管P1和第一数据写入晶体管N1在第二方向D2上并排设置，并且关于沿第一方向D1的对称轴对称。具体地，第一数据写入晶体管N1的栅极N1G和第二数据写入晶体管P1的栅极P1G在第二方向D2并排设置，并关于沿第一方向D1的对称轴对称；第一数据写入晶体管N1的第一极N1D和第二数据写入晶体管P1的第一极P1D在第二方向D2并排设置，并关于沿第一方向D1的对称轴对称；第一数据写入晶体管N1的第二极N1S和第二数据写入晶体管P1的第二极P1S在第二方向D2并排设置，并关于沿第一方向D1的对称轴对称，第一数据写入晶体管N1的有源区N1a和第二数据写入晶体管P1的有源区P1a在第二方向D2并排设置，并关于沿第一方向D1的对称轴对称。
在一些实施例中，存储电容Cst的第一电容电极141，即存储晶体管N3的栅极N3G与电阻器R同层绝缘设置，且都包括多晶硅材料；对多晶硅材料进行掺杂形成存储电容Cst的第一电容电极141和电阻器R。存储电容Cst的第一电容电极141的掺杂浓度高于电阻器R的掺杂浓度。使得电阻器R的导电率低于存储电容Cst的第一电容电极141，即电阻器R的电阻率高于存储电容Cst的第一电容电极141。
在一些实施例中，如图4B所示，所述驱动晶体管N2的沟道与所述第一数据写入晶体管N1之间的最短距离大于所述驱动晶体管N2的沟道与所述第二数据写入晶体管P1之间的最短距离，也就是说，所述驱动晶体管N2的栅极和有源层的重叠部分与所述第一数据写入晶体管N1之间的最短距离大于所述驱动晶体管N2的栅极和有源层的重叠部分与所述第二数据写入晶体管P1之间的最短距离。
在一些实施例中，如图4B所示，所述电阻器R与所述第一数据写入晶体管N1之间的最短距离小于所述电阻器R与所述第二数据写入晶体管P1之间的最短距离。
在本文中，两个部件之间的最短距离，指的是一个部件上的任一点到另一个部件上的任一点之间的距离中最小距离。
在一些实施例中，如图4B所示，所述电阻器R的宽度小于所述第一数据写入晶体管N1的栅极N1G、所述第二数据写入晶体管P1的栅极P1G以及驱动晶体管N2的栅极N2G中的一个的宽度，其中，第一数据写入晶体管N1的栅极N1G、所述第二数据写入晶体管P1的栅极P1G以及驱动晶体管N2的栅极N2G沿第二方向D2延伸，电阻器R沿第一方向D1延伸。
在一些实施例中，各晶体管P1、N1-N3的栅极P1G、N1G、N2G、N3G均同层设置，均包括多晶硅材料，且采用相同的掺杂工艺形成。在一些实施例中，如图4B所示，驱动晶体管N2的栅极N3G与第一电容电极141即存储晶体管N3的栅极N3G彼此连接为一体的结构。
在一些实施例中，如图4B所示，子像素包括第一区401和第二区402，其中第二区402为P型衬底基板101中通过N型重掺杂形成的N型阱区，第一区401为子像素100中去除N型阱区的剩余区域。第二数据写入晶体管P2形成在第二区402中。第一数据写入晶体管N1，驱动晶体管N2，存储晶体管N3以及 电阻器R均形成在第一区401中。
在一些实施例中，图4B还示出了各晶体管P1、N1-N3的有源区P1a、N1a、N2a、N3a。第一数据写入晶体管N1，驱动晶体管N2以及存储晶体管N3的有源区N1a、N2a、N3a均是在P型衬底101上采用N型轻掺杂工艺形成的，它们可以采用同一掺杂工艺同步形成。第二数据写入晶体管P1的有源区P1a是在第二区402中采P型轻掺杂工艺形成的。
如图4B所示，驱动晶体管N2的有源区N2a的面积相较于第一数据写入晶体管N1的有源区N1a以及第二数据写入晶体管P1的有源区P1a的面积大，可以获得较大的宽长比，有助于提高驱动晶体管N2的驱动能力，从而提高显示效果。
如图4B所示，存储晶体管N3的有源区N3a明显大于其他晶体管的有源区的面积，由此可以在存储晶体管N3作为存储电容Cst时，保证子像素的存储电容的电容值，保证显示效果。
在一些实施例中，各晶体管P1、N1-N3的第一极P1D、N1D、N2D、N3D和第二极P1S、N1S、N2S、N3S均是通过对其对应的有源区的一部分实施重掺杂工艺形成的，例如采用后续形成的对应的栅极作为掩膜来实施掺杂工艺。具体地，第一数据写入晶体管N1，驱动晶体管N2以及存储晶体管N3的第一极N1D、N2D、N3D和第二极N1S、N2S、N3S均是第一区401中采用N型重掺杂工艺形成的，它们可以采用同一掺杂工艺同步形成。第二数据写入晶体管P1的第一极P1D和第二极P1S是在第二区402中采P型重掺杂工艺形成的。
图4B还示出了第一数据写入晶体管N1的栅极接触区161、第一极接触区162和第二极接触区163，第二数据写入晶体管P1的栅极接触区171、第一极接触区172和第二极接触区173，驱动晶体管N2的第一极接触区152和第二极接触区153，存储晶体管N3的栅极接触区181，第一极接触区182和第二极接触区183。各第一极接触区为对应第一极用于形成电接触的区域，各第二极接触区为对应的第二极为用于形成电接触的区域，各栅极接触区为对应的栅极用于形成电接触的区域。
如图4B所示，对于有源区较大的晶体管，如驱动晶体管N2由于有足够空间，可以在其第一极和第二极上分别设置至少两个接触区，从而可以与待连接结 构获得充分的接触并形成并联结构，从而降低接触电阻。
在一些实施例中，图4B还示出了接触孔区411、400a、400b。其中，接触孔区411位于第二区402中，配置为电连接第一电源电压VDD，对第二数据写入晶体管P1所在的N型衬底进行高压偏置。接触孔区400a、400b位于第一区401中，且在第一方向D1上，分别位于存储电容Cst的两侧，接触孔区400a、400b均配置为电连接至接地电压GND，对晶体管N1-N3所在的P型衬底进行低压偏置。接触孔区400a、400b采用P型重掺杂工艺形成，可以与第二数据写入晶体管P1的第一极P1D和第二极P1S同步形成。接触孔区411采用N型重掺杂工艺形成，可以与第一数据写入晶体管N1的第一极N1D和第二极N1S同步形成。
结合参考图4A，在第一方向D1上相邻的两个子像素100关于沿第二方向D2的对称轴对称，在第二方向D2上相邻的两个子像素100关于沿第一方向D1的对称轴对称。具体地，在第一方向D1上相邻的两个子像素100中各晶体管(例如包括各晶体管的形状、尺寸等)以及存储电容、电阻器的分布关于沿第二方向D2的对称轴对称，也即该两个子像素中对应的结构分别关于沿第二方向D2的对称轴对称。在第二方向D2上相邻的两个子像素100中晶体管以及存储电容、电阻器的分布关于沿第一方向D1的对称轴对称。
这种对称设置可以尽量提高工艺误差的均一性，从而提高显示面板的均一性。此外，这种对称设置使得基板中一些同层设置且可以彼此连接的结构可以一体形成，相较于分开设置，可以使得像素布局更加紧凑，提高空间的利用率，从而提高了显示面板的分辨率。
在一些实施例中，如图4A所示，在第一方向D1上相邻的两个子像素100的第二区402为一体的结构，在第二方向D2上相邻的两个子像素100的第二区402为一体的结构，也即该相邻的四个子像素100的第二区组成一N型阱区402N。该相邻的四个子像素100的第二数据写入晶体管P1位于同一N型阱区402N。该四个相邻的子像素100构成一个像素组420。相较于各子像素分别设置独立的N型阱区，这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示面板的分辨率。
在一些实施例中，如图4A所示，该相邻的四个子像素100共用同一接触孔 区411，且该接触孔区411位于像素组420的N型阱区402N的中心位置。
在一些实施例中，如图4A所示，在第一方向D1上相邻的两个子像素的第二数据写入晶体管P1的有源区P1a彼此连接为一体的结构，上述相邻两个子像素的第二数据写入晶体管P1共用第二极P1S。
在一些实施例中，如图4A所示，在第一方向D1上相邻的两个子像素的第一数据写入晶体管N1的有源区N1a彼此连接为一体的结构，上述相邻两个子像素的第一数据写入晶体管N1共用第二极N1S。
在一些实施例中，如图4A所示，在第二方向D2上相邻的两个子像素100的第一数据写入晶体管N1的栅极N1G或者第二数据写入晶体管P1的栅极P1G彼此连接为一体的结构。
由于对于每行像素，第一数据写入晶体管N1的栅极都配置为接收同一第一控制信号SEL，第二数据写入晶体管P1的栅极都配置为接收同一第二控制信号SEL_B。又由于在第二方向D2上相邻的两个子像素的晶体管镜像对称，在第二方向D2上交替出现两个子像素的第一数据写入晶体管N1相邻的情形与第二数据写入晶体管P1相邻的情形。因此相邻两个第一数据写入晶体管N1的栅极可以直接连接为一体的结构，形成第一控制电极组191，相邻的第二数据写入晶体管P1的栅极可以直接连接为一体的结构，形成第二控制电极组192。这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示面板的分辨率。
如图4A所示，对于第二方向D2上相邻的两个子像素100，当它们的驱动晶体管N2相邻的情形，两个驱动晶体管N2的有源区N2a彼此连接为一体的结构，且该两个驱动晶体管N2共用第一极N2D。这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示面板的分辨率。
如图4A所示，对于第二方向D2上相邻的两个子像素100，当它们的驱动晶体管N2相邻的情形，该两个相邻的子像素的存储晶体管N3共用第一极N3D；当它们的电阻器R相邻的情形，两个相邻的子像素的存储晶体管N3共用第二极N3S。这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示面板的分辨率。
图5A-图5H示出了图4A所示的基板结构的形成过程，如图4A所示，该显 示面板包括沿第一方向D1和第二方向D2排列的多个像素单元组420。
以下结合图5A-5H对本公开实施例提供的显示面板的形成过程进行示例性说明，然而这并不作为对本公开的限制。
例如，提供一块硅基衬底基板101，例如其材料为P型单晶硅。N型晶体管(例如驱动晶体管)可以直接在该P型硅衬底上制作，也即在该P型衬底上直接掺杂来形成该N型晶体管的沟道区，有利于发挥NMOS器件高速的优势，提高了电路性能。
图5A示出了在衬底基板上形成的N型阱区。如图5A所示，在一些实施例中，在P型硅衬底基板上进行N型重掺杂，形成N型阱区402N，包括子像素的第二区402，以作为第二数据写入晶体管P1的衬底。
在一些实施例中，在第一方向D1上相邻的两个子像素的第二区402可以彼此连接，在第二方向D2上相邻的两个子像素的第二区402可以彼此连接。例如，一个像素组420中的四个子像素的第二区402连接为一体结构，形成该像素组420的N型阱区402N，图5A中示出了三个相邻像素组的N型阱区。在一些实施例，在进行该N型中掺杂形成N型阱区时对该衬底基板101上不掺杂的区域进行遮挡。
图5B示出了衬底基板上的有源区图案，图5C中的下图示出了图5A所示基板结构上形成有源区图案。有源区图案可以在衬底基板上进行轻掺杂来获得。具体地，在N型阱区内，通过P型轻掺杂在N型阱区内形成第二数据写入晶体管P1的有源区图案,其配置为后续用于形成第二数据写入晶体管P1的第一极P1D、第二极P1S以及用作沟道的有源区P1a。在N型晶阱区外，通过N型轻掺杂形成第一数据写入晶体管N1、驱动晶体管N2以及存储晶体管N3的有源区图案，第一数据写入晶体管N1、驱动晶体管N2以及存储晶体管N3的有源区图案分别配置为后续用形成第一数据写入晶体管N1、驱动晶体管N2以及存储晶体管N3的第一极N1D、N2D、N3D、第二极N1S、N2S、N3S以及用作沟道的有源区N1a、N2a、N3a。
在掺杂过程中，需要分别进行N型掺杂和P型掺杂。在进行N型掺杂工艺时，需要形成阻挡层不进行N型掺杂的区域遮挡；在进行P型掺杂工艺时，需要形成阻挡层将不进行P型掺杂的区域遮挡。
图5D示出了衬底基板上的多晶硅层图案，图5E中的下图示出了图5C所示基板结构上形成多晶硅层图案。
结合图3B、图4B和图5E所示，在一些实施例中，在该衬底基板101上形成第一绝缘层201，接着在该第一绝缘层201上形成多晶硅层102。本领域技术人员可以理解的是，为了清除表示各膜层之间的关系，图4B和图5E中省略了透明的第一绝缘层201。
该第一绝缘层201包括各晶体管的栅极绝缘层，还包括存储电容Cst的介质层104。该多晶硅层102配置为形成第一电容电极141即存储晶体管N3的栅极N3G、电阻器R以及各晶体管(P1、N1、N2)的栅极P1G、N1G、N2G。
如图4B和5E所示，第二数据写入晶体管P1的栅极P1G位于该第二区402中。第一数据写入晶体管N1、驱动晶体管N2的栅极N2G、第一电容电极141以及电阻器R形成在该N型阱区外的第一区401上。
在一些实施例中，如图4B和5E所示，每个像素单元组中的4个子像素的第一电容电极141在衬底基板的正投影位于该四个子像素的第二区402组成的N型阱区外，且环绕该N型阱区。例如，该N型阱区为矩形，每个子像素的第一电容电极141在衬底基板的正投影环绕该矩形的一个角；例如，每个第一电容电极141包括一个凹入结构，该凹入结构的轮廓大致为L形，该矩形的一个角伸入该凹入结构的正投影，与该L形轮廓匹配。
如图4B和5E所示，在第一方向D1上相邻的两个子像素中的多晶硅层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的多晶硅层的图案关于沿第一方向D1的对称轴对称，也即该多晶硅层的图案为对称图案。在一些实施例中，如图4B和5E所示，在所述第一方向上相邻的子像素的电阻器关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的电阻器关于沿所述第一方向的对称轴对称。在一些实施例中，在所述第一方向上相邻的子像素的第一电容电极关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的第一电容电极关于沿所述第一方向的对称轴对称。
在一些实施例中，在第二方向D2上相邻的两个子像素的第一数据写入晶体管N1和第二数据写入晶体管P1的栅极分别关于沿所述第一方向D1的对称轴对称。例如，在第二方向D2上相邻的两个子像素的第一数据写入晶体管N1或者 第二数据写入晶体管P1的栅极一体成型。
在一些实施例中，在第一方向D1上相邻的两个子像素的第一数据写入晶体管N1和第二数据写入晶体管P1的栅极分别关于沿所述第二方向D2的对称轴对称。
在一些实施例中，通过热氧化法在衬底基板上形成该第一绝缘层201。例如，该第一绝缘层的材料为硅的氮化物、氧化物或氮氧化物。
例如，通过化学气相淀积工艺(PVD)在该第一绝缘层上形成多晶硅材料层，然后对该多晶硅材料层进行光刻工艺形成该多晶硅层102。
图5F示出了衬底基板的N型重掺杂窗口区，图5G示出了衬底基板的P型重掺杂窗口区，图5H示出了在图5E所示基板结构完成N型重掺杂和P型掺杂重掺杂后的基板结构示意图。在一些实施例中，在形成有多晶硅层102的衬底基板上采用N型重掺杂窗口区执行N型重掺杂以及采用P型重掺杂窗口区来执行P型重掺杂，以形成用于电连接的接触孔区。例如，该掺杂窗口区包括各晶体管的源极区和漏极区，由此形成各晶体管的第一极，例如为漏极和第二极，例如为源极。在一些实施例中，该掺杂窗口区还包括衬底的各接触孔区以及电阻器R的接触孔区，例如包括图4B所示的接触孔区400a、400b、411、133、134。在一些实施例中，由于晶体管的栅极由多晶硅材料形成，也需要对该多晶硅栅极进行掺杂。在进行掺杂时，可以根据需要形成阻挡层以遮挡非掺杂区域，而仅仅暴露出相应的掺杂窗口区。
需要说明的是，图5F和图5G仅对各掺杂窗口区进行了示意，在实际进行掺杂工艺时再设置相应的阻挡层/掩模层暴露相应的掺杂窗口区及多晶硅区进行掺杂即可。例如，该阻挡层/掩模层的材料可以是光刻胶或者氧化物材料。
在一些实施例中，在进行N型重掺杂时，如图5H所示，对应电阻器R形成阻挡层135。为了保护电阻器R的阻值，需要在N型掺杂过程中对电阻器R进行遮挡以避免电阻器R因掺杂而被破坏。该阻挡层135遮挡住了电阻器R的主体部分，仅暴露出电阻器R两端的接触孔区133、134。本领域技术人员可以理解的是，图5H仅示出一对相邻子像素中遮挡电阻器R主体部分的遮挡层135，本领域技术人员可以理解的是，对于其他子像素，亦需要阻挡层来遮蔽电阻器R主体部分。
在一些实施例中，该阻挡层135可以是硅的氮化物、氧化物或者氮氧化物，也可以是光刻胶材料。待掺杂工艺结束后，该阻挡层135可以保留在显示面板中，也可以去除。
在一些实施例中，该电阻器R的阻挡层135也可以在掺杂时同其它区域的阻挡层/掩模层一同形成，本公开实施例对此不作限制。
在一些实施例中，在掺杂过程中，需要分别进行N型重掺杂和P型重掺杂，例如分布以形成N型晶体管的源极区和漏极区以及P型晶体管的源极区和漏极区。在进行N型重掺杂工艺时，可以形成阻挡层不进行N型重掺杂的区域遮挡；在进行P型重掺杂工艺时，可以形成阻挡层将不进行P型重掺杂的区域遮挡。
在一些实施例中，对照图4B，通过该N型重掺杂工艺可以形成晶体管N1-N3的栅极以及第一极和第二极，以及接触孔区411、133、134。该N型掺杂工艺可例如可以为离子注入工艺，掺杂元素例如可以是硼元素。通过该P型重掺杂工艺可以形成晶体管P1的栅极、第一极和第二极，以及接触孔区400a、400b。该P型掺杂工艺可例如可以为离子注入工艺，掺杂元素例如可以是磷元素。
在上述掺杂过程中，例如采用离子注入工艺，多晶硅图案可以充当掩模，使得离子对于硅基衬底的注入正好发生在该多晶硅的两侧，从而形成了各晶体管的第一极和第二极，实现了自对准。此外，原本电阻较高的多晶硅经过掺杂工艺电阻率降低，可以形成各晶体管的栅极以及该第一电容电极。因此，采用多晶硅材料作为电阻器及栅极材料具有多种有益效果，并节省了工艺成本。
如此，就形成了图4A所示的显示面板的结构，包括各晶体管P1、N1、N2以及电阻器R、存储电容Cst。
在一些实施例中，在第一方向D1上相邻的两个子像素中相应的晶体管、电阻器及存储电容Cst分别关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中相应的晶体管、电阻器及存储电容Cst分别关于沿第一方向D1的对称轴对称。
需要说明的是，在本实施例中，存储电容Cst是存储晶体管T3作为了电容，具体地，存储晶体管N3的栅极T3G作为第一电容电极141，存储晶体管N3的第一极N3D、第二极N3S以及它们之间的有源区N3a作为第二电容电极142，在第一电容电极141上施加电压后，衬底基板101中位于该第一电容电极1411下 方的区域产生反型电荷，使得存储晶体管N3的第一极N3D、第二极N3S以及它们之间的有源区N3a构成为一导体结构。
在一些实施例中，所述第一电容电极141在所述衬底基板101上的正投影和所述第二电容电极142在所述衬底基板101上的正投影具有交叠区域，所述交叠区域包括朝向所述驱动晶体管凸出的第一突出部和朝向所述第一数据写入晶体管N1凸出的第二突出部。
在图4A所示的基板上依次形成第二绝缘层202、第一导电层301、第三绝缘层203、第二导电层302、第四绝缘层204、第三导电层303、第五绝缘层205和第四导电层304，就形成了图3A所示的显示面板。
图6A和图6B分别示出了第一导电层301的图案以及该第一导电层301设置于图4A所示基板结构上的情形，图6B中还示出了第二绝缘层202中的过孔，该过孔与图4B中的各接触区一一对应，用于将各接触孔区与第一导电层301中的图案电连接。为了清楚起见，图中仅示出了两行六列子像素，并用虚线框示出了一个子像素100的区域；此外在图6B中还对应示出了图3A中剖面线I-I’所在的位置。
如图6A所示，在第一方向D1上相邻的两个子像素中的第一导电层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的第一导电层的图案关于沿第一方向D1的对称轴对称。以下将以一个子像素为例对该第一导电层的图案进行示例性说明。
如图6A所示，该第一导电层301包括连接电极313，该连接电极313用于将电阻器R的第一端131与驱动晶体管N2的第二极N2S电连接。
在一些实施例中，结合参考图6B，该连接电极313整体呈L型，其包括沿第一方向D1延伸的第一部分以及自第一部分沿第二方向D2朝向电阻器R延伸的第二部分，该连接电极313的第二部分的自由端通过第二绝缘层202中的过孔225与电阻器R的第一端131电连接；该连接电极313的第一部分通过第二绝缘层202中的过孔226与驱动晶体管N2的第二极N2S电连接。在一些实施例中，连接电极313在衬底基板101上的正投影落入驱动晶体管N2的第二极N2S在在衬底基板101上的正投影内。
在一些实施例中，该过孔226可以设置为一个或更多个，如图6B所示，例 如为两个，以降低接触电阻。
在一些实施例中，结合参考图6A和图6B，该第一导电层301还包括连接电极314，该连接电极314通过第二绝缘层202中的过孔229与电阻器R的第二端132电连接，该连接电极314用于与发光元件120的第一电极121电连接。例如，该连接电极314为L型，其一个分支与电阻器R的第二端132电连接，另一分支用于与发光元件120的第一电极121电连接。
在一些实施例中，结合图6A和图6B所示，该第一导电层301还包括第三电容电极315，该第三电容电极315与第一电容电极141以及第二电容电极142在垂直于衬底基板101的方向上重叠。该第三电容电极315位于该第一电容电极141远离该第二电容电极142的一侧，且配置为与该第二电容电极142电连接；也即，在垂直于衬底基板的方向上，第二电容电极142和第三电容电极315分别位于第一电容电极141的两侧，且彼此电连接，从而形成并联电容的结构，增大存储电容Cst的电容值。
在一些实施例中，结合图6A和图6B所示，该第三电容电极315通过第二绝缘层202中的过孔228与存储晶体管N3的第一极N3D电连接，以与第二电容电极142电连接，第三电容电极315大致呈L型，包括沿第一方向D1延伸的第一部分以及自所述第一部分沿第二方向D2朝向存储晶体管N3的第二极N3S延伸的第二部分。
结合图4B、6A和6B所示，所述第三电容电极315靠近第二电容电极142第一区域的部分在第一方向D1上的宽度大于所述第三电容电极315靠近第二电容电极第三区域的部分在第一方向D1上的宽度。
在一些实施例中，在第一方向D1上，过孔228更加靠近驱动晶体管N2，更远离数据写入子电路，也就是说，过孔228与所述驱动晶体管N2之间的距离在第一方向D1上的正投影小于所述过孔228与所述数据写入子电路之间的距离在第一方向D1上的正投影。由此可以更好的维持驱动晶体管的电压。
在一些实施例中，第一方向D1上相邻的两个子像素的第三电容电极315关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素的第三电容电极315关于沿第一方向D1的对称轴对称。对于同一像素组中的在第二方向D2上相邻的两个子像素，它们的第三电容电极315为一体结构，即它们的第三 电容电极315的第一部分连接为一体。
在一些实施例中，该第一导电层301还包括连接电极317，该连接电极317用于将数据写入子电路的第二端与存储子电路的第一端电连接，也即将第一数据写入晶体管N1的第一极N1D、第二数据写入晶体管P1的第一极P1G与第一电容电极141电连接。
结合参考图6A和图6B，该连接电极317例如为h型结构，包括沿第二方向D2平行延伸的第一部分和第二部分以及连接第一部分和第二部分的第三部分，第三部分沿第一方向D1延伸，连接第一部分的中部以及第二部分的一端部。该连接电极317的第一部分的第一端通过第二绝缘层202中的过孔261a与第一数据写入晶体管N1的第一极N1D电连接，该连接电极317的第一部分的第二端通过第二绝缘层202中的过孔261b与第二数据写入晶体管P1的第二极P1D电连接，该连接电极317的第二部分通过第二绝缘层202中的过孔261c与第一电容电极141电连接，在一些实施例中，过孔261c可以设置为一个或更多个，如图6B所示，例如为两个，以降低接触电阻。
在一些实施例中，在第二方向D2上，过孔261c更加靠近地第二电容电极142的第一区域，更加远离第二容电极的第三区域，也就是说，过孔261c与所述第一区域之间的距离小于过孔261c与所述第三区域之间的距离。
结合参考图6A和图6B，该第一导电层301还包括第一扫描线连接部311和第二扫描线连接部312，该第一扫描线连接部311用于与第一扫描线电连接以使得该第一数据写入晶体管N1的栅极接收第一控制信号SEL。该第二扫描线连接部312用于与第二扫描线电连接以使得该第二数据写入晶体管P1的栅极接收第一控制信号SEL_B。
在一些实施例中，该第一扫描线连接部311通过第二绝缘层202中的过孔221a与第一数据写入晶体管N1的栅极N1G电连接，第二扫描线连接部312通过第二绝缘层202中的过孔221b与第二数据写入晶体管P1的栅极P1G电连接。
在一些实施例中，如图6A和图6B所示，在第二方向D1上相邻的子像素共用第一扫描线连接部311或第二扫描线连接部312。
如图6A所示，该第一导电层301还包括数据线连接部316，该数据线连接部316用于与数据线电连接，以使得该第一数据写入晶体管N1的第二极N1S和 第二数据写入晶体管P1的第二极P1S接收到数据线传输的数据信号Vd。
如图6B所示，该数据线连接部316呈沿第二方向D2延伸的条状，数据线连接部316的第一端通过第二绝缘层202中的过孔222a与第一数据写入晶体管N1的第二极N1S电连接，第二端通过第二绝缘层202中的孔222b与第二数据写入晶体管P1的第二极P1S电连接。
在一些实施例中，如图6A所示，多个数据线连接部316在第二方向D2上间隔排布，例如位于两个子像素行的分界处。例如，在第一方向D1上相邻的两个子像素共用一个数据线连接部316。
参考图6A和图6B，该第一导电层301还包括连接电极318，该连接电极318通过第二绝缘层202中的过孔223与驱动晶体管N2的第一极N2D电连接，该连接电极318配置为将第一电源电压VDD引入驱动晶体管N2的第一极N2D。
参考图6A和图6B，该第一导电层301还包括连接电极319，连接电极319呈L状，包括沿第一方向D1延伸的第一部分以及沿第二方向D2延伸的第二部分。连接电极319的第一部分包括宽度不同的第一段和第二段，其中第二段的两端分别连接第一段以及第二部分，第一段的宽度较第二段更宽。连接电极319的第一部分的第一段通过第二绝缘层202中的过孔223a与存储晶体管N3的第二极N3S电连接，配置为将接地电压GND引入存储晶体管N3的第二极N3S。L形连接电极319的拐角处通过第二绝缘层202中的过孔223b与P型衬底基板上的接触孔区400a电连接，用于将P型衬底连接至接地电压GND，将P型衬底偏置为低压。
在一些实施例中，参考图6A和图6B，对于任意行子像素，其连接电极319的第二部分连接为一体结构。对于在第一方向D1上相邻的两子像素，当该相邻两子像素位于不同的像素组时，它们共用连接电极319的第二部分。对于在第二方向D2相邻的两子像素，当该相邻两子像素位于不同的像素组时，它们共用连接电极319的第一部分。
参考图4A和图6B，该第一导电层301还包括连接电极319a、319b，这些连接电极均是为了对晶体管的衬底进行偏置而设置，例如用于将N型衬底连接至第一电源电压端以接收第一电源电压VDD(高电压)，或者用于将P型衬底连接至接地电压端以接收接地电压GND(低电压)，由此可以避免衬偏效应等寄生效 应，提高电路的稳定性。
结合参考图4B，该连接电极319a、319b分别通过第二绝缘层202中的过孔224a、224b与衬底基板101中接触孔区400b、411电连接，该连接电极319a用于连接到接地电压GND以对与第一数据写入晶体管N1所在的P型衬底进行偏置。该连接电极319b用于连接到第一电源电压VDD以对该第二数据写入晶体管P1的N型衬底进行偏置。
图7A示出了第二导电层302的示意图，图7B在第一导电层301的基础上示出了第二导电层302,，图7B中还示出了第三绝缘层203中的过孔，该第三绝缘层203中的过孔用于连接第一导电层301中的图案和第二导电层302中的图案。为了清楚起见，图中仅示出了二行六列子像素，并用虚线框示出了一个子像素100的区域。本领域技术人员可以理解的是图7B中省略了形成第一导电层301之前的各层结构。
如图7A所示，在第一方向D1上相邻的两个子像素中的第二导电层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的第二导电层的图案关于沿第一方向D1的对称轴对称。以下将以一个子像素为例对该第二导电层的图案进行示例性说明。
如图7A和7B所示，第二导电层302包括连接电极324，该连接电极324通过第三绝缘层203中的过孔239与第一导电层301中的连接电极314电连接，该连接电极324用于与发光元件120的第一电极121电连接。例如，连接电极324呈沿第一方向D1延伸的长条形。
在一些实施例中，该过孔239可以设置为一个或更多个，如图7B所示，例如为两个，以降低接触电阻。
在一些实施例中，连接电极324在衬底基板101上的正投影基本上落入连接电极314在衬底基板101的正投影内。例如，连接电极324在衬底基板101上的正投影与连接电极314沿第一方向D1延伸的分支在衬底基板101上的正投影基本重合。
如图4B、7A和7B所示，对于每一行子像素来说，第二导电层302包括沿第二方向D2延伸的第一扫描线321、第二扫描线322、接地线325、电源线328。第一扫描线321配置为传输第一扫描信号SEL，第二扫描线322配置为传输第二 扫描信号SEL_B，接地线325配置传输地电压GND、电源线328配置为传输第一电压信号VDD。第一扫描线321、第二扫描线322、接地线325、电源线328在第一方向D1上依次远该行子像素的各N型阱区的中心。
在一些实施例中，对于任意相邻的两行子像素，它们的第一扫描线321、第二扫描线322、接地线325、电源线328中的每一个均相对于沿第二方向D2的对称轴对称。
结合参考图7A和图7B，第一扫描线321通过第三绝缘层203中的过孔231与第一电极层301中的第一扫描线连接部311电连接，用与向第一数据写入晶体管N1的栅极N1G提供第一扫描信号SEL。第二扫描线322通过第三绝缘层203中的过孔232与第一电极层301中的第二扫描线连接部312电连接，用与向第二数据写入晶体管P1的栅极P1G提供第一扫描信号SEL_B。
第一扫描线321和第二扫描线322均沿第二方向D2蜿蜒延伸，且在同一行子像素中，第一扫描线321和第二扫描线322相对于沿第二方向D2的对称轴对称。
对于在第二方向D2上相邻的两个子像素来说，若该相邻两个子像素位于同一像素组，则这两个子像素中的第一扫描线321和第二扫描线322相互平行的部分之间的距离相同。若该相邻两个子像素位于不同像素组，则这两个子像素中的第一扫描线321和第二扫描线322相互平行的部分之间的距离不相同。
结合参考图7A和图7B，接地线325通过第三绝缘层203中的过孔233与第一电极层301中第三电容电极315电连接，并且通过第三绝缘层203中的过孔234与第一电极层301中的连接电极319沿第一方向D1延伸的第一部分电连接，使得存储晶体管N3的第一极N3D与第二极N3S电连接，且均接入接地电压GND。
在每一个子像素100中，接地线235基本上呈L形，包括沿第一方向D1延伸的第一部分以及自所述第一部分沿第二方向D2朝向存储晶体管N3的第二极N3S延伸的第二部分。接地线325在衬底基板101上的正投影与第三电容电极315在衬底基板101上的正投影部分重叠，如图7B所示，接地线325的第一部分在衬底基板101上的正投影落入第三电容电极315的第一部分在衬底基板101上的正投影内，接地线325的第二部分在衬底基板101上的正投影覆盖第三电容电极315的第二部分在衬底基板101上的正投影内。
结合参考图7A和图7B，电源线328通过第三绝缘层203中的过孔235与第一导电层301中的连接电极318电连接，用于通过连接电极318向驱动晶体管N2的第一极N2D提供第一电压信号VDD。
在每一个子像素单元中，电源线328在衬底基板上的正投影覆盖驱动晶体管N2正在衬底基板101上的正投影，由此可以使得驱动晶体管N2屏蔽外界干扰，保障驱动晶体管N2的正常工作。
在一些实施例中，如图7A所示，电源线328为沿第二方向D2延伸的长条状结构。
结合参考图7A和图7B，第二导电层302还包括数据线连接部326，该数据线连接部326用于与数据线电连接，并通过第三绝缘层203中的过孔236与第一导电层301中的数据线连接部316电连接，使得该第一数据写入晶体管N1的第二极N1S和第二数据写入晶体管P1的第二极P1S接收到数据线传输的数据信号Vd。
如图7B所示，数据线连接部326呈沿第二方向D2延伸的条状，数据线连接部326在衬底基板101上的正投影落入数据线连接部316在衬底基板101上的正投影内。
结合参考图7A和图7B，第二导电层302还包括连接电极329a、329b，这些连接电极均是为了对晶体管的衬底进行偏置而设置。例如用于将N型衬底连接至第一电源电压端以接收第一电源电压VDD(高电压)，或者用于将P型衬底连接至接地电压端以接收接地电压GND(低电压)，由此可以避免衬偏效应等寄生效应，提高电路的稳定性。
结合参考图4B、7A和7B，该连接电极329a、329b分别通过第三绝缘层203中的过孔237、238与第一导电层中的连接电极319a、319b电连接，进而分别与衬底基板101中接触孔区400b、411电连接，该连接电极329a用于连接到接地电压GND以对与第一数据写入晶体管N1所在的P型衬底进行偏置。该连接电极329b用于连接到第一电源电压VDD以对该第二数据写入晶体管P1的N型衬底进行偏置。
图8A示出了第三导电层303的示意图，图8B在第二导电层302的基础上示出了第三导电层303，图7B中还示出了第四绝缘层204中的过孔，该第四绝 缘层204中的过孔用于连接第二导电层302中的图案和第三导电层303中的图案。为了清楚起见，图中仅示出了二行六列子像素，并用虚线框示出了一个子像素100的区域。本领域技术人员可以理解的是图8B中省略了形成第一导电层301之前的各层结构。
如图8A和8B所示，第三导电层303包括连接电极334，该连接电极334通过第四绝缘层204中的过孔249与第二导电层302中的连接电极324电连接，该连接电极334用于与发光元件120的第一电极121电连接。例如，连接电极334呈沿第一方向D1延伸的长条形。在一些实施例中，连接电极334在衬底基板101上的正投影与连接电极324在衬底基板101上的正投影部分重叠。
在一些实施例中，该过孔249可以设置为一个或更多个，如图8B所示，例如为两个，以降低接触电阻。
如图4B、8A和8B所示，第三导电层303包括沿第一方向D1延伸的多条电源线338、多条数据线336以及多条接地线335。多条电源线338、多条数据线336以及多条接地线335沿第二方向D2交替排布。接地线335配置传输地电压GND、电源线338配置为传输第一电压信号VDD，数据线336配置为传输数据线信号Vd。
如图4B、8A和8B所示，每一列子像素对应一条数据线336，一条电源线338和一条接地线335，对于一列子像素，数据线336沿第一方向D1贯穿对应的该列子像素，电源线338和接电线335分别设置在数据线336两侧。
如图4B、8A和8B所示，对于任意相邻的两列子像素，它们共用一条电源线338或一条接地线335。
结合参考图8A和图8B，数据线336通过第四绝缘层204中的过孔246与第二导电层302中的数据线连接部326电连接，使得该第一数据写入晶体管N1的第二极N1S和第二数据写入晶体管P1的第二极P1S接收到数据线传输的数据信号Vd。在一些实施例中，数据线336沿第一方向D1蜿蜒延伸，使得数据线336与同层设置的电源线338、接地线335以及连接电极334之间均保持预定的距离，避免数据线336与同层设置的电源线338、接地线335以及连接电极334中的任一者距离过近，而对数据信号Vd的传输造成不良影响。
结合参考图8A和图8B，电源线338通过第四绝缘层204中的过孔241与第 二导电层302中的连接电极329b电连接，用于引入第一电源电压VDD对该第二数据写入晶体管P1的N型衬底进行偏置。电源线338还通过第四绝缘层204中的过孔242与第二导电层302中的电源线328电连接。在一些实施例中，该过孔242可以设置为一个或更多个，如图8B所示，例如为三个，以降低接触电阻。
如图8B所示，第三电极层303中的电源线338与第二电极层302中的电源线328相互电连接，沿第一方向D1延伸的多条电源线328与沿第二方向D2延伸的多条电源线328组成网状结构，为各子像素提供第一电源电压VDD。
结合参考图8A和图8B，接地线335通过第四绝缘层204中的过孔243与第二导电层302中的连接电极329a电连接，用于引入接地电压GND对该第一数据写入晶体管N1的P型衬底进行偏置。接地线335还通过第四绝缘层204中的过孔244与第二导电层302中的接地线325电连接。在一些实施例中，该过孔244可以设置为一个或更多个，如图8B所示，例如为两个，以降低接触电阻。
如图8B所示，第三电极层303中的接地线335与第二电极层302中的接地线325相互电连接，沿第一方向D1延伸的多条接地线335与沿第二方向D2延伸的多条接地线325组成网状结构，为各子像素提供接地电压GND。
图9A示出了第四导电层304的示意图，图9B在第三导电层303的基础上示出了第四导电层304，图9B中还示出了第五绝缘层205中的过孔，该第五绝缘层205中的过孔用于连接第三导电层303中的图案和第四导电层304中的图案。为了清楚起见，图中仅示出了二行六列子像素，并用虚线框示出了一个子像素100的区域。本领域技术人员可以理解的是图9B中省略了形成第一导电层301之前的各层结构。
如图9A和9B所示，第四导电层304包括连接电极344，该连接电极344通过第五绝缘层205中的过孔259与第三导电层303中的连接电极334电连接，该连接电极344用于与发光元件120的第一电极121电连接。
在一些实施例中，该过孔249可以设置为一个或更多个，如图9B所示，例如为两个，以降低接触电阻。
如图9A和9B所示，第四导电层304包括连接电极345和连接电极346，连接电极345和连接电极346分别通过第五绝缘层205中的过孔255和过孔256与第三电极层303中的电源线338电连接。连接电极345和连接电极346均与第三 电极层303中的电源线338并联，由此可以降低电源线338的传输电阻，有利于第一电源电压VDD的传输。
在一些实施例中，连接电极345和连接电极346均为沿第一方向D1延伸的条形。
在一些实施例中，过孔255和过孔256中的每一个可以设置为一个或更多个，如图9B所示，例如为两个，以降低接触电阻。
如图9A和9B所示，第四导电层304还包括连接电极347和连接电极348。连接电极347和连接电极348分别通过第五绝缘层205中的过孔257和过孔258与第三电极层303中的接地线335电连接。连接电极347和连接电极348均与第三电极层303中的接地线335并联，由此可以降低接地线335的传输电阻，有利于第一电源电压VDD的传输。
在一些实施例中，连接电极347和连接电极348均为沿第一方向D1延伸的条形。
在一些实施例中，过孔257和过孔258中的每一个可以设置为一个或更多个，如图9B所示，例如为两个，以降低接触电阻。
例如，各过孔中可以通过额外填充导电材料(如钨)进行导电。
图9B中还示出了该连接电极344的接触孔区349，该接触孔区349用于与发光元件120的第一电极121电连接。在一些实施例中，。例如，如图3B所示，该显示面板10还包括第六绝缘层206，该第六绝缘层206中对应连接电极344的接触孔区349形成有过孔267，用于电连接后续发光元件120的第一电极121，例如为阳极，过孔267亦称为阳极过孔267，该过孔267中填充有导电材料(如钨)，然后经过抛光工艺(如化学机械抛光)形成平整的表面，以用于形成发光元件120。
结合图3B-9B所示，阳极过孔267在衬底基板101上的正投影与所述第一电容电极141在衬底基板101上的正投影至少部分重叠。阳极过孔267在衬底基板101上的正投影与所述第三电容电极315在衬底基板101上的正投影至少部分重叠。该种设计可以避免阳极过孔处段差过高，保障接触孔区349与发光元件120的第一电极121，例如为阳极的电连接效果。
在一些实施例中，该过孔267的数目为至少两个。
例如，如图3B所示，与发光元件120的第一电极121连接的连接电极314、324、334、344上用于电连接的接触孔区的数目可以为一个更多个，降低了连接电极之间的接触电阻，进而降低了电阻器R与该发光元件120的第一电极121之间的连接电阻，从而降低了数据信号从电阻器R传输至该第一电极121的传输路径上的电压降，缓解了由于该电压降导致的阳极电位损失(灰阶损失)所造成的造成色偏、显示不均等问题，提高了显示效果。
如图3B所示，该发光元件120包括依次设置于该第六绝缘层206上的第一电极121、发光层123和第二电极122。例如，该第一电极121和第二电极122分别为OLED的阳极和阴极。例如，多个第一电极121同层间隔设置，与多个子像素一一对应。例如，第二电极122为公共电极，整面布置于该显示面板10中。
在一些实施例中，如图3B所示，该显示面板还包括位于发光元件120远离衬底基板101一侧的第一封装层124、彩膜层125以及盖板126等。
例如，该第一封装层124配置为对发光元件进行密封以防止外界的湿气和氧向该发光元件及像素电路的渗透而造成对器件的损坏。例如，封装层124包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层124与发光元件之间还可以设置吸水层，配置为吸收发光元件在前期制作。
在一些实施例中，如图3B所示，该显示面板还可以包括位于该彩膜层125与盖板126之间的第二封装层127，该第二封装层127可以对该彩膜层125形成保护。
例如，该发光元件120配置为发白光，结合彩膜层124实现全彩显示。
在另一些示例中，该发光元件120配置为发出三原色的光，此时彩膜层124不是必须的。本公开实施例对于显示面板10实现全彩显示的方式不作限制。
在一些实施例中，上述第一到第四导电层的材料为金属材料，例如为金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料。例如，第一到第四导电层的材料也可以是导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
在一些实施例中，第一绝缘层到第六绝缘层的材料例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧 化铝、氮化钛等包括金属氮氧化物绝缘材料。
在一些实施例中，该发光元件120为顶发射结构，第一电极具121有反射性而第二电极122具有透射性或半透射性。例如，第一电极121为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极122为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
本公开的一些实施例还提供一种显示装置40，如图10所示，该显示装置40包括上述任一显示面板10，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (30)

  1. 一种显示面板，其特征在于，所述显示面板包括衬底基板以及在所述衬底基板上的子像素，其中，所述子像素包括像素电路和发光元件，所述像素电路包括数据写入子电路、存储子电路、驱动子电路：
    所述数据写入子电路配置为响应于控制信号将数据信号传输至所述存储子电路，
    所述驱动子电路包括控制电极、第一电极和第二电极，所述驱动子电路的控制电极与所述存储子电路耦接，所述驱动子电路的第一电极配置为接收第一电源电压，所述驱动子电路的第二电极与发光元件的第一电极耦接，所述驱动子电路配置为，所述驱动子电路配置为响应于所述驱动子电路的控制电极电压驱动所述发光元件发光，
    其中，所述存储子电路包括存储电容，所述存储电容包括相对设置的第一电容电极和第二电容电极，所述第一电容电极和第二电容电极分别作为所述存储子电路的第一端和第二端，所述第二电容电极位于所述衬底基板和所述第一电容电极之间，所述第二电容电极包括沿所述子像素的短边方向依次排列的第一区域、第二区域和第三区域，所述第二区域载流子迁移率的不同于第一区域和第三区域载流子迁移率，所述第二区域的面积大于第一区域和第三区域的面积，
    其中所述驱动子电路的控制电极与所述第一电容电极为同层设置的一体结构。
  2. 根据权利要求1所述显示面板，其中，所述像素电路还包括电阻器，所述电阻器串接在所述驱动子电路的第二电极和所述发光元件的第一电极之间，所述电阻器与所述驱动子电路的控制电极同层且分离设置，且所述电阻器的电阻率高于所述驱动子电路的控制电极的电阻率。
  3. 根据权利要求2所述的显示面板，其中，所述数据写入子电路包括传输门电路，所述传输门电路包括第一数据写入晶体管和第二数据写入晶体管，所述第 一数据写入晶体管和第二数据写晶体管均包括栅极、第一极和第二极，所述控制信号包括第一控制信号和第二控制信号，
    所述第一数据写入晶体管的栅极配置为接收所述第一控制信号，所述第二数据写入晶体管的栅极配置为接收所述第二控制信号，所述第一数据写入晶体管的第一极和所述第二数据写入晶体管的第一极耦接，且均与所述存储子电路的第一端以及驱动子电路的控制电极耦接，所述第一数据写入晶体管的第二极和所述第二数据写入晶体管的第二极耦接，均配置为接收所述数据信号。
  4. 根据权利要求3所述的显示面板，其中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极、第一极和第二极分别作为所述驱动子电路的控制电极、第一电极和第二电极。
  5. 根据权利要求4所述的显示面板，其中，所述第一数据写入晶体管以及驱动晶体管均为N型金属-氧化物半导体场效应晶体管，所述第二数据写入晶体管为P型金属-氧化物半导体场效应晶体管。
  6. 根据权利要求5所述的显示面板，其中，在平行于所述衬底基板的第一方向上，所述传输门电路和所述驱动晶体管分别位于所述存储电容的两侧。
  7. 根据权利要求6所述的显示面板，其中，在平行于所述衬底基板的第一方向上，所述电阻器和所述驱动晶体管位于所述存储电容的同侧。
  8. 根据权利要求7所述的显示面板，其中，所述驱动晶体管的沟道与所述第一数据写入晶体管之间的最短距离大于所述驱动晶体管的沟道与所述第二数据写入晶体管之间的最短距离。
  9. 根据权利要求7所述的显示面板，其中，所述电阻器与所述第一数据写入晶体管之间的最短距离小于所述电阻器与所述第二数据写入晶体管之间的最短距离。
  10. 根据权利要求7所述的显示面板，其中，在平行于所述衬底基板且垂直于所述第一方向的第二方向上，所述第二数据写入晶体管和所述第一数据写入晶体管依次排列，所述驱动晶体管与所述电阻器依次排列，所述第二方向为所述子像素的短边方向。
  11. 根据权利要求10所述的显示面板，其中，所述电阻器为沿第一方向延伸的长条形，所述电阻器位于所述驱动晶体管的第二极远离所述驱动晶体管的第一极一侧。
  12. 根据权利要求11所述的显示面板，其中，所述电阻器的宽度小于所述第一数据写入晶体管的栅极、所述第二数据写入晶体管的栅极以及驱动晶体管的栅极中的一个的宽度。
  13. 根据权利要求5所述的显示面板，其中，所述驱动晶体管的栅极、所述第一数据写入晶体管的栅极、所述第二数据写入晶体管的栅极、所述第一电容电极以及所述电阻器同层设置。
  14. 根据权利要求5所述的显示面板，其中，所述存储电容还包括第三电容电极，在垂直于所述衬底基板的方向上，所述第三电容电极位于所述第一电容电极远离所述第二电容电极的一侧，并通过第一过孔与所述第二电容电极的第一区域耦接。
  15. 根据权利要求14所述的显示面板，其中，所述第三电容电极在衬底基板上的正投影落入所述第二电容电极在在衬底基板上的正投影内，且所述第三电容电极在衬底基板上的正投影与所述第一电容电极在衬底基板上的正投影部分重叠。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括接地线， 配置为耦接所述第二电容电极的第一区域和第三区域，并将所述第二电容电极的第一区域和第三区域接入接地电压，在垂直于所述衬底基板的方向上，所述接地线位于所述第三电容电极远离所述第二电容电极的一侧，所述接地线在衬底基板上的正投影与所述述第三电容电极在衬底基板上的正投影部分重叠。
  17. 根据权利要求10所述的显示面板，其中，第二数据写入晶体管和所述第一数据写入晶体管沿所述第二方向并排设置，且关于沿所述第一方向的对称轴对称。
  18. 根据权利要求5所述的显示面板，包括4个所述子像素，所述4个子像素构成一个像素单元组，
    其中，所述4个子像素沿第一方向和第二方向排为阵列，所述第一方向与所述第二方向相互垂直，
    所述4个子像素的第二数据写入晶体管在所述衬底基板的正投影位于所述衬底基板中的同一N型阱区内。
  19. 根据权利要求18所述的显示面板，其中，在所述第一方向上相邻的子像素的电阻器关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的电阻器关于沿所述第一方向的对称轴对称。
  20. 根据权利要求18所述的显示面板，其中，在第一方向上相邻的两个子像素的传输门电路关于沿所述第二方向的对称轴对称，在第二方向上相邻的两个子像素的传输门电路关于沿所述第一方向的对称轴对称。
  21. 根据权利要求18所述的显示面板，其中在第一方向上相邻的两个子像素的驱动晶体管关于沿所述第二方向的对称轴对称，在第二方向上相邻的两个子像素的驱动晶体管关于沿所述第一方向的对称轴对称。
  22. 根据权利要求18所述的显示面板，其中，在所述第一方向上相邻的子像 素的第一电容电极关于沿所述第二方向的对称轴对称，在所述第二方向上相邻的子像素的第一电容电极关于沿所述第一方向的对称轴对称。
  23. 根据权利要求22所述显示面板，其中所述4个子像素中的第一电容电极在所述衬底基板的正投影位于所述N型阱区外，且环绕所述N型阱区设置。
  24. 根据权利要求14或15所述显示面板，其中，所述第三电容电极靠近第二电容电极第一区域的部分在第一方向上的宽度大于所述第三电容电极靠近第二电容电极第三区域的部分在第一方向上的宽度。
  25. 根据权利要求24所述显示面板，其中，所述子像素还包括用于连接像素电路和发光元件的阳极过孔，所述阳极过孔在衬底基板上的正投影与所述第一电容电极在衬底基板上的正投影至少部分重叠。
  26. 根据权利要求24所述显示面板，其中，所述子像素还包括用于连接像素电路和发光元件的阳极过孔，所述阳极过孔在衬底基板上正投影与所述第三电容电极在衬底基板上的正投影至少部分重叠。
  27. 根据权利要求1所述显示面板，其中，所述像素电路还包括：
    连接电极，配置耦接所述数据写入子电路和所述存储电容的第一电容电极，所述连接电极通过第二过孔与所述第一电容电极耦接，所述第二过孔与所述第一区域之间的距离小于所述第二过孔与所述第三区域之间的距离。
  28. 根据权利要求14或15所述显示面板，其中，所述第一过孔与所述驱动晶体管之间的距离小于所述第一过孔与所述数据写入子电路之间的距离。
  29. 根据权利要求4或5所述显示面板，其中，所述第一电容电极在所述衬底基板上的正投影和所述第二电容电极在所述衬底基板上的正投影具有交叠区域，所述交叠区域包括朝向所述驱动晶体管凸出的第一突出部和朝向所述第一数 据写入晶体管凸出的第二突出部。
  30. 一种显示装置，包括根据权利要求1-29任一项所述的显示面板。
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