WO2021254049A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021254049A1
WO2021254049A1 PCT/CN2021/093638 CN2021093638W WO2021254049A1 WO 2021254049 A1 WO2021254049 A1 WO 2021254049A1 CN 2021093638 W CN2021093638 W CN 2021093638W WO 2021254049 A1 WO2021254049 A1 WO 2021254049A1
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WIPO (PCT)
Prior art keywords
electrode
pixel unit
pixel
transfer electrode
display
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Application number
PCT/CN2021/093638
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English (en)
French (fr)
Inventor
龙跃
程羽雕
吴超
黄炜赟
肖星亮
王本莲
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/768,920 priority Critical patent/US20230048918A1/en
Publication of WO2021254049A1 publication Critical patent/WO2021254049A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate has a first side for display and a second side opposite to the first side, and includes: a base substrate, a display area, and at least one connection path. Wire and at least one transfer electrode.
  • the display area is disposed on the base substrate and includes a first display area that allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, wherein,
  • the first display area includes a first sub-pixel array, and the first sub-pixel array includes a plurality of first pixel unit groups arranged in a first direction and a second direction intersecting the first direction.
  • a first signal line and a plurality of first power lines, the first pixel unit group includes at least one first pixel unit, each of the plurality of first signal lines at least partially extends along the first direction, and Configured to provide a first display signal to the plurality of first pixel units, the plurality of first signal lines are connected to the first pixel units of the plurality of first pixel unit groups, and the plurality of first power lines At least partly extending along the first direction and configured to provide a first power voltage to the plurality of first pixel units, the plurality of first power lines and the first pixels of the plurality of first pixel unit groups Unit connection; each of the at least one connection trace at least partially extends along the first direction, and is connected to the first power line respectively connected to adjacent first pixel unit groups in the first direction; at least Each of a pair of transfer electrodes extends at least partially along the first direction and is connected to first signal lines respectively connected to adjacent first pixel unit groups in the first direction; wherein, the at least The film layer where at least part of the transfer electrode of one
  • the at least one connection trace includes a first connection trace, the first connection trace extends along the first direction, and the first connection trace The line is connected to the first power line connected to the first pixel units that are adjacent in the first direction and belong to different first pixel unit groups, and the first connection line is the same as the first power line. Layers are arranged and formed integrally.
  • At least one first pixel unit of the first pixel unit group includes a plurality of first pixel units
  • the at least one switching electrode includes a plurality of switching electrodes
  • the plurality of transfer electrodes are connected in a one-to-one correspondence with a plurality of first pixel units that are adjacent in the first direction and belong to different first pixel unit groups, and the plurality of transfer electrodes are respectively located on different film layers .
  • the plurality of first pixel units of the first pixel unit group are arranged in at least two rows in parallel along the second direction, and the plurality of transitions
  • the electrode includes a first switching electrode and a second switching electrode, the first switching electrode and the second switching electrode are arranged side by side, and the first switching electrode and the second switching electrode are connected to the
  • the first signal lines that are adjacent in the first direction and belong to the first pixel units of different first pixel unit groups are connected to each other, and the film layers of the first transfer electrode and the second transfer electrode are different
  • the orthographic projection of the first transfer electrode and the second transfer electrode on the base substrate and the orthographic projection of the first connection trace on the base substrate at least partially overlap.
  • a portion of the first transfer electrode extending along the first direction and a portion of the second transfer electrode extending along the first direction overlaps the orthographic projection of the base substrate with the portion of the first connection trace extending in the first direction.
  • the display substrate provided by at least one embodiment of the present disclosure, there is a gap allowing light transmission between the first direction and the first pixel unit group adjacent to the second direction, and the first The portion of the connecting wire and the portion of each of the at least one transfer electrode extend in the second direction and bypass the gap that allows light transmission.
  • the first connection trace is a bent trace, and includes a first part, a second part, and a third part.
  • the first end of the second part is respectively connected to both ends of the third part and extends in a second direction different from the first direction, the third part extends in the first direction, and
  • the second end of the first part and the second end of the second part are respectively connected to first power lines respectively connected to adjacent first pixel units in the first direction.
  • the plurality of first pixel units of the first pixel unit group include at least three rows arranged in parallel along the second direction, and the at least one
  • the connecting electrode includes a first switching electrode, a second switching electrode, and a third switching electrode.
  • the first switching electrode, the second switching electrode, and the third switching electrode are arranged side by side.
  • Three transition electrodes are located between the first transition electrode and the second transition electrode, and the first transition electrode, the second transition electrode, and the third transition electrode respectively correspond to and The first signal lines respectively connected to the first pixel units adjacent in the first direction are connected, and the film layers of the first transfer electrode, the second transfer electrode, and the third transfer electrode are different , The orthographic projection of the first connection trace on the base substrate and the orthographic projection of at least one of the first and second transition electrodes on the base substrate are at least partially Overlapping, the third transfer electrode and the first connecting wire are arranged in the same layer.
  • the orthographic projection of the third transfer electrode on the base substrate is at the same position as the first transfer electrode or the second transfer electrode.
  • the orthographic projections on the base substrate at least partially overlap.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer is located on the base substrate, and the second insulating layer Layer is located on the side of the first insulating layer away from the base substrate, the third insulating layer is located on the side of the second insulating layer away from the base substrate, the plurality of first signal lines, The plurality of first power lines and the first connection traces are located on a side of the third insulating layer away from the base substrate, and the second transfer electrode is located on the first insulating layer away from the substrate One side of the substrate is connected by a via hole penetrating the second insulating layer and the third insulating layer, and the first signal line connected to the first pixel unit adjacent in the first direction, the first A transfer electrode is located on the side of the second insulating layer away from the base substrate, and is connected through a via hole penetrating the third insulating layer,
  • the plurality of first pixel units of the first pixel unit group are arranged in at least one row along the second direction, and in the same row, the first pixel units A pixel unit group includes at least two first pixel units.
  • Each first pixel unit of the first pixel unit group includes a first pixel drive circuit and a first light-emitting device.
  • the first pixel drive circuit and the first pixel unit A light-emitting device is connected and drives the first light-emitting device to emit light.
  • the first pixel driving circuit includes a storage capacitor.
  • the storage capacitor includes a first electrode plate and a second electrode that is at least partially overlapped with the first electrode plate.
  • the first electrode plate is located on the side of the second insulating layer away from the base substrate, and the second electrode plate is located on the side of the first insulating layer away from the base substrate.
  • the plurality of first power lines connected to the first pixel unit are connected to the first electrode plate through the via hole penetrating the third insulating layer, and at least the first pixel unit group is located in the same row.
  • the first plates of the two first pixel units are connected to each other and are integrally formed.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a fourth transfer electrode, wherein the fourth transfer electrode at least partially extends along the second direction, and the fourth transfer electrode is connected to the The first power lines that are misaligned in the second direction and arranged adjacent to each other and are connected to first pixel units belonging to different first pixel unit groups are connected to each other.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a fourth switching electrode, wherein the fourth switching electrode extends along the second direction, and the fourth switching electrode is connected to the second switching electrode.
  • the first power lines respectively connected to two first pixel units that are arranged adjacent to each other and belong to different first pixel unit groups are connected.
  • both ends of the fourth transfer electrode are respectively disposed adjacent to the first pixel unit of two first pixel units belonging to different first pixel unit groups.
  • a plate connection is used to connect the first power lines located in the different first pixel unit groups.
  • the fourth transfer electrode is located on a side of the third insulating layer away from the base substrate, and the fourth transfer electrode passes through the The via hole of the third insulating layer is connected to the first electrode plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups.
  • the fourth transfer electrode is located on a side of the second insulating layer away from the base substrate, and the fourth transfer electrode is disposed adjacent to the And the first plates of the two first pixel units belonging to different first pixel unit groups are arranged in the same layer and formed integrally.
  • the fourth transfer electrode includes a first sub-transfer electrode, a second sub-transfer electrode, and a third sub-transfer electrode, and the first sub-transfer electrode The first end of the connecting electrode and the first end of the second sub-transfer electrode are respectively connected to the two ends of the third sub-transfer electrode.
  • the second end of the first sub-transfer electrode and the first end are respectively connected to the first plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups, and the first sub-transfer electrodes and the first pixel unit groups
  • the two sub-connecting electrodes are arranged in the same layer and integrally formed with the first plates of the two first pixel units that are adjacently arranged and belong to different first pixel unit groups, and the third sub-connecting electrode is located on the first electrode plate.
  • the third sub-transfer electrode is connected to the first sub-transfer electrode and the second sub-transfer electrode through a via hole penetrating the third insulating layer .
  • the multiple first pixel units of the first pixel unit group are arranged in multiple rows and multiple columns.
  • the first signal lines connected to the first pixel unit are connected to each other and formed integrally, and the first power supply lines connected to the first pixel unit in the same column are also connected to each other and formed integrally.
  • the display area further includes a second display area, the second display area at least partially surrounds the first display area, and the second display area includes a second display area.
  • the second sub-pixel array includes a plurality of second pixel units, each of the plurality of second pixel units includes a second light-emitting device and a second pixel drive circuit, the second pixel drive circuit Is configured to drive the second light-emitting device to emit light, and a first signal line connected to a first pixel unit close to the second display area extends to the second display area so as to be opposite to the first pixel unit
  • the second pixel unit located in the first direction is connected, and the first power line connected to the first pixel unit close to the second display area extends to the second display area so as to be opposite to the first pixel unit
  • the second pixel unit whose unit is located in the first direction is connected.
  • the pixel density of the second display area is greater than the pixel density of the first display area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of second signal lines and a plurality of second power lines located in the second display area, wherein the plurality of second pixel units are arranged as The plurality of rows paralleled in the second direction, the plurality of second signal lines extend along the first direction, and each of the plurality of second signal lines passes through and is arranged in the first direction as The plurality of second pixel units in a column to provide second display signals to the plurality of second pixel units, the plurality of second power lines extend along the first direction, and the plurality of second power sources Each of the lines passes through the plurality of second pixel units arranged in a column in the first direction to provide a second power supply voltage to the plurality of second pixel units.
  • At least one embodiment of the present disclosure also provides a display device, which includes any display substrate as described above.
  • the display device provided by at least one embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive information from the first side of the display substrate. Light.
  • the orthographic projection of the sensor on the base substrate at least partially overlaps the first display area.
  • FIG. 1A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 1B is a partial enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 1C is a partial enlarged schematic diagram of a display substrate provided by at least another embodiment of the present disclosure.
  • Fig. 1D is a schematic cross-sectional view taken along the line B1-B2 in Fig. 1A;
  • FIG. 2 is a schematic diagram of a planar layout of wiring in a first display area of a display substrate provided by at least one embodiment of the present disclosure
  • Figure 3A is an enlarged view of area A1 in Figure 2;
  • Figure 3B is an enlarged view of area A2 in Figure 2;
  • FIG. 4A is a schematic cross-sectional view along the line C1-C2 in FIG. 3A;
  • 4B is a schematic cross-sectional view along the line C3-C4 in FIG. 3A;
  • 4C is a schematic cross-sectional view along the line C5-C6 in FIG. 3A;
  • Fig. 4D is a schematic cross-sectional view along the line C7-C8 in Fig. 3B;
  • 5A-5C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 2;
  • 5D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 2;
  • FIG. 6 is a schematic diagram of a planar layout of wiring in a first display area of a display substrate provided by at least another embodiment of the present disclosure
  • Fig. 7A is an enlarged view of area A11 in Fig. 6;
  • Fig. 7B is an enlarged view of area A12 in Fig. 6;
  • Fig. 8 is a schematic cross-sectional view along the line C11-C12 in Fig. 7A;
  • 9A-9C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 6;
  • 9D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 6;
  • FIG. 10 is a schematic diagram of a planar layout of wiring in a first display area of a display substrate provided by at least another embodiment of the present disclosure
  • Figure 11 is an enlarged view of area A21 in Figure 10;
  • Fig. 12 is a schematic cross-sectional view along the line C21-C22 in Fig. 11;
  • FIG. 13A-13C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 10;
  • FIG. 13D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 10;
  • FIG. 14 is a schematic diagram of a planar layout of wiring in a first display area of a display substrate provided by at least another embodiment of the present disclosure
  • Figure 15 is an enlarged view of area A31 in Figure 14;
  • Fig. 16A is a schematic cross-sectional view along the line C31-C32 in Fig. 15;
  • 16B is a schematic cross-sectional view along the line C33-C34 in FIG. 15;
  • 17A-17C are schematic plan views of each layer of wiring in the first display area shown in FIG. 14;
  • FIG. 17D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 14;
  • FIG. 18 is a schematic diagram of a planar layout of wiring in a second display area of a display substrate provided by at least one embodiment of the present disclosure
  • 19 is an equivalent circuit diagram of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure
  • 20A is a schematic plan view of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure
  • 20B-20E are schematic diagrams of each layer of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure
  • 21 is a schematic cross-sectional view of a first display area in a display substrate provided by at least one embodiment of the present disclosure
  • 22 is a schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 23 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the technical or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs.
  • the "first”, “second” and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.
  • similar words such as “a”, “one” or “the” do not mean quantity limitation, but mean that there is at least one.
  • “Include” or “include” and other similar words mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents.
  • “upper”, “lower”, “front”, and “rear” are given.
  • the vertical direction is the direction from top to bottom, and the vertical direction It is the direction of gravity
  • the horizontal direction is the direction perpendicular to the vertical direction
  • the horizontal direction from right to left is the direction from front to back.
  • AMOLED active matrix organic light-emitting diodes
  • AMOLED has the characteristics of thinner and lighter, active light emission (no backlight source), no viewing angle problems, high definition, high brightness, fast response, low energy consumption, wide operating temperature range, strong shock resistance, and soft display. Since these display devices need to be combined with components such as cameras and light sensors, and these components usually occupy the display area of the display screen, it is difficult for the display screen to realize a full-screen design.
  • the display substrate has a first side for display and a second side opposite to the first side, and includes: a base substrate, a display area, and at least one connection path. Wire and at least one transfer electrode.
  • the display area is disposed on the base substrate and includes a first display area that allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate.
  • the first display area includes a first sub-pixel array, and the first sub-pixel array includes a plurality of first pixel unit groups, a plurality of first signal lines, and a plurality of first pixel unit groups arranged in a first direction and a second direction crossing the first direction. Multiple first power cords.
  • the first pixel unit group includes at least one first pixel unit.
  • Each of the plurality of first signal lines extends at least partially along the first direction and is configured to provide a first display signal to the plurality of first pixel units.
  • the plurality of first signal lines and the first pixel unit group Pixel unit connection.
  • Each of the plurality of first power lines extends at least partially along the first direction and is configured to provide a first power voltage to the plurality of first pixel units.
  • the plurality of first power lines and the first pixel unit group Pixel unit connection.
  • Each of the at least one connection trace extends at least partially along the first direction, and is connected to the first power line respectively connected to the adjacent first pixel unit groups in the first direction.
  • Each of the at least one transfer electrode at least partially extends along the first direction and is connected to a first signal line respectively connected to adjacent first pixel unit groups in the first direction.
  • the film layer where at least part of the at least one transfer electrode is located is different from the film layer where the at least one connection trace is located, and the orthographic projection of the at least one transfer electrode on the base substrate is in line with the at least one connection trace.
  • the orthographic projections on the base substrate at least partially overlap.
  • the orthographic projection of at least one transfer electrode on the base substrate and the orthographic projection of at least one connection trace on the base substrate at least partially overlap, thereby reducing the transfer electrodes and connection traces.
  • the wiring space occupied by the wires in the first display area is beneficial to reduce the grating effect caused by the switching electrodes and the connecting wires in the first display area, and to increase the aperture ratio and light transmittance of the first display area, allowing the In a display area and on the second side of the display substrate, for example, a sensor is arranged for sensing (for example, imaging), and the sensing effect (imaging quality) of the sensor is improved.
  • FIG. 1A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 1B is a partial enlarged schematic view of a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 1C is provided by at least another embodiment of the present disclosure
  • FIG. 1D is a schematic cross-sectional view taken along the line B1-B2 in FIG. 1A.
  • the display substrate 1 provided by at least one embodiment of the present disclosure includes a base substrate 100 and a display area.
  • the display area is disposed on the base substrate 100, and the display area includes a first display area 10 (for example, a light-transmitting display area) and a second display area 20 (for example, a normal display area).
  • the display substrate 1 may further include a peripheral area 30 that surrounds (eg partially surrounds) the display area.
  • the second display area 20 surrounds (eg partially surrounds) the first display area 10.
  • the display substrate 1 provided by at least one embodiment of the present disclosure may be a display substrate such as an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the embodiments of the present disclosure do not make specific types of display substrates. limited.
  • the first display area 10 is a light-transmitting display area, which allows light from the first side S1 (for example, the display side) of the display substrate 1 to be at least partially transmitted to the second side S2 of the display substrate 1 ( For example, the non-display side), that is, the incident light from the display side transmits through the first display area 10 to reach the non-display side of the display substrate 1.
  • a sensor 192 can also be provided on the second side S2 of the display substrate 1 to receive the transmitted light, so as to realize corresponding functions (for example, imaging, infrared sensing, distance sensing, etc.).
  • the sensor 192 is disposed on the second side S2 of the display substrate 1, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps the first display area 10, and is configured to receive and process the first display area from the display substrate 1.
  • the light from the first side S1 of the display substrate 1 may be collimated light along the normal direction of the display substrate 1 (for example, the Z1 direction), or may be non-collimated light.
  • the senor 192 is an image sensor, an infrared sensor, a distance sensor, etc.
  • the sensor 192 may be implemented in the form of a chip or the like, for example.
  • the sensor 192 is arranged on the second side S2 (the side facing away from the user) of the display substrate 1.
  • the sensor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.
  • the sensor 192 may be an image sensor, and may be used to collect images of the external environment facing the light-collecting surface of the sensor 192, for example, it may be a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor or a distance sensor. Wait.
  • the sensor 192 can be used to implement a camera of a mobile terminal such as a mobile phone and a notebook, and can also include optical devices such as a lens, a mirror, or an optical waveguide as required to modulate the optical path.
  • the embodiment of the present disclosure does not limit the type, function, and setting method of the sensor 192.
  • the sensor 192 is arranged on the first side S2 of the display substrate by means of double-sided tape, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps the first display area 10, and is configured to receive light from the first side S1. . Therefore, the first display area 10 provides convenience for the setting of the sensor 192 while realizing display.
  • the first display area 10 includes a first sub-pixel array (composed of gray squares in the first display area 10), and the first sub-pixel array includes a first direction Y1 and a second sub-pixel array.
  • a plurality of first pixel unit groups P0 are arranged in a second direction X1 where a direction Y1 crosses.
  • Each of the plurality of first pixel unit groups P0 may further include at least one first pixel unit (for example, a plurality of first pixel units) (described in detail later).
  • the first pixel unit includes a first light emitting device and a first pixel driving circuit that are directly connected to each other, and the first pixel driving circuit is configured to drive the first light emitting device to emit light.
  • the first light-emitting device and the first pixel driving circuit are located in the same pixel area and are not separated from each other in position.
  • first direction Y1 and the second direction X1 may or may not intersect vertically.
  • the range of the acute angle at which the first direction Y1 and the second direction X1 intersect each other may be less than or equal to 10° and greater than or equal to 45. °.
  • the first direction Y1 and the second direction X1 perpendicularly intersect each other as an example.
  • gaps between the plurality of first pixel unit groups P0 that allow light to pass through that is, a blank area in the first display area 10, to allow incident light from the first side S1 to pass between adjacent first pixel unit groups P0.
  • the gap is transmitted to ensure the light transmittance of the first display area 10.
  • the multiple first pixel unit groups P0 are arranged in a staggered arrangement between two adjacent columns, that is, the first pixel unit group P0 in the first column in the figure and the second column
  • the first pixel unit group P0 is staggered in the second direction X1 and distributed in different rows.
  • the first pixel unit group P0 in adjacent columns has different rows.
  • the multiple first pixel unit groups P0 are arranged in multiple rows and multiple columns, that is, the first pixel unit group P0 in the first column in the figure, and the first pixel unit group P0 in the second column in the figure. They are adjacent to each other in the second direction X1.
  • the second display area 20 includes a second sub-pixel array (composed of white squares in the second display area 20), and the second sub-pixel array includes a plurality of second pixel units C ( The white square in the second display area 20).
  • Each of the plurality of second pixel units C includes a second light emitting device and a second pixel driving circuit directly connected to each other, and the second pixel driving circuit is configured to drive the second light emitting device to emit light.
  • the second light-emitting device and the second pixel driving circuit are located in the same pixel area and are not separated from each other in position.
  • the pixel density of the second display area is greater than that of the first display area.
  • the arrangement density of the first pixel unit group P0 of the first display area 10 is less than that of the second display area 20.
  • the density of 20 sub-pixels in the display area is greater than that of the first display area.
  • FIG. 2 is a schematic diagram of a planar layout of wiring in a first display area of a display substrate provided by at least one embodiment of the present disclosure.
  • Fig. 3A is an enlarged view of area A1 in Fig. 2.
  • Fig. 3B is an enlarged view of area A2 in Fig. 2.
  • 5A-5C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 2.
  • FIG. 5A is a schematic plan view of the wiring in the first display area shown in FIG. 2 in the first conductive layer GA1.
  • FIG. 5B is a schematic plan view of the wiring in the first display area shown in FIG. 2 and located on the second conductive layer GA2.
  • FIG. 5C is a schematic plan view of the wiring in the first display area shown in FIG. 2 and located on the third conductive layer SD1.
  • the first display area 10 includes a plurality of first signal lines DATA1 and a plurality of first power lines VDD1.
  • the first pixel unit group P0 includes two first pixel units P1 arranged adjacently along the first direction X1.
  • the plurality of first signal lines DATA1 and the plurality of first power supply lines VDD1 extend along the first direction Y1.
  • Each of the plurality of first signal lines DATA1 is in one-to-one correspondence with and connected to the first pixel unit P1 of the plurality of first pixel unit groups P0.
  • Each of the plurality of first power supply lines VDD1 is in one-to-one correspondence with and connected to the first pixel unit P1 of the plurality of first pixel unit groups P0.
  • each first pixel unit P1 is connected to a first signal line DATA1 and a first power line VDD1 respectively.
  • the first signal line DATA1 is configured to provide a first display signal to the first pixel unit P1.
  • the first power line VDD1 is configured to provide a first power voltage to the plurality of first pixel units P1.
  • connection in the embodiments of the present disclosure includes the direct connection of wires or circuits, and the “electrical connections” and “signal connections” of wires or circuits.
  • the embodiments of the present disclosure are not limited thereto.
  • the first power line VDD1 and the first signal line DATA1 located in the same first pixel unit P1 are arranged in parallel.
  • the lower part of the first signal line DATA1 on the left in the same first pixel unit group P0 (the part for connecting the transfer electrode) is bent to the right (that is, toward the first voltage line connected to the connection trace). VDD1 bends).
  • the display substrate 1 further includes at least one connection trace, at least part of the connection trace extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of connection traces (for example, a plurality of first connection traces LS1), and each of the plurality of connection traces extends along the first direction Y1, and The first power supply lines VDD1 respectively connected to the first pixel unit group P0 adjacent in the first direction Y1 are connected.
  • the first power supply line VDD1 in the two corresponding first pixel units P1 of the first pixel unit group P0 adjacent in the first direction Y1 is connected to the connection line (for example, the first connection line LS1) .
  • the first power supply line VDD1 connected to the first pixel unit group P0 adjacent to the first direction Y1 is connected through a connection line (for example, a first connection line LS1).
  • the first power supply line VDD1 in one of the two first pixel units P1 of the first pixel unit group P0 is connected to a connection line (for example, the first connection line LS1), so as to reduce the number of lines and increase the number of lines.
  • the display substrate further includes at least one transfer electrode, and at least part of the transfer electrode extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction.
  • the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS1 and a second switching electrode TS2.
  • the main body of each of the plurality of transfer electrodes (that is, most of the transfer electrodes) extends along the first direction Y1, and is respectively connected to the first pixel unit group P0 adjacent in the first direction Y1.
  • the signal line DATA1 is connected.
  • the first signal line DATA1 in the two corresponding first pixel units P1 of the first pixel unit group P0 adjacent in the first direction Y1 is connected to one of the plurality of transfer electrodes (first rotation The connecting electrode TS1 or the second switching electrode TS2) is connected.
  • the first signal line DATA1 connected to the two adjacent first pixel units P1 in the first direction Y1 is connected through a switching electrode (the first switching electrode TS1 or the second switching electrode TS2).
  • a plurality of transfer electrodes are connected in a one-to-one correspondence with a plurality of first pixel units P1 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P0.
  • the first signal line DATA1 in one of the two first pixel units P1 of the first pixel unit group P0 (for example, located near the left side of one pixel unit P0) and a switch electrode (for example, the first turn The connection electrode TS1) is connected
  • the first signal line DATA1 in the other of the two first pixel units P1 of the first pixel unit group P0 for example, located on the right side of one pixel unit P0
  • a switching electrode for example The second transfer electrode TS2
  • the film layer where at least part of the at least one transfer electrode is located is different from the film layer where the at least one connection trace is located, and the orthographic projection of the at least one transfer electrode on the base substrate is at least The orthographic projection of a connecting trace on the base substrate at least partially overlaps.
  • a plurality of first connection traces (for example, the first connection trace LS1) are located on the plurality of transfer electrodes (for example, the first transfer electrode TS1 or the second transfer electrode TS2) away from the substrate One side of the substrate 100.
  • the orthographic projection of the connection trace (for example, the first connection trace LS1) on the base substrate 100 and the transfer electrode (for example, the first transfer electrode TS1 or the second transfer electrode TS2) are on the liner.
  • the orthographic projection on the base substrate 100 partially overlaps, for example, the orthographic projection and connection of the portion of the transfer electrode (such as the first transfer electrode TS1 or the second transfer electrode TS2) extending in the first direction Y1 on the base substrate 100
  • the orthographic projections of the traces (for example, the first connecting trace LS1) on the base substrate 100 overlap.
  • the orthographic projection of the portion of the transfer electrode (such as the first transfer electrode TS1 or the second transfer electrode TS2) extending in the first direction Y1 on the base substrate 100 is located on the connection trace (such as the first connection trace LS1).
  • the connecting wires are overlapped with the transfer electrodes and shield the transfer electrodes, which reduces the wiring space of the transfer electrodes and improves the aperture ratio and light transmittance of the first display area. It is also possible to reduce the occurrence of light interference phenomena between different traces, thereby allowing for example sensors to be arranged in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the The sensing effect of the sensor (image quality).
  • the “different film layers” in the embodiments of the present disclosure include that the two functional layers or structural layers are formed of different layers and different materials in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers Or the structure layer can be formed of different material layers, and the required patterns and structures can be formed through different patterning processes.
  • the at least one connection trace includes the first connection trace.
  • the first connection trace LS1 extends along the first direction Y1, and the first connection trace LS1 is adjacent to the first direction Y1 and belongs to a different first pixel unit group P0
  • the first power supply lines VDD1 connected to the first pixel units P1 are connected to each other. Both the first connection trace LS1 and the first power line VDD1 connected to it are substantially located in the first direction Y1. As shown in the figure, there is a gap between the adjacent first pixel unit groups P0 in the first direction Y1 to allow the light from the first side S1 of the display substrate 1 to pass through.
  • One of the two first pixel units P1 of the first pixel unit group P0 adjacent in the first direction Y1 is connected to the first connecting wire LS1 to reduce the number of wires and increase the size of the first display area 10 Aperture rate and light transmittance.
  • Fig. 4A is a schematic cross-sectional view along the line C1-C2 in Fig. 3A.
  • the lines C1-C2 pass through the first connection trace LS1, the first switching electrode TS1 and the second switching electrode TS2 along the second direction X1.
  • the display substrate 1 includes a first insulating layer 141 (e.g., a first gate insulating layer), a second insulating layer 142 (e.g., a second gate insulating layer), and a third insulating layer 141 (e.g., a first gate insulating layer) and a third insulating layer sequentially disposed on a base substrate 100.
  • Layer 143 (for example, an interlayer insulating layer).
  • the second insulating layer 142 is located on the side of the first insulating layer 141 away from the base substrate 100
  • the third insulating layer 143 is located on the side of the second insulating layer 142 away from the base substrate 100.
  • the first connection trace LS1 is located on a side of the third insulating layer 143 away from the base substrate 100, and the first power supply line VDD1 and the first connection trace LS1 are provided in the same layer and formed integrally by the same patterning process. For example, as shown in FIG. 5C, the first connection trace LS1 and the first power supply line VDD1 are located on the third conductive layer SD1.
  • the "integral formation" in the embodiments of the present disclosure means that two (or more than two) layers or structures are formed by the same deposition process and patterned by the same patterning process.
  • the connected structure, their materials can be the same or different.
  • the materials of the first connection trace LS1 and the first power supply line VDD1 may include metal materials or alloy materials, such as a single metal layer or multiple layers made of molybdenum, aluminum, and titanium.
  • the layer structure for example, the multi-layer structure is a multi-metal laminate (such as a three-layer metal laminate of titanium, aluminum, and titanium (Ti/Al/Ti)).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • “same-layer arrangement” includes that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers
  • the layer or structure layer can be formed of the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • One patterning process includes, for example, photoresist formation, exposure, development, and etching.
  • the material of one or more of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 143 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 143 may be the same or different.
  • film layers such as a buffer layer, a barrier layer, etc., may also be provided between the base substrate 100 and the first insulating layer 141, and the embodiment of the present disclosure is not limited thereto.
  • the plurality of transfer electrodes include a first transfer electrode TS1 and a second transfer electrode TS2.
  • the parts extending in one direction Y1 are arranged side by side.
  • the two first pixel units P1 of the first pixel unit group P0 are arranged in two parallel rows along the second direction Y1.
  • the first switching electrode TS1 and the second switching electrode TS2 are connected to the first signal line DATA1 adjacent to the first direction Y1 and connected to the first pixel units P1 belonging to different first pixel unit groups P0, respectively.
  • the two first pixel cells P1 of the first pixel cell group P0 located in the two columns are respectively connected to the first switching electrode TS1 and the second switching electrode TS2.
  • the first transfer electrode TS1 and the second transfer electrode TS2 first extend in the second direction X1 close to the first connection trace LS1, then extend in the first direction Y1, and finally extend in the second direction X1, so as to extend
  • the first signal lines DATA1 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P0 are connected.
  • the portions of the first transfer electrode TS1 and the second transfer electrode TS2 that extend along the second direction X1 are short, and the main body portions of the first transfer electrode TS1 and the second transfer electrode TS2 extend along the first direction Y1.
  • the second transfer electrode TS2 is shaped like a "concave” or “]” opening to the right side in the figure (away from the first connection trace LS1).
  • the first transfer electrode TS1 is similar to a "concave” or “[” shape that opens to the left side of the figure (away from the first connection trace LS1).
  • the directions of the second switching electrode TS2 and the second switching electrode TS1 are opposite, and both converge to the position where the first connection trace LS1 is located so as to overlap with the first connection trace LS1.
  • Fig. 4B is a schematic cross-sectional view along the line C3-C4 in Fig. 3A
  • Fig. 4C is a schematic cross-sectional view along the line C5-C6 in Fig. 3A.
  • the film layers of the first transfer electrode TS1 and the second transfer electrode TS2 are different.
  • the first transfer electrode TS1 is located between the second insulating layer 142 and the third insulating layer 143.
  • the first transfer electrode TS1 is located on the second conductive layer GA2.
  • the second transfer electrode TS2 is located between the first insulating layer 141 and the second insulating layer 142.
  • the second transfer electrode TS2 is located on the first conductive layer GA1.
  • the second insulating layer 142 insulates the first transit electrode TS1 and the second transit electrode TS2 at intervals.
  • the first transfer electrode TS1 and the second transfer electrode TS2 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS1 and the second transfer electrode TS2, thereby reducing the first transfer electrode TS1 and the second transfer electrode TS2. Space occupied by the second transit electrode TS2.
  • the materials of the first transfer electrode TS1 and the second transfer electrode TS2 may include metal materials or alloy materials, such as those made of molybdenum, aluminum, and titanium.
  • a metal single-layer or multi-layer structure for example, the multi-layer structure is a multi-metal laminate layer (such as a three-layer metal laminate of titanium, aluminum, and titanium (Ti/Al/Ti)).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the orthographic projection of the first transfer electrode and the second transfer electrode on the base substrate and the orthographic projection of the first connection trace on the base substrate at least partially overlap.
  • the orthographic projection of the first connection trace LS1 on the base substrate is related to the first transfer electrode TS1 (the part extending along the first direction Y1) and the second transfer electrode TS2 (along the first direction Y1).
  • the part extending in one direction Y1) overlaps the orthographic projection on the base substrate. That is, the orthographic projection of the first connection trace LS1 on the base substrate covers the first transit electrode TS1 (the part extending in the first direction Y1) and the second transit electrode TS2 (the part extending in the first direction Y1).
  • the width W1 of the cross-section of the first connection trace LS1 along the second direction X1 ranges from about 5 to 6 microns, and the width W1 is about 5.55 microns, for example.
  • the value range of the width W2 of the cross section of the first transfer electrode TS1 along the second direction X1 is, for example, about 2-3 micrometers, and the value of the width W2 is about 2.5 micrometers, for example.
  • the value range of the width W3 of the cross-section of the second transfer electrode TS2 along the second direction X1 is, for example, about 2-3 micrometers, and the value of the width W3 is about 2.5 micrometers, for example.
  • the width W4 of the gap between the first transfer electrode TS1 and the second transfer electrode TS2 along the second direction X1 ranges from about 0.2 to 1.5 micrometers, and the width W3 is, for example, about 0.55 micrometers.
  • the word "about” means that the numerical range or the value of the numerical value may fluctuate within a range of, for example, ⁇ 5%, or for example, ⁇ 10%.
  • the section lines C3-C4 in FIG. 3A pass through the first signal line DATA1, the first via hole GH1, and the first switching electrode TS1, and the section lines C5-C6 in FIG. Two via holes GH2 and the second transfer electrode TS2.
  • the two first signal lines DATA1 respectively connected to the first switching electrode TS1 and the second switching electrode TS2 are located in the two first pixel units P1 belonging to the first pixel unit group P0.
  • the first signal line DATA1 is located on the side of the third insulating layer 143 away from the base substrate 100.
  • the film layer where the first signal line DATA1 is located is different from the film layer where the first transfer electrode TS1 and the second transfer electrode TS2 are located.
  • the first signal line DATA1 is located on the third conductive layer SD1.
  • the first via hole GH1 is a via hole penetrating the third insulating layer 143, and the first signal line DATA1 is connected to the first transfer electrode TS1 through the first via hole GH1.
  • the second via hole GH2 is a via hole penetrating the third insulating layer 143 and the second insulating layer 142, and the first signal line DATA1 is connected to the second transfer electrode TS2 through the second via hole GH2.
  • FIG. 21 is a schematic cross-sectional view of a first display area in a display substrate provided by at least one embodiment of the present disclosure.
  • the two first pixel units P0 of the first pixel unit group P0 are arranged in at least one row along Y1 in the first direction, that is, in the same row, the first pixel unit group P0 includes two One pixel unit P0.
  • each first pixel unit P1 of the first pixel unit group P0 includes a first pixel driving circuit 12 and a first light-emitting device 11.
  • the first pixel driving circuit 12 is connected to the first light-emitting device 11 and drives the first pixel unit P0.
  • a light emitting device 11 emits light.
  • the first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 arranged to overlap (eg partially overlap) the first electrode plate CE1.
  • the first electrode plate CE1 is located on the side of the second insulating layer 142 away from the base substrate 100.
  • the second electrode plate CE2 is located on the side of the first insulating layer 141 away from the base substrate 100.
  • the second electrode plate CE2 is located on the second conductive layer GA2.
  • FIG. 20A is a schematic plan view of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure.
  • a plurality of first power lines VDD1 connected to each first pixel unit P0 in a one-to-one correspondence pass through the via holes VH9 and via holes VH3 passing through the third insulating layer 143 and the first electrode plate CE1 connect.
  • the first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via hole VH9 and the via hole VH3, which is not limited in the embodiment of the present disclosure.
  • the first pixel driving circuit shown in FIG. 20A is a 7T1C (ie, 7 transistors and 1 capacitor) type pixel driving circuit.
  • FIG. 20A is only an example of the first pixel driving circuit.
  • the embodiment does not limit the first pixel drive circuit.
  • it can also be a 2T1C (that is, 2 transistors and 1 capacitor) type pixel drive circuit.
  • the two transistors are the data writing transistor and the drive transistor.
  • the one capacitor It is a signal storage capacitor (such as the storage capacitor 13 in FIG. 20A).
  • the first pixel driving circuit can generate a driving current for driving the light-emitting element to emit light according to the received scan signal and data signal.
  • the light-emitting element generates different intensities according to the size of the driving current.
  • Light may also be other types of pixel circuits, for example, it may further have a compensation function, a reset function, a sensing function, etc., and thus may include more than two thin film transistors.
  • the first electrode plates CE1 of the two first pixel units P1 in the same row of the first pixel unit group P0 are connected to each other and formed integrally, so as to save the manufacturing process and reduce the cost. That is to say, the first power line VDD1 in each first pixel unit P1 is connected to the first plate CE1 of the storage capacitor 13 of the corresponding first pixel unit P1 to connect with the first pixel unit P1 through The first electrode plates CE1 of the two first pixel units P1 in the same row of the first pixel unit group P0 are connected to each other, and the first power lines VDD1 in the two first pixel units P1 are connected.
  • the two first pixels can be connected by setting a first connection line LS1.
  • the first power line VDD1 in one of the cells P1 is connected to reduce the number of wires.
  • the display substrate 1 further includes a fourth transfer electrode TS4, and a portion (most of) of the fourth transfer electrode TS4 extends along the second direction X1.
  • the fourth transfer electrode TS is connected to the first power supply line VDD1 which is staggered in the second direction X1 and is adjacently arranged and is connected to the first pixel units P1 belonging to different first pixel unit groups P0.
  • a plurality of first pixel unit groups P0 (four first pixel unit groups P0 are shown in the figure) are arranged in the form shown in FIG. 1B.
  • the plurality of first pixel unit groups P0 in two adjacent columns are arranged in different rows in a staggered manner, so as to leave more gaps in the first pixel unit group P0, thereby allowing the first side S1 of the display substrate 1 Light through.
  • both ends of the fourth transfer electrode TS4 are respectively connected to the first electrode plates CE1 of two first pixel units P1 that are adjacently arranged and belong to different first pixel unit groups P0.
  • the fourth transfer electrode TS4 first extends along the first direction Y1 , And then extend along the second direction X1, and finally extend along the first direction Y1, that is, the fourth transfer electrode TS4 includes a portion extending along the first direction Y1. Most of the fourth transfer electrode TS4 extends along the second direction X1.
  • the section line C7-C8 in FIG. 3B passes through the portion of the first electrode plate CE1, the third via GH3 and the fourth transfer electrode TS4.
  • Fig. 4D is a schematic cross-sectional view along the line C7-C8 in Fig. 3B.
  • the fourth transfer electrode TS4 is located on the side of the third insulating layer 143 away from the base substrate 100, and the third via hole GH3 is a via hole penetrating the third insulating layer 143.
  • the fourth transfer electrode TS4 is connected to the first electrode plate CE1 of the first pixel unit P1 through the third via 143.
  • the value range of the width W5 of the fourth transfer electrode TS4 (for example, perpendicular to the routing direction of the fourth transfer electrode TS4) is about 2-3 microns, and the value of the width W5 , For example, about 2.5 microns.
  • FIG. 5D is a schematic diagram of the sub-pixel arrangement of the first display area shown in FIG. 2; as shown in FIG. ) And the green sub-pixel (G) or the blue sub-pixel (B) and the green sub-pixel (G).
  • the first pixel unit group P0 in the first row in the first column includes a red sub-pixel (R) and a green sub-pixel (G1), that is, the left side of the first pixel unit group P0
  • the light emitting device 11 of the first pixel unit P1 on the side emits red light
  • the light emitting device 11 of the first pixel unit P1 on the right side of the first pixel unit group P0 emits green light.
  • the first pixel unit group P0 in the figure is regarded as a whole to divide rows and columns, that is, the first pixel unit group P0 arranged in the first column includes two rows of first pixel unit groups P0, the first pixel unit group P0 arranged in the second column includes two rows of the first pixel unit group P0.
  • the first pixel unit group P0 in the second row in the first column includes a red sub-pixel (R) and a green sub-pixel (G1)
  • the first pixel unit group P0 in the first row in the second column includes a blue sub-pixel (B) and the green sub-pixel (G2)
  • the first pixel unit group P0 in the second row in the second column includes a blue sub-pixel (B) and a green sub-pixel (G2).
  • the first pixel unit group P0 adjacent in the second direction X1 shares the red sub-pixel (R) and the blue sub-pixel (B), that is, the first pixel unit group P0 in the first row in the first column
  • the red sub-pixel (R) and the blue sub-pixel (B) are shared with the first pixel unit group P0 in the first row in the second column, and the first pixel unit group P0 and the second pixel unit in the second row in the first column
  • the first pixel unit group P0 in the second row in the column shares the red sub-pixel (R) and the blue sub-pixel (B) to realize the display of the picture.
  • the light-emitting color of the first pixel unit P1 of the first pixel unit group P0 can be selected according to actual display needs, and the embodiment of the present disclosure is not limited thereto.
  • FIG. 6 is a schematic diagram of a planar layout of wiring in the first display area of a display substrate provided by at least another embodiment of the present disclosure.
  • Fig. 7A is an enlarged view of area A11 in Fig. 6.
  • Fig. 7B is an enlarged view of area A12 in Fig. 6.
  • 9A-9C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 6.
  • FIG. 9A is a schematic plan view of the wiring in the first display area shown in FIG. 6 and located on the first conductive layer GA11.
  • FIG. 9B is a schematic plan view of the wiring in the first display area shown in FIG. 6 and located on the second conductive layer GA12.
  • FIG. 9C is a schematic plan view of the third conductive layer SD11 of the wiring in the first display area shown in FIG. 6.
  • the first display area 10 includes a plurality of first pixel unit groups P10, a plurality of first signal lines DATA1, and a plurality of first power lines VDD1.
  • the plurality of first pixel unit groups P10 are arranged in multiple rows and multiple columns, that is, according to the arrangement shown in FIG. 1C.
  • the first pixel unit group P10 includes three first pixel units P11 (that is, arranged in a row) adjacently arranged along the first direction X1.
  • the plurality of first signal lines DATA1 and the plurality of first power supply lines VDD1 extend along the first direction Y1.
  • Each of the plurality of first signal lines DATA1 is in one-to-one correspondence with and connected to the first pixel unit P11 of the plurality of first pixel unit groups P10.
  • Each of the plurality of first power supply lines VDD1 is in one-to-one correspondence with and connected to the first pixel unit P11 of the plurality of first pixel unit groups P10. That is, each first pixel unit P11 is connected to a first signal line DATA1 and a first power line VDD1 respectively.
  • the first signal line DATA1 is configured to provide a first display signal to the first pixel unit P11.
  • the first power line VDD1 is configured to provide a first power voltage to the plurality of first pixel units P11.
  • the first power supply line VDD1 and the first signal line DATA1 located in the same first pixel unit P11 are arranged in parallel.
  • the lower part of the first signal line DATA1 on the left in the same first pixel unit group P0 (the part for connecting the transfer electrode) is close to the first power line VDD1 in the middle (for connecting with the connection trace)
  • the lower part of the first signal line DATA1 on the right side (the part used to connect the transfer electrode) is close to the first power line VDD1 (used to connect to the connection trace) in the middle.
  • the upper part of the first signal line DATA1 (the part for connecting the transfer electrode) on the right side of the first pixel cell group P10 in the second row is directed toward the first power line VDD1 (used by Bend in the direction of connecting with the connection trace.
  • the display substrate 1 further includes at least one connection trace, at least part of the connection trace extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of connection traces (for example, a plurality of first connection traces LS11), each of the plurality of connection traces extends along the first direction Y1, and The first power supply lines VDD1 respectively connected to the first pixel unit groups P10 adjacent in the first direction Y1 are connected.
  • the first power supply line VDD1 in the two corresponding first pixel units P11 of the first pixel unit group P10 adjacent in the first direction Y1 is connected to the connection line (for example, the first connection line LS11) .
  • the first power supply line VDD1 connected to the first pixel unit group P10 adjacent in the first direction Y1 is connected through a connection line (for example, a first connection line LS11). That is, the first power supply line VDD1 in one of the three first pixel units P11 of the first pixel unit group P10 is connected to the connection line (for example, the first connection line LS11), so as to reduce the number of lines and increase the number of lines.
  • the display substrate 1 further includes at least one switching electrode, at least part of the switching electrode extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of transfer electrodes.
  • the transfer electrodes include a first transfer electrode TS11, a second transfer electrode TS12, and a third transfer electrode TS3.
  • the main body of each of the plurality of transfer electrodes (that is, most of the transfer electrodes) extends along the first direction Y1, and is respectively connected to the first pixel unit group P10 adjacent in the first direction Y1.
  • the signal line DATA1 is connected.
  • the first signal line DATA1 in the two corresponding first pixel units P11 of the first pixel unit group P10 adjacent in the first direction Y1 is connected to one of the plurality of transfer electrodes (first rotation The connecting electrode TS11, the second switching electrode TS12 or the third switching electrode TS3) are connected.
  • the first signal line DATA1 connected to the two adjacent first pixel units P11 in the first direction Y1 passes through one switching electrode (the first switching electrode TS11, the second switching electrode TS12, or the third switching electrode TS3) Connect.
  • a plurality of transfer electrodes are connected in a one-to-one correspondence with a plurality of first pixel units P11 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P10.
  • the first signal line DATA1 in one of the three first pixel units P1 of the first pixel unit group P10 (for example, located near the left side of one pixel unit P10) and a switch electrode (for example, the first switch The electrode TS11) is connected.
  • the first signal line DATA1 and one switching electrode (for example, the third switching electrode TS3) in another one of the three first pixel cells P11 of the first pixel cell group P10 (for example, located near the middle of one pixel cell P10) connect.
  • connection traces (such as the first connection trace LS11) are located on the multiple transition electrodes (such as the first transition electrode TS11 or the second transition electrode TS12) away from the substrate One side of the substrate.
  • the orthographic projection of the connection trace (for example, the first connection trace LS11) on the base substrate 100 and the transfer electrode (for example, the first transfer electrode TS11 or the second transfer electrode TS12) on the substrate The orthographic projection on the base substrate 100 partially overlaps.
  • the orthographic projection of the portion of the transfer electrode (such as the first transfer electrode TS11) extending in the first direction Y1 on the base substrate 100 and the connection traces (such as the first connection The trace LS11) the orthographic projection on the base substrate 100 overlaps.
  • the orthographic projection of the portion of the transfer electrode (for example, the first transfer electrode TS11) extending in the first direction Y1 on the base substrate 100 is located on the connection trace (for example, the first connection trace LS11) on the base substrate 100
  • the connecting wires are overlapped with the transfer electrodes and the transfer electrodes are covered, which reduces the wiring space of the wires, improves the aperture ratio and light transmittance of the first display area, and can also reduce the number of different wires.
  • the at least one connection trace includes the first connection trace.
  • the first connection trace LS11 extends along the first direction Y1, and the first connection trace LS11 is adjacent to the first direction Y1 and belongs to a different first pixel unit group P10
  • the first power supply lines VDD1 respectively connected to the first pixel units P11 are connected to each other.
  • Both the first connection trace LS11 and the first power line VDD1 connected to it are substantially located in the first direction Y1. As shown in the figure, there is a gap between the adjacent first pixel unit groups P10 in the first direction Y1 to allow the light from the first side S1 of the display substrate 1 to pass through.
  • One of the three first pixel units P1 of the first pixel unit group P10 adjacent in the first direction Y1 (for example, the one pixel unit P1 located in the middle) is connected to the first connection wiring LS11 to reduce wiring Increase the aperture ratio and light transmittance of the first display area 10.
  • the first connecting wire and the first power wire are provided on the same layer and formed integrally.
  • Fig. 8 is a schematic cross-sectional view along the line C11-C12 in Fig. 7A.
  • the lines C11-C12 pass through the first switching electrode TS11, the first connecting wire LS11, the third switching electrode TS3, and the second switching electrode TS12 along the second direction X1.
  • the first connection trace LS11 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power supply line VDD1 and the first connection trace LS11 are provided in the same layer and formed integrally by the same patterning process.
  • the first connection trace LS11 and the first power supply line VDD1 are located on the third conductive layer SD11.
  • the plurality of switching electrodes include a first switching electrode TS11, a second switching electrode TS12, and a third switching electrode TS3.
  • the portions of the first transition electrode TS11, the second transition electrode TS12, and the third transition electrode TS3 that extend along the first direction Y1 are arranged side by side.
  • the third switching electrode TS3 is located between the first switching electrode TS11 and the second switching electrode TS12.
  • the three first pixel units P11 of the first pixel unit group P10 are arranged in three parallel rows along the second direction Y1.
  • the first transfer electrode TS11, the third transfer electrode TS3, and the second transfer electrode TS12 are connected to the first pixel cells P11 that are adjacent in the first direction Y1 and belong to different first pixel cell groups P10, respectively.
  • the signal line DATA1 is connected. That is, the three first pixel cells P11 belonging to the same first pixel cell group P10 located in the three columns are respectively connected to the first switching electrode TS11, the third switching electrode TS3, and the second switching electrode TS12.
  • the third transfer electrode TS3 extends along the first direction Y1.
  • the first transfer electrode TS11 and the second transfer electrode TS12 first extend in the second direction X1 close to the first connection trace LS11, then extend in the first direction Y1, and then extend in the second direction X1, so as to
  • the first signal lines DATA1 of the first pixel units P11 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P10 are connected.
  • the portions of the first transfer electrode TS11 and the second transfer electrode TS12 that extend along the second direction X1 are short, and the main body portions of the first transfer electrode TS11 and the second transfer electrode TS12 extend along the first direction Y1.
  • the third transfer electrode TS3 extends along the first direction Y1, and the first signal line DATA1 connected to it is substantially located in a straight line (that is, all located in the first direction Y1).
  • the third transfer electrode TS3 may be integrally formed with the first signal line DATA1 connected to the third transfer electrode TS3.
  • the second transfer electrode TS12 is in the shape of a "concave” or “]” that opens to the right side in the figure (away from the first connection trace LS11).
  • the first transfer electrode TS11 is in the shape of a "concave” or “["-like opening to the left side of the figure (away from the first connection trace LS11).
  • the directions of the second switching electrode TS12 and the second switching electrode TS11 are opposite, and both converge to the position where the first connection trace LS11 is located so as to overlap with the first connection trace LS11. As shown in FIG.
  • the third transfer electrode TS3 is located on the third conductive layer SD11, and is provided in the same layer as the first signal line DATA1.
  • the third switching electrode TS3 and the first signal line DATA1 connected to it are both located in the first direction Y1.
  • the film layers where the multiple transfer electrodes are respectively located are different.
  • the film layers of the first transfer electrode TS11, the second transfer electrode TS12, and the third transfer electrode TS3 are different.
  • the first transfer electrode TS11 is located between the second insulating layer 142 and the third insulating layer 143.
  • the first transfer electrode TS11 is located on the second conductive layer GA12.
  • the second transfer electrode TS12 is located between the first insulating layer 141 and the second insulating layer 142.
  • the second transfer electrode TS12 is located on the first conductive layer GA11.
  • the second insulating layer 142 insulates the first transfer electrode TS11 and the second transfer electrode TS12 at intervals.
  • the first transfer electrode TS11 and the second transfer electrode TS12 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS11 and the second transfer electrode TS12, thereby reducing the first transfer electrode TS11 and the second transfer electrode TS12. Space occupied by the second transfer electrode TS12.
  • the third transfer electrode TS3 is located on the third conductive layer SD11, that is, the third insulating layer 143 is on the side far away from the base substrate 100, that is, it is provided on the same layer as the first connection trace LS11 to reduce Wiring space.
  • the first signal line DATA1 is located on the third conductive layer SD11, that is, the third insulating layer 143 is far away from the base substrate 100.
  • the film layer where the first signal line DATA1 is located is connected to the first transfer electrode TS11 and the second transfer electrode TS12
  • the film layers are not the same, but they are the same as the film layer where the third transfer electrode TS3 is located.
  • the third transfer electrode TS3 and the first signal line DATA1 connected to it are arranged in the same layer and formed integrally.
  • the orthographic projection of the third transfer electrode on the base substrate and the orthographic projection of the first transfer electrode or the second transfer electrode on the base substrate at least partially overlap.
  • the orthographic projection of the third transfer electrode TS3 on the base substrate 100 partially overlaps the orthographic projection of the second transfer electrode TS12 on the base substrate 100 to reduce wiring space.
  • the orthographic projection of the first connection trace on the base substrate at least partially overlaps the orthographic projection of at least one of the first transfer electrode and the second transfer electrode on the base substrate.
  • the orthographic projection of the first connection trace LS11 on the base substrate 100 and the orthographic projection of the first transfer electrode TS11 (the part extending along the first direction Y1) on the base substrate 100 overlapping.
  • the orthographic projection of the first connection trace LS11 on the base substrate 100 covers the orthographic projection of the first transfer electrode TS11 (the part extending along the first direction Y1) on the base substrate 100, so that the first connection The trace LS11 shields the first transfer electrode TS11, thereby reducing the wiring space for connecting traces, increasing the aperture ratio and light transmittance of the first display area, and reducing the occurrence of light interference between different traces .
  • the orthographic projection of the first connection trace LS11 on the base substrate 100 overlaps with the orthographic projection of the second transfer electrode TS21 (the part extending along the first direction Y1) on the base substrate 100 to reduce the wiring space.
  • the orthographic projection of the second transfer electrode TS21 (the part extending in the first direction Y1) on the base substrate 100 and the orthographic projection of the first connection trace LS11 and the third transfer electrode TS3 on the base substrate 100 are part Overlap, that is, the second transfer electrode TS21 blocks the gap between the first connection trace LS11 and the third transfer electrode TS3 to prevent light interference.
  • the width W11 of the cross section of the first connecting trace LS11 along the second direction X1 has a value range of, for example, about 5-6 microns, and the width W1 has a value of, for example, about 5.55 microns.
  • the value range of the width W12 of the cross section of the first transfer electrode TS11 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W12 is about 2.5 microns, for example.
  • the value range of the width W13 of the cross section of the second transfer electrode TS12 along the second direction X1 is, for example, about 3-4 microns, and the value of the width W13 is, for example, about 3.5 microns.
  • the value range of the width W14 of the gap between the first transfer electrode TS1 and the second transfer electrode TS2 along the second direction X1 is, for example, about 2-3 microns, and the width W13 is about 2.65 microns, for example.
  • the value range of the width W16 of the cross section of the third transfer electrode TS3 along the second direction X1 is, for example, about 1.5-2.5 micrometers, and the value of the width W16 is about 2 micrometers, for example.
  • the width W17 of the gap between the first connection trace LS11 and the third transfer electrode TS3 along the second direction X1 ranges, for example, about 2-3 micrometers, and the width W17 is about 2.7 micrometers, for example.
  • the first signal line DATA1 (located on the left in the figure) is connected to the first transfer electrode TS11 through the first via GH11.
  • the first signal line DATA1 (located on the right in the figure) is connected to the second switching electrode TS12 through the second via GH12. 4B and 4C, the first via GH11 and the first via GH1 are both vias penetrating the third insulating layer 143, the second via GH12 and the second via GH2 are both penetrating the third insulating layer 143 and Via hole of the second insulating layer 142.
  • the three first pixel units P10 of the first pixel unit group P0 are arranged in a row along the first direction Y1, that is, in the same row, the first pixel unit group P10 It includes three first pixel units P10.
  • Each first pixel unit P1 of the first pixel unit group P10 includes a first pixel driving circuit 12 and a first light emitting device 11.
  • the first pixel driving circuit 12 is electrically connected to the first light emitting device 11 and drives the first light emitting device 11 to emit light.
  • the first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 arranged to overlap (eg partially overlap) the first electrode plate CE1.
  • the first electrode plate CE1 is located on the side of the second insulating layer 142 away from the base substrate 100.
  • the second electrode plate CE2 is located on the side of the first insulating layer 141 away from the base substrate 100.
  • the first electrode plate CE1 is located on the second conductive layer GA12.
  • a plurality of first power supply lines VDD1 connected to each first pixel unit P10 in a one-to-one correspondence pass through the via holes VH9 and via holes VH3 passing through the third insulating layer 143 and the first electrode. Board CE1 connection.
  • the first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via hole VH9 and the via hole VH3.
  • the first electrode plates CE1 of the three first pixel units P11 in the same row of the first pixel unit group P10 are connected to each other and formed integrally, so as to save the manufacturing process and reduce the cost. . That is, the first power line VDD1 in each first pixel unit P11 is connected to the first plate CE1 of the storage capacitor 13 of the corresponding first pixel unit P11 to be electrically connected to the first pixel unit P11.
  • the first power supply lines VDD1 in the two first pixel units P11 are electrically connected.
  • one first connection line LS11 can be used to connect the three first power lines LS11.
  • the first power supply line VDD1 in one of the pixel units P11 is connected to reduce the number of wiring lines.
  • the display substrate 1 further includes a fourth transfer electrode TS14, and the fourth transfer electrode TS14 extends along the second direction X1.
  • the fourth transfer electrode TS14 is electrically connected to the first power line VDD1 which is arranged adjacent to the second direction X1 and is connected to the first pixel units P1 belonging to different first pixel unit groups P0.
  • a plurality of first pixel unit groups P10 (four first pixel unit groups P10 are shown in FIG. 6) are arranged in the form shown in FIG. 1C. That is, the plurality of first pixel unit groups P10 in two adjacent columns are located in the same row to leave more gaps between the first pixel unit groups P10, thereby allowing the signal from the first side S1 of the display substrate 1 Light through.
  • both ends of the fourth transfer electrode TS14 are respectively connected to the first electrode plates CE1 of two first pixel units P11 arranged adjacently and belonging to different first pixel unit groups P10.
  • the fourth transfer electrode TS14 extends along the first direction Y1.
  • the fourth transfer electrode TS14 is located on the second conductive layer GA12 and is connected to the first electrode plate CE1 of the first pixel unit P11 and may be integrally formed.
  • the value range of the width W15 of the fourth transfer electrode TS14 (for example, perpendicular to the routing direction of the fourth transfer electrode TS14), for example, is about 14-15 microns, and the value of the width W15 , For example, about 14.5 microns.
  • the width W15 of the fourth transfer electrode TS14 is relatively large, so that other wirings (for example, light-emitting control signal lines, gate lines, Polar scanning signal lines, etc.) are shielded to reduce light interference.
  • FIG. 9D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 6.
  • the three first pixel units P11 of the first pixel unit group P10 may respectively include a red sub-pixel (R), a green sub-pixel (G1), and a blue sub-pixel (B), that is, the first
  • the light emitting device 11 of the first pixel unit P1 on the left side of the pixel unit group P10 emits red light
  • the light emitting device 11 of the first pixel unit P1 in the middle of the first pixel unit group P10 emits green light
  • the light emitting device 11 of the first pixel unit group P10 emits green light.
  • the light emitting device 11 of the first pixel unit P1 on the right emits blue light to realize the display of the picture.
  • the light-emitting color of the first pixel unit P11 of the first pixel unit group P10 can be selected according to actual display needs, and the embodiment of the present disclosure is not limited thereto.
  • FIG. 10 is a schematic diagram of a planar layout of wiring in the first display area of a display substrate provided by at least another embodiment of the present disclosure.
  • Fig. 11 is an enlarged view of area A21 in Fig. 10.
  • 13A to 13C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 10.
  • FIG. 13A is a schematic plan view of the first conductive layer GA21 of the wiring in the first display area shown in FIG. 10.
  • FIG. 13B is a schematic plan view of the wiring in the first display area shown in FIG. 10 and located on the second conductive layer GA22.
  • FIG. 13C is a schematic plan view of the third conductive layer SD21 of the wiring in the first display area shown in FIG. 10.
  • the first display area 10 includes a plurality of first pixel unit groups P20, a plurality of first signal lines DATA1, and a plurality of first power lines VDD1.
  • the multiple first pixel unit groups P20 are arranged in staggered rows and multiple columns, that is, according to the arrangement shown in FIG. 1B, that is, the first pixel unit group P20 in the first column and the first pixel unit group P20 in the second column
  • the pixel unit groups P20 are mutually staggered.
  • the first pixel unit group P20 includes four first pixel units P21 arranged in two rows and two columns along the second direction X1 and the first direction Y1.
  • the plurality of first signal lines DATA1 and the plurality of first power supply lines VDD1 extend along the first direction Y1.
  • Each of the plurality of first signal lines DATA1 is in one-to-one correspondence with and electrically connected to the first pixel unit P21 of the plurality of first pixel unit groups P20.
  • Each of the plurality of first power supply lines VDD1 is in one-to-one correspondence with and electrically connected to the first pixel unit P21 of the plurality of first pixel unit groups P20. That is, each first pixel unit P21 is connected to a first signal line DATA1 and a first power line VDD1 respectively.
  • the first signal line DATA1 is configured to provide a first display signal to the first pixel unit P21.
  • the first power line VDD1 is configured to provide a first power voltage to the plurality of first pixel units P21.
  • the first signal line DATA1 connected to the first pixel unit P21 in the same column is connected to each other and integrated Formed, the first power supply line VDD1 connected to the first pixel cell P21 in the same column is also connected to each other and formed integrally.
  • the two first pixel unit groups P20 on the left in FIG. 13C only show two of the first pixel units P21, and the complete structure of the two first pixel unit groups P20 on the left is the same as that of FIG. 13C.
  • the first pixel unit group P20 located on the right side of P20 is the same.
  • the first power supply line VDD1 and the first signal line DATA1 located in the same first pixel unit P21 are arranged in parallel.
  • the lower part of the first signal line DATA1 on the left in the same first pixel unit group P20 (the part used to connect to the transfer electrode) is close to the first power line VDD1 on the right (used to connect to the connection trace) Bend in the direction.
  • the lower part of the first signal line DATA1 on the right in the same first pixel unit group P20 (the part used to connect to the transfer electrode) is far away from the first power line VDD1 on the right (used to connect to the connection trace) Bend in the direction.
  • the lower part of the first power supply line VDD1 on the right side in the same first pixel unit group P20 (the part for connecting the wiring) is bent to the right (the same as the right side of the first pixel unit group P20 in the same first pixel unit group P20).
  • the bending direction of the lower part of a signal line DATA1 is the same).
  • the upper part of the first signal line DATA1 on the right side in the same first pixel unit group P20 (the part for the transfer electrode) is bent to the right.
  • the display substrate 1 further includes at least one connection trace, at least part of the connection trace extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of connection traces (for example, a plurality of first connection traces LS21), and each of the plurality of connection traces includes a line extending along the first direction Y1.
  • the portion and the portion extending in the second direction X1 are connected to the first power supply line VDD1 respectively connected to the first pixel unit group P20 adjacent in the first direction Y1.
  • the first power supply line VDD1 in the two corresponding first pixel units P21 of the first pixel unit group P20 adjacent in the first direction Y1 is connected to the connection line (for example, the first connection line LS21) .
  • the first power supply line VDD1 connected to the first pixel unit group P20 adjacent in the first direction Y1 is connected through a connection line (for example, a first connection line LS21). That is, the first power supply line VDD1 in one of the two first pixel units P21 of the first pixel unit group P20 is connected to a connection line (for example, the first connection line LS21), so as to reduce the number of lines and increase the number of lines.
  • the display substrate 1 further includes at least one switching electrode, at least part of the switching electrode extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of switching electrodes.
  • the switching electrodes include a first switching electrode TS21 and a second switching electrode TS22.
  • the main body of each of the plurality of transfer electrodes (that is, most of the transfer electrodes) extends along the first direction Y1, and is respectively connected to the first pixel unit group P20 adjacent in the first direction Y1.
  • the signal line DATA1 is connected.
  • the first signal line DATA1 in the two corresponding first pixel units P21 of the first pixel unit group P20 adjacent in the first direction Y1 is connected to one of the plurality of transfer electrodes (first rotation The connection electrode TS21 or the second transfer electrode TS22) is connected.
  • the first signal line DATA1 connected to the two adjacent first pixel units P21 in the first direction Y1 is connected through one switching electrode (the first switching electrode TS21 or the second switching electrode TS22).
  • a plurality of transfer electrodes are connected in a one-to-one correspondence with a plurality of first pixel units P21 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P20.
  • the first signal line DATA1 in one of the two first pixel cells P21 in the same row (for example, located on the left side of one pixel cell P20) of the first pixel cell group P20 and a switching electrode (for example, The first transfer electrode TS21) is connected.
  • the first signal line DATA1 in the other of the two first pixel units P21 in the same row (for example, located on the right side of one pixel unit P20) of the first pixel unit group P20 and a switching electrode (for example, the second Transition electrode TS22) is connected.
  • connection traces are located on the side of the multiple transition electrodes (such as the first transition electrode TS21 or the second transition electrode TS22) away from the base substrate.
  • the orthographic projection of the connection trace (for example, the first connection trace LS21) on the base substrate 100 and the transfer electrodes (for example, the first transfer electrode TS21 and the second transfer electrode TS22) are on the liner.
  • the orthographic projection on the base substrate 100 overlaps, for example, the orthographic projection of the transfer electrodes (such as the first transfer electrode TS21 and the second transfer electrode TS22) on the base substrate 100 and the connection traces (such as the first connection trace) LS21)
  • the orthographic projections on the base substrate 100 overlap.
  • the orthographic projection of the portion of the transfer electrode (such as the first transfer electrode TS21 and the second transfer electrode TS22) extending in the first direction Y1 on the base substrate 100 is located on the connection trace (such as the first connection trace LS21).
  • the connecting wires are overlapped with the transfer electrodes and shield the transfer electrodes, which reduces the wiring space of the transfer electrodes, improves the aperture ratio and light transmittance of the first display area, and also It is possible to reduce the occurrence of light interference phenomena between different traces, thereby allowing a sensor to be arranged in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the sensor The sensing effect (image quality).
  • connection traces such as the first connection trace LS21
  • transition electrodes such as the first transition electrode TS21 and the second transition electrode TS22
  • connection traces for example, the first connection trace LS21
  • the transfer electrodes for example, the first transfer electrode TS21 and the second transfer electrode TS22
  • first approach to the right along the second direction X1 Extends in the direction of the first pixel unit group P20 on the side, then extends along the first direction Y1, and then extends away from the first pixel unit group P20 on the right side, so that the connection traces (such as the first connection trace LS21) and the The connection electrodes (for example, the first switching electrode TS21 and the second switching electrode TS22) are connected to two adjacent first pixel unit groups P20 in the first direction Y1.
  • connection traces such as the first connection trace LS21
  • the transfer electrodes such as the first transfer electrode TS21 and the second transfer electrode TS22
  • the connection traces are in a "three-segment polyline trace" to leave the first pixel
  • the larger gaps between the cell groups P20 prevent light interference.
  • the at least one connection trace includes the first connection trace.
  • the first connection trace LS21 is a bent trace, and includes a first part LSP1, a second part LSP2, and a third part LSP3.
  • the first part LSP1 and the second part LSP2 extend along the second direction X1, and the third part LSP3 extends along the first direction Y1.
  • the second end LSP12 of the first part LSP1 and the second end LSP22 of the second part LSP2 are respectively connected to the first power line VDD1 connected to the adjacent first pixel units P21 in the first direction Y1.
  • the first connection trace LS21 is connected to the first power supply line VDD1 to which the first pixel units P21 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P20 are respectively connected. As shown in the figure, there is a gap between the adjacent first pixel unit groups P20 in the first direction Y1 to allow the light from the first side S1 of the display substrate 1 to pass through.
  • One of the two first pixel units P21 of the first pixel unit group P20 adjacent in the first direction Y1 (for example, the one pixel unit P31 located in the middle) is connected to the first connecting wiring LS21 to reduce wiring Increase the aperture ratio and light transmittance of the first display area 10.
  • Fig. 12 is a schematic cross-sectional view taken along the line C21-C22 in Fig. 11.
  • the lines C11-C12 pass through the first transfer electrode TS21, the first connection trace LS21, and the second transfer electrode TS22 along the second direction Y1.
  • the first connection trace LS21 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power supply line VDD1 and the first connection trace LS21 are arranged in the same layer and formed integrally by the same patterning process.
  • the first connection trace LS21 and the first power supply line VDD1 are located on the third conductive layer SD21.
  • the plurality of switching electrodes include a first switching electrode TS21 and a second switching electrode TS12.
  • the shapes of the first transfer electrode TS21 and the second transfer electrode TS22 are the same as the shape of the first connecting wire LS21, that is, a bent wire formed by connecting three sections of wires.
  • the first transfer electrode TS21 and the second transfer electrode TS12 are arranged side by side, and first extend in the second direction X1 to a direction close to the first pixel unit group P20 on the right, then extend in the first direction Y1, and then away from the right.
  • the direction of the side first pixel unit group P20 extends to leave a larger gap between the first pixel unit group P20, thereby preventing light interference.
  • the orthographic projection of the first transfer electrode and the second transfer electrode on the base substrate and the orthographic projection of at least one of the first part, the second part and the third part of the first connection trace on the base substrate overlapping.
  • the orthographic projection of the first transfer electrode TS21 and the second transfer electrode TS22 on the base substrate and the first part LSP1, the second part LSP2, and the third part of the first connection trace LS21 are all overlapped (for example, partially overlapped).
  • the orthographic projection of the first transfer electrode TS21 on the base substrate 100 is located in the orthographic projection of the first portion LSP1, the second portion LSP2, and the third portion LSP3 of the first connection trace LS21 on the base substrate 100.
  • the first transfer electrode TS2 is completely shielded by the first connection trace LS21.
  • the orthographic projection of the second transfer electrode TS22 on the base substrate 100 is not completely located in the overlapped by the orthographic projections of the first portion LSP1, the second portion LSP2, and the third portion LSP3 of the first connection trace LS21 on the base substrate,
  • the orthographic projection of the portion of the second transfer electrode TS22 along the second direction X1 on the base substrate 100 overlaps the orthographic projection of the first portion LSP1 of the first connection trace LS21 on the base substrate 100.
  • the width of the first connection trace LS21 can be increased, so that the first connection trace LS21 completely shields the portion of the second transfer electrode TS22 that is routed along the second direction X1.
  • the space occupied by the first transfer electrode TS11 and the second transfer electrode TS12 can be reduced, the aperture ratio and light transmittance of the first display area can be improved, and the light between different traces can also be reduced.
  • the occurrence of interference phenomenon can be reduced.
  • the first switching electrode TS21 and the second switching electrode TS22 are adjacent to the first pixel unit P21 in the first direction Y1 and belonging to a different first pixel unit group P20, respectively.
  • the connected first signal line DATA1 is connected. That is, two first pixel cells P21 belonging to the same first pixel cell group P20 located in two columns are respectively connected to the first switching electrode TS2 and the second switching electrode TS22.
  • the portions of the first switching electrode TS11 and the second switching electrode TS12 extending along the first direction Y1 are close to the first pixel unit group P20 on the right side of the figure to reduce light interference.
  • the second transfer electrode TS22 is shaped like a "concave" opening to the right side in the figure (away from the first connection trace LS21).
  • the first transfer electrode TS21 has a shape similar to a "concave” opening to the left side of the figure (away from the first connection trace LS21).
  • the directions of the second switching electrode TS22 and the second switching electrode TS21 are opposite, and both converge to the position where the first connection trace LS21 is located so as to overlap with the first connection trace LS21.
  • the film layers where the multiple transfer electrodes are respectively located are different.
  • the film layers of the first transfer electrode TS21 and the second transfer electrode TS22 are different.
  • the first transfer electrode TS21 is located between the second insulating layer 142 and the third insulating layer 143.
  • the first transfer electrode TS21 is located on the second conductive layer GA22.
  • the second transfer electrode TS22 is located between the first insulating layer 141 and the second insulating layer 142.
  • the second transfer electrode TS22 is located on the first conductive layer GA21.
  • the second insulating layer 142 insulates the first transit electrode TS21 and the second transit electrode TS22 at intervals.
  • the first transfer electrode TS21 and the second transfer electrode TS22 are located in different film layers, which can reduce the size of the space between the first transfer electrode TS21 and the second transfer electrode TS22, thereby reducing the first transfer electrode TS21 and the second transfer electrode TS22. Space occupied by the second transfer electrode TS22.
  • the value range of the width W21 of the cross section of the first connecting trace LS21 along the second direction X1 is about 4.5-5.5 microns, and the value of the width W21 is about 5 microns, for example.
  • the value range of the width W22 of the cross section of the first transfer electrode TS21 along the second direction Y1 is, for example, about 2-3 micrometers, and the value of the width W22 is about 2.5 micrometers, for example.
  • the value range of the width W23 of the cross section of the second transfer electrode TS22 along the second direction Y1 is, for example, about 2-3 micrometers, and the value of the width W23 is about 2.5 micrometers, for example.
  • the value range of the width W24 of the gap between the first transfer electrode TS21 and the second transfer electrode TS22 along the second direction Y1 is, for example, about 1-2 microns, and the width W3 is about 0.8 microns, for example.
  • the first signal line DATA1 (located on the left in the figure) is connected to the first transfer electrode TS21 through the first via GH21.
  • the first signal line DATA1 (located on the right in the figure) is connected to the second switching electrode TS22 through the second via GH22.
  • the first via GH21 and the first via GH1 are both vias that penetrate the third insulating layer 143
  • the second via GH22 and the second via GH2 are both vias that penetrate the third insulating layer.
  • Layer 143 and via holes of the second insulating layer 142 are both vias that penetrate the third insulating layer.
  • the four first pixel units P20 of the first pixel unit group P20 are arranged in two rows and two columns, that is, in the same row, the first pixel unit group P10 includes two The first pixel unit P20.
  • Each first pixel unit P21 of the first pixel unit group P20 includes a first pixel driving circuit 12 and a first light-emitting device 11.
  • the first pixel driving circuit 12 is electrically connected to the first light-emitting device 11 and drives the first light-emitting device 11 to emit light.
  • the first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 arranged to overlap (eg partially overlap) the first electrode plate CE1.
  • the first electrode plate CE1 is located on the side of the second insulating layer 142 away from the base substrate 100.
  • the second electrode plate CE2 is located on the side of the first insulating layer 141 away from the base substrate 100.
  • the first electrode plate CE1 is located on the second conductive layer GA22.
  • the plurality of first power supply lines VDD1 connected to each first pixel unit P20 in a one-to-one correspondence pass through the via holes VH9 and the via holes VH3 passing through the third insulating layer 143 and the first electrode. Board CE1 connection.
  • the first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via hole VH9 and the via hole VH3.
  • the first electrode plates CE11 of the two first pixel units P11 in the same row of the first pixel unit group P20 are connected to each other and formed integrally, so as to save the manufacturing process and reduce the cost. . That is, the first power line VDD1 in each first pixel unit P21 is connected to the first plate CE1 of the storage capacitor 13 of the corresponding first pixel unit P11 to be electrically connected to the first pixel unit P21.
  • the first power supply lines VDD1 in the two first pixel units P21 are electrically connected.
  • the first power lines VDD1 located in different rows are connected to each other correspondingly and are integrally formed. As mentioned above, when the first power supply lines VDD1 in the two first pixel units P21 in the same row belonging to a first pixel unit group P20 are electrically connected, the two The first power supply line VDD1 in one of the first pixel units P21 is connected to reduce the number of wiring lines.
  • the display substrate 1 further includes a fourth transfer electrode TS24, and the fourth transfer electrode TS24 extends along the second direction X1.
  • the fourth transfer electrode TS24 is electrically connected to the first power line VDD1 which is arranged adjacent to the second direction X1 and is connected to the first pixel units P21 belonging to different first pixel unit groups P20.
  • a plurality of first pixel unit groups P20 (three first pixel unit groups P20 are shown in FIG. 6) are arranged in the form shown in FIG. 1B. That is, the plurality of first pixel unit groups P10 in two adjacent columns are located in different rows to leave more gaps between the first pixel unit groups P20, thereby allowing the signal from the first side S1 of the display substrate 1 Light through.
  • both ends of the fourth transfer electrode TS24 are respectively connected to the first electrode plates CE1 of two first pixel units P21 that are adjacently arranged and belong to different first pixel unit groups P20.
  • the fourth transfer electrode TS24 includes a portion extending along the first direction Y1.
  • the fourth transfer electrode TS24 is located on the second conductive layer GA22 and is connected to the first electrode plate CE1 of the first pixel unit P21 and may be integrally formed.
  • the first pixel unit P21 in the first row of the first pixel unit group P20 and The first pixel unit P21 in the second row is connected to a different fourth transfer electrode TS24.
  • first pixel units P21 the first column of the first row of the first pixel unit group P20 (ie, the left side )
  • the first plate CE1 of the first pixel unit P21 is connected to the fourth transfer electrode TS24 on the upper left, and the fourth transfer electrode TS24 on the upper left is also connected to the second row of the first pixel unit group P20 on the upper left.
  • the first electrode plate CE1 of the first pixel unit P21 in the second column ie, the right side
  • the first electrode plate CE1 of the first pixel unit P21 in the first row and the second column (ie, the right side) of the first pixel unit group P20 is connected to the fourth transfer electrode TS24 on the upper right, and the fourth transfer electrode on the upper right TS24 is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the second row of the first pixel unit group P20 (that is, on the left side) located at the upper right.
  • the first electrode plate CE1 of the first pixel cell P21 in the first column of the second row of the first pixel cell group P20 (ie, the left side) is connected to the fourth transition electrode TS24 on the bottom left, and the fourth transition electrode on the bottom left TS24 is also connected to the first electrode plate CE1 of the first pixel unit P21 in the second column of the first row of the first pixel unit group P20 (that is, on the right) located at the bottom left.
  • the first electrode plate CE1 of the first pixel cell P21 in the second row and second column of the second row of the first pixel cell group P20 (ie, the right side) is connected to the fourth transition electrode TS24 at the bottom right, and the fourth transition electrode at the top right
  • the TS24 is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the first row of the first pixel unit group P20 (ie, the left side) located at the bottom right.
  • the value range of the width W25 of the fourth transfer electrode TS24 (for example, perpendicular to the routing direction of the fourth transfer electrode TS24), for example, is about 2-3 microns, and the value of the width W15 , For example, about 2.5 microns.
  • FIG. 13D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 10.
  • the four first pixel units P21 of the first pixel unit group P20 arranged in two rows and two columns may respectively include a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel ( G1) and green sub-pixels (G2) (that is, two green sub-pixels), that is, in a first pixel unit group P20 (take the four first pixel units P21 on the right side of the figure as an example), they are located in the
  • the two first pixel units P21 in one row include blue sub-pixels (B) and green sub-pixels (G2)
  • the two first pixel units P21 in the second row include red sub-pixels (R) and green sub-pixels ( G1), that is, in a first pixel unit group P20 (take the 4 first pixel units P21 on the right side of the figure as an example), the first column in the first
  • the light-emitting device 11 of the first pixel unit P21 in the lower left corner emits red light
  • the light-emitting device 11 of the first pixel unit P21 in the second row that is, the lower right corner
  • the light-emitting color of the first pixel unit P21 of the first pixel unit group P20 can be selected according to actual display needs, and the embodiment of the present disclosure is not limited thereto.
  • FIG. 14 is a schematic diagram of a planar layout of wiring in the first display area of a display substrate provided by at least another embodiment of the present disclosure.
  • Fig. 15 is an enlarged view of area A31 in Fig. 14.
  • 17A-17C are schematic plan views of each layer of the wiring in the first display area shown in FIG. 14.
  • FIG. 17A is a schematic plan view of the first conductive layer GA31 of the wiring in the first display area shown in FIG. 14.
  • FIG. 17B is a schematic plan view of the wiring in the first display area shown in FIG. 14 and located on the second conductive layer GA32.
  • FIG. 17C is a schematic plan view of the third conductive layer SD31 of the wiring in the first display area shown in FIG. 14.
  • the first display area 10 includes a plurality of first pixel unit groups P30, a plurality of first signal lines DATA1, and a plurality of first power lines VDD1.
  • the multiple first pixel unit groups P30 are arranged in staggered rows and multiple columns, that is, according to the arrangement shown in FIG. 1B, that is, the first pixel unit group P30 in the first column and the first pixel unit group P30 in the second column are arranged
  • the pixel unit groups P30 are staggered (that is, located in two adjacent rows).
  • the first pixel unit group P30 includes four first pixel units P31 arranged in two rows and two columns along the second direction X1 and the first direction Y1.
  • the plurality of first signal lines DATA1 and the plurality of first power supply lines VDD1 extend along the first direction Y1.
  • Each of the plurality of first signal lines DATA1 is in one-to-one correspondence with and electrically connected to the first pixel units P31 of the plurality of first pixel unit groups P30.
  • Each of the plurality of first power supply lines VDD1 is in one-to-one correspondence with and electrically connected to the first pixel unit P31 of the plurality of first pixel unit groups P30. That is, each first pixel unit P31 is connected to a first signal line DATA1 and a first power line VDD1 respectively.
  • the first signal line DATA1 is configured to provide a first display signal to the first pixel unit P31.
  • the first power line VDD1 is configured to provide a first power voltage to the plurality of first pixel units P31.
  • the first signal line DATA1 connected to the first pixel cell P31 in the same column is connected to each other and formed integrally, and the first signal line DATA1 connected to the first pixel cell P31 in the same column is connected to the first power source.
  • the lines VDD1 are also connected to each other and formed integrally. It should be noted that only two first pixel unit groups P30 are shown in FIG. 14.
  • the first power supply line VDD1 and the first signal line DATA1 located in the same first pixel unit P31 are arranged in parallel.
  • the lower part of the first signal line DATA1 on the left in the same first pixel unit group P30 (the part for connecting the transfer electrode) is bent to the right (for example, toward the first power line connected to the connection trace). VDD1 bends).
  • the display substrate 1 further includes at least one connection trace, at least part of the connection trace extends along the first direction and is connected to the first power lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of connection traces (for example, a plurality of first connection traces LS31), and each of the plurality of connection traces extends along the first direction Y1, and The first power supply lines VDD1 respectively connected to the first pixel unit groups P30 adjacent in the first direction Y1 are connected.
  • the first power supply line VDD1 in the two corresponding first pixel units P31 of the first pixel unit group P30 adjacent in the first direction Y1 is connected to the connection line (for example, the first connection line LS31) .
  • the first power supply line VDD1 connected to the first pixel unit group P30 adjacent in the first direction Y1 is connected through a connection line (for example, a first connection line LS31). That is, the first power supply line VDD1 in one of the two first pixel units P31 of the first pixel unit group P30 is connected to a connection line (for example, the first connection line LS31), so as to reduce the number of lines and increase the number of lines.
  • the display substrate 1 further includes at least one switching electrode, at least part of the switching electrode extends along the first direction and is connected to the first signal lines respectively connected to the adjacent first pixel unit groups in the first direction .
  • the display substrate 1 further includes a plurality of switching electrodes, for example, the switching electrodes include a first switching electrode TS31 and a second switching electrode TS32.
  • the main body of each of the plurality of transfer electrodes (that is, most of the transfer electrodes) extends along the first direction Y1, and is respectively connected to the first pixel unit group P30 adjacent in the first direction Y1.
  • the signal line DATA1 is connected.
  • the first signal line DATA1 in the two corresponding first pixel units P31 of the first pixel unit group P30 adjacent in the first direction Y1 is connected to one of the plurality of transfer electrodes (first rotation The connecting electrode TS31 or the second switching electrode TS32) is connected.
  • the first signal line DATA1 connected to two adjacent first pixel units P31 in the first direction Y1 is connected through a switching electrode (the first switching electrode TS31 or the second switching electrode TS32).
  • the plurality of transfer electrodes are connected in a one-to-one correspondence with the plurality of first pixel units P31 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P30.
  • the first signal line DATA1 in one of the two first pixel cells P31 in the same row (for example, located near the left side of one pixel cell P30) of the first pixel cell group P30 and a switching electrode (for example, The first transfer electrode TS31) is connected.
  • the first signal line DATA1 in the other of the two first pixel units P31 in the same row (for example, located on the right side of one pixel unit P30) of the first pixel unit group P30 and a switching electrode (for example, the second Transition electrode TS32) is connected.
  • connection traces (such as the first connection trace LS31) are located on multiple transfer electrodes (such as the first transfer electrode TS31 or the second transfer electrode TS32) away from the substrate One side of the substrate.
  • transfer electrodes such as the first transfer electrode TS31 or the second transfer electrode TS32
  • the orthographic projection of the connection traces (for example, the first connection trace LS31) on the base substrate 100 and the transfer electrodes (for example, the first transfer electrode TS31 and the second transfer electrode TS32) are on the liner.
  • the orthographic projection on the base substrate 100 overlaps, for example, the orthographic projection of the transfer electrodes (such as the first transfer electrode TS31 and the second transfer electrode TS32) on the base substrate 100 and the connection traces (such as the first connection trace) LS31)
  • the orthographic projections on the base substrate 100 overlap.
  • the orthographic projection of the portion of the transfer electrode (such as the first transfer electrode TS31 and the second transfer electrode TS32) extending in the first direction Y1 on the base substrate 100 is located on the connection trace (such as the first connection trace LS31).
  • the connecting wires are overlapped with the transfer electrodes and shield the transfer electrodes, which reduces the wiring space of the transfer electrodes and improves the aperture ratio and light transmittance of the first display area. It is also possible to reduce the occurrence of light interference phenomena between different traces, thereby allowing for example sensors to be arranged in the first display area and on the second side S2 of the display substrate 1 for sensing (for example, imaging), and improving the The sensing effect of the sensor (image quality).
  • the at least one connection trace includes the first connection trace.
  • the first connection traces LS31 are respectively connected to the adjacent first pixel unit P31 in the first direction Y1 (that is, the adjacent first pixel unit group P30 in the first direction Y1 is located
  • the first pixel unit P31 in the second column (ie, the right side) is connected to the first power supply line VDD1 respectively. That is, the first connection trace LS31 is connected to the first power supply line VDD1 to which the first pixel units P31 that are adjacent in the first direction Y1 and belong to different first pixel unit groups P30 are respectively connected.
  • first connection wiring LS31 to reduce wiring Increase the aperture ratio and light transmittance of the first display area 10.
  • Fig. 16A is a schematic cross-sectional view taken along the line C31-C32 in Fig. 15.
  • the lines C31-C32 pass through the first transfer electrode TS31, the first connection trace LS31, and the second transfer electrode TS32 along the second direction X1.
  • the first connection trace LS31 is located on the side of the third insulating layer 143 away from the base substrate 100, and the first power supply line VDD1 and the first connection trace LS21 are arranged in the same layer and formed integrally by the same patterning process. For example, as shown in FIG.
  • the first connection trace LS31 and the first power supply line VDD1 are located on the third conductive layer SD31.
  • the first connection trace LS31 and the first power supply line VDD1 connected to the first connection trace LS31 are located in the first direction Y1.
  • the plurality of transfer electrodes include a first transfer electrode TS31 and a second transfer electrode TS32.
  • the extended parts are arranged side by side.
  • the first switching electrode TS31 and the second switching electrode TS32 are connected to the first signal line DATA1 adjacent to the first direction Y1 and connected to the first pixel units P31 belonging to different first pixel unit groups P30, respectively. That is, the two first pixel cells P31 belonging to the same first pixel cell group P30 located in two columns are respectively connected to the first switching electrode TS31 and the second switching electrode TS32.
  • the two first pixel cells P31 of the first pixel cell group P30 located in the two columns are respectively connected to the first switching electrode TS31 and the second switching electrode TS32.
  • the first switching electrode TS31 and the second switching electrode TS32 first extend in the second direction X1 close to the first switching electrode LS31, and then extend in the first direction Y1.
  • the portions of the first transfer electrode TS31 and the second transfer electrode TS32 that extend in the second direction X1 are relatively short, and the main body portions of the first transfer electrode TS31 and the second transfer electrode TS32 extend in the first direction Y1.
  • the second transfer electrode TS32 is shaped like a "concave” or “]” opening to the right (away from the first connection trace LS21) in the figure.
  • the first transfer electrode TS31 is in the shape of a "concave” or “["-like opening to the left side of the figure (away from the first connection trace LS21).
  • the directions of the second switching electrode TS32 and the second switching electrode TS31 are opposite, and both converge to the position where the first connection trace LS31 is located so as to overlap with the first connection trace LS31.
  • the film layers where the multiple transfer electrodes are respectively located are different.
  • the film layers of the first transfer electrode TS31 and the second transfer electrode TS32 are different.
  • the first transfer electrode TS31 is located between the second insulating layer 142 and the third insulating layer 143.
  • the first transfer electrode TS31 is located on the second conductive layer GA32.
  • the second transfer electrode TS32 is located between the first insulating layer 141 and the second insulating layer 142.
  • the second transfer electrode TS32 is located on the first conductive layer GA31.
  • the second insulating layer 142 insulates the first transit electrode TS31 and the second transit electrode TS32 at intervals.
  • the first transfer electrode TS31 and the second transfer electrode TS32 are located in different film layers, which can reduce the size of the interval between the first transfer electrode TS31 and the second transfer electrode TS32, thereby reducing the first transfer electrode TS31 and the second transfer electrode TS32. Space occupied by the second transit electrode TS32.
  • the width W31 of the cross-section of the first connection trace LS31 along the second direction X1 ranges from about 5 to 6 microns, and the width W31 is about 5.5 microns, for example.
  • the value range of the width W32 of the cross section of the first transfer electrode TS31 along the second direction X1 is, for example, about 2-3 microns, and the value of the width W32 is about 2.5 microns, for example.
  • the value range of the width W33 of the cross section of the second transfer electrode TS32 along the second direction X1 is, for example, about 2-3 micrometers, and the value of the width W33 is about 2.5 micrometers, for example.
  • the value range of the width W34 of the gap between the first transfer electrode TS31 and the second transfer electrode TS32 along the second direction X1 is, for example, about 0.2-1.5 micrometers, and the value of the width W34 is about 0.5 micrometers, for example.
  • the first signal line DATA1 (located on the left in the figure) is connected to the first transfer electrode TS31 through the first via GH31.
  • the first signal line DATA1 (located on the right in the figure) is connected to the second switching electrode TS32 through the second via GH32.
  • the first via GH31 and the first via GH1 are both vias that penetrate the third insulating layer 143
  • the second via GH32 and the second via GH2 are both vias that penetrate the third insulating layer.
  • Layer 143 and via holes of the second insulating layer 142 are both vias that penetrate the third insulating layer.
  • the four first pixel units P30 of the first pixel unit group P30 are arranged in two rows and two columns, that is, in the same row, the first pixel unit group P30 includes two The first pixel unit P30.
  • Each first pixel unit P31 of the first pixel unit group P30 includes a first pixel driving circuit 12 and a first light emitting device 11, and the first pixel driving circuit 12 is electrically connected to the first light emitting device 11 and drives the first light emitting device 11 to emit light.
  • the first pixel driving circuit 12 includes a storage capacitor 13, and the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2 arranged to overlap (eg partially overlap) the first electrode plate CE1.
  • the first electrode plate CE1 is located on the side of the second insulating layer 142 away from the base substrate 100.
  • the second electrode plate CE2 is located on the side of the first insulating layer 141 away from the base substrate 100.
  • the first electrode plate CE1 is located on the second conductive layer GA22.
  • a plurality of first power supply lines VDD1 connected to each first pixel unit P30 in a one-to-one correspondence pass through the via holes VH9 and via holes VH3 passing through the third insulating layer 143 and the first electrode. Board CE1 connection.
  • the first power line VDD1 may also be connected to the first electrode plate CE1 through one of the via hole VH9 and the via hole VH3.
  • the first electrode plates CE1 of the two first pixel units P31 in the same row of the first pixel unit group P30 are connected to each other and formed integrally to save manufacturing process flow and reduce cost. That is, the first power line VDD1 in each first pixel unit P31 is connected to the first plate CE1 of the storage capacitor 13 of the corresponding first pixel unit P31 to be electrically connected to the first pixel unit P31.
  • the first power supply lines VDD1 in the two first pixel units P31 are electrically connected.
  • the first power lines VDD1 located in different rows are connected to each other correspondingly and are integrally formed. As mentioned above, when the first power supply lines VDD1 in the two first pixel units P31 in the same row belonging to a first pixel unit group P30 are electrically connected, the two first power lines LS31 can be connected The first power line VDD1 in one of the first pixel units P31 is connected to reduce the number of wires.
  • the display substrate 1 further includes a fourth transfer electrode TS34, and the fourth transfer electrode TS24 (for example, most of the fourth transfer electrode TS24) extends along the second direction X1.
  • the fourth transfer electrode TS34 is arranged adjacent to the second direction X1 and is electrically connected to the first power line VDD1 to which the first pixel units P31 belonging to different first pixel unit groups P30 are respectively connected.
  • a plurality of first pixel unit groups P30 are arranged in the form shown in FIG. 1B. That is, the multiple first pixel unit groups P30 in two adjacent columns are located in different rows to leave more gaps between the first pixel unit groups P30, thereby allowing the Light through.
  • both ends of the fourth transfer electrode TS34 are respectively connected to the first electrode plates CE1 of two first pixel units P31 that are adjacently arranged and belong to different first pixel unit groups P30.
  • the fourth switching electrode TS24 further includes a portion extending along the first direction Y1. That is, the fourth transfer electrode TS34 first extends along the first direction Y1, then along the second direction X1, and then along the first direction Y1.
  • the fourth transfer electrode TS34 includes a first sub-transfer electrode TSP1, a second sub-transfer electrode TSP2, and a third sub-transfer electrode TSP3.
  • the first sub-transfer electrode TSP1 The first pixel unit group P30 on the left side of the connection diagram is in an "L" shape.
  • the second sub-transfer electrode TSP2 is connected to the first pixel unit group P30 on the right side in the figure, and has an "L" shape.
  • the first terminal TSP11 of the first sub-transition electrode TSP1 and the first terminal TSP21 of the second sub-transition electrode TSP2 are respectively connected to two ends of the third sub-transition electrode TSP3.
  • the third sub-transfer electrode TSP3 extends along the second direction X1.
  • the second terminal TSP2 of the first sub-transition electrode TSP1 and the second terminal TSP21 of the second sub-transition electrode TSP2 are respectively connected to the first of two first pixel units P31 arranged adjacently and belonging to different first pixel unit groups P30. Connect CE1 to the plate.
  • the third sub-transition electrode TSP3 can reduce the interference of the electrical signals of other traces on the fourth transition electrode TS34.
  • FIG. 16B is a schematic cross-sectional view along the line C33-C34 in FIG. 15.
  • the lines C33-C34 pass through the first sub-transition electrode TSP1, the second sub-transition electrode TSP2, and the third sub-transition electrode TSP3.
  • the first sub-transition electrode TSP1 and the second sub-transition electrode TSP2 are located between the second insulating layer 142 and the third insulating layer 143, that is, the first sub-transition electrode TSP1 and the second sub-transition electrode TSP1
  • the second transfer electrode TSP2 is located on the second conductive layer GA32.
  • the first sub-transition electrode TSP1 and the second sub-transition electrode TSP2 are connected to the first electrode plate CE1 of the first pixel unit P31 adjacent to each other and belong to a different first pixel unit group P30, and may be integrally formed.
  • the third sub-transfer electrode TSP3 is located on the side of the third insulating layer 143 away from the base substrate 100, that is, located on the third conductive layer SD31.
  • the fourth via hole GH33 is a via hole that penetrates the third insulating layer
  • the fifth via hole GH34 is also a via hole that penetrates the third insulating layer.
  • the third sub-transition electrode TSP3 is connected to the first terminal TSP11 of the first sub-transition electrode TSP1 through the fourth via GH33, and the third sub-transition electrode TSP3 is connected to the second sub-transition electrode TSP2 through the fifth via GH34.
  • the first end TSP21 is connected.
  • first pixel units P31 the first column of the first row of the first pixel unit group P30 (that is, the left side )
  • the first plate CE1 of the first pixel unit P31 is connected to the fourth transfer electrode TS34 on the upper left, and the fourth transfer electrode TS34 on the upper left is also connected to the second row of the first pixel unit group P30 on the upper left.
  • the first electrode plate CE1 of the first pixel unit P31 in the second column ie, the right side
  • the first electrode plate CE1 of the first pixel unit P31 in the first row and second column of the first pixel unit group P30 (ie, the right side) is connected to the fourth transfer electrode TS34 on the upper right, and the fourth transfer electrode on the upper right
  • the TS34 is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P21 in the first column of the second row (ie, the left side) of the first pixel unit group P30 located at the upper right.
  • the first electrode plate CE1 of the first pixel unit P31 in the first column (ie, the left side) of the second row of the first pixel unit group P30 may also be connected to the fourth transfer electrode TS34 at the bottom left.
  • the fourth transfer electrode TS34 at the bottom left is also connected to the first electrode plate CE1 of the first pixel unit P31 in the second column (ie, on the right) of the first row of the first pixel unit group P30 at the bottom left.
  • the first electrode plate CE1 of the first pixel cell P31 in the second row and second column of the second row of the first pixel cell group P30 (ie, the right side) is connected to the fourth transition electrode TS34 at the bottom right, and the fourth transition electrode at the top right
  • the TS34 is also connected to the first electrode plate CE1 (not shown in the figure) of the first pixel unit P31 in the first column of the first row of the first pixel unit group P30 (ie, the left side) located at the bottom right.
  • the width W35 of the fourth transfer electrode TS34 (for example, perpendicular to the routing direction of the fourth transfer electrode TS34) has a value range, for example, about 2-3 microns, and the value of the width W35 , For example, about 2.5 microns.
  • FIG. 17D is a schematic diagram of the arrangement of sub-pixels in the first display area shown in FIG. 14.
  • the four first pixel units P31 of the first pixel unit group P30 arranged in two rows and two columns may respectively include a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel ( G1) and green sub-pixels (G2) (that is, two green sub-pixels), that is, in a first pixel unit group P30, the two first pixel units P31 located in the first row include red sub-pixels (R) And the green sub-pixel (G1), the two first pixel units P31 in the second row include the blue sub-pixel (B) and the green sub-pixel (G2), that is, in one first pixel unit group P30, the first pixel unit P31
  • the light emitting device 11 of the first pixel unit P31 in the first column (that is, the upper left corner) of a row emits red light, and the light emitting device of the
  • the arrangement of the first pixel unit and the wiring in the first display area of the display substrate shown in FIG. 2, FIG. 6, FIG. 10, and FIG. In terms of efficiency, the embodiment shown in FIG. 10 is smaller than the embodiment shown in FIG. 6 than the embodiment shown in FIG. 14 is smaller than the embodiment shown in FIG. 2. In terms of the display effect of the first display area 10, the embodiment shown in FIG. 2 is smaller than the embodiment shown in FIG. 6 is smaller than the embodiment shown in FIG. 10, and the embodiment shown in FIG. 10 is equal to the embodiment shown in FIG. example.
  • the arrangement of the first pixel units and the wiring in the first display area can be flexibly selected according to the requirements of the product in terms of light transmittance and display effect in the first display area 10.
  • the first signal line DATA1 and the first power supply line VDD1 connected to the first pixel unit of the first pixel unit group P0 close to the second display area 20 It extends to the second display area 20 to be connected to the second pixel unit C located in the first direction Y1 with respect to the first pixel unit P0 (P10/P20/P30).
  • a row of first pixel units located closest to the second display area 20 (for example, the bottom or top of the first display area 10), the first pixel unit connected to the first pixel unit A signal line DATA1 and a first power supply line VDD1 may extend to the second display area 20 so as to be connected to the second pixel unit C in the second display area 20.
  • the second pixel unit C in the first direction Y1 (that is, located in the same column as the first pixel unit in the first display area 10) consists of a first A signal line DATA1 and a first power line VDD1 are connected to provide the same first display signal and first power voltage.
  • FIG. 18 is a schematic diagram of a planar layout of wiring in the second display area of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate further includes a plurality of second signal lines DATA2 and a plurality of second power lines VDD2 located in the second display area 20.
  • the plurality of second pixel units C of the second display area 20 are arranged in multiple columns parallel in the second direction X1, that is, arranged in multiple rows and multiple columns arranged in an array, and the plurality of second pixel units C are arranged There are no gaps between adjacent rows of cloth and adjacent columns.
  • the pixel density of the second display area 20 is greater than the pixel density of the first display area 10.
  • the second signal line DATA2 extends along the first direction Y1, and each of the plurality of second signal lines DATA2 passes through the plurality of second pixel units C arranged in a row in the first direction Y1, and is arranged in a row.
  • the plurality of second pixel units C are electrically connected to provide a second display signal to the plurality of second pixel units C.
  • the second power supply line VDD2 extends along the first direction Y1, and each of the plurality of second power supply lines VDD2 passes through the plurality of second pixel cells C arranged in a row in the first direction Y1, and is arranged in a row.
  • the plurality of second pixel units C are electrically connected to provide the second power supply voltage to the plurality of second pixel units C.
  • the structure of the second pixel driving circuit of the second pixel unit C may be the same as the structure of the first pixel driving circuit of the first pixel unit P1 (P11/P21/P31), for example, the structure shown in FIG. 20A may be selected.
  • the electrical connection mode of the second power line VDD2 and the second pixel unit C can be the same as the electrical connection mode of the second power line VDD1 and the first pixel unit P1 (P11/P21/P31), that is, the second power line VDD2 and
  • the first plate CE21 of the storage capacitor of the second pixel driving circuit of the second pixel unit C is connected.
  • the first plates CE0 of the second pixel units C located in the same row are connected to each other and formed integrally, so that the second power supply voltages of the plurality of second pixel units C in the second display area 20 are the same.
  • the second pixel drive circuit of the second pixel unit C can choose the same circuit structure as the first pixel drive circuit of the first pixel unit P1 (P11/P21/P31).
  • the first pixel drive circuit will be described in detail.
  • the pixel driving circuit takes the 7T1C circuit as an example, and the first pixel driving circuit will not be described in detail.
  • FIG. 19 is an equivalent circuit diagram of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure.
  • 20B-20E are schematic diagrams of each layer of a first pixel driving circuit in a first display area of a display substrate provided by at least one embodiment of the present disclosure.
  • the first pixel driving circuit includes a plurality of thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a Seven transistors T7, multiple signal lines and storage capacitors 13 connected to multiple thin film transistors T1, T2, T3, T4, T5, T6, and T7, that is, the pixel circuit in this embodiment has a 7T1C structure.
  • the plurality of signal lines include gate lines GLn/GLn-1 (ie, scan signal lines), light emission control lines EM, initialization lines RL, first signal lines DATA1, and first power supply lines VDD1.
  • the gate line GLn/GLn-1 may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn is used to transmit the gate scan signal
  • the second gate line GLn-1 is used to transmit the reset voltage signal.
  • the emission control line EM is used to transmit the emission control signal, for example, is connected to the first emission control terminal EM1 and the Two light-emitting control terminal EM2.
  • the gate of the fifth transistor T5 is connected to the first light emission control terminal EM1, or used as the first light emission control terminal EM1 to receive the first light emission control signal;
  • the gate of the sixth transistor T6 is connected to the second light emission control terminal EM2, or As the second light emission control terminal EM2, to receive the second light emission control signal.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned 7T1C structure pixel circuit.
  • the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, which is not limited by the embodiment of the present disclosure.
  • the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal; the second source S2 of the second thin film transistor T2 is configured To be electrically connected to the first signal line DATA1 to receive data signals.
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line GLn of the first thin film transistor T1.
  • the drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the fourth source S4 of the fourth thin film transistor T4 is configured
  • the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fifth gate electrode of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
  • the fifth source electrode S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
  • a power line VDD1 is electrically connected to receive the first power signal
  • the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film transistor.
  • the first drain D1 of T1 is electrically connected, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first electrode (for example, the anode 211) of the light-emitting element 11.
  • the thin film transistor T6 in FIG. 22 is the sixth thin film transistor T6.
  • the seventh gate of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the seventh source S7 of the seventh thin film transistor T7 is The first electrode (for example, the anode 111) of the element 11 is electrically connected
  • the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization voltage signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2.
  • the first electrode plate CE1 is electrically connected to the first power line VDD1
  • the second electrode plate CE2 is electrically connected to the first gate electrode of the first thin film transistor T1 and the third drain electrode D3 of the third thin film transistor T3.
  • the first power line VDD1 and the first plate CE1 of the storage capacitor 13 are connected through the third via VH3 and the ninth via VH9, and the first plate CE1 of the storage capacitor 13 is connected to the first plate CE1 through the first sub-wiring 2422.
  • the first electrode plates CE1 that are adjacent in the two directions X1 are connected.
  • the second electrode (for example, the cathode 113) of the light-emitting element 11 is electrically connected to the second power supply line VSS.
  • the first power line VDD1 provides a high voltage power line for the first pixel driving circuit
  • the second power line VSS provides a low voltage (lower than the aforementioned high voltage) power line for the first pixel driving circuit.
  • the first power supply line VDD1 provides a constant first power supply voltage, and the first power supply voltage is a positive voltage
  • the second power supply line VSS provides a constant second power supply voltage
  • the second power supply voltage can be It is negative voltage and so on.
  • the second power supply voltage may be a ground voltage.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, all or part of the source and drain of the transistor are as required Are interchangeable.
  • the pixel circuit includes the aforementioned thin film transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor 13, connected to a plurality of thin film transistors T1, T2, T3, T4, The first gate line GLn, the second gate line GLn-1, the light emission control line EM, the initialization line RL, the first signal line DATA1, and the first power supply line VDD1 of T5, T6, and T7.
  • FIG. 20A is a schematic layout diagram of the stacked positional relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel circuit.
  • FIG. 20B shows the semiconductor layer of the pixel circuit.
  • the semiconductor layer shown in FIG. 20B includes the active layer 121 shown in FIG. 21, and the active layer 121 is, for example, the active layer of the sixth thin film transistor T6.
  • the semiconductor layer can be formed by a patterning process using a semiconductor material layer.
  • the semiconductor layer can be used to make the aforementioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6, and seventh thin film transistor T7.
  • the source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials (for example, indium gallium tin oxide (IGZO)), or the like.
  • oxide semiconductor materials for example, indium gallium tin oxide (IGZO)
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • one or more other insulating layers are formed on the aforementioned semiconductor layer, and the insulating layer includes the first insulating layer 141 shown in FIG. 21; for clarity, FIG. 20A
  • the insulating layer is not shown in -20E, but is shown in the subsequent Figure 21 and Figure 22, which will be described in detail later.
  • FIG. 20C shows the first conductive layer of the first pixel driving circuit.
  • the first conductive layer may include the second plate CE2 of the storage capacitor 13, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the first thin film transistor T1, The gates of the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7.
  • the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are the first gate line GLn and the second gate line GLn- 1 The part that overlaps the semiconductor layer.
  • the third thin film transistor T3 may be a thin film transistor with a double-gate structure, one gate of the third thin film transistor T3 may be the part where the first gate line GLn overlaps the semiconductor layer, and the other gate of the third thin film transistor T3 may be A protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first electrode plate CE1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping portions of the second gate line GLn-1 and the semiconductor layer.
  • the gates of the above-mentioned thin film transistors are respectively integrally formed with the corresponding first gate line GLn or the second gate line GLn-1.
  • the insulating layer includes the second insulating layer 142 shown in FIG. 21.
  • FIG. 20D shows the second conductive layer of the first pixel driving circuit.
  • the second conductive layer of the first pixel driving circuit includes the first plate CE1 of the storage capacitor 13, the initialization line RL, and the second sub-wiring 2422, that is, the second sub-wiring 2422 and the storage capacitor 13
  • the first electrode plate CE1 of the capacitor 13 is arranged in the same layer and formed integrally.
  • the second sub-wiring 2422 can also be regarded as a part of the extension of the first electrode plate CE1.
  • the second electrode plate CE2 and the first electrode plate CE1 at least partially overlap to form a storage capacitor 13.
  • the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792.
  • the orthographic projection of the first light shielding portion 791 on the base substrate 100 covers the active layer between the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3 and the drain of the fourth thin film transistor T4, thereby Prevent external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
  • the orthographic projection of the second light shielding portion 792 on the base substrate 100 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
  • the first light shielding portion 791 may be an integral structure with the second light shielding portion 792 of the adjacent pixel circuit, and is electrically connected to the first power line VDD1 through the tenth via VH9' in the insulating layer, as shown in FIG. 20A.
  • the insulating layer includes the third insulating layer 143 shown in FIG. 21.
  • FIG. 20E shows the third conductive layer of the pixel circuit.
  • the third conductive layer of the first pixel driving circuit includes a first signal DATA1 and a first power supply line VDD1.
  • the first signal line DATA1 passes through at least one via (for example, via VH1) in the first insulating layer, the second insulating layer, and the third insulating layer and the second thin film transistor T2 in the semiconductor layer. Connected to the source region.
  • the first power line VDD1 is connected to the source region of the semiconductor layer corresponding to the fifth thin film transistor T5 through at least one via (for example, via VH2) in the first insulating layer, the second insulating layer, and the third insulating layer.
  • the first power line VDD1 is connected to the first electrode plate CE1 in the second conductive layer through at least one via (for example, via VH3) in the third insulating layer.
  • the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3.
  • One end of the first connecting portion CP1 is connected to the drain region of the semiconductor layer corresponding to the third thin film transistor T3 through at least one via (for example, via VH4) in the first insulating layer, the second insulating layer and the third insulating layer,
  • the other end of the first connecting portion CP1 is connected to the gate of the first thin film transistor T1 in the first conductive layer through at least one via (for example, via VH5) in the second insulating layer and the third insulating layer.
  • One end of the second connection part CP2 is connected to the initialization line RL through a via (for example, via VH6) in the third insulating layer, and the other end of the second connection part CP2 is connected to the initialization line RL through the first insulating layer, the second insulating layer, and the third insulating layer.
  • At least one via (for example, via VH7) in the insulating layer is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection portion CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (for example, via hole VH8) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer .
  • FIG. 21 is a schematic cross-sectional view of a first display area in a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 1 further includes a first planarization layer 144 and a pixel defining layer 145.
  • the first pixel unit includes a first light emitting device 11 and a first pixel driving circuit 12.
  • the first planarization layer 144 is located on a side of the first pixel driving circuit 12 away from the base substrate 100 to provide a planarized surface, and the first planarized layer 144 provides a planarized surface and includes a via 144A.
  • the sixth transistor T6 includes an active layer 121, a gate 122, and source and drain electrodes (source 123 and drain 124).
  • the storage capacitor 13 includes a first electrode plate CE1 and a second electrode plate CE2.
  • the active layer 121 is disposed on the base substrate 100, the first insulating layer 141 is disposed on the side of the active layer 121 away from the base substrate 100, and the gate 122 and the second electrode plate CE2 are disposed on the same layer on the first insulating layer.
  • the second insulating layer 142 is disposed on the side of the gate 122 and the second electrode plate CE2 far away from the base substrate 100.
  • the first electrode plate CE1 is arranged on the side of the second insulating layer 142 away from the base substrate 100
  • the third insulating layer 143 is arranged on the side of the first electrode plate CE1 away from the base substrate 100.
  • the source electrode 123 and the drain electrode 124 are disposed on the side of the third insulating layer 143 away from the base substrate 100, and pass through the via holes and the active layer in the first insulating layer 141, the second insulating layer 142, and the third insulating layer 143 121 electrical connection.
  • the material of the first planarization layer 144 includes inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may also include polyimide, polyphthalimide, polyphthalamide, acrylic resin, and benzocyclobutyl.
  • Organic insulating materials such as olefins or phenolic resins are not limited in the embodiments of the present disclosure.
  • the material of the active layer 121 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 122 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium. Metal stack (Ti/Al/Ti)).
  • the material of the source electrode 123 and the drain electrode 124 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal laminated layer (such as titanium, Aluminum and titanium three-layer metal stack (Ti/Al/Ti)).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the first light emitting device 11 includes a first electrode 111 (for example, an anode), a first light emitting layer 112, and a second electrode 113 (for example, a cathode).
  • the first electrode 111 is located on a side of the first planarization layer 144 away from the base substrate 100 and is connected to the source 123 (or drain 124) of the sixth transistor T6 through the via 144A of the first planarization layer 144.
  • the pixel defining layer 145 is located on a side of the first electrode 111 of the first light emitting device 11 away from the base substrate 100 and includes a first pixel opening 145A.
  • the first pixel opening 145A corresponds to the first light emitting device 11 to form a light emitting area of the first light emitting device 11.
  • the second electrode 113 is located on the side of the pixel defining layer 145 away from the base substrate 100.
  • the light emitting layer 112 is located in the first pixel opening 145A and between the first electrode 111 and the second electrode 112. The portion of the light-emitting layer 112 directly sandwiched between the first electrode 111 and the second electrode 112 will emit light after being energized, so the area occupied by this portion corresponds to the light-emitting area.
  • the material of the pixel defining layer 145 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the material of the first electrode 111 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 111 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the first light-emitting layer 112 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red, green, blue, or white light; and, If necessary, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 113 may include various conductive materials.
  • the second electrode 113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • a passivation layer may be provided between the first planarization layer and the source electrode 123 and the drain electrode 124.
  • the passivation layer may be configured to include a via hole to expose one of the source electrode 123 and the drain electrode 124, for example, to expose the drain electrode 124.
  • the passivation layer can protect the source electrode 123 and the drain electrode 124 from being corroded by water vapor.
  • the material of the passivation layer may include organic insulating materials or inorganic insulating materials, for example, silicon nitride material, which can protect the first pixel circuit due to its high dielectric constant and good hydrophobic function. 12 Not corroded by water vapor.
  • a transfer electrode may be further provided between the first electrode 111 and the first pixel circuit 12, and the transfer electrode is connected to the first electrode 111 and the first pixel circuit 12 to connect the first electrode 111 and the first pixel circuit 12 Electric connection.
  • the embodiments of the present disclosure are not limited to the specific structure of the first pixel unit.
  • the display substrate 1 further includes an encapsulation layer 146.
  • the encapsulation layer 146 is located on the side of the second electrode 113 away from the base substrate 100.
  • the encapsulation layer 146 seals the first light emitting device 11, so that deterioration of the first light emitting device 11 caused by moisture and/or oxygen included in the environment may be reduced or prevented.
  • the encapsulation layer 146 may have a single-layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 146 includes at least one encapsulation sublayer.
  • the encapsulation layer 146 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially arranged.
  • the material of the encapsulation layer 146 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • FIG. 22 is a schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure.
  • Each of the plurality of second pixel units C of the second display area 20 of the display substrate 1 includes a second light emitting device 21 and a second pixel driving circuit 22, and the second pixel driving circuit 22 is electrically connected to the second light emitting device 21 to drive the second light emitting device 21.
  • the second pixel driving circuit 22 includes structures such as a sixth transistor T6' and a storage capacitor 23.
  • the second light emitting device 21 includes a third electrode 211, a fourth electrode 213, and a second light emitting layer 212 between the third electrode 211 and the fourth electrode 213.
  • the first planarization layer 144 is located on a side of the second pixel driving circuit 22 away from the base substrate 100 to provide a planarized surface, and the first planarized layer 144 provides a planarized surface and includes a via 144A.
  • the third electrode 211 is electrically connected to the second pixel driving circuit 22 through the via 144A.
  • the third electrode 211 is the anode of the second light-emitting device 21, and the fourth electrode 213 is the cathode of the second light-emitting device 21.
  • the pixel defining layer 145 is disposed on a side of the third electrode 211 away from the base substrate 100 and includes a plurality of openings.
  • the second optical layer 212 is disposed in the plurality of openings of the pixel defining layer 145.
  • the fourth electrode 213 is disposed on the side of the second light-emitting layer 212 and the pixel defining layer 145 away from the base substrate 100.
  • the third electrode 211 and the first electrode 111 are provided in the same layer and the same material, and the fourth electrode 213 and the second electrode 113 are provided in the same layer and the same material.
  • the second light-emitting layer 212 and the first light-emitting layer 112 are arranged in the same layer and have the same material.
  • the sixth transistor T6' includes an active layer 221, a gate 222, source and drain electrodes (ie, a source 223 and a drain 224) and other structures, and the storage capacitor 23 includes a first electrode plate CE21 and a second electrode plate CE22.
  • the active layer 321 is disposed on the base substrate 100
  • the first insulating layer 141 is disposed on the side of the active layer 221 away from the base substrate 100
  • the gate 222 and the second electrode plate CE22 are disposed on the same layer on the first insulating layer.
  • the third insulating layer 143 is disposed on the side of the first electrode plate CE21 far away from the base substrate 100, and the source and drain electrodes are disposed on a side of the third insulating layer 143 away from the base substrate 14. It is electrically connected to the active layer 221 through the via holes in the first insulating layer 141, the second insulating layer 142, and the third insulating layer 143.
  • the flattening layer 144 provides a first flattened surface to flatten the third pixel circuit.
  • the active layer 221, the gate 222, the source and drain electrodes (ie, the source 223 and the drain 224) of the sixth transistor T6' are respectively connected to the source layer 121, the gate 122, and the source and drain electrodes (source and drain electrodes) of the sixth transistor T6.
  • the electrode 123 and the drain electrode 124) are arranged in the same layer and have the same material.
  • the first electrode plate CE21 and the second electrode plate CE22 of the storage capacitor 23 are arranged in the same layer and the same material as the first electrode plate CE1 and the second electrode plate CE2 of the storage capacitor 13 respectively.
  • the second pixel driving circuit 22 in the second display area 20 and the first pixel driving circuit 12 in the first display area 10 have the same structure, and therefore can be formed by the same patterning process in the manufacturing process.
  • the first insulating layer 141, the second insulating layer 142, the third insulating layer 143, the first planarization layer 144, the pixel defining layer 145, and the encapsulation layer 146 are in the same layer in the second display area 20 and the first display area 10.
  • the provided ones are integrated in some embodiments, such as the same insulating layer, so the same reference numerals are used in the drawings.
  • the base substrate 100 in at least one embodiment of the present disclosure may be a glass plate, a quartz plate, a metal plate, or a resin plate.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate.
  • resin materials such as polyethylene naphthalate; for example, the base substrate 100 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • FIG. 23 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, and the display device 20 may include the display substrate 1 of any of the above-mentioned embodiments.
  • the display device 2 may also include a flexible circuit board and a control chip.
  • the flexible circuit board is bonded to the bonding area of the display substrate 1, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby connecting with the display area. Area electrical connection.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), and so on.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires, signal lines, and the like.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • the display device 2 provided by at least one embodiment of the present disclosure may be any product or component with display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device 2 may also include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiment of the present disclosure.
  • the display device 2 further includes a sensor 192.
  • the sensor 192 is provided on the second side S2 (for example, the non-display side) of the display substrate 1.
  • the sensor 192 is configured to receive light (for example, collimated light or collimated light) from the first side S1 of the display substrate 1 (for example, the display side of the display substrate).
  • the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps the first display area 10.
  • the senor 192 is an image sensor, an infrared sensor, a distance sensor, etc.
  • the sensor 192 may be implemented in the form of a chip or the like, for example.
  • the sensor 192 is provided on the non-display side S2 (the side facing away from the user) of the display substrate.
  • the senor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.
  • the sensor 192 may be an image sensor, and may be used to collect images of the external environment facing the light-collecting surface of the sensor 192, for example, it may be a CMOS image sensor or a CCD image sensor; the sensor 192 may also be an infrared sensor or a distance sensor. Wait.
  • the sensor 192 can be used to implement a camera of a mobile terminal such as a mobile phone and a notebook, and can also include optical devices such as a lens, a mirror, or an optical waveguide as required to modulate the optical path.
  • the embodiment of the present disclosure does not limit the type, function, and setting method of the sensor 192.
  • the sensor 192 is arranged on the non-display side S2 of the display panel by means of double-sided tape, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps the first display area 10, and is configured to receive light from the first side S1 . Therefore, the first display area 10 provides convenience for the setting of the sensor 192 while realizing display.

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Abstract

一种显示基板和显示装置。该显示基板具有用于显示的第一侧和与第一侧相对的第二侧，包括：衬底基板、显示区、至少一条连接走线以及至少一条转接电极。至少一条连接走线的每条至少部分沿第一方向延伸，并与在第一方向上的相邻的第一显示区的第一像素单元组分别连接的第一电源线相连接；至少一条转接电极的每条至少部分沿第一方向延伸，并与在第一方向上的相邻的第一显示区的第一像素单元组分别连接的第一信号线相连接；其中，至少一条转接电极的至少部分条转接电极所在的膜层与至少一条连接走线的每条所在的膜层不同，并且至少一条转接电极在衬底基板上的正投影与至少一条连接走线在衬底基板上的正投影至少部分重叠。

Description

显示基板和显示装置
本申请要求于2020年6月18日提交的中国专利申请第202010558219.9的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
市场对于高屏占比的显示面板的需求越来越迫切，以使用户具有更好的视觉体验。以手机、平板电脑等电子产品为例，由于这些电子装置需要结合摄像头、光线传感器等部件，现有的“刘海屏”、“水滴屏”等设计逐渐不能满足用户的需求，在此背景下，屏下摄像头技术应运而生，它不需要在屏上打孔来放置摄像头，使真全面屏成为可能。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括：衬底基板、显示区、至少一条连接走线以及至少一条转接电极。显示区设置在所述衬底基板上，包括第一显示区，所述第一显示区允许来自所述显示基板的第一侧的光至少部分透射至所述显示基板的第二侧，其中，所述第一显示区包括第一子像素阵列，所述第一子像素阵列包括在第一方向以及与所述第一方向交叉的第二方向上排布的多个第一像素单元组、多条第一信号线以及多条第一电源线，所述第一像素单元组包括至少一个第一像素单元，所述多条第一信号线的每条至少部分沿所述第一方向延伸，并配置为给所述多个第一像素单元提供第一显示信号，所述多条第一信号线与所述多个第一像素单元组的第一像素单元连接，所述多条第一电源线至少部分沿所述第一方向延伸，并配置为给所述多个第一像素单元提供第一电源电压，所述多条第一电源线与所述多个第一像素单元组的第一像素单元连接；至少一条连接走线的每条至少部分沿所述第一方向延伸，并与在所述第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接；至少一条转接电极的每条至少部分沿所述第一方向延伸，并与在所述第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接；其中，所述至少一条转接电极的至少部分条转接电极所在的膜层与所述至少一条连接走线的每条所在的膜层不同，并且所述至少一条转接电极在所述衬底基板上的正投影与所述至少一条连接走线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示基板中，所述至少一条连接走线包括第一连接走线，所述第一连接走线沿所述第一方向延伸，所述第一连接走线与在所述第一方向上相邻的且属于不同第一像素单元组的第一像素单元分别连接的第一电源线相连接，所述第一连接走线与所述第一电源线同层设置且一体形成。
例如，在本公开至少一实施例提供的显示基板中，所述第一像素单元组的至少一个第一像素单元 包括多个第一像素单元，所述至少一条转接电极包括多条转接电极，所述多条转接电极一一对应连接在所述第一方向上相邻且属于不同第一像素单元组的多个第一像素单元，所述多条转接电极分别所在的膜层不同。
例如，在本公开至少一实施例提供的显示基板中，所述第一像素单元组的多个第一像素单元排布为沿所述第二方向并列的至少两列，所述多条转接电极包括第一转接电极以及第二转接电极，所述第一转接电极以及所述第二转接电极并列设置，所述第一转接电极以及所述第二转接电极与在所述第一方向上相邻的且属于不同第一像素单元组的第一像素单元分别连接的第一信号线相连接，所述第一转接电极以及所述第二转接电极所在膜层不同，所述第一转接电极与所述第二转接电极在所述衬底基板上的正投影与所述第一连接走线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示基板中，所述第一转接电极的沿所述第一方向延伸的部分以及所述第二转接电极的沿所述第一方向延伸的部分在所述衬底基板的正投影，与所述第一连接走线沿所述第一方向延伸的部分在所述衬底基板的正投影重叠。
例如，在本公开至少一实施例提供的显示基板中，在所述第一方向以及与所述第二方向上相邻的第一像素单元组之间具有允许光透射的间隙，所述第一连接线的部分以及所述至少一条转接电极的的每条的部分沿所述第二方向延伸并绕过所述允许光透射的间隙。
例如，在本公开至少一实施例提供的显示基板中，所述第一连接走线为弯折走线，且包括第一部分、第二部分以及第三部分，所述第一部分的第一端和所述第二部分的第一端分别与所述第三部分的两端连接且沿与所述第一方向不同的第二方向延伸，所述第三部分沿所述第一方向延伸，所述第一部分的第二端和所述第二部分的第二端分别与在所述第一方向上的相邻的第一像素单元分别连接的第一电源线相连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一转接电极和所述第二转接电极在衬底基板上的正投影与所述第一连接走线的第一部分、第二部分以及第三部分的至少之一在所述衬底基板上的正投影重叠。
例如，在本公开至少一实施例提供的显示基板中，所述第一像素单元组的多个第一像素单元包括排布为沿所述第二方向并列的至少三列，所述至少一条转接电极包括第一转接电极、第二转接电极以及第三转接电极，所述第一转接电极、所述第二转接电极以及所述第三转接电极并列设置，所述第三转接电极位于所述第一转接电极以及所述第二转接电极之间，所述第一转接电极、所述第二转接电极以及所述第三转接电极分别对应与在所述第一方向上相邻的第一像素单元分别连接的第一信号线相连接，所述第一转接电极、所述第二转接电极以及所述第三转接电极所在膜层不同，所述第一连接走线在所述衬底基板上的正投影与所述第一转接电极以及所述第二转接电极的至少之一在所述衬底基板上的正投影至少部分重叠，所述第三转接电极与所述第一连接走线同层设置。
例如，在本公开至少一实施例提供的显示基板中，所述第三转接电极在所述衬底基板上的正投影与所述第一转接电极或所述第二转接电极在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板，还包括：第一绝缘层、第二绝缘层以及第三绝缘层，所述第一绝缘层位于所述衬底基板上，所述第二绝缘层位于所述第一绝缘层远离所述衬底基板的一侧，所述第三绝缘层位于所述第二绝缘层远离所述衬底基板的一侧，所述多条第一信号线、所述多条 第一电源线以及所述第一连接走线位于所述第三绝缘层远离衬底基板的一侧，所述第二转接电极位于所述第一绝缘层远离所述衬底基板的一侧，并通过贯穿所述第二绝缘层以及所述第三绝缘层的过孔连接，在所述第一方向上相邻的第一像素单元连接的第一信号线，所述第一转接电极位于所述第二绝缘层远离所述衬底基板的一侧，并通过贯穿所述第三绝缘层的过孔连接，在所述第一方向上相邻的第一像素单元连接的第一信号线，所述第三转接电极位于所述第三绝缘层远离所述衬底基板的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述第一像素单元组的多个第一像素单元排布为沿所述第二方向的至少一行，在同一行中，所述第一像素单元组包括至少两个第一像素单元，所述第一像素单元组的每个第一像素单元包括第一像素驱动电路以及第一发光器件，所述第一像素驱动电路与所述第一发光器件连接以及驱动所述第一发光器件发光，所述第一像素驱动电路包括存储电容，所述存储电容包括第一极板和与所述第一极板至少部分重叠设置的第二极板，所述第一极板位于所述第二绝缘层远离所述衬底基板的一侧，所述第二极板位于所述第一绝缘层远离所述衬底基板的一侧，与每个所述第一像素单元连接的所述多条第一电源线通过贯穿所述第三绝缘层的过孔与所述第一极板连接，所述第一像素单元组的位于同一行的至少两个第一像素单元的第一极板相互连接且一体形成。
例如，本公开至少一实施例提供的显示基板，还包括第四转接电极，其中，所述第四转接电极至少部分沿所述第二方向延伸，所述第四转接电极与所述第二方向错位且相邻设置且属于不同第一像素单元组的第一像素单元分别连接的第一电源线相连接。
例如，本公开至少一实施例提供的显示基板，还包括第四转接电极，其中，所述第四转接电极沿所述第二方向延伸，所述第四转接电极与所述第二方向相邻设置且属于不同第一像素单元组的两个第一像素单元分别连接的第一电源线相连接。
例如，在本公开至少一实施例提供的显示基板中，所述第四转接电极的两端，分别与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接，以将位于所述不同第一像素单元组中的第一电源线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第四转接电极位于所述第三绝缘层远离所述衬底基板的一侧，所述第四转接电极通过贯穿所述第三绝缘层的过孔，与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接。
例如，在本公开至少一实施例提供的显示基板中，所述第四转接电极位于所述第二绝缘层远离衬底基板的一侧，所述第四转接电极与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板同层设置且一体形成。
例如，在本公开至少一实施例提供的显示基板中，所述第四转接电极包括第一子转接电极、第二子转接电极以及第三子转接电极，所述第一子转接电极的第一端和所述第二子转接电极的第一端分别与所述第三子转接电极的两端连接，所述第一子转接电极的第二端和所述第二子转接电极的第二端分别与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接，所述第一子转接电极和所述第二子转接电极与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板同层设置且一体形成，所述第三子转接电极位于所述第三绝缘层的远离衬底基板的一侧，所述第三子转接电极通过贯穿所述第三绝缘层的过孔与所述第一子转接电极以及所述第二子转接电极连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一像素单元组的多个第一像素单元排布为多行多列，在同一个第一像素单元组中，与同一列的第一像素单元的连接的第一信号线相互连接且一体形成，与同一列的第一像素单元的连接第一电源线也相互连接且一体形成。
例如，在本公开至少一实施例提供的显示基板中，所述显示区还包括第二显示区，所述第二显示区至少部分围绕所述第一显示区，所述第二显示区包括第二子像素阵列，所述第二子像素阵列包括多个第二像素单元，所述多个第二像素单元的每个包括第二发光器件以及第二像素驱动电路，所述第二像素驱动电路被配置为驱动所述第二发光器件发光，与靠近所述第二显示区的第一像素单元连接的第一信号线延伸至所述第二显示区，以与相对于所述第一像素单元位于所述第一方向的第二像素单元连接，与靠近所述第二显示区的第一像素单元连接的第一电源线延伸至所述第二显示区，以与相对于所述第一像素单元位于所述第一方向的第二像素单元连接。
例如，在本公开至少一实施例提供的显示基板中，所述第二显示区的像素密度大于所述第一显示区的像素密度。
例如，本公开至少一实施例提供的显示基板，还包括位于所述第二显示区的多条第二信号线以及多条第二电源线，其中，所述多个第二像素单元排布为所述第二方向上并列的多列，所述多条第二信号线沿所述第一方向延伸，所述多条第二信号线的每条穿过在所述第一方向上排布为一列的所述多个第二像素单元，以向所述多个第二像素单元提供第二显示信号，所述多条第二电源线沿所述第一方向延伸，所述多条第二电源线的每条穿过在所述第一方向上排布为一列的所述多个第二像素单元，以向所述多个第二像素单元提供第二电源电压。
本公开至少一实施例还提供了一种显示装置，该显示装置包括如上所述的任一显示基板。
例如，本公开至少一实施例提供的显示装置，还包括传感器，其中，所述传感器设置于所述显示基板的第二侧，并且所述传感器配置为接收来自所述显示基板的第一侧的光。
例如，在本公开至少一实施例提供的显示装置中，所述传感器在所述衬底基板上的正投影与所述第一显示区至少部分重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A本公开至少一实施例提供的一种显示基板的平面示意图；
图1B为本公开至少一实施例提供的一种显示基板的局部放大示意图；
图1C为本公开至少另一实施例提供的一种显示基板的局部放大示意图；
图1D为沿图1A中线B1-B2的截面示意图；
图2为本公开至少一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图；
图3A为图2中A1区的放大图；
图3B为图2中A2区的放大图；
图4A为图3A中沿线C1-C2的截面示意图；
图4B为图3A中沿线C3-C4的截面示意图；
图4C为图3A中沿线C5-C6的截面示意图；
图4D为图3B中沿线C7-C8的截面示意图；
图5A-图5C为图2所示的第一显示区中走线的各层的平面示意图；
图5D为图2所示的第一显示区的子像素排布示意图；
图6为本公开至少另一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图；
图7A为图6中A11区的放大图；
图7B为图6中A12区的放大图；
图8为图7A中沿线C11-C12的截面示意图；
图9A-图9C为图6所示的第一显示区中走线的各层的平面示意图；
图9D为图6所示的第一显示区的子像素排布示意图；
图10为本公开至少再一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图；
图11为图10中A21区的放大图；
图12为图11中沿线C21-C22的截面示意图；
图13A-图13C为图10所示的第一显示区中走线的各层的平面示意图；
图13D为图10所示的第一显示区的子像素排布示意图；
图14为本公开至少再一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图；
图15为图14中A31区的放大图；
图16A为图15中沿线C31-C32的截面示意图；
图16B为图15中沿线C33-C34的截面示意图；
图17A-图17C为图14所示的第一显示区中走线的各层的平面示意图；
图17D为图14所示的第一显示区的子像素排布示意图；
图18为本公开至少一实施例提供的一种显示基板的第二显示区中走线的平面布局示意图；
图19为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的等效电路图；
图20A为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的平面布局示意图；
图20B-20E为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的各层的示意图；
图21为本公开至少一实施例提供的一种显示基板中第一显示区的截面示意图；
图22为本公开至少一实施例提供的一种显示基板中第二显示区的截面示意图；
图23为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所 获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同。为了描述方便，在部分附图中，给出了“上”、“下”、“前”、“后”，本公开的实施例中，竖直方向为从上到下的方向，竖直方向为重力方向，水平方向为与竖直方向垂直的方向，从右到左的水平方向为从前到后的方向。
近年来移动显示技术发展迅猛，以柔性有源矩阵有机发光二极体(Active-Matrix Organic Light-Emitting Diode，AMOLED)为代表的新一代显示技术正在得到越来越广泛的应用。AMOLED具有更薄更轻、主动发光(不需要背光源)、无视角问题、高清晰、高亮度、响应快速、能耗低、使用温度范围广、抗震能力强、可实现柔软显示等特点。由于这些显示装置需要结合摄像头、光线传感器等部件，而这些部件通常占据显示屏的显示区，由此导致显示屏难以实现全屏化设计。为了显示屏中的摄像头所在区域的透光率，保证摄像头的拍照效果，通常在摄像头所在区域仅保留像素电路的发光器件。但是上述技术仍然需要挖去部分显示区，总体效果还是形成异形的显示区，影响视觉体验，提升透光率来放置摄像头的技术。
为了避免牺牲显示区，出现了局部区域降低像素分辨率PPI(Pixels Per Inch)，提升透光率，由此来在显示基板背侧放置摄像头以对显示基板的显示侧进行成像的技术。该技术将摄像头放在低分辨率PPI的区域中，在该区域，由于分辨率PPI较低，而光透过率高，因此在显示基板的显示侧的光线可以通过低PPI区域到达位于显示基板背侧的摄像头上。像素驱动电路的横纵交叉走线形成光栅，仍然会对摄像头成像产生不利影响，也会降低PPI区域的开口率以及透光率。
本公开至少一实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括：衬底基板、显示区、至少一条连接走线以及至少一条转接电极。显示区设置在衬底基板上，且包括第一显示区，第一显示区允许来自显示基板的第一侧的光至少部分透射至所述显示基板的第二侧。第一显示区包括第一子像素阵列，第一子像素阵列包括在第一方向以及与第一方向交叉的第二方向上排布的多个第一像素单元组、多条第一信号线以及多条第一电源线。第一像素单元组包括至少一个第一像素单元。多条第一信号线的每条至少部分沿第一方向延伸，并配置为给多个第一像素单元提供第一显示信号，多条第一信号线与多个第一像素单元组的第一像素单元连接。多条第一电源线的每条至少部分沿第一方向延伸，并配置为给多个第一像素单元提供第一电源电压，多条第一电源线与多个第一像素单元组的第一像素单元连接。至少一条连接走线的每条至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接。至少一条转接电极的每条至少部分沿所述第一方向延伸并与在第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接。至少一条转接电极的至少部分条转接电极所在的膜层与至少一条连接走线所在的膜层不同，并且至少一条转接电极在衬底基板上的正投影与至少一条连接走线在衬底基板上的正投影至少部分重叠。
上述实施例提供的显示基板中，至少一条转接电极在衬底基板上的正投影与至少一条连接走线在 衬底基板上的正投影至少部分重叠，由此可以减少转接电极以及连接走线在第一显示区占据的布线空间，以有利于减小第一显示区中转接电极以及连接走线导致的光栅效应，以及提高第一显示区的开口率以及透光率，允许在第一显示区中且在该显示基板的第二侧设置例如传感器以进行感测(例如成像)，且改善该传感器的感测效果(成像质量)。
下面结合附图对本公开的实施例及其示例进行详细说明。
图1A本公开至少一实施例提供的一种显示基板的平面示意图；图1B为本公开至少一实施例提供的一种显示基板的局部放大示意图；图1C为本公开至少另一实施例提供的一种显示基板的局部放大示意图；图1D为沿图1A中线B1-B2的截面示意图。
例如，如图1A所示，本公开至少一实施例提供的显示基板1包括衬底基板100以及显示区。显示区设置在衬底基板100上，显示区包括第一显示区10(例如透光显示区)和第二显示区20(例如正常显示区)。显示基板1还可以包括周边区30，周边区30围绕(例如部分围绕)显示区。第二显示区20围绕(例如部分围绕)第一显示区10。
例如，本公开至少一实施例提供的显示基板1可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等显示基板，本公开的实施例对显示基板的具体种类不做限定。
例如，如图1D所示，第一显示区10为透光显示区，即允许来自显示基板1的第一侧S1(例如显示侧)的光至少部分透射至显示基板1的第二侧S2(例如非显示侧)，即来自显示侧的入射光透射通过第一显示区10以到达显示基板1的非显示侧。在显示基板1的第二侧S2还可以设置传感器192以接收该透射光，从而实现相应的功能(例如成像、红外感测、距离感测等)。例如，该传感器192设置在显示基板1的第二侧S2，传感器192在衬底基板100的正投影与第一显示区10至少部分重叠，且被配置为接收并处理来自显示基板1的第一侧S1的光。自显示基板1的第一侧S1的光可以是沿显示基板1的法线方向(例如Z1方向)的准直光，也可以是非准直光。
例如，传感器192为图像传感器、红外传感器、距离传感器等，传感器192例如可以实现为芯片等形式。传感器192设置在显示基板1的第二侧S2(背离使用者一侧)。传感器192与第一显示区10在显示基板的显示面的法线方向上至少部分重叠。
例如，传感器192可以是图像传感器，并可以用于采集传感器192的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器；该传感器192还可以是红外传感器、距离传感器等。该传感器192可用于实现诸如手机、笔记本的移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。本公开的实施例对于传感器192的类型、功能以及设置方式不作限制。
传感器192通过双面胶等方式设置在显示基板的第一侧S2，并且传感器192在衬底基板100上的正投影与第一显示区10至少部分重叠，配置为接收来自第一侧S1的光。由此，第一显示区10在实现显示的同时，还为传感器192的设置提供了便利。
例如，如图1B以及图1C所示，第一显示区10包括第一子像素阵列(第一显示区10中的灰色方框组成)，第一子像素阵列包括在第一方向Y1以及与第一方向Y1交叉的第二方向X1上排布的多个第一像素单元组P0(第一显示区10中的灰色方框)。多个第一像素单元组P0的每个还可以包括至少一个第一像素单元(例如多个第一像素单元)(后续详细介绍)。第一像素单元包括彼此直接连接的 第一发光器件以及第一像素驱动电路，第一像素驱动电路被配置为驱动第一发光器件发光。第一发光器件以及第一像素驱动电路位于同一像素区域中，在位置上没有彼此分离。
需要说明的是，第一方向Y1与第二方向X1可以垂直交叉也可以不垂直交叉，例如第一方向Y1与第二方向X1相互交叉的锐角的取值范围可以小于等于10°并大于等于45°。本公开实施例的附图中以第一方向Y1与第二方向X1垂直交叉为例示出。
多个第一像素单元组P0之间具有允许光通过的间隙，即第一显示区10中的空白区域，以允许来自第一侧S1的入射光可以通过相邻第一像素单元组P0之间的间隙透射，以保证第一显示区10的透光性。
例如，如图1B所示，多个第一像素单元组P0排布为相邻的两列之间错位排布，也即图中第一列的第一像素单元组P0，与第二列的第一像素单元组P0在第二方向X1上错开而分布在不同行。例如，相邻列的第一像素单元组P0不同行。
例如，如图1C所示，多个第一像素单元组P0排布为多行多列，也即图中第一列的第一像素单元组P0，与第二列的第一像素单元组P0在第二方向X1上间隔相邻。
例如，如图1B以及图1C所示，第二显示区20包括第二子像素阵列(第二显示区20中的白色方框组成)，第二子像素阵列包括多个第二像素单元C(第二显示区20中的白色方框)。多个第二像素单元C的每个包括彼此直接连接的第二发光器件以及第二像素驱动电路，第二像素驱动电路被配置为驱动第二发光器件发光。第二发光器件以及第二像素驱动电路位于同一像素区域中，在位置上没有彼此分离。
例如，第二显示区的像素密度大于第一显示区的像素密度，如图1B以及图1C所示，第一显示区10的第一像素单元组P0的排布密度，小于第二显示区20中的第二像素单元C的排布密度。也即，第一显示区10的分辨率设置的低于第二显示区20的分辨率，以留出空间允许光线通过，即第一显示区10内排布的用于显示的像素密度小于第二显示区20子像素密度。
例如，图2为本公开至少一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图。图3A为图2中A1区的放大图。图3B为图2中A2区的放大图。图5A-图5C为图2所示的第一显示区中走线的各层的平面示意图。图5A为图2所示的第一显示区中走线的位于第一导电层GA1的平面示意图。图5B为图2所示的第一显示区中走线的位于第二导电层GA2的平面示意图。图5C为图2所示的第一显示区中走线的位于第三导电层SD1的平面示意图。
例如，如图2以及图5C所示，第一显示区10包括多条第一信号线DATA1和多条第一电源线VDD1。第一像素单元组P0包括沿第一方向X1相邻排列的两个第一像素单元P1。多条第一信号线DATA1以及多条第一电源线VDD1沿第一方向Y1延伸。多条第一信号线DATA1的每个与多个第一像素单元组P0的第一像素单元P1一一对应并连接。多条第一电源线VDD1的每个与多个第一像素单元组P0的第一像素单元P1一一对应并连接。也就是说，每个第一像素单元P1中分别连接一条第一信号线DATA1和一条第一电源线VDD1。第一信号线DATA1配置为给第一像素单元P1提供第一显示信号。第一电源线VDD1配置为给多个第一像素单元P1提供第一电源电压。
需要说明的是，本公开实施例中的“连接”，包括走线或者电路的直接连接、以及走线或者电路的“电连接”、“信号连接”等。本公开实施例不以此为限。
例如，如图5C所示，位于同一个第一像素单元P1中的第一电源线VDD1和第一信号线DATA1并列设置。同一个第一像素单元组P0中的左侧的第一信号线DATA1的下部(用于连接转接电极的部分)向右侧弯折(也即向靠近与连接走线连接的第一电压线VDD1弯折)。
例如，显示基板1还包括至少一条连接走线，连接走线的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接。如图2、图3A以及图5C所示，显示基板1还包括多条连接走线(例如多条第一连接走线LS1)，多条连接走线的每条沿第一方向Y1延伸，并与第一方向Y1上相邻的第一像素单元组P0分别连接的第一电源线VDD1相连接。也即，第一方向Y1上相邻的第一像素单元组P0的两个相对应的第一像素单元P1中的第一电源线VDD1，与连接走线(例如第一连接走线LS1)连接。例如，与第一方向Y1上相邻的第一像素单元组P0的连接第一电源线VDD1通过一条连接走线(例如第一连接走线LS1)连接。也即，第一像素单元组P0的两个第一像素单元P1的其中之一中的第一电源线VDD1与连接走线(例如第一连接走线LS1)连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，显示基板还包括至少一条转接电极，转接电极的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接。如图2以及图3A所示，显示基板1还包括多条转接电极，例如转接电极包括第一转接电极TS1和第二转接电极TS2。多条转接电极的每条的主体部分(也即转接电极的大部分)沿第一方向Y1延伸，并分别与第一方向Y1上相邻的第一像素单元组P0分别连接的第一信号线DATA1相连接。也即，第一方向Y1上相邻的第一像素单元组P0的两个相对应的第一像素单元P1中的第一信号线DATA1，与多条转接电极的其中之一(第一转接电极TS1或第二转接电极TS2)连接。例如，与第一方向Y1上相邻的两个第一像素单元P1连接的第一信号线DATA1通过一条转接电极(第一转接电极TS1或第二转接电极TS2)连接。多条转接电极一一对应连接在第一方向Y1上相邻且属于不同第一像素单元组P0的多个第一像素单元P1。也即，第一像素单元组P0的两个第一像素单元P1的其中之一(例如位于一个像素单元P0的靠近左侧)中的第一信号线DATA1与一条转接电极(例如第一转接电极TS1)连接，第一像素单元组P0的两个第一像素单元P1的其中另一(例如位于一个像素单元P0的靠近右侧)中的第一信号线DATA1与一条转接电极(例如第二转接电极TS2)连接。
例如，相对于衬底基板1，至少一条转接电极的至少部分条所在的膜层与至少一条连接走线所在的膜层不同，并且至少一条转接电极在衬底基板上的正投影与至少一条连接走线在衬底基板上的正投影至少部分重叠。如图2以及图3A所示，多条第一连接走线(例如第一连接走线LS1)位于多条转接电极(例如第一转接电极TS1或第二转接电极TS2)远离衬底基板100的一侧。如图3A所示的，连接走线(例如第一连接走线LS1)在衬底基板100上的正投影与转接电极(例如第一转接电极TS1或第二转接电极TS2)在衬底基板100上的正投影部分重叠，例如，转接电极(例如第一转接电极TS1或第二转接电极TS2)沿第一方向Y1延伸的部分在衬底基板100上的正投影与连接走线(例如第一连接走线LS1)衬底基板100上的正投影重叠。例如，转接电极(例如第一转接电极TS1或第二转接电极TS2)沿第一方向Y1延伸的部分在衬底基板100上的正投影位于连接走线(例如第一连接走线LS1)在衬底基板100上的正投影中，使连接走线与转接电极重叠并遮挡转接电极，减少了转接电极的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产 生，进而允许在第一显示区中且在该显示基板1的第二侧S2设置例如传感器以进行感测(例如成像)，且改善该传感器的感测效果(成像质量)。
需要说明的是，在本公开实施例中的“膜层不同”包括两个功能层或结构层在显示基板的层级结构中不同层且不同材料形成，即在制备工艺中，该两个功能层或结构层可以由不同材料层形成，且可以通过不同构图工艺形成所需要的图案和结构。
例如，至少一条连接走线包括第一连接走线。如图2、图3A以及图5C所示，第一连接走线LS1沿第一方向Y1延伸，第一连接走线LS1与在第一方向Y1上相邻的且属于不同第一像素单元组P0的第一像素单元P1分别连接的第一电源线VDD1相连接。第一连接走线LS1与其所连接的第一电源线VDD1都基本位于第一方向Y1上。如图中所示的，在第一方向Y1上相邻的第一像素单元组P0之间存在间隙，以允许来自显示基板1的第一侧S1的光透过。在第一方向Y1上相邻的第一像素单元组P0的两个第一像素单元P1的其中之一与第一连接走线LS1连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，第一连接走线与第一电源线同层设置且一体形成。图4A为图3A中沿线C1-C2的截面示意图。线C1-C2沿第二方向X1穿过第一连接走线LS1，第一转接电极TS1以及第二转接电极TS2。
如图4A所示，显示基板1包括依次设置在衬底基板100上的第一绝缘层141(例如第一栅绝缘层)、第二绝缘层142(例如第二栅绝缘层)以及第三绝缘层143(例如层间绝缘层)。第二绝缘层142位于第一绝缘层141远离衬底基板100的一侧，第三绝缘层143位于第二绝缘层142远离衬底基板100的一侧。第一连接走线LS1位于第三绝缘层143远离衬底基板100的一侧，第一电源线VDD1与第一连接走线LS1同层设置且通过同一构图工艺一体形成。例如，如图5C所示，第一连接走线LS1以及第一电源线VDD1位于第三导电层SD1。
需要说明的是，在本公开实施例中的“一体形成”是指两种(或两种以上)的膜层或结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，第一连接走线LS1以及第一电源线VDD1(也即第三导电层SD1)也即的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。本公开的实施例对各功能层的材料不做具体限定。
需要注意的是，在本公开的实施例中，“同层设置”包括两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。一次构图工艺例如包括光刻胶的形成、曝光、显影、刻蚀等工序。
例如，第一绝缘层141、第二绝缘层142以及第三绝缘层143中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一绝缘层141、第二绝缘层142以第三绝缘层143的材料可以相同也可以不相同。
需要说明的是，在衬底基板100与第一绝缘层141之间还可以设置其它膜层，例如缓冲层、阻挡层等，本公开实施例不以此为限。
例如，如图3A、图5A以及图5B所示，多条转接电极包括第一转接电极TS1以及第二转接电极 TS2，第一转接电极TS1以及第二转接电极TS2的沿第一方向Y1延伸的部分并列设置。第一像素单元组P0的两个第一像素单元P1排布为沿第二方向Y1并列的两列。第一转接电极TS1以及第二转接电极TS2与在第一方向Y1上相邻的且属于不同第一像素单元组P0的第一像素单元P1分别连接的第一信号线DATA1相连接。也即，位于两列的第一像素单元组P0的两个第一像素单元P1分别与第一转接电极TS1以及第二转接电极TS2连接。第一转接电极TS1以及第二转接电极TS2先向靠近第一连接走线LS1的沿第二方向X1延伸，然后再沿第一方向Y1延伸，最后再沿第二方向X1延伸，以将在第一方向Y1上相邻且属于不同第一像素单元组P0的第一信号线DATA1相连接。第一转接电极TS1以及第二转接电极TS2的沿第二方向X1延伸的部分较短，并且第一转接电极TS1以及第二转接电极TS2的主体部分沿第一方向Y1延伸。
例如，如图5A所示，第二转接电极TS2呈向图中右侧(远离第一连接走线LS1)开口的类似“凹”字型或“]”型。而如图5B所示，第一转接电极TS1呈向图中左侧(远离第一连接走线LS1)开口的类似“凹”字型或“[”型。第二转接电极TS2以及第二转接电极TS1的方向相反，都是都汇聚到第一连接走线LS1所在的位置，以与第一连接走线LS1重叠。
例如，相对于衬底基板，多条转接电极分别所在的膜层不同。图4B为图3A中沿线C3-C4的截面示意图；图4C为图3A中沿线C5-C6的截面示意图。如图3A、4B以及图4C所示，相对于衬底基板100，第一转接电极TS1以及第二转接电极TS2所在膜层不同。第一转接电极TS1位于第二绝缘层142与第三绝缘层143之间。例如，如图5B所示，第一转接电极TS1位于第二导电层GA2。第二转接电极TS2位于第一绝缘层141与第二绝缘层142之间。例如，如图5A所示，第二转接电极TS2位于第一导电层GA1。第二绝缘层142将第一转接电极TS1以及第二转接电极TS2间隔绝缘。第一转接电极TS1以及第二转接电极TS2位于不同的膜层可以减小第一转接电极TS1以及第二转接电极TS2之间间隔的尺寸，从而减小第一转接电极TS1以及第二转接电极TS2占据的空间。
例如，第一转接电极TS1以及第二转接电极TS2(也即第一导电层GA1以及第二导电层GA2)的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。本公开的实施例对各功能层的材料不做具体限定。
例如，第一转接电极与第二转接电极在衬底基板上的正投影与第一连接走线在衬底基板上的正投影至少部分重叠。如图3A和图4A所示，第一连接走线LS1在衬底基板上的正投影与第一转接电极TS1(沿第一方向Y1延伸的部分)与第二转接电极TS2(沿第一方向Y1延伸的部分)在衬底基板上的正投影重叠。也即，第一连接走线LS1在衬底基板上的正投影覆盖第一转接电极TS1(沿第一方向Y1延伸的部分)与第二转接电极TS2(沿第一方向Y1延伸的部分)在衬底基板上的正投影，以使得第一转接电极TS1遮挡第一连接走线LS1和第二转接电极TS2，从而减少了连接走线的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生。
例如，如图4A所示，第一连接走线LS1沿第二方向X1的截面的宽度W1的取值范围，例如约为5-6微米，宽度W1的取值，例如约为5.55微米。第一转接电极TS1沿第二方向X1的截面的宽度W2的取值范围，例如约为2-3微米，宽度W2的取值，例如约为2.5微米。第二转接电极TS2沿第二方向X1的截面的宽度W3的取值范围，例如约为2-3微米，宽度W3的取值，例如约为2.5微米。 第一转接电极TS1与第二转接电极TS2沿第二方向X1上的间隙的宽度W4的取值范围，例如约为0.2-1.5微米，宽度W3的取值，例如约为0.55微米。
需要说明的是，本公开实施例中，“约”字表示，数值范围或者数值的取值可以在例如±5％，又例如±10％范围内波动。
例如，图3A中的截线C3-C4穿过第一信号线DATA1、第一过孔GH1以及第一转接电极TS1，图3A中的截线C5-C6穿过第一信号线DATA1、第二过孔GH2以及第二转接电极TS2。分别与第一转接电极TS1以及第二转接电极TS2连接的两条第一信号线DATA1位于属于第一像素单元组P0的两个第一像素单元P1。如图4B以及图4C所示，第一信号线DATA1位于第三绝缘层143远离衬底基板100的一侧。第一信号线DATA1所在的膜层与第一转接电极TS1以及第二转接电极TS2所在膜层都不相同。例如，如图5C所示，第一信号线DATA1位于第三导电层SD1。
如图4B所示，第一过孔GH1为贯穿第三绝缘层143的过孔，第一信号线DATA1通过第一过孔GH1与第一转接电极TS1连接。
如图4C所示，第二过孔GH2为贯穿第三绝缘层143以及第二绝缘层142的过孔，第一信号线DATA1通过第二过孔GH2与第二转接电极TS2连接。
例如，图21为本公开至少一实施例提供的一种显示基板中第一显示区的截面示意图。如图2所示，第一像素单元组P0的两个第一像素单元P0排布为沿第一方向的Y1至少一行，也就是说在同一行中，第一像素单元组P0包括两个第一像素单元P0。如图21所示，第一像素单元组P0的每个第一像素单元P1包括第一像素驱动电路12以及第一发光器件11，第一像素驱动电路12与第一发光器件11连接以及驱动第一发光器件11发光。第一像素驱动电路12包括存储电容13，存储电容13包括第一极板CE1和与第一极板CE1重叠(例如部分重叠)设置的第二极板CE2。第一极板CE1位于第二绝缘层142远离衬底基板100的一侧。第二极板CE2位于第一绝缘层141远离衬底基板100的一侧。例如，如图5B所示，第二极板CE2位于第二导电层GA2。
例如，图20A为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的平面布局示意图。如图2以及图20A所示，与每个第一像素单元P0一一对应连接的多条第一电源线VDD1通过贯穿第三绝缘层143的过孔VH9和过孔VH3与第一极板CE1连接。第一电源线VDD1还可以通过过孔VH9和过孔VH3的其中之一与第一极板CE1连接，本公开实施例对此不作限制。
需要说明的是，图20A中示出的第一像素驱动电路的为7T1C型(即7个晶体管和1个电容)型像素驱动电路，图20A仅作为第一像素驱动电路的一个示例，本公开的实施例对于第一像素驱动电路不作限制，例如，还可以为2T1C(即2个晶体管和1个电容)型像素驱动电路，该两个晶体管分别为数据写入晶体管和驱动晶体管，该一个电容为信号存储电容(例如图20A中的存储电容13)，该第一像素驱动电路可以根据接收的扫描信号和数据信号产生驱动发光元件发光的驱动电流，发光元件根据驱动电流的大小产生不同强度的光。该像素电路例如还可以为其他类型的像素电路，例如，可以进一步具有补偿功能、复位功能、感测功能等，由此可以包括多于2个薄膜晶体管。
例如，如图2以及图5B所示，第一像素单元组P0的位于同一行的两个第一像素单元P1的第一极板CE1相互连接且一体形成，以节省制备工艺流程，降低成本。也就是说，每一个第一像素单元P1中的第一电源线VDD1都与其所对应的第一像素单元P1的存储电容13的第一极板CE1连接，以 与第一像素单元P1连接，通过将第一像素单元组P0的位于同一行的两个第一像素单元P1的第一极板CE1相互连接，而将两个第一像素单元P1中的第一电源线VDD1连接。如前所述，当属于一个第一像素单元组P0的两个第一像素单元P1中的第一电源线VDD1连接的情况下，可以通过设置一条第一连接走线LS1将两个第一像素单元P1其中之一中的第一电源线VDD1连接，以减少走线数量。
例如，如图2以及图3B所示，显示基板1还包括第四转接电极TS4，第四转接电极TS4的部分(大部分)沿第二方向X1延伸。第四转接电极TS与第二方向X1错位且相邻设置且属于不同第一像素单元组P0的第一像素单元P1分别连接的第一电源线VDD1相连接。如图2中所示的，多个第一像素单元组P0(图中示出4个第一像素单元组P0)，排布为图1B所示的形式。也即，相邻的两列的多个第一像素单元组P0错位排布在不同行，以在第一像素单元组P0留出更多的间隙，从而允许来自显示基板1的第一侧S1的光透过。
例如，如图2以及图5C所示，第四转接电极TS4的两端分别与相邻设置且属于不同第一像素单元组P0的两个第一像素单元P1的第一极板CE1连接，以将位于不同第一像素单元组P1中的第一电源线VDD1连接。由于相邻设置且属于不同第一像素单元组P0的两个第一像素单元P1是错位的，没有位于沿第二方向X1的一行中，所以第四转接电极TS4先沿第一方向Y1延伸，然后再沿第二方向X1延伸，最后再沿第一方向Y1延伸，也即第四转接电极TS4包括沿第一方向Y1延伸的部分。第四转接电极TS4的大部分沿第二方向X1延伸。
例如，图3B中的截线C7-C8穿过第一极板CE1的部分、第三过孔GH3以及第四转接电极TS4。图4D为图3B中沿线C7-C8的截面示意图。如图4C所示，第四转接电极TS4位于第三绝缘层143远离衬底基板100的一侧，第三过孔GH3为贯穿第三绝缘层143的过孔。第四转接电极TS4通过第三过孔143，与第一像素单元P1的第一极板CE1连接。
例如，如图3B所示，第四转接电极TS4的宽度W5(例如垂直于第四转接电极TS4的走线方向)的取值范围，例如约为2-3微米，宽度W5的取值，例如约为2.5微米。
例如，图5D为图2所示的第一显示区的子像素排布示意图；如图5D所所示，第一像素单元组P0的两个第一像素单元P1可以分别包括红色子像素(R)和绿色子像素(G)或蓝色子像素(B)和绿色子像素(G)。例如，如图中所示的，第一列中在第一行的第一像素单元组P0包括红色子像素(R)和绿色子像素(G1)，也即，第一像素单元组P0的左侧的第一像素单元P1的发光器件11发红色光，第一像素单元组P0的右侧的第一像素单元P1的发光器件11发绿色光。需要说明的是，这里将图中的第一像素单元组P0看成一个整体进行划分行与列，也即排布在第一列的第一像素单元组P0中包括两行第一像素单元组P0，排布在第二列的第一像素单元组P0中包括两行第一像素单元组P0。第一列中在第二行的第一像素单元组P0包括红色子像素(R)和绿色子像素(G1)，第二列中在第一行的第一像素单元组P0包括蓝色子像素(B)和绿色子像素(G2)，第二列中在第二行的第一像素单元组P0包括蓝色色子像素(B)和绿色子像素(G2)。在第二方向X1上相邻的第一像素单元组P0共用红色子像素(R)和蓝色子像素(B)，也就是说，第一列中在第一行的第一像素单元组P0与第二列中在第一行的第一像素单元组P0共用红色子像素(R)和蓝色子像素(B)，第一列中在第二行的第一像素单元组P0与第二列中在第二行的第一像素单元组P0共用红色子像素(R)和蓝色子像素(B)，以实现画面的显示。可以根据实际显示需要选择第一像素单元组P0的第一像素单元P1的发光颜色， 本公开实施例不以此为限。
在本公开的另一实施例中，例如，图6为本公开至少另一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图。图7A为图6中A11区的放大图。图7B为图6中A12区的放大图。图9A-图9C为图6所示的第一显示区中走线的各层的平面示意图。图9A为图6所示的第一显示区中走线的位于第一导电层GA11的平面示意图。图9B为图6所示的第一显示区中走线的位于第二导电层GA12的平面示意图。图9C为图6所示的第一显示区中走线的位于第三导电层SD11的平面示意图。
例如，如图6以及图9C所示，第一显示区10包括多个第一像素单元组P10、多条第一信号线DATA1以及多条第一电源线VDD1。多个第一像素单元组P10排布为多行多列，即按照图1C所示的排布方式。第一像素单元组P10包括沿第一方向X1相邻排列的三个第一像素单元P11(也即排布为一行)。多条第一信号线DATA1以及多条第一电源线VDD1沿第一方向Y1延伸。多条第一信号线DATA1的每个与多个第一像素单元组P10的第一像素单元P11一一对应并连接。多条第一电源线VDD1的每个与多个第一像素单元组P10的第一像素单元P11一一对应并连接。也就是说，每个第一像素单元P11中分别连接一条第一信号线DATA1和一条第一电源线VDD1。第一信号线DATA1配置为给第一像素单元P11提供第一显示信号。第一电源线VDD1配置为给多个第一像素单元P11提供第一电源电压。
例如，如图9C所示，位于同一个第一像素单元P11中的第一电源线VDD1和第一信号线DATA1并列设置。同一个第一像素单元组P0中的左侧的第一信号线DATA1的下部(用于连接转接电极的部分)向靠近位于中间的第一电源线VDD1(用于与连接走线连接)的方向弯折。同一个第一像素单元组P10中的右侧的第一信号线DATA1的下部(用于连接转接电极的部分)向靠近位于中间的第一电源线VDD1(用于与连接走线连接)的方向弯折。在图9C中，位于第二行的第一像素单元组P10中的右侧的第一信号线DATA1的上部(用于连接转接电极的部分)向靠近位于中间的第一电源线VDD1(用于与连接走线连接)的方向弯折。
例如，显示基板1还包括至少一条连接走线，连接走线的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接。如图6、图7A以及图9C所示，显示基板1还包括多条连接走线(例如多条第一连接走线LS11)，多条连接走线的每条沿第一方向Y1延伸，并与第一方向Y1上相邻的第一像素单元组P10分别连接的第一电源线VDD1相连接。也即，第一方向Y1上相邻的第一像素单元组P10的两个相对应的第一像素单元P11中的第一电源线VDD1，与连接走线(例如第一连接走线LS11)连接。例如，与第一方向Y1上相邻的第一像素单元组P10的连接第一电源线VDD1通过一条连接走线(例如第一连接走线LS11)连接。也即，第一像素单元组P10的三个第一像素单元P11的其中之一中的第一电源线VDD1与连接走线(例如第一连接走线LS11)连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，显示基板1还包括至少一条转接电极，转接电极的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接。如图6以及图7A所示，显示基板1还包括多条转接电极，例如转接电极包括第一转接电极TS11、第二转接电极TS12以及第三转接电极TS3。多条转接电极的每条的主体部分(也即转接电极的大部分)沿第一方向Y1延伸，并分别与第一方向Y1上相邻的第一像素单元组P10分别连接的第一信号线DATA1相连接。也即，第一方向Y1 上相邻的第一像素单元组P10的两个相对应的第一像素单元P11中的第一信号线DATA1，与多条转接电极的其中之一(第一转接电极TS11、第二转接电极TS12或第三转接电极TS3)连接。例如，与第一方向Y1上相邻的两个第一像素单元P11连接的第一信号线DATA1通过一条转接电极(第一转接电极TS11、第二转接电极TS12或第三转接电极TS3)连接。多条转接电极一一对应连接在第一方向Y1上相邻且属于不同第一像素单元组P10的多个第一像素单元P11。也即，第一像素单元组P10的三个第一像素单元P1的其中一个(例如位于一个像素单元P10的靠近左侧)中的第一信号线DATA1与一条转接电极(例如第一转接电极TS11)连接。第一像素单元组P10的三个第一像素单元P11的其中另一个(例如位于一个像素单元P10的靠近中间)中的第一信号线DATA1与一条转接电极(例如第三转接电极TS3)连接。第一像素单元组P10的三个第一像素单元P1的其中再一个(例如位于一个像素单元P10的靠近右侧)中的第一信号线DATA1与一条转接电极(例如第二转接电极TS12)连接。
例如，如图6以及图7A所示，多条连接走线(例如第一连接走线LS11)位于多条转接电极(例如第一转接电极TS11或第二转接电极TS12)远离衬底基板的一侧。如图7A所示的，连接走线(例如第一连接走线LS11)在衬底基板100上的正投影与转接电极(例如第一转接电极TS11或第二转接电极TS12)在衬底基板100上的正投影部分重叠，例如，转接电极(例如第一转接电极TS11)沿第一方向Y1延伸的部分在衬底基板100上的正投影与连接走线(例如第一连接走线LS11)衬底基板100上的正投影重叠。例如，转接电极(例如第一转接电极TS11)沿第一方向Y1延伸的部分在衬底基板100上的正投影位于连接走线(例如第一连接走线LS11)在衬底基板100上的正投影中，使连接走线与转接电极重叠并遮挡转接电极，减少了走线的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生，进而允许在第一显示区中且在该显示基板1的第二侧S2设置例如传感器以进行感测(例如成像)，且改善该传感器的感测效果(成像质量)。
例如，至少一条连接走线包括第一连接走线。如图6、图7A以及图9C所示，第一连接走线LS11沿第一方向Y1延伸，第一连接走线LS11与在第一方向Y1上相邻的且属于不同第一像素单元组P10的第一像素单元P11分别连接的第一电源线VDD1相连接。第一连接走线LS11与其所连接的第一电源线VDD1都基本位于第一方向Y1上。如图中所示的，在第一方向Y1上相邻的第一像素单元组P10之间存在间隙，以允许来自显示基板1的第一侧S1的光透过。在第一方向Y1上相邻的第一像素单元组P10的三个第一像素单元P1的其中之一(例如位于中间的一个像素单元P1)与第一连接走线LS11连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，第一连接走线与第一电源线同层设置且一体形成。图8为图7A中沿线C11-C12的截面示意图。线C11-C12沿第二方向X1穿过第一转接电极TS11、第一连接走线LS11、第三转接电极TS3以及第二转接电极TS12。如图8所示，第一连接走线LS11位于第三绝缘层143远离衬底基板100的一侧，第一电源线VDD1与第一连接走线LS11同层设置且通过同一构图工艺一体形成。例如，如图9C所示，第一连接走线LS11以及第一电源线VDD1位于第三导电层SD11。
例如，如图7A、图9A以及图9B所示，多条转接电极包括第一转接电极TS11、第二转接电极TS12以及第三转接电极TS3。第一转接电极TS11、第二转接电极TS12以及第三转接电极TS3的沿第一方向Y1延伸的部分并列设置。第三转接电极TS3位于第一转接电极TS11以及第二转接电极TS12 之间。第一像素单元组P10的三个第一像素单元P11排布为沿第二方向Y1并列的三列。第一转接电极TS11、第三转接电极TS3以及第二转接电极TS12与在第一方向Y1上相邻的且属于不同第一像素单元组P10的第一像素单元P11分别连接的第一信号线DATA1相连接。也即，位于三列的属于同一个第一像素单元组P10的三个第一像素单元P11分别与第一转接电极TS11、第三转接电极TS3以及第二转接电极TS12连接。第三转接电极TS3沿第一方向Y1延伸。第一转接电极TS11以及第二转接电极TS12先向靠近第一连接走线LS11的沿第二方向X1延伸，然后再沿第一方向Y1延伸，再沿第二方向X1延伸，以将在第一方向Y1上相邻的属于不同第一像素单元组P10的第一像素单元P11的第一信号线DATA1连接。第一转接电极TS11以及第二转接电极TS12的沿第二方向X1延伸的部分较短，并且第一转接电极TS11以及第二转接电极TS12的主体部分沿第一方向Y1延伸。第三转接电极TS3沿第一方向Y1延伸，并与其连接的第一信号线DATA1基本位于一条直线上(也即都位于第一方向Y1上)。第三转接电极TS3可以和第三转接电极TS3连接的第一信号线DATA1一体形成。
例如，如图9A所示，第二转接电极TS12呈向图中右侧(远离第一连接走线LS11)开口的类似“凹”字型或“]”型。而如图9B所示，第一转接电极TS11呈向图中左侧(远离第一连接走线LS11)开口的类似“凹”字型或“[”型。第二转接电极TS12以及第二转接电极TS11的方向相反，都是都汇聚到第一连接走线LS11所在的位置，以与第一连接走线LS11重叠。如图9C所示，第三转接电极TS3位于第三导电层SD11，与第一信号线DATA1同层设置。第三转接电极TS3与其连接的第一信号线DATA1都位于第一方向Y1。
例如，相对于衬底基板，多条转接电极分别所在的膜层不同。如图8所示，相对于衬底基板100，第一转接电极TS11、第二转接电极TS12以及第三转接电极TS3所在膜层不同。第一转接电极TS11位于第二绝缘层142与第三绝缘层143之间。例如，如图9B所示，第一转接电极TS11位于第二导电层GA12。第二转接电极TS12位于第一绝缘层141与第二绝缘层142之间。例如，如图5A所示，第二转接电极TS12位于第一导电层GA11。第二绝缘层142将第一转接电极TS11以及第二转接电极TS12间隔绝缘。第一转接电极TS11以及第二转接电极TS12位于不同的膜层可以减小第一转接电极TS11以及第二转接电极TS12之间间隔的尺寸，从而减小第一转接电极TS11以及第二转接电极TS12占据的空间。
例如，如图9C所示，第三转接电极TS3位于第三导电层SD11，即第三绝缘层143远离衬底基板100的一侧，即与第一连接走线LS11同层设置，以减少布线空间。第一信号线DATA1位于第三导电层SD11，即第三绝缘层143远离衬底基板100的一侧，第一信号线DATA1所在的膜层与第一转接电极TS11以及第二转接电极TS12所在膜层都不相同，但与第三转接电极TS3所在膜层相同。第三转接电极TS3与其连接的第一信号线DATA1同层设置且一体形成。
例如，第三转接电极在衬底基板上的正投影与第一转接电极或第二转接电极在衬底基板上的正投影至少部分重叠。如图7A以及图8所示，第三转接电极TS3在衬底基板100上的正投影与第二转接电极TS12在衬底基板100上的正投影部分重叠，以减少布线空间。
例如，第一连接走线在衬底基板上的正投影与第一转接电极以及第二转接电极的至少之一在衬底基板上的正投影至少部分重叠。如图7A和图8所示，第一连接走线LS11在衬底基板100上的正投影与第一转接电极TS11(沿第一方向Y1延伸的部分)在衬底基板100上的正投影重叠。也即，第一 连接走线LS11在衬底基板100上的正投影覆盖第一转接电极TS11(沿第一方向Y1延伸的部分)在衬底基板100上的正投影，以使得第一连接走线LS11遮挡第一转接电极TS11，从而减少了连接走线的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生。
第一连接走线LS11在衬底基板100上的正投影与第二转接电极TS21(沿第一方向Y1延伸的部分)在衬底基板100上的正投影重叠部分重叠，以减少布线空间。第二转接电极TS21(沿第一方向Y1延伸的部分)在衬底基板100上的正投影与第一连接走线LS11以及第三转接电极TS3在衬底基板100上的正投影都部分重叠，也即第二转接电极TS21遮挡第一连接走线LS11以及第三转接电极TS3之间的间隙，以防止光干涉现象的产生。
例如，如图8所示，第一连接走线LS11沿第二方向X1的截面的宽度W11的取值范围，例如约为5-6微米，宽度W1的取值，例如约为5.55微米。第一转接电极TS11沿第二方向X1的截面的宽度W12的取值范围，例如约为2-3微米，宽度W12的取值，例如约为2.5微米。第二转接电极TS12沿第二方向X1的截面的宽度W13的取值范围，例如约为3-4微米，宽度W13的取值，例如约为3.5微米。第一转接电极TS1与第二转接电极TS2沿第二方向X1上的间隙的宽度W14的取值范围，例如约为2-3微米，宽度W13的取值，例如约为2.65微米。第三转接电极TS3沿第二方向X1的截面的宽度W16的取值范围，例如约为1.5-2.5微米，宽度W16的取值，例如约为2微米。第一连接走线LS11与第三转接电极TS3沿第二方向X1上的间隙的宽度W17的取值范围，例如约为2-3微米，宽度W17的取值，例如约为2.7微米。
例如，如图7A所示，第一信号线DATA1(位于图中左侧)通过第一过孔GH11与第一转接电极TS11连接。第一信号线DATA1(位于图中右侧)通过第二过孔GH12与第二转接电极TS12连接。参考图4B以及图4C，第一过孔GH11与第一过孔GH1同为贯穿第三绝缘层143的过孔，第二过孔GH12与第二过孔GH2同为贯穿第三绝缘层143以及第二绝缘层142的过孔。
例如，如图6以及图21所示，第一像素单元组P0的三个第一像素单元P10排布为沿第一方向Y1的一行，也就是说在同一行中，第一像素单元组P10包括三个第一像素单元P10。第一像素单元组P10的每个第一像素单元P1包括第一像素驱动电路12以及第一发光器件11，第一像素驱动电路12与第一发光器件11电连接以及驱动第一发光器件11发光。第一像素驱动电路12包括存储电容13，存储电容13包括第一极板CE1和与第一极板CE1重叠(例如部分重叠)设置的第二极板CE2。第一极板CE1位于第二绝缘层142远离衬底基板100的一侧。第二极板CE2位于第一绝缘层141远离衬底基板100的一侧。例如，如图9B所示，第一极板CE1位于第二导电层GA12。
例如，如图6以及图20A所示，与每个第一像素单元P10一一对应连接的多条第一电源线VDD1通过贯穿第三绝缘层143的过孔VH9和过孔VH3与第一极板CE1连接。第一电源线VDD1还可以通过过孔VH9和过孔VH3的其中之一与第一极板CE1连接。
例如，如图6、以及图9B所示，第一像素单元组P10的位于同一行的三个第一像素单元P11的第一极板CE1相互连接且一体形成，以节省制备工艺流程，降低成本。也就是说，每一个第一像素单元P11中的第一电源线VDD1都与其所对应的第一像素单元P11的存储电容13的第一极板CE1连接，以与第一像素单元P11电连接，通过将第一像素单元组P10的位于同一行的两个第一像素单元P11的第一极板CE1相互连接，而将两个第一像素单元P11中的第一电源线VDD1电连接。如前所述， 当属于一个第一像素单元组P10的三个第一像素单元P11中的第一电源线VDD1电连接的情况下，可以通过设置一条第一连接走线LS11将三个第一像素单元P11其中之一中的第一电源线VDD1连接，以减少走线数量。
例如，如图6以及图7B所示，显示基板1还包括第四转接电极TS14，第四转接电极TS14沿第二方向X1延伸。第四转接电极TS14与第二方向X1相邻设置且属于不同第一像素单元组P0的第一像素单元P1分别连接的第一电源线VDD1相电连接。如图2中所示的，多个第一像素单元组P10(图6中示出4个第一像素单元组P10)，排布为图1C所示的形式。也即，相邻的两列的多个第一像素单元组P10位于同一行，以在第一像素单元组P10之间留出更多的间隙，从而允许来自显示基板1的第一侧S1的光透过。
例如，如图6以及图9C所示，第四转接电极TS14的两端分别与相邻设置且属于不同第一像素单元组P10的两个第一像素单元P11的第一极板CE1连接，以将位于不同第一像素单元P11中的第一电源线VDD1电连接。由于相邻设置且属于不同第一像素单元组P10的两个第一像素单元P11位于沿第二方向X1的一行中，所以第四转接电极TS14沿第一方向Y1延伸。
例如，如图7B以及9B所示，第四转接电极TS14位于第二导电层GA12并与第一像素单元P11的第一极板CE1连接且可以一体形成。
例如，如图7B所示，第四转接电极TS14的宽度W15(例如垂直于第四转接电极TS14的走线方向)的取值范围，例如约为14-15微米，宽度W15的取值，例如约为14.5微米。第四转接电极TS14的宽度W15较大，从而可以将相邻设置且属于不同第一像素单元组P10的两个第一像素单元P11之间的其它走线(例如，发光控制信号线、栅极扫描信号线等)遮挡，以减少光干涉的产生。
例如，图9D为图6所示的第一显示区的子像素排布示意图。如图9D所示，第一像素单元组P10的三个第一像素单元P11可以分别包括红色子像素(R)、绿色子像素(G1)以及蓝色子像素(B)，也即，第一像素单元组P10的左侧的第一像素单元P1的发光器件11发红色光，第一像素单元组P10的中间的第一像素单元P1的发光器件11发绿色光，第一像素单元组P10的右侧的第一像素单元P1的发光器件11发蓝色光，以实现画面的显示。可以根据实际显示需要选择第一像素单元组P10的第一像素单元P11的发光颜色，本公开实施例不以此为限。
在本公开的另一实施例中，例如，图10为本公开至少再一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图。图11为图10中A21区的放大图。图13A-图13C为图10所示的第一显示区中走线的各层的平面示意图。图13A为图10所示的第一显示区中走线的位于第一导电层GA21的平面示意图。图13B为图10所示的第一显示区中走线的位于第二导电层GA22的平面示意图。图13C为图10所示的第一显示区中走线的位于第三导电层SD21的平面示意图。
例如，如图10以及图13C所示，第一显示区10包括多个第一像素单元组P20、多条第一信号线DATA1以及多条第一电源线VDD1。多个第一像素单元组P20排布为错位的多行多列，即按照图1B所示的排布方式，也即图中第一列的第一像素单元组P20与第二列的第一像素单元组P20之间相互错开。第一像素单元组P20包括沿第二方向X1以及第一方向Y1排列为两行两列的四个第一像素单元P21。多条第一信号线DATA1以及多条第一电源线VDD1沿第一方向Y1延伸。多条第一信号线DATA1的每个与多个第一像素单元组P20的第一像素单元P21一一对应并电连接。多条第一电源线VDD1 的每个与多个第一像素单元组P20的第一像素单元P21一一对应并电连接。也就是说，每个第一像素单元P21中分别连接一条第一信号线DATA1和一条第一电源线VDD1。第一信号线DATA1配置为给第一像素单元P21提供第一显示信号。第一电源线VDD1配置为给多个第一像素单元P21提供第一电源电压。
例如，在同一个第一像素单元组P20(例如图13C中位于右侧的第一像素单元组P20)中，与同一列的第一像素单元P21的连接的第一信号线DATA1相互连接且一体形成，与同一列的第一像素单元P21的连接第一电源线VDD1也相互连接且一体形成。需要说明的是图13C中位于左侧的两个第一像素单元组P20仅示出了其中两个第一像素单元P21，该左侧的两个第一像素单元组P20的完整结构与图13C中位于右侧的第一像素单元组P20相同。
例如，如图13C所示，位于同一个第一像素单元P21中的第一电源线VDD1和第一信号线DATA1并列设置。同一个第一像素单元组P20中的左侧的第一信号线DATA1的下部(用于连接转接电极的部分)向靠近位于右侧的第一电源线VDD1(用于与连接走线连接)的方向弯折。同一个第一像素单元组P20中的右侧的第一信号线DATA1的下部(用于连接转接电极的部分)向远离位于右侧的第一电源线VDD1(用于与连接走线连接)的方向弯折。同一个第一像素单元组P20中的右侧的第一电源线VDD1的下部(用于连接走线的部分)向右侧弯折(与同一个第一像素单元组P20中的右侧的第一信号线DATA1的下部的弯折方向相同)。在图13C中，同一个的第一像素单元组P20中的右侧的第一信号线DATA1的上部(用于转接电极的部分)向右侧弯折。
例如，显示基板1还包括至少一条连接走线，连接走线的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接。如图10、图11以及图13C所示，显示基板1还包括多条连接走线(例如多条第一连接走线LS21)，多条连接走线的每条包括沿第一方向Y1延伸的部分以及沿第二方向X1延伸的部分，并与第一方向Y1上相邻的第一像素单元组P20分别连接的第一电源线VDD1相连接。也即，第一方向Y1上相邻的第一像素单元组P20的两个相对应的第一像素单元P21中的第一电源线VDD1，与连接走线(例如第一连接走线LS21)连接。例如，与第一方向Y1上相邻的第一像素单元组P20的连接第一电源线VDD1通过一条连接走线(例如第一连接走线LS21)连接。也即，第一像素单元组P20的两个第一像素单元P21的其中之一中的第一电源线VDD1与连接走线(例如第一连接走线LS21)连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，显示基板1还包括至少一条转接电极，转接电极的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接。如图10以及图11所示，显示基板1还包括多条转接电极，例如转接电极包括第一转接电极TS21以及第二转接电极TS22。多条转接电极的每条的主体部分(也即转接电极的大部分)沿第一方向Y1延伸，并分别与第一方向Y1上相邻的第一像素单元组P20分别连接的第一信号线DATA1相连接。也即，第一方向Y1上相邻的第一像素单元组P20的两个相对应的第一像素单元P21中的第一信号线DATA1，与多条转接电极的其中之一(第一转接电极TS21或第二转接电极TS22)连接。例如，与第一方向Y1上相邻的两个第一像素单元P21连接的第一信号线DATA1通过一条转接电极(第一转接电极TS21或第二转接电极TS22)连接。多条转接电极一一对应连接在第一方向Y1上相邻且属于不同第一像素单元组P20的多个第一像 素单元P21。也即，第一像素单元组P20的位于同一行的两个第一像素单元P21的其中一个(例如位于一个像素单元P20的靠近左侧)中的第一信号线DATA1与一条转接电极(例如第一转接电极TS21)连接。第一像素单元组P20的位于同一行的两个第一像素单元P21的其中另一个(例如位于一个像素单元P20的靠近右侧)中的第一信号线DATA1与一条转接电极(例如第二转接电极TS22)连接。
例如，多条连接走线(例如第一连接走线LS21)位于多条转接电极(例如第一转接电极TS21或第二转接电极TS22)远离衬底基板的一侧。如图11所示的，连接走线(例如第一连接走线LS21)在衬底基板100上的正投影与转接电极(例如第一转接电极TS21以及第二转接电极TS22)在衬底基板100上的正投影重叠，例如，转接电极(例如第一转接电极TS21以及第二转接电极TS22)在衬底基板100上的正投影与连接走线(例如第一连接走线LS21)衬底基板100上的正投影重叠。例如，转接电极(例如第一转接电极TS21以及第二转接电极TS22)沿第一方向Y1延伸的部分在衬底基板100上的正投影位于连接走线(例如第一连接走线LS21)在衬底基板上的正投影中，使连接走线与转接电极重叠并遮挡转接电极，减少了转接电极的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生，进而允许在第一显示区中且在该显示基板1的第二侧S2设置例如传感器以进行感测(例如成像)，且改善该传感器的感测效果(成像质量)。
例如，如图10以及图13C所示，在第一方向Y1以及与第二方向X1上相邻的第一像素单元组P20之间具有允许光透射的间隙。连接走线(例如第一连接走线LS21)以及转接电极(例如第一转接电极TS21以及第二转接电极TS22)的部分沿第二方向X1延伸并绕过允许光透射的间隙。如图10中所示的，连接走线(例如第一连接走线LS21)以及转接电极(例如第一转接电极TS21以及第二转接电极TS22)先向沿第二方向X1向靠近右侧第一像素单元组P20的方向延伸，再沿第一方向Y1延伸，再向远离右侧第一像素单元组P20的方向延伸，从而使连接走线(例如第一连接走线LS21)以及转接电极(例如第一转接电极TS21以及第二转接电极TS22)连接在第一方向Y1上相邻的两个第一像素单元组P20。也就是说连接走线(例如第一连接走线LS21)以及转接电极(例如第一转接电极TS21以及第二转接电极TS22)呈“三段折线走线”，以留出第一像素单元组P20之间的较大的间隙，从而防止光的干涉。
例如，至少一条连接走线包括第一连接走线。如图13C所示，第一连接走线LS21为弯折走线，且包括第一部分LSP1、第二部分LSP2以及第三部分LSP3。第一部分LSP1、第二部分LSP2沿第二方向X1延伸，第三部分LSP3沿第一方向Y1延伸，第一部分LSP1的第一端LSP11和第二部分LSP2的第一端LSP21分别与第三部分LSP3的两端连接，以使第一连接走线LS21设置为三段组合的弯折走线。第一部分LSP1的第二端LSP12和第二部分LSP2的第二端LSP22分别与在第一方向Y1上的相邻的第一像素单元P21分别连接的第一电源线VDD1相连接。也即，第一连接走线LS21与在第一方向Y1上相邻的且属于不同第一像素单元组P20的第一像素单元P21分别连接的第一电源线VDD1相连接。如图中所示的，在第一方向Y1上相邻的第一像素单元组P20之间存在间隙，以允许来自显示基板1的第一侧S1的光透过。在第一方向Y1上相邻的第一像素单元组P20的两个第一像素单元P21的其中之一(例如位于中间的一个像素单元P31)与第一连接走线LS21连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，第一连接走线与第一电源线同层设置且一体形成。图12为图11中沿线C21-C22的截面示 意图。线C11-C12沿第二方向Y1穿过第一转接电极TS21、第一连接走线LS21以及第二转接电极TS22。如图12所示，第一连接走线LS21位于第三绝缘层143远离衬底基板100的一侧，第一电源线VDD1与第一连接走线LS21同层设置且通过同一构图工艺一体形成。例如，如图13C所示，第一连接走线LS21以及第一电源线VDD1位于第三导电层SD21。
例如，如图11、图13A以及图13B所示，多条转接电极包括第一转接电极TS21以及第二转接电极TS12。第一转接电极TS21以及第二转接电极TS22的形状与第一连接走线LS21的形状相同，也即为由三段走线连接形成的弯折走线。第一转接电极TS21以及第二转接电极TS12并列设置，且先向沿第二方向X1向靠近右侧第一像素单元组P20的方向延伸，再沿第一方向Y1延伸，再向远离右侧第一像素单元组P20的方向延伸，以留出第一像素单元组P20之间的较大的间隙，从而防止光的干涉。
例如，第一转接电极和第二转接电极在衬底基板上的正投影与第一连接走线的第一部分、第二部分以及第三部分的至少之一在衬底基板上的正投影重叠。如图11以及图12所示，第一转接电极TS21以及第二转接电极TS22在衬底基板上的正投影与第一连接走线LS21的第一部分LSP1、第二部分LSP2以及第三部分LSP3在衬底基板上的正投影都重叠(例如部分重叠)。例如，第一转接电极TS21在衬底基板100上的正投影位于第一连接走线LS21的第一部分LSP1、第二部分LSP2以及第三部分LSP3在衬底基板100上的正投影中，也就是说，第一转接电极TS2完全被第一连接走线LS21遮挡。第二转接电极TS22在衬底基板100上的正投影没有完全位于被第一连接走线LS21的第一部分LSP1、第二部分LSP2以及第三部分LSP3在衬底基板上的正投影重叠中，第二转接电极TS22的沿第二方向X1走线的部分在衬底基板100上的正投影与第一连接走线LS21的第一部分LSP1在衬底基板100上的正投影部分重叠。例如，可以通过增加第一连接走线LS21的宽度的方式，使得第一连接走线LS21完全遮挡第二转接电极TS22的沿第二方向X1走线的部分。在上述情况下，可以减小第一转接电极TS11以及第二转接电极TS12占据的空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生。
例如，如图13A以及图13B所示，第一转接电极TS21以及第二转接电极TS22与在第一方向Y1上相邻的且属于不同第一像素单元组P20的第一像素单元P21分别连接的第一信号线DATA1相连接。也即，位于两列的属于同一个第一像素单元组P20的两个第一像素单元P21分别与第一转接电极TS2以及第二转接电极TS22连接。第一转接电极TS11以及第二转接电极TS12的沿第一方向Y1延伸的部分靠近图中右侧的第一像素单元组P20，以减少光的干涉。
例如，如图13A所示，第二转接电极TS22呈向图中右侧(远离第一连接走线LS21)开口的类似“凹”字型。而如图13B所示，第一转接电极TS21呈向图中左侧(远离第一连接走线LS21)开口的类似“凹”字型。第二转接电极TS22以及第二转接电极TS21的方向相反，都是都汇聚到第一连接走线LS21所在的位置，以与第一连接走线LS21重叠。
例如，相对于衬底基板，多条转接电极分别所在的膜层不同。如图12所示，相对于衬底基板100，第一转接电极TS21以及第二转接电极TS22所在膜层不同。第一转接电极TS21位于第二绝缘层142与第三绝缘层143之间。例如，如图13B所示，第一转接电极TS21位于第二导电层GA22。第二转接电极TS22位于第一绝缘层141与第二绝缘层142之间。例如，如图13A所示，第二转接电极TS22 位于第一导电层GA21。第二绝缘层142将第一转接电极TS21以及第二转接电极TS22间隔绝缘。第一转接电极TS21以及第二转接电极TS22位于不同的膜层可以减小第一转接电极TS21以及第二转接电极TS22之间间隔的尺寸，从而减小第一转接电极TS21以及第二转接电极TS22占据的空间。
例如，如图12所示，第一连接走线LS21沿第二方向X1的截面的宽度W21的取值范围，例如约为4.5-5.5微米，宽度W21的取值，例如约为5微米。第一转接电极TS21沿第二方向Y1的截面的宽度W22的取值范围，例如约为2-3微米，宽度W22的取值，例如约为2.5微米。第二转接电极TS22沿第二方向Y1的截面的宽度W23的取值范围，例如约为2-3微米，宽度W23的取值，例如约为2.5微米。第一转接电极TS21与第二转接电极TS22沿第二方向Y1上的间隙的宽度W24的取值范围，例如约为1-2微米，宽度W3的取值，例如约为0.8微米。
例如，如图11所示，第一信号线DATA1(位于图中左侧)通过第一过孔GH21与第一转接电极TS21连接。第一信号线DATA1(位于图中右侧)通过第二过孔GH22与第二转接电极TS22连接。参考图3A、图4B以及图4C，第一过孔GH21与第一过孔GH1同为贯穿第三绝缘层143的过孔，第二过孔GH22与第二过孔GH2同为贯穿第三绝缘层143以及第二绝缘层142的过孔。
例如，如图10以及图21所示，第一像素单元组P20的4个第一像素单元P20排布为两行两列，也就是说在同一行中，第一像素单元组P10包括两个第一像素单元P20。第一像素单元组P20的每个第一像素单元P21包括第一像素驱动电路12以及第一发光器件11，第一像素驱动电路12与第一发光器件11电连接以及驱动第一发光器件11发光。第一像素驱动电路12包括存储电容13，存储电容13包括第一极板CE1和与第一极板CE1重叠(例如部分重叠)设置的第二极板CE2。第一极板CE1位于第二绝缘层142远离衬底基板100的一侧。第二极板CE2位于第一绝缘层141远离衬底基板100的一侧。例如，如图13B所示，第一极板CE1位于第二导电层GA22。
例如，如图10以及图20A所示，与每个第一像素单元P20一一对应连接的多条第一电源线VDD1通过贯穿第三绝缘层143的过孔VH9和过孔VH3与第一极板CE1连接。第一电源线VDD1还可以通过过孔VH9和过孔VH3的其中之一与第一极板CE1连接。
例如，如图10、以及图13B所示，第一像素单元组P20的位于同一行的两个第一像素单元P11的第一极板CE11相互连接且一体形成，以节省制备工艺流程，降低成本。也就是说，每一个第一像素单元P21中的第一电源线VDD1都与其所对应的第一像素单元P11的存储电容13的第一极板CE1连接，以与第一像素单元P21电连接，通过将第一像素单元组P20的位于同一行的两个第一像素单元P11的第一极板CE1相互连接，而将两个第一像素单元P21中的第一电源线VDD1电连接。而位于不同行的第一电源线VDD1相互对应连接且一体成型。如前所述，当属于一个第一像素单元组P20的同一行的两个第一像素单元P21中的第一电源线VDD1电连接的情况下，可以通过设置一条第一连接走线LS21将两个第一像素单元P21其中之一中的第一电源线VDD1连接，以减少走线数量。
例如，如图10以及图13B所示，显示基板1还包括第四转接电极TS24，第四转接电极TS24沿第二方向X1延伸。第四转接电极TS24与第二方向X1相邻设置且属于不同第一像素单元组P20的第一像素单元P21分别连接的第一电源线VDD1相电连接。如图10中所示的，多个第一像素单元组P20(图6中示出3个第一像素单元组P20)，排布为图1B所示的形式。也即，相邻的两列的多个第一像素单元组P10位于不同行，以在第一像素单元组P20之间留出更多的间隙，从而允许来自显示基板1 的第一侧S1的光透过。
例如，如图10以及图13B所示，第四转接电极TS24的两端分别与相邻设置且属于不同第一像素单元组P20的两个第一像素单元P21的第一极板CE1连接，以将位于不同第一像素单元P21中的第一电源线VDD1电连接。由于相邻设置且属于不同第一像素单元组P20的两个第一像素单元P21位于沿第二方向X1的不同一行中，所以第四转接电极TS24包括沿第一方向Y1延伸的部分。
例如，如图13B所示，第四转接电极TS24位于第二导电层GA22并与第一像素单元P21的第一极板CE1连接且可以一体形成。
例如，如图13B所示，当第一像素单元组P20的4个第一像素单元P20排布为两行两列时，第一像素单元组P20的位于第一行的第一像素单元P21以及位于第二行的第一像素单元P21与不同的第四转接电极TS24连接。以图13B中示出的右侧的第一像素单元组P20(如图示出4个第一像素单元P21)为例，第一像素单元组P20的第一行的第一列(即左侧)第一像素单元P21的第一极板CE1与左上方的第四转接电极TS24连接，左上方的第四转接电极TS24还与位于左上方的第一像素单元组P20的第二行的第二列(即右侧)第一像素单元P21的第一极板CE1连接。第一像素单元组P20的第一行的第二列(即右侧)第一像素单元P21的第一极板CE1与右上方的第四转接电极TS24连接，右上方的第四转接电极TS24还与位于右上方的第一像素单元组P20的第二行的第一列(即左侧)第一像素单元P21的第一极板CE1(图中未示出)连接。第一像素单元组P20的第二行的第一列(即左侧)第一像素单元P21的第一极板CE1与左下方的第四转接电极TS24连接，左下方的第四转接电极TS24还与位于左下方的第一像素单元组P20的第一行的第二列(即右侧)第一像素单元P21的第一极板CE1连接。第一像素单元组P20的第二行的第二列(即右侧)第一像素单元P21的第一极板CE1与右下方的第四转接电极TS24连接，右上方的第四转接电极TS24还与位于右下方的第一像素单元组P20的第一行的第一列(即左侧)第一像素单元P21的第一极板CE1(图中未示出)连接。
例如，如图11所示，第四转接电极TS24的宽度W25(例如垂直于第四转接电极TS24的走线方向)的取值范围，例如约为2-3微米，宽度W15的取值，例如约为2.5微米。
例如，图13D为图10所示的第一显示区的子像素排布示意图。如图13D所示，第一像素单元组P20的排布为两行两列的四个第一像素单元P21可以分别包括红色子像素(R)、蓝色子像素(B)、绿色子像素(G1)以及绿色子像素(G2)(也就是两个绿色子像素)，即，在一个第一像素单元组P20(以图中右侧的4个第一像素单元P21为例)中，位于第一行的两个第一像素单元P21包括蓝色色子像素(B)以及绿色子像素(G2)，位于第二行的两个第一像素单元P21包括红色子像素(R)和绿色子像素(G1)，也即，在一个第一像素单元组P20(以图中右侧的4个第一像素单元P21为例)中，第一行中的第一列(也即左上角)的第一像素单元P21的发光器件11发蓝色光，第一行中的第二列(也即右上角)的第一像素单元P21的发光器件11发绿色光，第二行中的第一列(也即左下角)的第一像素单元P21的发光器件11发红色光，第二行中的第二列(也即右下角)的第一像素单元P21的发光器件11发绿色光，以实现画面的显示。可以根据实际显示需要选择第一像素单元组P20的第一像素单元P21的发光颜色，本公开实施例不以此为限。
在本公开的另一实施例中，例如，图14为本公开至少再一实施例提供的一种显示基板的第一显示区中走线的平面布局示意图。图15为图14中A31区的放大图。图17A-图17C为图14所示的第一 显示区中走线的各层的平面示意图。图17A为图14所示的第一显示区中走线的位于第一导电层GA31的平面示意图。图17B为图14所示的第一显示区中走线的位于第二导电层GA32的平面示意图。图17C为图14所示的第一显示区中走线的位于第三导电层SD31的平面示意图。
例如，如图14以及图17C所示，第一显示区10包括多个第一像素单元组P30、多条第一信号线DATA1以及多条第一电源线VDD1。多个第一像素单元组P30排布为错位的多行多列，即按照图1B所示的排布方式，也即图中第一列的第一像素单元组P30与第二列的第一像素单元组P30之间相互错开(也即位于相邻的两行)。第一像素单元组P30包括沿第二方向X1以及第一方向Y1排列为两行两列的四个第一像素单元P31。多条第一信号线DATA1以及多条第一电源线VDD1沿第一方向Y1延伸。多条第一信号线DATA1的每个与多个第一像素单元组P30的第一像素单元P31一一对应并电连接。多条第一电源线VDD1的每个与多个第一像素单元组P30的第一像素单元P31一一对应并电连接。也就是说，每个第一像素单元P31中分别连接一条第一信号线DATA1和一条第一电源线VDD1。第一信号线DATA1配置为给第一像素单元P31提供第一显示信号。第一电源线VDD1配置为给多个第一像素单元P31提供第一电源电压。
例如，在同一个第一像素单元组P30中，与同一列的第一像素单元P31的连接的第一信号线DATA1相互连接且一体形成，与同一列的第一像素单元P31的连接第一电源线VDD1也相互连接且一体形成。需要说明的是图14中仅示出了两个第一像素单元组P30。
例如，如图17C所示，位于同一个第一像素单元P31中的第一电源线VDD1和第一信号线DATA1并列设置。同一个第一像素单元组P30中的左侧的第一信号线DATA1的下部(用于连接转接电极的部分)向右侧弯折(例如，向靠近与连接走线连接的第一电源线VDD1弯折)。
例如，显示基板1还包括至少一条连接走线，连接走线的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接。如图14、图15以及图17C所示，显示基板1还包括多条连接走线(例如多条第一连接走线LS31)，多条连接走线的每条沿第一方向Y1延伸，并与第一方向Y1上相邻的第一像素单元组P30分别连接的第一电源线VDD1相连接。也即，第一方向Y1上相邻的第一像素单元组P30的两个相对应的第一像素单元P31中的第一电源线VDD1，与连接走线(例如第一连接走线LS31)连接。例如，与第一方向Y1上相邻的第一像素单元组P30的连接第一电源线VDD1通过一条连接走线(例如第一连接走线LS31)连接。也即，第一像素单元组P30的两个第一像素单元P31的其中之一中的第一电源线VDD1与连接走线(例如第一连接走线LS31)连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，显示基板1还包括至少一条转接电极，转接电极的至少部分沿第一方向延伸，并与在第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接。如图14以及图15所示，显示基板1还包括多条转接电极，例如转接电极包括第一转接电极TS31以及第二转接电极TS32。多条转接电极的每条的主体部分(也即转接电极的大部分)沿第一方向Y1延伸，并分别与第一方向Y1上相邻的第一像素单元组P30分别连接的第一信号线DATA1相连接。也即，第一方向Y1上相邻的第一像素单元组P30的两个相对应的第一像素单元P31中的第一信号线DATA1，与多条转接电极的其中之一(第一转接电极TS31或第二转接电极TS32)连接。例如，与第一方向Y1上相邻的两个第一像素单元P31连接的第一信号线DATA1通过一条转接电极(第一转接电极TS31或第二转接电极TS32)连 接。多条转接电极一一对应连接在第一方向Y1上相邻且属于不同第一像素单元组P30的多个第一像素单元P31。也即，第一像素单元组P30的位于同一行的两个第一像素单元P31的其中一个(例如位于一个像素单元P30的靠近左侧)中的第一信号线DATA1与一条转接电极(例如第一转接电极TS31)连接。第一像素单元组P30的位于同一行的两个第一像素单元P31的其中另一个(例如位于一个像素单元P30的靠近右侧)中的第一信号线DATA1与一条转接电极(例如第二转接电极TS32)连接。
例如，如图14以及图15所示，多条连接走线(例如第一连接走线LS31)位于多条转接电极(例如第一转接电极TS31或第二转接电极TS32)远离衬底基板的一侧。如图15所示的，连接走线(例如第一连接走线LS31)在衬底基板100上的正投影与转接电极(例如第一转接电极TS31以及第二转接电极TS32)在衬底基板100上的正投影重叠，例如，转接电极(例如第一转接电极TS31以及第二转接电极TS32)在衬底基板100上的正投影与连接走线(例如第一连接走线LS31)衬底基板100上的正投影重叠。例如，转接电极(例如第一转接电极TS31以及第二转接电极TS32)沿第一方向Y1延伸的部分在衬底基板100上的正投影位于连接走线(例如第一连接走线LS31)在衬底基板100上的正投影中，使连接走线与转接电极重叠并遮挡转接电极，减少了转接电极的布线空间，提高了第一显示区的开口率和透光率，还可以减小不同走线之间的光干涉现象的产生，进而允许在第一显示区中且在该显示基板1的第二侧S2设置例如传感器以进行感测(例如成像)，且改善该传感器的感测效果(成像质量)。
例如，至少一条连接走线包括第一连接走线。如图17C所示，第一连接走线LS31分别与在第一方向Y1上的相邻的第一像素单元P31(也即在第一方向Y1上的相邻的第一像素单元组P30的位于第二列(也即右侧)的第一像素单元P31)分别连接的第一电源线VDD1相连接。也即，第一连接走线LS31与在第一方向Y1上相邻的且属于不同第一像素单元组P30的第一像素单元P31分别连接的第一电源线VDD1相连接。如图中所示的，在第一方向Y1上相邻的第一像素单元组P30之间存在间隙，以允许来自显示基板1的第一侧S1的光透过。在第一方向Y1上相邻的第一像素单元组P30的两个第一像素单元P31的其中之一(例如位于中间的一个像素单元P31)与第一连接走线LS31连接，以减少走线数量，增大第一显示区10的开口率和透光率。
例如，第一连接走线与第一电源线同层设置且一体形成。图16A为图15中沿线C31-C32的截面示意图。线C31-C32沿第二方向X1穿过第一转接电极TS31、第一连接走线LS31以及第二转接电极TS32。如图16A所示，第一连接走线LS31位于第三绝缘层143远离衬底基板100的一侧，第一电源线VDD1与第一连接走线LS21同层设置且通过同一构图工艺一体形成。例如，如图17C所示，第一连接走线LS31以及第一电源线VDD1位于第三导电层SD31。第一连接走线LS31以及与第一连接走线LS31连接的第一电源线VDD1位于第一方向Y1上。
例如，如图17A以及图17B所示，多条转接电极包括第一转接电极TS31以及第二转接电极TS32，第一转接电极TS31以及第二转接电极TS32的沿第一方向YS延伸的部分并列设置。第一转接电极TS31以及第二转接电极TS32与在第一方向Y1上相邻的且属于不同第一像素单元组P30的第一像素单元P31分别连接的第一信号线DATA1相连接。也即，位于两列的属于同一个第一像素单元组P30的两个第一像素单元P31分别与第一转接电极TS31以及第二转接电极TS32连接。也即，位于两列的第一像素单元组P30的两个第一像素单元P31分别与第一转接电极TS31以及第二转接电极TS32 连接。第一转接电极TS31以及第二转接电极TS32先向靠近第一转接电极LS31的沿第二方向X1延伸，然后再沿第一方向Y1延伸。第一转接电极TS31以及第二转接电极TS32的沿第二方向X1延伸的部分较短，并且第一转接电极TS31以及第二转接电极TS32的主体部分沿第一方向Y1延伸。
例如，如图17A所示，第二转接电极TS32呈向图中右侧(远离第一连接走线LS21)开口的类似“凹”字型或“]”型。而如图17B所示，第一转接电极TS31呈向图中左侧(远离第一连接走线LS21)开口的类似“凹”字型或“[”型。第二转接电极TS32以及第二转接电极TS31的方向相反，都是都汇聚到第一连接走线LS31所在的位置，以与第一连接走线LS31重叠。
例如，相对于衬底基板，多条转接电极分别所在的膜层不同。如图16A所示，相对于衬底基板100，第一转接电极TS31以及第二转接电极TS32所在膜层不同。第一转接电极TS31位于第二绝缘层142与第三绝缘层143之间。例如，如图17B所示，第一转接电极TS31位于第二导电层GA32。第二转接电极TS32位于第一绝缘层141与第二绝缘层142之间。例如，如图17A所示，第二转接电极TS32位于第一导电层GA31。第二绝缘层142将第一转接电极TS31以及第二转接电极TS32间隔绝缘。第一转接电极TS31以及第二转接电极TS32位于不同的膜层可以减小第一转接电极TS31以及第二转接电极TS32之间间隔的尺寸，从而减小第一转接电极TS31以及第二转接电极TS32占据的空间。
例如，如图16A所示，第一连接走线LS31沿第二方向X1的截面的宽度W31的取值范围，例如约为5-6微米，宽度W31的取值，例如约为5.5微米。第一转接电极TS31沿第二方向X1的截面的宽度W32的取值范围，例如约为2-3微米，宽度W32的取值，例如约为2.5微米。第二转接电极TS32沿第二方向X1的截面的宽度W33的取值范围，例如约为2-3微米，宽度W33的取值，例如约为2.5微米。第一转接电极TS31与第二转接电极TS32沿第二方向X1上的间隙的宽度W34的取值范围，例如约为0.2-1.5微米，宽度W34的取值，例如约为0.5微米。
例如，如图15所示，第一信号线DATA1(位于图中左侧)通过第一过孔GH31与第一转接电极TS31连接。第一信号线DATA1(位于图中右侧)通过第二过孔GH32与第二转接电极TS32连接。参考图3A、图4B以及图4C，第一过孔GH31与第一过孔GH1同为贯穿第三绝缘层143的过孔，第二过孔GH32与第二过孔GH2同为贯穿第三绝缘层143以及第二绝缘层142的过孔。
例如，如图14以及图21所示，第一像素单元组P30的4个第一像素单元P30排布为两行两列，也就是说在同一行中，第一像素单元组P30包括两个第一像素单元P30。第一像素单元组P30的每个第一像素单元P31包括第一像素驱动电路12以及第一发光器件11，第一像素驱动电路12与第一发光器件11电连接以及驱动第一发光器件11发光。第一像素驱动电路12包括存储电容13，存储电容13包括第一极板CE1和与第一极板CE1重叠(例如部分重叠)设置的第二极板CE2。第一极板CE1位于第二绝缘层142远离衬底基板100的一侧。第二极板CE2位于第一绝缘层141远离衬底基板100的一侧。例如，如图17B所示，第一极板CE1位于第二导电层GA22。
例如，如图14以及图20A所示，与每个第一像素单元P30一一对应连接的多条第一电源线VDD1通过贯穿第三绝缘层143的过孔VH9和过孔VH3与第一极板CE1连接。第一电源线VDD1还可以通过过孔VH9和过孔VH3的其中之一与第一极板CE1连接。
例如，如图14以及图17B所示，第一像素单元组P30的位于同一行的两个第一像素单元P31的 第一极板CE1相互连接且一体形成，以节省制备工艺流程，降低成本。也就是说，每一个第一像素单元P31中的第一电源线VDD1都与其所对应的第一像素单元P31的存储电容13的第一极板CE1连接，以与第一像素单元P31电连接，通过将第一像素单元组P30的位于同一行的两个第一像素单元P31的第一极板CE1相互连接，而将两个第一像素单元P31中的第一电源线VDD1电连接。而位于不同行的第一电源线VDD1相互对应连接且一体成型。如前所述，当属于一个第一像素单元组P30的同一行的两个第一像素单元P31中的第一电源线VDD1电连接的情况下，可以通过设置一条第一连接走线LS31将两个第一像素单元P31其中之一中的第一电源线VDD1连接，以减少走线数量。
例如，如图10以及图13B所示，显示基板1还包括第四转接电极TS34，第四转接电极TS24(例如第四转接电极TS24的大部分)沿第二方向X1延伸。第四转接电极TS34与第二方向X1相邻设置且属于不同第一像素单元组P30的第一像素单元P31分别连接的第一电源线VDD1相电连接。如图14中所示的，多个第一像素单元组P30(图6中示出2个第一像素单元组P30)，排布为图1B所示的形式。也即，相邻的两列的多个第一像素单元组P30位于不同行，以在第一像素单元组P30之间留出更多的间隙，从而允许来自显示基板1的第一侧S1的光透过。
例如，如图14以及图17B所示，第四转接电极TS34的两端分别与相邻设置且属于不同第一像素单元组P30的两个第一像素单元P31的第一极板CE1连接，以将位于不同第一像素单元P31中的第一电源线VDD1电连接。由于相邻设置且属于不同第一像素单元组P30的两个第一像素单元P11相互错位，所以第四转接电极TS24还包括沿第一方向Y1延伸的部分。也即，第四转接电极TS34先沿第一方向Y1再沿第二方向X1延伸，然后沿第一方向Y1。
如图15、图17B以及图17C所示，第四转接电极TS34包括第一子转接电极TSP1、第二子转接电极TSP2以及第三子转接电极TSP3.第一子转接电极TSP1连接图中位于左侧的第一像素单元组P30，且呈“L”型。第二子转接电极TSP2连接图中位于右侧的第一像素单元组P30，且呈“L”型。第一子转接电极TSP1的第一端TSP11和第二子转接电极TSP2的第一端TSP21分别与第三子转接电极TSP3的两端连接。第三子转接电极TSP3沿第二方向X1延伸。第一子转接电极TSP1的第二端TSP2和第二子转接电极TSP2的第二端TSP21分别与相邻设置且属于不同第一像素单元组P30的两个第一像素单元P31的第一极板CE1连接。设置第三子转接电极TSP3可以降低其他走线的电信号对第四转接电极TS34的干扰。
例如，图16B为图15中沿线C33-C34的截面示意图。线C33-C34穿过第一子转接电极TSP1、第二子转接电极TSP2以及第三子转接电极TSP3。如图16B以及图17B所示，第一子转接电极TSP1和第二子转接电极TSP2位于第二绝缘层142与第三绝缘层143之间，也即第一子转接电极TSP1和第二子转接电极TSP2位于第二导电层GA32。第一子转接电极TSP1和第二子转接电极TSP2与相邻设置且属于不同第一像素单元组P30的第一像素单元P31的第一极板CE1连接且可以一体形成。
例如，如图16B以及图17C所示，第三子转接电极TSP3位于第三绝缘层143远离衬底基板100的一侧，也即位于第三导电层SD31。第四过孔GH33为贯穿所述第三绝缘层的过孔，第五过孔GH34也为贯穿第三绝缘层的过孔。第三子转接电极TSP3通过第四过孔GH33与第一子转接电极TSP1的第一端TSP11连接，第三子转接电极TSP3通过第五过孔GH34与第二子转接电极TSP2的第一端TSP21连接。
例如，如图14所示，当第一像素单元组P30的4个第一像素单元P20排布为两行两列时，第一像素单元组P30的位于第一行的第一像素单元P21与不同的第四转接电极TS24连接。以图14中示出的右侧的第一像素单元组P30(如图示出4个第一像素单元P31)为例，第一像素单元组P30的第一行的第一列(即左侧)第一像素单元P31的第一极板CE1与左上方的第四转接电极TS34连接，左上方的第四转接电极TS34还与位于左上方的第一像素单元组P30的第二行的第二列(即右侧)第一像素单元P31的第一极板CE1连接。第一像素单元组P30的第一行的第二列(即右侧)第一像素单元P31的第一极板CE1与右上方的第四转接电极TS34连接，右上方的第四转接电极TS34还与位于右上方的第一像素单元组P30的第二行的第一列(即左侧)第一像素单元P21的第一极板CE1(图中未示出)连接。
在其它实施例中，第一像素单元组P30的第二行的第一列(即左侧)第一像素单元P31的第一极板CE1还可以与左下方的第四转接电极TS34连接，左下方的第四转接电极TS34还与位于左下方的第一像素单元组P30的第一行的第二列(即右侧)第一像素单元P31的第一极板CE1连接。第一像素单元组P30的第二行的第二列(即右侧)第一像素单元P31的第一极板CE1与右下方的第四转接电极TS34连接，右上方的第四转接电极TS34还与位于右下方的第一像素单元组P30的第一行的第一列(即左侧)第一像素单元P31的第一极板CE1(图中未示出)连接。
例如，如图15所示，第四转接电极TS34的宽度W35(例如垂直于第四转接电极TS34的走线方向)的取值范围，例如约为2-3微米，宽度W35的取值，例如约为2.5微米。
例如，图17D为图14所示的第一显示区的子像素排布示意图。如图17D所示，第一像素单元组P30的排布为两行两列的四个第一像素单元P31可以分别包括红色子像素(R)、蓝色子像素(B)、绿色子像素(G1)以及绿色子像素(G2)(也就是两个绿色子像素)，即，在一个第一像素单元组P30中，位于第一行的两个第一像素单元P31包括红色子像素(R)以及绿色子像素(G1)，位于第二行的两个第一像素单元P31包括蓝色子像素(B)和绿色子像素(G2)，也即，在一个第一像素单元组P30中，第一行中的第一列(也即左上角)的第一像素单元P31的发光器件11发红色光，第一行中的第二列(也即右上角)的第一像素单元P31的发光器件11发绿色光，第二行中的第一列(也即左下角)的第一像素单元P31的发光器件11发蓝色光，第二行中的第二列(也即右下角)的第一像素单元P31的发光器件11发绿色光，以实现画面的显示。可以根据实际显示需要选择第一像素单元组P30的第一像素单元P31的发光颜色，本公开实施例不以此为限。
例如，图2、图6、图10以及图14分别示出的显示基板的第一显示区中的第一像素单元以及走线的排布方式都有差异，在第一显示区10的透光率方面，图10所示的实施例小于图6所示的实施例小于图14所示的实施例小于图2所示的实施例。在第一显示区10的显示效果方面，图2所示的实施例小于图6所示的实施例小于图10所示的实施例，而图10所示的实施例等于图14所示的实施例。可以根据对产品在第一显示区10在透光率以及显示效果方面的要求进行灵活选择第一显示区中的第一像素单元以及走线的排布方式。
例如，如图1B以及图1C所示，与靠近第二显示区20的第一像素单元组P0(P10/P20/P30)的第一像素单元连接的第一信号线DATA1以及第一电源线VDD1延伸至第二显示区20，以与相对于第一像素单元P0(P10/P20/P30)位于第一方向Y1的第二像素单元C连接。也即，图中第一显示区10 中的位于最靠近第二显示区20(例如第一显示区10的最下方或最上方)的一行第一像素单元，与该第一像素单元连接的第一信号线DATA1以及第一电源线VDD1，可以延伸至第二显示区20，从而与第二显示区20中的第二像素单元C连接。使得，相对于第一显示区10中的第一像素单元，在第一方向Y1上的第二像素单元C(也即与第一显示区10中的第一像素单元位于同一列)由一条第一信号线DATA1以及第一电源线VDD1连接以提供相同的第一显示信号以及第一电源电压。
例如，图18为本公开至少一实施例提供的一种显示基板的第二显示区中走线的平面布局示意图。如图18所示，显示基板还包括位于第二显示区20的多条第二信号线DATA2以及多条第二电源线VDD2。第二显示区20的多个第二像素单元C排布为第二方向X1上并列的多列，也即排布为阵列排布的多行多列，并且多个第二像素单元C所排布的相邻行以及相邻列之间不存在间隙。第二显示区20的像素密度大于第一显示区10的像素密度。
第二信号线DATA2沿第一方向Y1延伸，多条第二信号线DATA2的每条穿过在第一方向Y1上排布为一列的多个第二像素单元C，并与排布为一列的多个第二像素单元C电连接，以向多个第二像素单元C提供第二显示信号。第二电源线VDD2沿第一方向Y1延伸，多条第二电源线VDD2的每条穿过在第一方向Y1上排布为一列的多个第二像素单元C，并与排布为一列的多个第二像素单元C电连接，以向多个第二像素单元C提供第二电源电压。
例如，第二像素单元C的第二像素驱动电路的结构可以与第一像素单元P1(P11/P21/P31)的第一像素驱动电路的结构相同，例如，选择为图20A所示的结构。第二电源线VDD2与第二像素单元C的电连接方式，与第二电源线VDD1与第一像素单元P1(P11/P21/P31)的电连接方式可以相同，也即第二电源线VDD2与第二像素单元C的第二像素驱动电路的存储电容的第一极板CE21连接。位于同一行的第二像素单元C的第一极板CE0之间相互连接且一体形成，从而使得第二显示区20的多个第二像素单元C的第二电源电压相同。
需要说明的是，第二像素单元C的第二像素驱动电路可以选择与第一像素单元P1(P11/P21/P31)的第一像素驱动电路相同的电路结构，为了简洁，将详细介绍第一像素驱动电路以7T1C型电路为例的结构，第一像素驱动电路将不再赘述。
例如，图19为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的等效电路图。图20B-20E为本公开至少一实施例提供的一种显示基板的第一显示区中的第一像素驱动电路的各层的示意。
例如，如图19所示，第一像素驱动电路包括多个薄膜晶体管：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多条信号线和存储电容13，也即，该实施例中像素电路为7T1C结构。相应地，多条信号线包括栅线GLn/GLn-1(即扫描信号线)、发光控制线EM、初始化线RL、第一信号线DATA1和第一电源线VDD1。栅线GLn/GLn-1可包括第一栅线GLn和第二栅线GLn-1。例如，第一栅线GLn用于传输栅极扫描信号，第二栅线GLn-1用于传输复位电压信号发光控制线EM用于传输发光控制信号，例如连接到第一发光控制端EM1和第二发光控制端EM2。第五晶体管T5的栅极与第一发光控制端EM1连接，或作为第一发光控制端EM1，以接收第一发光控制信号；第六晶体管T6的栅极与第二发光控制端EM2连接，或作为第二发光控制端EM2，以接收第二 发光控制信号。
需要说明的是，本公开实施例包括但并不限于上述7T1C结构的像素电路，像素电路也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开实施例对此不作限制。
例如，如图19所示，第一薄膜晶体管T1的第一栅极与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图19所示，第二薄膜晶体管T2的第二栅极被配置为与第一栅线GLn电连接，以接收栅极扫描信号；第二薄膜晶体管T2的第二源极S2被配置为与第一信号线DATA1电连接，以接收数据信号。第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图19所示，第三薄膜晶体管T3的第三栅极被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏电极D1电连接，第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极电连接。
例如，如图19所示，第四薄膜晶体管T4的第四栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化电压信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极电连接。
例如，如图19所示，第五薄膜晶体管T5的第五栅极被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD1电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图19所示，第六薄膜晶体管T6的第六栅极被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光元件11的第一电极(例如阳极211)电连接。图22中的薄膜晶体管T6即第六薄膜晶体管T6。
例如，如图19所示，第七薄膜晶体管T7的第七栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第七薄膜晶体管T7的第七源极S7与发光元件11的第一电极(例如阳极111)电连接，第七薄膜晶体管T7的第七漏极D7被配置为与初始化线RL电连接以接收初始化电压信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如，如图19和图20A所示，存储电容13包括第一极板CE1和第二极板CE2。第一极板CE1与第一电源线VDD1电连接，第二极板CE2与第一薄膜晶体管T1的第一栅极和第三薄膜晶体管T3的第三漏极D3电连接。例如，第一电源线VDD1与存储电容13的第一极板CE1通过第三过孔VH3以及第九过孔VH9连接，存储电容13的第一极板CE1通过第一子走线2422与在第二方向X1相邻的第一极板CE1连接。
例如，如图19所示，发光元件11的第二电极(例如阴极113)与第二电源线VSS电连接。
例如，第一电源线VDD1为第一像素驱动电路提供高电压的电源线，第二电源线VSS为第一像素驱动电路提供低电压(低于前述高电压)的电源线。在如图19所示的实施例中，第一电源线VDD1 提供恒定的第一电源电压，第一电源电压为正电压；第二电源线VSS提供恒定的第二电源电压，第二电源电压可以为负电压等。例如，在一些示例中，第二电源电压可以为接地电压。
需要说明的是，上述的复位电压信号和上述的初始化电压信号可为同一信号。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
在一些实施例中，如20A所示，像素电路包括上述的薄膜晶体管T1、T2、T3、T4、T5、T6和T7、存储电容13、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、初始化线RL、第一信号线DATA1和第一电源线VDD1。
下面，结合图19和图20A-20E对像素电路的结构进行说明。
例如，图20A为像素电路的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的布局示意图。
图20B示出了像素电路的半导体层。例如，图20B所示的该半导体层包括图21中所示的有源层121，该有源层121例如为第六薄膜晶体管T6的有源层。如图20B所示，半导体层可采用半导体材料层通过构图工艺形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料(例如，氧化铟镓锡(IGZO))等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开一些实施例提供的显示基板中，在上述的半导体层上形成有一个或多个其他绝缘层，该绝缘层包括图21中所示的第一绝缘层141；为了清楚起见，图20A-20E中未示出绝缘层，而在后续的图21以及图22中示出，后续详细介绍。
图20C示出了第一像素驱动电路的第一导电层。例如，如图20C所示，第一导电层可包括存储电容13的第二极板CE2、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极。
如图20B所示，第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1与半导体层交叠的部分。第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可为第一极板CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
例如上述各个薄膜晶体管的栅极分别与相应的第一栅线GLn或第二栅线GLn-1一体成型。
在本公开一些实施例提供的显示基板中，在上述的第一导电层上形成有其他一个或多个绝缘层，例如，该绝缘层包括图21中所示的第二绝缘层142。
图20D示出了第一像素驱动电路的第二导电层。例如，结合图20A与图20D，第一像素驱动电路的第二导电层包括存储电容13的第一极板CE1、初始化线RL和第二子走线2422，即第二子走线2422与存储电容13的第一极板CE1同层设置且一体形成。例如，第二子走线2422也可以视为第一极板CE1延伸的一部分。第二极板CE2与第一极板CE1至少部分重叠以形成存储电容13。
例如，在一些实施例中，第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板100上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板100上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层，从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素电路的第二遮光部792为一体结构，并通过贯穿绝缘层中的第十过孔VH9’与第一电源线VDD1电连接，如图20A所示。
在本公开一些实施例提供的显示基板中，在上述的第二导电层上形成有一个或多个其他绝缘层，例如，该绝缘层包括图21中所示的第三绝缘层143。
图20E示出了像素电路的第三导电层。例如，如图20E所示，第一像素驱动电路的第三导电层包括第一信号DATA1和第一电源线VDD1。结合图50A-20E所示，第一信号线DATA1通过第一绝缘层、第二绝缘层和第三绝缘层中的至少一个过孔(例如过孔VH1)与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD1通过第一绝缘层、第二绝缘层和第三绝缘层中的至少一个过孔(例如过孔VH2)与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD1通过第三绝缘层中的至少一个过孔(例如过孔VH3)与第二导电层中的第一极板CE1相连。
例如，结合图20A和图20E，第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过第一绝缘层、第二绝缘层和第三绝缘层中的至少一个过孔(例如过孔VH4)与半导体层中对应第三薄膜晶体管T3的漏极区域相连，第一连接部CP1的另一端通过第二绝缘层和第三绝缘层中的至少一个过孔(例如过孔VH5)与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过第三绝缘层中的一个过孔(例如过孔VH6)与初始化线RL相连，第二连接部CP2的另一端通过第一绝缘层、第二绝缘层和第三绝缘层中的至少一个过孔(例如过孔VH7)与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过第一栅极绝缘层、第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。
例如，图21为本公开至少一实施例提供的一种显示基板中第一显示区的截面示意图。如图21所示，显示基板1还包括第一平坦化层144、像素限定层145。第一像素单元包括第一发光器件11以及第一像素驱动电路12。
例如，第一平坦化层144位于第一像素驱动电路12的远离衬底基板100的一侧以提供平坦化表面，第一平坦化层144提供平坦化表面且包括过孔144A。第六晶体管T6包括有源层121、栅极122、和源漏电极(源极123以及漏极124)。存储电容13包括第一极板CE1和第二极板CE2。有源层121设置在衬底基板100上，第一绝缘层141设置在有源层121的远离衬底基板100的一侧，栅极122和第二极板CE2同层设置在第一绝缘层141的远离衬底基板100的一侧，第二绝缘层142设置在栅极 122和第二极板CE2的远离衬底基板100的一侧。第一极板CE1设置在第二绝缘层142的远离衬底基板100的一侧，第三绝缘层143设置在第一极板CE1的远离衬底基板100的一侧。源极123以及漏极124设置在第三绝缘层143远离衬底基板100的一侧，并通过第一绝缘层141、第二绝缘层142以及第三绝缘层143中的过孔与有源层121电连接。
例如，第一平坦化层144的材料包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，也可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，本公开的实施例对此不做限定。
例如，有源层121的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极122的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。源极123及漏极124的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。本公开的实施例对各功能层的材料不做具体限定。
例如，如图21所示，第一发光器件11包括第一电极111(例如为阳极)、第一发光层112以及第二电极113(例如为阴极)。第一电极111位于第一平坦化层144远离衬底基板100的一侧并通过第一平坦化层144的过孔144A与第六晶体管T6的源极123(或漏极124)连接。像素限定层145位于第一发光器件11的第一电极111远离衬底基板100的一侧，并包括第一像素开口145A。第一像素开口145A与第一发光器件11对应，以形成第一发光器件11的发光区。第二电极113位于像素限定层145的远离衬底基板100的一侧。发光层112位于第一像素开口145A中且位于第一电极111与第二电极112之间。发光层112直接夹置在第一电极111与第二电极112之间的部分在通电后将会发光，由此该部分所占据的区域对应于发光区。
例如，像素限定层145的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，第一电极111的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极111可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，第一发光层112可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极113可以包括各种导电材料。例如，第二电极113可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，在第一平坦化层与源极123及漏极124之间还可以设置钝化层。钝化层可以设置为包括过孔以露出源极123及漏极124之一，例如露出漏极124。钝化层可以保护源极123及漏极124不被水 汽腐蚀。例如，钝化层的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护第一像素电路12不被水汽腐蚀。
例如，第一电极111与第一像素电路12之间还可以设置转接电极，该转接电极与第一电极111以及第一像素电路12连接，以将第一电极111与第一像素电路12电连接。本公开实施例不以第一像素单元的具体结构为限。
例如，如图21所示，显示基板1还包括封装层146。封装层146位于第二电极113远离衬底基板100的一侧。封装层146将第一发光器件11密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的第一发光器件11的劣化。封装层146可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层146包括至少一层封装子层。例如，封装层146可以包括依次设置的第一无机封装层、第一有机封装层、第二无机封装层。
例如，该封装层146的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，图22为本公开至少一实施例提供的一种显示基板中第二显示区的截面示意图。显示基板1的第二显示区20的多个第二像素单元C每个包括第二发光器件21以及第二像素驱动电路22，第二像素驱动电路22与第二发光器件21电连接以驱动第二发光器件21。
例如，第二像素驱动电路22包括第六晶体管T6’和存储电容23等结构。第二发光器件21包括第三电极211、第四电极213以及第三电极211与第四电极213之间的第二发光层212。第一平坦化层144位于第二像素驱动电路22的远离衬底基板100的一侧以提供平坦化表面，第一平坦化层144提供平坦化表面且包括过孔144A。第三电极211通过过孔144A与第二像素驱动电路22电连接。例如，第三电极211为第二发光器件21的阳极，第四电极213为第二发光器件21的阴极。像素限定层145设置在第三电极211的远离衬底基板100的一侧，且包括多个开口。第二光层212设置在像素限定层145的多个开口中。第四电极213设置在第二发光层212以及像素限定层145的远离衬底基板100的一侧。第三电极211与第一电极111同层设置且材料相同，第四电极213与第二电极113同层设置且材料相同。第二发光层212与第一发光层112同层设置且材料相同。
例如，第六晶体管T6’包括有源层221、栅极222、源漏电极(即源极223和漏极224)等结构，存储电容23包括第一极板CE21和第二极板CE22。有源层321设置在衬底基板100上，第一绝缘层141设置在有源层221的远离衬底基板100的一侧，栅极222和第二极板CE22同层设置在第一绝缘层141的远离衬底基板100的一侧，第二绝缘层142设置在栅极222和第一电容极板231的远离衬底基板14的一侧，第一极板CE21设置在第二绝缘层142的远离衬底基板100的一侧，第三绝缘层143设置在第一极板CE21的远离衬底基板100的一侧，源漏电极设置在第三绝缘层143的远离衬底基板14的一侧，并通过第一绝缘层141、第二绝缘层142和第三绝缘层143中的过孔与有源层221电连接，源漏电极的远离衬底基板100的一侧设置有第一平坦化层144提供第一平坦化表面，以平坦化第三像素电路。
例如，第六晶体管T6’的有源层221、栅极222、源漏电极(即源极223和漏极224)分别与第六晶体管T6源层121、栅极122、和源漏电极(源极123以及漏极124)的同层设置且材料相同。存储电容23的第一极板CE21和第二极板CE22分别与存储电容13的第一极板CE1和第二极板CE2同层设置且材料相同。
需要说明的是，第二显示区20中的第二像素驱动电路22与第一显示区10中的第一像素驱动电路12具有相同的结构，因此在制备工艺中可采用相同的构图工艺形成。例如，第一绝缘层141、第二绝缘层142、第三绝缘层143、第一平坦化层144、像素限定层145以及封装层146在第二显示区20和第一显示区10是同层设置的，在一些实施例中还是一体的，例如为同一绝缘层，因此在附图中采用了相同的标号。
例如，本公开至少一实施例中的衬底基板100可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料；例如，衬底基板100可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
图23为本公开至少一实施例提供的一种显示装置的示意图。本公开至少一个实施例提供一种显示装置2，该显示装置20可以包括上述任一实施例的显示基板1。
例如，如图23所示，显示装置2还可以包括柔性电路板及控制芯片。例如，柔性电路板邦定到显示基板1的邦定区，而控制芯片安装在柔性电路板上，由此与显示区电连接；或者，控制芯片直接邦定到邦定区，由此与显示区电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置2可以为OLED面板、OLED电视、QLED面板、QLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置2还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。
例如，如图23以及图1D所示，显示装置2还包括传感器192。传感器192设置于显示基板1的第二侧S2(例如非显示侧)。传感器192配置为接收来自显示基板1的第一侧S1(例如显示基板的显示侧)的光(例如为准直光或准直光)。传感器192在衬底基板100上的正投影与第一显示区10至少部分重叠。
例如，传感器192为图像传感器、红外传感器、距离传感器等，传感器192例如可以实现为芯片等形式。传感器192设置在显示基板的非显示侧S2(背离使用者一侧)。
例如，在传感器192与第一显示区10在显示基板的显示面的法线方向上至少部分重叠。
例如，传感器192可以是图像传感器，并可以用于采集传感器192的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器；该传感器192还可以是红外传感器、距离传 感器等。该传感器192可用于实现诸如手机、笔记本的移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。本公开的实施例对于传感器192的类型、功能以及设置方式不作限制。
传感器192通过双面胶等方式设置在显示面板的非显示侧S2，并且传感器192在衬底基板100上的正投影与第一显示区10至少部分重叠，配置为接收来自第一侧S1的光。由此，第一显示区10在实现显示的同时，还为传感器192的设置提供了便利。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置的全部组成单元。为实现该显示装置的基板功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示装置的技术效果可以参考本公开的实施例中提供的显示基板的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，具有用于显示的第一侧，和与所述第一侧相对的第二侧，包括：
    衬底基板，
    显示区，设置在所述衬底基板上，包括第一显示区，所述第一显示区允许来自所述显示基板的第一侧的光至少部分透射至所述显示基板的第二侧，
    其中，所述第一显示区包括第一子像素阵列，所述第一子像素阵列包括在第一方向以及与所述第一方向交叉的第二方向上排布的多个第一像素单元组、多条第一信号线以及多条第一电源线，
    所述第一像素单元组包括至少一个第一像素单元，
    所述多条第一信号线的每条至少部分沿所述第一方向延伸，并配置为给所述多个第一像素单元提供第一显示信号，所述多条第一信号线与所述多个第一像素单元组的第一像素单元连接，
    所述多条第一电源线至少部分沿所述第一方向延伸，并配置为给所述多个第一像素单元提供第一电源电压，所述多条第一电源线与所述多个第一像素单元组的第一像素单元连接；
    至少一条连接走线，其中，至少一条连接走线的每条至少部分沿所述第一方向延伸，并与在所述第一方向上的相邻的第一像素单元组分别连接的第一电源线相连接；以及
    至少一条转接电极，其中，至少一条转接电极的每条至少部分沿所述第一方向延伸，并与在所述第一方向上的相邻的第一像素单元组分别连接的第一信号线相连接；
    其中，所述至少一条转接电极的至少部分条转接电极所在的膜层与所述至少一条连接走线的每条所在的膜层不同，并且
    所述至少一条转接电极在所述衬底基板上的正投影与所述至少一条连接走线在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述至少一条连接走线包括第一连接走线，
    所述第一连接走线沿所述第一方向延伸，所述第一连接走线与在所述第一方向上相邻的且属于不同第一像素单元组的第一像素单元分别连接的第一电源线相连接，
    所述第一连接走线与所述第一电源线同层设置且一体形成。
  3. 根据权利要求2所述的显示基板，其中，所述第一像素单元组的至少一个第一像素单元包括多个第一像素单元，所述至少一条转接电极包括多条转接电极，
    所述多条转接电极一一对应连接在所述第一方向上相邻且属于不同第一像素单元组的多个第一像素单元，
    所述多条转接电极分别所在的膜层不同。
  4. 根据权利要求3所述的显示基板，其中，所述第一像素单元组的多个第一像素单元排布为沿所述第二方向并列的至少两列，所述多条转接电极包括第一转接电极以及第二转接电极，所述第一转接电极以及所述第二转接电极并列设置，
    所述第一转接电极以及所述第二转接电极与在所述第一方向上相邻的且属于不同第一像素单元组的第一像素单元分别连接的第一信号线相连接，
    所述第一转接电极以及所述第二转接电极所在膜层不同，所述第一转接电极与所述第二转接电极在所述衬底基板上的正投影与所述第一连接走线在所述衬底基板上的正投影至少部分重叠。
  5. 根据权利要求4所述的显示基板，其中，所述第一转接电极的沿所述第一方向延伸的部分以及所述第二转接电极的沿所述第一方向延伸的部分在所述衬底基板的正投影，与所述第一连接走线沿所述第一方向延伸的部分在所述衬底基板的正投影重叠。
  6. 根据权利要求4或5所述的显示基板，其中，在所述第一方向以及与所述第二方向上相邻的第一像素单元组之间具有允许光透射的间隙，
    所述第一连接线的部分以及所述至少一条转接电极的每条的部分沿所述第二方向延伸并绕过所述允许光透射的间隙。
  7. 根据权利要求6所述的显示基板，其中，所述第一连接走线为弯折走线，且包括第一部分、第二部分以及第三部分，
    所述第一部分的第一端和所述第二部分的第一端分别与所述第三部分的两端连接且沿与所述第一方向不同的第二方向延伸，
    所述第三部分沿所述第一方向延伸，
    所述第一部分的第二端和所述第二部分的第二端分别与在所述第一方向上的相邻的第一像素单元分别连接的第一电源线相连接。
  8. 根据权利要求7所述的显示基板，其中，所述第一转接电极和所述第二转接电极在衬底基板上的正投影与所述第一连接走线的第一部分、第二部分以及第三部分的至少之一在所述衬底基板上的正投影重叠。
  9. 根据权利要求3所述的显示基板，其中，所述第一像素单元组的多个第一像素单元包括排布为沿所述第二方向并列的至少三列，
    所述至少一条转接电极包括第一转接电极、第二转接电极以及第三转接电极，所述第一转接电极、所述第二转接电极以及所述第三转接电极并列设置，所述第三转接电极位于所述第一转接电极以及所述第二转接电极之间，
    所述第一转接电极、所述第二转接电极以及所述第三转接电极分别对应与在所述第一方向上相邻的第一像素单元分别连接的第一信号线相连接，
    所述第一转接电极、所述第二转接电极以及所述第三转接电极所在膜层不同，
    所述第一连接走线在所述衬底基板上的正投影与所述第一转接电极以及所述第二转接电极的至少之一在所述衬底基板上的正投影至少部分重叠，
    所述第三转接电极与所述第一连接走线同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述第三转接电极在所述衬底基板上的正投影与所述第一转接电极或所述第二转接电极在所述衬底基板上的正投影至少部分重叠。
  11. 根据权利要求9或10所述的显示基板，还包括：第一绝缘层、第二绝缘层以及第三绝缘层，
    所述第一绝缘层位于所述衬底基板上，所述第二绝缘层位于所述第一绝缘层远离所述衬底基板的一侧，所述第三绝缘层位于所述第二绝缘层远离所述衬底基板的一侧，
    所述多条第一信号线、所述多条第一电源线以及所述第一连接走线位于所述第三绝缘层远离衬底基板的一侧，
    所述第二转接电极位于所述第一绝缘层远离所述衬底基板的一侧，并通过贯穿所述第二绝缘层以及所述第三绝缘层的过孔连接，在所述第一方向上相邻的第一像素单元连接的第一信号线，
    所述第一转接电极位于所述第二绝缘层远离所述衬底基板的一侧，并通过贯穿所述第三绝缘层的过孔连接，在所述第一方向上相邻的第一像素单元连接的第一信号线，
    所述第三转接电极位于所述第三绝缘层远离所述衬底基板的一侧。
  12. 根据权利要求11所述的显示基板，其中，所述第一像素单元组的多个第一像素单元排布为沿所述第二方向的至少一行，在同一行中，所述第一像素单元组包括至少两个第一像素单元，
    所述第一像素单元组的每个第一像素单元包括第一像素驱动电路以及第一发光器件，所述第一像素驱动电路与所述第一发光器件连接以及驱动所述第一发光器件发光，
    所述第一像素驱动电路包括存储电容，所述存储电容包括第一极板和与所述第一极板至少部分重叠设置的第二极板，
    所述第一极板位于所述第二绝缘层远离所述衬底基板的一侧，所述第二极板位于所述第一绝缘层远离所述衬底基板的一侧，
    与每个所述第一像素单元连接的所述多条第一电源线通过贯穿所述第三绝缘层的过孔与所述第一极板连接，
    所述第一像素单元组的位于同一行的至少两个第一像素单元的第一极板相互连接且一体形成。
  13. 根据权利要求12所述的显示基板，还包括第四转接电极，
    其中，所述第四转接电极至少部分沿所述第二方向延伸，所述第四转接电极与所述第二方向错位且相邻设置且属于不同第一像素单元组的第一像素单元分别连接的第一电源线相连接。
  14. 根据权利要求12所述的显示基板，还包括第四转接电极，其中，所述第四转接电极沿所述第二方向延伸，所述第四转接电极与所述第二方向相邻设置且属于不同第一像素单元组的两个第一像素单元分别连接的第一电源线相连接。
  15. 根据权利要求13或14所述的显示基板，其中，所述第四转接电极的两端，分别与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接，以将位于所述不同第一像素单元组中的第一电源线连接。
  16. 根据权利要求15所述的显示基板，其中，所述第四转接电极位于所述第三绝缘层远离所述衬底基板的一侧，所述第四转接电极通过贯穿所述第三绝缘层的过孔，与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接。
  17. 根据权利要求15或16所述的显示基板，其中，所述第四转接电极位于所述第二绝缘层远离衬底基板的一侧，所述第四转接电极与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板同层设置且一体形成。
  18. 根据权利要求15或16所述的显示基板，其中，所述第四转接电极包括第一子转接电极、 第二子转接电极以及第三子转接电极，
    所述第一子转接电极的第一端和所述第二子转接电极的第一端分别与所述第三子转接电极的两端连接，
    所述第一子转接电极的第二端和所述第二子转接电极的第二端分别与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板连接，
    所述第一子转接电极和所述第二子转接电极与所述相邻设置且属于不同第一像素单元组的两个第一像素单元的第一极板同层设置且一体形成，
    所述第三子转接电极位于所述第三绝缘层的远离衬底基板的一侧，所述第三子转接电极通过贯穿所述第三绝缘层的过孔与所述第一子转接电极以及所述第二子转接电极连接。
  19. 根据权利要求3所述的显示基板，其中，所述第一像素单元组的多个第一像素单元排布为多行多列，
    在同一个第一像素单元组中，与同一列的第一像素单元的连接的第一信号线相互连接且一体形成，与同一列的第一像素单元的连接第一电源线也相互连接且一体形成。
  20. 根据权利要求1-19任一所述的显示基板，其中，所述显示区还包括第二显示区，所述第二显示区至少部分围绕所述第一显示区，
    所述第二显示区包括第二子像素阵列，所述第二子像素阵列包括多个第二像素单元，
    所述多个第二像素单元的每个包括第二发光器件以及第二像素驱动电路，所述第二像素驱动电路被配置为驱动所述第二发光器件发光，
    与靠近所述第二显示区的第一像素单元连接的第一信号线延伸至所述第二显示区，以与相对于所述第一像素单元位于所述第一方向的第二像素单元连接，
    与靠近所述第二显示区的第一像素单元连接的第一电源线延伸至所述第二显示区，以与相对于所述第一像素单元位于所述第一方向的第二像素单元连接。
  21. 根据权利要求20所述的显示基板，其中，所述第二显示区的像素密度大于所述第一显示区的像素密度。
  22. 根据权利要求20或21所述的显示基板，还包括位于所述第二显示区的多条第二信号线以及多条第二电源线，
    其中，所述多个第二像素单元排布为所述第二方向上并列的多列，
    所述多条第二信号线沿所述第一方向延伸，所述多条第二信号线的每条穿过在所述第一方向上排布为一列的所述多个第二像素单元，以向所述多个第二像素单元提供第二显示信号，
    所述多条第二电源线沿所述第一方向延伸，所述多条第二电源线的每条穿过在所述第一方向上排布为一列的所述多个第二像素单元，以向所述多个第二像素单元提供第二电源电压。
  23. 一种显示装置，包括权利要求1-21任一所述的显示基板。
  24. 根据权利要求23所述的显示装置，还包括传感器，
    其中，所述传感器设置于所述显示基板的第二侧，并且所述传感器配置为接收来自所述显示基板的第一侧的光。
  25. 根据权利要求24所述的显示装置，其中，所述传感器在所述衬底基板上的正投影与所述 第一显示区至少部分重叠。
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