WO2021147160A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021147160A1
WO2021147160A1 PCT/CN2020/080182 CN2020080182W WO2021147160A1 WO 2021147160 A1 WO2021147160 A1 WO 2021147160A1 CN 2020080182 W CN2020080182 W CN 2020080182W WO 2021147160 A1 WO2021147160 A1 WO 2021147160A1
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WIPO (PCT)
Prior art keywords
line
display area
display
sub
light
Prior art date
Application number
PCT/CN2020/080182
Other languages
English (en)
French (fr)
Inventor
黄炜赟
黄耀
于池
肖星亮
石博
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from PCT/CN2020/073996 external-priority patent/WO2021147083A1/zh
Priority claimed from PCT/CN2020/073993 external-priority patent/WO2021147081A1/zh
Priority claimed from PCT/CN2020/074001 external-priority patent/WO2021147086A1/zh
Priority claimed from PCT/CN2020/073995 external-priority patent/WO2021147082A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020217038802A priority Critical patent/KR20220129999A/ko
Priority to CN202080000311.1A priority patent/CN113508466A/zh
Priority to US17/297,641 priority patent/US11968865B2/en
Priority to JP2022502521A priority patent/JP2023520267A/ja
Priority to EP20891410.1A priority patent/EP4095921A4/en
Publication of WO2021147160A1 publication Critical patent/WO2021147160A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a display area, at least one first signal line, and at least one connection trace.
  • the display area includes a first display area and a second display area; the second display area at least partially surrounds the first display area; the first display area includes at least one first light-emitting element, and the second display area
  • the area includes at least one first pixel circuit; the at least one first signal line includes a first body portion and a first winding portion; the first body portion extends in a first direction, and the first winding portion is offset
  • the first main body portion is routed along a virtual extension line in the first direction; the at least one first signal line is electrically connected to the at least one first pixel circuit to form the at least one first pixel
  • the circuit provides a first driving signal; the at least one first pixel circuit is electrically connected to the at least one first light-emitting element via corresponding connecting wires; and the at least one first pixel circuit is configured to drive the At least one first light-
  • the display substrate further includes at least one second signal line.
  • the at least one second signal line includes a second main body portion that extends in a second direction that crosses the first direction; the first main body portion extends in the first direction
  • the virtual extension line and the virtual extension line of the second main body portion extending along the second direction intersect in the first display area; the second main body portion of the at least one second signal line and the at least one second signal line
  • One first pixel circuit is electrically connected to provide the at least one first pixel circuit with a second driving signal different from the first driving signal.
  • the at least one connecting wire extends from the first display area to the second display area along the second direction.
  • the first body portion includes a first sub-portion and a second sub-portion separated by the first display area; the first sub-portion and the first sub-portion The two sub-parts are electrically connected via the first winding part; and at least a part of the first winding part is located between the first sub-part and the second sub-part and extends in the first direction The virtual lines cross.
  • the second display area has an inner edge and an outer edge, and the inner edge of the second display area surrounds the first winding part.
  • the at least one first signal line further includes a second winding part.
  • the first end of the second winding part is electrically connected to the second sub-part, and the second end of the second winding part is electrically connected to the corresponding first pixel circuit;
  • the second winding part includes The first wire portion and the second wire portion that are sequentially connected; the end of the first wire portion that is not connected to the second wire portion serves as the first end of the second winding portion; the second wire portion The end that is not connected to the first wire portion serves as the second end of the second winding portion;
  • the first wire portion extends in a second direction that crosses the first direction;
  • the second wire portion extends along The first direction extends and is arranged side by side with the second sub-portion in the second direction; and in operation, the current flow in the second wire portion is opposite to the current flow in the main body portion.
  • the display substrate further includes a peripheral area surrounding the display area.
  • the first line portion is entirely located in the peripheral area, and is arranged side by side with the second display area in the first direction.
  • the display substrate further includes a peripheral area surrounding the display area.
  • the first wire portion includes a first portion, a second portion, and a third portion that are sequentially connected; the first portion of the first wire portion is electrically connected to the second sub-portion, and the first portion of the first wire portion is electrically connected to the second sub-portion.
  • the three parts are electrically connected to the second line part; the first part of the first line part is located in the peripheral area and is arranged in parallel with the second display area in the first direction; the first line part The second portion of the first line portion extends from the peripheral area to the second display area along the first direction; and the third portion of the first line portion is located in the second display area, and the first line portion A virtual extension line of the third part extending along the second direction is arranged side by side with the first display area in the first direction.
  • the at least one first signal line further includes a third winding part.
  • the first end of the third winding part is electrically connected to the first sub-part, and the second end of the third winding part is electrically connected to the corresponding first pixel circuit, and is connected to the second winding part.
  • the connected first pixel circuit is different from the first pixel circuit connected to the third winding portion.
  • the third winding portion includes a third wire portion and a fourth wire portion that are sequentially connected; the third wire portion is not connected to the fourth wire portion.
  • One end serves as the first end of the third winding part, and the end of the fourth thread part that is not connected to the third thread part serves as the second end of the third winding part;
  • the second direction extends and is arranged side by side with the first line portion in the first direction;
  • the fourth line portion extends along the first direction and is in the first direction with the first sub-portion. Arranged side by side in two directions; and in operation, the current direction in the fourth wire portion is the same as the current direction in the main body portion.
  • the first body portion, the first winding portion, and the second wire portion are located on the first electrode layer of the display substrate; the first wire portion The second electrode layer is located on the display substrate; the first electrode layer and the second electrode layer are stacked in the normal direction of the display surface of the display substrate; and the first line portions are respectively located via The first via hole and the second via hole of the insulating layer between the first electrode layer and the second electrode layer are electrically connected to the second sub-portion and the second line portion.
  • each of the at least one first pixel circuit includes a thin film transistor; the thin film transistor includes a gate and a source and drain; and the source and drain are located in the second An electrode layer, and the gate is located on the second electrode layer.
  • the first winding part surrounds the first display area and is located in the second display area as a whole; Five-wire portion, sixth-wire portion, and seventh-wire portion; said fifth-wire portion is electrically connected with said first sub-portion, and said seventh-wire portion is electrically connected with said second sub-portion; said sixth The line portion extends in the first direction, the fifth line portion and the seventh line portion extend in a second direction crossing the first direction; the sixth line portion is connected to the first sub-portion and The virtual lines extending along the first direction between the second sub-portions are arranged side by side in the first direction; the sixth line portion and the first pixel electrically connected to the sixth line portion The circuits overlap at least partially; and in operation, the current flow in the sixth line portion is the same as the current flow in the main body portion.
  • the first winding part surrounds the first display area and is located in the second display area as a whole;
  • the eighth line part is electrically connected to the first main body part and extends along the second direction;
  • the ninth line part extends along the first direction and is connected to
  • the virtual extension lines of the first main body part are arranged side by side in the first direction; in operation, the current flow in the ninth line part is the same as the current flow in the main body part;
  • the ninth line The line portion is electrically connected to a first pixel circuit configured to drive the first number of first light-emitting elements arranged in parallel along the first direction in the first display area.
  • the second signal line further includes a fourth winding part, the fourth winding part deviates from the virtual direction of the second main body part along the second direction.
  • the second main body portion includes a third sub-portion and a fourth sub-portion separated by the first display area, and the third sub-portion and the fourth sub-portion pass through the first display area.
  • the four winding parts are electrically connected; and the fourth winding part is routed away from a virtual line extending in the second direction between the third sub-part and the fourth sub-part.
  • each of the at least one first pixel circuit includes a thin film transistor, the thin film transistor includes a gate and a source and drain; and the source and drain, the second A winding portion and the second signal line are both located on the first electrode layer, and the first main body portion and the gate are located on the second electrode layer.
  • the portion of the at least one connecting wire located in the first display area is a transparent wire.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display substrate provided by at least one embodiment of the present disclosure.
  • the display device further includes a sensor.
  • the sensor is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area.
  • the light signal of the display area is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area. The light signal of the display area.
  • FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A;
  • FIG. 1D is a schematic diagram of a part of the first display area and a part of the second display area of the display substrate shown in FIG. 1B;
  • FIG. 2A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2B is a schematic plan view of the first display area and the second display area of the display substrate shown in FIG. 2A;
  • FIG. 2C is an example of the first display area and the second display area of the display substrate shown in FIG. 2B;
  • Fig. 2D is an enlarged view of a partial area of Fig. 2C;
  • FIG. 2E is an enlarged view of a partial area of the first display area shown in FIG. 2D;
  • 2F is an enlarged view of a partial area of a third display area of the display substrate shown in FIG. 2A;
  • FIG. 4 is a first example of the display substrate shown in FIG. 2A;
  • FIG. 5A is a first schematic diagram for showing the first display area, the second display area and part of the peripheral area of the display substrate shown in FIG. 4;
  • FIG. 5D shows a schematic diagram of a stacked structure of a first light-emitting element and a first pixel circuit that drives the first light-emitting element according to at least one embodiment of the present disclosure
  • FIG. 5E shows a schematic diagram of a laminated structure of a second pixel unit provided by at least one embodiment of the present disclosure
  • FIG. 5F shows a schematic diagram of a laminated structure of a third pixel unit provided by at least one embodiment of the present disclosure
  • Fig. 5I is a schematic cross-sectional view taken along the line HH' shown in Fig. 5A;
  • FIG. 6 is a second example of the display substrate shown in FIG. 2A;
  • FIG. 7A is a first schematic diagram for showing the first display area, the second display area and part of the peripheral area of the display substrate shown in FIG. 6;
  • FIG. 7B is a second schematic diagram for showing the first display area, the second display area and a part of the peripheral area of the display substrate shown in FIG. 6;
  • FIG. 8 is a third example of the display substrate shown in FIG. 2A;
  • FIG. 9A is a first schematic diagram for showing the first display area, the second display area and part of the peripheral area of the display substrate shown in FIG. 8;
  • FIG. 10 is a fourth example of the display substrate shown in FIG. 2A;
  • FIG. 11 is a fifth example of the display substrate shown in FIG. 2A;
  • FIG. 12B is a second schematic diagram for showing the first display area, the second display area and a part of the peripheral area of the display substrate shown in FIG. 11;
  • FIG. 12C is a schematic plan view of a partial area corresponding to FIG. 12B;
  • FIG. 13A is a schematic plan view of the sixth example of the display substrate 01 shown in FIG. 2A;
  • FIG. 13B is another schematic plan view of the sixth example of the display substrate shown in FIG. 2A;
  • FIG. 13C is still another schematic plan view of the sixth example of the display substrate shown in FIG. 2A;
  • FIG. 13D is a schematic plan view corresponding to the partial area REG_B shown in FIG. 13C;
  • FIG. 15 is a schematic plan view of the eighth example of the display substrate shown in FIG. 2A;
  • Fig. 16 is another schematic plan view of the eighth example of the display substrate shown in Fig. 2A;
  • FIG. 17 is a pixel circuit provided by at least one embodiment of the present disclosure and a light-emitting element driven by the pixel electrode;
  • FIG. 18 is a schematic structural diagram of the 7T1C pixel circuit shown in FIG. 17;
  • FIG. 19 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure.
  • Fig. 24 is a schematic diagram showing the layout of the layer overlay shown in Figs. 20-23 in sub-pixels according to an embodiment of the present disclosure.
  • the inventors of the present disclosure have noticed that for current display substrates with under-screen sensors (for example, cameras), in order to increase the transmittance of the display area of the display substrates corresponding to the under-screen sensors (for example, cameras), corresponding to the screen
  • the unit area distribution density (PPI) of the light-emitting elements in the display area of the lower sensor (camera) is smaller than the unit area distribution of the light-emitting elements in other display areas of the display substrate.
  • FIG. 1A is a schematic cross-sectional view of a display substrate 500
  • FIG. 1B is a schematic plan view of the display substrate 500 shown in FIG. 1A
  • the display substrate 500 shown in FIG. 1A corresponds to the line BB' of the display substrate 10 shown in FIG. 1B
  • FIG. 1C is a schematic diagram of a partial area 513 of the display substrate 500 shown in FIG. 1B.
  • the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on the non-display side of the display substrate 500 (that is, the side away from the user). As shown in FIGS.
  • the sensing layer 520 includes a sensor 521.
  • the sensor 521 and the first display area 511 overlap in the normal direction of the display surface of the display substrate 500, and are configured to receive and process the first display area. 511 light signal.
  • the first display area 511 has multiple first pixel units 531
  • the unit area distribution density is less than the unit area distribution density of the plurality of second pixel units 532 in the second display area 512
  • the unit area distribution density of the plurality of first light-emitting elements in the first display area 511 is less than the unit area distribution density of the plurality of first light-emitting elements in the second display area 512.
  • the distribution density per unit area of the second light-emitting element is less than the unit area distribution density of the plurality of first light-emitting elements in the second display area 512.
  • the inventors of the present disclosure also noticed that although by reducing the distribution density per unit area (PPI) of the first light-emitting elements, increasing the spacing between adjacent first light-emitting elements can improve the display substrate corresponding to the under-screen to a certain extent.
  • PPI distribution density per unit area
  • the transmittance of the display area of the sensor (camera) but the improvement effect of the solution on the transmittance is still limited, and it is difficult to fully meet the user's demand for obtaining high-quality photos through the under-screen camera.
  • FIG. 1D is a schematic diagram of a part of the first display area and a part of the second display area of the display substrate 500 shown in FIG. 1B. As shown in FIG. 1D, the data line 541 passes through the first display area 511.
  • the inventor of the present disclosure also noticed that the data line 541 and the grating line 542 passing through the first display area 511 will not only block the light incident to the first display area 511 and transmitted toward the sensor 521, but may also cause diffraction, causing the sensor to output There are ghost or ghost images in the image, which further reduces the image quality of the image output by the sensor.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate includes a display area, at least one first signal line and at least one connection wire.
  • the display area includes a first display area and a second display area; the second display area at least partially surrounds the first display area; the first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit;
  • a first signal line includes a first main body part and a first winding part; the first main body part extends in a first direction, and at least a part of the first winding part extends in a direction crossing the first direction;
  • a signal line is electrically connected to at least one first pixel circuit to provide a first driving signal for the at least one first pixel circuit; at least one first pixel circuit is electrically connected to at least one first light-emitting element via corresponding connecting wires; at least One first pixel circuit is configured to drive at least one first light-emitting element, respectively.
  • FIG. 2A is a schematic plan view of a display substrate 01 provided by at least one embodiment of the present disclosure.
  • the display substrate 01 includes a display area 10 and a peripheral area 14.
  • the display area 10 includes a first display area 11, a second display area 12, and a third display area 13, and the peripheral area 14 at least partially surrounds (for example, Completely surround) the third display area 13.
  • the first display area 11, the second display area 12, and the third display area 13 do not overlap with each other.
  • the third display area 13 at least partially surrounds (eg, partially surrounds) the second display area 12.
  • the third display area 13 partially surrounds the second display area 12.
  • the display substrate 01 may not have the peripheral area 14.
  • FIG. 2B is a schematic plan view of the first display area 11 and the second display area 12 of the display substrate 01 shown in FIG. 2A.
  • the second display area 12 at least partially surrounds (for example, completely surrounds) the first display area 11.
  • FIG. 2C is an example of the first display area 11 and the second display area 12 of the display substrate 01 shown in FIG. 2B.
  • Fig. 2D is an enlarged view of a partial area REG1 of Fig. 2C.
  • FIG. 2E is an enlarged view of a partial area REG3 of the first display area 11 shown in FIG. 2D.
  • the first display area 11 includes a plurality of first light-emitting elements 411.
  • the related drawings use the anode structure 4111 of the first light-emitting element 411 to schematically show the first light-emitting element 411.
  • the first display area 11 includes a plurality of first pixel units 41 arranged in an array, and each of the plurality of first pixel units 41 includes a first number of first light-emitting elements 411, The first number of first light-emitting elements 411 are configured to emit a second number of colors of light.
  • the anode structures 4111 of different first light-emitting elements 411 in the first number of first light-emitting elements 411 have different shapes.
  • the first number of first light-emitting elements 411 has different shapes.
  • Different first light emitting elements 411 have different shapes.
  • the first number may be four, and the second number may be three, that is, each of the plurality of first pixel units 41 includes four first light-emitting elements 411, and the above four
  • the first light emitting elements 411 are configured to emit light of three colors (for example, red, green and blue).
  • each of the plurality of first pixel units 41 includes four first light-emitting elements 411 (for example, GGRB, that is, two green light-emitting elements, one red light-emitting element, and one blue light-emitting element), and the above-mentioned four light-emitting elements
  • the elements eg, GGRB are configured to emit green, green, red, and blue light, respectively.
  • each of the plurality of first pixel units 41 includes four first light-emitting elements 411
  • the arrangement of the four first light-emitting elements 411 is not limited to GGRB
  • the arrangement of the four first light-emitting elements 411 is not limited to GGRB.
  • the arrangement method can also be RGBG or other suitable arrangement methods. It should be noted that in some examples, both the first number and the second number may be three; in this case, each of the plurality of first pixel units 41 includes three first light-emitting elements 411 (for example, RGB) .
  • the second display area 12 includes a plurality of first pixel circuits 412.
  • the plurality of first pixel circuits 412 are configured to drive the plurality of first light-emitting elements 411 in a one-to-one correspondence.
  • the white rectangular boxes shown in FIGS. 2C and 2D represent first pixel driving units, and each first pixel driving unit includes a first number of pixel circuits.
  • the ratio of the number of first pixel driving units to the number of first pixel units 41 in the second display area 12 shown in FIGS. 2C and 2D is three; correspondingly, there is only one pixel driving unit in every three first pixel driving units.
  • the pixel circuit of a first pixel driving unit is used to drive the first light-emitting element 411. Therefore, the pixel circuit included in the first pixel driving unit used to drive the first light-emitting element 411 is called the first pixel circuit 412, which is useless.
  • the pixel circuit included in the first pixel driving unit that drives the first light-emitting element 411 is called a dummy pixel circuit.
  • the first pixel circuit 412 and the dummy pixel circuit have the same circuit structure.
  • the second display area 12 further includes a plurality of second pixel units 42, and each of the plurality of second pixel units 42 includes a second light-emitting element 421 (for example, a first number of second pixel units 42). Two light-emitting elements 421) and a second pixel circuit 422 for driving the second light-emitting element 421 (for example, a first number of second pixel circuits 422).
  • each of the plurality of second pixel units 42 includes a second light-emitting element 421 and a second pixel circuit 422 (that is, a rectangular frame that at least partially overlaps the second light-emitting element 421).
  • FIGS. 2C and 2D At least partially overlap in the normal direction of the display surface of the display substrate 01 (for example, a direction perpendicular to the display substrate 01).
  • a plurality of second pixel units 42 are arranged in an array.
  • the specific structure of the second pixel unit 42 will be described in the example shown in FIG. 5E, and will not be repeated here.
  • the rectangular frame shown in FIG. 2D is only used to illustrate the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 and the specific boundary of the second pixel circuit 422.
  • the first number of second light emitting elements 421 included in the second pixel unit 42 and the first number of first light emitting elements 411 included in the first pixel unit 41 have the same arrangement and structure.
  • the first number of second pixel circuits 422 included in the second pixel unit 42 and the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting element 411 have the same arrangement. And structure.
  • FIG. 2F is an enlarged view of a partial area REG2 of the third display area 13 of the display substrate 01 shown in FIG. 2A.
  • the third display area 13 includes a plurality of third pixel units 43, and each of the plurality of third pixel units 43 includes a third light-emitting element 431 (for example, a first number of third light-emitting elements 431). ) And a third pixel circuit 432 for driving the third light-emitting element 431 (for example, the first number of third pixel circuits 432).
  • the third display area 13 includes a plurality of third pixel units 43, and each of the plurality of third pixel units 43 includes a third light-emitting element 431 (for example, a first number of third light-emitting elements 431).
  • a third pixel circuit 432 for driving the third light-emitting element 431 for example, the first number of third pixel circuits 432).
  • each of the plurality of third pixel units 43 includes a third light-emitting element 431 and a third pixel circuit 432 at least partially overlapping in the normal direction of the display surface of the display substrate 01.
  • the specific structure of the third pixel unit 43 will be described in the example shown in FIG. 5F, and will not be repeated here. It should be noted that the rectangular frame shown in FIG. 2F is only used to illustrate the third pixel circuit 432, and does not indicate the specific shape of the third pixel circuit 432 and the specific boundary of the third pixel circuit 432.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the second display area 12;
  • the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the second display area 12.
  • the first display area 11 and the second display area 12 may be referred to as a low-resolution area of the display substrate 01.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is equal to the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12.
  • FIG. 3 is a schematic cross-sectional view of a display device 03 provided by at least one embodiment of the present disclosure.
  • the display device 03 includes the display substrate 01 shown in FIG. 2A.
  • the schematic cross-sectional view of the display device 03 shown in FIG. 3 corresponds to the line AA' shown in FIG. 2A.
  • the display device 03 also includes a sensor 02.
  • the display substrate 01 includes a display side and a non-display side opposite to each other, and the display substrate 01 is configured to perform a display operation on the display side of the display substrate 01, that is, the display side of the display substrate 01 is the light-emitting side of the display substrate 01 , Towards the user.
  • the display side and the non-display side face each other in the normal direction of the display surface of the display substrate 01.
  • the sensor 02 and the first display area 11 overlap in the normal direction of the display surface of the display substrate 01 (for example, the direction perpendicular to the display substrate 01), and are configured to receive and process the first display area.
  • a light signal of the display area 11, the light signal may be visible light, infrared light, or the like.
  • the first display area 11 is not provided with a pixel circuit; in this case, the transmittance of the first display area 11 can be improved.
  • the senor 02 can be an image sensor, and can be used to collect images of the external environment facing the light-collecting surface of the sensor 02, for example, it can be a CMOS image sensor or a CCD image sensor; the sensor 02 can also be an infrared sensor or a distance sensor Wait.
  • the display device 03 is a mobile terminal such as a mobile phone or a notebook
  • the sensor 02 can be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may also include, for example, a lens, a mirror, or an optical waveguide as required.
  • the sensor 02 may include photosensitive pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching transistor).
  • a photosensitive detector for example, a photodiode, a phototransistor
  • a switching transistor for example, a switching transistor
  • the photodiode can convert the light signal irradiated on it into an electrical signal
  • the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • the anode of the first light-emitting element 411 in the first display area 11 does not transmit light, that is, the wiring used to drive the first light-emitting element 411 bypasses the first display area 11 or is set to be transparent. Line; In this case, not only can the transmittance of the first display area 11 be further improved, but also the diffraction caused by various elements in the first display area 11 can be reduced.
  • An exemplary description will be given below with reference to the example shown in FIG. 4.
  • FIG. 4 is a first example of the display substrate 01 shown in FIG. 2A.
  • FIG. 5A is a first schematic diagram for showing the first display area 11, the second display area 12 and a part of the peripheral area 14 of the display substrate 01 shown in FIG. 4.
  • At least one first signal line includes multiple first signal lines, and at least one first pixel circuit includes multiple first pixel circuits; in another example, at least one first signal line includes one In another example, at least one first signal line includes a plurality of first signal lines, and at least one first pixel circuit includes a first pixel circuit. Pixel circuit.
  • the first display area 11 includes at least one first light-emitting element 411
  • the second display area 12 includes at least one first pixel circuit 412; At least one first pixel circuit 412 and at least one first light-emitting element 411 are electrically connected; at least one first pixel circuit 412 is configured to drive at least one first light-emitting element 411 in a one-to-one correspondence.
  • At least one connecting wire 60 extends from the first display area 11 to the second display area 12 along the second direction D2. It should be noted that the first number of first light emitting elements 411 included in each first pixel unit 41 and the first number of first light emitting elements 411 included in each first pixel driving unit for driving the first light emitting element 411 shown in FIG. 5A are connected.
  • the line segments between a number of first pixel circuits 412 represent a first number (for example, four) of connection traces 60.
  • the portion of at least one connecting wire 60 located in the first display area 11 is a transparent wire; in this case, not only can the transmittance of the first display area 11 and the signal noise of the image output by the sensor 02 be further improved In comparison, diffraction caused by non-transparent traces can also be avoided, thereby further improving the image quality of the image output by the sensor.
  • the transparent conductive material may be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the connection trace may include a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other.
  • the first part includes a first light-transmitting wiring layer made of a transparent conductive material
  • the second part includes a metal wiring layer made of a metal material, which will not be repeated here.
  • At least one connecting wire 60 includes a plurality of connecting wires 60
  • at least one first light-emitting element 411 includes a plurality of first light-emitting elements 411;
  • the length of one bar is greater than twice the distance between two adjacent first pixel units 41.
  • the resistances of the multiple connecting wires 60 are equal to each other, thereby improving the uniformity of the driving current (for example, when the data signals are equal to each other).
  • the lengths of the multiple connecting wires 60 are equal to each other, so that the multiple connecting wires 60 can be made of the same material.
  • the resistances are equal to each other.
  • At least one first signal line 20 includes a first main body portion 21 and a first winding portion 22; the first main body portion 21 extends along the first direction D1, and the first winding portion 22 is deviated from the virtual extension line 213 of the first main body portion 21 along the first direction D1 to be routed.
  • at least part of the first winding portion 22 extends in a direction crossing the first direction D1.
  • at least part of the first winding portion 22 extends in a direction perpendicular to the first direction D1.
  • the at least one second signal line 30 includes a second main body portion 32 extending along the second direction D2; a virtual extension of the first main body portion 21 along the first direction D1 It intersects the virtual extension line of the second body portion 32 along the second direction D2 in the first display area 11.
  • the second signal line 30 also includes a winding part (for example, a winding part surrounding the first display area 11), so that the second signal line can still be used without passing through the first display area.
  • the pixel circuits located on both sides of the first display area 11 and in the same row in the second direction D2 are driven at the same time, which will not be repeated here.
  • the first signal line and the second signal line may be closely adjacent to the pixel circuit driven by the first signal line and the second signal line but do not cross at the position of the pixel circuit, and the corresponding traces may be used to electrically connect the pixel circuit and the pixel circuit.
  • the first signal line and the second signal line may be closely adjacent to the pixel circuit driven by the first signal line and the second signal line but do not cross at the position of the pixel circuit, and the corresponding traces may be used to electrically connect the pixel circuit and the pixel circuit.
  • At least one first signal line 20 is electrically connected to at least one first pixel circuit 412 to provide a first driving signal for at least one first pixel circuit 412; at least one second signal line 30
  • the second body portion 32 is electrically connected to the at least one first pixel circuit 412 to provide the at least one first pixel circuit 412 with a second driving signal different from the first driving signal.
  • At least one first signal line 20 is electrically connected to the data driving circuit 50 to receive the first driving signal from the data driving circuit 50, that is, the first signal line 20 is a data line and the first driving signal For the data signal.
  • the first direction D1 and the second direction D2 are the column direction and the row direction of the display substrate 01, respectively;
  • the first signal line 20 and the second signal line 30 are the data line and the gate of the display substrate 01, respectively.
  • Line; the first driving signal and the second driving signal are the data signal and the gate scanning signal, respectively.
  • At least one first signal line 20 is configured to drive the first light-emitting element 411 and the third light-emitting element 431 arranged side by side along the first direction D1, that is, the same
  • the first light-emitting element 411 and the third light-emitting element 431 driven by a signal line 20 are located in the same column of the display substrate 01.
  • at least one first signal line 20 is configured to drive the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 that are arranged in parallel along the first direction D1, that is, are driven by the same first signal line.
  • the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 driven by 20 are located in the same column of the display area of the display substrate 01.
  • the display substrate further includes a third signal line (for example, a data line) and a fourth signal line (for example, a gate line).
  • the third signal line extends along the first direction D1
  • the fourth signal line extends along the second direction.
  • D2 extends; the third signal line and the fourth signal line are both straight line segments, and do not overlap with the first display area 11 (that is, do not pass through the first display area 11).
  • the first body portion 21 includes a first sub-portion 211 and a second sub-portion 212 (that is, the first sub-portion 211 and the second sub-portion 211 and the second sub-portion 211 separated by the first display area 11).
  • the parts 212 are respectively located on both sides of the first display area 11 in the first direction D1); the first sub-part 211 and the second sub-part 212 are electrically connected via the first winding part 22; the first winding part 22 is deviated from the first
  • the virtual line extending along the first direction D1 between the sub-part 211 and the second sub-part 212 that is, the virtual extension line 213 of the first main body part 21 along the first direction D1 is routed.
  • the first sub-section 211 and the second sub-section 212 are both straight line segments.
  • the first winding portion 22 by deviating the first winding portion 22 from the virtual extension line of the first main body portion 21 along the first direction D1 and routing it, it is possible to prevent the first signal line 20 from being interfered by the first signal line 20.
  • the second display area 12 has an inner edge 121 and an outer edge 122.
  • the inner edge 121 of the second display area 12 consists of a circle of pixel circuits (for example, the first pixel circuit 412 and the second pixel circuit 422) located at the innermost side of the second display area 12.
  • the boundary near the first display area 11 is formed by the inner edge 121 of the second display area 12 by a circle of pixel circuits located in the second display area 12 closest to the first display area 11, which is close to the first display area 11.
  • the border constitutes.
  • the inner edge 121 of the second display area 12 surrounds the first winding portion 22; in this case, the first winding portion 22 and the second display area 12 can be avoided
  • the pixel circuits (for example, the first pixel circuit 412 and the second pixel circuit 422) are short-circuited.
  • the inner edge 121 of the second display area 12 surrounds the first winding portion 22 and the first winding portion 22 surrounds the first display area 11.
  • the shielding of the light signal incident on the first display area 11 and transmitted toward the sensor 02 by 22 can also avoid the shielding of the light emitted by the first light-emitting element 411 located in the first display area 11 by the first winding portion 22, thereby Not only can the signal-to-noise ratio of the image output by the sensor 02 be improved and the diffraction caused by the first winding portion 22 can be avoided, but the display quality of the first display area 11 can also be improved.
  • the inner edge 121 of the second display area 12 surrounds the first winding portion 22 and the first winding portion 22 surrounds the effective boundary of the first display area 11.
  • the line 22 blocks the light signal incident into the effective boundary of the first display area 11 and transmitted toward the sensor 02, thereby improving the signal-to-noise ratio of the image output by the sensor 02 and the display quality of the first display area 11.
  • the effective boundary of the first display area 11 is formed by the outer boundary of the first light-emitting element 411 located on the outermost side of the first display area 11. In this case, it is possible to prevent the first winding portion 22 from being positioned on the second side.
  • the effective boundary of the first display area 11 is defined by a circle of first light emitting elements 411 located on the second outer side of the first display area 11 (that is, removing the first light emitting element 411 located on the outermost side of the first display area 11).
  • the first light-emitting elements 411 are at least partially overlapped, so that the wiring space of the first winding portion 22 can be increased while the effective area of the first display region 11 is slightly reduced.
  • the second line segment 222 may be located at the innermost side of the second display area 12 (that is, the side close to the first display area 11) and the second line segment 222 in the second direction D2.
  • the display substrate 01 may further include a second winding part 23.
  • at least part of the second winding portion 23 is routed in a direction crossing (for example, perpendicular to) the first direction D1.
  • the first end of the second winding part 23 is electrically connected to the second sub-part 212, and the second end of the second winding part 23 is electrically connected to the corresponding first pixel circuit 412.
  • the second end of the second winding part 23 may be in the same column as the first pixel circuit 412 (for example, the same column directly adjacent to the second line part 232 of the second winding part 23).
  • the column first pixel circuit 412) is electrically connected.
  • the second winding portion 23 includes a first wire portion 231 and a second wire portion 232 that are sequentially connected; the end of the first wire portion 231 that is not connected to the second wire portion 232 serves as The first end of the second winding portion 23; the end of the second wire portion 232 that is not connected to the first wire portion 231 serves as the second end of the second winding portion 23; the first wire portion 231 extends in the second direction D2; The second line portion 232 extends along the first direction D1 and is arranged side by side with the second sub-portion 212 in the second direction D2.
  • the second line portion 232 is a straight line segment.
  • the first line portion 231 may be a straight line segment.
  • the first line portion 231 may have a bent structure and extend along the second direction D2 as a whole.
  • the same first signal line 20 can be used to connect the first light-emitting element 411 and the third light-emitting element 431 located in the same column in different columns.
  • the data signal provided by the data driving circuit 50 can directly correspond to the position of the light-emitting element, so there is no need to change the algorithm for providing the data signal and the setting of the data driving circuit 50.
  • the data line of the winding part is provided with a data driving circuit separately, thereby reducing the calculation amount of the data driving circuit 50 or related controllers and processors.
  • the first signal line 20 includes the second winding portion 23, it is not necessary to connect the first signal line for supplying data signals to the first pixel circuit configured to drive the first light-emitting element from the first light-emitting element.
  • the first signal line in the same column (the part of the first signal line in the third display area is in the same column as the first light-emitting element) is adjusted to the first signal line in the same column as the first pixel circuit (the first signal line)
  • the part of a signal line located in the third display area is located in the same column as that of the first pixel circuit).
  • the current flow in the second wire portion 232 is opposite to the current flow in the main body portion.
  • the current flow in the first main body portion 21 flows from the lower side of the display substrate 01 (the side where the data drive circuit 50 is provided) to the upper side of the display substrate 01, and the current flow in the second line portion 232 is caused by the display
  • the upper side of the substrate 01 flows to the lower side of the display substrate 01.
  • FIG. 5B is a second schematic diagram for showing the first display area 11, the second display area 12 and a part of the peripheral area 14 of the display substrate 01 shown in FIG. 4, and FIG. 5C is for showing the display shown in FIG. 4
  • Fig. 5B is the upper part of Fig. 5C.
  • FIG. 5C is similar to FIG. 5A.
  • the difference between FIG. 5C and FIG. 5A is that FIG. 5C shows more first light-emitting elements 411, connecting wires 60, first pixel circuits 412, first signal lines 20, and second light-emitting elements. 421 and the second pixel circuit 422, and FIG. 5C also shows a fifth signal line 71 (for example, a data line) electrically connected to the second pixel circuit 422.
  • a fifth signal line 71 for example, a data line
  • the fifth signal line 71 also has a winding portion.
  • the fifth signal line 71 also has an effective boundary where the winding part surrounds the first display area 11, and the inner edge of the second display area 12 surrounds the winding part of the fifth signal line 71.
  • the display substrate 01 includes a plurality of first signal lines 20, and the plurality of first line portions 231 included in the plurality of first signal lines 20 are arranged side by side in the first direction D1 (that is, , At least partially overlap in the first direction D1).
  • the lengths of the plurality of first line portions 231 included in the plurality of first signal lines 20 in the second direction D2 are equal to each other, so that the upper portion of the first line portion 231 can be further lifted.
  • the uniformity of the driving current (for example, in the case where the data signals are equal to each other).
  • the first body portion 21, the first winding portion 22, and the second wire portion 232 are located on the first electrode layer of the display substrate 01; the first wire portion 231 is located on the second electrode layer of the display substrate 01; the first electrode layer and the second electrode layer The two electrode layers are stacked in the normal direction of the display surface of the display substrate 01; the first line portion 231 respectively passes through the first via hole and the second via hole of the insulating layer located between the first electrode layer and the second electrode layer It is electrically connected to the second sub-portion 212 and the second line portion 232.
  • first wire portion 231 of the second winding portion 23 of each first signal wire 20 and other parts of each first signal wire 20 for example, the second wire portion 232 and the second sub-portion 212
  • both the first electrode layer and the second electrode layer are made of metal materials.
  • the metal material may be selected from silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), aluminum alloy or other suitable materials.
  • the specific structures of the first light-emitting element 411, the first pixel circuit 412, the second pixel unit 42 and the third pixel unit 43 and the relationship between the various parts of the first signal line 20 and the pixel circuit will be exemplarily described below with reference to FIGS. 5D-5G.
  • FIG. 5D shows a schematic diagram of the stacked structure of the first light-emitting element 411 and the first pixel circuit 412 driving the first light-emitting element 411 provided by at least one embodiment of the present disclosure.
  • the first pixel circuit 412 includes structures such as a thin film transistor 412T and a storage capacitor 412C.
  • the first light emitting element 411 includes a first anode structure 4111, a first cathode structure 4113, and a first light emitting layer 4112 between the first anode structure 4111 and the first cathode structure 4113.
  • the first anode structure 4111 communicates with the first pixel through the via hole.
  • the thin film transistor 412T included in the circuit 412 is electrically connected.
  • the first anode structure 4111 may include a plurality of anode sub-layers, such as a three-layer structure of ITO/Ag/ITO (not marked in the figure), etc.
  • the specific form of the first anode structure 4111 is not limited in the embodiment of the present disclosure.
  • the first cathode structure 4113 may be a structure formed on the entire surface of the display substrate 01.
  • the first cathode structure 4113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the first cathode structure 4113 can be formed as a very thin layer, the first cathode structure 4113 has good light transmittance.
  • the thin film transistor 412T includes an active layer 4121, a gate 4122, and source and drain electrodes (ie, a source 4123 and a drain 4124), and the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126.
  • the active layer 4121 is provided on the base substrate 74, the side of the active layer 4121 away from the base substrate 74 is provided with a first gate insulating layer 741, the gate 4122 and the first capacitor plate 4125 are provided in the same layer, And on the side of the first gate insulating layer 741 away from the base substrate 74, the gate 4122 and the first capacitor plate 4125 are provided with a second gate insulating layer 742 on the side away from the base substrate 74, and the second capacitor The plate 4126 is arranged on the side of the second gate insulating layer 742 away from the base substrate 74, the side of the second capacitor plate 4126 away from the base substrate 74 is provided with an interlayer insulating layer 743, and the source and drain electrodes are arranged between the layers.
  • the side of the insulating layer 743 away from the base substrate 74 is electrically connected to the active layer 4121 through the via holes in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743.
  • the source and drain electrodes A planarization layer 744 is provided on the side away from the base substrate 74 to planarize the first pixel circuit 412.
  • the planarization layer 744 has a via hole, and the first anode structure 4111 is electrically connected to the source 4123 or the drain 4124 of the thin film transistor 412T through the via in the planarization layer 744.
  • FIG. 5E shows a schematic diagram of a laminated structure of a second pixel unit 42 provided by at least one embodiment of the present disclosure.
  • the second pixel unit 42 includes a second light-emitting element 421 and drives the second light-emitting element 421 of the second pixel circuit 422.
  • the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C.
  • the second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 between the second anode structure 4211 and the second cathode structure 4213.
  • the second anode structure 4211 communicates with the second anode structure 4211 through the via hole 744A.
  • the thin film transistor 422T included in the pixel circuit 422 is electrically connected.
  • the second anode structure 4211 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the second anode structure 4211 is not made in the embodiment of the present disclosure. limited.
  • the thin film transistor 422T includes an active layer 4221, a gate 4222, and source and drain electrodes (ie, a source 4223 and a drain 4224), and the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226.
  • the active layer 4221 is provided on the base substrate 74, the side of the active layer 4221 away from the base substrate 74 is provided with a first gate insulating layer 741, the gate 4222 and the first capacitor plate 4225 are in the same layer, and The second gate insulating layer 742 is provided on the side of the first gate insulating layer 741 away from the base substrate 74.
  • the gate 4222 and the first capacitor plate 4225 are provided on the side away from the base substrate 74 with a second gate insulating layer 742.
  • the plate 4226 is arranged on the side of the second gate insulating layer 742 away from the base substrate 74, the side of the second capacitor plate 4226 away from the base substrate 74 is provided with an interlayer insulating layer 743, and the source and drain electrodes are arranged between the layers.
  • the side of the insulating layer 743 away from the base substrate 74 is electrically connected to the active layer 4221 through the via holes in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743.
  • the source and drain electrodes A planarization layer 744 is provided on the side away from the base substrate 74 to planarize the second pixel circuit 422.
  • the planarization layer 744 has a via 744A, and the second anode structure 4211 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via 744A in the planarization layer 744.
  • FIG. 5E only shows one second light-emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42, and only shows one thin film transistor included in the second pixel circuit 422. 422T and a storage capacitor 422C, but the embodiment of the present disclosure is not limited thereto.
  • FIG. 5F shows a schematic diagram of a stacked structure of a third pixel unit 43 provided by at least one embodiment of the present disclosure.
  • each third sub-pixel includes a third light-emitting element 431 and a third pixel unit 43.
  • a third pixel circuit 432 electrically connected to the three light-emitting elements, and the third pixel circuit 432 is configured to drive the third light-emitting element 431.
  • the third light-emitting element 431 includes a third anode structure 4311, a third cathode structure 4313, and a third light-emitting layer 4312 between the third anode structure 4311 and the third cathode structure 4313.
  • the third anode structure 4311 communicates with the third pixel through the via hole.
  • the circuit 432 is electrically connected.
  • the third anode structure 4311 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the third anode structure 4311 is not made in the embodiment of the present disclosure. limited.
  • the third pixel circuit 432 includes structures such as a thin film transistor 432T and a storage capacitor 432C.
  • the thin film transistor 432T includes an active layer 4321, a gate 4322, and source and drain electrodes (ie, a source 4323 and a drain 4324), and the storage capacitor 432C includes a first capacitor plate 4325 and a second capacitor plate 4326.
  • the active layer 4321 is provided on the base substrate 74, the side of the active layer 4321 away from the base substrate 74 is provided with a first gate insulating layer 741, the gate 4322 and the first capacitor plate 4325 are in the same layer, and Is provided on the side of the first gate insulating layer 741 away from the base substrate 74, the gate 4322 and the first capacitor plate 4325 are provided on the side away from the base substrate 74 with a second gate insulating layer 742, and the second capacitor
  • the plate 4326 is arranged on the side of the second gate insulating layer 742 away from the base substrate 74, the side of the second capacitor plate 4326 away from the base substrate 74 is provided with an interlayer insulating layer 743, and the source and drain electrodes are arranged between the layers.
  • the side of the insulating layer 743 away from the base substrate 74 is electrically connected to the active layer 4321 through the via holes in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743.
  • a planarization layer 744 is provided on the side away from the base substrate 74 to planarize the third pixel circuit 432.
  • the planarization layer 744 has a via 744B, and the third anode structure 4311 is electrically connected to the source 4323 or the drain 4324 of the thin film transistor 432T through the via 744B in the insulating layer 745.
  • FIG. 5F only shows one third light-emitting element 431 and one third pixel circuit 432 included in the third pixel unit 43, and only shows one thin film transistor included in the third pixel circuit 432. 432T and a storage capacitor 432C, but the embodiment of the present disclosure is not limited thereto.
  • the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 are arranged in the same layer, so the same patterning process can be used in the manufacturing process.
  • the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, and the planarization layer 744 are arranged in the same layer in the first display area 11, the second display area 12, and the third display area 13. In some embodiments, they are still integrally connected (that is, integrally formed and connected to each other), so the same reference numerals are used in the drawings.
  • the display substrate further includes structures such as a pixel defining layer 746 and an encapsulation layer 747.
  • the pixel defining layer 746 is disposed on the first anode structure and includes a plurality of openings to define different pixels or sub-pixels.
  • the first light-emitting layer is formed in the opening of the pixel defining layer 746.
  • the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, for example, the multilayer encapsulation structure includes a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate.
  • the pixel defining layers 746 in the first display area 11, the second display area 12, and the third display area 13 are arranged in the same layer, and the pixel defining layers 746 in the first display area 11, the second display area 12 and the third display area 13 are
  • the encapsulation layer 747 is arranged in the same layer, and in some embodiments, it is still integrally connected, so the same reference numerals are used in the drawings.
  • the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate, etc., and may be a rigid substrate or a flexible substrate.
  • the embodiments of the present disclosure do not limit this.
  • the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743 and the planarization layer 744, the insulating layer 745, the pixel defining layer 746, the encapsulation layer 747, and the insulating layer 748 may include silicon oxide, Inorganic insulating materials such as silicon nitride and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the material of the active layer 4121/4221/4321 may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 4121/4221/4321 can be made into a conductor through conduction treatment such as doping, so as to have higher conductivity.
  • the materials of the gate 4122/4222/4322, the first capacitor plate 4125/4225/4325 and the second capacitor plate 4126/4226/4326 may include metal materials or alloy materials, such as molybdenum. , Aluminum and Titanium, etc.
  • the material of the source electrode 4123/4223/4323 and the drain electrode 4124/4224/4324 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer The structure is a multi-metal laminated layer, such as a three-layer metal laminated layer (Ti/Al/T i) of titanium, aluminum, and titanium.
  • a metal material or an alloy material such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer The structure is a multi-metal laminated layer, such as a three-layer metal laminated layer (Ti/Al/T i) of titanium, aluminum, and titanium.
  • the display substrate provided by the embodiment of the present disclosure may be a display substrate such as an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light-emitting layer 411/4211/4311 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light or green light. Light, blue light, or white light, etc.
  • the light-emitting layer 411/4211/4311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer 411/4211/4311 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots Dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • 5G is a schematic diagram of the laminated structure of the second pixel unit 42, the first wire portion 231 of the second winding portion 23, and the second sub-portion 212 of the first main body portion 21 provided by at least one embodiment of the present disclosure.
  • the second sub-portion 212, the source electrode 4223, and the drain electrode 4224 of the first body portion 21 are located on the first electrode layer 251 of the display substrate 01, for example, the first sub-portion of the first body portion 21 211.
  • the second wire portion 232 of the first winding portion 22 and the second winding portion 23 is also located on the first electrode layer 251.
  • FIG. 5G is a schematic diagram of the laminated structure of the second pixel unit 42, the first wire portion 231 of the second winding portion 23, and the second sub-portion 212 of the first main body portion 21 provided by at least one embodiment of the present disclosure.
  • the second sub-portion 212, the source electrode 4223, and the drain electrode 4224 of the first body portion 21 are located on the first electrode layer 251 of the display
  • the first wire portion 231 of the second winding portion 23, the gate 4222, and the first capacitor plate 4225 are located on the second electrode layer 252 of the display substrate 01.
  • the first line portion 231 passes through the first via hole 254 and the second via hole 255 and the second sub portion 212 of the insulating layer located between the first electrode layer 251 and the second electrode layer 252, respectively. It is electrically connected to the second line portion 232, that is, the first signal line 20 adopts a jumper design, for example, a design including multiple jumpers may be adopted.
  • the first wire portion 231 and the second capacitor plate 4226 of the second winding portion 23 are located on the second electrode layer 252 of the display substrate 01, which will not be repeated here.
  • the second main body portion 32 of the second signal line 30 is also located on the second electrode layer 252 of the display substrate 01.
  • FIG. 5H shows a schematic diagram of another laminated structure of a second pixel unit 42 provided by at least one embodiment of the present disclosure.
  • the second pixel unit 42 includes a second light-emitting element 421 and a driving second pixel unit 42.
  • the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C.
  • the second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 between the second anode structure 4211 and the second cathode structure 4213.
  • the second anode structure 4211 is connected to the through hole 744A.
  • the electrode 749 is electrically connected, and the transfer electrode 749 is electrically connected to the thin film transistor 422T included in the second pixel circuit 422 via the via 744B.
  • the second anode structure 4211 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the second anode structure 4211 is not made in the embodiment of the present disclosure. limited.
  • the transfer electrode 749 may be made of a transparent conductive material.
  • the transparent conductive material may be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the thin film transistor 422T includes an active layer 4221, a gate 4222, and source and drain electrodes (ie, a source 4223 and a drain 4224), and the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226.
  • the active layer 4221 is provided on the base substrate 74, the side of the active layer 4221 away from the base substrate 74 is provided with a first gate insulating layer 741, the gate 4222 and the first capacitor plate 4225 are in the same layer, and The second gate insulating layer 742 is provided on the side of the first gate insulating layer 741 away from the base substrate 74.
  • the gate 4222 and the first capacitor plate 4225 are provided on the side away from the base substrate 74 with a second gate insulating layer 742.
  • the plate 4226 is arranged on the side of the second gate insulating layer 742 away from the base substrate 74, the side of the second capacitor plate 4226 away from the base substrate 74 is provided with an interlayer insulating layer 743, and the source and drain electrodes are arranged between the layers.
  • the side of the insulating layer 743 away from the base substrate 74 is electrically connected to the active layer 4221 through the via holes in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743; source and drain electrodes
  • the side of the passivation layer 748 away from the base substrate 74 is provided with a passivation layer 748; the side of the passivation layer 748 away from the base substrate 74 is provided with a first planarization layer 744 to planarize the second pixel circuit 422; 749 is disposed on a side of the first planarization layer 7441 away from the base substrate 74; a second planarization layer 7442 is disposed on the side of the transfer electrode 749 away from the base substrate 74.
  • the first planarization layer 7441 has a via 744B, and the transfer electrode 749 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via 744B in the first planarization layer 7441.
  • the planarization layer 744 has a via 744A, and the second anode structure 4211 is electrically connected to the transfer electrode 749 through the via 744A in the second planarization layer 7442, so that the second anode structure 4211 can be connected to the source of the thin film transistor 422T.
  • the pole 4223 or the drain 4224 is electrically connected.
  • the display substrate further includes a pixel defining layer 746, an encapsulation layer 747 and other structures.
  • the pixel defining layer 746 is disposed on the first anode structure and includes a plurality of openings to define different pixels or sub-pixels.
  • the first light-emitting layer is formed in the opening of the pixel defining layer 746.
  • the encapsulation layer 747 may include a first encapsulation layer 7471, a second encapsulation layer 7472, and a third encapsulation layer 7473 that are sequentially disposed on the second cathode structure 4213 in a direction perpendicular to the display substrate.
  • the first encapsulation layer 7471, the second encapsulation layer 7472, and the third encapsulation layer 7473 are an inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer, respectively.
  • FIG. 5H only shows one second light-emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42, and only shows one thin film transistor included in the second pixel circuit 422. 422T and a storage capacitor 422C, but the embodiment of the present disclosure is not limited thereto.
  • the third pixel unit 43 provided by at least one embodiment of the present disclosure and at least The first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 provided in an embodiment may also adopt the structure shown in FIG. 5H, which will not be repeated here.
  • Fig. 5I is a schematic cross-sectional view taken along the line HH' shown in Fig. 5A.
  • the second sub-portion 212 of the first main body portion 21 and the second wire portion 232 of the second winding portion 23 are located on the side of the interlayer insulating layer 743 away from the base substrate 74, that is, The second sub-portion 212 of the first body portion 21 and the second wire portion 232 of the second winding portion 23 and the source and drain electrodes of the thin film transistor (for example, the source 4223 and the drain 4224) are arranged on the same electrode layer (for example, the first An electrode layer 251).
  • the first sub-portion 211 of the first body portion 21 and the first winding portion 22 are also located on the same electrode layer (for example, the first electrode layer 251) described above.
  • the first wire portion 231 of the second winding portion 23 is located between the first gate insulating layer 741 and the second gate insulating layer 742, that is, the first wire portion of the second winding portion 23
  • the portion 231, the gate 4222, and the first capacitor plate 4225 are located on the same electrode layer (for example, located on the second electrode layer 252 of the display substrate 01).
  • the first line portion 231 passes through the first via hole 254 and the second via hole 255 and the second sub portion 212 of the insulating layer located between the first electrode layer 251 and the second electrode layer 252, respectively.
  • the first signal line 20 adopts a jumper design, for example, a design including multiple jumpers may be adopted.
  • the second body portion 32 of the second signal line 30 is also located on the second electrode layer 252 of the display substrate 01.
  • the first wire portion 231 of the second winding portion 23 and the second capacitor plate 4226 are located on the same electrode layer (for example, the second electrode layer 252 of the display substrate 01), and the gate 4222 is not located on the same electrode. Layer (for example, the second electrode layer 252 of the display substrate 01).
  • the first line portion 231 is located in the peripheral area 14 as a whole, and is arranged side by side with the second display area 12 in the first direction D1.
  • the peripheral region 14 does not have pixel circuits (the first pixel circuit 412 to the third pixel circuit 432), the wiring difficulty of the first line portion 231 can be reduced.
  • the first line portion 231 is located on the side of the second display area 12 away from the third display area 13 in the first direction D1 as a whole.
  • the entire first line portion 231 is located on the upper edge of the display substrate 01.
  • first line portion 231 shown in FIGS. 4, 5A-5C, and 5G is located in the peripheral area 14 as a whole, the embodiment of the present disclosure is not limited to this. According to actual application requirements, the first line portion The 231 may also be located in the second display area 12 as a whole or the first line portion 231 may be located in the peripheral area 14 and the second display area 12 at the same time. Exemplary description will be given below in conjunction with Fig. 6, Fig. 7A-7B, Fig. 8 and Fig. 9A-9B.
  • FIG. 6 is a second example of the display substrate 01 shown in FIG. 2A.
  • FIG. 7A is a first schematic diagram showing the first display area 11, the second display area 12, and a part of the peripheral area 14 of the display substrate 01 shown in FIG. 6, and
  • FIG. 7B is a first schematic diagram showing the display shown in FIG. A second schematic diagram of the first display area 11, the second display area 12, and a part of the peripheral area 14 of the substrate 01.
  • the first line portion 231 is located in the second display area 12 as a whole, and is arranged side by side with the first display area 11 in the first direction D1.
  • the first line portion 231 is located on the side of the first display area 11 away from the third display area 13 in the first direction D1.
  • the plurality of first line portions 231 included in the plurality of first signal lines 20 are all straight (that is, straight line segments).
  • at least part of the first line portion 231 included in the plurality of first signal lines 20 may have a bent structure, so as to avoid overlapping of part of the first line portion 231 with the second light-emitting element 421 and shield the second light-emitting element. 421 emitted light.
  • the size of the peripheral area 14 of the display substrate 01 can be reduced, thereby facilitating the narrow bezel or full-screen design of the display substrate 01.
  • first light-emitting element 411 and the second light-emitting element 421 are farther away from the base substrate of the display substrate 01 than the connecting wires 60; the schematic plan view shown in FIG. 7A and other related schematic plan views are used for illustration. Shows the arrangement and connection of the various elements of the display substrate 01 in the plane parallel to the base substrate of the display substrate 01, and is not used to restrict the various elements of the display substrate 01 in the direction perpendicular to the base substrate of the display substrate 01 The arrangement or relative position relationship on the top. The arrangement and relative positional relationship of the various elements of the display substrate 01 in a direction perpendicular to the base substrate of the display substrate 01 can be seen in the schematic diagrams of the laminated structure shown in FIGS. 5D-5H and the schematic cross-sectional diagram shown in FIG. 5I. I won't repeat them here.
  • FIG. 8 is a third example of the display substrate 01 shown in FIG. 2A.
  • 9A is a first schematic diagram showing the first display area 11, the second display area 12, and a part of the peripheral area 14 of the display substrate 01 shown in FIG. 8, and
  • FIG. 9B is a first schematic diagram showing the display shown in FIG. A second schematic diagram of the first display area 11, the second display area 12, and a part of the peripheral area 14 of the substrate 01.
  • the first line portion 231 includes a first portion 2311, a second portion 2312, and a third portion 2313 that are sequentially connected; the first portion 2311 and the third portion 2311 of the first line portion 231
  • the two sub-parts 212 are electrically connected, and the third part 2313 of the first line part 231 is electrically connected to the second line part 232; the first part 2311 of the first line part 231 is located in the peripheral area 14 and is connected to the second display in the first direction D1
  • the areas 12 are arranged side by side; the second portion 2312 of the first line portion 231 extends from the peripheral area 14 along the first direction D1 to the second display area 12; the third portion 2313 of the first line portion 231 is located in the second display area 12, and
  • the virtual extension line of the third portion 2313 of the first line portion 231 extending in the second direction D2 is arranged side by side with the first display area 11 in the first direction D1.
  • the third portion 2313 of the first wire portion 231 is electrically connected to the second sub-portion 212, and the first portion 2311 of the first wire portion 231 is electrically connected to the second wire portion 232, that is, the first wire portion 231 is electrically connected to
  • the electrical connection portion of the second sub-portion 212 is located in the second display area 12, and the electrical connection portion of the first line portion 231 and the second line portion 232 is located in the peripheral area 14, which will not be repeated here.
  • the second winding portion 23 of the display substrate 01 shown in FIGS. 4, 6 and 8 is all separated from the side of the third display area 13 in the first direction D1 via the first display area 11
  • the second sub-portion 212 of the first main body portion 21 is wound to a position parallel to the second sub-portion 212 of the first main body portion 21 (in the second direction D2), but the embodiment of the present disclosure is not limited thereto.
  • the second winding part 23 may be wound from the first sub-part 211 of the first body part 21 via the first display area 11 in the first direction D1 on the side close to the third display area 13 to the second A position where the second sub-parts 212 of the main body 21 are juxtaposed (in the second direction D2) is exemplified below with reference to FIG. 10.
  • FIG. 10 is a fourth example of the display substrate 01 shown in FIG. 2A.
  • the display substrate 01 shown in FIG. 10 is similar to the display substrate 01 shown in FIG. 6, and only the differences between the two are described here, and the similarities will not be repeated.
  • the difference between the display substrate 01 shown in FIG. 10 and the display substrate 01 shown in FIG. 6 is that the first line portion 231 of the display substrate 01 shown in FIG. Three sides of the display area 13, and, in operation, the current flow in the second line portion 232 of the display substrate 01 shown in FIG. 10 is the same as the current flow in the main body portion.
  • At least a part (for example, all) of the first line portion 231 may be arranged side by side with the first display area 11, and located in the third display area 13 close to the first display area 11.
  • first signal lines 20 of the display substrate 01 shown in FIGS. 4, 6, 8 and 10 are all routed from one side of the first display area 11 in the first direction D1 to and At a position where the first body parts 21 are juxtaposed (in the second direction D2), however, the embodiment of the present disclosure is not limited to this. In some examples, the first signal line 20 of the display substrate 01 may be routed from both sides of the first display area 11 in the first direction D1 to be juxtaposed with the first body portion 21 (in the second direction D2) Location. An exemplary description will be given below with reference to FIGS. 11 and 12A-12C.
  • FIG. 11 is a fifth example of the display substrate 01 shown in FIG. 2A.
  • 12A is a first schematic diagram showing the first display area 11, the second display area 12, and a part of the peripheral area 14 of the display substrate 01 shown in FIG. 11, and
  • FIG. 12B is a first schematic diagram showing the display shown in FIG. 11 A second schematic diagram of the first display area 11, the second display area 12 and a part of the peripheral area 14 of the substrate 01;
  • FIG. 12C is a schematic plan view of the partial area REG_E corresponding to FIG. 12B.
  • the display substrate 01 shown in FIG. 11 is similar to the display substrate 01 shown in FIG. 4, and only the differences between the two are described here, and the similarities will not be repeated.
  • the difference between the display substrate 01 shown in FIG. 11 and the display substrate 01 shown in FIG. 4 is that the display substrate 01 further includes a third winding portion 24.
  • the third winding portion 24 runs in a direction crossing (for example, perpendicular to) the first direction D1.
  • the first end of the third winding part 24 is electrically connected to the first sub-part 211, and the second end of the third winding part 24 is connected to the corresponding first pixel circuit. 412 is electrically connected, and the first pixel circuit 412 connected to the second winding portion 23 is different from the first pixel circuit 412 connected to the third winding portion 24.
  • the first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are located in the same column, that is, The first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are arranged in the first direction D1.
  • the first pixel circuit 412 connected to the second winding portion 23 is the first pixel circuit 412 in the upper column of the first pixel circuit 412 in the same column
  • the first pixel circuit 412 connected to the second winding portion 23 is The first pixel circuit 412 in the lower half column of the first pixel circuit 412 in the same column described above.
  • the first signal line 20 further include the third winding portion 24, it is possible to use the data line to pair the pixel circuits in the second display area 12 and the first display area 11 in the second direction D2.
  • a pixel circuit 412 and a second pixel circuit 422) perform bidirectional driving, that is, from the upper and lower directions of the second display area 12 and the first display area 11 in the second direction D2.
  • the pixel circuit inputs a data signal; in this case, the size of the opening of the second display area 12 (for example, the inner edge 121 of the second display area 12) is larger.
  • the third winding portion 24 includes a third wire portion 241 and a fourth wire portion 242 that are sequentially connected; the third wire portion 241 is not connected to the fourth wire portion 242 One end is used as the first end of the third winding portion 24, and the end of the fourth wire portion 242 that is not connected to the third wire portion 241 is used as the second end of the third winding portion 24; the third wire portion 241 extends in the second direction D2 , And arranged side by side with the first line portion 231 in the first direction D1; the fourth line portion 242 extends along the first direction D1 and is arranged side by side with the first sub-portion 211 in the second direction D2; in operation, the fourth line
  • the current flow in the wire portion 242 is the same as the current flow in the main body portion.
  • the fourth line portion 242 is a straight line segment.
  • the third line portion 241 may be a straight line segment.
  • the third line portion 241 may have
  • the fourth line portion 242 is located on the first electrode layer of the display substrate 01; the third line portion 241 is located on the second electrode layer of the display substrate 01; the third line portion 241 is located between the first electrode layer and the second electrode layer.
  • the third via hole and the fourth via hole of the insulating layer are electrically connected to the first sub-portion 211 and the fourth line portion 242.
  • first wire portion 231 of the second winding portion 23 of each first signal line 20 and the third wire portion 241 of the third winding portion 24 and other parts of each first signal line 20 can prevent the first wire portion 231 of the second winding portion 23 and the third wire portion 241 of the third winding portion 24 of each first signal line 20 from being in contact with other A signal line 20 is short-circuited.
  • the first display area 11 only includes a plurality of transparent wires and anode structures 4111 arranged side by side, so that the transmittance of the first display area 11 can be improved.
  • a plurality of transparent wiring lines arranged in parallel includes a connecting wiring 60 and a dummy wiring 601.
  • the virtual wiring 601 has a break, thereby making the virtual wiring 601 a discontinuous wiring.
  • the etching uniformity of the first display area 11 can be improved.
  • the line pointed by the arrow in FIG. 12C is a shading, not a real trace.
  • the first line portion 231 of the display substrate shown in FIGS. 11 and 12A-12B is not limited to being located in the peripheral area 14; the third line portion 241 is not limited to being aligned with the first display area 11 in the first direction D1 It is arranged and located at one end of the third display area 13 close to the first display area 11.
  • the first line portion 231 and the third line portion 241 may both be located in the second display area 12, and the first line portion 231 is located in the first direction D1 away from the third display area 13 of the first display area 11.
  • the third line portion 241 is located between the first display area 11 and the third display area 13 in the first direction D1.
  • the first line portion 231 may be located in the peripheral area 14 and the second display area 12 at the same time, and the third line portion 241 may be located in the third display area 13 and the second display area 12 at the same time.
  • the shapes of the first display area 11 of the display substrate 01 shown in FIGS. 4, 6, 8, 10, and 11 are all rectangular, the embodiment of the present disclosure is not limited to this.
  • the shape of the first display area 11 may also be a circle or other applicable shapes; correspondingly, the shape of the first winding portion 22 is adaptively changed.
  • the shape of the first winding portion 22 matches the shape of the first display area 11 to reduce the influence of the first winding portion 22 on the elements located in the first display area 11 and the second display area 12. An exemplary description will be given below with reference to FIGS. 13A to 13D.
  • FIG. 13A is a schematic plan view of the sixth example of the display substrate 01 shown in FIG. 2A
  • FIG. 13B is another schematic plan view of the sixth example of the display substrate 01 shown in FIG. 2A
  • FIG. 13C is FIG. 2A
  • the shown sixth example of the display substrate 01 is still another schematic plan view.
  • FIG. 13D is a schematic plan view corresponding to the partial area REG_B shown in FIG. 13C.
  • FIG. 13A only shows a part of the second display area 12 and a part of the peripheral area 14 of the display substrate 01
  • FIG. 13B and FIG. 13C only show a part of the first display area 11 of the display substrate 01 , Part of the second display area 12 and part of the peripheral area 14.
  • the display substrate 01 shown in FIGS. 13A to 13C is similar to the display substrate 01 shown in FIGS. 4 and 5A to 5C, and only the differences between the two are described here, and the similarities are not repeated here.
  • the difference between the display substrate 01 shown in FIGS. 13A-13C and the display substrate 01 shown in FIGS. 4 and 5A-5C lies in the shape of the first display area 11 of the display substrate 01 shown in FIGS. 13A-13C and The shape of the first winding portion 22 is different.
  • the shape of the first display area 11 is a circle; the first winding portion 22 is an arc, and the first end of the arc is close to the first sub-portion 211 near the second sub-portion 212 The ends are connected, and the second end of the arc is connected to the end of the second sub-part 212 close to the first sub-part 211.
  • the curvature of the above-mentioned arc and the curvature of the above-mentioned circle match each other (e.g., are equal).
  • the peripheral area 14 further includes a plurality of wires 2911 and a plurality of wires 2921; the plurality of wires 2911 are located on the electrode layer 291, and the multiple wires 2921 are located on the electrode layer 292.
  • the electrode layer 291 and the electrode layer 292 are different electrode layers in a direction perpendicular to the display substrate.
  • the multiple wires 2911 and the multiple wires 2921 are alternately arranged in a direction perpendicular to the extending direction of the wires 2911.
  • the wires 2911 and the multiple wires 2921 are alternately arranged in a direction perpendicular to the extending direction of the wires 2911, and making the wires 2911 and the wires 2921 be located on different electrode layers, the wires ( The layout density of the trace 2911 and trace 2921 as a whole).
  • the second sub-portion 212 of the first signal line 20 and the multiple traces 2911 are located on different electrode layers, and the second sub-portion 212 of the first signal line 20 and the multiple traces 2921 are located on different electrode layers.
  • the gate 4222 and the first capacitor plate 4225 shown in FIG. 5H are also located on the electrode layer 291; the second capacitor plate 4226 shown in FIG. 5H is also located on the electrode layer 292; the second sub-portion of the first signal line 20 212 is located on the same electrode layer as the source 4223 and the drain 4224 shown in FIG. 5H.
  • the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 is electrically connected to the corresponding trace 2911 or the corresponding trace 2921 (for example, via a via Electrical connection), as a result, the signal on the second sub-portion 212 of the first signal line 20 is transferred to the corresponding wiring 2911 or the corresponding wiring 2921 for transmission.
  • the trace 2911 or the trace 2921 electrically connected to the second sub-portion 212 of the first signal line 20 is referred to as the first line portion 231.
  • the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 is electrically connected to the corresponding wiring 2911 or the corresponding wiring 2921.
  • the first signal line (located in the SD layer) from each pixel unit will be changed to the Gat1 (electrode layer 291) or Gat2 layer (electrode layer 292).
  • the leads in the longitudinal direction and the leads in the lateral direction cross, the leads in the longitudinal direction (the second sub-portion 212 of the first signal line 20) adopt the SD layer, because the SD layer and the Gat layer (electrode layer 291 or The distance between 292) will be greater than the distance between the Gat1 (electrode layer 291) and the Gat2 layer (electrode layer 292), thereby reducing capacitive coupling.
  • the shapes of the second display area 12 of the display substrate 01 shown in FIGS. 4, 6, 8, 10, 11, and 13A-13C are all rectangular, the embodiments of the present disclosure Not limited to this.
  • the shape of the second display area 12 may also be a circle or other applicable shapes, which will not be repeated here.
  • first signal line 20 of the display substrate 01 shown in FIG. 4, FIG. 6, FIG. 8, FIG. 10, FIG. 11, and FIG. 13A-13C uses two or more winding portions
  • the first signal line 20 is wound to a position parallel to the first main body portion 21 (in parallel in the second direction D2), but the embodiment of the present disclosure is not limited to this.
  • the first signal line 20 of the display substrate 01 may only use one winding part to wind the first signal line 20 to a position parallel to the first body part 21 (parallel in the second direction D2)
  • an exemplary description will be given with reference to FIG. 14.
  • FIG. 14 is a schematic plan view of a seventh example of the display substrate 01 shown in FIG. 2A.
  • the display substrate 01 shown in FIG. 14 is similar to the display substrate 01 shown in FIG. 4, and only the differences between the two are described here, and the similarities will not be repeated.
  • the difference between the display substrate 01 shown in FIG. 14 and the display substrate 01 shown in FIG. 4 includes: the display substrate 01 shown in FIG. 14 only has the first winding portion 22 and not the second winding portion 23.
  • the first winding portion 22 surrounds the first display area 11 and is located in the second display area 12 as a whole.
  • the first winding portion 22 includes a fifth wire portion 271, a sixth wire portion 272, and a seventh wire portion 273 that are sequentially connected; the fifth wire portion 271 is electrically connected to the first sub-portion 211.
  • the seventh line portion 273 is electrically connected to the second sub-portion 212; the sixth line portion 272 extends along the first direction D1, and the fifth line portion 271 and the seventh line portion 273 extend along the second direction crossing the first direction D1 D2 extends; the sixth line portion 272 and the virtual line extending along the first direction D1 located between the first sub-portion 211 and the second sub-portion 212 are arranged side by side in the first direction D1; the sixth line portion 272 and The first pixel circuit 412 electrically connected to the sixth line portion 272 is at least partially overlapped (or located in the same column, closely adjacent but not overlapped); in operation, the current flow in the sixth line portion 272 is the same as that of the first main body portion.
  • the current flow in 211 is the same.
  • the fifth line portion 271, the sixth line portion 272, and the seventh line portion 273 are all straight line segments.
  • the data driving circuit 50 may be implemented as a driving chip.
  • the driving chip may be bonded on the display substrate 01 via a flexible circuit board, and provide data signals for display to a plurality of data lines via the flexible circuit, so as to drive the display substrate 01 to realize the display function.
  • the peripheral area 14 may also be provided with a gate driving chip, or a gate driving circuit (GOA, not shown in the figure) formed on the array substrate.
  • the gate driving chip or the multiple output terminals of the GOA are connected to the multiple gates respectively.
  • the lines are connected to provide a gate scan signal to a plurality of gate lines.
  • the display substrate 01 is not limited to being driven by a single data driving circuit.
  • the display substrate 01 can be driven by two data driving circuits, and the two data driving circuits are located on both sides of the display substrate 01 (for example, Located on both sides of the display substrate 01 in the first direction D1).
  • FIG. 15 is a schematic plan view of the eighth example of the display substrate 01 shown in FIG. 2A
  • FIG. 16 is another schematic plan view of the eighth example of the display substrate 01 shown in FIG. 2A. It should be noted that, for the sake of clarity, FIG. 15 only shows the first display area 11 and a part of the second display area 12 of the display substrate 01.
  • the display substrate 01 shown in FIG. 15 is similar to the display substrate 01 shown in FIG. 4, and only the differences between the two are described here, and the similarities will not be repeated.
  • the difference between the display substrate 01 shown in FIG. 15 and the display substrate 01 shown in FIG. 4 includes: the first direction D1 of the display substrate 01 shown in FIG. 15 is the row direction of the display panel; The connecting wires 60 extend in the column direction; the first signal line 20 of the display substrate 01 shown in 15 is a gate line, and the second signal line 30 is a data line; the first signal line 20 and the first signal line of the display substrate 01 shown in FIG. 15 are The structure of the winding portion of the second signal line 30 is different from the structure of the winding portion of the first signal line 20 and the second signal line 30 of the display substrate 01 shown in FIG. 15, respectively.
  • the first winding portion 22 surrounds the first display area 11 and is located in the second display area 12 as a whole;
  • the line portion 282; the eighth line portion 281 is electrically connected to the first main body portion 21 and extends along the second direction D2;
  • the ninth line portion 282 extends along the first direction D1 and is at the virtual extension line of the first main body portion 21 Arranged side by side in the first direction D1; in operation, the current direction in the ninth line portion 282 is the same as that in the main body;
  • the ninth line portion 282 is configured to drive in the first display area 11 along the first
  • the first pixel circuits 412 of the first number of first light-emitting elements 411 arranged in parallel in the direction D1 are electrically connected.
  • the eighth line portion 281 and the ninth line portion 282 are both straight line segments.
  • the first main body part 21 includes a first sub-part 211 and a second sub-part 212 (not shown in the figure), and the first winding part 22 further includes a tenth line part (not shown in the figure), The first end of the tenth line is connected to the ninth line 282, the second end of the tenth line is connected to the second sub-part 212, and the tenth line extends in the second direction D2.
  • the second signal line 30 includes a second main body portion 32, a fourth winding portion 33, and a fifth winding portion 34; the fourth winding portion 33 is offset from the second main body portion 32 along the second
  • the second main body portion 32 includes a third sub-portion 321 and a fourth sub-portion 322 separated by the first display area 11.
  • the third sub-portion 321 and the fourth sub-portion 322 pass through the The four winding portions 33 are electrically connected; the fourth winding portion 33 deviates from the virtual line extending in the second direction D2 between the third sub-portion 321 and the fourth sub-portion 322 to be routed.
  • at least part of the fourth winding portion 33 extends in a direction crossing the second direction D2.
  • at least part of the fifth winding portion 34 extends in a direction crossing the second direction D2.
  • the third sub-section 321 and the fourth sub-section 322 are both straight line segments.
  • the fourth winding portion 33 includes a fourth line segment 331, a fifth line segment 332, and a sixth line segment 333 that are sequentially connected, and the end of the fourth line segment 331 that is not connected to the fifth line segment 332 is connected to The end of the third sub-part 321 close to the fourth sub-part 322 is connected, and the end of the sixth line segment 333 that is not connected to the fifth line 332 is connected to the end of the fourth sub-part 322 close to the third sub-part 321,
  • the fourth line segment 331 and the sixth line segment 333 extend along the first direction D1, and the fifth line segment 332 extends along the second direction D2.
  • the fourth line segment 331, the fifth line segment 332, and the sixth line segment 333 are all straight line segments.
  • the first end of the fifth winding part 34 is electrically connected to the second sub-part 212, and the second end of the fifth winding part 34 is electrically connected to the corresponding first pixel circuit 412.
  • the second end of the fifth winding portion 34 may be connected to the first pixel circuit 412 in the same column (for example, the first pixel circuit 412 in the same column directly adjacent to the second line portion 232 of the second winding portion 23).
  • the pixel circuit 412) is electrically connected.
  • the fifth winding part 34 includes a seventh line segment 341 and an eighth line segment 342 that are sequentially connected, and the end of the seventh line segment 341 that is not connected to the eighth line segment 342 serves as the fifth winding part 34
  • the first end of the eighth line segment 342 is not connected to the seventh line segment 341 as the second end of the fifth winding portion 34;
  • the seventh line segment 341 extends in the first direction D1;
  • the eighth line segment 342 is in the second direction D2 extends and is arranged side by side with the second sub-section 212 in the first direction D1; in operation, the current flow in the eighth line segment 342 is opposite to the current flow in the second sub-section 212.
  • the seventh line segment 341 and the eighth line segment 342 are both straight line segments.
  • the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 are located in adjacent columns of the display panel.
  • at least one second signal line 30 is configured to drive the first light-emitting element 411 and the second light-emitting element 421 arranged side by side in the second direction D2, that is, the same second signal line
  • the first light-emitting element 411 and the third light-emitting element 431 driven by 30 are located in the same column of the display substrate 01.
  • the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 may also be located in the same column of the display panel, that is, the first light-emitting element 411 and the first pixel circuit 412 may be located in the same column of the display panel.
  • the first pixel circuits 412 for driving the first light-emitting element 411 are arranged side by side in the column direction.
  • the first direction D1 is the row direction of the display panel
  • the second direction D2 is the column direction of the display panel
  • the first signal line 20 is a gate line
  • the second signal line 30 is a data line.
  • connection trace 60 of the display substrate 01 shown in FIG. 15 in the column direction is not limited to the straight connection traces 60 of the display substrate 01 (that is, it is not limited to the connection traces 60 of the display substrate 01). It is a straight line segment).
  • the connection trace 60 of the display substrate 01 shown in FIG. 15 further includes a portion extending in the row direction.
  • the source and drain electrodes, the first winding part and the second signal line are all located on the first electrode layer, and the first body part, the gate and the first capacitor plate are located on the second electrode layer.
  • the first winding portion and the second signal line are both located on the first electrode layer, and the first body portion and the second capacitor plate of the storage capacitor are located on the second electrode layer.
  • FIG. 16 is similar to FIG. 15.
  • FIG. 16 shows more first signal lines 20, and FIG. 6 does not show the fifth winding portion 34 of the second signal line 30, which will not be repeated here.
  • FIG. 17 shows a pixel circuit 921 provided by at least one embodiment of the present disclosure and a light-emitting element 920 driven by the pixel electrode.
  • a pixel circuit 921 provided by at least one embodiment of the present disclosure and a light-emitting element 920 driven by the pixel electrode.
  • at least one (for example, all) of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may be implemented as the pixel circuit 921 shown in FIG. 17.
  • the pixel circuit 921 further includes a first light emission control circuit 923 and a second light emission control circuit 924.
  • the driving circuit 922 includes a control terminal, a first terminal, and a second terminal, and is configured to provide the organic light emitting element 920 with a driving current for driving the organic light emitting element 920 to emit light.
  • the first light emission control circuit 923 is connected to the first terminal of the driving circuit 922 and the first voltage terminal VDD, and is configured to enable or disconnect the connection between the driving circuit 922 and the first voltage terminal VDD
  • the second The light emission control circuit 924 is electrically connected to the second end of the driving circuit 922 and the first electrode of the organic light emitting element 920, and is configured to realize the on or off of the connection between the driving circuit 922 and the organic light emitting element 920.
  • the pixel circuit 921 further includes a data writing circuit 926, a storage circuit 927, a threshold compensation circuit 928, and a reset circuit 929.
  • the data writing circuit 926 is electrically connected to the first terminal of the driving circuit 922, and is configured to write the data signal into the storage circuit 927 under the control of the scan signal;
  • the storage circuit 927 and the control terminal and the first voltage terminal of the driving circuit 922 VDD is electrically connected and configured to store data signals;
  • the threshold compensation circuit 928 is electrically connected to the control terminal and the second terminal of the drive circuit 922, and is configured to perform threshold compensation on the drive circuit 922;
  • the control terminal is electrically connected to the first electrode of the organic light emitting element 920, and is configured to reset the control terminal of the driving circuit 922 and the first electrode of the organic light emitting element 920 under the control of the reset control signal.
  • the driving circuit 922 includes a driving transistor T1
  • the control terminal of the driving circuit 922 includes the gate of the driving transistor T1
  • the first terminal of the driving circuit 922 includes the first electrode of the driving transistor T1.
  • the second terminal includes the second terminal of the driving transistor T1.
  • the data writing circuit 926 includes a data writing transistor T2
  • the storage circuit 927 includes a capacitor C
  • the threshold compensation circuit 928 includes a threshold compensation transistor T3
  • the first light emission control circuit 923 includes a first light emission control transistor T4.
  • the second light emission control circuit 924 includes a second light emission control transistor T5
  • the reset circuit 929 includes a first reset transistor T6 and a second reset transistor T7.
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal.
  • the gate of the data writing transistor T2 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first electrode of the capacitor C is electrically connected to the first power supply terminal VDD, and the second electrode of the capacitor C is electrically connected to the driving transistor
  • the gate of T1 is electrically connected; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is electrically connected.
  • the electrode is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal;
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal,
  • the first reset The second electrode of the transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal;
  • the second reset transistor The first electrode of T7 is configured to be electrically connected to the second reset power terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 920, and the second reset transistor T7
  • the gate of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, and the first light-emitting control transistor T4 is electrically connected to the second reset control signal line Rst2 to receive the second sub-
  • the second electrode of the drive transistor T1 is electrically connected to the first electrode, the gate of the first light emission control transistor T4 is configured to be electrically connected to the first light emission control signal line EM1 to receive the first light emission control signal; the second light emission control transistor
  • the first electrode of T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the organic light emitting element 920, and the gate of the second light emitting control transistor T5 is configured as It is electrically connected to the second light emission control signal line EM2 to receive the second light emission control signal;
  • the first electrode of the organic light emitting element 920 is electrically connected to the second power terminal VSS.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to the same signal line, such as the first scan signal line.
  • Ga1 is used to receive the same signal (for example, a scan signal).
  • the display substrate 1000 may not be provided with the second scan signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T3 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, which increases the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may be electrically connected to the same signal Lines, such as the first light emission control signal line EM1, to receive the same signal (e.g., the first light emission control signal).
  • the display substrate 1000 may not be provided with the second light emission control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to the first light emission.
  • Control signal line EM1 the gate of the second light emission control transistor T5 is electrically connected to the second light emission control signal line EM2, and the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit the same signal.
  • first light-emission control transistor T4 and the second light-emission control transistor T5 are different types of transistors, for example, the first light-emission control transistor T4 is a P-type transistor and the second light-emission control transistor T5 is an N-type transistor
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited in the embodiment of the present disclosure.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, for example, the first reset The signal line Rst1 is controlled to receive the same signal (for example, the first sub-reset control signal).
  • the display substrate 1000 may not be provided with the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal. It should be noted that the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, and the first reset power terminal Vinit1 and the second reset power terminal Vinit2 can be It is the DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be high-voltage terminals or low-voltage terminals, as long as they can provide a first reset signal and a second reset signal to connect the gate of the driving transistor T1 and the light-emitting element 920
  • the first electrode only needs to be reset, which is not limited in the present disclosure.
  • the driving circuit 922, the data writing circuit 926, the storage circuit 927, the threshold compensation circuit 928, and the reset circuit 929 in the pixel circuit shown in FIG. 17 are only illustrative, and the driving circuit 922, the data writing circuit
  • the specific structures of the circuits 926, the storage circuit 927, the threshold compensation circuit 928, and the reset circuit 929 can be set according to actual application requirements, which are not specifically limited in the embodiment of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to illustrate the details of the present disclosure in detail.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the first The two reset transistors T7 and so on can all be P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the transistors in the embodiments of the present disclosure have the first pole and the second pole.
  • the first pole and the second pole are interchangeable as needed.
  • the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure are not limited to being implemented as a pixel circuit including seven transistors and one capacitor (that is, not Limited to the 7T1C pixel circuit shown in FIG. 17), the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may include a suitable number of transistors and a suitable number of capacitors.
  • the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may be 7T2C pixel circuits, 6T1C pixel circuits, 6T2C pixel circuits, or 9T2C pixel circuits. .
  • FIG. 18 is a schematic diagram of the structure of the 7T1C pixel circuit shown in FIG. 17. The positions of the first transistor T1 to the seventh transistor T7 included in the 7T1C pixel circuit are shown in FIG. 18, and will not be repeated here.
  • FIG. 19 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure.
  • 20-23 are schematic diagrams respectively showing the layout of a certain layer in the sub-pixels according to some embodiments of the present disclosure.
  • 20 is a schematic plan view showing the LTPS layer (low temperature polysilicon layer) of the sub-pixel according to an embodiment of the present disclosure;
  • FIG. 21 is a schematic diagram showing the SD layer (source drain electrode layer) of the sub-pixel according to an embodiment of the present disclosure;
  • Fig. 22 is a schematic plan view showing the Gat1 layer (first gate layer) of the sub-pixel according to an embodiment of the present disclosure;
  • FIG. 23 is a schematic diagram showing the Gat2 layer (the first gate layer) of the sub-pixel according to an embodiment of the present disclosure; A schematic plan view of the second gate layer.
  • FIG. 24 is a schematic diagram showing the layout of the layer overlay shown in FIG. 20, FIG. 22, and FIG. 23 in sub-pixels according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram showing the layout of the layer overlay shown in FIG. 20 to FIG. 23 in a sub-pixel according to an embodiment of the present disclosure.
  • the LTPS layer low temperature polysilicon layer
  • Gat1 layer first gate layer
  • Gat2 layer second gate layer
  • SD layer source drain electrode layer
  • the data lines of the SD layer (source and drain electrode layer) will be switched to the Gat1 layer (the first gate layer) and the Gat2 layer (the second gate layer) after being led out.
  • the sub-pixel may include a light emitting element D, a first transistor T1, a capacitor C, a second transistor T2, and a third transistor T3.
  • the light emitting element D includes an anode D1 and a cathode D2.
  • the light-emitting element D may be an OLED.
  • the first transistor T1 may also be referred to as a switching transistor
  • the second transistor T2 may also be referred to as a driving transistor
  • the third transistor T3 may also be referred to as a reset transistor.
  • the first transistor T1 is configured to transmit a data signal from the data line Dat to the second transistor T2 in response to the scan signal of the gate line Gat when turned on.
  • the second transistor T2 is configured to transmit the driving current Id to the light-emitting element D when turned on to drive the light-emitting element D to emit light.
  • the third transistor T3 is configured to reset the voltage of the gate G2 of the second transistor T2 to the voltage of the initialization voltage line Vinit when turned on in response to the reset signal of the reset line Rese.
  • the sub-pixel may further include one or more of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.
  • the fourth transistor T4 may also be referred to as a compensation transistor
  • the fifth transistor T5 may also be referred to as a drive control transistor
  • the sixth transistor T6 may also be referred to as an emission control transistor
  • the seventh transistor T7 may also be referred to as a bypass transistor.
  • the fourth transistor T4 is configured to respond to the scan signal of the scan line Gat and make the second transistor T2 in a diode connection state when turned on.
  • the fifth transistor T5 and the sixth transistor T6 are configured to make the emission current Id flow to the light emitting element D in response to the control signal of the control line EM when turned on.
  • the seventh transistor T7 is configured to respond to the reset signal of the reset line Rese to cause a part of the driving current Id to flow as the bypass current Ibp when turned on.
  • the third gate G3 of the third transistor T3 and the seventh gate G7 of the seventh transistor T7 shown in FIG. 19 are both connected to the same reset line Rese.
  • the seventh gate G7 of the seventh transistor T7 may be connected to another reset line different from the reset line Rese.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-channel thin film transistors. In other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N Channel thin film transistor.
  • the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be as shown in FIG. 20 .
  • the material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon.
  • the active layer of each transistor includes two electrode regions and a channel region located between the two electrode regions.
  • one of the two electrode regions is a source region, and the other is a drain region.
  • the doping concentration in the two electrode regions is greater than the doping concentration in the channel region.
  • each of the two electrode regions is a conductor region, and the channel region is a semiconductor region.
  • the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gat.
  • the scan line Gat and the first gate G1 may be integrally provided.
  • the first active layer ACT1 includes a first electrode area ACT11, a second electrode area ACT12, and a first channel area ACT13 located between the first electrode area and the second electrode area.
  • the first electrode area ACT11 is connected to the data line Dat
  • the second electrode area ACT12 is connected to the power supply line VDD.
  • the first electrode area ACT11 may be connected to the data line Dat via the via V1 shown in FIG. 25.
  • the second electrode region ACT12 may be connected to the power supply line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the fifth active layer ACT5 may be connected to the power supply line VDD via the via V2 shown in FIG. 25.
  • the data line Dat and the power supply line VDD may be located in the same layer.
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply line VDD.
  • the second electrode plate C2 may be connected to the power supply line VDD via the via V3 shown in FIG. 25.
  • the second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1.
  • the first electrode plate C1 and the second grid G2 may be integrally provided.
  • the second active layer ACT2 includes a third electrode area ACT21, a fourth electrode area ACT22, and a second channel area ACT23 located between the third electrode area ACT21 and the fourth electrode area ACT22.
  • the third electrode area ACT21 is connected to the second electrode area ACT12
  • the fourth electrode area ACT22 is connected to the anode D1.
  • the third electrode area ACT21 and the second electrode area ACT12 may be integrally provided.
  • the third electrode region ACT21 may be connected to the power supply line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Rese.
  • the reset line Rese and the third gate G3 may be integrally provided.
  • the third active layer ACT3 includes a fifth electrode area ACT31, a sixth electrode area ACT32, and a third channel area ACT33 located between the fifth electrode area ACT31 and the sixth electrode area ACT32.
  • the fifth electrode area ACT31 is connected to the first electrode plate C1
  • the sixth electrode area ACT32 is connected to the initialization voltage line Vinit.
  • the fifth electrode area ACT31 may be connected to the first connector CT1 via the via hole V4 shown in FIG.
  • the first electrode plate C1 may be connected to the first connector CT1 via the via hole V5 shown in FIG. 25.
  • the sixth electrode area ACT32 may be connected to the second connector CT2 via the via hole V6 shown in FIG. 25, and the initialization voltage line Vinit may be connected to the second connector CT2 via the via hole V7 shown in FIG. 25.
  • the first connector CT1, the second connector CT2, the data line Dat, and the power line VDD may be located in the same layer.
  • the scan line Gat, the first electrode plate C1, and the reset line Rese may be located in the same layer.
  • the second electrode plate C2 and the initialization voltage line Vinit may be located on the same layer.
  • the first channel region ACT13 may be a region where the first active layer ACT1 overlaps the scan line Gat
  • the second channel region ACT23 may be a region where the second active layer ACT2 overlaps the first electrode plate C1
  • the third channel region ACT33 may be a region where the third active layer ACT3 overlaps the reset line Rese
  • the fourth channel region ACT43 may be a region where the fourth active layer ACT4 overlaps the scan line Gat.
  • the light-emitting element D includes an anode D1 and a cathode D2.
  • the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gat.
  • the first active layer ACT1 includes a first electrode region ACT11, a second electrode region ACT12, and a In the first channel region ACT13 between the second electrode regions, the first electrode region ACT11 is connected to the data line Dat, and the second electrode region ACT12 is connected to the power line VDD.
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply line VDD.
  • the second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1.
  • the second active layer ACT2 includes a third electrode area ACT21, a fourth electrode area ACT22, and a third electrode
  • the second channel area ACT23 between the area ACT21 and the fourth electrode area ACT22, the third electrode area ACT21 is connected to the second electrode area ACT12, and the fourth electrode area ACT22 is connected to the anode D1.
  • the third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Rese.
  • the third active layer ACT3 includes a fifth electrode area ACT31, a sixth electrode area ACT32, and a fifth electrode area ACT31. Between the third channel region ACT33 and the sixth electrode region ACT32, the fifth electrode region ACT31 is connected to the first electrode plate C1, and the sixth electrode region ACT32 is connected to the initialization voltage line Vinit.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 will be introduced below in conjunction with FIGS. 19 and 20.
  • the fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4 connected to the scan line Gat.
  • the scan line Gat and the fourth gate G4 may be integrally provided.
  • the fourth active layer ACT4 includes a seventh electrode area ACT41, an eighth electrode area ACT42, and a fourth channel area ACT43 located between the seventh electrode area ACT41 and the eighth electrode area ACT42.
  • the seventh electrode area ACT41 is connected to the second gate G2, and the eighth electrode area ACT42 is connected to the fourth electrode area ACT22.
  • the seventh electrode region ACT41 may be connected to the first connector CT1 via the via hole V4 shown in FIG.
  • the second gate G2 may be connected to the first connector CT1 via the via hole V5 shown in FIG. 25.
  • the seventh electrode area ACT41 and the fifth electrode area ACT31 may be integrally provided.
  • the eighth electrode area ACT42 and the fourth electrode area ACT22 may be integrally provided.
  • the fourth channel region ACT43 may include two parts spaced apart, that is, the fourth gate G4 may include two gates.
  • the fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5 connected to the control line EM.
  • the fifth active layer ACT5 includes a ninth electrode area ACT51, a tenth electrode area ACT52, and a fifth channel area ACT53 located between the ninth electrode area ACT51 and the tenth electrode area ACT52.
  • the ninth electrode area ACT51 is connected to the power supply line VDD
  • the tenth electrode area ACT52 is connected to the second electrode area ACT12.
  • the ninth electrode region ACT51 may be connected to the power supply line VDD via the via V2 shown in FIG. 25.
  • the tenth electrode area ACT52 may be connected to the second electrode area ACT12 via the third electrode area ACT21.
  • the control line EM, the scan line Gat, the first electrode plate C1, and the reset line Rese may be located in the same layer.
  • the sixth transistor T6 includes a sixth active layer ACT6 and a sixth gate G6 connected to the control line EM.
  • the sixth active layer ACT6 includes an eleventh electrode area ACT61, a twelfth electrode area ACT62, and a sixth channel area located between the eleventh electrode area ACT61 and the twelfth electrode area ACT62.
  • ACT63 The eleventh electrode area ACT61 is connected to the fourth electrode area ACT22, and the twelfth electrode area ACT62 is connected to the anode D1.
  • the eleventh electrode area ACT61 and the fourth electrode area ACT22 may be integrally provided.
  • the twelfth electrode region ACT62 may be connected to the conductive layer M (for example, a metal layer) via the via hole V8 shown in FIG. 25, and the conductive layer M may be connected to the anode D1 via other via holes.
  • the conductive layer M, the first connection member CT1, the second connection member CT2, the data line Dat, and the power supply line VDD may be located in the same layer.
  • the seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7 connected to the reset line Rese.
  • the reset line Rese and the seventh gate G7 may be integrally provided.
  • the seventh active layer ACT7 includes a thirteenth electrode area ACT71, a fourteenth electrode area ACT72, and a seventh channel area located between the thirteenth electrode area ACT71 and the fourteenth electrode area ACT72.
  • ACT73 The thirteenth electrode area ACT71 is connected to the twelfth electrode area ACT62, and the fourteenth electrode area ACT72 is connected to the initialization voltage line Vinit.
  • the fourteenth electrode area ACT72 may be connected to the second connector CT2 via the via hole V6 shown in FIG. 25, and the initialization voltage line Vinit may be connected to the second connector CT2 via the via hole V7 shown in FIG. 25.
  • the fourteenth electrode area ACT72 and the sixth electrode area ACT32 may be integrally provided.
  • the fifth channel region ACT53 may be a region where the fifth active layer ACT5 overlaps the control line EM
  • the sixth channel region ACT63 may be a region where the sixth active layer ACT6 overlaps the control line EM
  • the seventh channel region ACT73 may be a region where the seventh active layer ACT7 overlaps the reset line.
  • the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, and the sixth active layer ACT6 and the seventh active layer ACT7 may be located in the same layer.
  • sub-pixels include T1, T2, T3, T4, T5, T6, and T7, and the transistors T1, T2, T3, T4, T5, T6, and T7 are all P-type grooves. Road transistor.
  • the third transistor T3 is turned on in response to the reset signal of the reset line Rese, and the second gate G2 of the second transistor T2 is connected to the initialization voltage line Vinit via the third transistor T3. In this way, the voltage of the second gate G2 of the driving transistor T1 is reset to the voltage of the initialization voltage line Vinit.
  • the first transistor T1 and the fourth transistor T4 are turned on in response to the scan signal of the scan line Gat.
  • the second transistor T2 is in a diode connection state and is forward biased.
  • the voltage of the second gate G2 of the second transistor T2 is the sum of the voltage Vdata of the data signal from the data line Dat and the threshold voltage Vth (negative number) of the second transistor T2, that is, Vdata+Vth.
  • the voltage of the first electrode plate C1 of the capacitor Cst is Vdata+Vth
  • the voltage of the second electrode plate C2 of the capacitor Cst is the voltage ELVDD of the power supply line VDD.
  • the capacitor Cst is charged with electric charge corresponding to the voltage difference between the first electrode plate C1 and the second electrode plate C2.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the control signal of the control line EM.
  • the driving current Id is generated in response to the voltage difference between the voltage of the second gate G2 of the second transistor T2 and the voltage of the power supply line VDD, and the driving current Id is supplied to the light emitting element D through the sixth transistor T6.
  • the gate-source voltage Vgs of the second transistor T2 is maintained at (Vdata+Vth)-ELVDD.
  • the drive current Id is proportional to (Vdata-ELVDD) 2 . Therefore, the driving current Id is independent of the threshold voltage Vth of the first transistor T1.
  • the seventh transistor T7 is turned on in response to the reset signal of the reset line Rese.
  • the seventh transistor T7 may be turned on simultaneously with the first transistor T1 and the fourth transistor T4.
  • a part of the driving current Id may be used as a bypass current Ibp to flow out through the seventh transistor T7.
  • At least one embodiment of the present disclosure also provides a display device, which includes any of the above-mentioned display substrates of the present disclosure.
  • the display device can be implemented as any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

Abstract

一种显示基板（01）和显示装置（03）。该显示基板（01）包括显示区域（10），至少一根第一信号线（20）以及至少一根连接走线（60）。显示区域（10）包括第一显示区域（11）和第二显示区域（12）；第二显示区域（12）至少部分围绕第一显示区域（11）；第一显示区域（11）包括至少一个第一发光元件（411），第二显示区域（12）包括至少一个第一像素电路（412）；至少一根第一信号线（20）包括第一主体部（21）和第一绕线部（22）；第一主体部（21）沿第一方向（D1）延伸，第一绕线部（22）的至少部分沿与第一方向交叉（D1）的方向延伸；至少一根第一信号线（20）与至少一个第一像素电路（412）电连接，以为至少一个第一像素电路（412）提供第一驱动信号；至少一个第一像素电路（412）分别经由对应的连接走线（60）与至少一个第一发光元件（411）电连接；以及至少一个第一像素电路（412）被配置为分别驱动至少一个第一发光元件（411）。该显示基板（01）和显示装置（03）可以提升第一显示区域（11）的透过率。

Description

显示基板和显示装置
对相关申请的交叉参考
本申请要求于2020年1月23日递交的PCT专利申请PCT/CN2020/073993、PCT/CN2020/073995、PCT/CN2020/073996和PCT/CN2020/074001的优先权，出于所有目的，在此全文引用上述PCT专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快、色域广、屏占比高、自发光、轻薄等特点。并且，相比于无机发光显示器件，有机发光二极管显示器件具有更高的发光亮度、更低的驱动电压等优势。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、智能手表、数码相机、仪器仪表、柔性可穿戴装置等具有显示功能的装置。随着显示技术的进一步发展，具有高屏占比的显示装置已经不能满足人们的需求，具有全面屏的显示装置成为未来显示技术的发展趋势。
发明内容
本公开的至少一个实施例提供了一种显示基板，其包括显示区域，至少一根第一信号线以及至少一根连接走线。所述显示区域包括第一显示区域和第二显示区域；所述第二显示区域至少部分围绕所述第一显示区域；所述第一显示区域包括至少一个第一发光元件，所述第二显示区域包括至少一个第一像素电路；所述至少一根第一信号线包括第一主体部和第一绕线部；所述第一主体部沿第一方向延伸，所述第一绕线部偏离所述第一主体部的沿所述第一方向的虚拟延长线而走线；所述至少一根第一信号线与所述至少一个第一像素电路电连接，以为所述至少一个第一像素电路提供第一驱动信号；所述至少一个第一像素电路分别经由对应的连接走线与所述至少一个第一发光元件电连接；以及所述至少一个第一像素电路被配置为分别驱动所述至少一个第一发光元件。
例如，在所述显示基板的至少一个示例中，所述显示区域还包括第三显示区域；所述第三显示区域至少部分围绕所述第二显示区域；所述至少一个第一发光元件包括多个第一发光元件；所述第二显示区域包括多个第二发光元件；所述第三显示区域包括多个第三发光元件；以及所述至少一根第一信号线被配置为驱动沿所述第一方向并列布置的第一发光元件和第三发光元件。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括至少一根第二信号线。 所述至少一根第二信号线包括第二主体部，所述第二主体部沿与所述第一方向交叉的第二方向延伸；所述第一主体部的沿所述第一方向延伸的虚拟延长线和所述第二主体部的沿所述第二方向延伸的虚拟延长线相交于所述第一显示区域内；所述至少一根第二信号线的第二主体部与所述至少一个第一像素电路电连接，以为所述至少一个第一像素电路提供不同于所述第一驱动信号的第二驱动信号。
例如，在所述显示基板的至少一个示例中，所述至少一根连接走线从所述第一显示区域沿所述第二方向延伸至所述第二显示区域。
例如，在所述显示基板的至少一个示例中，所述第一主体部包括被所述第一显示区域间隔开的第一子部和第二子部；所述第一子部和所述第二子部经由所述第一绕线部电连接；以及所述第一绕线部的至少部分与位于所述第一子部和所述第二子部之间的沿所述第一方向延伸的虚拟连线交叉。
例如，在所述显示基板的至少一个示例中，所述第一绕线部为弧线，所述弧线的第一端与所述第一子部的靠近所述第二子部的端部相连，所述弧线的第二端与所述第二子部的靠近所述第一子部的端部相连；或者所述第一绕线部包括顺次相连的第一线段、第二线段和第三线段，所述第一线段的不与所述第二线段相连的端部与所述第一子部的靠近所述第二子部的端部相连，所述第三线段的不与所述第二线段相连的端部与所述第二子部的靠近所述第一子部的端部相连，所述第二线段沿所述第一方向延伸，所述第一线段和所述第三线段沿与所述第一方向交叉的第二方向延伸。
例如，在所述显示基板的至少一个示例中，所述第二显示区域具有内边缘和外边缘，所述第二显示区域的内边缘围绕所述第一绕线部。
例如，在所述显示基板的至少一个示例中，所述至少一根第一信号线还包括第二绕线部。所述第二绕线部的第一端与所述第二子部电连接，所述第二绕线部的第二端与对应的第一像素电路电连接；所述第二绕线部包括顺次相接的第一线部和第二线部；所述第一线部的不与所述第二线部相连的一端作为所述第二绕线部的第一端；所述第二线部的不与所述第一线部相连的一端作为所述第二绕线部的第二端；所述第一线部沿与所述第一方向交叉的第二方向延伸；所述第二线部沿所述第一方向延伸且与所述第二子部在所述第二方向上并列布置；以及在工作中，所述第二线部中的电流走向与所述主体部中的电流走向相反。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括围绕所述显示区域的周边区域。所述第一线部整体位于所述周边区域，且在所述第一方向上与所述第二显示区域并列布置。
例如，在所述显示基板的至少一个示例中，所述第一线部整体位于所述第二显示区域中，且所述第一线部的至少部分在所述第一方向上与所述第一显示区域并列布置。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括围绕所述显示区域的周边区域。所述第一线部包括顺次相接的第一部分、第二部分和第三部分；所述第一线部的第一部分与所述第二子部电连接，所述第一线部的第三部分与所述第二线部电连接；所述第一线部的第一部分位于所述周边区域，且在所述第一方向上与所述第二显示区域并列 布置；所述第一线部的第二部分从所述周边区域沿所述第一方向延伸至所述第二显示区域；以及所述第一线部的第三部分位于所述第二显示区域，且所述第一线部的第三部分的沿所述第二方向延伸的虚拟延长线在所述第一方向上与所述第一显示区域并列布置。
例如，在所述显示基板的至少一个示例中，所述至少一根第一信号线还包括第三绕线部。所述第三绕线部的第一端与所述第一子部电连接，所述第三绕线部的第二端与对应的第一像素电路电连接，与所述第二绕线部相连的第一像素电路不同于与所述第三绕线部相连的第一像素电路。
例如，在所述显示基板的至少一个示例中，所述第三绕线部包括顺次相接的第三线部和第四线部；所述第三线部不与所述第四线部相连的一端作为所述第三绕线部的第一端，所述第四线部的不与所述第三线部相连的一端作为所述第三绕线部的第二端；所述第三线部沿所述第二方向延伸，且与所述第一线部在所述第一方向上并列布置；所述第四线部沿所述第一方向延伸且与所述第一子部在所述第二方向上并列布置；以及在工作中，所述第四线部中的电流走向与所述主体部中的电流走向相同。
例如，在所述显示基板的至少一个示例中，所述第一主体部、所述第一绕线部和所述第二线部位于所述显示基板的第一电极层；所述第一线部位于所述显示基板的第二电极层；所述第一电极层和所述第二电极层在所述显示基板的显示面的法线方向上叠置；以及所述第一线部分别经由位于所述第一电极层和所述第二电极层之间的绝缘层的第一过孔和第二过孔与所述第二子部和所述第二线部电连接。
例如，在所述显示基板的至少一个示例中，所述至少一个第一像素电路的每个包括薄膜晶体管；所述薄膜晶体管包括栅极和源漏极；以及所述源漏极位于所述第一电极层，所述栅极位于所述第二电极层。
例如，在所述显示基板的至少一个示例中，所述第一绕线部围绕所述第一显示区域，且整体位于第二显示区域；所述第一绕线部包括顺次相接的第五线部、第六线部和第七线部；所述第五线部与所述第一子部电连接，所述第七线部与所述第二子部电连接；所述第六线部沿所述第一方向延伸，所述第五线部和第七线部沿与所述第一方向交叉的第二方向延伸；所述第六线部与位于所述第一子部和所述第二子部之间的沿所述第一方向延伸的虚拟连线在所述第一方向上并列布置；所述第六线部和与所述第六线部电连接的第一像素电路至少部分交叠；以及在工作中，所述第六线部中的电流走向与所述主体部中的电流走向相同。
例如，在所述显示基板的至少一个示例中，所述第一绕线部围绕所述第一显示区域，且整体位于第二显示区域；所述第一绕线部包括顺次相接的第八线部和第九线部；所述第八线部与所述第一主体部电连接，且沿所述第二方向延伸；所述第九线部沿所述第一方向延伸，且与所述第一主体部的虚拟延长线在所述第一方向上并列布置；在工作中，所述第九线部中的电流走向与所述主体部中的电流走向相同；以及所述第九线部与被配置为驱动在所述第一显示区域中沿所述第一方向并列布置的所述第一数目的第一发光元件的第一像素电路电连接。
例如，在所述显示基板的至少一个示例中，所述第二信号线还包括第四绕线部，所述第四绕线部偏离所述第二主体部的沿所述第二方向的虚拟延长线而走线；所述第二主体部包括被所述第一显示区域间隔开的第三子部和第四子部，所述第三子部和所述第四子部经由所述第四绕线部电连接；以及所述第四绕线部偏离位于所述第三子部和所述第四子部之间的沿所述第二方向延伸的虚拟连线而走线。
例如，在所述显示基板的至少一个示例中，所述至少一个第一像素电路的每个包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极；以及所述源漏极、所述第一绕线部和所述第二信号线均位于所述第一电极层，所述第一主体部和所述栅极位于第二电极层。
例如，在所述显示基板的至少一个示例中，所述至少一根连接走线位于所述第一显示区域的部分为透明走线。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一显示基板。
例如，在所述显示基板的至少一个示例中，所述的显示装置还包括传感器。所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种显示基板的截面示意图；
图1B是图1A所示的显示基板的平面示意图；
图1C是图1B所示的显示基板的部分区域的示意图；
图1D是图1B所示的显示基板的部分第一显示区域和部分第二显示区域的示意图；
图2A是本公开的至少一个实施例提供的显示基板的平面示意图；
图2B是图2A所示的显示基板的第一显示区域和第二显示区域的平面示意图；
图2C是图2B所示的显示基板的第一显示区域和第二显示区域的一个示例；
图2D是图2C的部分区域的放大图；
图2E是图2D所示的第一显示区域的部分区域的放大图；
图2F是图2A所示的显示基板的第三显示区域的部分区域的放大图；
图3是本公开的至少一个实施例提供的显示装置的截面示意图；
图4是图2A所示的显示基板的第一个示例；
图5A是用于示出图4所示的显示基板第一显示区域、第二显示区域和部分周边区域的第一个示意图；
图5B是用于示出图4所示的显示基板第一显示区域、第二显示区域和部分周边区域的第二个示意图；
图5C是用于示出图4所示的显示基板第一显示区域、第二显示区域和部分周边区域 的第三个示意图；
图5D示出了本公开的至少一个实施例提供的第一发光元件以及驱动第一发光元件的第一像素电路的叠层结构示意图；
图5E示出了本公开的至少一个实施例提供的一种第二像素单元的叠层结构示意图；
图5F示出了本公开的至少一个实施例提供的一种第三像素单元的叠层结构示意图；
图5G是本公开的至少一个实施例提供的第二像素单元、第二绕线部的第一线部和第一主体部的第二子部的叠层结构示意图；
图5H示出了本公开的至少一个实施例提供的一种第二像素单元的另一种叠层结构示意图；
图5I是沿图5A所示的HH’线的截面示意图；
图6是图2A所示的显示基板的第二个示例；
图7A是用于示出图6所示的显示基板第一显示区域、第二显示区域和部分周边区域的第一个示意图；
图7B是用于示出图6所示的显示基板第一显示区域、第二显示区域和部分周边区域的第二个示意图；
图8是图2A所示的显示基板的第三个示例；
图9A是用于示出图8所示的显示基板第一显示区域、第二显示区域和部分周边区域的第一个示意图；
图9B是用于示出图8所示的显示基板第一显示区域、第二显示区域和部分周边区域的第二个示意图；
图10是图2A所示的显示基板的第四个示例；
图11是图2A所示的显示基板的第五个示例；
图12A是用于示出图11所示的显示基板第一显示区域、第二显示区域和部分周边区域的第一个示意图；
图12B是用于示出图11所示的显示基板第一显示区域、第二显示区域和部分周边区域的第二个示意图；
图12C是对应于图12B的部分区域的平面示意图；
图13A是图2A所示的显示基板01的第六个示例的一种平面示意图；
图13B是图2A所示的显示基板的第六个示例的另一种平面示意图；
图13C是图2A所示的显示基板的第六个示例的再一种平面示意图；
图13D是对应于图13C所示的部分区域REG_B的平面示意图；
图14是图2A所示的显示基板的第七个示例的一种平面示意图；
图15是图2A所示的显示基板的第八个示例的一种平面示意图；
图16是图2A所示的显示基板的第八个示例的另一种平面示意图；
图17是本公开的至少一个实施例提供的像素电路以及被该像素电极驱动的发光元件；
图18是图17所示的7T1C像素电路的结构示意图；
图19是示出根据本公开一个实施例的子像素的结构示意图；
图20-图23是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图；
图24是示出根据本公开一个实施例的子像素中图20-图23所示的层叠加的布局示意图；以及
图25是示出根据本公开一个实施例的子像素中图20-图23所示的层叠加的布局示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人注意到，对于当前的具有屏下传感器(例如，摄像头)的显示基板，为了提高显示基板的对应于屏下传感器(例如，摄像头)的显示区域的透过率，对应于屏下传感器(摄像头)的显示区域的发光元件的单位面积分布密度(PPI)小于显示基板的其它显示区域的发光元件的单位面积分布。下面结合图1A和图1B进行示例性说明。
图1A是一种显示基板500的截面示意图，图1B是图1A所示的显示基板500的平面示意图，图1A所示的显示基板500对应于图1B所示的显示基板10的BB’线。图1C是图1B所示的显示基板500的部分区域513的示意图。
如图1A所示，该显示基板500包括显示层510和感测层520，感测层520设置在显示基板500的非显示侧(即背离使用者一侧)。如图1A-图1C所示，显示层510包括第一显示区域511和第二显示区域512；第一显示区域511包括阵列排布的多个第一像素单元531，多个第一像素单元531的每个包括第一发光元件和第一像素电路；第二显示区域512包括阵列排布的多个第二像素单元532，多个第二像素单元532的每个包括第二发光元件和第二像素电路。例如，多个第一发光元件和多个第二发光元件具有相同的结构和性能特性；多个第一像素电路和多个第二第一像素电路具有相同的结构和性能特性。
如图1A所示，感测层520包括传感器521，传感器521与第一显示区域511在显示基板500的显示面的法线方向上叠置，且被配置为接收并处理穿过第一显示区域511的光信号。
如图1C所示，为了减小第一显示区域511中的元件对入射至第一显示区域511并朝向传感器521传输的光信号的遮挡，第一显示区域511中多个第一像素单元531的单位面积分布密度小于第二显示区域512中多个第二像素单元532的单位面积分布密度，第一显示区域511中多个第一发光元件的单位面积分布密度小于第二显示区域512中多个第二发光元件的单位面积分布密度。
本公开的发明人还注意到，尽管通过降低第一发光元件的单位面积分布密度(PPI)，增加相邻的第一发光元件之间的间距可以在一定程度上提升显示基板的对应于屏下传感器(摄像头)的显示区域的透过率，但是该方案对透过率的提升作用仍然受到限制，难以完全满足用户的通过屏下摄像头获取高质量照片的需求。
如图1A-图1C所示，显示基板的数据线541和栅线542穿过第一显示区域511。图1D是图1B所示的显示基板500的部分第一显示区域和部分第二显示区域的一种示意图。如图1D所示，数据线541穿过第一显示区域511。
本公开的发明人还注意到，穿过第一显示区域511的数据线541和栅线542不仅会阻挡入射至第一显示区域511并朝向传感器521传输的光线，还可能导致衍射，使得传感器输出的图像存在重影或者鬼影，由此进一步地降低了传感器输出的图像的图像质量。
本公开的至少一个实施例提供了一种显示基板和显示装置。该显示基板包括显示区域，至少一根第一信号线以及至少一根连接走线。显示区域包括第一显示区域和第二显示区域；第二显示区域至少部分围绕第一显示区域；第一显示区域包括至少一个第一发光元件，第二显示区域包括至少一个第一像素电路；至少一根第一信号线包括第一主体部和第一绕线部；第一主体部沿第一方向延伸，第一绕线部的至少部分沿与第一方向交叉的方向延伸；至少一根第一信号线与至少一个第一像素电路电连接，以为至少一个第一像素电路提供第一驱动信号；至少一个第一像素电路分别经由对应的连接走线与至少一个第一发光元件电连接；至少一个第一像素电路被配置为分别驱动至少一个第一发光元件。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一显示基板。该显示基板和显示装置可以提升第一显示区域的透过率。
下面通过几个示例或实施例对根据本公开的至少一个实施例提供的显示基板和显示装置进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例或实施例中不同特征可以相互组合，从而得到新的示例或实施例，这些新的示例或实施例也都属于本公开保护的范围。
图2A是本公开的至少一个实施例提供的显示基板01的平面示意图。如图2A所示，该显示基板01包括显示区域10和周边区域14，显示区域10包括第一显示区域11、第二显示区域12和第三显示区域13，周边区域14至少部分围绕(例如，完全围绕)第三显示区域13。例如，如图2A所示，第一显示区域11、第二显示区域12和第三显示区域13互 不重叠。例如，如图2A所示，第三显示区域13至少部分围绕(例如，部分围绕)第二显示区域12。例如，如图2A所示，第三显示区域13部分围绕第二显示区域12。需要说明是，在一些示例中，显示基板01也可以不具有周边区域14。
图2B是图2A所示的显示基板01的第一显示区域11和第二显示区域12的平面示意图。例如，如图2A和图2B所示，第二显示区域12至少部分围绕(例如，完全围绕)第一显示区域11。
例如，如图2A和图2B所示，第一显示区域11的形状可以为圆形，第二显示区域12的形状可以为矩形，但本公开的实施例不限于此。又例如，第一显示区域11和第二显示区域12的形状可以均为矩形或者其它适用的形状。
图2C是图2B所示的显示基板01的第一显示区域11和第二显示区域12的一个示例。图2D是图2C的部分区域REG1的放大图。图2E是图2D所示的第一显示区域11的部分区域REG3的放大图。
例如，如图2C-图2E所示，第一显示区域11包括多个第一发光元件411。需要说明的是，为清楚起见，相关附图使用了第一发光元件411的阳极结构4111来示意性的示出第一发光元件411。例如，如图2C-图2E所示，第一显示区域11包括阵列排布的多个第一像素单元41，多个第一像素单元41的每个包括第一数目的第一发光元件411，第一数目的第一发光元件411被配置为发射第二数目种颜色的光线。例如，如图2C-图2E所示，第一数目的第一发光元件411中不同的第一发光元件411的阳极结构4111具有不同的形状，对应地，第一数目的第一发光元件411中不同的第一发光元件411具有不同的形状。
例如，如图2C-图2E所示，第一数目可以为四，第二数目可以为三，也即，多个第一像素单元41的每个包括四个第一发光元件411，且上述四个第一发光元件411被配置为发射三种颜色的光线(例如，红绿蓝)。例如，多个第一像素单元41的每个包括四个第一发光元件411(例如，GGRB，也即，两个绿色发光元件、一个红色发光元件和一个蓝色发光元件)，上述四个发光元件(例如，GGRB)分别被配置为发出绿色、绿色、红色和蓝色的光线。又例如，在多个第一像素单元41的每个包括四个第一发光元件411的情况下，四个第一发光元件411的排布方式不限于GGRB，四个第一发光元件411的排布方式还可以为RGBG或其它适用的排布方式。需要说明的是，在一些示例中，第一数目和第二数目均可以为三；此种情况下，多个第一像素单元41的每个包括三个第一发光元件411(例如，RGB)。
例如，如图2C和图2D所示，第二显示区域12包括多个第一像素电路412。例如，多个第一像素电路412被配置为一一对应地驱动多个第一发光元件411。例如，图2C和图2D所示的白色矩形框表示第一像素驱动单元，每个第一像素驱动单元包括第一数目的像素电路。例如，图2C和图2D所示的第二显示区域12中第一像素驱动单元的数目与第一像素单元41的数目的比值为三；对应地，每三个第一像素驱动单元中仅有一个第一像素驱动单元的像素电路用于驱动第一发光元件411，因此，被用于驱动第一发光元件411的第一像素驱动单元包括的像素电路被称为第一像素电路412，没有用于驱动第一发光元件411 的第一像素驱动单元包括的像素电路被称为虚拟(dummy)像素电路。例如，第一像素电路412和虚拟(dummy)像素电路具有相同的电路结构。例如，每个被用于驱动第一发光元件411的第一像素驱动单元包括的第一数目的第一像素电路412被配置为一一对应地驱动多个第一像素单元41中对应的一个第一像素单元41的第一数目的第一发光元件411。例如，如图2C-图2E所示，多个第一发光元件411阵列排布，多个第一像素电路412阵列排布。为清楚起见，第一发光元件411和第一像素电路412的具体结构将在图5D所示的示例进行描述，在此不再赘述。
例如，如图2C和图2D所示，第二显示区域12还包括多个第二像素单元42，多个第二像素单元42的每个包括第二发光元件421(例如，第一数目的第二发光元件421)以及用于驱动第二发光元件421的第二像素电路422(例如，第一数目的第二像素电路422)。例如，如图2C和图2D所示，多个第二像素单元42的每个包括第二发光元件421和第二像素电路422(也即，与第二发光元件421至少部分交叠的矩形框)在显示基板01的显示面的法线方向(例如，垂直于显示基板01的方向)至少部分重叠。例如，如图2C和图2D所示，多个第二像素单元42阵列排布。为清楚起见，第二像素单元42的具体结构将在图5E所示的示例进行描述，在此不再赘述。需要说明的是，图2D所示的矩形框仅用于示出第二像素电路422，而并不表示第二像素电路422的具体形状以及第二像素电路422的具体边界。
例如，第二像素单元42包括的第一数目的第二发光元件421与第一像素单元41包括的第一数目的第一发光元件411具有相同的排布方式和结构。例如，第二像素单元42包括的第一数目的第二像素电路422与用于驱动第一发光元件411的第一像素驱动单元包括的第一数目的第一像素电路412具有相同的排布方式和结构。
图2F是图2A所示的显示基板01的第三显示区域13的部分区域REG2的放大图。例如，如图2F所示，第三显示区域13包括多个第三像素单元43，多个第三像素单元43的每个包括第三发光元件431(例如，第一数目的第三发光元件431)以及用于驱动第三发光元件431的第三像素电路432(例如，第一数目的第三像素电路432)。例如，如图2F所示，多个第三像素单元43的每个包括第三发光元件431和第三像素电路432在显示基板01的显示面的法线方向至少部分重叠。为清楚起见，第三像素单元43的具体结构将在图5F所示的示例进行描述，在此不再赘述。需要说明的是，图2F所示的矩形框仅用于示出第三像素电路432，而并不表示第三像素电路432的具体形状以及第三像素电路432的具体边界。
例如，第三像素单元43包括的第一数目的第三发光元件431与第一像素单元41包括的第一数目的第一发光元件411具有相同的排布方式和结构。例如，第三像素单元43包括的第一数目的第三像素电路432与用于驱动第一发光元件411的第一像素驱动单元包括的第一数目的第一像素电路412具有相同的排布方式和结构。
例如，如图2D和图2F所示，第一显示区域11中多个第一发光元件411的单位面积分布密度小于第二显示区域12中多个第三发光元件431的单位面积分布密度；第二显示区 域12中多个第二发光元件421的单位面积分布密度小于第二显示区域12中多个第三发光元件431的单位面积分布密度。例如，第一显示区域11和第二显示区域12可以被称为显示基板01的低分辨率区域。例如，如图2D所示，第一显示区域11中多个第一发光元件411的单位面积分布密度等于第二显示区域12中多个第二发光元件421的单位面积分布密度。
图3是本公开的至少一个实施例提供的显示装置03的截面示意图。如图3所示，该显示装置03包括图2A所示的显示基板01。图3所示的显示装置03的截面示意图对应于图2A所示的AA’线。如图3所示，该显示装置03还包括传感器02。
例如，该显示基板01包括彼此相反的显示侧和非显示侧，显示基板01被配置为在显示基板01的显示侧执行显示操作，也即，显示基板01的显示侧为显示基板01的出光侧，朝向用户。显示侧和非显示侧在显示基板01的显示面的法线方向上对置。
如图3所示，传感器02与第一显示区域11在显示基板01的显示面的法线方向(例如，垂直于显示基板01的方向)上叠置，且被配置为接收并处理穿过第一显示区域11的光信号，该光信号可以为可见光、红外光等。例如，第一显示区域11未设置像素电路；此种情况下，可以提升第一显示区域11的透过率。
例如，通过使得被配置为一一对应地驱动多个第一发光元件411的多个第一像素电路412设置在第二显示区域12，并使得传感器02与第一显示区域11在显示基板01的显示面的法线方向上叠置，可以减小第一显示区域11中的元件对入射至第一显示区域11并朝向传感器02传输的光信号的遮挡，由此可以提升传感器02输出的图像的信噪比。例如，第一显示区域11可以被称为显示基板01的低分辨率区域的高透光区。
例如，传感器02可以是图像传感器，并可以用于采集传感器02的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器；该传感器02还可以是红外传感器、距离传感器等。例如，在该显示装置03为诸如手机、笔记本的移动终端的情况下，该传感器02可用于实现诸如手机、笔记本的移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。例如，该传感器02可以包括阵列排布感光像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，开关晶体管)。例如，光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
在一些示例中，第一显示区域11中仅有第一发光元件411的阳极不透光，也即，用于驱动第一发光元件411的走线绕过第一显示区域11或者设置为透明走线；此种情况下，不仅可以进一步地提升第一显示区域11的透过率，还可以降低第一显示区域11中的各个元件导致的衍射。下面结合图4所示的示例进行示例性说明。
图4是图2A所示的显示基板01的第一个示例。图5A是用于示出图4所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第一个示意图。
如图4和图5A所示，该显示基板01包括至少一根第一信号线20、至少一根第二信号 线30和至少一根连接走线60。需要说明的是，为清楚起见，图4放大了第一显示区域11和第二显示区域12的尺寸，并缩小了第三显示区域13在第一方向D1上的尺寸。为方便描述，图4还示出了数据驱动电路。
在一个示例中，至少一根第一信号线包括多根第一信号线，至少一个第一像素电路包括多个第一像素电路；在另一个示例中，至少一根第一信号线包括一根第一信号线，至少一个第一像素电路包括多个第一像素电路；在再一个示例中，至少一根第一信号线包括多根第一信号线，至少一个第一像素电路包括一个第一像素电路。
例如，如图4和图5A所示，第一显示区域11包括至少一个第一发光元件411，第二显示区域12包括至少一个第一像素电路412；至少一根连接走线60一一对应地电连接至少一个第一像素电路412和至少一个第一发光元件411；至少一个第一像素电路412被配置为一一对应地驱动至少一个第一发光元件411。
例如，如图4和图5A所示，至少一根连接走线60从第一显示区域11沿第二方向D2延伸至第二显示区域12。需要说明的是，图5A示出的连接在每个第一像素单元41包括的第一数目的第一发光元件411和每个用于驱动第一发光元件411的第一像素驱动单元包括的第一数目的第一像素电路412之间的线段表示第一数目(例如，四根)的连接走线60。
例如，如图4和图5A所示，至少一个第一像素电路412和被至少一个第一像素电路412一一对应地驱动地至少一个第一发光元件411分别在与第一方向D1交叉(例如，垂直)的第二方向D2上并列布置。
例如，至少一根连接走线60位于第一显示区域11的部分为透明走线；此种情况下，不仅可以进一步地提升第一显示区域11的透过率以及传感器02输出的图像的信噪比，还可以避免非透明走线导致的衍射，由此可以进一步地提升传感器输出的图像的图像质量。例如，通过使得至少一根连接走线60整体由透明导电材料制成。例如，透明导电材料可以选自氧化铟锡(ITO)、氧化铟锌(IZO)等透明金属氧化物。
在一些示例中，为降低连接走线60的电阻以及提升连接走线60上信号的传输速度，连接走线可以包括彼此电连接的位于第一显示区域的第一部分和位于第二显示区域的第二部分，第一部分包括由透明导电材料制成的第一透光走线层，第二部分包括由金属材料制成的金属走线层，在此不再赘述。
例如，如图4和图5A所示，至少一根连接走线60包括多根连接走线60，至少一个第一发光元件411包括多个第一发光元件411；多根连接走线60的至少一根的长度大于相邻的两个第一像素单元41的间距的两倍。
例如，多根连接走线60的电阻彼此相等，由此可以提升驱动电流的均匀性(例如，在数据信号彼此相等的情况下)。例如，例如，如图4和图5A所示，多根连接走线60的长度彼此相等，由此可以在多根连接走线60由相同的材料制成的情况下使得多根连接走线60的电阻彼此相等。
例如，如图4和图5A所示，至少一根第一信号线20包括第一主体部21和第一绕线部22；第一主体部21沿第一方向D1延伸，第一绕线部22偏离第一主体部21的沿第一方 向D1的虚拟延长线213而走线。例如，第一绕线部22的至少部分沿与所述第一方向D1交叉的方向延伸。例如，第一绕线部22的至少部分沿与所述第一方向D1垂直的方向延伸。
例如，如图4所示，至少一根第二信号线30包括第二主体部32，第二主体部32沿第二方向D2延伸；第一主体部21的沿第一方向D1的虚拟延长线和第二主体部32的沿第二方向D2的虚拟延长线相交于第一显示区域11内。在一些示例中，第二信号线30也包括绕线部(例如，围绕第一显示区域11的绕线部)，以使得第二信号线在不穿过第一显示区的情形下，仍可以同时驱动在第二方向D2上位于第一显示区域11两侧且位于同一行中的像素电路，在此不再赘述。
需要说明的是，为了表示第一信号线和第二信号线用于驱动对应的像素电路，第一信号线和第二信号线在对应驱动的像素电路位置处交叉，但本公开的实施例不限于此。例如，第一信号线和第二信号线可以与被第一信号线和第二信号线驱动的像素电路紧密相邻但在像素电路位置处不交叉，可以使用相应的走线电连接像素电路和对应的一信号线和第二信号线。
例如，如图4所示，至少一根第一信号线20与至少一个第一像素电路412电连接，以为至少一个第一像素电路412提供第一驱动信号；至少一根第二信号线30的第二主体部32与至少一个第一像素电路412电连接，以为至少一个第一像素电路412提供不同于第一驱动信号的第二驱动信号。
例如，如图4所示，至少一根第一信号线20与数据驱动电路50电连接，以从数据驱动电路50接收第一驱动信号，即第一信号线20为数据线而第一驱动信号为数据信号。
例如，如图4所示，第一方向D1和第二方向D2分别为显示基板01的列方向和行方向；第一信号线20和第二信号线30分别为显示基板01的数据线和栅线；第一驱动信号和第二驱动信号分别为数据信号和栅极扫描信号。
例如，如图4和图5A所示，至少一根第一信号线20被配置为驱动沿第一方向D1并列布置的第一发光元件411和第三发光元件431，也即，被同一根第一信号线20驱动的第一发光元件411和第三发光元件431位于显示基板01的同一列。例如，至少一根第一信号线20被配置为驱动沿第一方向D1并列布置的第一发光元件411、第二发光元件421和第三发光元件431，也即，被同一根第一信号线20驱动的第一发光元件411、第二发光元件421和第三发光元件431位于显示基板01的显示区域的同一列中。
需要说明的是，显示基板还包括第三信号线(例如，数据线)和第四信号线(例如，栅线)，第三信号线沿第一方向D1延伸，第四信号线沿第二方向D2延伸；第三信号线和第四信号线均为直线线段，且不与第一显示区域11交叠(也即，不穿过第一显示区域11)。
例如，如图4和图5A所示，第一主体部21包括被第一显示区域11间隔开的第一子部211和第二子部212(也即，第一子部211和第二子部212分别位于第一显示区域11在第一方向D1的两侧)；第一子部211和第二子部212经由第一绕线部22电连接；第一绕线部22偏离位于第一子部211和第二子部212之间的沿第一方向D1延伸的虚拟连线(也即，第一主体部21的沿第一方向D1的虚拟延长线213)而走线。例如，第一子部211和 第二子部212均为直线线段。
例如，如图4和图5A所示，通过使得第一绕线部22偏离第一主体部21的沿第一方向D1的虚拟延长线而走线，可以避免第一信号线20与被该第一信号线20驱动的第一发光元件411及其附近的区域交叠，由此可以提升与被该第一信号线20驱动的第一发光元件411附近的显示区域10的透过率。
例如，如图4和图5A所示，第二显示区域12具有内边缘121和外边缘122。例如，如图4和图5A所示，第二显示区域12的内边缘121由位于第二显示区域12的最内侧的一圈像素电路(例如，第一像素电路412和第二像素电路422)的靠近第一显示区域11的边界构成，也即，第二显示区域12的内边缘121由位于第二显示区域12的最靠近第一显示区域11的一圈像素电路的靠近第一显示区域11的边界构成。
例如，如图4和图5A所示，第二显示区域12的内边缘121围绕第一绕线部22；此种情况下，可以避免第一绕线部22与位于第二显示区域12中的像素电路(例如，第一像素电路412和第二像素电路422)短接。
在第一个示例中，第二显示区域12的内边缘121围绕第一绕线部22且第一绕线部22围绕第一显示区域11，此种情况下，不仅可以避免第一绕线部22对入射至第一显示区域11并朝向传感器02传输的光信号的遮挡，还可以避免第一绕线部22对位于第一显示区域11的第一发光元件411发射的光线的遮挡，由此不仅可以提升传感器02输出的图像的信噪比以及避免第一绕线部22导致的衍射，还可以提升第一显示区域11的显示质量。
在第二个示例中，第二显示区域12的内边缘121围绕第一绕线部22且第一绕线部22围绕第一显示区域11的有效边界，此种情况下，可以避免第一绕线部22对入射至第一显示区域11的有效边界内并朝向传感器02传输的光信号的遮挡，由此可以提升传感器02输出的图像的信噪比以及第一显示区域11的显示质量。例如，第一显示区域11的有效边界由位于第一显示区域11的位于最外侧的一圈第一发光元件411的外边界构成，此种情况下，可以避免第一绕线部22对位于第一显示区域11的第一发光元件411发射的光线的遮挡，由此可以提升第一显示区域11的显示质量。又例如，第一显示区域11的有效边界由位于第一显示区域11的位于次外侧的一圈第一发光元件411(也即，去除位于第一显示区域11的最外侧的一圈第一发光元件411后剩余的第一发光元件411中位于最外侧的一圈发光元件)的外边界构成；此种情况下，第一绕线部22可以与位于第一显示区域11的位于最外侧的一圈第一发光元件411至少部分交叠，由此可以略微降低第一显示区域11的有效面积的情况下增加第一绕线部22的布线空间。
例如，如图5A所示，第一显示区域11的形状为矩形；第一绕线部22包括顺次相连的第一线段221、第二线段222和第三线段223；第一线段221的不与第二线段222相连的端部与第一子部211的靠近第二子部212的端部相连；第三线段223的不与第二线段222相连的端部与第二子部212的靠近第一子部211的端部相连；第二线段222沿第一方向D1延伸，第一线段221和第三线段223沿与第一方向D1交叉的第二方向D2延伸。例如，第一线段221、第二线段222和第三线段223均为直线线段。
例如，如图4和图5A所示，第二线段222在第二方向D2上可以位于第二显示区域12的最内侧(也即，靠近第一显示区域11的一侧)的像素电路和第一显示区域11的最外侧的像素电路之间。
例如，如图4和图5A所示，显示基板01还可以包括第二绕线部23。例如，第二绕线部23的至少部分沿与第一方向D1交叉(例如，垂直)的方向而走线。例如，第二绕线部23的第一端与第二子部212电连接，第二绕线部23的第二端与对应的第一像素电路412电连接。例如，如图4和图5A所示，第二绕线部23的第二端可以与同一列第一像素电路412(例如，与第二绕线部23的第二线部232直接相邻的同一列第一像素电路412)电连接。
例如，如图4和图5A所示，第二绕线部23包括顺次相接的第一线部231和第二线部232；第一线部231的不与第二线部232相连的一端作为第二绕线部23的第一端；第二线部232的不与第一线部231相连的一端作为第二绕线部23的第二端；第一线部231沿第二方向D2延伸；第二线部232沿第一方向D1延伸且与第二子部212在第二方向D2上并列布置。例如，第二线部232为直线线段。例如，第一线部231可以为直线线段。又例如，第一线部231可以为具有弯折结构，且整体沿第二方向D2延伸。
例如，通过使得第一信号线20包括第二绕线部23，可以使用同一根第一信号线20连接分别用于驱动位于同一列的第一发光元件411和第三发光元件431的位于不同列的像素电路，此种情况下，可以使得数据驱动电路50提供的数据信号与发光元件的位置直接对应，由此可以无需改变提供数据信号的算法，以及改变数据驱动电路50的设置，无需为具有绕线部的数据线单独提供数据驱动电路，由此可以降低数据驱动电路50或相关的控制器和处理器的运算量。例如，通过使得第一信号线20包括第二绕线部23，无需将用于向被配置为驱动第一发光元件的第一像素电路提供数据信号的第一信号线从与上述第一发光元件的位于同一列的第一信号线(第一信号线的位于第三显示区域部分与第一发光元件的位于同一列)调整为与上述第一像素电路的位于同一列的第一信号线(第一信号线的位于第三显示区域部分与第一像素电路的位于同一列)。
例如，在工作中，第二线部232中的电流走向与主体部中的电流走向相反。例如，第一主体部21中的电流走向为由显示基板01的下侧(设置了数据驱动电路50的一侧)向显示基板01的上侧流动，第二线部232中的电流走向为由显示基板01的上侧向显示基板01的下侧流动。
图5B是用于示出图4所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第二个示意图，图5C是用于示出图4所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第三个示意图。图5B为图5C的上半部分。
图5C与图5A相似，图5C与图5A区别在于，图5C示出了更多的第一发光元件411、连接走线60、第一像素电路412、第一信号线20、第二发光元件421和第二像素电路422，并且图5C还示出了与第二像素电路422电连接的第五信号线71(例如，数据线)。
例如，如图5B和图5C所示，第五信号线71也具有绕线部。例如，第五信号线71也 具有绕线部围绕第一显示区域11的有效边界，且第二显示区域12的内边缘围绕第五信号线71的绕线部。
例如，如图5A-图5C所示，显示基板01包括多根第一信号线20，多根第一信号线20包括的多个第一线部231在第一方向D1上并列布置(也即，在第一方向D1上至少部分重叠)。
例如，如图5A-图5C所示，多根第一信号线20包括的多个第一线部231在第二方向D2上的长度彼此相等，由此可以进一步地提升第一线部231上驱动电流的均匀性(例如，在数据信号彼此相等的情况下)。
例如，第一主体部21、第一绕线部22和第二线部232位于显示基板01的第一电极层；第一线部231位于显示基板01的第二电极层；第一电极层和第二电极层在显示基板01的显示面的法线方向上叠置；第一线部231分别经由位于第一电极层和第二电极层之间的绝缘层的第一过孔和第二过孔与第二子部212和第二线部232电连接。
例如，通过使得每根第一信号线20的第二绕线部23的第一线部231与每根第一信号线20的其它部分(例如，第二线部232和第二子部212)，可以避免每根第一信号线20的第二绕线部23的第一线部231与其它第一信号线20短接。
例如，第一电极层和第二电极层均由金属材料制成。例如，金属材料可以选自银(Ag)、铝(Al)、钼(Mo)、钛(Ti)、铝合金或者其它适合的材料。
下面结合图5D-图5G示例性的说明第一发光元件411、第一像素电路412、第二像素单元42和第三像素单元43的具体结构以及第一信号线20的各个部分与像素电路的薄膜晶体管的各个部件的关系。
图5D示出了本公开的至少一个实施例提供的第一发光元件411以及驱动第一发光元件411的第一像素电路412的叠层结构示意图。例如，第一像素电路412包括薄膜晶体管412T和存储电容412C等结构。第一发光元件411包括第一阳极结构4111、第一阴极结构4113以及第一阳极结构4111与第一阴极结构4113之间的第一发光层4112，第一阳极结构4111通过过孔与第一像素电路412包括的薄膜晶体管412T电连接。例如，第一阳极结构4111可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未标示)，本公开的实施例对第一阳极结构4111的具体形式不做限定。例如，第一阴极结构4113可以为显示基板01上整个表面上形成的结构，第一阴极结构4113例如可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。例如，由于第一阴极结构4113可以形成为很薄的一层，因此第一阴极结构4113具有良好的透光性。
例如，薄膜晶体管412T包括有源层4121、栅极4122和源漏电极(即源极4123和漏极4124)等结构，存储电容412C包括第一电容极板4125和第二电容极板4126。例如，有源层4121设置在衬底基板74上，有源层4121的远离衬底基板74的一侧设置有第一栅绝缘层741，栅极4122和第一电容极板4125同层设置，且位于第一栅绝缘层741的远离衬底基板74的一侧，栅极4122和第一电容极板4125的远离衬底基板74的一侧设置有第二栅绝缘层742，第二电容极板4126设置在第二栅绝缘层742的远离衬底基板74的一侧， 第二电容极板4126的远离衬底基板74的一侧设置有层间绝缘层743，源漏电极设置在层间绝缘层743的远离衬底基板74的一侧，并通过位于第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4121电连接，源漏电极的远离衬底基板74的一侧设置有平坦化层744，以平坦化第一像素电路412。
例如，平坦化层744中具有过孔，第一阳极结构4111通过平坦化层744中过孔与薄膜晶体管412T的源极4123或漏极4124电连接。
例如，第一显示区域11还包括位于衬底基板74上的透明支撑层78，第一发光元件11位于透明支撑层78的远离衬底基板74的一侧。由此，相对于衬底基板74来说，第一显示区域11中的第一发光元件411可以与第二显示区域12中的第二发光元件421以及第三显示区域13中的第三发光元件431处于基本相同的高度，从而可以提高显示基板的显示效果。
图5E示出了本公开的至少一个实施例提供的一种第二像素单元42的叠层结构示意图，如图5E所示，第二像素单元42包括第二发光元件421以及驱动第二发光元件421的第二像素电路422。例如，第二像素电路422包括薄膜晶体管422T和存储电容422C等结构。第二发光元件421包括第二阳极结构4211、第二阴极结构4213以及第二阳极结构4211与第二阴极结构4213之间的第二发光层4212，第二阳极结构4211通过过孔744A与第二像素电路422包括的薄膜晶体管422T电连接。例如，第二阳极结构4211可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未示出)，本公开的实施例对第二阳极结构4211的具体形式不做限定。
例如，薄膜晶体管422T包括有源层4221、栅极4222和源漏电极(即源极4223和漏极4224)等结构，存储电容422C包括第一电容极板4225和第二电容极板4226。例如，有源层4221设置在衬底基板74上，有源层4221的远离衬底基板74的一侧设置有第一栅绝缘层741，栅极4222和第一电容极板4225同层，且设置在第一栅绝缘层741的远离衬底基板74的一侧，栅极4222和第一电容极板4225的远离衬底基板74的一侧设置有第二栅绝缘层742，第二电容极板4226设置在第二栅绝缘层742的远离衬底基板74的一侧，第二电容极板4226的远离衬底基板74的一侧设置有层间绝缘层743，源漏电极设置在层间绝缘层743的远离衬底基板74的一侧，并通过位于第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4221电连接，源漏电极的远离衬底基板74的一侧设置有平坦化层744，以平坦化第二像素电路422。
例如，平坦化层744中具有过孔744A，第二阳极结构4211通过平坦化层744中过孔744A与薄膜晶体管422T的源极4223或漏极4224电连接。
需要说明的是，为清楚起见，图5E仅示出了第二像素单元42包括的一个第二发光元件421和一个第二像素电路422，且仅示出第二像素电路422包括的一个薄膜晶体管422T和一个存储电容422C，但本公开的实施例不限于此。
例如，图5F示出了本公开的至少一个实施例提供的一种第三像素单元43的叠层结构示意图，如图5F所示，每个第三子像素包括第三发光元件431以及与第三发光元件电连 接的第三像素电路432，第三像素电路432配置为驱动第三发光元件431。第三发光元件431包括第三阳极结构4311、第三阴极结构4313以及第三阳极结构4311与第三阴极结构4313之间的第三发光层4312，第三阳极结构4311通过过孔与第三像素电路432电连接。例如，第三阳极结构4311可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未示出)，本公开的实施例对第三阳极结构4311的具体形式不做限定。
例如，第三像素电路432包括薄膜晶体管432T和存储电容432C等结构。例如，薄膜晶体管432T包括有源层4321、栅极4322和源漏电极(即源极4323和漏极4324)等结构，存储电容432C包括第一电容极板4325和第二电容极板4326。例如，有源层4321设置在衬底基板74上，有源层4321的远离衬底基板74的一侧设置有第一栅绝缘层741，栅极4322和第一电容极板4325同层，且设置在第一栅绝缘层741的远离衬底基板74的一侧，栅极4322和第一电容极板4325的远离衬底基板74的一侧设置有第二栅绝缘层742，第二电容极板4326设置在第二栅绝缘层742的远离衬底基板74的一侧，第二电容极板4326的远离衬底基板74的一侧设置有层间绝缘层743，源漏电极设置在层间绝缘层743的远离衬底基板74的一侧，并通过第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4321电连接，源漏电极的远离衬底基板74的一侧设置有平坦化层744，以平坦化第三像素电路432。
例如，平坦化层744中具有过孔744B，第三阳极结构4311通过绝缘层745中的过孔744B与薄膜晶体管432T的源极4323或漏极4324电连接。
需要说明的是，为清楚起见，图5F仅示出了第三像素单元43包括的一个第三发光元件431和一个第三像素电路432，且仅示出第三像素电路432包括的一个薄膜晶体管432T和一个存储电容432C，但本公开的实施例不限于此。
例如，第一像素电路412、第二像素电路422、第三像素电路432是同层设置的，因此在制备工艺中可采用相同的构图工艺形成。例如，第一栅极绝缘层741、第二栅极绝缘层742、层间绝缘层743以及平坦化层744在第一显示区域11、第二显示区域12和第三显示区域13是同层设置的，在一些实施例中还是一体连接(也即，一体形成且彼此连接)的，因此在附图中采用了相同的标号。
例如，在一些实施例中，显示基板还包括像素界定层746、封装层747等结构，例如，像素界定层746设置在第一阳极结构上，包括多个开口以界定不同的像素或子像素，第一发光层形成在像素界定层746的开口中。例如，封装层747可以包括单层或多层封装结构，多层封装结构例如包括无机封装层和有机封装层的叠层，由此提高对显示基板的封装效果。
例如，第一显示区域11、第二显示区域12和第三显示区域13中的像素界定层746是同层设置的，第一显示区域11、第二显示区域12和第三显示区域13中的封装层747是同层设置的，在一些实施例中还是一体连接的，因此在附图中采用了相同的标号。
例如，本公开的各个实施例中，衬底基板74可以为玻璃基板、石英基板、金属基板或树脂类基板等，可以是刚性基板或柔性基板。本公开的实施例对此不作限制。
例如，第一栅极绝缘层741、第二栅极绝缘层742、层间绝缘层743以及平坦化层744、绝缘层745、像素界定层746、封装层747以及绝缘层748可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对上述各功能层的材料均不做具体限定。
例如，有源层4121/4221/4321的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等半导体材料。例如，有源层4121/4221/4321的部分可以通过掺杂等导体化处理以导体化，从而具有较高的导电性。
例如，在上述各个示例中，栅极4122/4222/4322、第一电容极板4125/4225/4325和第二电容极板4126/4226/4326的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。
例如，源极4123/4223/4323和漏极4124/4224/4324的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/T i)等。
例如，本公开实施例提供的显示基板可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等显示基板，本公开的实施例对显示基板的具体种类不做限定。
例如，在显示基板为有机发光二极管显示基板的情形，发光层4111/4211/4311可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等。并且，根据实际不同需要，在不同的示例中，发光层4111/4211/4311还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。
例如，在显示基板为量子点发光二极管(QLED)显示基板的情形，发光层4111/4211/4311可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
图5G是本公开的至少一个实施例提供的第二像素单元42、第二绕线部23的第一线部231和第一主体部21的第二子部212的叠层结构示意图。例如，如图5G所示，第一主体部21的第二子部212、源极4223和漏极4224位于显示基板01的第一电极层251，例如，第一主体部21的第一子部211、第一绕线部22和第二绕线部23的第二线部232也位于第一电极层251。例如，如图5F所示，第二绕线部23的第一线部231、栅极4222和第一电容极板4225位于显示基板01的第二电极层252。例如，如图5G所示，第一线部231分别经由位于第一电极层251和第二电极层252之间的绝缘层的第一过孔254和第二过孔255与第二子部212和第二线部232电连接，也即，第一信号线20采用了跳线设计，例如可以采用包括多次跳线的设计。在一些示例中，第二绕线部23的第一线部231和第二电容极板4226位于显示基板01的第二电极层252，在此不做赘述。例如，第二信号线30的第二主 体部32也位于显示基板01的第二电极层252。
图5H示出了本公开的至少一个实施例提供的一种第二像素单元42的另一种叠层结构示意图，如图5H所示，第二像素单元42包括第二发光元件421以及驱动第二发光元件421的第二像素电路422。例如，第二像素电路422包括薄膜晶体管422T和存储电容422C等结构。第二发光元件421包括第二阳极结构4211、第二阴极结构4213以及第二阳极结构4211与第二阴极结构4213之间的第二发光层4212，第二阳极结构4211通过过孔744A与转接电极749电连接，转接电极749经由过孔744B与第二像素电路422包括的薄膜晶体管422T电连接。例如，第二阳极结构4211可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未示出)，本公开的实施例对第二阳极结构4211的具体形式不做限定。例如，转接电极749可以由透明导电材料制成。例如，透明导电材料可以选自氧化铟锡(ITO)、氧化铟锌(IZO)等透明金属氧化物。
例如，薄膜晶体管422T包括有源层4221、栅极4222和源漏电极(即源极4223和漏极4224)等结构，存储电容422C包括第一电容极板4225和第二电容极板4226。例如，有源层4221设置在衬底基板74上，有源层4221的远离衬底基板74的一侧设置有第一栅绝缘层741，栅极4222和第一电容极板4225同层，且设置在第一栅绝缘层741的远离衬底基板74的一侧，栅极4222和第一电容极板4225的远离衬底基板74的一侧设置有第二栅绝缘层742，第二电容极板4226设置在第二栅绝缘层742的远离衬底基板74的一侧，第二电容极板4226的远离衬底基板74的一侧设置有层间绝缘层743，源漏电极设置在层间绝缘层743的远离衬底基板74的一侧，并通过位于第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4221电连接；源漏电极的远离衬底基板74的一侧设置有钝化层748；钝化层748的远离衬底基板74的一侧设置有第一平坦化层744，以平坦化第二像素电路422；转接电极749设置在第一平坦化层7441的远离衬底基板74的一侧；转接电极749的远离衬底基板74的一侧设置有第二平坦化层7442。
例如，第一平坦化层7441中具有过孔744B，转接电极749通过第一平坦化层7441中过孔744B与薄膜晶体管422T的源极4223或漏极4224电连接。例如，平坦化层744中具有过孔744A，第二阳极结构4211通过第二平坦化层7442中过孔744A与转接电极749电连接，由此第二阳极结构4211可以与薄膜晶体管422T的源极4223或漏极4224电连接。
例如，如图5H所示，显示基板还包括像素界定层746、封装层747等结构，例如，像素界定层746设置在第一阳极结构上，包括多个开口以界定不同的像素或子像素，第一发光层形成在像素界定层746的开口中。例如，封装层747可以包括在垂直于显示基板的方向上顺次设置在第二阴极结构4213上的第一封装层7471、第二封装层7472和第三封装层7473。例如，第一封装层7471、第二封装层7472和第三封装层7473分别为无机封装层、有机封装层和无机封装层。
需要说明的是，为清楚起见，图5H仅示出了第二像素单元42包括的一个第二发光元件421和一个第二像素电路422，且仅示出第二像素电路422包括的一个薄膜晶体管 422T和一个存储电容422C，但本公开的实施例不限于此。
需要说明的是，在本公开的至少一个实施例提供的第二像素单元42采用图5H所示的结构的情况下，本公开的至少一个实施例提供的第三像素单元43以及本公开的至少一个实施例提供的第一发光元件411以及驱动第一发光元件411的第一像素电路412也可以采用图5H所示的结构，在此不再赘述。
图5I是沿图5A所示的HH’线的截面示意图。例如，如图5I所示，第一主体部21的第二子部212和第二绕线部23的第二线部232位于层间绝缘层743的远离衬底基板74的一侧，也即，第一主体部21的第二子部212和第二绕线部23的第二线部232与薄膜晶体管的源漏电极(例如，源极4223和漏极4224)设置在同一电极层(例如，第一电极层251)。例如，第一主体部21的第一子部211和第一绕线部22也位于上述同一电极层(例如，第一电极层251)。
例如，如图5I所示，第二绕线部23的第一线部231位于第一栅绝缘层741和第二栅绝缘层742之间，也即，第二绕线部23的第一线部231、栅极4222和第一电容极板4225位于同一电极层(例如，位于显示基板01的第二电极层252)。例如，如图5I所示，第一线部231分别经由位于第一电极层251和第二电极层252之间的绝缘层的第一过孔254和第二过孔255与第二子部212和第二线部232电连接，也即，第一信号线20采用了跳线设计，例如可以采用包括多次跳线的设计。例如，第二信号线30的第二主体部32也位于显示基板01的第二电极层252。在一些示例中，第二绕线部23的第一线部231和第二电容极板4226位于同一电极层(例如，显示基板01的第二电极层252)，栅极4222不位于上述同一电极层(例如，显示基板01的第二电极层252)。
例如，如图4、图5A-图5C和图5G所示，第一线部231整体位于周边区域14，且在第一方向D1上与第二显示区域12并列布置。例如，由于周边区域14不具有像素电路(第一像素电路412-第三像素电路432)，因此，可以降低第一线部231的布线难度。
例如，如图4和图5A-图5C所示，第一线部231在第一方向D1上整体位于第二显示区域12的远离第三显示区域13的一侧。例如，如图4和图5A-图5C所示，第一线部231整体位于显示基板01的上边缘。
需要说明的是，尽管图4、图5A-图5C和图5G所示的第一线部231整体位于周边区域14，但本公开的实施例不限于此，根据实际应用需求，第一线部231还可以整体位于第二显示区域12或者第一线部231同时位于周边区域14和第二显示区域12。下面结合图6、图7A-图7B、图8和图9A-图9B进行示例性说明。
图6是图2A所示的显示基板01的第二个示例。图7A是用于示出图6所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第一个示意图，图7B是用于示出图6所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第二个示意图。
例如，如图6和图7A-图7B所示，第一线部231整体位于第二显示区域12中，且在第一方向D1上与第一显示区域11并列布置。例如，如图6和图7A-图7B所示，第一线 部231在第一方向D1上位于第一显示区域11的远离第三显示区域13的一侧。
在一个示例中，多根第一信号线20包括的多个第一线部231均为平直的(也即，直线线段)。在另一个示例中，多根第一信号线20包括的至少部分第一线部231可以具有弯折结构，以避免部分第一线部231与第二发光元件421交叠，遮挡第二发光元件421发射的光线。
例如，通过使得第一线部231整体位于第二显示区域12，可以降低显示基板01的周边区域14的尺寸，由此有利于显示基板01的窄边框或全面屏设计。
需要说明的是，图6所述的显示基板01的其它结构和具体实现方式与图4所述的显示基板01的其它结构和具体实现方式相同或相似，相同或相似之处不做赘述。
需要说明的是，相比于连接走线60，第一发光元件411和第二发光元件421更远离显示基板01的衬底基板；图7A所示的平面示意图以及其它相关的平面示意图用于示出显示基板01的各个元件在平行于显示基板01的衬底基板的平面内的排布方式和连接方式，而不用于限制显示基板01的各个元件在垂直于显示基板01的衬底基板的方向上的排布方式或者相对位置关系。显示基板01的各个元件在垂直于显示基板01的衬底基板的方向上的排布方式和相对位置关系可以参见图5D-图5H所示的叠层结构示意图以及图5I所示的截面示意图，在此不再赘述。
图8是图2A所示的显示基板01的第三个示例。图9A是用于示出图8所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第一个示意图，图9B是用于示出图8所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第二个示意图。
例如，如图8和图9A-图9B所示，第一线部231包括顺次相接的第一部分2311、第二部分2312和第三部分2313；第一线部231的第一部分2311与第二子部212电连接，第一线部231的第三部分2313与第二线部232电连接；第一线部231的第一部分2311位于周边区域14，且在第一方向D1上与第二显示区域12并列布置；第一线部231的第二部分2312从周边区域14沿第一方向D1延伸至第二显示区域12；第一线部231的第三部分2313位于第二显示区域12，且第一线部231的第三部分2313的沿第二方向D2延伸的虚拟延长线在第一方向D1上与第一显示区域11并列布置。
在一些示例中，第一线部231的第三部分2313与第二子部212电连接，第一线部231的第一部分2311与第二线部232电连接，也即，第一线部231与第二子部212电连接部分位于第二显示区域12，第一线部231与第二线部232电连接部分位于周边区域14，在此不再赘述。
需要说明的是，图8所述的显示基板01的其它结构和具体实现方式与图4所述的显示基板01的其它结构和具体实现方式相同或相似，相同或相似之处不做赘述。
需要说明的是，尽管图4、图6和图8所示的显示基板01的第二绕线部23均经由第一显示区域11在第一方向D1上远离第三显示区域13的一侧由第一主体部21的第二子部212绕线至与第一主体部21的第二子部212并列(在第二方向D2上并列)的位置处，然 而本公开的实施例不限于此。在一些示例中，第二绕线部23可以从第一主体部21的第一子部211经由第一显示区域11在第一方向D1上靠近第三显示区域13的一侧绕线至与第一主体部21的第二子部212并列(在第二方向D2上并列)的位置处，下面结合图10进行示例性说明。
图10是图2A所示的显示基板01的第四个示例。图10所示的显示基板01与图6所示的显示基板01类似，在此仅阐述两者的不同之处，相同之处不再赘述。图10所示的显示基板01与图6所示的显示基板01的区别在于，图10所示的显示基板01的第一线部231在第一方向D1上位于第一显示区域11的靠近第三显示区域13的一侧，并且，在工作中，图10所示的显示基板01的第二线部232中的电流走向与所述主体部中的电流走向相同。
在一些示例中，在第一方向D1上，第一线部231的至少部分(例如，全部)可以与第一显示区域11并列布置，且位于第三显示区域13的靠近第一显示区域11的一端，在此不再赘述。
需要说明的是，尽管图4、图6、图8和图10所示的显示基板01的第一信号线20均从第一显示区域11的在第一方向D1上的一侧绕线至与第一主体部21并列(在第二方向D2上并列)的位置处，然而，本公开的实施例不限于此。在一些示例中，显示基板01的第一信号线20可以从第一显示区域11的在第一方向D1上的两侧绕线至与第一主体部21并列(在第二方向D2上并列)的位置处。下面结合图11和图12A-图12C进行示例性说明。
图11是图2A所示的显示基板01的第五个示例。图12A是用于示出图11所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第一个示意图，图12B是用于示出图11所示的显示基板01第一显示区域11、第二显示区域12和部分周边区域14的第二个示意图；图12C是对应于图12B的部分区域REG_E的平面示意图。
图11所示的显示基板01与图4所示的显示基板01类似，在此仅阐述两者的不同之处，相同之处不再赘述。图11所示的显示基板01与图4所示的显示基板01的区别在于，显示基板01还包括第三绕线部24。例如，第三绕线部24的至少部分沿与第一方向D1交叉(例如，垂直)的方向而走线。
例如，如图11和图12A-图12B所示，第三绕线部24的第一端与第一子部211电连接，第三绕线部24的第二端与对应的第一像素电路412电连接，与第二绕线部23相连的第一像素电路412不同于与第三绕线部24相连的第一像素电路412。
例如，如图11和图12A-图12B所示，与第二绕线部23相连的第一像素电路412以及与第三绕线部24相连的第一像素电路412位于同一列，也即，与第二绕线部23相连的第一像素电路412以及与第三绕线部24相连的第一像素电路412在第一方向D1上排布。例如，与第二绕线部23相连的第一像素电路412为上述同一列第一像素电路412的上半列第一像素电路412，与第二绕线部23相连的第一像素电路412为上述同一列第一像素电路412的下半列第一像素电路412。
例如，通过使得第一信号线20还包括第三绕线部24，可以使用数据线对第二显示区 域12的与第一显示区域11在第二方向D2上并列的区域中的像素电路(第一像素电路412和第二像素电路422)进行双向驱动，也即，从第二显示区域12的与第一显示区域11在第二方向D2上并列的区域的上方和下方向位于该区域中的像素电路输入数据信号；此种情况下，第二显示区域12的开口(例如，第二显示区域12的内边缘121)的尺寸更大。
例如，如图11和图12A-图12B所示，第三绕线部24包括顺次相接的第三线部241和第四线部242；第三线部241不与第四线部242相连的一端作为第三绕线部24的第一端，第四线部242的不与第三线部241相连的一端作为第三绕线部24的第二端；第三线部241沿第二方向D2延伸，且与第一线部231在第一方向D1上并列布置；第四线部242沿第一方向D1延伸且与第一子部211在第二方向D2上并列布置；在工作中，第四线部242中的电流走向与主体部中的电流走向相同。例如，第四线部242为直线线段。例如，第三线部241可以为直线线段。又例如，第三线部241可以为具有弯折结构，且整体沿第二方向D2延伸。
例如，第四线部242位于显示基板01的第一电极层；第三线部241位于显示基板01的第二电极层；第三线部241分别经由位于第一电极层和第二电极层之间的绝缘层的第三过孔和第四过孔与第一子部211和第四线部242电连接。
例如，通过使得每根第一信号线20的第二绕线部23的第一线部231以及第三绕线部24的第三线部241与每根第一信号线20的其它部分(例如，第四线部242和第一子部211)，可以避免每根第一信号线20的第二绕线部23的第一线部231和第三绕线部24的第三线部241与其它第一信号线20短接。
例如，如图12C所示，第一显示区域11仅包括多根并列布置的透明走线和阳极结构4111，由此可以提升第一显示区域11的透射率。例如，如图12C所示，如图12C所示，多根并列布置的透明走线包括连接走线60和虚拟(dummy)走线601。例如，虚拟走线601具有断口，由此使得虚拟走线601为不连续的走线。例如，通过设置具有断口的虚拟走线601，可以提升第一显示区域11的刻蚀均一性。需要说明的是，图12C中箭头所指向的线条为底纹，而不是真实的走线。
需要说明的是，图11和图12A-图12B所示的显示基板的第一线部231不限于位于周边区域14；第三线部241不限于在第一方向D1上与第一显示区域11并列布置，且位于第三显示区域13的靠近第一显示区域11的一端。在一个示例中，第一线部231和第三线部241可以均位于第二显示区域12，并且，第一线部231在第一方向D1上位于第一显示区域11的远离第三显示区域13的一侧，第三线部241在第一方向D1上位于第一显示区域11和第三显示区域13之间。在另一个示例中，第一线部231可以同时位于周边区域14和第二显示区域12，第三线部241可以同时位于第三显示区域13和第二显示区域12。
需要说明的是，尽管图4、图6、图8、图10和图11所示的显示基板01的第一显示区域11的形状均为矩形，但本公开的实施例不限于此。例如，根据实际应用需求，第一显示区域11的形状还可以为圆形或其它适用的形状；对应地，第一绕线部22的形状适应性地改变。例如，第一绕线部22的形状与第一显示区域11的形状相匹配，以降低第一绕线 部22对位于第一显示区域11和第二显示区域12中元件的影响。下面结合图13A-图13D进行示例性说明。
图13A是图2A所示的显示基板01的第六个示例的一种平面示意图，图13B是图2A所示的显示基板01的第六个示例的另一种平面示意图，图13C是图2A所示的显示基板01的第六个示例的再一种平面示意图。图13D是对应于图13C所示的部分区域REG_B的平面示意图。
需要说明的是，为清楚起见，图13A仅示出了显示基板01的部分第二显示区域12和部分周边区域14，图13B和图13C仅示出了显示基板01的部分第一显示区域11、部分第二显示区域12和部分周边区域14。
图13A-图13C所示的显示基板01与图4和图5A-图5C所示的显示基板01类似，在此仅阐述两者的不同之处，相同之处不再赘述。图13A-图13C所示的显示基板01与图4和图5A-图5C所示的显示基板01的区别在于，图13A-图13C所示的显示基板01的第一显示区域11的形状以及第一绕线部22的形状不同。
如图13A-图13C所示，第一显示区域11的形状为圆形；第一绕线部22为弧线，弧线的第一端与第一子部211的靠近第二子部212的端部相连，弧线的第二端与第二子部212的靠近第一子部211的端部相连。例如，上述弧线的曲率与上述圆形的曲率的彼此匹配(例如，相等)。
需要说明的是，根据实际应用需求，还可以将图6、图8、图10和图11所示的显示基板01的第一显示区域11的形状修改为圆形，第一绕线部22修改为弧线，在此不做赘述。
例如，如图13C和图13D所示，周边区域14还包括多条走线2911和多条走线2921；多条走线2911位于电极层291，多条走线2921位于电极层292。例如，电极层291和电极层292为垂直于显示基板的方向上的不同的电极层。例如，多条走线2911和多条走线2921在垂直于走线2911的延伸方向的方向上交替布置。例如，通过使得多条走线2911和多条走线2921在垂直于走线2911的延伸方向的方向上交替布置，且使得走线2911和走线2921位于不同的电极层，可以增加走线(走线2911和走线2921整体)的设置密度。
例如，第一信号线20的第二子部212与多条走线2911位于不同的电极层，第一信号线20的第二子部212与多条走线2921位于不同的电极层。例如，图5H所示的栅极4222和第一电容极板4225也位于电极层291；图5H所示的第二电容极板4226也位于电极层292；第一信号线20的第二子部212与图5H所示的源极4223和漏极4224位于同一电极层。
例如，如图13C和图13D所示，穿过第二像素电路422的第一信号线20的第二子部212与对应的走线2911或对应的走线2921电连接(例如，经由过孔电连接)，由此，第一信号线20的第二子部212上的信号换层至对应的走线2911或对应的走线2921上传输。例如，与第一信号线20的第二子部212电连接的走线2911或走线2921被称为第一线部231。例如，通过使得穿过第二像素电路422的第一信号线20的第二子部212与对应的走线2911或对应的走线2921电连接。
例如，每一个像素单元出来的第一信号线(位于SD层)均会通过换层至Gat1(电极层291)或者Gat2层(电极层292)。例如，若纵向上的引线和横向上的引线存在交叉，则纵向上的引线(第一信号线20的第二子部212)采用SD层，这是因为SD层与Gat层(电极层291或292)之间的距离会大于Gat1(电极层291)和Gat2层(电极层292)之间的距离，由此可以减小电容耦合。
需要说明的是，尽管图4、图6、图8、图10、图11、图13A-图13C所示的显示基板01的第二显示区域12的形状均为矩形，但本公开的实施例不限于此。例如，根据实际应用需求，第二显示区域12的形状还可以为圆形或其它适用的形状，在此不做赘述。
需要说明的是，尽管图4、图6、图8、图10、图11、图13A-图13C所示的显示基板01的第一信号线20均采用了两个或者更多的绕线部将第一信号线20绕线至与第一主体部21并列(在第二方向D2上并列)的位置处，但本公开的实施例不限于此。例如，根据实际应用需求，显示基板01的第一信号线20可以仅采用一个绕线部将第一信号线20绕线至与第一主体部21并列(在第二方向D2上并列)的位置处，下面结合图14进行示例性说明。
图14是图2A所示的显示基板01的第七个示例的一种平面示意图。图14所示的显示基板01与图4所示的显示基板01类似，在此仅阐述两者的不同之处，相同之处不再赘述。图14所示的显示基板01与图4所示的显示基板01的区别包括：图14所示的显示基板01仅具有第一绕线部22，而不具有第二绕线部23。
例如，如图14所示，第一绕线部22围绕第一显示区域11，且整体位于第二显示区域12。例如，如图14所示，第一绕线部22包括顺次相接的第五线部271、第六线部272和第七线部273；第五线部271与第一子部211电连接，第七线部273与第二子部212电连接；第六线部272沿第一方向D1延伸，第五线部271和第七线部273沿与第一方向D1交叉的第二方向D2延伸；第六线部272与位于第一子部211和第二子部212之间的沿第一方向D1延伸的虚拟连线在第一方向D1上并列布置；第六线部272和与第六线部272电连接的第一像素电路412至少部分交叠(或者位于同一列，紧密相邻但不交叠)；在工作中，第六线部272中的电流走向与第一主体部211中的电流走向相同。例如，第五线部271、第六线部272和第七线部273均为直线线段。
例如，数据驱动电路50可以实现为驱动芯片。例如，驱动芯片可经由柔性电路板邦定在显示基板01上，并经由柔性电路向多根数据线提供显示用的数据信号，以驱动显示基板01实现显示功能。例如，周边区域14还可以设置有栅极驱动芯片，或者形成有阵列基板上的栅驱动电路(GOA，图中未示出)，栅极驱动芯片或GOA的多个输出端分别与多根栅线相连，以向多根栅线提供栅扫描信号。需要说明的是，显示基板01不限于被单个数据驱动电路驱动，在一些示例中，显示基板01可以被两个数据驱动电路驱动，上述两个数据驱动电路位于显示基板01的两侧(例如，在第一方向D1上位于显示基板01的两侧)。
图15是图2A所示的显示基板01的第八个示例的一种平面示意图，图16是图2A所示的显示基板01的第八个示例的另一种平面示意图。需要说明的是，为清楚起见，图15 仅示出了显示基板01的第一显示区域11和部分第二显示区域12。
图15所示的显示基板01与图4所示的显示基板01类似，在此仅阐述两者的不同之处，相同之处不再赘述。图15所示的显示基板01与图4所示的显示基板01的区别包括：图15所示的显示基板01的第一方向D1为显示面板的行方向；图15所示的显示基板01的连接走线60沿列方向延伸；15所示的显示基板01的第一信号线20为栅线，第二信号线30为数据线；图15所示的显示基板01的第一信号线20和第二信号线30的绕线部的结构分别与图15所示的显示基板01的第一信号线20和第二信号线30的绕线部的结构不同。
例如，如图15所示，第一绕线部22围绕第一显示区域11，且整体位于第二显示区域12；第一绕线部22包括顺次相接的第八线部281和第九线部282；第八线部281与第一主体部21电连接，且沿第二方向D2延伸；第九线部282沿第一方向D1延伸，且与第一主体部21的虚拟延长线在第一方向D1上并列布置；在工作中，第九线部282中的电流走向与主体部中的电流走向相同；第九线部282与被配置为驱动在第一显示区域11中沿第一方向D1并列布置的第一数目的第一发光元件411的第一像素电路412电连接。例如，第八线部281和第九线部282均为直线线段。
在一些示例中，第一主体部21包括第一子部211和第二子部212(图中未示出)，第一绕线部22还包括第十线部(图中未示出)，第十线部的第一端与第九线部282相连，第十线部的第二端与第二子部212相连，第十线部沿第二方向D2延伸。
例如，如图15所示，第二信号线30包括第二主体部32、第四绕线部33和第五绕线部34；第四绕线部33偏离第二主体部32的沿第二方向D2的虚拟延长线而走线；第二主体部32包括被第一显示区域11间隔开的第三子部321和第四子部322，第三子部321和第四子部322经由第四绕线部33电连接；第四绕线部33偏离位于第三子部321和第四子部322之间的沿第二方向D2延伸的虚拟连线而走线。例如，第四绕线部33的至少部分沿与第二方向D2交叉的方向延伸。例如，第五绕线部34的至少部分沿与第二方向D2交叉的方向延伸。例如，第三子部321和第四子部322均为直线线段。
例如，如图15所示，第四绕线部33包括顺次相连的第四线段331、第五线段332和第六线段333，第四线段331的不与第五线段332相连的端部与第三子部321的靠近第四子部322的端部相连，第六线段333的不与第五线段332相连的端部与第四子部322的靠近第三子部321的端部相连，第四线段331和第六线段333沿与第一方向D1延伸，第五线段332沿第二方向D2延伸。例如，第四线段331、第五线段332和第六线段333均为直线线段。
例如，如图15所示，第五绕线部34的第一端与第二子部212电连接，第五绕线部34的第二端与对应的第一像素电路412电连接。例如，如图15所示，第五绕线部34的第二端可以与同一列第一像素电路412(例如，与第二绕线部23的第二线部232直接相邻的同一列第一像素电路412)电连接。
例如，如图15所示，第五绕线部34包括顺次相连的第七线段341和第八线段342，第七线段341的不与第八线段342相连的一端作为第五绕线部34的第一端；第八线段342 的不与第七线段341相连的一端作为第五绕线部34的第二端；第七线段341沿第一方向D1延伸；第八线段342沿第二方向D2延伸且与第二子部212在第一方向D1上并列布置；在工作中，第八线段342中的电流走向与第二子部212中的电流走向相反。例如，第七线段341和第八线段342均为直线线段。
例如，如图15所示，第一发光元件411和用于驱动该第一发光元件411的第一像素电路412位于显示面板的相邻列。例如，如图15所示，至少一根第二信号线30被配置为驱动沿第二方向D2并列布置的第一发光元件411和第二发光元件421，也即，被同一根第二信号线30驱动的第一发光元件411和第三发光元件431位于显示基板01的同一列。
需要说明的是，在一些示例中，第一发光元件411和用于驱动该第一发光元件411的第一像素电路412也可以位于显示面板的相同列，也即，第一发光元件411和用于驱动该第一发光元件411的第一像素电路412在列方向上并列布置。
例如，如图15所示，第一方向D1为显示面板的行方向，第二方向D2为显示面板的列方向；第一信号线20为栅线，第二信号线30为数据线。
需要说明的是，图15所示的显示基板01的连接走线60沿列方向延伸不限于显示基板01的连接走线60为平直的(也即，不限于显示基板01的连接走线60为直线线段)，在一些示例中，图15所示的显示基板01的连接走线60还包括沿行方向上延伸的部分。
例如，源漏极、第一绕线部和第二信号线均位于第一电极层，第一主体部、栅极和第一电容极板位于第二电极层。又例如，第一绕线部和第二信号线均位于第一电极层，第一主体部和存储电容的第二电容极板位于第二电极层。
图16与图15相似，图16示出了更多的第一信号线20，且图6未示出第二信号线30的第五绕线部34，在此不再赘述。
图17是本公开的至少一个实施例提供的像素电路921以及被该像素电极驱动的发光元件920。例如，本公开的至少一个实施例提供的第一像素电路412、第二像素电路422和第三像素电路432的至少一个(例如，全部)可以实现为图17所示的像素电路921。
例如，如图17所示，像素电路921还包括第一发光控制电路923和第二发光控制电路924。驱动电路922包括控制端、第一端和第二端，且被配置为对有机发光元件920提供驱动有机发光元件920发光的驱动电流。例如，第一发光控制电路923与驱动电路922的第一端和第一电压端VDD连接，且被配置为实现驱动电路922和第一电压端VDD之间的连接导通或断开，第二发光控制电路924与驱动电路922的第二端和有机发光元件920的第一电极电连接，且被配置为实现驱动电路922和有机发光元件920之间的连接导通或断开。
例如，如图17所示，像素电路921还包括数据写入电路926、存储电路927、阈值补偿电路928和复位电路929。数据写入电路926与驱动电路922的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路927；存储电路927与驱动电路922的控制端和第一电压端VDD电连接，且被配置为存储数据信号；阈值补偿电路928与驱动电路922的控制端和第二端电连接，且被配置为对驱动电路922进行阈值补偿；复位电路929与驱动电路922的控制端和有机发光元件920的第一电极电连接，且配置为在复位控 制信号的控制下对驱动电路922的控制端和有机发光元件920的第一电极进行复位。
例如，如图17所示，驱动电路922包括驱动晶体管T1，驱动电路922的控制端包括驱动晶体管T1的栅极，驱动电路922的第一端包括驱动晶体管T1的第一极，驱动电路922的第二端包括驱动晶体管T1的第二极。
例如，如图17所示，数据写入电路926包括数据写入晶体管T2，存储电路927包括电容C，阈值补偿电路928包括阈值补偿晶体管T3，第一发光控制电路923包括第一发光控制晶体管T4，第二发光控制电路924包括第二发光控制晶体管T5，复位电路929包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
例如，如图17所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；电容C的第一极与第一电源端VDD电连接，电容C的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与有机发光元件920的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与有机发光元件920的第二电极电连接，第二发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；有机发光元件920的第一电极与第二电源端VSS电连接。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图17所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
例如，如图17所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板1000可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅 极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图17所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板1000可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板1000可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。
例如，在一些示例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到第一扫描信号线Ga1以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T6的栅极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的栅极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件920的第一电极进行复位即可，本公开对此不作限制。
需要说明的是，图17所示的像素电路中的驱动电路922、数据写入电路926、存储电路927、阈值补偿电路928和复位电路929仅为示意性的，驱动电路922、数据写入电路 926、存储电路927、阈值补偿电路928和复位电路929等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，本公开的至少一个实施例提供的第一像素电路412、第二像素电路422和第三像素电路432不限于实现为包括七个晶体管和一个电容的像素电路(也即，不限于图17所示的7T1C像素电路)，本公开的至少一个实施例提供的第一像素电路412、第二像素电路422和第三像素电路432可以包括适用数目的晶体管和适用数目的电容。例如，根据实际应用需求，本公开的至少一个实施例提供的第一像素电路412、第二像素电路422和第三像素电路432可以为7T2C像素电路、6T1C像素电路、6T2C像素电路或者9T2C像素电路。
图18是图17所示的7T1C像素电路的结构示意图。7T1C像素电路包括的第一晶体管T1至第七晶体管的T7的位置如图18所示，在此不再赘述。
图19是示出根据本公开一个实施例的子像素的结构示意图。图20-图23是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图。图20是示出根据本公开一个实施例的子像素的LTPS层(低温多晶硅层)的平面示意图；图21是示出根据本公开一个实施例的子像素的SD层(源漏电极层)的平面示意图；图22是示出根据本公开一个实施例的子像素的Gat1层(第一栅极层)的平面示意图；图23是示出根据本公开一个实施例的子像素的Gat2层(第二栅极层)的平面示意图。图24是示出根据本公开一个实施例的子像素中图20、图22和图23所示的层叠加的布局示意图。图25是示出根据本公开一个实施例的子像素中图20至图23所示的层叠加的布局示意图。例如，LTPS层(低温多晶硅层)、Gat1层(第一栅极层)、Gat2层(第二栅极层)和SD层(源漏电极层)在垂直于子像素上的方向上由下向上顺次设置。SD层(源漏电极层)的数据线引出后会换到Gat1层(第一栅极层)和Gat2层(第二栅极层)。
如图19所示，子像素可以包括发光元件D、第一晶体管T1、电容器C、第二晶体管 T2和第三晶体管T3。发光元件D包括阳极D1和阴极D2。在一些实现方式中，发光元件D可以是OLED。这里，第一晶体管T1也可以称为开关晶体管，第二晶体管T2也可以称为驱动晶体管，第三晶体管T3也可以称为复位晶体管。
第一晶体管T1被配置为响应于栅极线Gat的扫描信号，在导通的情况下将来自数据线Dat的数据信号传输至第二晶体管T2。第二晶体管T2被配置为在导通的情况下将驱动电流Id传输至发光元件D，以驱动发光元件D发光。第三晶体管T3被配置为响应于复位线Rese的复位信号，在导通的情况下将第二晶体管T2的栅极G2的电压复位至初始化电压线Vinit的电压。
在不同的实施例中，如图19所示，子像素还可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个。这里，第四晶体管T4也可以称为补偿晶体管，第五晶体管T5也可以称为驱动控制晶体管，第六晶体管T6也可以称为发射控制晶体管，第七晶体管T7也可以称为旁路晶体管。例如，第四晶体管T4被配置为响应于扫描线Gat的扫描信号，在导通的情况下使得第二晶体管T2处于二极管连接状态。例如，第五晶体管T5和第六晶体管T6被配置为响应于控制线EM的控制信号，在导通的情况下使得发射电流Id流向发光元件D。例如，第七晶体管T7被配置为响应于复位线Rese的复位信号，在导通的情况下使得驱动电流Id的一部分作为旁路电流Ibp流过。需要说明的是，虽然图19示出的第三晶体管T3的第三栅极G3和第七晶体管T7的第七栅极G7均连接至同一复位线Rese。但是，这并非是限制性的。例如，在某些实施例中，第七晶体管T7的第七栅极G7可以连接至与复位线Rese不同的另一复位线。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P沟道薄膜晶体管。在另一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个可以为N沟道薄膜晶体管。
例如，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的每一个的有源层可以如图20所示。有源层的材料例如可以包括多晶硅，例如低温多晶硅等。每个晶体管的有源层包括两个电极区和位于两个电极区之间的沟道区。这里，两个电极区中的一个为源极区，另一个为漏极区。应理解，两个电极区中的掺杂浓度大于沟道区中的掺杂浓度。换言之，两个电极区中的每一个为导体区，而沟道区为半导体区。
参见图19和图20，第一晶体管T1包括第一有源层ACT1和连接至扫描线Gat的第一栅极G1。在一些实施例中，扫描线Gat和第一栅极G1可以一体设置。如图20所示，第一有源层ACT1包括第一电极区ACT11、第二电极区ACT12、以及位于第一电极区和第二电极区之间的第一沟道区ACT13。这里，第一电极区ACT11连接至数据线Dat，第二电极区ACT12连接至电源线VDD。例如，第一电极区ACT11可以经由图25所示的过孔V1连接至数据线Dat。在一些实施例中，第二电极区ACT12可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。例如，第五有源层ACT5可以经由图25所示的过孔V2 连接至电源线VDD。在一些实施例中，参见图21，数据线Dat和电源线VDD可以位于同一层。
需要说明的是，在本文中，两个部件位于同一层是指这两个部件是通过同一图案化工艺形成的，即，通过对同一材料层进行一次图案化形成的；或者，这两个部件位于同一膜层之上，并且与该膜层直接接触。
电容器C包括第一电极板C1和连接至电源线VDD的第二电极板C2。例如，第二电极板C2可以经由图25所示的过孔V3连接至电源线VDD。
第二晶体管T2包括第二有源层ACT2和连接至第一电极板C1的第二栅极G2。在一些实施例中，第一电极板C1和第二栅极G2可以一体设置。如图20所示，第二有源层ACT2包括第三电极区ACT21、第四电极区ACT22、以及位于第三电极区ACT21和第四电极区ACT22之间的第二沟道区ACT23。第三电极区ACT21连接至第二电极区ACT12，第四电极区ACT22连接至阳极D1。在一些实施例中，第三电极区ACT21和第二电极区ACT12可以一体设置。在一些实施例中，第三电极区ACT21可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。
第三晶体管T3包括第三有源层ACT3和连接至复位线Rese的第三栅极G3。在一些实施例中，复位线Rese和第三栅极G3可以一体设置。如图20所示，第三有源层ACT3包括第五电极区ACT31、第六电极区ACT32、以及位于第五电极区ACT31和第六电极区ACT32之间的第三沟道区ACT33。第五电极区ACT31连接至第一电极板C1，第六电极区ACT32连接至初始化电压线Vinit。例如，第五电极区ACT31可以经由图25所示的过孔V4连接至第一连接件CT1，第一电极板C1可以经由图25所示的过孔V5连接至第一连接件CT1。例如，第六电极区ACT32可以经由图25所示的过孔V6连接至第二连接件CT2，初始化电压线Vinit可以经由图25所示的过孔V7连接至第二连接件CT2。在一些实施例中，参见图21，第一连接件CT1、第二连接件CT2、数据线Dat和电源线VDD可以位于同一层。在一些实施例中，参见图22，扫描线Gat、第一电极板C1和复位线Rese可以位于同一层。在一些实施例中，参见图23，第二电极板C2和初始化电压线Vinit可以位于同一层。
参见图20和图24，第一沟道区ACT13可以是第一有源层ACT1与扫描线Gat重叠的区域，第二沟道区ACT23可以是第二有源层ACT2与第一电极板C1重叠的区域，第三沟道区ACT33可以是第三有源层ACT3与复位线Rese重叠的区域，第四沟道区ACT43可以是第四有源层ACT4与扫描线Gat重叠的区域。
参见图19和图20，发光元件D包括阳极D1和阴极D2。第一晶体管T1包括第一有源层ACT1和连接至扫描线Gat的第一栅极G1，第一有源层ACT1包括第一电极区ACT11、第二电极区ACT12、以及位于第一电极区和第二电极区之间的第一沟道区ACT13，第一电极区ACT11连接至数据线Dat，第二电极区ACT12连接至电源线VDD。
电容器C包括第一电极板C1和连接至电源线VDD的第二电极板C2。第二晶体管T2包括第二有源层ACT2和连接至第一电极板C1的第二栅极G2，第二有源层ACT2包括第 三电极区ACT21、第四电极区ACT22、以及位于第三电极区ACT21和第四电极区ACT22之间的第二沟道区ACT23，第三电极区ACT21连接至第二电极区ACT12，第四电极区ACT22连接至阳极D1。
第三晶体管T3包括第三有源层ACT3和连接至复位线Rese的第三栅极G3，第三有源层ACT3包括第五电极区ACT31、第六电极区ACT32、以及位于第五电极区ACT31和第六电极区ACT32之间的第三沟道区ACT33，第五电极区ACT31连接至第一电极板C1，第六电极区ACT32连接至初始化电压线Vinit。
下面结合图19和图20对第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7进行介绍。
第四晶体管T4包括第四有源层ACT4和连接至扫描线Gat的第四栅极G4。在一些实施例中，扫描线Gat和第四栅极G4可以一体设置。如图20所示，第四有源层ACT4包括第七电极区ACT41、第八电极区ACT42、以及位于第七电极区ACT41和第八电极区ACT42之间的第四沟道区ACT43。第七电极区ACT41连接至第二栅极G2，第八电极区ACT42连接至第四电极区ACT22。例如，第七电极区ACT41可以经由图25所示的过孔V4连接至第一连接件CT1，第二栅极G2可以经由图25所示的过孔V5连接至第一连接件CT1。在一些实施例中，第七电极区ACT41和第五电极区ACT31可以一体设置。在一些实施例中，第八电极区ACT42和第四电极区ACT22可以一体设置。在某些实施例中，第四沟道区ACT43可以包括间隔开的两部分，即，第四栅极G4可以包括两个栅极。
第五晶体管T5包括第五有源层ACT5和连接至控制线EM的第五栅极G5。如图20所示，第五有源层ACT5包括第九电极区ACT51、第十电极区ACT52、以及位于第九电极区ACT51和第十电极区ACT52之间的第五沟道区ACT53。第九电极区ACT51连接至电源线VDD，第十电极区ACT52连接至第二电极区ACT12。例如，第九电极区ACT51可以经由图25所示的过孔V2连接至电源线VDD。例如，第十电极区ACT52可以经由第三电极区ACT21连接至第二电极区ACT12。在一些实施例中，参见图22，控制线EM、扫描线Gat、第一电极板C1和复位线Rese可以位于同一层。
第六晶体管T6包括第六有源层ACT6和连接至控制线EM的第六栅极G6。如图20所示，第六有源层ACT6包括第十一电极区ACT61、第十二电极区ACT62、以及位于第十一电极区ACT61和第十二电极区ACT62之间的第六沟道区ACT63。第十一电极区ACT61连接至第四电极区ACT22，第十二电极区ACT62连接至阳极D1。在一些实施例中，第十一电极区ACT61和第四电极区ACT22可以一体设置。在一些实施例中，第十二电极区ACT62可以经由图25所示的过孔V8连接至导电层M(例如金属层)，导电层M可以经由其他过孔连接至阳极D1。在一些实施例中，参见图21，导电层M、第一连接件CT1、第二连接件CT2、数据线Dat和电源线VDD可以位于同一层。
第七晶体管T7包括第七有源层ACT7和连接至复位线Rese的第七栅极G7。在一些实施例中，复位线Rese和第七栅极G7可以一体设置。如图20所示，第七有源层ACT7包括第十三电极区ACT71、第十四电极区ACT72、以及位于第十三电极区ACT71和第十 四电极区ACT72之间的第七沟道区ACT73。第十三电极区ACT71连接至第十二电极区ACT62，第十四电极区ACT72连接至初始化电压线Vinit。例如，例如，第十四电极区ACT72可以经由图25所示的过孔V6连接至第二连接件CT2，初始化电压线Vinit可以经由图25所示的过孔V7连接至第二连接件CT2。在一些实施例中，第十四电极区ACT72和第六电极区ACT32可以一体设置。
参见图20和图24，第五沟道区ACT53可以是第五有源层ACT5与控制线EM重叠的区域，第六沟道区ACT63可以是第六有源层ACT6与控制线EM重叠的区域，第七沟道区ACT73可以是第七有源层ACT7与复位线重叠的区域。
在一些实施例中，参见图20，第一有源层ACT1、第二有源层ACT2、第三有源层ACT3、第四有源层ACT4、第五有源层ACT5、第六有源层ACT6和第七有源层ACT7可以位于同一层。
下面介绍根据本公开一些实施例的子像素的驱动方法。需要说明的是，在下面的描述中，假设子像素包括T1、T2、T3、T4、T5、T6和T7，并且，晶体管T1、T2、T3、T4、T5、T6和T7均为P型沟道晶体管。
在复位阶段，第三晶体管T3响应于复位线Rese的复位信号而导通，第二晶体管T2的第二栅极G2经由第三晶体管T3连接到初始化电压线Vinit。如此，驱动晶体管T1的第二栅极G2的电压被复位至初始化电压线Vinit的电压。
在补偿阶段，第一晶体管T1和第四晶体管T4响应于扫描线Gat的扫描信号而导通。这种情况下，第二晶体管T2处于二极管连接状态，并且处于正向偏置。第二晶体管T2的第二栅极G2的电压为来自数据线Dat的数据信号的电压Vdata与第二晶体管T2的阈值电压Vth(负数)之和，即，Vdata+Vth。此时，电容器Cst的第一电极板C1的电压为Vdata+Vth，电容器Cst的第二电极板C2的电压为电源线VDD的电压ELVDD。电容器Cst被充入与第一电极板C1和第二电极板C2之间的电压差对应的电荷。
在发光阶段，第五晶体管T5和第六晶体管T6响应于控制线EM的控制信号而导通。响应于第二晶体管T2的第二栅极G2的电压与电源线VDD的电压之间的电压差而产生驱动电流Id，驱动电流Id通过第六晶体管T6被供应至发光元件D。在发光阶段，第二晶体管T2的栅源电压Vgs保持为(Vdata+Vth)-ELVDD。驱动电流Id与(Vdata-ELVDD) 2成比例。因此，驱动电流Id与第一晶体管T1的阈值电压Vth无关。
另外，在复位阶段，第七晶体管T7响应于复位线Rese的复位信号而导通。另外，第七晶体管T7可以与第一晶体管T1和第四晶体管T4同时导通。为了避免在第二晶体管T2截止的情况下的驱动电流Id驱动发光元件D发光，驱动电流Id的一部分可以作为旁路电流Ibp通过第七晶体管T7流出。
需要说明的是，对于该显示基板01和显示装置03的其它组成部分(例如，图像数据编码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开上述任一的显示基板。 该显示装置可以实现为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种显示基板，包括显示区域，至少一根第一信号线以及至少一根连接走线，
    其中，所述显示区域包括第一显示区域和第二显示区域；
    所述第二显示区域至少部分围绕所述第一显示区域；
    所述第一显示区域包括至少一个第一发光元件，所述第二显示区域包括至少一个第一像素电路；
    所述至少一根第一信号线包括第一主体部和第一绕线部；
    所述第一主体部沿第一方向延伸，所述第一绕线部的至少部分沿与所述第一方向交叉的方向延伸；
    所述至少一根第一信号线与所述至少一个第一像素电路电连接，以为所述至少一个第一像素电路提供第一驱动信号；
    所述至少一个第一像素电路分别经由对应的连接走线与所述至少一个第一发光元件电连接；以及
    所述至少一个第一像素电路被配置为分别驱动所述至少一个第一发光元件。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域还包括第三显示区域；
    所述第三显示区域至少部分围绕所述第二显示区域；
    所述至少一个第一发光元件包括多个第一发光元件；
    所述第二显示区域包括多个第二发光元件；
    所述第三显示区域包括多个第三发光元件；以及
    所述至少一根第一信号线被配置为驱动沿所述第一方向并列布置的第一发光元件和第三发光元件。
  3. 根据权利要求1或2所述的显示基板，还包括至少一根第二信号线，
    其中，所述至少一根第二信号线包括第二主体部，所述第二主体部沿与所述第一方向交叉的第二方向延伸；
    所述第一主体部的沿所述第一方向延伸的虚拟延长线和所述第二主体部的沿所述第二方向延伸的虚拟延长线相交于所述第一显示区域内；以及
    所述至少一根第二信号线的第二主体部与所述至少一个第一像素电路电连接，以为所述至少一个第一像素电路提供不同于所述第一驱动信号的第二驱动信号。
  4. 根据权利要求3所述的显示基板，其中，所述至少一根连接走线从所述第一显示区域沿所述第二方向延伸至所述第二显示区域。
  5. 根据权利要求1-4任一项所述的显示基板，其中，所述第一主体部包括被所述第一显示区域间隔开的第一子部和第二子部；
    所述第一子部和所述第二子部经由所述第一绕线部电连接；以及
    所述第一绕线部的至少部分与位于所述第一子部和所述第二子部之间的沿所述第一方向延伸的虚拟连线交叉。
  6. 根据权利要求5所述的显示基板，其中，所述第一绕线部为弧线，所述弧线的第一端与所述第一子部的靠近所述第二子部的端部相连，所述弧线的第二端与所述第二子部的靠近所述第一子部的端部相连；或者
    所述第一绕线部包括顺次相连的第一线段、第二线段和第三线段，所述第一线段的不与所述第二线段相连的端部与所述第一子部的靠近所述第二子部的端部相连，所述第三线段的不与所述第二线段相连的端部与所述第二子部的靠近所述第一子部的端部相连，所述第二线段沿所述第一方向延伸，所述第一线段和所述第三线段沿与所述第一方向交叉的第二方向延伸。
  7. 根据权利要求5或6所述的显示基板，其中，所述第二显示区域具有内边缘和外边缘，所述第二显示区域的内边缘围绕所述第一绕线部。
  8. 根据权利要求5-7任一项所述的显示基板，其中，所述至少一根第一信号线还包括第二绕线部，
    其中，所述第二绕线部的第一端与所述第二子部电连接，所述第二绕线部的第二端与对应的第一像素电路电连接；
    所述第二绕线部包括顺次相接的第一线部和第二线部；
    所述第一线部的不与所述第二线部相连的一端作为所述第二绕线部的第一端；
    所述第二线部的不与所述第一线部相连的一端作为所述第二绕线部的第二端；
    所述第一线部沿与所述第一方向交叉的第二方向延伸；
    所述第二线部沿所述第一方向延伸且与所述第二子部在所述第二方向上并列布置；以及
    在工作中，所述第二线部中的电流走向与所述主体部中的电流走向相反。
  9. 根据权利要求8所述的显示基板，还包括围绕所述显示区域的周边区域，
    其中，所述第一线部整体位于所述周边区域，且在所述第一方向上与所述第二显示区域并列布置。
  10. 根据权利要求8所述的显示基板，其中，所述第一线部整体位于所述第二显示区域中，且所述第一线部的至少部分在所述第一方向上与所述第一显示区域并列布置。
  11. 根据权利要求8所述的显示基板，还包括围绕所述显示区域的周边区域，
    其中，所述第一线部包括顺次相接的第一部分、第二部分和第三部分；
    所述第一线部的第一部分与所述第二子部电连接，所述第一线部的第三部分与所述第二线部电连接；
    所述第一线部的第一部分位于所述周边区域，且在所述第一方向上与所述第二显示区域并列布置；
    所述第一线部的第二部分从所述周边区域沿所述第一方向延伸至所述第二显示区域；以及
    所述第一线部的第三部分位于所述第二显示区域，且所述第一线部的第三部分的沿所述第二方向延伸的虚拟延长线在所述第一方向上与所述第一显示区域并列布置。
  12. 根据权利要求8-11任一项所述的显示基板，其中，所述至少一根第一信号线还包括第三绕线部，
    其中，所述第三绕线部的第一端与所述第一子部电连接，所述第三绕线部的第二端与对应的第一像素电路电连接，与所述第二绕线部相连的第一像素电路不同于与所述第三绕线部相连的第一像素电路。
  13. 根据权利要求12所述的显示基板，其中，所述第三绕线部包括顺次相接的第三线部和第四线部；
    所述第三线部不与所述第四线部相连的一端作为所述第三绕线部的第一端，所述第四线部的不与所述第三线部相连的一端作为所述第三绕线部的第二端；
    所述第三线部沿所述第二方向延伸，且与所述第一线部在所述第一方向上并列布置；
    所述第四线部沿所述第一方向延伸且与所述第一子部在所述第二方向上并列布置；以及
    在工作中，所述第四线部中的电流走向与所述主体部中的电流走向相同。
  14. 根据权利要求8-13任一项所述的显示基板，其中，所述第一主体部、所述第一绕线部和所述第二线部位于所述显示基板的第一电极层；
    所述第一线部位于所述显示基板的第二电极层；
    所述第一电极层和所述第二电极层在所述显示基板的显示面的法线方向上叠置；以及
    所述第一线部分别经由位于所述第一电极层和所述第二电极层之间的绝缘层的第一过孔和第二过孔与所述第二子部和所述第二线部电连接。
  15. 根据权利要求14所述的显示基板，其中，所述至少一个第一像素电路的每个包括薄膜晶体管；
    所述薄膜晶体管包括栅极和源漏极；以及
    所述源漏极位于所述第一电极层，所述栅极位于所述第二电极层。
  16. 根据权利要求5所述的显示基板，其中，所述第一绕线部围绕所述第一显示区域，且整体位于第二显示区域；
    所述第一绕线部包括顺次相接的第五线部、第六线部和第七线部；
    所述第五线部与所述第一子部电连接，所述第七线部与所述第二子部电连接；
    所述第六线部沿所述第一方向延伸，所述第五线部和第七线部沿与所述第一方向交叉的第二方向延伸；
    所述第六线部与位于所述第一子部和所述第二子部之间的沿所述第一方向延伸的虚拟连线在所述第一方向上并列布置；
    所述第六线部和与所述第六线部电连接的第一像素电路至少部分交叠；以及
    在工作中，所述第六线部中的电流走向与所述主体部中的电流走向相同。
  17. 根据权利要求4所述的显示基板，其中，所述第一绕线部围绕所述第一显示区域，且整体位于第二显示区域；
    所述第一绕线部包括顺次相接的第八线部和第九线部；
    所述第八线部与所述第一主体部电连接，且沿所述第二方向延伸；
    所述第九线部沿所述第一方向延伸，且与所述第一主体部的虚拟延长线在所述第一方向上并列布置；
    在工作中，所述第九线部中的电流走向与所述主体部中的电流走向相同；以及
    所述第九线部与被配置为驱动在所述第一显示区域中沿所述第一方向并列布置的所述第一数目的第一发光元件的第一像素电路电连接。
  18. 根据权利要求17所述的显示基板，其中，所述第二信号线还包括第四绕线部，所述第四绕线部偏离所述第二主体部的沿所述第二方向的虚拟延长线而走线；
    所述第二主体部包括被所述第一显示区域间隔开的第三子部和第四子部，所述第三子部和所述第四子部经由所述第四绕线部电连接；以及
    所述第四绕线部偏离位于所述第三子部和所述第四子部之间的沿所述第二方向延伸的虚拟连线而走线。
  19. 根据权利要求18所述的显示基板，其中，所述至少一个第一像素电路的每个包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极；以及
    所述源漏极、所述第一绕线部和所述第二信号线均位于所述第一电极层，所述第一主体部和所述栅极位于第二电极层。
  20. 根据权利要求1-19任一项所述的显示基板，其中，所述至少一根连接走线位于所述第一显示区域的部分为透明走线。
  21. 一种显示装置，包括如权利要求1-20任一项所述的显示基板。
  22. 根据权利要求21所述的显示装置，还包括传感器，其中，所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
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