WO2021238484A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021238484A1
WO2021238484A1 PCT/CN2021/087457 CN2021087457W WO2021238484A1 WO 2021238484 A1 WO2021238484 A1 WO 2021238484A1 CN 2021087457 W CN2021087457 W CN 2021087457W WO 2021238484 A1 WO2021238484 A1 WO 2021238484A1
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WIPO (PCT)
Prior art keywords
signal line
pixel circuit
light
display area
display
Prior art date
Application number
PCT/CN2021/087457
Other languages
English (en)
French (fr)
Inventor
蔡建畅
杜丽丽
王彬艳
邱远游
程羽雕
杨国波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/599,258 priority Critical patent/US11985874B2/en
Priority to EP21773274.2A priority patent/EP4002480A4/en
Publication of WO2021238484A1 publication Critical patent/WO2021238484A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • Organic Light-Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, fast response speed, wide color gamut, high screen-to-body ratio, self-luminous, thin and light. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to mobile phones, displays, notebook computers, smart watches, digital cameras, instrumentation, flexible wearable devices and other display functions. Device. With the further development of display technology, display devices with a high screen-to-body ratio can no longer meet people's needs, and display devices with a full screen have become the development trend of display technology in the future.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, and including a display area; wherein, the display area includes a first display area, A second display area and a third display area, the second display area at least partially surrounds the first display area, the third display area at least partially surrounds the second display area, the first display area, the The second display area and the third display area do not overlap each other; the first display area includes at least one first light-emitting element, and the first display area allows light from the first side to be at least partially transmitted to The second side; the second display area includes at least one first pixel circuit, at least one second light-emitting element, and at least one second pixel circuit, the first light-emitting element is electrically connected to the first pixel circuit, The second light-emitting element is electrically connected to the second pixel circuit; the third display area includes at least one third light-emitting element and at least one third pixel circuit, the third light-emitting element and the
  • the first display area; the first connection portion is electrically connected to the first pixel circuit, and the first signal line is configured to transmit a first driving signal to the first pixel circuit, so that the first pixel circuit
  • the first light-emitting element is driven to emit light
  • the second signal line extends along the first direction and includes a first part and a second part, the first part is located in the third display area, and the second part is located in the The second display area;
  • the first portion is electrically connected to the third pixel circuit, the second portion is electrically connected to the second pixel circuit, and the second signal line is configured to be connected to the second pixel circuit
  • the third pixel circuit to transmit a second driving signal, so that the second pixel circuit drives the second light-emitting element to emit light and the third pixel circuit drives the third light-emitting element to emit light;
  • the third The signal line is located in the second display area and extends along the first direction, and the third signal line is suspended.
  • the display substrate provided by an embodiment of the present disclosure further includes at least one fourth signal line; wherein, the fourth signal line is located in the third display area and extends along the first direction, and the fourth signal line
  • the line is electrically connected to the third pixel circuit, and the fourth signal line is configured to transmit a third driving signal to the third pixel circuit, so that the third pixel circuit drives the third light-emitting element to emit light;
  • the third signal line and the fourth signal line are located on the same extension line, and there is a gap between the third signal line and the fourth signal line so as to be insulated from each other.
  • the extension line is a straight line.
  • the first body portion of the first signal line includes a first sub-portion and a second sub-portion, and the first sub-portion is located in the third display. Area, the second sub-portion is located in the second display area; the first sub-portion is electrically connected to the third pixel circuit, and the second sub-portion is electrically connected to the second pixel circuit; the The first signal line is also configured to transmit the first driving signal to the second pixel circuit and the third pixel circuit, so that the second pixel circuit drives the second light-emitting element to emit light and causes the first pixel circuit to emit light.
  • the three-pixel circuit drives the third light-emitting element to emit light.
  • the at least one second pixel circuit includes a plurality of second pixel circuits, and the plurality of second pixel circuits are arranged in multiple columns along the first direction; The second pixel circuit connected to the first signal line and the second pixel circuit connected to the second signal line are located in different columns.
  • the at least one third pixel circuit includes a plurality of third pixel circuits, and the plurality of third pixel circuits are arranged in multiple columns along the first direction;
  • the third pixel circuit connected to the first signal line, the third pixel circuit connected to the second signal line, and the third pixel circuit connected to the fourth signal line are located in different columns.
  • the first winding portion is spaced from the edge of the first display area, and the first winding portion is along the edge of the first display area.
  • the extension direction extends.
  • the shape of the first display area is a circle or an ellipse, and the first winding portion extends along an arc.
  • the at least one second signal line includes a plurality of second signal lines
  • the at least one third signal line includes a plurality of third signal lines
  • the plurality of The second signal line is spaced apart from the plurality of third signal lines.
  • the at least one second signal line includes a plurality of second signal lines
  • the at least one first signal line includes a plurality of first signal lines
  • the plurality of The second signal line is spaced apart from the first connection portion of the plurality of first signal lines.
  • the first driving signal, the second driving signal, and the third driving signal are different or the same data signals, and the data signal is different from the display gray scale. correspond.
  • each of the first pixel circuit, the second pixel circuit, and the third pixel circuit includes a switching thin film transistor, and the switching thin film transistor includes a gate.
  • the first electrode, the first electrode and the second electrode; the first signal line, the second signal line or the fourth signal line is electrically connected to the first electrode or the second electrode of the switching thin film transistor.
  • the first main body portion, the first winding portion, the first connection portion, the second signal line, and the third signal line are located at The same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a source and drain metal layer, wherein the first electrode and the second electrode of the switching thin film transistor are located in the source and drain metal layer, and the first body part, The first winding part, the first connection part, the second signal line, and the third signal line are located in the source-drain metal layer.
  • the first bending portion and the first connecting portion are located on different layers.
  • the display substrate provided by an embodiment of the present disclosure further includes a gate metal layer, wherein the gate of the switching thin film transistor is located on the gate metal layer, and the first bend of at least one of the first signal lines The part is located in the gate metal layer.
  • the display substrate provided by an embodiment of the present disclosure further includes a first metal layer, wherein the first metal layer and the gate metal layer are different film layers and are insulated from the gate metal layer, so
  • the at least one first signal line includes a plurality of first signal lines, a first bent portion of a part of the first signal line is located on the gate metal layer, and a first bent portion of another part of the first signal line is located on the first signal line.
  • the first signal line, the second signal line, and the third signal line include metal wiring or transparent conductive wiring.
  • the first light-emitting element, the second light-emitting element, and the third light-emitting element include organic light-emitting diodes.
  • the unit area distribution density of the second light-emitting element in the second display area is smaller than that of the third light-emitting element in the third display area. Area distribution density.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate according to any embodiment of the present disclosure.
  • the display device provided by an embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side.
  • the orthographic projection of the sensor on the display substrate at least partially overlaps the first display area.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a first display area and a second display area of the display substrate shown in FIG. 1;
  • FIG. 3 is an example of the first display area and the second display area of the display substrate shown in FIG. 2;
  • Fig. 4 is an enlarged view of a partial area of Fig. 3;
  • FIG. 5 is an enlarged view of a partial area of a third display area of the display substrate shown in FIG. 1;
  • 6A is one of the schematic plan views of a partial area of a display substrate provided by at least one embodiment of the present disclosure
  • 6B is the second schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure
  • 6C is the third schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic plan view of a partial area of another display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8A is one of the schematic layouts of a display substrate provided by at least one embodiment of the present disclosure.
  • 8B is the second schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • 8C is the third schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • 8D is the fourth schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • 10A is a schematic diagram of the structure of a 7T1C pixel circuit
  • 10B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 10A;
  • FIG. 11 is a schematic diagram of a laminated structure of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the distribution density per unit area (PPI) of the element may be smaller than the distribution density per unit area of light-emitting elements in other display regions of the display substrate.
  • the arrangement of the light-emitting elements and corresponding pixel circuits in different areas is different, which will generate different driving requirements and reduce the uniformity of the circuit environment. , Affecting the loaded signal.
  • the traditional wiring method is difficult to adapt to a variety of different driving requirements, it is difficult to improve the circuit environment, and it will also affect the light transmittance of the display area corresponding to the sensor (camera) under the screen, which makes the wiring design difficult and affects the adoption The performance of the display device of the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate can meet the driving requirements of different display areas, and can balance the circuit environment, optimize the wiring design, improve the rationality of the layout layout, and ensure normal display. Helps improve the performance of full-screen display devices.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 01 includes a display area 10, and the display area 10 includes a first display area 11, a second display area 12 and a third display area 13.
  • the first display area 11, the second display area 12, and the third display area 13 do not overlap each other.
  • the third display area 13 at least partially surrounds (eg, partially surrounds) the second display area 12, and the second display area 12 at least partially surrounds (eg, completely surrounds) the first display area 11.
  • the display substrate 01 may further include a peripheral area that at least partially surrounds the third display area 13.
  • the display substrate 01 has a first side for display and a second side opposite to the first side.
  • the first side is the front side of the display substrate 01 (that is, the plane shown in FIG. 1)
  • the second side is the back side of the display substrate.
  • a sensor may be provided at a position corresponding to the first display area 11 on the second side of the display substrate 01, and the sensor may be, for example, an image sensor or an infrared sensor.
  • the sensor is configured to receive light from the first side of the display substrate 01, so that operations such as image shooting, distance sensing, and light intensity sensing can be performed.
  • FIG. 2 is a schematic plan view of a first display area and a second display area of the display substrate shown in FIG. 1.
  • the second display area 12 at least partially surrounds (for example, completely surrounds) the first display area 11.
  • the shape of the first display area 11 may be a circle or an ellipse, and the shape of the second display area 12 may be a rectangle, but the embodiment of the present disclosure is not limited thereto.
  • the shapes of the first display area 11 and the second display area 12 may both be rectangles or other suitable shapes.
  • FIG. 3 is an example of the first display area and the second display area of the display substrate shown in FIG. 2.
  • 4 is an enlarged view of a partial area REG1 of FIG. 3
  • FIG. 5 is an enlarged view of a partial area REG2 of the third display area 13 of the display substrate shown in FIG. 1.
  • the first display area 11 includes at least one (for example, multiple) first light-emitting elements 411.
  • the first display area 11 includes a plurality of first light emitting elements 411 arranged in an array, and the first light emitting elements 411 are configured to emit light.
  • the pixel circuit for driving the first light-emitting element 411 is arranged in the second display area 12, thereby reducing the metal coverage area of the first display area 11 and increasing the first display area 11. ⁇ Transmittance.
  • the pixel circuit for driving the first light-emitting element 411 will be described below, and will not be repeated here.
  • the plurality of first light-emitting elements 411 may be arranged in a plurality of light-emitting units, and these light-emitting units are arranged in an array.
  • each light emitting unit may include one or more first light emitting elements 411.
  • the multiple first light-emitting elements 411 may emit light of the same color or light of different colors, for example, may emit white light, red light, blue light, green light, etc., which may be determined according to actual needs. No restrictions.
  • the arrangement of the plurality of first light-emitting elements 411 can refer to the conventional arrangement of pixel units, such as GGRB, RGBG, RGB, etc., which is not limited in the embodiment of the present disclosure.
  • the first display area 11 allows light from the first side of the display substrate 01 to be at least partially transmitted to the second side of the display substrate 01.
  • a sensor on the second side of the display substrate 01 and corresponding to the position of the first display area 11. Strong perception and other operations.
  • the second display area 12 includes at least one (for example, a plurality of) first pixel circuits 412.
  • the first light-emitting elements 411 and the first pixel circuits 412 are electrically connected in a one-to-one correspondence, and the plurality of first pixel circuits 412 are used to drive the plurality of first light-emitting elements 411 in a one-to-one correspondence.
  • the rectangular frame shown in FIGS. 3 and 4 represents the first pixel driving unit, and each first pixel driving unit includes a first pixel circuit 412.
  • the first pixel circuit 412 is configured to drive a plurality of first light-emitting elements 411 to emit light in a one-to-one correspondence. That is, one first pixel circuit 412 drives one corresponding first light-emitting element 411, and different first pixel circuits 412 drive different first light-emitting elements 411.
  • the first pixel driving unit may include one or more first pixel circuits 412.
  • the first pixel driving unit also includes a first pixel circuit 412.
  • the first pixel driving unit also includes a plurality of first pixel circuits 412, and the number of first light-emitting elements 411 in each light-emitting unit is, for example, It is equal to the number of first pixel circuits 412 in each first pixel driving unit, thereby achieving one-to-one corresponding driving.
  • the plurality of first light-emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four first light-emitting elements 411 is a group, and multiple groups of first light-emitting elements 411 are arranged in an array.
  • every four first pixel circuits 412 is a group, and multiple groups of first pixel circuits 412 are arranged in an array.
  • each first pixel driving unit includes four first pixel circuits 412.
  • the second display area 12 further includes at least one (for example, multiple) second light-emitting elements 421 and at least one (for example, multiple) second pixel circuits 422.
  • the second light-emitting element 421 is electrically connected to the second pixel circuit 422 in a one-to-one correspondence, and the second pixel circuit 422 is used to drive the second light-emitting element 421 to emit light.
  • the rectangular frame indicated by the reference number 422 in FIG. 4 is only used to show the approximate position of the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 and the specific boundary of the second pixel circuit 422. .
  • a plurality of second light emitting elements 421 are arranged in an array, and a plurality of second pixel circuits 422 are also arranged in an array.
  • at least one second light-emitting element 421 and its corresponding second pixel circuit 422 constitute a second pixel driving unit 42.
  • the second pixel driving unit 42 may include a second pixel circuit 422 and a second light-emitting element 421, or may include a plurality of second pixel circuits 422 and a plurality of second pixel circuits.
  • Light-emitting element 421 When the second pixel driving unit 42 includes a plurality of second pixel circuits 422 and a plurality of second light-emitting elements 421, the number of second pixel circuits 422 in each second pixel driving unit 42 is, for example, equal to that of the second light-emitting elements 421. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of second light emitting elements 421 are arranged in an array, and a plurality of second pixel circuits 422 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four second light-emitting elements 421 form a group, and multiple groups of second light-emitting elements 421 are arranged in an array.
  • every four second pixel circuits 422 is a group, and multiple groups of second pixel circuits 422 are arranged in an array.
  • each second pixel driving unit 42 includes four second pixel circuits 422 and four second light-emitting elements 421.
  • the third display area 13 includes at least one (for example, a plurality of) third light-emitting elements 431 and at least one (for example, a plurality of) third pixel circuits 432.
  • the third light-emitting element 431 is electrically connected to the third pixel circuit 432 in a one-to-one correspondence, and the third pixel circuit 432 is used to drive the third light-emitting element 431 to emit light.
  • the rectangular frame indicated by the reference number 432 in FIG. 5 is only used to show the approximate position of the third pixel circuit 432, and does not indicate the specific shape of the third pixel circuit 432 and the specific boundary of the third pixel circuit 432. .
  • a plurality of third light emitting elements 431 are arranged in an array, and a plurality of third pixel circuits 432 are also arranged in an array.
  • at least one third light-emitting element 431 and its corresponding third pixel circuit 432 constitute a third pixel driving unit 43.
  • the third pixel driving unit 43 may include a third pixel circuit 432 and a third light-emitting element 431, or may include a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431.
  • the third pixel driving unit 43 includes a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431
  • the number of third pixel circuits 432 in each third pixel driving unit 43 is, for example, equal to that of the third light-emitting element 431. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of third light emitting elements 431 are arranged in an array, and a plurality of third pixel circuits 432 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four third light-emitting elements 431 form a group, and multiple groups of third light-emitting elements 431 are arranged in an array.
  • every four third pixel circuits 432 form one group.
  • Groups of third pixel circuits 432 are arranged in an array.
  • each third pixel driving unit 43 includes four third pixel circuits 432 and four third light-emitting elements 431.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is smaller than the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12;
  • the distribution density per unit area of the light emitting element 421 is smaller than the distribution density per unit area of the plurality of third light emitting elements 431 in the third display area 13.
  • the first display area 11 and the second display area 12 may be referred to as a low-resolution area of the display substrate 01, and correspondingly, the third display area 13 may be referred to as a high-resolution area of the display substrate 01.
  • the sum of the pixel light-emitting area of the second display area 12 and the first display area 11 may be 1/8 to 1/2 of the pixel light-emitting area of the third display area 13.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 may also be equal to the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12. This may be determined according to actual requirements, and the embodiments of the present disclosure do not limit this.
  • the display substrate 01 By increasing the distribution density per unit area of the light-emitting elements in the first display area 11, the second display area 12, and the third display area 13, it is possible to facilitate the display substrate 01 while ensuring that the three display areas emit light normally to display images.
  • the light on the first side of the first display area 11 passes through the first display area 11 to reach the second side, thereby facilitating the sensor provided on the second side of the display substrate 01 to sense the light.
  • FIG. 6A is one of a schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6B is a second plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6C The third schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 01 is provided with at least one first signal line 21, at least one second signal line 22, and at least one third signal line 23.
  • the first signal line 21 includes a first body portion 211, a first winding portion 212, a first bending portion 213, and a first connecting portion 214 that are connected in sequence.
  • Both the first main body portion 211 and the first connection portion 214 extend along a first direction, and the first direction is, for example, the column direction in which the aforementioned multiple pixel circuits or light-emitting element arrays are arranged.
  • the embodiments of the present disclosure are not limited to this, and the first direction may also have a certain angle with the column direction, which may be determined according to actual requirements.
  • both the first body portion 211 and the first connecting portion 214 are straight lines extending in the first direction.
  • the virtual extension line of the first body portion 211 along the first direction and the virtual extension line of the first connection portion 214 along the first direction do not overlap, that is, the first body portion 211 and the first connection portion 214 are perpendicular to The directions of the first direction are staggered from each other.
  • the embodiment of the present disclosure is not limited to this, and the first main body portion 211 and the first connecting portion 214 may also be a curve with a certain arc, and the curve generally extends along the first direction.
  • the first winding portion 212 extends along a curve.
  • the first winding portion 212 has a distance from the edge of the first display area 11, and the first winding portion 212 extends along the extending direction of the edge of the first display area 11. That is, the first winding portion 212 does not pass through the first display area 11, and the first winding portion 212 is at least partially distributed around the first display area 11.
  • the shape of the first display area 11 is a circle or an ellipse. Accordingly, the first winding portion 212 extends along an arc, and the arc of the arc is less than or equal to ⁇ .
  • the distance between the first winding portion 212 and the edge of the first display area 11 can be set to any value, which is not limited in the embodiment of the present disclosure.
  • the first bending portion 213 is, for example, composed of a plurality of folding lines, and is used to connect the first winding portion 212 and the first connecting portion 214.
  • the first winding portion 212, the first bending portion 213, and the first connecting portion 214 are all located in the second display area 12, the first main body portion 211 is at least partially located in the second display area 12, and the first main body portion 211 is located along the second display area 12.
  • a virtual extension line in one direction passes through the first display area 11.
  • the first main body portion 211, the first winding portion 212, the first bending portion 213, and the first connecting portion 214 are not located in the first display area 11. In this way, it is possible to avoid affecting the light transmittance of the first display area 11.
  • the first connection part 214 is electrically connected to the first pixel circuit 412.
  • the first signal line 21 is configured to transmit a first driving signal to the first pixel circuit 412 so that the first pixel circuit 412 drives the first light-emitting element 411 to emit light.
  • the first pixel circuit 412 is electrically connected to the first light-emitting element 411 through the connection line 60, so that the first light-emitting element 411 can be driven to emit light.
  • the connecting wire 60 may be provided in the same layer as the anode of the first light-emitting element 411 and formed integrally with the anode of the first light-emitting element 411.
  • the embodiments of the present disclosure are not limited to this, and any applicable manner may be adopted to electrically connect the first pixel circuit 412 and the first light-emitting element 411, which may be determined according to actual requirements.
  • a separate layer of ITO may be provided to form the connection line 60.
  • the ITO layer is located between the source and drain metal layer (SD layer) and the anode layer of the first light-emitting element 411, and passes through the via hole.
  • the connecting line 60 is electrically connected to the first pixel circuit 412 and the first light-emitting element 411 respectively.
  • the second signal line 22 extends in the first direction and includes a first portion 221 and a second portion 222.
  • the first part 221 is located in the third display area 13, and the second part 222 is located in the second display area 12.
  • the first part 221 is electrically connected to the third pixel circuit 432, and the second part 222 is electrically connected to the second pixel circuit 422.
  • the second signal line 22 is configured to transmit a second driving signal to the second pixel circuit 422 and the third pixel circuit 432, so that the second pixel circuit 422 drives the second light-emitting element 421 to emit light and the third pixel circuit 432 to drive the third light-emitting The element 431 emits light.
  • the second signal line 22 is electrically connected to the second pixel circuit 422 and to the third pixel circuit 432, but this does not mean that the second signal line 22 is provided to the second pixel circuit 422.
  • the second driving signal is the same as the second driving signal provided to the third pixel circuit 432.
  • progressive scanning or time-sharing scanning can be used, so that the second driving signal provided to the second pixel circuit 422 is different from the second driving signal provided to the third pixel circuit 432, so that the corresponding second The light-emitting element 421 and the third light-emitting element 431 respectively display required gray scales.
  • the third signal line 23 is located in the second display area 12 and extends along the first direction, and the third signal line 23 is suspended.
  • the third signal line 23 is a straight line extending in the first direction.
  • the third signal line 23 is a dummy line and is not electrically connected to any pixel circuit. Since the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the third display area 13, a driving signal (for example, corresponding to a display gray scale) is provided.
  • the distribution density of the signal lines in the second display area 12 is also smaller than the distribution density of the signal lines in the third display area 13.
  • the signal line that provides the driving signal generally extends in the first direction (column direction), so by providing the third signal line 23 extending in the first direction in the second display area 12, The difference in the distribution density of the signal lines in the second display area 12 and the third display area 13 can be effectively reduced, the circuit environment in the second display area 12 can be effectively balanced, and the etching uniformity can be improved.
  • the first signal line 21, the second signal line 22, and the third signal line 23 exist in the display area (for example, the second display area 12) at the same time, and a variety of different wiring methods are provided, thereby
  • the driving requirements of different display areas can be met, for example, the driving requirements of the first display area 11, the second display area 12, and the third display area 13 can be met at the same time.
  • the third signal line 23 can extend the third signal line 23 in the first direction, the circuit environment can be effectively balanced.
  • the display substrate 01 can optimize the wiring design, improve the rationality of the layout, ensure normal display, and help improve the performance of the full-screen display device.
  • the display substrate 01 can also improve the performance of a display device with an under-screen sensor.
  • the display substrate 01 further includes at least one fourth signal line 24.
  • the fourth signal line 24 is located in the third display area 13 and extends along the first direction.
  • the fourth signal line 24 is a straight line extending in the first direction.
  • the fourth signal line 24 is electrically connected to the third pixel circuit 432, and the fourth signal line 24 is configured to transmit a third driving signal to the third pixel circuit 432, so that the third pixel circuit 432 drives the third light-emitting element 431 to emit light.
  • the third signal line 23 and the fourth signal line 24 are located on the same extension line, and there is a gap between the third signal line 23 and the fourth signal line 24 so as to be insulated from each other.
  • the extension line is a straight line.
  • the third signal line 23 and the fourth signal line 24 can be regarded as two insulated parts formed after the same signal line is cut off.
  • the distribution density of the third signal line 23 in the second display area 12 may be substantially equal to the distribution density of the fourth signal line 24 in the third display area 13, so that the overall signal line distribution density of the second display area 12
  • the overall signal line distribution density of the third display area 13 is not much different, so that the circuit environment in the display area (for example, the second display area 12 and the third display area 13) can be effectively balanced.
  • the third signal line 23 and the fourth signal line 24 can be formed in the same process, thereby improving etching uniformity, simplifying the production process, improving production efficiency, and reducing production costs.
  • a signal line that penetrates the third display area 13 and the second display area 12 may be formed first, and then the signal line may be cut off at the junction of the third display area 13 and the second display area 12, thereby The third signal line 23 and the fourth signal line 24 are formed, thereby being compatible with the usual panel manufacturing process.
  • FIG. 7 is a schematic plan view of a partial area of another display substrate provided by at least one embodiment of the present disclosure. Except for the difference in the arrangement of the first signal line 21, the display substrate 01 provided in this embodiment is basically the same as the display substrate 01 shown in FIGS. 6A-6C.
  • the first body portion 211 of the first signal line 21 includes a first sub-portion 211a and a second sub-portion 211b, and the first sub-portion 211a is located in the third display area 13.
  • the second sub-portion 211b is located in the second display area 12.
  • the first sub-portion 211 a is electrically connected to the third pixel circuit 432, and the second sub-portion 211 b is electrically connected to the second pixel circuit 422.
  • the first signal line 21 is also configured to transmit a first driving signal to the second pixel circuit 422 and the third pixel circuit 432, so that the second pixel circuit 422 drives the second light-emitting element 421 to emit light and the third pixel circuit 432 to drive The third light emitting element 431 emits light.
  • the first signal line 21 is electrically connected to the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432, but this does not mean that the signal provided to the first pixel circuit 412
  • the first driving signal, the first driving signal provided to the second pixel circuit 422 and the first driving signal provided to the third pixel circuit 432 are the same.
  • progressive scanning or time-sharing scanning may be used, so that the first driving signal provided to the first pixel circuit 412, the first driving signal provided to the second pixel circuit 422, and the first driving signal provided to the third pixel circuit 432
  • the first driving signals are different from each other, so that the corresponding first light-emitting element 411, second light-emitting element 421, and third light-emitting element 431 can respectively display the required gray scales.
  • the display substrate 01 includes a plurality of second pixel circuits 422 and a plurality of third pixel circuits 432.
  • the plurality of second pixel circuits 422 are arranged in multiple rows along the first direction
  • the plurality of third pixel circuits 432 are arranged in multiple rows along the first direction.
  • the second pixel circuit 422 connected to the first signal line 21 and the second pixel circuit 422 connected to the second signal line 22 are located in different columns.
  • the third pixel circuit 432 connected to the first signal line 21, the third pixel circuit 432 connected to the second signal line 22, and the third pixel circuit 432 connected to the fourth signal line 24 are located in different columns.
  • FIG. 7 does not show a complete multi-column pixel circuit, but only shows a few pixel circuits electrically connected to the first signal line 21, the second signal line 22, and the fourth signal line 24. It does not constitute a limitation to the embodiments of the present disclosure.
  • the manner in which the pixel circuits are arranged in multiple columns can refer to the structure shown in FIGS. 3-5 and the conventional design, which will not be repeated here.
  • FIG. 8A is one of the schematic layouts of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8A is, for example, an enlarged view of a partial region REG3 in FIG. 1.
  • FIG. 8B is the second schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8B is, for example, an enlarged view of a partial region REG4 in FIG. 8A.
  • FIG. 8C is the third schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8C is, for example, an enlarged view of a partial region REG5 in FIG. 8A.
  • FIG. 8D is the fourth schematic layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8D is, for example, another enlarged view of a partial region REG5 in FIG. 8A.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is substantially equal to the unit area distribution density of the plurality of second light-emitting elements 421 in the second display area 12.
  • the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the third display area 13.
  • the first signal line 21 can provide a driving signal for the first light-emitting element 411 in the first display area 11 with a lower pixel density through the first pixel circuit 412.
  • a sensor such as a camera
  • the first signal line 21 needs to be drawn in from the third display area 13 and extend around the first display area 11, and the first signal line 21 is cut off at the position S1 in FIG. 8B.
  • the second signal line 22 may extend from the third display area 13 to the second display area 12 in the first direction (for example, the column direction), and end at the S2 position shown in FIG. 8C.
  • the second signal line 22 passes through the third display area 13 and the second display area 12.
  • the third signal line 23 and the fourth signal line 24 are located on the same extension line, and there is a gap between the third signal line 23 and the fourth signal line 24 so as to be insulated from each other. Therefore, the third signal line 23 and the fourth signal line 24 can be regarded as disconnected from each other, for example, disconnected at the S3 position in FIG. 8B.
  • the third signal line 23 functions as a dummy line, so that the circuit environment in the second display area 12 can be balanced.
  • the third signal line 23 is reserved at the pixel position in the second display area 12 where the pixel circuit is not required to be driven, and the third signal line 23 and the fourth signal line 24 are disconnected from each other, so that the uniformity of the circuit environment of the second display area 12 can be maintained.
  • the first bending portions 213 of different first signal lines 21 may be alternately arranged in different metal layers.
  • the first bending portions 213_1, 213_2, 213_3, and 213_4 belong to four different first signal lines 21, the first bending portions 213_1, 213_2 may be disposed on the gate metal layer, and the first bending portions 213_3, 213_4 It can be arranged on the first metal layer, thereby facilitating wiring and avoiding short circuits at overlapping lines.
  • the first metal layer may be any film layer different from the gate metal layer in the display substrate 01, which is not limited in the embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of a partial area of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 01 includes a plurality of first signal lines 21, a plurality of second signal lines 22, and a plurality of third signal lines 23.
  • the plurality of second signal lines 22 and the plurality of third signal lines 23 are spaced apart, so as to more effectively balance the circuit environment of the second display area 12.
  • the plurality of second signal lines 22 are spaced apart from the first connection portions 214 of the plurality of first signal lines 21, so that the wiring space of the second display area 12 can be effectively used, the wiring design is optimized, and the rationality of the layout layout is improved.
  • the other structure of the display substrate 01 is basically the same as the display substrate 01 provided in the foregoing embodiment, and will not be repeated here.
  • the second signal line 22 and the third signal line 23 can be arranged at intervals of a ratio of 1:1, or can be arranged at intervals of any ratio of 2:1, 3:1, etc.
  • the second signal line The signal line 22 and the first connection portion 214 can be arranged at intervals of a number ratio of 1:1, or can be arranged at intervals of any number ratios such as 2:1, 3:1, etc., which can be determined according to actual needs.
  • the implementation of the present disclosure The example does not restrict this.
  • the respective numbers of the first signal line 21, the second signal line 22, and the third signal line 23 are not limited, which can be determined according to actual needs, for example, according to the display substrate 01 It depends on factors such as size, pixel distribution density, etc., which are not limited in the embodiments of the present disclosure.
  • the driving signals transmitted by the first signal line 21, the second signal line 22, and the fourth signal line 24 are data signals, that is, the first signal line 21, the second signal line 22, and the fourth signal line 24 may be
  • the data line (data line), the first driving signal, the second driving signal, and the third driving signal are all data signals.
  • the data signal corresponds to the display gray scale.
  • the first driving signal, the second driving signal, and the third driving signal may be different or the same data signals, which is not limited in the embodiment of the present disclosure.
  • FIG. 10A is a schematic diagram of the structure of a 7T1C pixel circuit.
  • the aforementioned first pixel circuit 412, second pixel circuit 422, and third pixel circuit 432 can all adopt the 7T1C pixel circuit.
  • the 7T1C pixel circuit 100 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a memory Capacitance Cst.
  • the first transistor CT1 to the seventh transistor CT7 are all P-type transistors.
  • the first terminal of the storage capacitor Cst is connected to the first power supply voltage terminal VDD to receive the first power supply voltage V1
  • the second terminal of the storage capacitor Cst is connected to the first node N1.
  • the first end of the light emitting element EL is connected to the fourth node N4, and the second end of the light emitting element EL is connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2.
  • the control terminal of the first transistor CT1 is connected to the first node N1, the first terminal of the first transistor CT1 is connected to the second node N2, and the second terminal of the first transistor CT1 is connected to the third node N3.
  • the first terminal of the second transistor CT2 is connected to the second node N2, and the second terminal of the second transistor CT2 is connected to the data signal terminal DAT to receive a data signal (for example, a data voltage) Vdata.
  • the first terminal of the third transistor CT3 is connected to the first node N1, and the second terminal of the third transistor CT3 is connected to the third node N3.
  • the first terminal of the fourth transistor CT4 is connected to the first node N1, and the second terminal of the fourth transistor CT4 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init1.
  • the first terminal of the fifth transistor CT5 is connected to the first power supply voltage terminal VDD, and the first terminal of the fifth transistor CT5 is connected to the second node N2.
  • the first terminal of the sixth transistor CT6 is connected to the fourth node N4, and the second terminal of the sixth transistor CT6 is connected to the second reset signal terminal Init2 to receive the second reset signal Vinit2.
  • the first terminal of the seventh transistor CT7 is connected to the third node N3, and the second terminal of the seventh transistor CT7 is connected to the fourth node N4.
  • control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown in the figure)
  • the control terminal EM1 of the fifth transistor CT5 and the control terminal of the seventh transistor CT7 EM2 are all connected to the light-emitting control terminal EM (not shown in the figure)
  • the control terminal of the fourth transistor CT4 is configured to be connected to the first reset control terminal RST1
  • the control terminal of the sixth transistor CT6 is configured to be connected to the second reset control terminal RST2.
  • FIG. 10A also shows the first node N1, the second node N2, the third node N3, the fourth node N4, and the light emitting element EL.
  • FIG. 10B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 10A. As shown in FIG. 10B, each driving cycle of the 7T1C pixel circuit 100 includes a first phase t1, a second phase t2, and a third phase t3.
  • the first reset control terminal RST1 receives an active level
  • the scan signal terminal GAT, the second reset control terminal RST2 and the light emission control terminal EM all receive an invalid level.
  • the fourth transistor CT4 is turned on, the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive the first reset signal (for example , Reset voltage) Vinit1, and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value.
  • the first transistor CT1 is turned on.
  • the scan signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the light-emitting control terminal EM receive an invalid level;
  • the first transistor CT1-the third transistor CT3 and the sixth transistor CT6 are turned on, the fourth transistor CT4, the fifth transistor CT5, and the seventh transistor CT7 are turned off;
  • the second transistor CT2 receives the data signal Vdata, and the data signal Vdata is turned on
  • the first transistor CT1 and the third transistor CT3 are written to the control terminal of the first transistor CT1, and the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1.
  • the voltage of a node N1 is Vdata+Vth; the sixth transistor CT6 is configured to receive a second reset signal (for example, a reset voltage) Vinit2, and write the second reset signal Vinit2 to the first end of the light-emitting element EL to emit light
  • a second reset signal for example, a reset voltage
  • Vinit2 The first terminal of the element EL is reset
  • Vinit2 Vinit2
  • Vinit2 is, for example, a negative value.
  • the light-emitting control terminal EM receives the valid level
  • the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive the invalid level
  • the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on
  • the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off
  • the first transistor CT1 is configured to be based on storage
  • the data signal (for example, the data voltage) Vdata in the storage capacitor Cst and the received first power supply voltage V1 are controlled to flow through the first transistor CT1 and from the first power supply voltage terminal VDD to the light-emitting element EL for driving the light-emitting element
  • the driving current of EL; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD;
  • the driving current Id can be expressed by the following formula:
  • k ⁇ Cox ⁇ W/L; ⁇ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, and W/L is the channel of the first transistor CT1.
  • the width-to-length ratio of the channel Vth is the threshold voltage of the first transistor CT1, Vth is the gate-source voltage of the first transistor CT1, Vg is the gate voltage of the first transistor CT1, and Vs is the source voltage of the first transistor CT1.
  • the 7T1C pixel circuit 100 shown in FIGS. 10A and 10B has a threshold compensation function.
  • the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 are not limited to the above 7T1C pixel circuit, and other applicable pixel circuits may also be used.
  • the implementation of the present disclosure The example does not restrict this.
  • the specific circuit structures of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 may be the same or different from each other, which may be determined according to actual requirements, which is not limited in the embodiment of the present disclosure.
  • each of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 includes a switching thin film transistor
  • the switching thin film transistor is, for example, the second transistor CT2 in FIG. 10A.
  • the switching thin film transistor (for example, the second transistor CT2) includes a gate, a first electrode and a second electrode, the first signal line 21, the second signal line 22 or the fourth signal line 24 and the first signal line of the switching thin film transistor
  • the pole or the second pole is electrically connected. That is, the first signal line 21, the second signal line 22, or the fourth signal line 24 may be electrically connected to the data signal terminal DAT in FIG. 10A to provide a data signal.
  • the aforementioned first light emitting element 411, second light emitting element 421, and third light emitting element 431 include organic light emitting diodes (OLED). That is, the first light-emitting element 411, the second light-emitting element 421, or the third light-emitting element 431 may be the light-emitting element EL in FIG. 10A, and the light-emitting element EL may be an organic light-emitting diode (OLED).
  • OLED organic light emitting diodes
  • the embodiments of the present disclosure are not limited thereto.
  • the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 may also be quantum dot light-emitting diodes (QLEDs) or other applicable light-emitting devices. There is no restriction on this.
  • QLEDs quantum dot light-emitting diodes
  • FIG. 11 is a schematic diagram of a laminated structure of a display substrate provided by at least one embodiment of the present disclosure.
  • the schematic diagram of the laminated structure mainly schematically shows the first pixel circuit 412 and the first light-emitting element 411.
  • the first pixel circuit 412 includes structures such as a switching thin film transistor 412T and a storage capacitor 412C.
  • the first light emitting element 411 includes a first anode structure 4111, a first cathode structure 4113, and a first light emitting layer 4112 located between the first anode structure 4111 and the first cathode structure 4113.
  • the first anode structure 4111 communicates with the first anode structure 4111 through the via hole.
  • the switching thin film transistor 412T included in the pixel circuit 412 is electrically connected.
  • the first anode structure 4111 may be integrally formed with the aforementioned connecting wire 60, that is, the connecting wire 60 may be regarded as a part of the first anode structure 4111.
  • a separate layer of ITO may be provided to form the connecting line 60.
  • This layer of ITO is located between the source and drain metal layer (SD layer) and the film layer where the first anode structure 4111 is located, and passes through The holes make the required electrical connections.
  • the first anode structure 4111 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not labeled in the figure), etc.
  • the specific form of the first anode structure 4111 is not limited in the embodiment of the present disclosure. .
  • the first cathode structure 4113 may be a structure formed on the entire surface of the display substrate 01.
  • the first cathode structure 4113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the first cathode structure 4113 can be formed as a very thin layer, the first cathode structure 4113 has good light transmittance.
  • the switching thin film transistor 412T includes an active layer 4121, a gate 4122, and source and drain electrodes (ie, a source 4123 and a drain 4124), and the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126.
  • the active layer 4121 is disposed on the base substrate 74
  • the first gate insulating layer 741 is disposed on the side of the active layer 4121 away from the base substrate 74.
  • the gate 4122 and the first capacitor plate 4125 are arranged in the same layer and are located on the side of the first gate insulating layer 741 away from the base substrate 74.
  • a second gate insulating layer 742 is provided on the side.
  • the second capacitor plate 4126 is disposed on the side of the second gate insulating layer 742 away from the base substrate 74, and the side of the second capacitor plate 4126 away from the base substrate 74 is provided with an interlayer insulating layer 743.
  • the source and drain electrodes are arranged on the side of the interlayer insulating layer 743 away from the base substrate 74, and pass through the via holes and the active layer in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. 4121 electrical connection.
  • a planarization layer 744 is provided on the side of the source and drain electrodes away from the base substrate 74 to planarize the first pixel circuit 412.
  • the planarization layer 744 has a via hole, and the first anode structure 4111 is electrically connected to the source 4123 or the drain 4124 of the switching thin film transistor 412T through the via hole in the planarization layer 744.
  • the first display area 11 further includes a transparent support layer 78 on the base substrate 74, and the first light-emitting element 411 is located on the side of the transparent support layer 78 away from the base substrate 74. Therefore, with respect to the base substrate 74, the first light-emitting element 411 in the first display area 11 can be combined with the second light-emitting element 421 in the second display area 12 and the third light-emitting element in the third display area 13. 431 are at substantially the same height, so that the display effect of the display substrate 01 can be improved.
  • the first body part 211, the first winding part 212, the first connection part 214, the second signal line 22, and the third signal line 23 may be located in the same layer.
  • the film layer where the source and drain electrodes (ie, the source 4123 and the drain 4124) are located is called the source and drain metal layer (SD layer), that is, as shown in FIG. 11, the switch
  • the first electrode and the second electrode (that is, the source electrode 4123 and the drain electrode 4124) of the thin film transistor 412T are located on the source and drain metal layer.
  • the first body portion 211, the first winding portion 212, the first connection portion 214, the second signal line 22, and the third signal line 23 are located on the source and drain metal layer, that is, connected to the source 4123 and the drain 4124. Same layer settings.
  • the first bending portion 213 and the first connecting portion 214 are located on different layers, and the first body portion 211, the first winding portion 212, the first connecting portion 214, and the second signal line are located on different layers.
  • the first bending portion 213 is connected to the first main body portion 211, the first winding portion 212, the first connection portion 214, the second signal line 22, and the third signal line Any one of 23 is located on a different level.
  • the film layer where the gate 4122 is located is called the gate metal layer, that is, as shown in FIG. 11, the gate 4122 of the switching thin film transistor 412T is located on the gate metal layer.
  • the first bent portion 213 of at least one of the first signal lines 21 is located on the gate metal layer, that is, the first bent portion 213 of at least one of the first signal lines 21 and the gate 4122 are provided in the same layer.
  • all the first bent portions 213 of the first signal lines 21 may be located on the gate metal layer, or only a part of the first bent portions 213 of the first signal lines 21 may be located on the gate metal layer. The example does not restrict this.
  • the display substrate 01 may further include a first metal layer, the first metal layer and the gate metal layer are different film layers, and the first metal layer is insulated from the gate metal layer.
  • the first metal layer is any other metal layer different from the gate metal layer in the display substrate 01.
  • a part of the first bent portion 213 of the first signal line 21 among the plurality of first signal lines 21 is located on the gate metal layer, and the other part of the first bent portion 213 of the first signal line 21 is located on the gate metal layer.
  • the first bent portions 213 of different first signal lines 21 may be alternately arranged in the gate metal layer and the first metal layer. For example, as shown in FIG.
  • the first bent portions 213 of the different first signal lines 21 can be alternately arranged on the same layer as the gate 4122 and the second capacitor plate 4126, that is, part of the first signal line 21
  • the first bending portion 213 and the gate 4122 are provided in the same layer, and the first bending portion 213 of the other part of the first signal line 21 is provided in the same layer as the second capacitor plate 4126.
  • the embodiment of the present disclosure is not limited to this.
  • the first signal line 21, the second signal line 22, and the third signal line 23 may also be located on the same layer, that is, located on the same layer in the display substrate 01.
  • One film layer can reduce the thickness of the display substrate 01, and is easy to prepare in the same process, simplifying the preparation process.
  • the film layer relationship of the first signal line 21, the second signal line 22, and the third signal line 23 can be determined according to actual requirements, and the three can be located on the same layer or different layers, which is not limited in the embodiment of the present disclosure.
  • any two of the first signal line 21, the second signal line 22, and the third signal line 23 may be located on the same layer, and the remaining one may be located on a different layer; or, all three may be located on different layers.
  • the fourth signal line 24 may be located on the same layer as any one or more of the first signal line 21, the second signal line 22, and the third signal line 23, or may be located on the same layer as the first signal line 21 and the second signal line.
  • the 22 and the third signal line 23 are located on different layers, which is not limited in the embodiment of the present disclosure.
  • the first signal line 21, the second signal line 22, and the third signal line 23 include metal traces, and at least part of the metal traces are located on the source and drain metal layers of the display substrate 01, for example.
  • the metal traces except for the first bent portion 213 are located in the source and drain metal layers.
  • the second signal line 22, the third signal line 23, and the first body portion 211 and the first winding of the first signal line 21 can be prepared together.
  • the part 212 and the first connecting part 214 can simplify the production process, improve the production efficiency, and reduce the production cost.
  • a metal trace serving as the first bent portion 213 may be prepared together.
  • the first signal line 21, the second signal line 22, and the third signal line 23 may include transparent conductive traces, which are made of, for example, indium tin oxide (ITO).
  • the transparent conductive trace can be provided on any suitable film layer, which is not limited in the embodiments of the present disclosure. Setting the first signal line 21, the second signal line 22, and the third signal line 23 as transparent conductive traces can increase the light transmittance of the display substrate 01.
  • the display substrate 01 further includes a pixel defining layer 746, an encapsulation layer 747, and other structures.
  • the pixel defining layer 746 is disposed on the first anode structure 4111 (for example, a part of the first anode structure 4111), and includes a plurality of openings to define different pixels or sub-pixels, and the first light-emitting layer 4112 is formed on the pixel defining layer 746 In the opening.
  • the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, for example, the multilayer encapsulation structure includes a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate 01.
  • the pixel defining layers 746 in the first display area 11, the second display area 12, and the third display area 13 are arranged in the same layer, and the pixel defining layers 746 in the first display area 11, the second display area 12 and the third display area 13 are
  • the encapsulation layer 747 is provided in the same layer, and in some embodiments is still integrally connected, which is not limited in the embodiments of the present disclosure.
  • the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate, etc., and may be a rigid substrate or a flexible substrate.
  • the embodiment of the present disclosure does not limit this.
  • the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743 and the planarization layer 744, the insulating layer 745, the pixel defining layer 746, and the encapsulation layer 747 may include silicon oxide, silicon nitride, Inorganic insulating materials such as silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the material of the active layer 4121 may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 4121 may be conductive through a conductive process such as doping, so as to have higher conductivity.
  • the materials of the gate 4122, the first capacitor plate 4125, and the second capacitor plate 4126 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the material of the source electrode 4123 and the drain electrode 4124 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer, such as Titanium, aluminum, titanium three-layer metal laminate (Ti/Al/Ti), etc.
  • the display substrate 01 provided by the embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • the light-emitting layer (for example, the aforementioned first light-emitting layer 4112) may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may It emits red light, green light, blue light, or white light.
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, and cadmium sulfide quantum dots. , Cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is, for example, 2-20nm.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by any embodiment of the present disclosure.
  • the display device can meet the driving requirements of different display areas, and can balance the circuit environment, optimize the wiring design, improve the rationality of the layout layout, ensure normal display, and help improve the performance of the full-screen display device.
  • FIG. 12 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 30 includes a display substrate 310, which is a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 30 can be any electronic device with a display function, such as a smart phone, a notebook computer, a tablet computer, a TV, and the like.
  • the smart phone or tablet computer may have a full-screen design, that is, there is no peripheral area surrounding the third display area 13.
  • the smart phone or tablet computer also has an under-screen sensor (such as a camera, an infrared sensor, etc.), which can perform operations such as image shooting, distance sensing, and light intensity sensing.
  • FIG. 13 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the display device 30 includes a display substrate 310, which is a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 30 further includes a sensor 320.
  • the display substrate 01 includes a first side F1 for display and a second side F2 opposite to the first side F1. That is, the first side F1 is the display side, and the second side F2 is the non-display side.
  • the display substrate 01 is configured to perform a display operation on the first side F1, that is, the first side F1 of the display substrate 01 is the light emitting side of the display substrate 01, and the first side F1 faces the user.
  • the first side F1 and the second side F2 are opposed to each other in the normal direction of the display surface of the display substrate 01.
  • the sensor 320 is disposed on the second side F2 of the display substrate 01, and the sensor 320 is configured to receive light from the first side F1.
  • the sensor 320 and the first display area 11 are overlapped in the normal direction of the display surface of the display substrate 01 (for example, the direction perpendicular to the display substrate 01), and the sensor 320 may receive and process the data passing through the first display area 11.
  • the optical signal may be visible light, infrared light, etc.
  • the first display area 11 allows light from the first side F1 to be at least partially transmitted to the second side F2.
  • the first display area 11 is not provided with a pixel circuit. In this case, the light transmittance of the first display area 11 can be improved.
  • the orthographic projection of the sensor 320 on the display substrate 01 at least partially overlaps the first display area 11.
  • the orthographic projection of the sensor 320 on the display substrate 01 is located in the first display area 11.
  • the orthographic projection of the sensor 320 on the display substrate 01 is the same as that of the first display. Area 11 partially overlaps. At this time, since the light can propagate to the sensor 320 laterally, it is not necessary that the sensor 320 is completely located at a position corresponding to the first display area 11.
  • the first display area 11 can be reduced.
  • the element in the shielding of the light signal incident to the first display area 11 and irradiated to the sensor 320 can improve the signal-to-noise ratio of the image output by the sensor 320.
  • the first display area 11 may be referred to as a high light transmission area of a low resolution area of the display substrate 01.
  • the sensor 320 may be an image sensor, which may be used to collect an image of the external environment facing the light-collecting surface of the sensor 320, and may be, for example, a CMOS image sensor or a CCD image sensor.
  • the sensor 320 may also be an infrared sensor, a distance sensor, or the like.
  • the display device 30 is a mobile terminal such as a mobile phone, a notebook, etc.
  • the sensor 320 can be implemented as a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may also include, for example, a lens, a mirror, or an optical waveguide, etc., as required.
  • Optical devices to modulate the optical path may be an image sensor, which may be used to collect an image of the external environment facing the light-collecting surface of the sensor 320, and may be, for example, a CMOS image sensor or a CCD image sensor.
  • the sensor 320 may also be an infrared sensor, a distance sensor, or the
  • the sensor 320 may include photosensitive pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching thin film transistor).
  • the photodiode can convert the light signal irradiated on it into an electrical signal
  • the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • the anode of the first light-emitting element 411 adopts a stacked structure of ITO/Ag/ITO.
  • the first display area 11 only the anode of the first light-emitting element 411 does not transmit light, that is, it is used for
  • the wiring that drives the first light-emitting element 411 bypasses the first display area 11 or is set as a transparent wiring. In this case, not only can the light transmittance of the first display area 11 be further improved, but also the diffraction caused by various elements in the first display area 11 can be reduced.
  • the display device 30 may further include more components and structures, which are not limited in the embodiments of the present disclosure.
  • the technical effects and detailed description of the display device 30 reference may be made to the above description of the display substrate 01, which will not be repeated here.

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Abstract

一种显示基板及显示装置，该显示基板(01)具有第一侧和第二侧，且包括显示区域。第一显示区域(11)包括第一发光元件(411)，且允许来自第一侧的光至少部分透射至第二侧。第二显示区域(12)包括第一像素电路(412)、第二发光元件(421)和第二像素电路(422)。第三显示区域(13)包括第三发光元件(431)和第三像素电路(432)。显示基板(01)上设有第一至第三信号线(21-23)。第一信号线(21)的第一绕线部(212)沿曲线延伸，第一绕线部(212)、第一弯折部(213)和第一连接部(214)均位于第二显示区域(12)。第一信号线(21)向第一像素电路(412)传输第一驱动信号以驱动第一发光元件(411)发光。第二信号线(22)向第二和第三像素电路(422-432)传输第二驱动信号以驱动第二和第三发光元件(421-431)发光。第三信号线(23)悬浮设置，位于第二显示区域(12)且沿第一方向延伸。该显示基板(01)能平衡电路环境，优化走线设计。

Description

显示基板及显示装置
本申请要求于2020年5月29日递交的中国专利申请第202010479767.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快、色域广、屏占比高、自发光、轻薄等特点。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、智能手表、数码相机、仪器仪表、柔性可穿戴装置等具有显示功能的装置。随着显示技术的进一步发展，具有高屏占比的显示装置已经不能满足人们的需求，具有全面屏的显示装置成为未来显示技术的发展趋势。
发明内容
本公开至少一个实施例提供一种显示基板，具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括显示区域；其中，所述显示区域包括第一显示区域、第二显示区域和第三显示区域，所述第二显示区域至少部分围绕所述第一显示区域，所述第三显示区域至少部分围绕所述第二显示区域，所述第一显示区域、所述第二显示区域和所述第三显示区域互不重叠；所述第一显示区域包括至少一个第一发光元件，且所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；所述第二显示区域包括至少一个第一像素电路、至少一个第二发光元件和至少一个第二像素电路，所述第一发光元件与所述第一像素电路电连接，所述第二发光元件与所述第二像素电路电连接；所述第三显示区域包括至少一个第三发光元件和至少一个第三像素电路，所述第三发光元件与所述第三像素电路电连接；所述显示基板上设有至少一根第一信号线、至少一根第二信号线和至少一根第三信号线；所述第一信号线包括依次连接的第一主体部、第一绕线部、第一弯折部和第一连接部；所述第一主体部和所述第一连接部均沿第一方向延伸，所述第一主体部沿所述第一方向的虚拟延长线与所述第一连接部沿所述第一方向的虚拟延长线不重叠，所述第一绕线部沿曲线延伸；所述第一绕线部、所述第一弯折部和所述第一连接部均位于所述第二显示区域，所述第一主体部至少部分位于所述第二显示区域，所述第一主体部沿所述第一方向的虚拟延长线穿过所述第一显示区域；所述第一连接部与所述第一像素电路电连接，所述第一信号线配置为向所述第一像素电路传输第一驱动信号，以使所述第一像素电路驱动所述第一发光元件发光；所述第二信号线沿所述第一方向延伸且包括第一部分和第二部分，所述第一部分位于所述第三显示区域，所述第二部分位于所述第二显示区域；所述第一部分 与所述第三像素电路电连接，所述第二部分与所述第二像素电路电连接，所述第二信号线配置为向所述第二像素电路和所述第三像素电路传输第二驱动信号，以使所述第二像素电路驱动所述第二发光元件发光且使所述第三像素电路驱动所述第三发光元件发光；所述第三信号线位于所述第二显示区域且沿所述第一方向延伸，所述第三信号线悬浮设置。
例如，本公开一实施例提供的显示基板还包括至少一根第四信号线；其中，所述第四信号线位于所述第三显示区域且沿所述第一方向延伸，所述第四信号线与所述第三像素电路电连接，所述第四信号线配置为向所述第三像素电路传输第三驱动信号，以使所述第三像素电路驱动所述第三发光元件发光；所述第三信号线与所述第四信号线位于同一条延伸线上，所述第三信号线与所述第四信号线之间具有间隙从而彼此绝缘。
例如，在本公开一实施例提供的显示基板中，所述延伸线为直线。
例如，在本公开一实施例提供的显示基板中，所述第一信号线的所述第一主体部包括第一子部和第二子部，所述第一子部位于所述第三显示区域，所述第二子部位于所述第二显示区域；所述第一子部与所述第三像素电路电连接，所述第二子部与所述第二像素电路电连接；所述第一信号线还配置为向所述第二像素电路和所述第三像素电路传输所述第一驱动信号，以使所述第二像素电路驱动所述第二发光元件发光且使所述第三像素电路驱动所述第三发光元件发光。
例如，在本公开一实施例提供的显示基板中，所述至少一个第二像素电路包括多个第二像素电路，所述多个第二像素电路沿所述第一方向呈多列排布；与所述第一信号线连接的第二像素电路和与所述第二信号线连接的第二像素电路位于不同列。
例如，在本公开一实施例提供的显示基板中，所述至少一个第三像素电路包括多个第三像素电路，所述多个第三像素电路沿所述第一方向呈多列排布；与所述第一信号线连接的第三像素电路、与所述第二信号线连接的第三像素电路以及与所述第四信号线连接的第三像素电路位于不同列。
例如，在本公开一实施例提供的显示基板中，所述第一绕线部与所述第一显示区域的边缘具有间距，所述第一绕线部沿着所述第一显示区域的边缘的延伸方向延伸。
例如，在本公开一实施例提供的显示基板中，所述第一显示区域的形状为圆形或椭圆形，所述第一绕线部沿弧线延伸。
例如，在本公开一实施例提供的显示基板中，所述至少一条第二信号线包括多条第二信号线，所述至少一条第三信号线包括多条第三信号线，所述多条第二信号线与所述多条第三信号线间隔设置。
例如，在本公开一实施例提供的显示基板中，所述至少一条第二信号线包括多条第二信号线，所述至少一条第一信号线包括多条第一信号线，所述多条第二信号线与所述多条第一信号线的第一连接部间隔设置。
例如，在本公开一实施例提供的显示基板中，所述第一驱动信号、所述第二驱动信号、所述第三驱动信号为不同或相同的数据信号，所述数据信号与显示灰阶对应。
例如，在本公开一实施例提供的显示基板中，所述第一像素电路、所述第二像素电路 和所述第三像素电路中的每个包括开关薄膜晶体管，所述开关薄膜晶体管包括栅极、第一极和第二极；所述第一信号线、所述第二信号线或所述第四信号线与所述开关薄膜晶体管的第一极或第二极电连接。
例如，在本公开一实施例提供的显示基板中，所述第一主体部、所述第一绕线部、所述第一连接部、所述第二信号线和所述第三信号线位于同一层。
例如，本公开一实施例提供的显示基板还包括源漏极金属层，其中，所述开关薄膜晶体管的第一极和第二极位于所述源漏极金属层，所述第一主体部、所述第一绕线部、所述第一连接部、所述第二信号线和所述第三信号线位于所述源漏极金属层。
例如，在本公开一实施例提供的显示基板中，所述第一弯折部与所述第一连接部位于不同层。
例如，本公开一实施例提供的显示基板还包括栅极金属层，其中，所述开关薄膜晶体管的栅极位于所述栅极金属层，所述第一信号线至少之一的第一弯折部位于所述栅极金属层。
例如，本公开一实施例提供的显示基板还包括第一金属层，其中，所述第一金属层与所述栅极金属层为不同的膜层，且与所述栅极金属层绝缘，所述至少一条第一信号线包括多条第一信号线，一部分第一信号线的第一弯折部位于所述栅极金属层，另一部分第一信号线的第一弯折部位于所述第一金属层。
例如，在本公开一实施例提供的显示基板中，所述第一信号线、所述第二信号线和所述第三信号线包括金属走线或透明导电走线。
例如，在本公开一实施例提供的显示基板中，所述第一发光元件、所述第二发光元件和所述第三发光元件包括有机发光二极管。
例如，在本公开一实施例提供的显示基板中，所述第二发光元件在所述第二显示区域内的单位面积分布密度小于所述第三发光元件在所述第三显示区域内的单位面积分布密度。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的显示基板。
例如，本公开一实施例提供的显示装置还包括传感器，其中，所述传感器设置于所述显示基板的第二侧，所述传感器配置为接收来自所述第一侧的光。
例如，在本公开一实施例提供的显示装置中，所述传感器在所述显示基板上的正投影与所述第一显示区域至少部分重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一个实施例提供的一种显示基板的平面示意图；
图2为图1所示的显示基板的第一显示区域和第二显示区域的平面示意图；
图3为图2所示的显示基板的第一显示区域和第二显示区域的一个示例；
图4为图3的部分区域的放大图；
图5为图1所示的显示基板的第三显示区域的部分区域的放大图；
图6A为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之一；
图6B为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之二；
图6C为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之三；
图7为本公开至少一个实施例提供的另一种显示基板的部分区域的平面示意图；
图8A为本公开至少一个实施例提供的一种显示基板的示意版图之一；
图8B为本公开至少一个实施例提供的一种显示基板的示意版图之二；
图8C为本公开至少一个实施例提供的一种显示基板的示意版图之三；
图8D为本公开至少一个实施例提供的一种显示基板的示意版图之四；
图9为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图；
图10A为一种7T1C像素电路的结构示意图；
图10B为图10A所示的7T1C像素电路的驱动时序图；
图11为本公开至少一个实施例提供的一种显示基板的叠层结构示意图；
图12为本公开至少一个实施例提供的一种显示装置的示意框图；以及
图13为本公开至少一个实施例提供的一种显示装置的叠层结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
对于当前的具有屏下传感器(例如，摄像头)的显示基板，为了提高显示基板的对应于屏下传感器(摄像头)的显示区域的透光率，对应于屏下传感器(摄像头)的显示区域的发光元件的单位面积分布密度(PPI)可以小于显示基板的其它显示区域的发光元件的单位面积分布密度。
然而，由于显示基板上不同区域的发光元件的单位面积分布密度不同，导致不同区域 的发光元件及相应的像素电路的设置方式不同，从而会产生不同的驱动需求，并且会降低电路环境的均一性，影响所加载的信号。传统的布线方式难以适应多种不同的驱动需求，难以改善电路环境，并且也会影响对应于屏下传感器(摄像头)的显示区域的透光率，这使得走线设计的难度大，影响了采用该显示基板的显示装置的性能。
本公开至少一个实施例提供一种显示基板及显示装置，该显示基板可以满足不同显示区域的驱动需求，并且可以平衡电路环境，优化走线设计，提升版图布局的合理性，保证正常显示，有助于提高全面屏显示装置的性能。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图1为本公开至少一个实施例提供的一种显示基板的平面示意图。如图1所示，该显示基板01包括显示区域10，显示区域10包括第一显示区域11、第二显示区域12和第三显示区域13。例如，第一显示区域11、第二显示区域12和第三显示区域13互不重叠。例如，第三显示区域13至少部分围绕(例如，部分围绕)第二显示区域12，第二显示区域12至少部分围绕(例如，完全围绕)第一显示区域11。需要说明是，在一些示例中，显示基板01还可以包括周边区域，该周边区域至少部分围绕第三显示区域13。
例如，该显示基板01具有用于显示的第一侧和与第一侧相对的第二侧。例如，在一些示例中，如图1所示，第一侧为显示基板01的正侧(也即图1所示的平面)，第二侧为显示基板的背侧。例如，可以在显示基板01的第二侧对应于第一显示区域11的位置设置传感器，该传感器例如为图像传感器或红外传感器等。该传感器配置为接收来自显示基板01的第一侧的光线，从而可以进行图像拍摄、距离感知、光强感知等操作。
图2为图1所示的显示基板的第一显示区域和第二显示区域的平面示意图。例如，如图1和图2所示，第二显示区域12至少部分围绕(例如，完全围绕)第一显示区域11。
例如，第一显示区域11的形状可以为圆形或椭圆形，第二显示区域12的形状可以为矩形，但本公开的实施例不限于此。又例如，第一显示区域11和第二显示区域12的形状可以均为矩形或者其它适用的形状。
图3为图2所示的显示基板的第一显示区域和第二显示区域的一个示例。图4为图3的部分区域REG1的放大图，图5为图1所示的显示基板的第三显示区域13的部分区域REG2的放大图。
例如，如图3和图4所示，第一显示区域11包括至少一个(例如多个)第一发光元件411。需要说明的是，为清楚起见，相关附图使用了第一发光元件411的阳极结构来示意性的示出第一发光元件411。例如，第一显示区域11包括阵列排布的多个第一发光元件411，第一发光元件411被配置为发射光线。例如，第一显示区域11中没有像素电路，用于驱动第一发光元件411的像素电路设置在第二显示区域12中，从而减少第一显示区域11的金属覆盖面积，提高第一显示区域11的透光率。关于驱动第一发光元件411的像素电路，将在下文进行说明，此处不再赘述。
例如，多个第一发光元件411可以设置在多个发光单元中，这些发光单元呈阵列排布。 例如，每个发光单元可以包括一个或多个第一发光元件411。例如，多个第一发光元件411可以发射相同颜色的光或不同颜色的光，例如可以发射白光、红光、蓝光、绿光等，这可以根据实际需求而定，本公开的实施例对此不作限制。例如，多个第一发光元件411的排布方式可以参考常规的像素单元排布方式，例如GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
例如，第一显示区域11允许来自显示基板01的第一侧的光至少部分透射至显示基板01的第二侧。通过这种方式，可以便于在显示基板01的第二侧且对应于第一显示区域11的位置处设置传感器，该传感器可以接收来自第一侧的光线，从而可以进行图像拍摄、距离感知、光强感知等操作。
例如，如图3和图4所示，第二显示区域12包括至少一个(例如多个)第一像素电路412。例如，第一发光元件411与第一像素电路412一一对应地电连接，多个第一像素电路412用于一一对应地驱动多个第一发光元件411。例如，图3和图4所示的矩形框(标号412所指示的黑色边框白色填充区域)表示第一像素驱动单元，每个第一像素驱动单元均包括第一像素电路412。例如，第一像素电路412被配置为一一对应地驱动多个第一发光元件411发光。也即是，一个第一像素电路412驱动一个对应的第一发光元件411，不同的第一像素电路412驱动不同的第一发光元件411。
需要说明的是，在图3和图4中，并非所有矩形框都表示第一像素驱动单元，在第一像素电路412及第一发光元件411的分布密度改变(例如分布密度减小)时，可以仅有一部分矩形框表示第一像素驱动单元，而另一部分矩形框中不再设置有第一像素驱动单元。
需要说明的是，在图3和图4中，第一像素驱动单元可以包括一个或多个第一像素电路412。当第一显示区域11中的发光单元包括一个第一发光元件411时，该第一像素驱动单元也包括一个第一像素电路412。当第一显示区域11中的发光单元包括多个第一发光元件411时，该第一像素驱动单元也包括多个第一像素电路412，每个发光单元中的第一发光元件411的数量例如等于每个第一像素驱动单元中的第一像素电路412的数量，由此实现一一对应驱动。
例如，多个第一发光元件411阵列排布，多个第一像素电路412也阵列排布。这里，“阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图3和图4所示，每4个第一发光元件411为一组，多组第一发光元件411呈阵列排布，相应地，每4个第一像素电路412为一组，多组第一像素电路412呈阵列排布，此时，每个第一像素驱动单元中包括4个第一像素电路412。
例如，如图3和图4所示，第二显示区域12还包括至少一个(例如多个)第二发光元件421以及至少一个(例如多个)第二像素电路422。第二发光元件421与第二像素电路422一一对应地电连接，第二像素电路422用于驱动第二发光元件421发光。需要说明的是，图4中标号422所指示的矩形框仅用于示出第二像素电路422的大概位置，而并不表示第二像素电路422的具体形状以及第二像素电路422的具体边界。例如，多个第二发光 元件421阵列排布，多个第二像素电路422也阵列排布。例如，至少一个第二发光元件421及其对应的第二像素电路422构成一个第二像素驱动单元42。
需要说明的是，在图3和图4中，第二像素驱动单元42可以包括一个第二像素电路422及一个第二发光元件421，或者可以包括多个第二像素电路422及多个第二发光元件421。当第二像素驱动单元42包括多个第二像素电路422及多个第二发光元件421时，每个第二像素驱动单元42中的第二像素电路422的数量例如等于第二发光元件421的数量，由此实现一一对应驱动。
例如，多个第二发光元件421阵列排布，多个第二像素电路422也阵列排布。这里，“阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图3和图4所示，每4个第二发光元件421为一组，多组第二发光元件421呈阵列排布，相应地，每4个第二像素电路422为一组，多组第二像素电路422呈阵列排布，此时，每个第二像素驱动单元42中包括4个第二像素电路422和4个第二发光元件421。
例如，如图5所示，第三显示区域13包括至少一个(例如多个)第三发光元件431和至少一个(例如多个)第三像素电路432。第三发光元件431与第三像素电路432一一对应地电连接，第三像素电路432用于驱动第三发光元件431发光。需要说明的是，图5中标号432所指示的矩形框仅用于示出第三像素电路432的大概位置，而并不表示第三像素电路432的具体形状以及第三像素电路432的具体边界。例如，多个第三发光元件431阵列排布，多个第三像素电路432也阵列排布。例如，至少一个第三发光元件431及其对应的第三像素电路432构成一个第三像素驱动单元43。
需要说明的是，在图5中，第三像素驱动单元43可以包括一个第三像素电路432及一个第三发光元件431，或者可以包括多个第三像素电路432及多个第三发光元件431。当第三像素驱动单元43包括多个第三像素电路432及多个第三发光元件431时，每个第三像素驱动单元43中的第三像素电路432的数量例如等于第三发光元件431的数量，由此实现一一对应驱动。
例如，多个第三发光元件431阵列排布，多个第三像素电路432也阵列排布。这里，“阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图5所示，每4个第三发光元件431为一组，多组第三发光元件431呈阵列排布，相应地，每4个第三像素电路432为一组，多组第三像素电路432呈阵列排布，此时，每个第三像素驱动单元43中包括4个第三像素电路432和4个第三发光元件431。
例如，第一显示区域11中多个第一发光元件411的单位面积分布密度小于第二显示区域12中多个第二发光元件421的单位面积分布密度；第二显示区域12中多个第二发光元件421的单位面积分布密度小于第三显示区域13中多个第三发光元件431的单位面积分布密度。例如，第一显示区域11和第二显示区域12可以被称为显示基板01的低分辨率区域，相应地，第三显示区域13可以被称为显示基板01的高分辨率区域。例如，第二显示区域 12与第一显示区域11的像素发光面积之和可以为第三显示区域13的像素发光面积的1/8～1/2。
需要说明的是，在一些示例中，第一显示区域11中多个第一发光元件411的单位面积分布密度也可以等于第二显示区域12中多个第二发光元件421的单位面积分布密度，这可以根据实际需求而定，本公开的实施例对此不作限制。
通过使第一显示区域11、第二显示区域12和第三显示区域13的发光元件的单位面积分布密度依次增大，可以在保证三个显示区域正常发光以显示画面的同时，便于显示基板01的第一侧的光线透过第一显示区域11以到达第二侧，进而便于设置在显示基板01的第二侧的传感器感测光线。
图6A为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之一，图6B为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之二，图6C为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图之三。例如，如图6A-6C所示，该显示基板01上设有至少一根第一信号线21、至少一根第二信号线22和至少一根第三信号线23。
例如，如图6A-6C所示，第一信号线21包括依次连接的第一主体部211、第一绕线部212、第一弯折部213和第一连接部214。第一主体部211和第一连接部214均沿第一方向延伸，第一方向例如为前述的多个像素电路或发光元件阵列排布的列方向。当然，本公开的实施例不限于此，第一方向也可以与列方向具有一定夹角，这可以根据实际需求而定。
例如，在一些示例中，第一主体部211和第一连接部214均为沿第一方向延伸的直线。例如，第一主体部211沿第一方向的虚拟延长线与第一连接部214沿第一方向的虚拟延长线不重叠，也即是，第一主体部211和第一连接部214在垂直于第一方向的方向上彼此错开。当然，本公开的实施例不限于此，第一主体部211和第一连接部214也可以为具有一定弧度的曲线，该曲线大体上沿着第一方向延伸。
例如，第一绕线部212沿曲线延伸。例如，第一绕线部212与第一显示区域11的边缘具有间距，第一绕线部212沿着第一显示区域11的边缘的延伸方向延伸。也即是，第一绕线部212不会穿过第一显示区域11，第一绕线部212至少部分围绕第一显示区域11分布。例如，在一些示例中，第一显示区域11的形状为圆形或椭圆形，相应地，第一绕线部212沿弧线延伸，该弧线的弧度小于或等于π。例如，第一绕线部212与第一显示区域11的边缘之前的间距可以设置为任意数值，本公开的实施例对此不作限制。第一弯折部213例如由多段折线组成，用于将第一绕线部212和第一连接部214连接。
例如，第一绕线部212、第一弯折部213和第一连接部214均位于第二显示区域12，第一主体部211至少部分位于第二显示区域12，第一主体部211沿第一方向的虚拟延长线穿过第一显示区域11。例如，第一主体部211、第一绕线部212、第一弯折部213和第一连接部214均不位于第一显示区域11。由此可以避免影响第一显示区域11的透光率。
例如，第一连接部214与第一像素电路412电连接。第一信号线21配置为向第一像素电路412传输第一驱动信号，以使第一像素电路412驱动第一发光元件411发光。例如， 在一些示例中，第一像素电路412通过连接线60与第一发光元件411电连接，由此可以驱动第一发光元件411发光。例如，在一些示例中，连接线60可以与第一发光元件411的阳极同层设置，并且与第一发光元件411的阳极一体形成。当然，本公开的实施例不限于此，可以采用任意适用的方式使第一像素电路412与第一发光元件411电连接，这可以根据实际需求而定。例如，在另一些示例中，可以单独设置一层ITO以形成连接线60，该层ITO例如位于源漏极金属层(SD层)与第一发光元件411的阳极层之间，并通过过孔使得连接线60分别与第一像素电路412和第一发光元件411电连接。
例如，如图6A和图6B所示，第二信号线22沿第一方向延伸且包括第一部分221和第二部分222。第一部分221位于第三显示区域13，第二部分222位于第二显示区域12。第一部分221与第三像素电路432电连接，第二部分222与第二像素电路422电连接。第二信号线22配置为向第二像素电路422和第三像素电路432传输第二驱动信号，以使第二像素电路422驱动第二发光元件421发光且使第三像素电路432驱动第三发光元件431发光。
需要说明的是，本公开的实施例中，第二信号线22既与第二像素电路422电连接，又与第三像素电路432电连接，但这并非表示提供给第二像素电路422的第二驱动信号和提供给第三像素电路432的第二驱动信号相同。例如，可以采用逐行扫描或分时扫描的方式，从而使提供给第二像素电路422的第二驱动信号和提供给第三像素电路432的第二驱动信号不同，以便于使对应的第二发光元件421和第三发光元件431分别显示需要的灰阶。
例如，如图6A和图6B所示，第三信号线23位于第二显示区域12且沿第一方向延伸，第三信号线23悬浮设置。例如，第三信号线23为沿第一方向延伸的直线。例如，第三信号线23为dummy线，不与任何像素电路电连接。由于第二显示区域12中多个第二发光元件421的单位面积分布密度小于第三显示区域13中多个第三发光元件431的单位面积分布密度，因此提供驱动信号(例如对应于显示灰阶的数据信号)的信号线在第二显示区域12的分布密度也小于其在第三显示区域13中的分布密度。提供驱动信号(例如对应于显示灰阶的数据信号)的信号线通常沿第一方向(列方向)延伸，因此通过在第二显示区域12中设置沿第一方向延伸的第三信号线23，可以有效减小信号线在第二显示区域12和第三显示区域13中的分布密度差异，有效平衡第二显示区域12内的电路环境，提升刻蚀均一性。
在本公开的实施例中，第一信号线21、第二信号线22和第三信号线23同时存在于显示区域(例如第二显示区域12)中，提供了多种不同的布线方式，从而可以满足不同显示区域的驱动需求，例如，同时满足第一显示区域11、第二显示区域12、第三显示区域13的驱动需求。并且，通过设置第三信号线23，使第三信号线23沿第一方向延伸，可以有效平衡电路环境。该显示基板01可以优化走线设计，提升版图布局的合理性，保证正常显示，有助于提高全面屏显示装置的性能。该显示基板01还可以提升具有屏下传感器的显示装置的性能。
例如，在一些示例中，如图6A和图6B所示，该显示基板01还包括至少一根第四信 号线24。第四信号线24位于第三显示区域13且沿第一方向延伸。例如，第四信号线24为沿第一方向延伸的直线。例如，第四信号线24与第三像素电路432电连接，第四信号线24配置为向第三像素电路432传输第三驱动信号，以使第三像素电路432驱动第三发光元件431发光。
例如，第三信号线23与第四信号线24位于同一条延伸线上，第三信号线23与第四信号线24之间具有间隙从而彼此绝缘。例如，该延伸线为直线。例如，第三信号线23和第四信号线24可以看作是同一条信号线被截断之后所形成的彼此绝缘的两部分。由此，第三信号线23在第二显示区域12中的分布密度可以基本等于第四信号线24在第三显示区域13中的分布密度，使得第二显示区域12总体上的信号线分布密度与第三显示区域13总体上的信号线分布密度相差不大，从而可以有效平衡显示区域(例如第二显示区域12和第三显示区域13)内的电路环境。而且，可以在同一工艺中形成第三信号线23和第四信号线24，从而提升刻蚀均一性，可以简化生产工艺，提高生产效率，降低生产成本。例如，在一些示例中，可以首先形成一条贯穿第三显示区域13和第二显示区域12的信号线，然后在第三显示区域13和第二显示区域12的交界处将该信号线截断，从而形成第三信号线23和第四信号线24，由此可以兼容通常的面板制造工艺。
图7为本公开至少一个实施例提供的另一种显示基板的部分区域的平面示意图。除了第一信号线21的设置方式不同，该实施例提供的显示基板01与图6A-6C所示的显示基板01基本相同。
例如，在一些实施例中，如图7所示，第一信号线21的第一主体部211包括第一子部211a和第二子部211b，第一子部211a位于第三显示区域13，第二子部211b位于第二显示区域12。第一子部211a与第三像素电路432电连接，第二子部211b与第二像素电路422电连接。例如，第一信号线21还配置为向第二像素电路422和第三像素电路432传输第一驱动信号，以使第二像素电路422驱动第二发光元件421发光且使第三像素电路432驱动第三发光元件431发光。
需要说明的是，在该实施例中，第一信号线21与第一像素电路412、第二像素电路422、第三像素电路432均电连接，但这并非表示提供给第一像素电路412的第一驱动信号、提供给第二像素电路422的第一驱动信号和提供给第三像素电路432的第一驱动信号相同。例如，可以采用逐行扫描或分时扫描的方式，从而使提供给第一像素电路412的第一驱动信号、提供给第二像素电路422的第一驱动信号和提供给第三像素电路432的第一驱动信号彼此不同，以便于使对应的第一发光元件411、第二发光元件421和第三发光元件431分别显示需要的灰阶。
例如，如图7所示，该显示基板01包括多个第二像素电路422和多个第三像素电路432。多个第二像素电路422沿第一方向呈多列排布，多个第三像素电路432沿第一方向呈多列排布。例如，与第一信号线21连接的第二像素电路422和与第二信号线22连接的第二像素电路422位于不同列。例如，与第一信号线21连接的第三像素电路432、与第二信号线22连接的第三像素电路432以及与第四信号线24连接的第三像素电路432位于不同 列。
需要说明的是，图7并未示出完整的多列像素电路，而仅示出了与第一信号线21、第二信号线22、第四信号线24电连接的几个像素电路，这并不构成对本公开实施例的限制。像素电路排布为多列的方式可以参考图3-5示出的结构以及参考常规设计，此处不再赘述。
图8A为本公开至少一个实施例提供的一种显示基板的示意版图之一，图8A例如为图1中的部分区域REG3的放大图。图8B为本公开至少一个实施例提供的一种显示基板的示意版图之二，图8B例如为图8A中的部分区域REG4的放大图。图8C为本公开至少一个实施例提供的一种显示基板的示意版图之三，图8C例如为图8A中的部分区域REG5的一种放大图。图8D为本公开至少一个实施例提供的一种显示基板的示意版图之四，图8D例如为图8A中的部分区域REG5的另一种放大图。
例如，如图8A所示，在该示例中，第一显示区域11中多个第一发光元件411的单位面积分布密度基本等于第二显示区域12中多个第二发光元件421的单位面积分布密度，第二显示区域12中多个第二发光元件421的单位面积分布密度小于第三显示区域13中多个第三发光元件431的单位面积分布密度。
第一信号线21可以通过第一像素电路412为像素密度较低的第一显示区域11内的第一发光元件411提供驱动信号，第一显示区域11对应的位置例如设置有传感器(例如摄像头)。由于第一显示区域11内没有像素电路，因此需要利用第一信号线21将驱动信号传输至第二显示区域12内的第一像素电路412，以使第一像素电路412驱动第一发光元件411发光。因此，第一信号线21需要从第三显示区域13引入并绕着第一显示区域11延伸，第一信号线21截止于图8B的S1位置。
第二信号线22可以从第三显示区域13沿第一方向(例如列方向)延伸至第二显示区域12，并截止于图8C所示的S2位置。第二信号线22穿过第三显示区域13和第二显示区域12。
第三信号线23与第四信号线24位于同一条延伸线上，第三信号线23与第四信号线24之间具有间隙从而彼此绝缘。因此，可以将第三信号线23与第四信号线24看作彼此断开，例如在图8B的S3位置处断开。第三信号线23起到dummy线的作用，从而可以平衡第二显示区域12内的电路环境。由于第二显示区域12和第三显示区域13的像素密度并不一致，因此在第二显示区域12中不需要驱动像素电路的像素位置处保留第三信号线23的走线并使第三信号线23与第四信号线24彼此断开，从而可以保持第二显示区域12的电路环境的均一性。
例如，如图8D所示，当显示基板01包括多条第一信号线21时，不同第一信号线21的第一弯折部213可以交替设置在不同的金属层中。例如，第一弯折部213_1、213_2、213_3、213_4分别属于4条不同的第一信号线21，第一弯折部213_1、213_2可以设置在栅极金属层，第一弯折部213_3、213_4可以设置在第一金属层，由此可以为布线提供便利，避免线路交叠处短路。这里，第一金属层可以为显示基板01中任意的不同于栅极金属层的膜层，本公开的实施例对此不作限制。
图9为本公开至少一个实施例提供的一种显示基板的部分区域的平面示意图。例如，如图9所示，在一些示例中，显示基板01包括多条第一信号线21、多条第二信号线22和多条第三信号线23。例如，多条第二信号线22与多条第三信号线23间隔设置，从而更有效地平衡第二显示区域12的电路环境。例如，多条第二信号线22与多条第一信号线21的第一连接部214间隔设置，从而可以有效利用第二显示区域12的布线空间，优化走线设计，提升版图布局的合理性。该显示基板01的其他结构与前述实施例所提供的显示基板01基本相同，此处不再赘述。
需要说明的是，第二信号线22与第三信号线23可以按照1:1的数量比例间隔设置，也可以按照2:1、3:1等任意的数量比例间隔设置，类似地，第二信号线22与第一连接部214可以按照1:1的数量比例间隔设置，也可以按照2:1、3:1等任意的数量比例间隔设置，这可以根据实际需求而定，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，第一信号线21、第二信号线22和第三信号线23各自的数量不受限制，这可以根据实际需求而定，例如根据显示基板01的尺寸、像素分布密度等因素而定，本公开的实施例对此不作限制。
例如，第一信号线21、第二信号线22和第四信号线24传输的驱动信号为数据信号，也即是，第一信号线21、第二信号线22和第四信号线24可以为数据线(data线)，第一驱动信号、第二驱动信号和第三驱动信号均为数据信号。例如，该数据信号与显示灰阶对应。例如，第一驱动信号、第二驱动信号、第三驱动信号可以为不同或相同的数据信号，本公开的实施例对此不作限制。
图10A为一种7T1C像素电路的结构示意图。例如，前述的第一像素电路412、第二像素电路422、第三像素电路432均可以采用该7T1C像素电路。
例如，如图10A所示，该7T1C像素电路100包括第一晶体管CT1、第二晶体管CT2、第三晶体管CT3、第四晶体管CT4、第五晶体管CT5、第六晶体管CT6、第七晶体管CT7和存储电容Cst。例如，第一晶体管CT1至第七晶体管CT7均为P型晶体管。
如图10A所示，存储电容Cst的第一端与第一电源电压端VDD相连，以接收第一电源电压V1，存储电容Cst的第二端与第一节点N1相连。发光元件EL的第一端与第四节点N4相连，发光元件EL的第二端与第二电源电压端VSS相连，以接收第二电源电压V2。第一晶体管CT1的控制端与第一节点N1相连，第一晶体管CT1的第一端与第二节点N2相连，第一晶体管CT1的第二端与第三节点N3相连。第二晶体管CT2的第一端与第二节点N2相连，第二晶体管CT2的第二端与数据信号端DAT相连，以接收数据信号(例如，数据电压)Vdata。第三晶体管CT3的第一端与第一节点N1相连，第三晶体管CT3的第二端与第三节点N3相连。
第四晶体管CT4的第一端与第一节点N1相连，第四晶体管CT4的第二端与第一复位信号端Init1相连，以接收第一复位信号端Init1提供的第一复位信号Vinit1。第五晶体管CT5的第一端与第一电源电压端VDD相连，第五晶体管CT5的第一端与第二节点N2相连。第六晶体管CT6的第一端与第四节点N4相连，第六晶体管CT6的第二端与第二复位 信号端Init2相连，以接收第二复位信号Vinit2。第七晶体管CT7的第一端与第三节点N3相连，第七晶体管CT7的第二端与第四节点N4相连。
例如，第二晶体管CT2的控制端GAT1和第三晶体管CT3的控制端GAT2均连接至扫描信号端GAT(图中未示出)，第五晶体管CT5的控制端EM1和第七晶体管CT7的控制端EM2均连接至发光控制端EM(图中未示出)，第四晶体管CT4的控制端被配置为连接第一复位控制端RST1，第六晶体管CT6的控制端被配置为连接第二复位控制端RST2。为描述方便，图10A还示出了第一节点N1、第二节点N2、第三节点N3、第四节点N4和发光元件EL。
图10B为图10A所示的7T1C像素电路的驱动时序图。如图10B所示，该7T1C像素电路100的每个驱动周期包括第一阶段t1、第二阶段t2和第三阶段t3。
如图10A和图10B所示，在第一阶段t1中，第一复位控制端RST1接收有效电平，扫描信号端GAT、第二复位控制端RST2和发光控制端EM均接收无效电平。此种情况下，第四晶体管CT4开启，第二晶体管CT2、第三晶体管CT3、第五晶体管CT5、第六晶体管CT6和第七晶体管CT7关闭；第四晶体管CT4被配置接收第一复位信号(例如，复位电压)Vinit1，且将第一复位信号Vinit1写入至存储电容Cst，以对存储电容Cst复位；第一节点N1的电压为Vinit1，Vinit1例如为负值。例如，在对存储电容Cst复位之后，第一晶体管CT1开启。
如图10A和图10B所示，在第二阶段t2中，扫描信号端GAT和第二复位控制端RST2接收有效电平，第一复位控制端RST1和发光控制端EM接收无效电平；此种情况下，第一晶体管CT1-第三晶体管CT3以及第六晶体管CT6开启，第四晶体管CT4、第五晶体管CT5和第七晶体管CT7关闭；第二晶体管CT2接收数据信号Vdata，且数据信号Vdata经由开启的第一晶体管CT1和第三晶体管CT3被写入至第一晶体管CT1的控制端，存储电容Cst在第一晶体管CT1的控制端存储被写入至第一晶体管CT1的控制端的数据信号Vdata，第一节点N1的电压为Vdata+Vth；第六晶体管CT6被配置接收第二复位信号(例如，复位电压)Vinit2，且将第二复位信号Vinit2写入至发光元件EL的第一端，以对发光元件EL的第一端复位，第四节点N4的电压为Vinit2，Vinit2例如为负值。
如图10A和图10B所示，在第三阶段t3中，发光控制端EM接收有效电平，第一复位控制端RST1、扫描信号端GAT和第二复位控制端RST2接收无效电平；此种情况下，第一晶体管CT1、第五晶体管CT5和第七晶体管CT7开启，第二晶体管CT2、第三晶体管CT3、第四晶体管CT4和第六晶体管CT6关闭；第一晶体管CT1被配置为，基于存储在存储电容Cst中的数据信号(例如，数据电压)Vdata以及所接收的第一电源电压V1，控制流经第一晶体管CT1且从第一电源电压端VDD至发光元件EL、用于驱动发光元件EL的驱动电流；第一节点N1的电压为Vdata+Vth，第二节点N2的电压为VDD；驱动电流Id可以由以下的公式表示：
Figure PCTCN2021087457-appb-000001
此处，k＝μ×Cox×W/L；μ为第一晶体管CT1中载流子的迁移率，Cox为第一晶体管CT1的栅氧化层的电容，W/L为第一晶体管CT1的沟道的宽长比，Vth为第一晶体管CT1的阈值电压，Vth为第一晶体管CT1的栅源电压，Vg为第一晶体管CT1的栅极电压，Vs为第一晶体管CT1的源极电压。
由上述公式可知，第一晶体管CT1生成的驱动电流Id与第一晶体管CT1的阈值电压无关，因此，图10A和图10B所示的7T1C像素电路100具有阈值补偿功能。
需要说明的是，本公开的实施例中，第一像素电路412、第二像素电路422、第三像素电路432不限于采用上述7T1C像素电路，还可以采用其他适用的像素电路，本公开的实施例对此不作限制。第一像素电路412、第二像素电路422、第三像素电路432的具体电路结构可以相同，也可以彼此不同，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，第一像素电路412、第二像素电路422和第三像素电路432中的每个包括开关薄膜晶体管，该开关薄膜晶体管例如为图10A中的第二晶体管CT2。例如，该开关薄膜晶体管(例如第二晶体管CT2)包括栅极、第一极和第二极，第一信号线21、第二信号线22或第四信号线24与该开关薄膜晶体管的第一极或第二极电连接。也即是，第一信号线21、第二信号线22或第四信号线24可以与图10A中的数据信号端DAT电连接，从而提供数据信号。
例如，前述的第一发光元件411、第二发光元件421和第三发光元件431包括有机发光二极管(OLED)。也即是，第一发光元件411、第二发光元件421或第三发光元件431可以为图10A中的发光元件EL，该发光元件EL可以为有机发光二极管(OLED)。当然，本公开的实施例不限于此，第一发光元件411、第二发光元件421和第三发光元件431还可以为量子点发光二极管(QLED)或其他适用的发光器件，本公开的实施例对此不作限制。
图11为本公开至少一个实施例提供的一种显示基板的叠层结构示意图，该叠层结构示意图主要示意性地示出了第一像素电路412和第一发光元件411。
例如，第一像素电路412包括开关薄膜晶体管412T和存储电容412C等结构。第一发光元件411包括第一阳极结构4111、第一阴极结构4113以及位于第一阳极结构4111与第一阴极结构4113之间的第一发光层4112，第一阳极结构4111通过过孔与第一像素电路412包括的开关薄膜晶体管412T电连接。例如，在一些示例中，第一阳极结构4111可以与前述的连接线60一体形成，也即是，连接线60可以看作是第一阳极结构4111的一部分。例 如，在另一些示例中，可以单独设置一层ITO以形成连接线60，该层ITO例如位于源漏极金属层(SD层)与第一阳极结构4111所在的膜层之间，并通过过孔实现所需要的电连接。例如，第一阳极结构4111可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未标示)，本公开的实施例对第一阳极结构4111的具体形式不做限定。
例如，第一阴极结构4113可以为显示基板01上整个表面上形成的结构，第一阴极结构4113例如可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。例如，由于第一阴极结构4113可以形成为很薄的一层，因此第一阴极结构4113具有良好的透光性。
例如，开关薄膜晶体管412T包括有源层4121、栅极4122和源漏电极(即源极4123和漏极4124)等结构，存储电容412C包括第一电容极板4125和第二电容极板4126。例如，有源层4121设置在衬底基板74上，有源层4121的远离衬底基板74的一侧设置有第一栅绝缘层741。栅极4122和第一电容极板4125同层设置，且位于第一栅绝缘层741的远离衬底基板74的一侧，栅极4122和第一电容极板4125的远离衬底基板74的一侧设置有第二栅绝缘层742。第二电容极板4126设置在第二栅绝缘层742的远离衬底基板74的一侧，第二电容极板4126的远离衬底基板74的一侧设置有层间绝缘层743。源漏电极设置在层间绝缘层743的远离衬底基板74的一侧，并通过位于第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4121电连接。源漏电极的远离衬底基板74的一侧设置有平坦化层744，以平坦化第一像素电路412。
例如，平坦化层744中具有过孔，第一阳极结构4111通过平坦化层744中过孔与开关薄膜晶体管412T的源极4123或漏极4124电连接。
例如，第一显示区域11还包括位于衬底基板74上的透明支撑层78，第一发光元件411位于透明支撑层78的远离衬底基板74的一侧。由此，相对于衬底基板74来说，第一显示区域11中的第一发光元件411可以与第二显示区域12中的第二发光元件421以及第三显示区域13中的第三发光元件431处于基本相同的高度，从而可以提高显示基板01的显示效果。
例如，在本公开的实施例中，第一主体部211、第一绕线部212、第一连接部214、第二信号线22和第三信号线23可以位于同一层。例如，在该显示基板01中，将源漏电极(即源极4123和漏极4124)所在的膜层称为源漏极金属层(SD层)，也即是，如图11所示，开关薄膜晶体管412T的第一极和第二极(即源极4123和漏极4124)位于源漏极金属层。例如，第一主体部211、第一绕线部212、第一连接部214、第二信号线22和第三信号线23位于源漏极金属层，也即，与源极4123和漏极4124同层设置。
例如，在本公开的实施例中，第一弯折部213与第一连接部214位于不同层，在第一主体部211、第一绕线部212、第一连接部214、第二信号线22和第三信号线23同层设置的情形下，第一弯折部213与第一主体部211、第一绕线部212、第一连接部214、第二信号线22和第三信号线23中的任意之一均位于不同层。例如，在该显示基板01中，将栅极4122所在的膜层称为栅极金属层，也即是，如图11所示，开关薄膜晶体管412T的栅极4122位于栅极金属层。例如，第一信号线21至少之一的第一弯折部213位于栅极金属层， 也即是，至少一条第一信号线21的第一弯折部213与栅极4122同层设置。例如，可以全部第一信号线21的第一弯折部213均位于栅极金属层，也可以仅有一部分第一信号线21的第一弯折部213位于栅极金属层，本公开的实施例对此不作限制。
例如，显示基板01还可以包括第一金属层，该第一金属层与栅极金属层为不同的膜层，第一金属层与栅极金属层绝缘。例如，第一金属层为显示基板01中任意的不同于栅极金属层的其他金属层。例如，在一些示例中，多条第一信号线21中的一部分第一信号线21的第一弯折部213位于栅极金属层，另一部分第一信号线21的第一弯折部213位于第一金属层。例如，不同第一信号线21的第一弯折部213可以交替设置在栅极金属层和第一金属层中。例如，如图11所示，不同第一信号线21的第一弯折部213可以交替地与栅极4122和第二电容极板4126同层设置，也即是，一部分第一信号线21的第一弯折部213与栅极4122同层设置，另一部分第一信号线21的第一弯折部213与第二电容极板4126同层设置。
通过上述设置方式，可以兼容现有工艺，对工艺的改动小，且便于布线，可以降低布线设计的难度。
当然，本公开的实施例不限于此，在其他一些示例中，第一信号线21、第二信号线22和第三信号线23也可以位于同一层，也即，在显示基板01中位于同一个膜层，从而可以减小显示基板01的厚度，并且便于在同一工艺中制备，简化制备工艺。第一信号线21、第二信号线22和第三信号线23的膜层关系可以根据实际需求而定，三者可以位于同一层或不同层，本公开的实施例对此不作限制。例如，第一信号线21、第二信号线22和第三信号线23中的任意两个可以位于同一层，而剩余的一个位于不同层；或者，也可以三者均位于不同层。例如，第四信号线24可以与第一信号线21、第二信号线22和第三信号线23中的任意一个或多个位于同一层，也可以与第一信号线21、第二信号线22和第三信号线23位于不同层，本公开的实施例对此不作限制。
例如，在一些示例中，第一信号线21、第二信号线22和第三信号线23包括金属走线，该金属走线的至少部分例如位于显示基板01的源漏极金属层。例如，该金属走线中除了第一弯折部213以外的部分均位于源漏极金属层。由此，可以在制备源漏极金属层中的源极和漏极时，一同制备第二信号线22、第三信号线23以及第一信号线21的第一主体部211、第一绕线部212和第一连接部214，从而可以简化生产工艺，提高生产效率，降低生产成本。在该情形中，可以在制备栅极金属层中的栅极时，一同制备作为第一弯折部213的金属走线。
例如，在另一些示例中，第一信号线21、第二信号线22和第三信号线23可以包括透明导电走线，该透明导电走线例如采用氧化铟锡(Indium tin oxide，ITO)制备。例如，可以在任意适当的膜层设置该透明导电走线，本公开的实施例对此不作限制。将第一信号线21、第二信号线22和第三信号线23设置为透明导电走线，可以提高显示基板01的透光率。
例如，在一些实施例中，如图11所示，该显示基板01还包括像素界定层746、封装层747等结构。例如，像素界定层746设置在第一阳极结构4111(例如第一阳极结构4111 的部分结构)上，包括多个开口以界定不同的像素或子像素，第一发光层4112形成在像素界定层746的开口中。例如，封装层747可以包括单层或多层封装结构，多层封装结构例如包括无机封装层和有机封装层的叠层，由此提高对显示基板01的封装效果。
例如，第一显示区域11、第二显示区域12和第三显示区域13中的像素界定层746是同层设置的，第一显示区域11、第二显示区域12和第三显示区域13中的封装层747是同层设置的，在一些实施例中还是一体连接的，本公开的实施例对此不作限制。
例如，本公开的各个实施例中，衬底基板74可以为玻璃基板、石英基板、金属基板或树脂类基板等，可以是刚性基板或柔性基板。本公开的实施例对此不作限制。
例如，第一栅极绝缘层741、第二栅极绝缘层742、层间绝缘层743以及平坦化层744、绝缘层745、像素界定层746、封装层747可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对上述各功能层的材料均不做具体限定。
例如，有源层4121的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等半导体材料。例如，有源层4121的部分可以通过掺杂等导体化处理以导体化，从而具有较高的导电性。
例如，栅极4122、第一电容极板4125和第二电容极板4126的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。
例如，源极4123和漏极4124的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/Ti)等。
例如，本公开实施例提供的显示基板01可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等，本公开的实施例对显示基板的具体种类不做限定。
例如，在显示基板为有机发光二极管显示基板的情形，发光层(例如前述的第一发光层4112)可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等。并且，根据实际不同需要，在不同的示例中，发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。
例如，在显示基板为量子点发光二极管(QLED)显示基板的情形，发光层(例如前述的第一发光层4112)可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径例如为2-20nm。
本公开至少一个实施例还提供一种显示装置，该显示装置包括本公开任一实施例提供的显示基板。该显示装置可以满足不同显示区域的驱动需求，并且可以平衡电路环境，优化走线设计，提升版图布局的合理性，保证正常显示，有助于提高全面屏显示装置的性能。
图12为本公开至少一个实施例提供的一种显示装置的示意框图。例如，如图12所示， 该显示装置30包括显示基板310，显示基板310为本公开任一实施例提供的显示基板，例如前述的显示基板01。该显示装置30可以为任何具有显示功能的电子装置，例如智能手机、笔记本电脑、平板电脑、电视等。例如，当显示装置30为智能手机或平板电脑时，该智能手机或平板电脑可以具有全面屏设计，也即是，没有围绕第三显示区域13的周边区域。并且，该智能手机或平板电脑还具有屏下传感器(例如摄像头、红外传感器等)，可以进行图像拍摄、距离感知、光强感知等操作。
需要说明的是，对于该显示基板310和显示装置30的其它组成部分(例如，图像数据编码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开实施例的限制。
图13为本公开至少一个实施例提供的一种显示装置的叠层结构示意图。例如，如图13所示，该显示装置30包括显示基板310，显示基板310为本公开任一实施例提供的显示基板，例如前述的显示基板01。例如，该显示装置30还包括传感器320。
例如，该显示基板01包括用于显示的第一侧F1和与第一侧F1相对的第二侧F2。也即是，第一侧F1为显示侧，第二侧F2为非显示侧。显示基板01被配置为在第一侧F1执行显示操作，也即，显示基板01的第一侧F1为显示基板01的出光侧，第一侧F1朝向用户。第一侧F1和第二侧F2在显示基板01的显示面的法线方向上对置。
如图13所示，传感器320设置于显示基板01的第二侧F2，并且传感器320配置为接收来自第一侧F1的光。例如，传感器320与第一显示区域11在显示基板01的显示面的法线方向(例如，垂直于显示基板01的方向)上叠置，传感器320可以接收并处理穿过第一显示区域11的光信号，该光信号可以为可见光、红外光等。例如，第一显示区域11允许来自第一侧F1的光至少部分透射至第二侧F2。例如，第一显示区域11未设置像素电路，此种情况下，可以提升第一显示区域11的透光率。
例如，传感器320在显示基板01上的正投影与第一显示区域11至少部分重叠。例如，在一些示例中，当采用直下式设置方式时，传感器320在显示基板01上的正投影位于第一显示区域11内。例如，在另一些示例中，当采用其他导光元件(例如导光板、导光管等)以使光线从侧面入射至传感器320上时，传感器320在显示基板01上的正投影与第一显示区域11部分重叠。此时，由于光线可以横向传播至传感器320，不需要传感器320完全位于对应于第一显示区域11的位置处。
例如，通过使第一像素电路412设置在第二显示区域12，并使传感器320与第一显示区域11在显示基板01的显示面的法线方向上叠置，可以减小第一显示区域11中的元件对入射至第一显示区域11并照射到传感器320的光信号的遮挡，由此可以提升传感器320输出的图像的信噪比。例如，第一显示区域11可以被称为显示基板01的低分辨率区域的高透光区。
例如，传感器320可以是图像传感器，可以用于采集传感器320的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器。该传感器320还可以是红外传感器、距离传感器等。例如，在该显示装置30为诸如手机、笔记本等移动终端的情 形下，该传感器320可实现为诸如手机、笔记本等移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。例如，该传感器320可以包括阵列排布感光像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，开关薄膜晶体管)。例如，光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
在一些示例中，第一发光元件411的阳极采用ITO/Ag/ITO的叠层结构，则在第一显示区域11中，仅有第一发光元件411的阳极不透光，也即，用于驱动第一发光元件411的走线绕过第一显示区域11或者设置为透明走线。此种情况下，不仅可以进一步地提升第一显示区域11的透光率，还可以降低第一显示区域11中的各个元件导致的衍射。
需要说明的是，本公开的实施例中，显示装置30还可以包括更多的部件和结构，本公开的实施例对此不作限制。关于该显示装置30的技术效果和详细说明，可以参考上文中关于显示基板01的描述，此处不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种显示基板，具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括显示区域；
    其中，所述显示区域包括第一显示区域、第二显示区域和第三显示区域，所述第二显示区域至少部分围绕所述第一显示区域，所述第三显示区域至少部分围绕所述第二显示区域，所述第一显示区域、所述第二显示区域和所述第三显示区域互不重叠；
    所述第一显示区域包括至少一个第一发光元件，且所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    所述第二显示区域包括至少一个第一像素电路、至少一个第二发光元件和至少一个第二像素电路，所述第一发光元件与所述第一像素电路电连接，所述第二发光元件与所述第二像素电路电连接；
    所述第三显示区域包括至少一个第三发光元件和至少一个第三像素电路，所述第三发光元件与所述第三像素电路电连接；
    所述显示基板上设有至少一根第一信号线、至少一根第二信号线和至少一根第三信号线；
    所述第一信号线包括依次连接的第一主体部、第一绕线部、第一弯折部和第一连接部；
    所述第一主体部和所述第一连接部均沿第一方向延伸，所述第一主体部沿所述第一方向的虚拟延长线与所述第一连接部沿所述第一方向的虚拟延长线不重叠，所述第一绕线部沿曲线延伸；
    所述第一绕线部、所述第一弯折部和所述第一连接部均位于所述第二显示区域，所述第一主体部至少部分位于所述第二显示区域，所述第一主体部沿所述第一方向的虚拟延长线穿过所述第一显示区域；
    所述第一连接部与所述第一像素电路电连接，所述第一信号线配置为向所述第一像素电路传输第一驱动信号，以使所述第一像素电路驱动所述第一发光元件发光；
    所述第二信号线沿所述第一方向延伸且包括第一部分和第二部分，所述第一部分位于所述第三显示区域，所述第二部分位于所述第二显示区域；
    所述第一部分与所述第三像素电路电连接，所述第二部分与所述第二像素电路电连接，所述第二信号线配置为向所述第二像素电路和所述第三像素电路传输第二驱动信号，以使所述第二像素电路驱动所述第二发光元件发光且使所述第三像素电路驱动所述第三发光元件发光；
    所述第三信号线位于所述第二显示区域且沿所述第一方向延伸，所述第三信号线悬浮设置。
  2. 根据权利要求1所述的显示基板，还包括至少一根第四信号线；
    其中，所述第四信号线位于所述第三显示区域且沿所述第一方向延伸，所述第四信号 线与所述第三像素电路电连接，所述第四信号线配置为向所述第三像素电路传输第三驱动信号，以使所述第三像素电路驱动所述第三发光元件发光；
    所述第三信号线与所述第四信号线位于同一条延伸线上，所述第三信号线与所述第四信号线之间具有间隙从而彼此绝缘。
  3. 根据权利要求2所述的显示基板，其中，所述延伸线为直线。
  4. 根据权利要求2或3所述的显示基板，其中，所述第一信号线的所述第一主体部包括第一子部和第二子部，所述第一子部位于所述第三显示区域，所述第二子部位于所述第二显示区域；
    所述第一子部与所述第三像素电路电连接，所述第二子部与所述第二像素电路电连接；
    所述第一信号线还配置为向所述第二像素电路和所述第三像素电路传输所述第一驱动信号，以使所述第二像素电路驱动所述第二发光元件发光且使所述第三像素电路驱动所述第三发光元件发光。
  5. 根据权利要求4所述的显示基板，其中，所述至少一个第二像素电路包括多个第二像素电路，所述多个第二像素电路沿所述第一方向呈多列排布；
    与所述第一信号线连接的第二像素电路和与所述第二信号线连接的第二像素电路位于不同列。
  6. 根据权利要求4或5所述的显示基板，其中，所述至少一个第三像素电路包括多个第三像素电路，所述多个第三像素电路沿所述第一方向呈多列排布；
    与所述第一信号线连接的第三像素电路、与所述第二信号线连接的第三像素电路以及与所述第四信号线连接的第三像素电路位于不同列。
  7. 根据权利要求1-6任一所述的显示基板，其中，所述第一绕线部与所述第一显示区域的边缘具有间距，所述第一绕线部沿着所述第一显示区域的边缘的延伸方向延伸。
  8. 根据权利要求7所述的显示基板，其中，所述第一显示区域的形状为圆形或椭圆形，所述第一绕线部沿弧线延伸。
  9. 根据权利要求1-6任一所述的显示基板，其中，所述至少一条第二信号线包括多条第二信号线，所述至少一条第三信号线包括多条第三信号线，所述多条第二信号线与所述多条第三信号线间隔设置。
  10. 根据权利要求1-6任一所述的显示基板，其中，所述至少一条第二信号线包括多条第二信号线，所述至少一条第一信号线包括多条第一信号线，所述多条第二信号线与所述多条第一信号线的第一连接部间隔设置。
  11. 根据权利要求2-6任一所述的显示基板，其中，所述第一驱动信号、所述第二驱动信号、所述第三驱动信号为不同或相同的数据信号，所述数据信号与显示灰阶对应。
  12. 根据权利要求2-6任一所述的显示基板，其中，所述第一像素电路、所述第二像素电路和所述第三像素电路中的每个包括开关薄膜晶体管，所述开关薄膜晶体管包括栅极、第一极和第二极；
    所述第一信号线、所述第二信号线或所述第四信号线与所述开关薄膜晶体管的第一极 或第二极电连接。
  13. 根据权利要求12所述的显示基板，其中，所述第一主体部、所述第一绕线部、所述第一连接部、所述第二信号线和所述第三信号线位于同一层。
  14. 根据权利要求13所述的显示基板，还包括源漏极金属层，
    其中，所述开关薄膜晶体管的第一极和第二极位于所述源漏极金属层，
    所述第一主体部、所述第一绕线部、所述第一连接部、所述第二信号线和所述第三信号线位于所述源漏极金属层。
  15. 根据权利要求13或14所述的显示基板，其中，所述第一弯折部与所述第一连接部位于不同层。
  16. 根据权利要求15所述的显示基板，还包括栅极金属层，
    其中，所述开关薄膜晶体管的栅极位于所述栅极金属层，
    所述第一信号线至少之一的第一弯折部位于所述栅极金属层。
  17. 根据权利要求16所述的显示基板，还包括第一金属层，
    其中，所述第一金属层与所述栅极金属层为不同的膜层，且与所述栅极金属层绝缘，
    所述至少一条第一信号线包括多条第一信号线，一部分第一信号线的第一弯折部位于所述栅极金属层，另一部分第一信号线的第一弯折部位于所述第一金属层。
  18. 根据权利要求1-17任一所述的显示基板，其中，所述第一信号线、所述第二信号线和所述第三信号线包括金属走线或透明导电走线。
  19. 根据权利要求1-18任一所述的显示基板，其中，所述第一发光元件、所述第二发光元件和所述第三发光元件包括有机发光二极管。
  20. 根据权利要求1-19任一所述的显示基板，其中，所述第二发光元件在所述第二显示区域内的单位面积分布密度小于所述第三发光元件在所述第三显示区域内的单位面积分布密度。
  21. 一种显示装置，包括如权利要求1-20任一所述的显示基板。
  22. 根据权利要求21所述的显示装置，还包括传感器，其中，所述传感器设置于所述显示基板的第二侧，所述传感器配置为接收来自所述第一侧的光。
  23. 根据权利要求22所述的显示装置，其中，所述传感器在所述显示基板上的正投影与所述第一显示区域至少部分重叠。
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