WO2023230785A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023230785A1
WO2023230785A1 PCT/CN2022/096056 CN2022096056W WO2023230785A1 WO 2023230785 A1 WO2023230785 A1 WO 2023230785A1 CN 2022096056 W CN2022096056 W CN 2022096056W WO 2023230785 A1 WO2023230785 A1 WO 2023230785A1
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WIPO (PCT)
Prior art keywords
area
display
light
substrate
pixel circuit
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Application number
PCT/CN2022/096056
Other languages
English (en)
French (fr)
Inventor
朱健超
商广良
刘利宾
史世明
张玉欣
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/096056 priority Critical patent/WO2023230785A1/zh
Priority to CN202310822515.9A priority patent/CN117156901A/zh
Priority to CN202280001581.3A priority patent/CN115152031B/zh
Priority to CN202211497510.5A priority patent/CN115835698B/zh
Publication of WO2023230785A1 publication Critical patent/WO2023230785A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • this embodiment provides a display substrate, including: a first display area.
  • the first display area includes: a plurality of display island areas separated from each other, a light-transmitting area located between adjacent display island areas, and a connection area connecting adjacent display island areas.
  • the display island area includes: a first pixel unit provided on a substrate, the first pixel unit includes: a first area pixel circuit and a first area light-emitting element electrically connected to the first area pixel circuit; The front projection of the first area pixel circuit on the substrate overlaps with the front projection of the electrically connected first area light-emitting element on the substrate.
  • the display island area has an arc edge.
  • the display island is circular or elliptical.
  • the edges of the light-transmitting area include: a first edge in contact with the connection area, and a second edge in contact with the display island area; the first edge and the third edge are in contact with the display island area.
  • the two edges are connected at intervals, and the second edge is arc-shaped.
  • the light-transmitting area is octagonal.
  • the first edge of the light-transmitting area is linear, wavy or zigzag.
  • the display island area includes a first pixel unit, the first pixel unit includes: three first area light-emitting elements; the three first area light-emitting elements include: an emitting first area A first light-emitting element that emits color light, a second light-emitting element that emits second color light, and a third light-emitting element that emits third color light.
  • the light-emitting areas of the first light-emitting element, the second light-emitting element and the third light-emitting element form a circular or elliptical shape as a whole.
  • the first pixel unit further includes: three first area pixel circuits, and the three first area pixel circuits and the three first area light-emitting elements are electrically connected in a one-to-one correspondence.
  • the three first area pixel circuits are arranged in sequence along the first direction; the first light-emitting element and the second light-emitting element are arranged in sequence in the second direction, and the third light-emitting element is arranged in the first direction.
  • the first direction intersects the second direction.
  • the display island area further includes: a plurality of data lines; at least one first area pixel circuit is electrically connected to one data line, and the first area pixel circuit is on the front side of the substrate.
  • the projection overlaps with the orthographic projection of the two data lines on the substrate. At least one data line among the plurality of data lines surrounds the outside of all first area pixel circuits of the first pixel unit.
  • the first pixel unit includes three first area pixel circuits; the three first area pixel circuits include first pixel circuits and second pixel circuits arranged sequentially along the first direction. and a third pixel circuit.
  • the display island area includes: first to twelfth data lines arranged sequentially along the first direction. The first to third data lines are located on one side of the three first area pixel circuits in the first direction, and the tenth to twelfth data lines are located on one side of the three first area pixel circuits in the first direction. The other side of the three first area pixel circuits.
  • the first pixel circuit is electrically connected to the fourth data line, and the front projection of the first pixel circuit on the substrate and the front projection of the fourth and fifth data lines on the substrate exist. overlap.
  • the second pixel circuit is electrically connected to the sixth data line, and the orthographic projection of the second pixel circuit on the substrate and the orthographic projection of the sixth and seventh data lines on the substrate exist. overlap.
  • the third pixel circuit is electrically connected to the eighth data line, and the orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the eighth and ninth data lines on the substrate. .
  • the first to third data lines and the tenth to twelfth data lines are all bent in the first direction away from the first region pixel circuit.
  • arc-shaped wiring wherein the bending directions of the first to third data lines are different from the bending directions of the tenth to twelfth data lines.
  • the first to third data lines and the tenth to twelfth data lines are in the same layer structure, and are located far away from the fourth to ninth data lines. one side of the substrate.
  • the first area pixel circuit includes: at least one first type transistor, at least one second type transistor, and a storage capacitor, and the first type transistor and the second type transistor have different transistor types.
  • the first display area at least includes: a substrate and a first semiconductor layer, a second conductive layer, a second semiconductor layer disposed on the substrate layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer.
  • the first semiconductor layer includes at least an active layer of a first type transistor of the first region pixel circuit.
  • the second conductive layer at least includes: a gate electrode of a first type transistor of the first region pixel circuit.
  • the second semiconductor layer includes at least an active layer of a second type transistor of the first region pixel circuit.
  • the third conductive layer at least includes: the gate electrode of the second type transistor of the first region pixel circuit.
  • the fourth conductive layer at least includes: a plurality of scanning signal lines electrically connected to the pixel circuit in the first region.
  • the fifth conductive layer at least includes: a plurality of data lines electrically connected to or overlapping the first area pixel circuit.
  • the sixth conductive layer at least includes: a plurality of data lines located on the periphery of the first area pixel circuit.
  • the first semiconductor layer, the second conductive layer, the second semiconductor layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and The sixth conductive layer is sequentially disposed on the substrate.
  • the sixth conductive layer of the display island region further includes: a power transmission line that transmits a first voltage signal, a power transmission line that transmits a second voltage signal, an initial transmission line that transmits a first initial signal, and a transmission line that transmits a first initial signal. Initial transmission line for the second initial signal.
  • the display substrate further includes: a second display area located on at least one side of the first display area; the second display area includes: a second pixel unit disposed on the substrate, The second pixel unit includes: a second area pixel circuit and a second area light-emitting element electrically connected to the second area pixel circuit; the second area pixel circuit is electrically connected to the front projection of the substrate.
  • the orthographic projections of the second area light-emitting elements on the substrate overlap. Wherein, the density of the first pixel units in the first display area is smaller than the density of the second pixel units in the second display area.
  • two rows of second pixel units in the second display area correspond to one row of first pixel units in the first display area
  • two columns of second pixel units in the second display area correspond to One column of first pixel units corresponds to the first display area.
  • the second display area further includes: a plurality of data lines, and the second area pixel circuit in the 2nth row and jth column is connected to the second area pixel circuit in the 2n-1th row and jth column.
  • Different data lines where n and j are both integers.
  • the first display area further includes: a pixel definition layer and a black matrix located on a side of the pixel definition layer away from the substrate.
  • the pixel definition layer of the display island area has a pixel opening, and the pixel opening exposes a part of the anode of the light-emitting element in the first area;
  • the black matrix has a matrix opening;
  • the matrix opening covers the orthographic projection of the substrate The orthographic projection of the pixel opening on the substrate, and the orthographic projection of the anode of the first area light-emitting element on the substrate covers the orthographic projection of the matrix opening on the substrate.
  • the black matrix covers the connection area.
  • this embodiment provides a display device, including the display substrate as described above and a sensor located on the non-display side of the display substrate, where the front projection of the sensor and the display There is overlap in the first display area of the substrate.
  • Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a working timing diagram of the pixel circuit shown in Figure 2;
  • Figure 4 is a partial diagram of the first display area according to at least one embodiment of the present disclosure.
  • Figure 5 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • 6A to 6D are partial enlarged schematic views of the first edge of at least one embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram of the arrangement of the first area light-emitting elements and the first area pixel circuit in the first display area according to at least one embodiment of the present disclosure
  • FIG. 7B is a schematic diagram of the arrangement of the second area light-emitting elements and the second area pixel circuit in the second display area according to at least one embodiment of the present disclosure
  • Figure 7C is a partial schematic diagram of area S1 in Figure 1;
  • Figure 8 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure.
  • 9A is a partially enlarged schematic diagram of the display substrate after forming the first conductive layer in the first display area according to at least one embodiment of the present disclosure
  • 9B is a partially enlarged schematic diagram of the display substrate after forming the first conductive layer in the second display area according to at least one embodiment of the present disclosure
  • FIG. 10A is a partially enlarged schematic diagram of the display substrate after forming the first semiconductor layer in the first display area according to at least one embodiment of the present disclosure
  • 10B is a partially enlarged schematic view of the display substrate after forming the first semiconductor layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 11A is a schematic diagram of the first semiconductor layer in Figure 10A;
  • Figure 11B is a schematic diagram of the first semiconductor layer in Figure 10B;
  • FIG. 12A is a partially enlarged schematic view of the display substrate after forming the second conductive layer in the first display area according to at least one embodiment of the present disclosure
  • FIG. 12B is a partially enlarged schematic view of the display substrate after forming the second conductive layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 13A is a schematic diagram of the second conductive layer in Figure 12A;
  • Figure 13B is a schematic diagram of the second conductive layer in Figure 12B;
  • 14A is a partially enlarged schematic view of the display substrate after forming the second semiconductor layer in the first display area according to at least one embodiment of the present disclosure
  • 14B is a partially enlarged schematic view of the display substrate after forming the second semiconductor layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 15A is a schematic diagram of the second semiconductor layer in Figure 14A;
  • Figure 15B is a schematic diagram of the second semiconductor layer in Figure 14B;
  • 16A is a partially enlarged schematic view of the display substrate after forming a third conductive layer in the first display area according to at least one embodiment of the present disclosure
  • 16B is a partially enlarged schematic diagram of the display substrate after forming a third conductive layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 17A is a schematic diagram of the third conductive layer in Figure 16A;
  • Figure 17B is a schematic diagram of the third conductive layer in Figure 16B;
  • 18A is a partially enlarged schematic diagram of the display substrate after forming the fifth insulating layer in the first display area according to at least one embodiment of the present disclosure
  • FIG. 18B is a partially enlarged schematic view of the display substrate after forming the fifth insulating layer in the second display area according to at least one embodiment of the present disclosure
  • FIG. 19A is a partially enlarged schematic view of the display substrate after forming a fourth conductive layer in the first display area according to at least one embodiment of the present disclosure
  • 19B is a partially enlarged schematic view of the display substrate after forming a fourth conductive layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 20A is a schematic diagram of the fourth conductive layer in Figure 19A;
  • Figure 20B is a schematic diagram of the fourth conductive layer in Figure 19B;
  • 21A is a partially enlarged schematic diagram of the display substrate after forming a sixth insulating layer in the first display area according to at least one embodiment of the present disclosure
  • Figure 21B is a partially enlarged schematic diagram of the display substrate after the sixth insulating layer is formed in the second display area according to at least one embodiment of the present disclosure
  • 22A is a partially enlarged schematic view of the display substrate after forming the fifth conductive layer in the first display area according to at least one embodiment of the present disclosure
  • 22B is a partially enlarged schematic diagram of the display substrate after forming the fifth conductive layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 23A is a schematic diagram of the fifth conductive layer in Figure 22A;
  • Figure 23B is a schematic diagram of the fifth conductive layer in Figure 22B;
  • 24A is a partially enlarged schematic diagram of the display substrate after forming a seventh insulating layer in the first display area according to at least one embodiment of the present disclosure
  • 24B is a partially enlarged schematic view of the display substrate after forming a seventh insulating layer in the second display area according to at least one embodiment of the present disclosure
  • FIG. 25A is a partially enlarged schematic diagram of the display substrate after the sixth conductive layer is formed in the first display area according to at least one embodiment of the present disclosure
  • 25B is a partially enlarged schematic view of the display substrate after forming a sixth conductive layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 26A is a schematic diagram of the sixth conductive layer in Figure 25A;
  • Figure 26B is a schematic diagram of the sixth conductive layer in Figure 25B;
  • FIG. 27A is a partially enlarged schematic diagram of the display substrate after forming an eighth insulating layer in the first display area according to at least one embodiment of the present disclosure
  • FIG. 27B is a partially enlarged schematic view of the display substrate after forming an eighth insulating layer in the second display area according to at least one embodiment of the present disclosure
  • 28A is a partially enlarged schematic view of the display substrate after forming an anode layer in the first display region according to at least one embodiment of the present disclosure
  • FIG. 28B is a partially enlarged schematic diagram of the display substrate after forming an anode layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 29A is a schematic diagram of the anode layer in Figure 28A;
  • Figure 29B is a schematic diagram of the anode layer in Figure 28B;
  • FIG. 30A is a partially enlarged schematic diagram of the display substrate after forming a pixel definition layer in the first display area according to at least one embodiment of the present disclosure
  • FIG. 30B is a partially enlarged schematic diagram of the display substrate after forming a pixel definition layer in the second display area according to at least one embodiment of the present disclosure
  • Figure 31 is a partial cross-sectional schematic diagram along the Q-Q' direction in Figure 30A;
  • FIG. 32A is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • 32B is a partial schematic diagram of the display substrate after forming a black matrix in the first display area according to at least one embodiment
  • Figure 32C is a schematic diagram of the black matrix in Figure 32B;
  • FIG. 33 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • circles, ovals, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, and may be approximately circles, approximately ellipses, approximately triangles, approximately rectangles, approximately trapezoids, Approximate pentagons or approximate hexagons may have some small deformations caused by tolerances, such as leading corners, arc edges, and deformations.
  • Light transmittance in this disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part The length of the portion extending along direction B is greater than the length of the minor portion extending along the other directions. “A extends along direction B” mentioned in this disclosure all means “the main body part of A extends along direction B”.
  • An embodiment of the present disclosure provides a display substrate, including: a first display area.
  • the first display area includes: a plurality of display island areas separated from each other, a light-transmitting area located between adjacent display island areas, and a connection area connecting adjacent display island areas.
  • the display island area includes: a first pixel unit disposed on the substrate.
  • the first pixel unit includes: a first regional pixel circuit and a first regional light-emitting element electrically connected to the first regional pixel circuit.
  • the front projection of the first area pixel circuit on the substrate overlaps with the front projection of the electrically connected first area light-emitting element on the substrate. Display islands have curved edges.
  • the edge shape of the display island area may be determined by the arrangement and shape of the signal traces in the display island area, or the edge shape of the display island area may be determined by the edge of the black matrix provided in the display island area.
  • this embodiment is not limited to this.
  • the display substrate provided in this embodiment can reduce the light diffraction effect of the display substrate by setting the edge of the display island area in an arc shape, thereby improving the display effect and shooting effect of the display device.
  • the display island may be circular or elliptical.
  • this embodiment is not limited to this.
  • the edge of the display island area may be formed by connecting multiple arc segments.
  • the arcs of the multiple arc segments may be the same, or the arcs of some of the arc segments may be the same, or the arcs of the multiple arc segments may be different.
  • the edges of the light-transmitting area may include: a first edge in contact with the connection area, and a second edge in contact with the display island area.
  • the first edge is spaced apart from the second edge.
  • the second edge is curved. There is no right angle formed between the first edge and the second edge, that is, neither the first edge nor the second edge is a right-angled edge, thereby reducing the light diffraction effect of the display substrate.
  • the light-transmitting area may be octagonal.
  • the light-transmitting area may be surrounded by four display island areas and four connection areas, thereby forming an octagonal light-transmitting area.
  • the first edge of the light-transmitting area may be linear, wavy or zigzag.
  • the connection area may be a strip area, and the connection area may be connected to the adjacent display island area.
  • the first edge of the light-transmitting area is the edge of the connecting area close to the light-transmitting area.
  • the first edge may be a flat edge, or the first edge may be uneven.
  • the first edge may include at least one of the following: protrusion. Department, depression.
  • the second edge of the connection area may be an arc-shaped flat edge, or may include at least one of the following: a protrusion, a recess.
  • a display island may include a first pixel unit.
  • the first pixel unit may include: three first area light-emitting elements.
  • the three first area light-emitting elements may include: a first light-emitting element that emits light of a first color, a second light-emitting element that emits light of a second color, and a third light-emitting element that emits light of a third color.
  • the first color light, the second color light and the third color light may be lights of different colors.
  • the first color light may be green light
  • the second color light may be red light
  • the third color light may be blue light.
  • this embodiment is not limited to this.
  • the first pixel units can be evenly distributed, thereby effectively improving the display effect of the first display area.
  • the entire light-emitting area of the first, second, and third light-emitting elements of the display island region may form a circular or elliptical shape. In this way, it can be ensured that the light-transmitting area has no right-angled edges, thereby reducing the diffraction effect of the display substrate.
  • the light-emitting area of the light-emitting element may be a portion of the light-emitting element located in the pixel opening of the pixel definition layer.
  • the first pixel unit may further include: three first area pixel circuits.
  • the three first area pixel circuits and the three first area light emitting elements are electrically connected in a one-to-one correspondence.
  • the three first area pixel circuits may be arranged sequentially along the first direction.
  • the first light-emitting element and the second light-emitting element may be arranged sequentially in the second direction, and the third light-emitting element may be located on the same side of the first light-emitting element and the second light-emitting element in the first direction.
  • the first direction intersects the second direction.
  • the first direction and the second direction are perpendicular to each other.
  • the display island area may further include: a plurality of data lines.
  • the first area pixel circuit in the display island area is electrically connected to one data line, and the front projection of the first area pixel circuit on the substrate overlaps with the front projection of the two data lines on the substrate.
  • At least one data line among the plurality of data lines in the display island area surrounds the outside of all the first area pixel circuits of the first pixel unit.
  • the multiple data lines in the display island area can be divided into two groups, the first group of data lines can pass through the first area pixel circuit, and the second group of data lines can bypass the first area pixel circuit, thereby reducing Mutual interference between the data lines and the first area pixel circuit.
  • the second set of data lines may be located on a side of the first set of data lines away from the substrate in a direction perpendicular to the display substrate.
  • the first area pixel circuit may include: at least one first type transistor, at least one second type transistor, and a storage capacitor, and the first type transistor and the second type transistor may have different transistor types.
  • the first type transistor may be a P-type transistor
  • the second type transistor may be an N-type transistor.
  • the display substrate may further include: a second display area located on at least one side of the first display area.
  • the second display area may include: at least one second pixel unit disposed on the substrate.
  • the second pixel unit may include: at least one second area pixel circuit and at least one second area light-emitting element; the at least one second area pixel circuit is electrically connected to the at least one second area light-emitting element, and the at least one An orthographic projection of the second area pixel circuit on the substrate overlaps with an orthographic projection of the at least one second area light-emitting element on the substrate.
  • the density of the first pixel units in the first display area may be smaller than the density of the second pixel units in the second display area.
  • the display substrate of this example can ensure the light transmittance of the first display area.
  • two rows of second pixel units in the second display area may correspond to one row of first pixel units in the first display area, and two columns of second pixel units in the second display area may correspond to two rows of second pixel units in the first display area.
  • a column of first pixel units can correspond.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2.
  • the second display area A2 may be located at at least one side of the first display area A1.
  • the first display area A1 may be located at the top middle position of the display area AA, and the second display area A2 may surround the first display area A1.
  • this embodiment is not limited to this.
  • the first display area A1 may be located at other locations such as the upper left corner or the upper right corner of the display area AA.
  • the first display area A1 may also be called an under-display camera (UDC, Under Display Camera) area
  • the second display area A2 may also be called a normal display area.
  • the orthographic projection of hardware such as sensors (eg, cameras, infrared sensors) on the display substrate may be located in the first display area A1 of the display substrate.
  • the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be smaller than or equal to the size of the first display area A1 .
  • this embodiment is not limited to this.
  • the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the first display area A1 may be circular or elliptical. However, this embodiment is not limited to this.
  • the first display area A1 may be in a rectangular, pentagonal, hexagonal or other shape.
  • the display area AA may be a flat area, and the display area AA may at least include a plurality of regularly arranged pixel units. Multiple pixel units can be configured to display moving pictures or still images.
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling.
  • One pixel unit may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively. However, this embodiment is not limited to this. In other examples, one pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • At least one subpixel may include a pixel circuit and a light emitting element.
  • the pixel circuit may be configured to drive connected light emitting elements.
  • the pixel circuit may be configured to provide a driving current to drive the light emitting element to emit light.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, an 8T1C (8 transistors and 1 capacitor) structure, or a 7T1C (7 transistors and 1 capacitor) structure. capacitor) structure or 5T1C (5 transistors and 1 capacitor) structure.
  • the light-emitting element may be an organic light-emitting diode (OLED).
  • the light-emitting element emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the light-emitting color of the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • the shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically or vertically.
  • the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically or horizontally. Arranged in straight rows or squares. However, this embodiment is not limited to this.
  • the pixel circuit may include: at least one first type transistor, at least one second type transistor, and a storage capacitor.
  • the first type transistor may be a P-type transistor
  • the second type transistor may be an N-type transistor.
  • the first type transistor may be a low temperature polysilicon thin film transistor
  • the second type transistor may be an oxide thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor can be low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor can be oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polysilicon thin film transistors (LTPS). +Oxide) display substrate, you can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • this embodiment is not limited to this.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit may have an 8T1C structure, that is, it may include first to eighth transistors T1 to T8 and a storage capacitor Cst.
  • the first to seventh transistors T1 to T7 may be first type transistors, such as P-type transistors
  • the eighth transistor T8 may be a second type transistor, such as N-type transistors.
  • this embodiment is not limited to this.
  • the plurality of transistors of the pixel circuit may all be P-type transistors, or may all be N-type transistors.
  • the first type transistors may employ low-temperature polysilicon thin film transistors
  • the second type transistors eg, the eighth transistor T8
  • oxide thin film transistors may be employed.
  • this embodiment is not limited to this.
  • the multiple transistors of the pixel circuit may all use low-temperature polysilicon thin film transistors, or they may all use oxide thin film transistors.
  • the pixel circuit may be connected to ten signal lines (for example, including: data line DL, first power line VDD, second power line VSS, first scan signal line GL1, second scan signal line The signal line GL2, the third scanning signal line RST1, the fourth scanning signal line RST2, the light emission control line EML, the first initial signal line INIT1, and the second initial signal line INIT2) are electrically connected.
  • ten signal lines for example, including: data line DL, first power line VDD, second power line VSS, first scan signal line GL1, second scan signal line The signal line GL2, the third scanning signal line RST1, the fourth scanning signal line RST2, the light emission control line EML, the first initial signal line INIT1, and the second initial signal line INIT2
  • the first power line VDD may be configured to provide a constant first voltage signal to the pixel circuit
  • the second power line VSS may be configured to provide a constant second voltage signal to the pixel circuit
  • the first voltage signal may be greater than second voltage signal.
  • the first scan signal line GL1 may be configured to provide the first scan signal SCAN1 to the pixel circuit
  • the second scan signal line GL2 may be configured to provide the second scan signal SCAN2 to the pixel circuit
  • the third scan signal line RST1 may be configured to provide the pixel circuit with the second scan signal SCAN2.
  • the first reset control signal RESET1 is provided
  • the fourth scanning signal line RST2 may be configured to provide the second reset control signal RESET2 to the pixel circuit.
  • the data line DL may be configured to provide the data signal DATA to the pixel circuit
  • the emission control line EML may be configured to provide the emission control signal EM to the pixel circuit.
  • the third scanning signal line RST1 may be connected to the first scanning signal line GL1 of the n-1th row of pixel circuits to be input with the first scanning signal SCAN1(n-1) , that is, the first reset control signal RESET1(n) and the first scan signal SCAN1(n-1) may be the same.
  • the fourth scanning signal line RST2 electrically connected to the n-th row of pixel circuits and the third scanning signal line RST1 electrically connected to the n-th row of pixel circuits may have an integrated structure. That is, the first reset control signal RESET1(n) and the second reset control signal RESET2(n) may be the same. In this way, the signal lines of the display substrate can be reduced and the narrow frame of the display substrate can be achieved.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but are not limited to this.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the gate electrode of the third transistor T3 is electrically connected to the first node N1
  • the first electrode of the third transistor T3 is electrically connected to the second node N2
  • the second electrode of the third transistor T3 It is electrically connected to the third node N3.
  • the third transistor T3 may be called a driving transistor.
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scanning signal line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.
  • the fourth transistor T4 may be called a data writing transistor.
  • the gate electrode of the second transistor T2 is electrically connected to the first scanning signal line GL1, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the second transistor T2 may be called a threshold compensation transistor.
  • the gate electrode of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emission control transistors.
  • the gate electrode of the first transistor T1 is electrically connected to the third scanning signal line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. .
  • the gate electrode of the seventh transistor T7 is electrically connected to the fourth scanning signal line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. .
  • the first transistor T1 and the seventh transistor T7 may be called reset control transistors.
  • the gate electrode of the eighth transistor T8 is electrically connected to the second scanning signal line GL2, the first electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the first node N1, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power line VDD.
  • the first node N1 is a connection point of the storage capacitor Cst
  • the eighth transistor T8 and the third transistor T3 and the second node N2 is a connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3,
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6.
  • the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.
  • the fifth node N5 is The connection point of the first transistor T1, the second transistor T2 and the eighth transistor T8.
  • the light-emitting element EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), Quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light emitting element EL may be electrically connected to the second power supply line VSS.
  • the signal of the second power line VSS may be a continuously provided low-level signal
  • the signal of the first power line VDD may be a continuously provided high-level signal.
  • FIG. 3 is an operating timing diagram of the pixel circuit shown in FIG. 2 .
  • the working process of the pixel circuit shown in FIG. 2 will be described below with reference to FIG. 3 .
  • the first to seventh transistors T1 to T7 of the pixel circuit are P-type transistors
  • the eighth transistor T8 is an N-type transistor.
  • the first reset control signal RESET1 provided by the third scanning signal line RST1 electrically connected to the pixel circuit and the second reset control signal RESET2 provided by the fourth scanning signal line RST2 may be the same.
  • the working process of the pixel circuit may include: a first phase t1, a second phase t2, and a third phase t3.
  • the first phase t1 is called the reset phase.
  • the first reset control signal RESET1 provided by the third scanning signal line RST1 is a low-level signal, turning on the first transistor T1 and the seventh transistor T7, and the second scanning signal SCAN2 provided by the second scanning signal line GL2 is a high-level signal. signal to turn on the eighth transistor T8.
  • the first initial signal provided by the first initial signal line INIT1 is provided to the fifth node N5 and the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst.
  • the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4 to initialize the fourth node N4.
  • the first scanning signal SCAN1 provided by the first scanning signal line GL1 is a high-level signal
  • the lighting control signal EM provided by the lighting control line EML is a high-level signal, so that the fourth transistor T4, the second transistor T2, and the fifth transistor T5 , and the sixth transistor T6 is turned off.
  • the light-emitting element EL does not emit light.
  • the second stage t2 is called the data writing stage or threshold compensation stage.
  • the first scan signal SCAN1 provided by the first scan signal line GL1 is a low-level signal
  • the second scan signal SCAN2 provided by the second scan signal line GL2 the first reset control signal RESET1 provided by the third scan signal line RST1 and the light emission control
  • the light-emitting control signals EM provided by the line EML are all high-level signals
  • the data line DL outputs the data signal DATA.
  • the third transistor T3 is turned on.
  • the first scan signal SCAN1 is a low-level signal, turning on the second transistor T2 and the fourth transistor T4.
  • the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, so that the data voltage Vdata output by the data line DL passes through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T8.
  • the transistor T2, the fifth node N5 and the turned-on eighth transistor T8 are provided to the first node N1, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor Cst.
  • the first reset control signal RESET1 provided by the third scanning signal line RST1 is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned off.
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.
  • the third stage t3 is called the luminous stage.
  • the light-emitting control signal EM provided by the light-emitting control line EML changes from a high level to a low-level signal.
  • the fifth transistor T5 and the sixth transistor T6 can be turned on.
  • the second scanning signal SCAN2 provided by the second scanning signal line GL2 is a low-level signal, causing the eighth transistor T8 to turn off.
  • the first scan signal SCAN1 provided by the first scan signal line GL1 and the first reset control signal RESET1 provided by the third scan signal line RST1 are high-level signals, causing the second transistor T2, the fourth transistor T4, the seventh transistor T7 and The first transistor T1 is turned off.
  • the first voltage signal output by the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [Vdd-Vdata] 2 ;
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data line DL
  • Vdd is the first voltage signal output by the first power line VDD.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the third transistor T3.
  • FIG. 4 is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • the first display area A1 may include: a plurality of display island areas A11 spaced apart from each other, a transparent screen between adjacent display island areas A11 The light area A12 and the connection area A13 connecting the adjacent display island area A11.
  • Each display island area A11 can be configured to display images
  • each light-transmitting area A12 can be configured to provide a light transmission space
  • each connection area A13 can be configured to provide signal wiring.
  • the shapes of the multiple display island areas A11 may be approximately the same, for example, they may all be circular.
  • Multiple connection areas A13 can connect multiple display island areas A11 to each other.
  • the connection area A13 may be a strip area extending along the first direction X or the second direction Y.
  • each display island area A13 may be connected to four connection areas A13.
  • Four connection areas A13 connected to one display island area A11 may extend in different directions.
  • two of the connection areas A13 may extend along the first direction X, and the other two connection areas A13 may extend along the second direction Y.
  • the first direction X and the second direction Y intersect.
  • first direction X and the second direction Y may be perpendicular to each other.
  • One display island area A11 can be connected to four other display island areas surrounding the display island area A11 through four connection lines A13.
  • this embodiment is not limited to this.
  • the display island may be an ellipse; or the display island may be other shapes without right-angled sides. In other examples, the shapes of the multiple display islands may be different.
  • the shapes of the multiple light-transmitting areas A12 may be approximately the same, for example, they may all be octagonal.
  • One light-transmitting area A12 may be surrounded by four connection areas A13 and four display island areas A11.
  • the edges of the light-transmitting area A12 may include: a first edge A12-1 in contact with the connection area A13, and a second edge A12-2 in contact with the display island area A11.
  • the first edge A12-1 and the second edge A12-2 are connected at intervals.
  • the first edge A12-1 is the edge of the connection area A13 close to the light-transmitting area A12.
  • the first edge A12-1 may be a flat edge, for example, a straight edge.
  • the second edge A12-2 is the edge of the display island area A11 close to the light-transmitting area A12.
  • the second edge A12-2 may be arc-shaped.
  • the second edge A12-2 may be an arc-shaped flat edge, or may be an uneven edge, such as some small deformation caused by tolerance.
  • the connection between the first edge A12-1 and the second edge 12-2 of the light-transmitting area A12 does not form a right-angled edge, which can reduce the light diffraction effect.
  • FIG. 5 is another partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • the second edge A12 - 2 of the light-transmitting area A12 may be arc-shaped in a plane parallel to the display substrate.
  • the first edge A12-1 of the light-transmitting area A12 may be an uneven edge.
  • the connection between the first edge A12-1 and the second edge 12-2 of the light-transmitting area A12 does not form a right-angled edge, which can reduce the light diffraction effect.
  • FIG. 6A to 6D are partial enlarged schematic views of the first edge of at least one embodiment of the present disclosure.
  • the first edge A12 - 1 of the light-transmitting area may be wavy.
  • the first edge A12-1 may be formed by connecting multiple continuous arc segments.
  • the first edge A12-1 may include protrusions and recesses connected at intervals, and the protrusions and recesses may be semicircular or semielliptical.
  • the first edge A12-1 of the light-transmitting area may be in a zigzag shape.
  • the first edge A12-1 may be formed by connecting multiple consecutive straight line segments.
  • the first edge A12-1 may include protrusions and recesses connected at intervals, and the protrusions and recesses may be triangular.
  • the first edge A12-1 of the light-transmitting area may include a plurality of protrusions, and the protrusions may be semicircular or semielliptical.
  • the first edge A12-1 may be formed by connecting arc ends and straight segments at intervals.
  • the first edge A12-1 of the light-transmitting area may include a plurality of protrusions, and the protrusions may be triangular.
  • the first edge A12-1 may be formed by connecting multiple straight line segments with different inclination directions.
  • the protrusions or recesses may be quadrilateral or pentagonal.
  • the second edge of the light-transmitting area may be an uneven edge, such as having a protruding portion or a concave portion. On the basis that the second edge ensures an arc shape, the non-flat shape of the second edge may be similar to the non-flat shape of the first edge, so no details will be given here.
  • the shape of the second edge of the light-transmissive area may be determined by the shape of the peripheral edge of the signal trace in the display island area.
  • the shape of the first edge of the light-transmitting area may be determined by the peripheral edge shape of the signal traces (eg, light-shielding traces) of the connection area.
  • this embodiment is not limited to this.
  • the shapes of the first edge and the second edge of the light-transmitting area may be determined by the shape of the peripheral edge of the black matrix.
  • the black matrix can cover the non-luminous area and connection area of the display island.
  • the first display area A1 may include: a plurality of first area light-emitting elements and a plurality of first area pixel circuits. At least one first area pixel circuit is electrically connected to at least one first area light emitting element. For example, a plurality of first area pixel circuits and a plurality of first area light emitting elements may be electrically connected in a one-to-one correspondence. The front projection of the at least one first area pixel circuit on the substrate and the front projection of the at least one electrically connected first area light-emitting element on the substrate may at least partially overlap.
  • the second display area A2 may include: a plurality of second area light-emitting elements and a plurality of second area pixel circuits. At least one second area pixel circuit is electrically connected to at least one second area light emitting element. For example, a plurality of second area light-emitting elements and a plurality of second area pixel circuits may be electrically connected in a one-to-one correspondence. The front projection of the at least one second area pixel circuit on the substrate and the front projection of the electrically connected at least one second area light-emitting element on the substrate may at least partially overlap.
  • FIG. 7A is a schematic diagram of the arrangement of the first area light-emitting elements and the first area pixel circuit in the first display area according to at least one embodiment of the present disclosure.
  • a display island A11 may include a first pixel unit P1.
  • the first pixel unit P1 may include: three first sub-pixels that emit light of different colors, and each first sub-pixel may include: a first area pixel circuit 13 and a first area light-emitting element 11.
  • the three first area light-emitting elements 11 of the display island area A11 may include: a first light-emitting element 11a that emits light of the first color, a second light-emitting element 11b that emits light of the second color, and a third light-emitting element 11b that emits light of the third color.
  • the three first area pixel circuits 13 of the display island area A11 may include: a first pixel circuit 13a electrically connected to the first light-emitting element 11a, a second pixel circuit 13b electrically connected to the second light-emitting element 11b, and a third pixel circuit 13b electrically connected to the second light-emitting element 11b.
  • the light-emitting element 11c is electrically connected to the third pixel circuit 13c.
  • the first light-emitting element 11a may be configured to emit light under the driving of the first pixel circuit 13a
  • the second light-emitting element 11b may be configured to emit light under the driving of the second pixel circuit 13b
  • the third light-emitting element 11c may be configured to emit light under the driving of the second pixel circuit 13b.
  • the third pixel circuit 13c emits light when driven.
  • the front projection of the first light-emitting element 11a on the substrate may overlap with the front projection of the first pixel circuit 13a on the substrate.
  • the front projection of the second light-emitting element 11b on the substrate and the front projection of the second pixel circuit 13b on the substrate may overlap.
  • the projections may overlap, and the orthographic projection of the third light-emitting element 11c on the substrate may overlap with the orthographic projection of the third pixel circuit 13c on the substrate.
  • an independent first pixel unit is provided in each display island area A11 instead of multiple first pixel units being aggregated, which can make the pixel units more evenly distributed, thereby effectively improving the display effect.
  • the first color light may be green light
  • the second color light may be red light
  • the third color light may be blue light.
  • this embodiment is not limited to this.
  • the three first area light-emitting elements 11 in the display island area A11 may be arranged in a zigzag shape.
  • the second light-emitting element 11b and the first light-emitting element 11a in the display island area A11 can be arranged sequentially along the second direction Y
  • the third light-emitting element 11c can be located between the first light-emitting element 11a and the second light-emitting element 11a in the first direction X. the same side of the light emitting element 11c.
  • the three first area pixel circuits 13 in the display island area A11 may be arranged side by side along the first direction X.
  • the first pixel circuit 13a, the second pixel circuit 13b and the third pixel circuit 13c in the display island area A11 may be arranged sequentially along the first direction X.
  • the first light-emitting element 11a of the display island area A11 may have a first light-emitting area
  • the second light-emitting element 11b may have a second light-emitting area
  • the third light-emitting element 11c may have a third light-emitting area. area.
  • the first light-emitting area, the second light-emitting area and the third light-emitting area may be combined to form a circle as a whole.
  • the first light-emitting area of the first light-emitting element 11a may be surrounded by two straight edges and one arc edge, and the two straight edges may be perpendicular to each other.
  • the second light-emitting area of the second light-emitting element 11b may be surrounded by two straight edges and one arc edge, and the two straight edges may be perpendicular to each other.
  • the third light-emitting area of the third light-emitting element 11c may be surrounded by a straight edge and an arc edge.
  • the first light emitting area may be smaller than the second light emitting area.
  • the first light-emitting area and the second light-emitting area may be shaped like a quarter circle, and the third light-emitting area may be shaped like a semicircle.
  • the second display area A2 may include a plurality of regularly arranged second pixel units P2.
  • the second pixel unit P2 may include: three second sub-pixels emitting light of different colors.
  • Each second sub-pixel may include: a second area pixel circuit 14 and a second area light-emitting element 12.
  • the three second area light-emitting elements 12 of one second pixel unit P2 of the second display area A2 may include: a fourth light-emitting element 12a that emits the first color light, and a fifth light-emitting element that emits the second color light. element 12b, and a sixth light-emitting element 12c that emits third color light.
  • the three second area pixel circuits 14 of the second display area A2 may include: a fourth pixel circuit 14a electrically connected to the fourth light-emitting element 12a, a fifth pixel circuit 14b electrically connected to the fifth light-emitting element 12b, and a fourth pixel circuit 14b electrically connected to the fifth light-emitting element 12b.
  • the six light-emitting elements 12c are electrically connected to the sixth pixel circuit 14c.
  • the fourth light-emitting element 12a may be configured to emit light under the driving of the fourth pixel circuit 14a
  • the fifth light-emitting element 12b may be configured to emit light under the driving of the fifth pixel circuit 14b
  • the sixth light-emitting element 12c may be configured to emit light under the driving of the fourth pixel circuit 14a.
  • the sixth pixel circuit 14c emits light when driven.
  • the front projection of the fourth light-emitting element 12a on the substrate and the front projection of the fourth pixel circuit 14a on the substrate may overlap.
  • the front projection of the fifth light-emitting element 12b on the substrate and the front projection of the fifth pixel circuit 14b on the substrate may overlap.
  • the projections may overlap, and the orthographic projection of the sixth light-emitting element 12c on the substrate may overlap with the orthographic projection of the sixth pixel circuit 14c on the substrate.
  • the three second area light-emitting elements 12 of the second pixel unit P2 may be arranged in a zigzag shape.
  • the fifth light-emitting element 12b and the fourth light-emitting element 12a may be arranged sequentially along the second direction Y, and the sixth light-emitting element 12c may be located on the same side of the fourth light-emitting element 12a and the fifth light-emitting element 12b in the first direction X.
  • the three second area pixel circuits 14 of the second pixel unit P2 may be arranged side by side along the first direction X.
  • the fourth pixel circuit 14a, the fifth pixel circuit 14b and the sixth pixel circuit 14c may be arranged sequentially along the first direction X.
  • the fourth light-emitting element 12a of the second pixel unit P2 may have a fourth light-emitting area
  • the fifth light-emitting element 12b may have a fifth light-emitting area
  • the sixth light-emitting element 12c may have a sixth light-emitting area.
  • Glowing area The fourth light-emitting area, the fifth light-emitting area and the sixth light-emitting area may be combined to form a rectangle as a whole.
  • the fourth, fifth, and sixth light-emitting areas may all be rectangular.
  • the fourth light-emitting area may be smaller than the fifth light-emitting area.
  • FIG. 7C is a partial schematic diagram of area S1 in FIG. 1 .
  • FIG. 7C illustrates the arrangement of light-emitting elements and pixel circuits at the junction of the first display area A1 and the second display area A2.
  • the density of the first pixel unit P1 of the first display area A1 may be smaller than the density of the second pixel unit P2 of the second display area A2.
  • the density of the first area light-emitting elements 11 of the first display area A1 may be smaller than the density of the second area light-emitting elements 12 of the second display area A2. In this way, the light transmittance of the first display area A1 can be improved.
  • two rows of second pixel units P2 in the second display area A2 may correspond to one row of first pixel units P1 in the first display area A1, and two columns in the second display area A2.
  • the second pixel unit P2 may correspond to a column of first pixel units P1 in the first display area A1.
  • a row of A may represent a plurality of A's arranged along the first direction X
  • a column of A may represent a plurality of A's arranged along the second direction Y.
  • the first area pixel circuit 13 in the first display area A1 and the second area pixel circuit 14 in the second display area A2 may both be the 8T1C structure shown in FIG. 2 .
  • the second area pixel circuit in the 2nth row and jth column and the second area pixel circuit in the 2n-1th row and jth column may be electrically connected to different data lines.
  • the first scanning signal, the second scanning signal, the first reset control signal, and the second reset control signal received by the second regional pixel circuit in the 2nth row and jth column and the second regional pixel circuit in the 2n-1th row and jth column.
  • the lighting control signals can be the same, and receive the same or different data signals through different data lines.
  • n and j are both positive integers.
  • the 2nth row and the 2n-1th row of second area pixel circuits in the second display area A2 correspond to a row of first area pixel circuits in the first display area A1
  • the 2nth row and the 2nth row in the second display area A2 correspond to The 2n-1th row of second area pixel circuits and the corresponding row of first area pixel circuits in the first display area A1 can receive the same first scanning signal, second scanning signal, first reset control signal, and second reset control signal. and lighting control signals.
  • the k-1th column and the k-th column of second pixel units in the second display area A2 correspond to one column of first pixel units in the first display area A1.
  • the k-1th and k-th second pixel units include a total of six columns of second region pixel circuits. Since the second region pixel circuits of odd-numbered rows and even-numbered rows are connected to different data lines, the six columns of second region pixel circuits can be connected to Twelve data lines are electrically connected, and six of the twelfth data lines (for example, the fourth to ninth data lines arranged along the first direction) can pass through a corresponding column of first pixels.
  • the arrangement of the first pixel unit in the column can be bypassed.
  • k is a positive integer.
  • FIG. 8 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure.
  • the display substrate may include: a substrate 101, a driving circuit layer 102, a light-emitting structure layer 103 and a packaging structure layer 104 sequentially disposed on the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of second area pixel circuits located in the second display area A2 and a plurality of first area pixel circuits located in the first display area A1.
  • the light-emitting structure layer 103 may include a plurality of first area light-emitting elements located in the first display area A1 and a plurality of second area light-emitting elements located in the second display area A2.
  • the light-emitting structure layer 103 may include at least an anode layer 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode layer 304.
  • the anode layer 301 may be electrically connected to the pixel circuit of the driving circuit layer, and the organic light-emitting layer 303 may be connected to the anode layer 301.
  • the cathode layer 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of corresponding colors driven by the anode layer 301 and the cathode layer 304.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials, and the second packaging layer 402 may be made of Organic material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the driving circuit layer 102 may include: a first conductive layer, a first semiconductor layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate 101, fifth conductive layer and sixth conductive layer.
  • the driving circuit layer 102 may further include: a first insulation layer, a second insulation layer, a third insulation layer, a fourth insulation layer, a fifth insulation layer, a sixth insulation layer, a seventh insulation layer, and an eighth insulation layer. Insulation.
  • the first insulating layer may be disposed between the first conductive layer and the first semiconductor layer
  • the second insulating layer may be disposed between the first semiconductor layer and the second conductive layer
  • the third insulating layer may be disposed between the second conductive layer and the second conductive layer.
  • layer and the second semiconductor layer, the fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, the fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer
  • the sixth insulating layer may be disposed between the second semiconductor layer and the third conductive layer.
  • the layer may be disposed between the fourth conductive layer and the fifth conductive layer, the seventh insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and the eighth insulating layer may be disposed away from the sixth conductive layer away from the substrate. one side.
  • the first to fifth insulating layers may be inorganic insulating layers, and the sixth to eighth insulating layers may be organic insulating layers. However, this embodiment is not limited to this.
  • a first pixel unit of a display island area in the first display area A1 and a second pixel unit of the second display area A2 are taken as an example, and the second pixel unit of the second display area A2
  • the second pixel unit in the current row and the next row may correspond to the row in which the first pixel unit is located.
  • the "patterning process” mentioned in the embodiments of this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials including processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate.
  • the "thin film” can also be called a "layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • the substrate may be a rigid substrate or a flexible substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, and polyether ether ketone.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may Materials such as polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft films are used.
  • the first inorganic material layer and the second inorganic material layer can be made of silicon nitride. (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • a first conductive film is deposited on the substrate, and the first conductive film is patterned through a patterning process to form a first conductive layer.
  • the first conductive layer may also be called a light shielding (LS) layer.
  • FIG. 9A is a partially enlarged schematic view of the display substrate after the first conductive layer is formed in the first display area according to at least one embodiment of the present disclosure.
  • the first conductive layer of a single display island area of the first display area may include at least: a first shielding line 211 and a second shielding line 212 .
  • the first shielding trace 211 may extend along the first direction X, and may extend along the first direction X to the connection areas of the display island area on both sides of the first direction X.
  • the second shielding trace 212 may extend along the second direction Y, and may extend along the second direction Y to the connection areas of the display island area on both sides of the second direction Y.
  • the first shielding trace 211 and the second shielding trace 212 may be an integral structure.
  • the first shielding wiring 211 of the adjacent display island area of the first display area may be an integral structure, and the second shielding wiring 212 of the adjacent display island area may be an integral structure.
  • the first shielding wire 211 and the second shielding wire 212 may be connected to form a mesh structure.
  • the first shielding trace 211 may include: three first shielding parts 2111 and three second shielding parts 2112.
  • the first shielding part 2111 may extend outward from the main body part of the first shielding trace 211 along the second direction Y
  • the second shielding part 2112 may extend outward from the first shielding part 2111 along the second direction Y.
  • the orthographic projection of the first shielding part 2111 on the substrate may be a rectangle, for example, it may be a rounded rectangle.
  • the orthographic projection of the second shielding part 2112 on the substrate may be L-shaped.
  • the second first shielding portion 2111 and the second second shielding portion 2112 arranged along the first direction X may be electrically connected to the second shielding line 212 .
  • FIG. 9B is a partially enlarged schematic view of the display substrate after forming the first conductive layer in the second display area according to at least one embodiment of the present disclosure.
  • the first conductive layer of the second display area may include: third shielding wires 213 and fourth shielding wires 214 .
  • the third shielding trace 213 may extend along the first direction X, and the plurality of third shielding traces 213 may be sequentially arranged along the second direction Y.
  • the fourth shielding trace 214 extends along the second direction Y, and the plurality of fourth shielding traces 214 may be arranged sequentially along the first direction X.
  • the third shielding trace 213 may include: a third shielding portion 2131 , and the third shielding portion 2131 may extend outward from the main body portion of the third shielding trace 213 along the second direction Y.
  • the orthographic projection of the third shielding part 2131 on the substrate may be a rectangle, such as a rounded rectangle.
  • the third shielding part 2131 is electrically connected to the fourth shielding line 214 .
  • the third shielding line 213 and the fourth shielding line 214 may be an integral structure. In the second display area, the third shielding wire 213 and the fourth shielding wire 214 may be connected to form a mesh structure.
  • the third shielding wire 213 of the second display area may be electrically connected to the first shielding wire 211 of the first display area, and may be an integrated structure, for example.
  • the fourth shielding wire 214 of the second display area may be electrically connected to the second shielding wire 212 of the first display area, and may be an integrated structure, for example.
  • the first shielding wire 211 , the second shielding wire 212 , the third shielding wire 213 and the fourth shielding wire 214 may be electrically connected with the first power line.
  • the first shielding wire 211 and the third shielding wire 213 may extend to the peripheral area along the first direction X and be electrically connected to the first power line in the peripheral area.
  • the second shielding wire 212 and the fourth shielding wire 214 may extend to the peripheral area along the second direction X and be electrically connected to the first power line in the peripheral area.
  • this embodiment is not limited to this.
  • the first conductive layer of at least one connection area of the first display area may include: a first shielding line 211 or a second shielding line 212 .
  • a first insulating film and a first semiconductor film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the first semiconductor film is patterned through a patterning process to form a first insulating layer disposed on the substrate and first semiconductor layer.
  • the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene or polythiophene.
  • FIG. 10A is a partially enlarged schematic diagram of a display substrate after forming a first semiconductor layer in the first display region according to at least one embodiment of the present disclosure.
  • FIG. 11A is a schematic diagram of the first semiconductor layer in FIG. 10A.
  • the first semiconductor layer of the single display island area of the first display area may include: three first area pixel circuits (for example, including three first area pixel circuits arranged sequentially along the first direction X).
  • the first active layer 310 of the first transistor 31 to the seventh active layer 370 of the seventh transistor 37 of a first region pixel circuit may be an integral structure connected to each other.
  • the first active layer 310 of the first transistor 31 to the seventh active layer 370 of the seventh transistor 37 of the first pixel circuit is used as an example for explanation.
  • the first active layer 310, the second active layer 320 and the fourth active layer 340 of the first pixel circuit may be located on one side of the third active layer 330 of the first pixel circuit in the second direction Y, and the fifth active layer 310, the second active layer 320 and the fourth active layer 340 of the first pixel circuit may be located on The active layer 350, the sixth active layer 360, and the seventh active layer 370 may be located on the other side of the third active layer 330 of the first pixel circuit in the second direction Y.
  • the first active layer 310 , the second active layer 320 , the fourth active layer 340 , the fifth active layer 350 , and the sixth active layer 360 of the first pixel circuit and the seventh active layer 370 may both be I-shaped.
  • the shape of the third active layer 330 may be n-shaped. However, this embodiment is not limited to this.
  • the active layer 310 of the first transistor 31 to the active layer 370 of the seventh transistor 37 of the first pixel circuit may each include: a first region, a second region, and a first region located at the first region. The channel area between the second area and the second area.
  • Zone 1 370-1 can be set individually.
  • the second area 310-2 of the first active layer 310 may simultaneously serve as the first area 320-1 of the second active layer 320.
  • the second region 320-2 of the second active layer 320 may simultaneously serve as the second region 330-2 of the third active layer 330 and the first region 360-1 of the sixth active layer 360.
  • the first region 330-1 of the third active layer 330 may simultaneously serve as the second region 340-2 of the fourth active layer 340 and the second region 350-2 of the fifth active layer 350.
  • the second region 360-2 of the sixth active layer 360 may simultaneously serve as the second region 370-2 of the seventh active layer 370.
  • an orthographic projection of a first shielding portion 2111 of the first shielding line 211 on the substrate may cover the channel of the third active layer 330 of the third transistor of the first pixel circuit. Orthographic projection of the area on the substrate.
  • the front projection of the second shielding portion 2112 of the first shielding line 211 on the substrate may cover the front projection of the channel region of the second active layer 320 of the second transistor of the first pixel circuit on the substrate.
  • the orthographic projection of the first shielding line 211 on the substrate can also cover the channel region of the third active layer of the third transistor of the second pixel circuit and the third pixel circuit and the second active layer of the second transistor. The orthographic projection of the channel region of the layer on the substrate.
  • FIG. 10B is a partially enlarged schematic diagram of the display substrate after forming the first semiconductor layer in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 11B is a schematic diagram of the first semiconductor layer in FIG. 10B.
  • the second conductive layer of the second display area may include: a plurality of second area pixel circuits (for example, including: fourth pixel circuits arranged sequentially along the first direction X , the fifth pixel circuit and the sixth pixel circuit) the first active layer 410 of the first transistor 41 to the seventh active layer 470 of the seventh transistor 47 .
  • the first active layer 410 of the first transistor 41 to the seventh active layer 470 of the seventh transistor 47 of a second region pixel circuit may be an integral structure connected to each other.
  • the first to sixth transistors 41 to 46 of the second regional pixel circuit in one row and the seventh transistor 47 of the second regional pixel circuit in the previous row are used as examples for illustration.
  • the first active layer 410 of the first transistor 41 to the seventh active layer 470 of the seventh transistor 47 of the fourth pixel circuit is used as an example for explanation.
  • the first active layer 410, the second active layer 420 and the fourth active layer 440 of the fourth pixel circuit may be located on one side of the third active layer 430 of the fourth pixel circuit in the second direction Y.
  • the active layer 450, the sixth active layer 460, and the seventh active layer 470 may be located on the other side of the third active layer 430 of the fourth pixel circuit in the second direction Y.
  • the shapes of the first active layer 410 , the fourth active layer 440 , the fifth active layer 450 and the seventh active layer 470 of the fourth pixel circuit may all be I-shaped. type.
  • the shape of the second active layer 420 may be L-shaped.
  • the shape of the sixth active layer 460 may be a zigzag type.
  • the shape of the third active layer 430 may be n-shaped. However, this embodiment is not limited to this.
  • the active layer 410 of the first transistor 41 to the active layer 470 of the seventh transistor 47 of the fourth pixel circuit may each include: a first region, a second region, and a first region located at the first region. The channel area between the second area and the second area.
  • Zone 1 470-1 can be set individually.
  • the second area 410-2 of the first active layer 410 may simultaneously serve as the first area 420-1 of the second active layer 420.
  • the second region 420-2 of the second active layer 420 may simultaneously serve as the second region 430-2 of the third active layer 430 and the first region 460-1 of the sixth active layer 460.
  • the first region 430-1 of the third active layer 430 may simultaneously serve as the second region 440-2 of the fourth active layer 440 and the second region 450-2 of the fifth active layer 450.
  • the second region 460-2 of the sixth active layer 460 may simultaneously serve as the second region 470-2 of the seventh active layer 470.
  • an orthographic projection of a third shielding portion 2131 of the third shielding line 213 on the substrate may cover the channel of the third active layer 430 of the third transistor of the fourth pixel circuit. Orthographic projection of the area on the substrate.
  • the front projection of the third shielding line 213 on the substrate can also cover the front projection of the channel region of the third active layer of the third transistor of the fifth pixel circuit and the sixth pixel circuit on the substrate.
  • connection area of the first display area may include: a substrate and a first conductive layer and a first insulating layer sequentially disposed on the substrate.
  • the light-transmitting area of the first display area may include: a substrate, and a first insulating layer provided on the substrate.
  • a second insulating film and a second conductive film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the second conductive film is patterned through a patterning process to form a second insulating layer covering the first semiconductor layer. and a second conductive layer disposed on the second insulating layer.
  • the second conductive layer may also be called a first gate metal layer.
  • Figure 12A is a partially enlarged schematic view of the display substrate after forming the second conductive layer in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 13A is a schematic diagram of the second conductive layer in FIG. 12A. In some examples, as shown in FIGS.
  • the second conductive layer of the single display island area of the first display area may include: three first area pixel circuits (ie, first pixel circuit to third pixel circuit)
  • the gates of the first to seventh transistors 31 to 37 , the first capacitor plate 391 of the storage capacitor, the light emitting control line EML(n), the fifth shielding line 221 and a plurality of data connection lines for example, including: the first data connection line 521, second data connection line 522, fifth data connection line 525, sixth data connection line 526, fifteenth data connection line 535 and sixteenth data connection line 536).
  • the orthographic projections of the gate electrode 311 of the first transistor 31 and the gate electrode 371 of the seventh transistor 37 of the first pixel circuit on the substrate may be substantially the same. , roughly in the shape of a key, for example.
  • the orthographic projection of the gate electrode 321 of the second transistor 32 on the substrate may be approximately U-shaped.
  • the gate electrode 341 of the fourth transistor 34 of one first regional pixel circuit and the gate electrode 321 of the second transistor 32 of the adjacent first regional pixel circuit may have an integrated structure.
  • the gate electrode 341 of the fourth transistor 34 of the first pixel circuit in the display island area and the gate electrode of the second transistor of the second pixel circuit can be an integral structure, and the gate electrode 341 of the fourth transistor 34 of the second pixel circuit can be integrated.
  • the gate electrode of the second pixel circuit of the pixel circuit and the gate electrode of the fourth transistor of the third pixel circuit may have an integrated structure. In this way, the layout space can be reasonably saved.
  • the gate 331 of the third transistor 33 of the first pixel circuit and the first capacitor plate 391 of the storage capacitor may have an integrated structure, for example, may be a rounded rectangle.
  • the gate electrode 351 of the fifth transistor 35 and the gate electrode 361 of the sixth transistor 36 of the first to third pixel circuits, and the light emission control line EML(n) may have an integrated structure.
  • the light-emitting control line EML(n) may bypass the first capacitor plate 391 of the storage capacitor in the second direction Y in the display island area, and extend along the first direction X to the connection areas on both sides of the display island area.
  • the fifth shielding trace 221 may extend along the first direction X within the display island area.
  • the fifth shielding line 221 may be located between the gate electrode 311 of the first transistor 31 and the gate electrode 321 of the second transistor 32 of the first pixel circuit in the second direction Y.
  • the first data connection line 521 , the fifth data connection line 525 and the fifteenth data connection line 535 may be located away from the gate electrode 311 of the first transistor 31 in the second direction Y. Five shields one side of trace 221.
  • the first data connection line 521, the fifth data connection line 525 and the fifteenth data connection line 535 may be arranged sequentially along the first direction X.
  • the first data connection line 521, the fifth data connection line 525 and the fifteenth data connection line 535 may extend to the connection region in the second direction Y to a side away from the gate electrode 311 of the first transistor 31.
  • the second data connection line 522 , the sixth data connection line 526 and the sixteenth data connection line 536 may be located away from the gate electrode 371 of the seventh transistor 37 in the second direction Y.
  • the second data connection line 522, the sixth data connection line 526, and the sixteenth data connection line 536 may be arranged sequentially along the first direction X.
  • the second data connection line 522 , the sixth data connection line 526 and the sixteenth data connection line 536 may extend in the second direction Y to a side away from the gate electrode 371 of the seventh transistor 37 to the connection area.
  • the orthographic projection of the data connection lines 536 on the substrate may be approximately L-shaped.
  • the first data connection line 521 and the second data connection line 522 may be substantially symmetrical about the center line of the display island area in the second direction Y, and the fifth data connection line 525 and the sixth data connection line 526 may be in the second direction about the display island area.
  • the center line in the direction Y is approximately symmetrical, and the fifteenth data connection line 535 and the sixteenth data connection line 536 may be approximately symmetrical with respect to the center line of the display island area in the second direction Y.
  • FIG. 12B is a partially enlarged schematic view of the display substrate after the second conductive layer is formed in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 13B is a schematic diagram of the second conductive layer in FIG. 12B.
  • the second conductive layer of the second display area may include: first transistors 41 of a plurality of second area pixel circuits (eg, fourth to sixth pixel circuits). to the gate of the seventh transistor 47 , the first capacitor plate 491 of the storage capacitor, the light emission control line EML(n), and the sixth shielding line 222 .
  • the light emission control line EML(n) may extend along the first direction X.
  • the overlapping area of the light-emitting control line EML(n) and the active layer 450 of the fifth transistor 45 can be used as the gate of the fifth transistor 45, and the intersection of the light-emitting control line EML(n) and the active layer 460 of the sixth transistor 46 can be used as a gate electrode of the fifth transistor 45.
  • the stacked region may serve as the gate of sixth transistor 46 .
  • the gate electrode 421 of the second transistor 42 of one second regional pixel circuit and the gate electrode of the fourth transistor of the adjacent second regional pixel circuit may have an integrated structure.
  • the gate of the second transistor of the fourth pixel circuit and the gate of the fourth transistor of the fifth pixel circuit may have an integrated structure
  • the gate of the second transistor of the fifth pixel circuit and the fourth transistor of the sixth pixel circuit may have an integrated structure.
  • the gate can be an integrated structure.
  • the gate electrode 411 of the first transistor 41 of the second regional pixel circuit in the n-th row and the gate electrode of the seventh transistor 47 of the second regional pixel circuit in the previous row may have an integrated structure.
  • the sixth shielding trace 222 may extend along the first direction X.
  • the sixth shielding line 222 may be located between the gate electrode 421 of the second transistor 42 and the gate electrode 431 of the third transistor 43.
  • the light emission control line EML(n) may extend from the first display area to the second display area via the connection area, or may directly extend from the first display area to the second display area.
  • the second conductive layer of at least one connection area of the first display area may include: a light emitting control line extending along the first direction.
  • the light-transmitting area of the first display area may include: a substrate, and a first insulating layer and a second insulating layer sequentially disposed on the substrate.
  • a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the second semiconductor film is patterned through a patterning process to form a third insulating layer covering the second conductive layer. and a second semiconductor layer disposed on the third insulating layer.
  • the material of the second semiconductor layer may be amorphous indium gallium zinc oxide material (a-IGZO), indium gallium zinc oxide material (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) and other materials, that is, this disclosure is applicable to transistors based on oxide (Oxide) technology.
  • FIG. 14A is a partially enlarged schematic view of the display substrate after the second semiconductor layer is formed in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 15A is a schematic diagram of the second semiconductor layer in FIG. 14A.
  • the second semiconductor layer of the single display island area of the first display area may include: three first area pixel circuits (ie, first pixel circuit to third pixel circuit)
  • the eighth active layer 380 of the eighth transistor 38 .
  • the eighth active layer 380 of the first pixel circuit may include: a first area 380-1, a second area 380-2, and the first area 380-1 and the second area 380-2. channel area between.
  • the shape of the eighth active layer 380 may be I-shaped.
  • the front projection of the fifth shielding line 221 on the substrate may overlap with the front projection of the eighth active layer 380 of the eighth transistor 38 of the first to third pixel circuits on the substrate.
  • FIG. 14B is a partially enlarged schematic view of the display substrate after forming the second semiconductor layer in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 15B is a schematic diagram of the second semiconductor layer in FIG. 14B.
  • the second semiconductor layer of the second display region may include: eighth transistors 48 of a plurality of second region pixel circuits (eg, fourth to sixth pixel circuits). the eighth active layer 480.
  • the eighth active layer 480 may include: a first region 480-1, a second region 480-2, and a channel between the first region 480-1 and the second region 480-2. district.
  • the shape of the eighth active layer 480 may be I-shaped.
  • the orthographic projection of the sixth shielding line 222 on the substrate may overlap with the orthographic projection of the eighth active layer 480 of the eighth transistor 48 of the plurality of second area pixel circuits on the substrate.
  • the connection area of the first display area may include: a substrate, and a first conductive layer, a first insulating layer, a second insulating layer, and a first insulating layer sequentially disposed on the substrate.
  • the light-transmissive area of the first display area may include: a substrate, and a first insulation layer, a second insulation layer, and a third insulation layer sequentially provided on the substrate.
  • a third conductive layer In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the third conductive film is patterned through a patterning process to form a fourth insulating layer covering the second semiconductor layer. and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be called a second gate metal layer.
  • FIG. 16A is a partially enlarged schematic view of the display substrate after forming a third conductive layer in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 17A is a schematic diagram of the third conductive layer in FIG. 16A.
  • the third conductive layer of the single display island area of the first display area may include: three first area pixel circuits (ie, the first pixel circuit to the third pixel circuit).
  • the gate electrode 381 of the eighth transistor 38 and the second capacitor plate 392 of the storage capacitor, the second scanning signal line GL2(n), the first initial transmission line 611, the eleventh initial transmission line 631, and a plurality of data connection lines (for example, it includes: the third data connection line 523, the fourth data connection line 524, the thirteenth data connection line 533, the fourteenth data connection line 534, the seventeenth data connection line 537 and the eighteenth data connection line 538).
  • the second scanning signal line GL2(n) may bypass the second capacitor plate 392 of the storage capacitor along the second direction Y in the display island area and along the first The direction X extends to the connection area on both sides of the display island area.
  • the gate 381 of the eighth transistor 38 of the first pixel circuit and the second scanning signal line GL2(n) may have an integrated structure.
  • the second capacitance plate 392 of the storage capacitor of the first pixel circuit may have a first hollow structure K1, and the orthographic projection of the first hollow structure K1 on the substrate may be located within the orthographic projection range of the first capacitance plate 391 on the substrate.
  • the first initial transmission line 611 and the eleventh initial transmission line 631 may be located in the display island area and extend along the first direction X.
  • the length of the eleventh initial transmission line 631 along the first direction X may be smaller than the length of the first initial transmission line 611 along the first direction X.
  • the third data connection line 523 , the thirteenth data connection line 533 and the seventeenth data connection line 537 may be located away from the first initial transmission line 611 in the second direction Y.
  • the third data connection line 523, the thirteenth data connection line 533, and the seventeenth data connection line 537 may be arranged sequentially along the first direction X.
  • the third data connection line 523 , the thirteenth data connection line 533 and the seventeenth data connection line 537 may extend to the connection area in the second direction Y to a side away from the first initial transmission line 611 .
  • the fourth data connection line 524 , the fourteenth data connection line 534 and the eighteenth data connection line 538 may be located away from the storage capacitor from the eleventh initial transmission line 631 in the second direction Y. one side of the second capacitor plate 392.
  • the fourth data connection line 524, the fourteenth data connection line 534, and the eighteenth data connection line 538 may be arranged sequentially along the first direction X.
  • the fourth data connection line 524 , the fourteenth data connection line 534 and the eighteenth data connection line 538 may extend to the connection area to a side away from the second initial transmission line 631 in the second direction Y.
  • the third data connection line 523 , the fourth data connection line 524 , the thirteenth data connection line 533 , the fourteenth data connection line 534 , the seventeenth data connection line 537 and the The orthographic projections of the eighteen data connection lines 538 on the substrate may all be roughly L-shaped.
  • the third data connection line 523 and the fourth data connection line 524 may be substantially symmetrical about the center line of the display island area in the second direction Y.
  • the thirteenth data connection line 533 and the fourteenth data connection line 534 may be substantially symmetrical about the center line of the display island area in the second direction Y.
  • the seventeenth data connection line 537 and the eighteenth data connection line 538 may be substantially symmetrical about the center line of the display island area in the second direction Y.
  • the orthographic projection of the third data connection line 523 on the substrate may be located between the orthographic projections of the first data connection line 521 and the fifth data connection line 525 on the substrate.
  • the orthographic projection of the fourth data connection line 524 on the substrate may be located between the orthographic projections of the second data connection line 522 and the sixth data connection line 526 on the substrate.
  • the orthographic projection of the thirteenth data connection line 533 on the substrate may be located between the orthographic projections of the fifth data connection line 525 and the fifteenth data connection line 535 on the substrate.
  • the orthographic projection of the fourteenth data connection line 534 on the substrate may be located between the orthographic projections of the sixth and sixteenth data connection lines 526 and 536 on the substrate.
  • the orthographic projection of the seventeenth data connection line 537 on the substrate may be located on the side of the orthographic projection of the fifteenth data connection line 535 on the substrate away from the thirteenth data connection line 533 in the first direction X.
  • the orthographic projection of the eighteenth data connection line 538 on the substrate may be located on a side of the orthographic projection of the sixteenth data connection line 536 on the substrate away from the fourteenth data connection line 534 in the first direction X.
  • FIG. 16B is a partially enlarged schematic view of the display substrate after forming a third conductive layer in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 17B is a schematic diagram of the third conductive layer in FIG. 16B.
  • the third conductive layer of the second display area may include: eighth transistors 48 of a plurality of second area pixel circuits (eg, fourth to sixth pixel circuits).
  • the second scanning signal line GL2(n) may extend along the first direction X in the second display area.
  • the gate 481 of the eighth transistor 48 of the fourth pixel circuit and the second scanning signal line GL2(n) may have an integrated structure.
  • the second capacitance plate 492 of the storage capacitor of the fourth pixel circuit may have a second hollow structure K2, and the orthographic projection of the second hollow structure K2 on the substrate may be located within the orthographic projection range of the first capacitance plate 491 on the substrate.
  • the fourth initial transmission line 614 and the fourteenth initial transmission line 634 may each extend along the first direction X.
  • the fourth initial transmission line 614 is located on a side of the fourteenth initial transmission line 634 away from the second scanning signal line GL2(n) in the second direction Y.
  • the second scanning signal line GL2(n) may extend from the first display area to the second display area via the connection area, or may directly extend from the first display area to the second display area.
  • the first initial transmission line 611 and the fourth initial transmission line 614 may be configured to transmit the first initial signal
  • the eleventh initial transmission line 631 and the fourteenth initial transmission line 634 may be configured to transmit the second initial signal.
  • the third conductive layer of at least one connection area of the first display area may include: a second scanning signal line.
  • the light-transmitting area of the first display area may include: a substrate, and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer sequentially provided on the substrate.
  • a fifth insulating film is deposited on the substrate on which the foregoing pattern is formed, and the fifth insulating film is patterned through a patterning process to form a fifth insulating layer.
  • FIG. 18A is a partially enlarged schematic view of the display substrate after the fifth insulating layer is formed in the first display area according to at least one embodiment of the present disclosure.
  • the fifth insulating layer of a single display island area of the first display area may be provided with multiple via holes, which may include, for example: first via holes V1 to eighteenth via holes V18, The twenty-first via hole V21 to the forty-sixth via hole V46, and the fifty-first via hole V51 to the sixty-ninth via hole V69.
  • the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole V1 to the eighteenth via hole V18 are removed, exposing the surface of the first semiconductor layer.
  • the fifth insulating layer, the fourth insulating layer and the third insulating layer in the twenty-first via hole V21 to the fortieth via hole V40 are removed, exposing the surface of the second conductive layer.
  • the fifth insulating layer and the fourth insulating layer in the forty-first via hole V41 and the forty-sixth via hole V46 are removed, exposing the surface of the second semiconductor layer.
  • the fifth insulating layer in the fifty-first via hole V51 to the sixty-ninth via hole V69 is removed, exposing the surface of the third conductive layer.
  • FIG. 18B is a partially enlarged schematic diagram of the display substrate after the fifth insulating layer is formed in the second display area according to at least one embodiment of the present disclosure.
  • the fifth insulating layer of the second display area may have a plurality of via holes.
  • the via holes opened in the fifth insulating layer in the area where the fourth pixel circuit is located may include, for example: the seventy-first via hole V71 to the seventy-sixth via hole V76, the eighth via hole The eleventh via hole V81 to the eighty-sixth via hole V86, the ninety-first via hole V91 to the ninety-fifth via hole V95.
  • the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventy-first via hole V71 to the seventy-sixth via hole V76 are removed, exposing the surface of the first semiconductor layer.
  • the fifth insulating layer, the fourth insulating layer and the third insulating layer in the eighty-first via hole V81 to the eighty-fourth via hole V84 are removed, exposing the surface of the second conductive layer.
  • the fifth insulating layer and the fourth insulating layer in the eighty-fifth via hole V85 and the eighty-sixth via hole V86 are removed, exposing the surface of the second semiconductor layer.
  • the fifth insulating layer in the ninety-first via hole V91 to the ninety-fifth via hole V95 is removed, exposing the surface of the third conductive layer.
  • the connection area of the first display area may include: a substrate, and a first conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer sequentially disposed on the substrate. a second conductive layer, a third insulating layer, a fourth insulating layer, a third conductive layer and a fifth insulating layer.
  • the light-transmitting area of the first display area may include: a substrate, and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer sequentially provided on the substrate.
  • a fourth conductive layer is deposited on the substrate on which the foregoing pattern is formed, and the fourth conductive film is patterned through a patterning process to form a fourth conductive layer disposed on the fifth insulating layer.
  • the fourth conductive layer may also be called a first source-drain metal layer.
  • Figure 19A is a partially enlarged schematic view of the display substrate after forming the fourth conductive layer in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 20A is a schematic diagram of the fourth conductive layer in FIG. 19A.
  • the fourth conductive layer of the single display island area of the first display area may at least include: a plurality of connection electrodes (for example, including: the first connection electrode 231 to the twentieth connection electrode). electrode 250), the second initial transmission line 612, the third initial transmission line 613, the first power transmission line 661, the first scanning signal lines GL1(n) and GL1(n+1), and the fourth scanning signal line RST2(n).
  • the first connection electrode 231 may be electrically connected to the first region of the first active layer of the first transistor of the first pixel circuit through the first via hole V1 , and can also be electrically connected to the first initial transmission line 611 through the fifty-fifth via V55.
  • the second connection electrode 232 can be electrically connected to the first area of the second active layer of the second transistor of the first pixel circuit through the second via hole V2, and can also be electrically connected to the first area of the first pixel circuit through the forty-first via hole V41.
  • the first region of the eighth active layer of the eighth transistor is electrically connected.
  • the third connection electrode 233 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the first pixel circuit through the third via hole V3.
  • the fourth connection electrode 234 can be electrically connected to the second area of the eighth active layer of the eighth transistor of the first pixel circuit through the 42nd via hole V42, and can also be electrically connected to the first pixel through the 29th via hole V29.
  • the gate of the third transistor of the circuit is electrically connected.
  • the fifth connection electrode 235 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the first pixel circuit through the fifth via hole V5.
  • the sixth connection electrode 236 can be electrically connected to the first region of the seventh active layer of the seventh transistor of the first pixel circuit through the sixth via V6, and can also be electrically connected to the eleventh initial transmission line through the sixty-fourth via V64. 631 electrical connection.
  • the seventh connection electrode 237 may be electrically connected to the first region of the first active layer of the first transistor of the second pixel circuit through the seventh via hole V7. , and can also be electrically connected to the first initial transmission line 611 through the fifty-sixth via V56.
  • the eighth connection electrode 238 may be electrically connected to the first region of the second active layer of the second transistor of the second pixel circuit through the eighth via hole V8, and may also be electrically connected to the second active layer of the second pixel circuit through the forty-third via hole V43. The first region of the eighth active layer of the eighth transistor is electrically connected.
  • the ninth connection electrode 239 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the second pixel circuit through the ninth via hole V9.
  • the tenth connection electrode 240 can be electrically connected to the second area of the eighth active layer of the eighth transistor of the second pixel circuit through the forty-fourth via hole V44, and can also be electrically connected to the second pixel circuit through the thirtieth via hole V30.
  • the gate of the third transistor is electrically connected.
  • the eleventh connection electrode 241 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the second pixel circuit through the eleventh via hole V11.
  • the twelfth connection electrode 242 may be electrically connected to the first region of the seventh active layer of the seventh transistor of the second pixel circuit through the twelfth via hole V12, and may also be electrically connected to the eleventh through the sixty-fifth via hole V65.
  • the initial transmission line 631 is electrically connected.
  • the thirteenth connection electrode 243 may be connected to the first region of the first active layer of the first transistor of the third pixel circuit through the thirteenth via hole V13.
  • the electrical connection can also be electrically connected to the first initial transmission line 611 through the fifty-seventh via V57.
  • the fourteenth connection electrode 244 can be electrically connected to the first region of the second active layer of the second transistor of the third pixel circuit through the fourteenth via hole V14, and can also be electrically connected to the third pixel through the forty-fifth via hole V45.
  • the first region of the eighth active layer of the eighth transistor of the circuit is electrically connected.
  • the fifteenth connection electrode 245 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the third pixel circuit through the fifteenth via hole V15.
  • the sixteenth connection electrode 246 can be electrically connected to the second area of the eighth active layer of the eighth transistor of the third pixel circuit through the forty-sixth via hole V46, and can also be electrically connected to the third through the thirty-first via hole V31.
  • the gate of the third transistor of the pixel circuit is electrically connected.
  • the seventeenth connection electrode 247 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the third pixel circuit through the seventeenth via hole V17.
  • the eighteenth connection electrode 248 can be electrically connected to the first region of the seventh active layer of the seventh transistor of the third pixel circuit through the eighteenth via hole V18, and can also be electrically connected to the eleventh through the sixty-sixth via hole V66.
  • the initial transmission line 631 is electrically connected.
  • the nineteenth connection electrode 249 may be electrically connected to the fifth shielding trace 221 located on the second conductive layer through the twenty-fourth via hole V24, and may also It is electrically connected to the second scanning signal line GL2(n) located on the third conductive layer through the fifty-ninth via hole V59.
  • the twentieth connection electrode 250 can be electrically connected to the fifth shielding line 221 located on the second conductive layer through the twenty-fifth via hole V24, and can also be electrically connected to the second scan line located on the third conductive layer through the sixtieth via hole V60.
  • the signal line GL2(n) is electrically connected.
  • the nineteenth connection electrode 249 and the twentieth connection electrode 250 may be substantially symmetrical about the center line of the display island area in the first direction X.
  • the overlapping area of the fifth shielding line 221 and the eighth active layer 380 of the eighth transistor 38 may serve as the bottom gate of the eighth transistor 38 .
  • the second initial transmission line 612 may extend along the first direction X from the connection area to the display island area, and extend along the second direction Y in the display island area.
  • the third initial transmission line 613 may extend from the connection area to the display island area along the first direction X, and extend along the second direction Y in the display island area.
  • the second initial transmission line 612 and the third initial transmission line 613 may be substantially symmetrical with respect to the center line of the display island area along the first direction X.
  • the second initial transmission line 612 can be electrically connected to one end of the first initial transmission line 611 through the fifty-fourth via V54, and the third initial transmission line 613 can be electrically connected to the other end of the first initial transmission line 611 through the fifty-eighth via V58. .
  • the seventh connection electrode 237 and the thirteenth connection electrode 243 three connections to the display island area can be realized.
  • the first area pixel circuit transmits a first initial signal.
  • the first scanning signal lines GL1(n) and GL1(n+1) may be located opposite to the fourth scanning signal line RST2(n). both sides.
  • the third scanning signal line RST1(n) may be located on a side of the first scanning signal line GL1(n) away from the fourth scanning signal line RST2(n).
  • the first scanning signal line GL1(n) may extend along the first direction X from the connection area to the display island area, and then extend from the display island area to another connection area.
  • the first scanning signal line GL1(n) can be electrically connected to the gate of the second transistor of the first pixel circuit through the thirty-eighth via V38 in the display island area, and can also be electrically connected to the second transistor through the thirty-ninth via V39.
  • the gate of the second transistor of the pixel circuit is electrically connected, and may also be electrically connected to the gate of the second transistor of the third pixel circuit through the fortieth via hole V40.
  • the first scanning signal line GL1(n) may be configured to provide the first scanning signal to the three first area pixel circuits of the display island area.
  • the fourth scanning signal line RST2(n) may extend from the connection area to the display island area along the first direction X, and bypass the display island area in the second direction Y. After the third transistor, it extends to another connection area along the first direction X.
  • the fourth scanning signal line RST2(n) can be electrically connected to the gate of the seventh transistor of the first pixel circuit through the thirty-second via V32, and can also be electrically connected to the gate of the seventh transistor of the second pixel circuit through the thirty-third via V33.
  • the gate electrode of the seventh transistor is electrically connected, and can also be electrically connected to the gate electrode of the seventh transistor of the third pixel circuit through the thirty-fourth via hole V34.
  • the fourth scanning signal line RST2(n) may be configured to provide a second reset control signal to the three first area pixel circuits of the display island area.
  • the first scanning signal line GL1(n+1) may extend from the connection area to the display island area along the first direction X, where the display island area is in the second direction Y. After bypassing the third transistor, it extends to another connection area along the first direction X.
  • the first scanning signal line GL1(n+1) may be located on a side of the fourth scanning signal line RST2(n) away from the first scanning signal line GL1(n) in the second direction Y.
  • the first scanning signal can be used to electrically connect the second area pixel circuits of the n+1th row on both sides of the first display area in the first direction X. Line connection ensures signal uniformity.
  • the first power transmission line 661 may be located within the display island area and may include a first body portion extending along the first direction X and a second body portion extending from the first body portion along the second direction Y.
  • the three first protrusions protrude from the same side.
  • the first first protrusion of the first power transmission line 661 may be electrically connected to the first region of the fifth active layer of the fifth transistor of the first pixel circuit through the fourth via V4, and the second first protrusion
  • the third first protruding portion can be electrically connected to the first region of the fifth active layer of the fifth transistor of the second pixel circuit through the tenth via hole V10, and the third first protruding portion can be electrically connected to the third pixel through the sixteenth via hole V16.
  • the first region of the fifth active layer of the fifth transistor of the circuit is electrically connected.
  • the first main part of the first power transmission line 661 can be electrically connected to the second capacitor plate of the storage capacitor of the first pixel circuit through the sixty-first via V61, and can also be electrically connected to the second pixel through the sixty-second via V62.
  • the second capacitor plate of the storage capacitor of the circuit is electrically connected, and can also be electrically connected to the second capacitor plate of the storage capacitor of the third pixel circuit through the sixty-third via hole V63.
  • the fourth conductive layer of the single display island area of the first display area may further include: a plurality of data connection electrodes (for example, including: the first data connection electrode 541 , the fourth data connection electrode 544, the fifth data connection electrode 545, the eighth data connection electrode 548, the ninth data connection electrode 549, the thirteenth data connection electrode 553, the sixteenth data connection electrode 556, the seventeenth data connection electrode 557, the twentieth data connection electrode 560, the twenty-first data connection electrode 561, the twenty-fourth data connection electrode 564), and a plurality of data connection lines (for example, including: the seventh data connection line 527, the eighth data connection line connection line 528, ninth data connection line 529, tenth data connection line 530, eleventh data connection line 531 and twelfth data connection line 532).
  • a plurality of data connection electrodes for example, including: the first data connection electrode 541 , the fourth data connection electrode 544, the fifth data connection electrode 545, the eighth data connection electrode 548, the ninth data connection electrode 549,
  • the seventh data connection line 527 , the ninth data connection line 529 and the eleventh data connection line 531 may be located away from the third scanning signal line RST1 (n) in the second direction Y.
  • the seventh data connection line 527 , the ninth data connection line 529 and the eleventh data connection line 531 may be arranged sequentially along the first direction X.
  • the eighth data connection line 528 , the tenth data connection line 530 and the twelfth data connection line 532 may be located in the second direction Y away from the first scanning signal line GL1 (n+1) and away from the fourth scanning signal line RST2 (n). one side.
  • the eighth data connection line 528 , the tenth data connection line 530 and the twelfth data connection line 532 may be arranged sequentially along the first direction X.
  • the first data connection electrode 541 may be electrically connected to the first data connection line 521 located on the second conductive layer through the twelfth via hole V12.
  • the fourth data connection electrode 544 may be electrically connected to the second data connection line 522 located on the second conductive layer through the thirty-sixth via hole V36.
  • the fifth data connection electrode 545 may be electrically connected to the third data connection line 523 located on the third conductive layer through the fifty-first via hole V51.
  • the eighth data connection electrode 548 may be electrically connected to the fourth data connection line 524 located on the third conductive layer through the sixty-eighth via hole V68.
  • the ninth data connection electrode 549 may be electrically connected to the fifth data connection line 525 located on the second conductive layer through the twenty-third via hole V23.
  • the twelfth data connection electrode 552 may be electrically connected to the sixth data connection line 526 located on the second conductive layer through the thirty-fifth via hole V35.
  • the thirteenth data connection electrode 553 may be electrically connected to the thirteenth data connection line 533 located on the third conductive layer through the fifty-third via hole V53 .
  • the sixteenth data connection electrode 556 may be electrically connected to the fourteenth data connection line 534 located on the third conductive layer through the sixty-seventh via hole V67.
  • the seventeenth data connection electrode 557 may be electrically connected to the fifteenth data connection line 535 located on the second conductive layer through the twenty-second via hole V22.
  • the twentieth data connection electrode 560 may be electrically connected to the sixteenth data connection line 536 located on the second conductive layer through the thirty-seventh via hole V37.
  • the twenty-first data connection electrode 561 may be electrically connected to the seventeenth data connection line 537 located on the third conductive layer through the fifty-second via hole V52.
  • the twenty-fourth data connection electrode 564 may be electrically connected to the eighteenth data connection line 538 located on the third conductive layer through the sixty-ninth via hole V69.
  • FIG. 19B is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 20B is a schematic diagram of the fourth conductive layer in FIG. 19B.
  • the fourth conductive layer of the second display area may include: a plurality of connection electrodes (for example, including: twenty-first connection electrodes 251 to thirty-second connection electrodes 262), a third scanning signal line RST1(n ), the first scanning signal line GL1(n) and the fourth power transmission line 664.
  • a fourth pixel circuit in the second display area is used as an example for explanation.
  • the twenty-first connection electrode 251 can be electrically connected to the first area of the first active layer of the first transistor of the fourth pixel circuit through the seventy-first via hole V71, and can also be electrically connected to the first area of the first active layer of the first transistor of the fourth pixel circuit through the ninety-fifth via hole V95.
  • Four initial transmission lines 614 are electrically connected.
  • the twenty-second connection electrode 252 can be electrically connected to the first region of the seventh active layer of the seventh transistor of the fourth pixel circuit in the previous row through the seventy-sixth via hole V76, and can also be electrically connected through the ninety-second via hole V76.
  • V92 is electrically connected to the fourteenth initial transmission line 634.
  • the twenty-third connection electrode 253 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the fourth pixel circuit through the seventy-third via hole V73.
  • the twenty-fourth connection electrode 254 may be electrically connected to the first region of the second active layer of the second transistor of the fourth pixel circuit through the seventy-second via hole V72, and may also be electrically connected to the second active layer through the eighty-fifth via hole V85.
  • the first region of the eighth active layer of the eighth transistor of the four-pixel circuit is electrically connected.
  • the twenty-fifth connection electrode 255 can be electrically connected to the second region of the eighth active layer of the eighth transistor of the fourth pixel circuit through the eighty-sixth via hole V86, and can also be electrically connected to the eighth active layer through the eighty-fourth via hole V84.
  • the gate of the third transistor of the four-pixel circuit is electrically connected.
  • the twenty-sixth connection electrode 256 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the fourth pixel circuit through the seventy-fifth via hole V75.
  • the twenty-seventh connection electrode 257 may be electrically connected to the fourth initial transmission line 614 through the ninety-first via hole V91.
  • the twenty-eighth connection electrode 258 may be electrically connected to the fourteenth initial transmission line 634 through the ninety-third via hole V93.
  • the twenty-ninth connection electrode 259 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the fifth pixel circuit.
  • the thirtieth connection electrode 260 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the fifth pixel circuit.
  • the thirty-first connection electrode 261 may be electrically connected to the first region of the fourth active layer of the fourth transistor of the sixth pixel circuit.
  • the thirty-second connection electrode 262 may be electrically connected to the second region of the sixth active layer of the sixth transistor of the sixth pixel circuit.
  • the first scanning signal line GL1(n) may extend along the first direction X and may connect to the fourth transistor of the fourth pixel circuit through the eighty-second via hole V82
  • the gate electrode is electrically connected, and can also be electrically connected to the gate electrode of the second transistor of the fourth pixel circuit through the eighty-third via hole V83.
  • the third scanning signal line RST1(n) may extend along the first direction X, and may be electrically connected to the gate of the first transistor of the fourth pixel circuit through the eighty-first via hole V81.
  • the fourth power transmission line 664 may include a second body portion extending along the first direction X and three protruding portions along the second direction Y on the same side of the second body portion. a second protrusion.
  • One second protrusion of the fourth power transmission line 664 may be electrically connected to the first region of the fifth active layer of the fifth transistor of the fourth pixel circuit through the seventy-fourth via hole V74, and the remaining two second protrusions
  • the portions may be electrically connected to the first regions of the fifth active layer of the fifth transistor of the fifth pixel circuit and the sixth pixel circuit respectively.
  • the second main part of the fourth power transmission line 664 can be electrically connected to the second capacitor plate of the storage capacitor of the fourth pixel circuit through the ninety-fourth via hole V94, and can also be connected to the storage capacitor of the fifth pixel circuit and the sixth pixel circuit.
  • the second capacitor plate of the capacitor is electrically connected.
  • the fourth conductive layer of at least one connection area of the first display area may include: a second initial transmission line, a third initial transmission line, a first scanning signal line, and a third scanning signal line extending along the first direction X. ; Alternatively, it may include multiple data connection lines extending along the second direction Y.
  • the film structure of the light-transmitting area of the first display area does not change.
  • a sixth insulating layer is formed on the substrate on which the foregoing pattern is formed, and the sixth insulating film is patterned through a patterning process to form a sixth insulating layer.
  • FIG. 21A is a partially enlarged schematic diagram of a display substrate after a sixth insulating layer is formed in the first display region according to at least one embodiment of the present disclosure.
  • the sixth insulating layer of a single display island area of the first display area may be provided with multiple via holes, which may include, for example: one hundred and first via holes V101 to one hundred and thirteen. Thirteen vias V133.
  • the sixth insulating layer in the 101st via hole V101 to the 133rd via hole V133 is removed, exposing the surface of the fourth conductive layer.
  • FIG. 21B is a partially enlarged schematic view of the display substrate after forming a sixth insulating layer in the second display area according to at least one embodiment of the present disclosure.
  • the sixth insulation layer of the second display area may be provided with a plurality of via holes.
  • the via holes opened in the sixth insulation layer in the area where the second pixel unit is located may include, for example: the 141st via hole V141 to the 146th via hole V146.
  • the sixth insulating layer in the one hundred and forty-first via hole V141 to the one hundred and forty-sixth via hole V146 is removed, exposing the surface of the fourth conductive layer.
  • a fifth conductive film is deposited on the substrate on which the foregoing pattern is formed, and the fifth conductive film is patterned through a patterning process to form a fifth conductive layer disposed on the sixth insulating layer.
  • the fifth conductive layer may also be called a second source-drain metal layer.
  • FIG. 22A is a partially enlarged schematic diagram of the display substrate after forming the fifth conductive layer in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 23A is a schematic diagram of the fifth conductive layer in FIG. 22A.
  • the fifth conductive layer of the single display island area of the first display area may at least include: a plurality of connection electrodes (for example, including the forty-first connection electrodes 271 to the fortieth connection electrodes).
  • the forty-first connection electrode 271 may be electrically connected to the fifth connection electrode 235 through the one hundred and nineteenth via hole V119 to achieve connection with the first pixel circuit.
  • the sixth transistor is electrically connected to the second region of the sixth active layer.
  • the forty-second connection electrode 272 may be electrically connected to the eleventh connection electrode 241 through the one hundred and twentieth via hole V120 to achieve electrical connection with the second area of the sixth active layer of the sixth transistor of the second pixel circuit.
  • the forty-third connection electrode 273 can be electrically connected to the seventeenth connection electrode 247 through the one hundred and twenty-first via hole V121 to achieve electrical connection with the second area of the sixth active layer of the sixth transistor of the third pixel circuit. connect.
  • the forty-fourth connection electrode 274 may be electrically connected to the seventh connection electrode 237 through the one hundred and tenth via hole V110 to achieve connection with the first initial transmission line 611 Electrical connection.
  • the forty-fifth connection electrode 275 may be electrically connected to the first power transmission line 661 through the seventeenth via hole V117.
  • the forty-sixth connection electrode 276 can be electrically connected to the twelfth connection electrode 242 through the one hundred and twenty-third via hole V123 to achieve electrical connection with the eleventh initial transmission line 631 .
  • the first scan connection line 651 and the second scan connection line 652 may respectively extend to the display island area from the connection areas on opposite sides of the first direction X, and extends along the second direction Y in the display island area.
  • the first scan connection line 651 can be electrically connected to one end of the third scan signal line RST1(n) through the 111th via V111
  • the second scan connection line 652 can be connected to the third scan signal line RST1(n) through the 112th via V112.
  • the other end of the scanning signal line RST1(n) is electrically connected.
  • the transmission of the first reset control signal in the first display area can be achieved.
  • the second power transmission line 662 and the third power transmission line 663 may extend from the connection areas on both sides of the display island area to the display island area in the first direction X.
  • the second power transmission line 662 can be electrically connected to one end of the first power transmission line 661 through the 116th via V116
  • the third power transmission line 663 can be electrically connected to the other end of the first power transmission line 661 through the 118th via V118. Electrical connection.
  • the twelfth initial transmission line 632 and the thirteenth initial transmission line 633 may extend from the connection areas on both sides of the display island area to the display island area in the first direction X. .
  • the twelfth initial transmission line 632 may be electrically connected to the sixth connection electrode 236 through the one hundred and twenty-second via hole V122, thereby achieving electrical connection with the eleventh initial transmission line 631.
  • the thirteenth initial transmission line 633 may be electrically connected to the eighteenth connection electrode 248 through the one hundred and twenty-fourth via hole V124, thereby achieving electrical connection with the eleventh initial transmission line 631.
  • the fifth conductive layer of the single display island area of the first display area may further include: a plurality of data connection electrodes (for example, including: the second data connection electrode 542, the third Data connection electrode 543, sixth data connection electrode 546, seventh data connection electrode 547, tenth data connection electrode 550, eleventh data connection electrode 551, fourteenth data connection electrode 554, fifteenth data connection electrode 555, The eighteenth data connection electrode 558, the nineteenth data connection electrode 559, the twenty-second data connection electrode 562 and the twenty-third data connection electrode 563), and a plurality of data lines (for example, including: the fourth data line 514 to Ninth data line 519).
  • a plurality of data connection electrodes for example, including: the second data connection electrode 542, the third Data connection electrode 543, sixth data connection electrode 546, seventh data connection electrode 547, tenth data connection electrode 550, eleventh data connection electrode 551, fourteenth data connection electrode 554, fifteenth data connection electrode 555, The eighteenth data connection electrode 558, the nineteenth data connection electrode
  • the second data connection electrode 542 may be electrically connected to the first data connection electrode 541 through the one hundred and first via hole V101.
  • the third data connection electrode 543 may be electrically connected to the fourth data connection electrode 544 through the one hundred and twenty-eighth via hole V128.
  • the sixth data connection electrode 546 may be electrically connected to the fifth data connection electrode 545 through the one hundred and third via hole V103.
  • the seventh data connection electrode 547 may be electrically connected to the eighth data connection electrode 548 through the 127th via hole V127.
  • the tenth data connection electrode 550 may be electrically connected to the ninth data connection electrode 549 through the one hundred and fifth via hole V105.
  • the eleventh data connection electrode 551 may be electrically connected to the twelfth data connection electrode 552 through the one hundred and twenty-sixth via hole V126.
  • the fourteenth data connection electrode 554 may be electrically connected to the thirteenth data connection electrode 553 through the one hundred and sixth via hole V106.
  • the fifteenth data connection electrode 555 may be electrically connected to the sixteenth data connection electrode 556 through the one hundred and thirty via hole V130.
  • the eighteenth data connection electrode 558 may be electrically connected to the seventeenth data connection electrode 557 through the one hundred and fourth via hole V104.
  • the nineteenth data connection electrode 559 may be electrically connected to the twentieth data connection electrode 560 through the one hundred and thirty-first via hole V131.
  • the twenty-second data connection electrode 562 may be electrically connected to the twenty-first data connection electrode 561 through the one hundred and second via hole V102.
  • the twenty-third data connection electrode 563 may be electrically connected to the twenty-fourth data connection electrode 564 through the one hundred and thirty-second via hole V132.
  • the fourth, sixth, and eighth data lines 514, 516, and 518 extend along the second direction Y within the display island area.
  • the fifth data line 515, the seventh data line 517 and the ninth data line 519 extend along the second direction Y from the connection area to the display island area, and then extend to another connection area.
  • the fourth to ninth data lines 514 to 519 may be arranged sequentially along the first direction X.
  • One end of the fourth data line 514 can be electrically connected to the seventh data connection line 527 through the 107th via V107, and the other end can be electrically connected to the eighth data connection line 528 through the 129th via V129.
  • the fourth data line 514 may also be electrically connected to the third connection electrode 233 through the thirteenth via hole V113, thereby achieving electrical connection with the first region of the fourth active layer of the fourth transistor of the first pixel circuit.
  • One end of the sixth data line 516 can be electrically connected to the ninth data connection line 529 through the 108th via V108, and the other end can be electrically connected to the tenth data connection line 530 through the 125th via V125.
  • the sixth data line 516 may also be electrically connected to the ninth connection electrode 239 through the 14th via hole V114, thereby achieving electrical connection with the first region of the fourth active layer of the fourth transistor of the second pixel circuit.
  • One end of the eighth data line 518 can be electrically connected to the eleventh data connection line 531 through the 109th via V109, and the other end can be electrically connected to the twelfth data connection line 532 through the 133rd via V133. connect.
  • the eighth data line 518 may also be electrically connected to the fifteenth connection electrode 245 through the fifteenth via hole V115, thereby achieving electrical connection with the first region of the fourth active layer of the fourth transistor of the third pixel circuit. .
  • the fourth data line 514 may be configured to provide a data signal to the first pixel circuit
  • the sixth data line 516 may be configured to provide a data signal to the second pixel circuit
  • the eighth data line 518 may be configured to A data signal is provided to the third pixel circuit.
  • the fifth data line 515 may pass through the display island area from the area where the first pixel circuit is located
  • the seventh data line 517 may pass through the display island area from the area where the second pixel circuit is located
  • the ninth data line 519 may pass from the area where the third pixel circuit is located.
  • the area passes through the display island area.
  • the fifth, seventh and ninth data lines 515, 517 and 519 may directly extend to the connection area along the second direction Y.
  • the fourth data line 514, the sixth data line 516 and the eighth data line 518 may be electrically connected to the data connection lines of the connection area respectively.
  • the orthographic projection of a first area pixel circuit on the substrate may overlap with the orthographic projection of the two data lines on the substrate.
  • the orthographic projection of the first semiconductor layer of a first region pixel circuit on the substrate may overlap with the orthographic projection of the two data lines on the substrate.
  • the front projection of the first semiconductor layer (including the active layer of a plurality of first type transistors) of the first pixel circuit on the substrate may be the same as the front projection of the fourth data line 514 and the fifth data line 515 on the substrate. Projections overlap.
  • the orthographic projection of the first semiconductor layer of the second pixel circuit on the substrate may overlap with the orthographic projection of the sixth and seventh data lines 516 and 517 on the substrate.
  • the orthographic projection of the first semiconductor layer of the third pixel circuit on the substrate may overlap with the orthographic projection of the eighth and ninth data lines 518 and 519 on the substrate.
  • FIG. 22B is a partially enlarged schematic diagram of the display substrate after the fifth conductive layer is formed in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 23B is a schematic diagram of the fifth conductive layer in FIG. 22B.
  • the fifth conductive layer of the second display area may include: a plurality of connection electrodes (for example, including: the forty-seventh connection electrode 277 to the forty-ninth connection electrode 279 ) , a plurality of data lines extending along the second direction Y (for example, including: data lines DL1a, DL1b, DL2a, DL2b, DL3a and DL3b).
  • the data lines DL1a, DL1b, DL2a, DL2b, DL3a and DL3b may be arranged sequentially along the first direction X.
  • the 47th connection electrode 277 may be electrically connected to the 26th connection electrode 256 through the 142nd via hole V142.
  • the forty-eighth connection electrode 278 may be electrically connected to the thirtieth connection electrode 260 through the one hundred and forty-fourth via hole V144.
  • the forty-ninth connection electrode 279 may be electrically connected to the thirty-second connection electrode 262 through the one hundred and forty-sixth via hole V146.
  • the fourth pixel circuit is located at the j-1th column and the nth row
  • the fifth pixel circuit is located at the jth column and the nth row
  • the sixth pixel circuit is located at the j+1th column and the nth row.
  • the data line DL1a can be electrically connected to the twenty-third connection electrode 253 through the 141st via hole V141, and is configured to provide a data signal to the fourth pixel circuit located in the j-1th column and the nth row.
  • the data line DL2a can be electrically connected to the 29th connection electrode 259 through the 143rd via V143, and is configured to provide a data signal to the fifth pixel circuit located in the jth column and nth row.
  • the data line DL3a may be electrically connected to the thirty-first connection electrode 261 through the one hundred and forty-fifth via hole V145, and is configured to provide a data signal to the sixth pixel circuit located in the j+1th column and the nth row.
  • the data line DL1b may be configured to provide a data signal to the fourth pixel circuit located at the j-1th column and the n-1th row
  • the data line DL2b may be configured to provide a data signal to the fourth pixel circuit located at the jth column and the n-th row.
  • the five pixel circuits provide data signals
  • the data line DL3b may be configured to provide data signals to the sixth pixel circuit located in the j+1th column and nth row.
  • the second area pixel circuits in odd-numbered rows and even-numbered rows are electrically connected to different data lines, which can ensure that the data signal better matches the parasitic capacitance of the second area pixel circuit, thereby ensuring the display effect.
  • the fifth conductive layer of at least one connection area of the first display area may include: first and second scanning connection lines 651 and 652 extending along the first direction Three power transmission lines 663, a twelfth initial transmission line 632 and a thirteenth initial transmission line 633; or may include fifth, seventh and ninth data lines 515, 517 and 519 extending along the second direction Y.
  • the film structure of the light-transmitting area of the first display area does not change.
  • a seventh insulating layer is formed on the substrate on which the foregoing pattern is formed, and the seventh insulating film is patterned through a patterning process to form a seventh insulating layer.
  • FIG. 24A is a partially enlarged schematic view of the display substrate after forming a seventh insulating layer in the first display area according to at least one embodiment of the present disclosure.
  • the seventh insulating layer of a single display island area of the first display area may be provided with multiple via holes, which may include, for example: one hundred and fifty-first via holes V151 to one hundred. Sixty-eight vias V168.
  • the seventh insulating layer in the one hundred and fifty-first via hole V151 to the one hundred and sixty-eighth via hole V168 is removed, exposing the surface of the fifth conductive layer.
  • FIG. 24B is a partially enlarged schematic diagram of the display substrate after forming a seventh insulating layer in the second display area according to at least one embodiment of the present disclosure.
  • the seventh insulation layer of the second display area may be provided with a plurality of via holes.
  • the via holes opened in the seventh insulation layer in the area where a second pixel unit of the second display area is located may include, for example: the 171st via hole V171 to the 176th via hole V176.
  • the seventh insulating layer and the sixth insulating layer in the 171st via hole V171 to the 173rd via hole V173 are removed, exposing the surface of the fourth conductive layer.
  • the seventh insulating layer in the one hundred and seventy-fourth via hole V174 and the one hundred and seventy-sixth via hole V176 is removed, exposing the surface of the fifth conductive layer.
  • the connection area of the first display area may include a substrate, and a first conductive layer, a first insulating layer, a second insulating layer, and a second insulating layer sequentially disposed on the substrate. a conductive layer, a third insulating layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer and a seventh insulating layer.
  • the light-transmitting area of the first display area may include a substrate, and first to seventh insulating layers sequentially disposed on the substrate.
  • a sixth conductive layer is deposited on the substrate on which the foregoing pattern is formed, and the sixth conductive film is patterned through a patterning process to form a sixth conductive layer disposed on the seventh insulating layer.
  • the sixth conductive layer may also be called a third source-drain metal layer.
  • Figure 25A is a partially enlarged schematic view of the display substrate after forming a sixth conductive layer in the first display area according to at least one embodiment of the present disclosure.
  • FIG. 26A is a schematic diagram of the sixth conductive layer in FIG. 25A. In some examples, as shown in FIGS.
  • the sixth conductive layer of the single display island area of the first display area may at least include: a plurality of connection electrodes (for example, including: the fifty-first connection electrodes 281 to the fifth Thirteen connection electrodes 583), a plurality of data lines (for example, including the first to third data lines 511 to 513, the tenth to twelfth data lines 520 to 522), the fifth initial transmission line 615, the fifteenth initial The transmission line 635, the fifth power transmission line 665, and the seventh power transmission line 667.
  • a plurality of connection electrodes for example, including: the fifty-first connection electrodes 281 to the fifth Thirteen connection electrodes 583
  • a plurality of data lines for example, including the first to third data lines 511 to 513, the tenth to twelfth data lines 520 to 522
  • the fifth initial transmission line 615 for example, including the fifteenth initial The transmission line 635, the fifth power transmission line 665, and the seventh power transmission line 667.
  • the fifty-first connection electrode 281 may be electrically connected to the forty-first connection electrode 271 through the one hundred and fifty-eighth via hole V158.
  • the fifty-second connection electrode 282 may be electrically connected to the forty-second connection electrode 272 through the one hundred and sixtieth via hole V160.
  • the fifty-third connection electrode 283 may be electrically connected to the forty-third connection electrode 273 through the one hundred and sixty-first via hole V161.
  • the first data line 511 , the second data line 512 and the third data line 513 may be located in the display island area and arranged sequentially along the first direction X, and located in the display island area.
  • the fifth power transmission line 665 is on a side away from the fifth initial transmission line 615 .
  • the first data line 511, the second data line 512 and the third data line 513 may be arc-shaped.
  • the tenth data line 520 , the eleventh data line 521 and the twelfth data line 522 may be located in the display island area and arranged sequentially along the first direction X, and be located away from the seventh power transmission line 668 away from the fifteenth initial transmission line 635 one side.
  • the tenth data line 520, the eleventh data line 521, and the twelfth data line 522 may be arc-shaped.
  • one end of the first data line 511 may be electrically connected to the second data connection electrode 542 through the 151st via hole V151, and the other end may be through the 151st via hole V151.
  • One hundred and sixty-seven via holes V167 are electrically connected to the third data connection electrode 543 .
  • One end of the second data line 512 can be electrically connected to the sixth data connection electrode 546 through the 153rd via hole V153, and the other end can be electrically connected to the seventh data connection electrode 547 through the 165th via hole V165. .
  • One end of the third data line 513 can be electrically connected to the tenth data connection electrode 550 through the 155th via hole V155, and the other end can be electrically connected to the 11th data connection electrode 551 through the 163rd via hole V163. connect.
  • One end of the tenth data line 520 can be electrically connected to the fourteenth data connection electrode 554 through the one hundred and fifty-sixth via hole V156, and the other end can be connected to the fifteenth data connection electrode 555 through the one hundred and sixty-fourth via hole V164. Electrical connection.
  • One end of the eleventh data line 521 can be electrically connected to the eighteenth data connection electrode 558 through the one hundred and fifty-fourth via hole V154, and the other end can be connected to the nineteenth data connection electrode through the one hundred and sixty-sixth via hole V166. 559 electrical connection.
  • One end of the twelfth data line 522 can be electrically connected to the 22nd data connection electrode 562 through the 152nd via V152, and the other end can be connected to the 23rd data connection electrode 562 through the 168th via V168.
  • the connection electrode 563 is electrically connected.
  • the first to third data lines 511 to 513 and the tenth to twelfth data lines 520 to 522 may surround the periphery of the three first area pixel circuits in the display island area and bypass the third A region is the area where the pixel circuit is located.
  • the first to third data lines 511 to 513 and the tenth to twelfth data lines 520 to 522 may be arc-shaped respectively, and the first to third data lines 511 to 513 may be in the first direction X.
  • the side away from the first pixel circuit is bent, and the tenth to twelfth data lines 520 to 522 may be bent toward the side away from the third pixel circuit in the first direction X. In this way, the edge of the display island area can be made into an arc edge, and the interference between the above-mentioned plurality of data lines and the first area pixel circuit can be reduced.
  • the fifth power transmission line 665 may transmit the first voltage signal in the second direction Y, and the first power transmission line 661 , the second power transmission line 662 and the third power transmission line 663 may be electrically connected.
  • the first voltage signal is transmitted in the first direction X.
  • the fifth power transmission line 665 located in the sixth conductive layer is electrically connected to the first power transmission line 661 located in the fourth conductive layer through the 45th connection electrode 275 located in the fifth conductive layer, and can provide the first voltage in the first display area.
  • the mesh transmission path of the signal can reduce the load of the transmission line of the first voltage signal and improve the transmission uniformity of the first voltage signal in the first display area.
  • the seventh power transmission line 667 may be configured to transmit the second voltage signal.
  • the fifth initial transmission line 615 may transmit the first initial signal in the second direction Y within the first display area.
  • the first initial signal can be transmitted in the first direction X by electrically connecting the second initial transmission line 612, the first initial transmission line 611 and the third initial transmission line 613.
  • the fifth initial transmission line 615 located in the sixth conductive layer may be connected to the first initial transmission line 611 located in the third conductive layer through the 44th connection electrode 274 located in the fifth conductive layer and the seventh connection electrode 237 located in the fourth conductive layer.
  • the electrical connection can provide a mesh transmission path for the first initial signal in the first display area, thereby reducing the load on the transmission line of the first initial signal and improving the transmission uniformity of the first initial signal in the first display area.
  • the fifteenth initial transmission line 635 may transmit the second initial signal in the second direction Y.
  • the second initial signal may be transmitted in the first direction X by electrically connecting the twelfth initial transmission line 632, the eleventh initial transmission line 631, and the thirteenth initial transmission line 633.
  • the fifteenth initial transmission line 635 located in the sixth conductive layer may be connected to the eleventh connection electrode located in the third conductive layer through the forty-sixth connection electrode 276 located in the fifth conductive layer and the twelfth connection electrode 242 located in the fourth conductive layer.
  • the initial transmission line 631 is electrically connected to provide a mesh transmission path for the second initial signal in the first display area, thereby reducing the load on the transmission line of the second initial signal and improving the uniformity of transmission of the second initial signal in the first display area. sex.
  • a single display island area of the first display area can be provided with twelve data lines, six of which can pass through the area where the pixel circuit is located in the first area, and the remaining six data lines can surround the three first areas.
  • the periphery of the pixel circuit can be provided with twelve data lines, six of which can pass through the area where the pixel circuit is located in the first area, and the remaining six data lines can surround the three first areas. The periphery of the pixel circuit.
  • FIG. 25B is a partially enlarged schematic diagram of the display substrate after the sixth conductive layer is formed in the second display area according to at least one embodiment of the present disclosure.
  • FIG. 26B is a schematic diagram of the sixth conductive layer in FIG. 25B.
  • the sixth conductive layer of the second display area may include: a plurality of connection electrodes (for example, including the fifty-fourth connection electrode 284 to the fifty-sixth connection electrode 286 ), The sixth initial transmission line 616 , the sixteenth initial transmission line 636 , the sixth power transmission line 666 and the eighth power transmission line 668 .
  • the fifty-fourth connection electrode 284 may be electrically connected to the forty-seventh connection electrode 277 through the one hundred and seventy-fourth via hole V174.
  • the fifty-fifth connection electrode 285 may be electrically connected to the forty-eighth connection electrode 278 through the one hundred and seventy-fifth via hole V175.
  • the fifty-fifth connection electrode 285 may extend in the second direction Y.
  • the fifty-sixth connection electrode 286 may be electrically connected to the forty-ninth connection electrode 279 through the one hundred and seventy-sixth via hole V176.
  • the sixth initial transmission line 616 , the sixteenth initial transmission line 636 , the sixth power transmission line 666 , and the eighth power transmission line 668 may all extend along the second direction Y.
  • the sixth initial transmission line 616 may be electrically connected to the twenty-seventh connection electrode 257 located on the fourth conductive layer through the one hundred and seventy-first via hole V171 to achieve electrical connection with the fourth initial transmission line 614.
  • the sixteenth initial transmission line 636 located on the sixth conductive layer may transmit the second initial signal in the second direction Y.
  • the fourteenth initial transmission line 634 located on the third conductive layer may transmit the second initial signal in the first direction X.
  • the sixteenth initial transmission line 636 can provide a mesh transmission path for the second initial signal in the second display area, thereby reducing the load of the transmission line of the second initial signal and improving the performance of the second initial signal.
  • the transmission uniformity of the second initial signal in the second display area is not limited.
  • the sixteenth initial transmission line 636 may be electrically connected to the twenty-eighth connection electrode 258 through the one hundred and seventy-second via hole V172 to achieve electrical connection with the fourteenth initial transmission line 634 .
  • the sixth initial transmission line 616 located on the sixth conductive layer may transmit the first initial signal in the second direction Y.
  • the fourth initial transmission line 614 located on the third conductive layer may transmit the first initial signal in the first direction X.
  • the sixth initial transmission line 616 can provide a mesh transmission path for the first initial signal in the second display area, thereby reducing the load on the transmission line of the first initial signal and improving the second display. Transmission uniformity of the first initial signal in the area.
  • the sixth power transmission line 666 may be electrically connected to the fourth power transmission line 664 located on the fourth conductive layer through the one hundred and seventy-third via hole V173. By being electrically connected to the fourth power transmission line 664, the sixth power transmission line 666 can provide a mesh transmission path for the first voltage signal in the second display area, thereby reducing the load on the transmission line of the first voltage signal and improving the second display. area of first voltage signal transmission uniformity.
  • the sixteenth initial transmission line 636 may be located between the fourth pixel circuit and the fifth pixel circuit, and the sixth initial transmission line 634 may be located between the fourth pixel circuit and the corresponding phase.
  • the eighth power transmission line 668 may be located between the fifth pixel circuit and the sixth pixel circuit.
  • the sixth conductive layer of at least one connection area of the first display area may include: a fifth power transmission line 665 extending along the second direction Y, a fifth initial transmission line 615, a fifteenth initial transmission line 635, and a seventh Power transmission line 667.
  • the film structure of the light-transmitting area of the first display area does not change.
  • the driving circuit layer 102 can be prepared.
  • the display island area of the first display area and the driving circuit layer 102 of the second display area may include a first conductive layer, a first insulating layer, a first semiconductor layer, a second insulating layer stacked on the substrate. layer, second conductive layer, third insulating layer, second semiconductor layer, fourth insulating layer, third conductive layer, fifth insulating layer, fourth conductive layer, sixth insulating layer, fifth conductive layer, seventh insulating layer layer and the sixth conductive layer.
  • the driving circuit layer 102 of the connection area of the first display area may include a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third insulating layer, and a fourth insulating layer stacked on the substrate. , a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, a seventh insulating layer and a sixth conductive layer.
  • the driving circuit layer 102 of the light-transmissive area of the first display area may include first to seventh insulating layers stacked on the substrate.
  • the first to third data lines 511 to 513 and the tenth to twelfth data lines 520 to 522 in the display island area are in an arc shape, which can make the peripheral edge (ie, transparent) of the display island area
  • the second edge of the light area that contacts the display island area) is arc-shaped.
  • the signal traces (for example, including data connection lines, data lines, and scanning signal lines) provided in the connection area and located on multiple conductive film layers can all be line segments or strip-shaped bodies, which can make the peripheral edge of the connection area (i.e., transparent
  • the first edge of the light area in contact with the connection area) extends in one direction.
  • the shape of the first edge of the light-transmitting area can be determined by the signal wiring closest to the light-transmitting area in the connection area (for example, the second initial transmission line 612, the third initial transmission line 613, the first scanning signal line GL1 located on the fifth conductive layer)
  • the peripheral edge shape of (n+1), etc.) is determined.
  • this embodiment is not limited to this.
  • the orthographic projection of the first shielding trace 211 located on the first conductive layer on the substrate can cover the orthographic projection of the signal traces of the remaining conductive layers on the substrate, and the second shielding trace
  • the orthographic projection of 212 on the substrate can cover the orthographic projection of the signal traces of the remaining conductive layers on the substrate.
  • an eighth insulating film is coated on the substrate on which the foregoing pattern is formed, and the eighth insulating film is patterned through a patterning process to form an eighth insulating layer.
  • FIG. 27A is a partially enlarged schematic view of the display substrate after forming an eighth insulating layer in the first display region according to at least one embodiment of the present disclosure.
  • the eighth insulating layer of a single display island area of the first display area may be provided with multiple via holes, for example, may include the one hundred and eighty-first via holes V181 to the eighteenth one. Thirteen vias V183.
  • the eighth insulating layer in the one hundred and eighty-first via hole V181 to the one hundred and eighty-third via hole V183 can be removed to expose the surface of the sixth conductive layer.
  • FIG. 27B is a partially enlarged schematic diagram of the display substrate after forming an eighth insulating layer in the second display area according to at least one embodiment of the present disclosure.
  • the eighth insulation layer of the second display area may be provided with a plurality of via holes.
  • the via holes opened in the eighth insulation layer in the area where a second pixel unit of the second display area is located may include, for example, the one hundred and eighty-fourth via hole V184 to the one hundred and eighty-sixth via hole V186.
  • the eighth insulating layer in the one hundred and eighty-fourth via hole V184 to the one hundred and eighty-sixth via hole V186 is removed, exposing the surface of the seventh conductive layer.
  • anode film is deposited on a substrate on which the foregoing pattern is formed, and the anode film is patterned through a patterning process to form an anode layer.
  • FIG. 28A is a partially enlarged schematic view of the display substrate after forming an anode layer in the first display region according to at least one embodiment of the present disclosure.
  • Figure 29A is a schematic diagram of the anode layer in Figure 28A.
  • the anode layer of the single display island area of the first display area may include: a first anode 671 of the first light-emitting element, a second anode 672 of the second light-emitting element, and a second anode 672 of the second light-emitting element.
  • the third anode 673 of the three light-emitting elements may include: a first anode 671 of the first light-emitting element, a second anode 672 of the second light-emitting element, and a second anode 672 of the second light-emitting element.
  • the third anode 673 of the three light-emitting elements may include: a first anode 671 of the first light-emitting element, a
  • the first anode 671 and the second anode 672 may be arranged along the second direction Y, and the third anode 673 may be located on the same side of the first anode 671 and the second anode 672 in the first direction X.
  • the overall shapes of the first anode 671, the second anode 672, and the third anode 673 may be combined into a generally circular shape.
  • the first anode 671 may be electrically connected to the fifty-first connection electrode 281 located on the sixth conductive layer through the one hundred and eighty-first via hole V181 , so that the first anode 671 may be electrically connected to the fifty-first connection electrode 281 located on the sixth conductive layer through the one hundred and eighty-first via hole V181 .
  • the forty-first connection electrode 271 of the fifth conductive layer and the fifth connection electrode 235 located in the fourth conductive layer are electrically connected to the second region of the sixth active layer of the sixth transistor of the first pixel circuit.
  • the second anode 672 can be electrically connected to the 52nd connection electrode 282 located on the sixth conductive layer through the 182nd via hole V182, so that the second anode 672 can be electrically connected to the 52nd connection electrode 282 located on the fifth conductive layer through the 42nd connection electrode 272 located on the fifth conductive layer.
  • the eleventh connection electrode 241 of the fourth conductive layer is electrically connected to the second region of the sixth active layer of the sixth transistor of the second pixel circuit.
  • the third anode 673 can be electrically connected to the fifty-third connection electrode 283 located on the sixth conductive layer through the one hundred and eighty-third via hole V183, so that it can be electrically connected to the fifty-third connection electrode 283 located on the fifth conductive layer through the forty-third connection electrode 273 located on the fifth conductive layer.
  • the seventeenth connection electrode 247 of the fourth conductive layer is electrically connected to the second region of the sixth active layer of the sixth transistor of the third pixel circuit.
  • FIG. 28B is a partially enlarged schematic view of the display substrate after forming an anode layer in the second display region according to at least one embodiment of the present disclosure.
  • Figure 29B is a schematic diagram of the anode layer in Figure 28B.
  • the anode layer of the second display area may include: a plurality of anodes (for example, including the fourth anode 674 of the fourth light-emitting element, the fifth anode 675 of the fifth light-emitting element, and The sixth anode 676) of the sixth light-emitting element.
  • the fourth anode 674 and the fifth anode 675 may be arranged along the second direction Y, and the sixth anode 676 may be located on the same side of the fourth anode 674 and the fifth anode 675 in the first direction X.
  • the overall shape of the fourth anode 674, the fifth anode 675, and the sixth anode 676 may be generally rectangular.
  • the fourth anode 674 may be electrically connected to the fifty-fourth connecting electrode 284 located on the sixth conductive layer through the one hundred and eighty-fourth via hole V184, so that the fourth anode 674 may be electrically connected to the fifty-fourth connecting electrode 284 located on the sixth conductive layer through the one hundred and eighty-fourth via hole V184.
  • the forty-seventh connection electrode 277 of the fifth conductive layer and the twenty-sixth connection electrode 256 located on the fourth conductive layer are electrically connected to the second region of the sixth active layer of the sixth transistor of the fourth pixel circuit.
  • the fifth anode 675 can be electrically connected to the fifty-fifth connection electrode 285 located on the sixth conductive layer through the one hundred and eighty-fifth via hole V185, so that it can be electrically connected to the fifty-fifth connection electrode 285 located on the fifth conductive layer through the forty-eighth connection electrode 278 located on the fifth conductive layer.
  • the thirtieth connection electrode 260 of the fourth conductive layer is electrically connected to the second region of the sixth active layer of the sixth transistor of the fifth pixel circuit.
  • the sixth anode 676 can be electrically connected to the fifty-sixth connection electrode 286 located on the sixth conductive layer through the one hundred and eighty-sixth via hole V186, so that it can be electrically connected to the fifty-sixth connection electrode 286 located on the fifth conductive layer through the forty-ninth connection electrode 279 located on the fifth conductive layer.
  • the thirty-second connection electrode 262 of the fourth conductive layer is electrically connected to the second region of the sixth active layer of the sixth transistor of the sixth pixel circuit.
  • a pixel definition film is coated on the substrate on which the foregoing pattern is formed, and a pixel definition layer (PDL, Pixel Define Layer) is formed through masking, exposure and development processes.
  • PDL Pixel Define Layer
  • FIG. 30A is a partially enlarged schematic diagram of a display substrate after forming a pixel definition layer in the first display area according to at least one embodiment of the present disclosure.
  • the pixel definition layer of a single display island area of the first display area may form a first pixel opening OP1, a second pixel opening OP2, and a third pixel opening OP3.
  • the first pixel opening OP1 may expose the surface of the first anode 671
  • the second pixel opening OP2 may expose the surface of the second anode 672
  • the third pixel opening OP3 may expose the surface of the third anode 673 .
  • the pixel definition layer of the second display area may form a plurality of pixel openings (for example, including fourth to sixth pixel openings OP4 to OP6).
  • the fourth pixel opening OP4 can expose the surface of the fourth anode 674
  • the fifth pixel opening OP5 can expose the surface of the fifth anode 675
  • the sixth pixel opening OP6 can expose the surface of the sixth anode 676.
  • an organic light-emitting layer may be formed within the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode layer.
  • the cathode layer is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • Figure 31 is a partial cross-sectional view along the Q-Q' direction in Figure 30A.
  • a single display island area of the first display area may include: a substrate 101 , and a driving circuit layer 102 and a light emitting layer disposed on the substrate 101 Structural layer 103.
  • the driving circuit layer 102 may include: a first conductive layer 21, a first insulating layer 201, a first semiconductor layer 27, a second insulating layer 202, a second conductive layer 22, a third insulating layer 203, a second semiconductor layer 28, Four insulating layers 204, a third conductive layer 23, a fifth insulating layer 205, a fourth conductive layer 24, a sixth insulating layer 206, a fifth conductive layer 25, a seventh insulating layer 207 and a sixth conductive layer 26.
  • An eighth insulating layer 208 is disposed between the driving circuit layer 102 and the light-emitting structure layer 103 .
  • the light-emitting structure layer 103 may include: an anode layer 301, a pixel definition layer 302, an organic light-emitting layer and a cathode layer.
  • the structure of each film layer is as shown before, so no details will be given here.
  • the first to sixth conductive layers may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). species, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). species, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the first to fifth insulating layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite. layer.
  • the sixth to eighth insulating layers can also be called flat layers, and can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited to this.
  • the display substrate provided in this embodiment can reduce the wiring space in the four corner areas of the display island area by adjusting the wiring of the display island area, so that the display island area is circular or elliptical, thereby reducing poor diffraction of the display substrate, for example
  • the shooting effect of the camera below the display substrate can be improved; and the area of the light-transmitting area can be increased, thereby increasing the light transmittance of the first display area.
  • the second display area of the display substrate uses odd and even row second area pixel circuits to connect different data lines, which can ensure that the data signal matches the parasitic capacitance of the pixel circuit.
  • the wiring of the first display area can be consistent with the wiring of the second display area, and multiple data lines can be arranged around the periphery of the first area pixel circuit to reduce the impact of the data lines passing through the display island area on the first area pixel circuit. interference.
  • the structure of the display substrate and its preparation process in this embodiment are only illustrative. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, the first conductive layer may not need to be provided. However, this embodiment is not limited to this.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • FIG. 32A is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure.
  • 32B is a partial schematic diagram of the display substrate after forming a black matrix in the first display area according to at least one embodiment.
  • FIG. 32C is a schematic diagram of the black matrix in FIG. 32B.
  • FIG. 32A illustrates the anode layers of a plurality of first pixel units (for example, including the first anode 671 of the first light-emitting element, the second anode 672 of the second light-emitting element, and the third anode 673 of the third light-emitting element) and pixel definitions.
  • pixel openings of the layer eg, first pixel opening OP1, second pixel opening OP2, and third pixel opening OP3.
  • the black matrix 105 may be located on a side of the encapsulation layer away from the substrate.
  • a black matrix may be provided in both the first display area and the second display area, or a black matrix may be provided only in the first display area.
  • the black matrix 105 may be located in the connection area and the display island area.
  • the black matrix 105 may not overlap with the orthographic projection of the substrate and the light-transmitting area.
  • the black matrix 105 of the display island area may include: a first matrix opening 105a, a second matrix opening 105b, and a third matrix opening 105c.
  • the orthographic projection of the first pixel opening OP1 on the substrate may be located within the orthographic projection range of the first matrix opening 105a on the substrate.
  • the orthographic projection of the second pixel opening OP2 on the substrate may be located within the orthographic projection range of the second matrix opening 105b on the substrate.
  • the orthographic projection of the third pixel opening OP3 on the substrate may be located within the orthographic projection range of the third matrix opening 105c on the substrate.
  • the orthographic projection of the first matrix opening 105a on the substrate may be located within the orthographic projection range of the first anode 671 on the substrate.
  • the orthographic projection of the second matrix opening 105b on the substrate may be located within the orthographic projection range of the second anode 672 on the substrate.
  • the orthographic projection of the third matrix opening 105c on the substrate may be located within the orthographic projection range of the third anode 673 on the substrate.
  • the anode layer in the display island area can cover the gap between the black matrix 105 and the pixel opening of the pixel definition layer, which can avoid light leakage through the gap and reduce diffraction caused by the gap.
  • the connection area can be covered by a black matrix, which can reduce the extension caused by gaps between traces.
  • the anode layer of the second display area may also cover the gap between the black matrix and the pixel opening of the pixel definition layer.
  • this embodiment is not limited to this.
  • the black matrix can cover the non-luminous and connecting areas of the display island.
  • the shape of the first edge and the second edge of the light-transmitting area may be determined by the shape of the peripheral edge of the black matrix.
  • both the first edge and the second edge of the light-transmitting area may be flat edges.
  • the first edge and the second edge of the light-transmitting area may be uneven edges, for example, there may be some small deformation caused by tolerance.
  • At least one embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • FIG. 33 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 33 , this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91 .
  • the photosensitive sensor 92 is located on the non-display surface side of the display substrate 91 .
  • the orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the first display area A1.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be a product with a function of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • the display device can be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a camcorder, Any product including viewfinders, navigators, vehicles, large-area walls, information query equipment (such as business query equipment for e-government, banks, hospitals, electric power and other departments), monitors, etc.
  • the display device may be any product including a microdisplay, a VR device or an AR device including a microdisplay.

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Abstract

一种显示基板，包括：第一显示区(A1)。第一显示区(A1)包括：彼此隔开的多个显示岛区(A11)、位于相邻显示岛区之间的透光区(A12)以及连接相邻显示岛区(A11)的连接区(A13)。显示岛区(A11)包括：第一像素单元(P1)。第一像素单元(P1)包括：第一区域像素电路(13)和第一区域发光元件(11)。显示岛区(A11)具有弧形边缘。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：第一显示区。所述第一显示区包括：彼此隔开的多个显示岛区、位于相邻显示岛区之间的透光区以及连接相邻显示岛区的连接区。所述显示岛区包括：设置在衬底上的第一像素单元，所述第一像素单元包括：第一区域像素电路和与所述第一区域像素电路电连接的第一区域发光元件；所述第一区域像素电路在所述衬底的正投影与电连接的所述第一区域发光元件在所述衬底的正投影存在交叠。所述显示岛区具有弧形边缘。
在一些示例性实施方式中，所述显示岛区为圆形或椭圆形。
在一些示例性实施方式中，所述透光区的边缘包括：与所述连接区接触的第一边缘、以及与所述显示岛区接触的第二边缘；所述第一边缘与所述第二边缘间隔连接，所述第二边缘为弧形。
在一些示例性实施方式中，所述透光区为八边形。
在一些示例性实施方式中，所述透光区的第一边缘为直线型、波浪型或 者折线型。
在一些示例性实施方式中，所述显示岛区包括一个第一像素单元，所述第一像素单元包括：三个第一区域发光元件；所述三个第一区域发光元件包括：出射第一颜色光的第一发光元件、出射第二颜色光的第二发光元件、以及出射第三颜色光的第三发光元件。
在一些示例性实施方式中，所述第一发光元件、所述第二发光元件和所述第三发光元件的发光区域整体组成圆形或椭圆形。
在一些示例性实施方式中，所述第一像素单元还包括：三个第一区域像素电路，所述三个第一区域像素电路和所述三个第一区域发光元件一一对应电连接。所述三个第一区域像素电路沿第一方向依次排布；所述第一发光元件和第二发光元件在第二方向上依次排布，所述第三发光元件在所述第一方向上位于所述第一发光元件和第二发光元件的同一侧；其中，所述第一方向与所述第二方向交叉。
在一些示例性实施方式中，所述显示岛区还包括：多条数据线；至少一个第一区域像素电路与一条数据线电连接，且所述第一区域像素电路在所述衬底的正投影与两条数据线在所述衬底的正投影存在交叠。所述多条数据线中的至少一条数据线围绕在所述第一像素单元的全部第一区域像素电路的外侧。
在一些示例性实施方式中，所述第一像素单元包括三个第一区域像素电路；所述三个第一区域像素电路包括沿第一方向依次排布的第一像素电路、第二像素电路和第三像素电路。所述显示岛区包括：沿所述第一方向依次排布的第一数据线至第十二数据线。所述第一数据线至第三数据线在所述第一方向上位于所述三个第一区域像素电路的一侧，第十数据线至第十二数据线在所述第一方向上位于所述三个第一区域像素电路的另一侧。所述第一像素电路与第四数据线电连接，且所述第一像素电路在所述衬底的正投影与所述第四数据线和第五数据线在所述衬底的正投影存在交叠。所述第二像素电路与第六数据线电连接，且所述第二像素电路在所述衬底的正投影与所述第六数据线和第七数据线在所述衬底的正投影存在交叠。所述第三像素电路与第八数据线电连接，且所述第三像素电路在所述衬底的正投影与所述第八数据 线和第九数据线在衬底的正投影存在交叠。
在一些示例性实施方式中，所述第一数据线至第三数据线、第十数据线至第十二数据线均为在所述第一方向往远离所述第一区域像素电路的方向弯曲的弧状走线，其中，所述第一数据线至第三数据线的弯曲方向不同于所述第十数据线至第十二数据线的弯曲方向。
在一些示例性实施方式中，所述第一数据线至第三数据线、所述第十数据线至第十二数据线为同层结构，且位于第四数据线至第九数据线远离所述衬底的一侧。
在一些示例性实施方式中，所述第一区域像素电路包括：至少一个第一类型晶体管、至少一个第二类型晶体管和存储电容，所述第一类型晶体管和第二类型晶体管的晶体管类型不同。
在一些示例性实施方式中，在垂直于显示基板的方向上，所述第一显示区至少包括：衬底以及设置在所述衬底上的第一半导体层、第二导电层、第二半导体层、第三导电层、第四导电层、第五导电层和第六导电层。所述第一半导体层至少包括：所述第一区域像素电路的第一类型晶体管的有源层。所述第二导电层至少包括：所述第一区域像素电路的第一类型晶体管的栅极。所述第二半导体层至少包括：所述第一区域像素电路的第二类型晶体管的有源层。所述第三导电层至少包括：所述第一区域像素电路的第二类型晶体管的栅极。所述第四导电层至少包括：所述第一区域像素电路电连接的多条扫描信号线。所述第五导电层至少包括：与所述第一区域像素电路电连接或交叠的多条数据线。所述第六导电层至少包括：位于所述第一区域像素电路外围的多条数据线。
在一些示例性实施方式中，所述第一半导体层、所述第二导电层、所述第二半导体层、所述第三导电层、所述第四导电层、所述第五导电层和所述第六导电层依次设置在所述衬底上。
在一些示例性实施方式中，所述显示岛区的第六导电层还包括：传输第一电压信号的电源传输线、传输第二电压信号的电源传输线、传输第一初始信号的初始传输线、以及传输第二初始信号的初始传输线。
在一些示例性实施方式中，显示基板还包括：位于所述第一显示区至少 一侧的第二显示区；所述第二显示区包括：设置在所述衬底上的第二像素单元，所述第二像素单元包括：第二区域像素电路和与所述第二区域像素电路电连接的第二区域发光元件；所述第二区域像素电路在所述衬底的正投影与电连接的所述第二区域发光元件在所述衬底的正投影存在交叠。其中，所述第一显示区的第一像素单元的密度小于所述第二显示区的第二像素单元的密度。
在一些示例性实施方式中，所述第二显示区的两行第二像素单元与所述第一显示区的一行第一像素单元对应，所述第二显示区的两列第二像素单元与所述第一显示区的一列第一像素单元对应。
在一些示例性实施方式中，所述第二显示区还包括：多条数据线，第2n行第j列的第二区域像素电路与第2n-1行第j列的第二区域像素电路连接不同的数据线，其中，n和j均为整数。
在一些示例性实施方式中，所述第一显示区还包括：像素定义层和位于所述像素定义层远离所述衬底一侧的黑矩阵。所述显示岛区的像素定义层具有像素开口，所述像素开口暴露出第一区域发光元件的阳极的部分；所述黑矩阵具有矩阵开口；所述矩阵开口在所述衬底的正投影覆盖所述像素开口在所述衬底的正投影，所述第一区域发光元件的阳极在所述衬底的正投影覆盖所述矩阵开口在所述衬底的正投影。
在一些示例性实施方式中，所述黑矩阵覆盖所述连接区。
另一方面，本实施例提供一种显示装置，包括如上所述的显示基板以及位于所述显示基板的非显示面一侧的传感器，所述传感器在所述显示基板的正投影与所述显示基板的第一显示区存在交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例， 目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为图2所示的像素电路的工作时序图；
图4为本公开至少一实施例的第一显示区的局部示意；
图5为本公开至少一实施例的第一显示区的另一局部示意图；
图6A至图6D为本公开至少一实施例的第一边缘的局部放大示意图；
图7A为本公开至少一实施例的第一显示区的第一区域发光元件和第一区域像素电路的排布示意图；
图7B为本公开至少一实施例的第二显示区的第二区域发光元件和第二区域像素电路的排布示意图；
图7C为图1中区域S1的局部示意图；
图8为本公开至少一实施例的显示区域的局部剖面示意图；
图9A为本公开至少一实施例的第一显示区形成第一导电层后的显示基板的局部放大示意图；
图9B为本公开至少一实施例的第二显示区形成第一导电层后的显示基板的局部放大示意图；
图10A为本公开至少一实施例的第一显示区形成第一半导体层后的显示基板的局部放大示意图；
图10B为本公开至少一实施例的第二显示区形成第一半导体层后的显示基板的局部放大示意图；
图11A为图10A中的第一半导体层的示意图；
图11B为图10B中的第一半导体层的示意图；
图12A为本公开至少一实施例的第一显示区形成第二导电层后的显示基板的局部放大示意图；
图12B为本公开至少一实施例的第二显示区形成第二导电层后的显示基板的局部放大示意图；
图13A为图12A中的第二导电层的示意图；
图13B为图12B中的第二导电层的示意图；
图14A为本公开至少一实施例的第一显示区形成第二半导体层后的显示基板的局部放大示意图；
图14B为本公开至少一实施例的第二显示区形成第二半导体层后的显示基板的局部放大示意图；
图15A为图14A中的第二半导体层的示意图；
图15B为图14B中的第二半导体层的示意图；
图16A为本公开至少一实施例的第一显示区形成第三导电层后的显示基板的局部放大示意图；
图16B为本公开至少一实施例的第二显示区形成第三导电层后的显示基板的局部放大示意图；
图17A为图16A中的第三导电层的示意图；
图17B为图16B中的第三导电层的示意图；
图18A为本公开至少一实施例的第一显示区形成第五绝缘层后的显示基板的局部放大示意图；
图18B为本公开至少一实施例的第二显示区形成第五绝缘层后的显示基板的局部放大示意图；
图19A为本公开至少一实施例的第一显示区形成第四导电层后的显示基板的局部放大示意图；
图19B为本公开至少一实施例的第二显示区形成第四导电层后的显示基板的局部放大示意图；
图20A为图19A中的第四导电层的示意图；
图20B为图19B中的第四导电层的示意图；
图21A为本公开至少一实施例的第一显示区形成第六绝缘层后的显示基板的局部放大示意图；
图21B为本公开至少一实施例的第二显示区形成第六绝缘层后的显示基 板的局部放大示意图；
图22A为本公开至少一实施例的第一显示区形成第五导电层后的显示基板的局部放大示意图；
图22B为本公开至少一实施例的第二显示区形成第五导电层后的显示基板的局部放大示意图；
图23A为图22A中的第五导电层的示意图；
图23B为图22B中的第五导电层的示意图；
图24A为本公开至少一实施例的第一显示区形成第七绝缘层后的显示基板的局部放大示意图；
图24B为本公开至少一实施例的第二显示区形成第七绝缘层后的显示基板的局部放大示意图；
图25A为本公开至少一实施例的第一显示区形成第六导电层后的显示基板的局部放大示意图；
图25B为本公开至少一实施例的第二显示区形成第六导电层后的显示基板的局部放大示意图；
图26A为图25A中的第六导电层的示意图；
图26B为图25B中的第六导电层的示意图；
图27A为本公开至少一实施例的第一显示区形成第八绝缘层后的显示基板的局部放大示意图；
图27B为本公开至少一实施例的第二显示区形成第八绝缘层后的显示基板的局部放大示意图；
图28A为本公开至少一实施例的第一显示区形成阳极层后的显示基板的局部放大示意图；
图28B为本公开至少一实施例的第二显示区形成阳极层后的显示基板的局部放大示意图；
图29A为图28A中的阳极层的示意图；
图29B为图28B中的阳极层的示意图；
图30A为本公开至少一实施例的第一显示区形成像素定义层后的显示基板的局部放大示意图；
图30B为本公开至少一实施例的第二显示区形成像素定义层后的显示基板的局部放大示意图；
图31为图30A中沿Q-Q’方向的局部剖面示意图；
图32A为本公开至少一实施例的第一显示区的局部示意图；
图32B为公开至少一实施例的第一显示区形成黑矩阵之后的显示基板的局部示意图；
图32C为图32B中的黑矩阵的示意图；
图33为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描 述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩 形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本公开中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
随着OLED技术的广泛发展和应用深入，对具有更优视觉体验的高屏占比显示屏和全面屏的追求已成为当前显示技术发展的潮流之一。例如，屏下指纹识别技术、“美人尖”等技术均极大地提升了显示屏的屏占比。然而，受限于多个膜层结构的透光性和阵列基板的金属走线的“纱窗效应”等对前置摄像头制造工艺的制约，显示产品的光透过率、显示效果和摄像效果均有待加强。
本公开实施例提供一种显示基板，包括：第一显示区。第一显示区包括：彼此隔开的多个显示岛区、位于相邻显示岛区之间的透光区以及连接相邻显示岛区的连接区。显示岛区包括：设置在衬底上的第一像素单元。第一像素单元包括：第一区域像素电路和与第一区域像素电路电连接的第一区域发光元件。第一区域像素电路在衬底的正投影与电连接的所述第一区域发光元件在衬底的正投影存在交叠。显示岛区具有弧形边缘。在一些示例中，显示岛区的边缘形状可以由显示岛区内的信号走线的排布和形态确定，或者，显示岛区的边缘形状可以由显示岛区设置的黑矩阵的边缘确定。然而，本实施例对此并不限定。
本实施例提供的显示基板，通过设置显示岛区的边缘为弧形，可以降低显示基板的光线衍射效果，从而提高显示装置的显示效果和拍摄效果。
在一些示例性实施方式中，显示岛区可以为圆形或椭圆形。然而，本实施例对此并不限定。在另一些示例中，显示岛区的边缘可以由多条弧线段连接形成。其中，多条弧线段的弧度可以相同，或者，多条弧线段中的部分弧线段的弧度可以相同，或者，多条弧线段的弧度可以不同。
在一些示例性实施方式中，透光区的边缘可以包括：与连接区接触的第一边缘、以及与显示岛区接触的第二边缘。第一边缘与第二边缘间隔连接。第二边缘为弧形。第一边缘与第二边缘之间没有形成直角，即，第一边缘和第二边缘均不是直角边，从而可以降低显示基板的光线衍射效果。
在一些示例中，透光区可以为八边形。例如，透光区可以由四个显示岛区和四个连接区围绕，从而形成八边形的透光区。
在一些示例中，透光区的第一边缘可以为直线型、波浪型或者折线型。例如，连接区可以为条状区域，连接区与相邻的显示岛区可以连通。透光区的第一边缘即为连接区靠近透光区的边缘，第一边缘可以为平坦边缘，或者，第一边缘可以是不平坦的，比如第一边缘可以包括以下至少一项：凸出部、凹陷部。类似地，连接区的第二边缘可以为弧形的平坦边缘，或者可以包括以下至少一项：凸出部、凹陷部。
在一些示例性实施方式中，一个显示岛区可以包括一个第一像素单元。第一像素单元可以包括：三个第一区域发光元件。所述三个第一区域发光元件可以包括：出射第一颜色光的第一发光元件、出射第二颜色光的第二发光元件、以及出射第三颜色光的第三发光元件。第一颜色光、第二颜色光和第三颜色光可以为不同颜色的光。例如，第一颜色光可以为绿光、第二颜色光可以为红光，第三颜色光可以为蓝光。然而，本实施例对此并不限定。本示例中通过在显示岛区设置一个独立的第一像素单元，可以平均分布第一像素单元，从而有效提升第一显示区的显示效果。
在一些示例性实施方式中，显示岛区的第一发光元件、第二发光元件和第三发光元件的发光区域的整体可以组成圆形或椭圆形。如此一来，可以保证透光区没有直角边，从而降低显示基板的衍射效果。在本公开中，发光元件的发光区域可以为发光元件位于像素定义层的像素开口的部分。
在一些示例性实施方式中，第一像素单元还可以包括：三个第一区域像 素电路。所述三个第一区域像素电路和所述三个第一区域发光元件一一对应电连接。所述三个第一区域像素电路可以沿第一方向依次排布。所述第一发光元件和第二发光元件可以在第二方向上依次排布，所述第三发光元件可以在所述第一方向上位于所述第一发光元件和第二发光元件的同一侧。其中，所述第一方向与所述第二方向交叉。例如，第一方向与第二方向相互垂直。
在一些示例性实施方式中，显示岛区还可以包括：多条数据线。显示岛区的第一区域像素电路与一条数据线电连接，且所述第一区域像素电路在衬底的正投影与两条数据线在衬底的正投影存在交叠。显示岛区的多条数据线中的至少一条数据线围绕在第一像素单元的全部第一区域像素电路的外侧。在本示例中，显示岛区的多条数据线可以被分成两组，第一组数据线可以穿过第一区域像素电路，第二组数据线可以绕过第一区域像素电路，从而可以减少数据线与第一区域像素电路之间的相互干扰。在一些示例中，在垂直于显示基板的方向上，第二组数据线可以位于第一组数据线远离衬底的一侧。
在一些示例性实施方式中，第一区域像素电路可以包括：至少一个第一类型晶体管、至少一个第二类型晶体管和存储电容，第一类型晶体管和第二类型晶体管的晶体管类型可以不同。例如，第一类型晶体管可以为P型晶体管，第二类型晶体管可以为N型晶体管。
在一些示例性实施方式中，显示基板还可以包括：位于第一显示区至少一侧的第二显示区。第二显示区可以包括：设置在衬底上的至少一个第二像素单元。第二像素单元可以包括：至少一个第二区域像素电路和至少一个第二区域发光元件；所述至少一个第二区域像素电路与所述至少一个第二区域发光元件电连接，且所述至少一个第二区域像素电路在所述衬底的正投影与所述至少一个第二区域发光元件在所述衬底的正投影存在交叠。其中，第一显示区的第一像素单元的密度可以小于第二显示区的第二像素单元的密度。本示例的显示基板可以保证第一显示区的光透过率。
在一些示例性实施方式中，第二显示区的两行第二像素单元与第一显示区的一行第一像素单元可以对应，第二显示区的两列第二像素单元与第一显示区的一列第一像素单元可以对应。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA外围的周边区域BB。显示基板的显示区域AA可以包括：第一显示区A1和第二显示区A2。第二显示区A2可以位于第一显示区A1的至少一侧。例如，第一显示区A1可以位于显示区域AA的顶部正中间位置，第二显示区A2可以围绕在第一显示区A1的四周。然而，本实施例对此并不限定。例如，第一显示区A1可以位于显示区域AA的左上角或者右上角等其他位置。
在一些示例中，第一显示区A1还可以称为屏下摄像头(UDC，Under Display Camera)区域，第二显示区A2还可以称为正常显示区。例如，传感器(比如，摄像头、红外传感器)等硬件在显示基板上的正投影可以位于显示基板的第一显示区A1内。在一些示例中，如图1所示，第一显示区A1可以为圆形，传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的尺寸。然而，本实施例对此并不限定。在另一些示例中，第一显示区A1可以为矩形，传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的内切圆的尺寸。
在一些示例中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。第一显示区A1可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第一显示区A1可以为矩形、五边形、或六边形等其他形状。
在一些示例中，显示区域AA可以是平坦的区域，显示区域AA至少可以包括规则排布的多个像素单元。多个像素单元可以被配置为显示动态图片或静止图像。在一些示例中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在另一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，至少一个子像素可以包括像素电路和发光元件。像素电路可以配置为驱动所连接的发光元件。例如，像素电路可以配置为提供驱动电流以驱动发光元件发光。像素电路可以包括多个晶体管和至少一个电容， 例如，像素电路可以为3T1C(3个晶体管和1个电容)结构、8T1C(8个晶体管和1个电容)结构、7T1C(7个晶体管和1个电容)结构或者5T1C(5个晶体管和1个电容)结构。在一些示例中，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件的发光颜色可根据需要而定。发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例中，发光元件的形状可以为矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，像素电路可以包括：至少一个第一类型晶体管、至少一个第二类型晶体管、以及存储电容。例如，第一类型晶体管可以为P型晶体管，第二类型晶体管可以为N型晶体管。例如，第一类型晶体管可以为低温多晶硅薄膜晶体管，第二类型晶体管可以为氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层可以采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层可以采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPS+Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。在一些示例中，像素电路可以为8T1C结构，即可以包括第一晶体管T1至第八晶体管T8以及存储电容Cst。其中，第一晶体管T1至第七晶体管T7可以为第一类型晶体管，例如可以为P型晶体管，第八晶体管T8可以为第二类型晶体管，例如可以为N型晶体管。然而，本实施例对此并不限定。例如，像素电路的多个晶体管可以均是P型晶体管，或者可以均是N型晶体管。
在一些示例中，第一类型晶体管(例如，第一晶体管T1至第七晶体管T7)可以采用低温多晶硅薄膜晶体管，第二类型晶体管(例如，第八晶体管T8)可以采用氧化物薄膜晶体管。然而，本实施例对此并不限定。例如，像素电路的多个晶体管可以均采用低温多晶硅薄膜晶体管，或者，均采用氧化物薄膜晶体管。
在一些示例中，如图2所示，像素电路可以分别与十个信号线(例如包括：数据线DL、第一电源线VDD、第二电源线VSS、第一扫描信号线GL1、第二扫描信号线GL2、第三扫描信号线RST1、第四扫描信号线RST2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2)电连接。
在一些示例中，第一电源线VDD可以配置为向像素电路提供恒定的第一电压信号，第二电源线VSS可以配置为向像素电路提供恒定的第二电压信号，并且第一电压信号可以大于第二电压信号。第一扫描信号线GL1可以配置为向像素电路提供第一扫描信号SCAN1，第二扫描信号线GL2可以配置为向像素电路提供第二扫描信号SCAN2，第三扫描信号线RST1可以配置为向像素电路提供第一复位控制信号RESET1，第四扫描信号线RST2可以配置为向像素电路提供第二复位控制信号RESET2。数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM。
在一些示例中，在第n行像素电路中，第三扫描信号线RST1可以与第n-1行像素电路的第一扫描信号线GL1连接，以被输入第一扫描信号SCAN1(n-1)，即第一复位控制信号RESET1(n)与第一扫描信号SCAN1(n-1)可以相同。在一些示例中，第n行像素电路所电连接的第四扫描信号线RST2与第n行像素电路所电连接的第三扫描信号线RST1可以为一体结构。即，第一复位控制信号RESET1(n)与第二复位控制信号RESET2(n)可以相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电源线VDD提供的第一电压 信号和第二电源线VSS提供的第二电压信号之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些示例中，如图2所示，第三晶体管T3的栅极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第三晶体管T3可以称为驱动晶体管。第四晶体管T4的栅极与第一扫描信号线GL1电连接，第四晶体管T4的第一极与数据线DL电连接，第四晶体管T4的第二极与第二节点N2电连接。第四晶体管T4可以称为数据写入晶体管。第二晶体管T2的栅极与第一扫描信号线GL1电连接，第二晶体管T2的第一极与第五节点N5电连接，第二晶体管T2的第二极与第三节点N3电连接。第二晶体管T2可以称为阈值补偿晶体管。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第二节点N2电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接。第五晶体管T5和第六晶体管T6可以称为发光控制晶体管。第一晶体管T1的栅极与第三扫描信号线RST1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第五节点N5电连接。第七晶体管T7的栅极与第四扫描信号线RST2电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与第四节点N4电连接。第一晶体管T1和第七晶体管T7可以称为复位控制晶体管。第八晶体管T8的栅极与第二扫描信号线GL2电连接，第八晶体管T8的第一极与第五节点N5电连接，第八晶体管T8的第二极与第一节点N1电连接。存储电容Cst的第一电容极板与第一节点N1电连接，存储电容Cst的第二电容极板与第一电源线VDD电连接。
在本示例中，第一节点N1为存储电容Cst、第八晶体管T8和第三晶体管T3的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件 EL的连接点，第五节点N5为第一晶体管T1、第二晶体管T2和第八晶体管T8的连接点。
在一些示例中，发光元件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。发光元件EL的第二极可以与第二电源线VSS电连接。第二电源线VSS的信号可以为持续提供的低电平信号，第一电源线VDD的信号可以为持续提供的高电平信号。
图3为图2所示的像素电路的工作时序图。下面参照图3对图2所示的像素电路的工作过程进行说明。其中，以像素电路的第一晶体管T1至第七晶体管T7为P型晶体管，第八晶体管T8为N型晶体管为例进行说明。其中，像素电路所电连接的第三扫描信号线RST1提供的第一复位控制信号RESET1和第四扫描信号线RST2提供的第二复位控制信号RESET2可以相同。
在一些示例中，如图2和图3所示，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段t1、第二阶段t2和第三阶段t3。
第一阶段t1，称为复位阶段。第三扫描信号线RST1提供的第一复位控制信号RESET1为低电平信号，使第一晶体管T1和第七晶体管T7导通，第二扫描信号线GL2提供的第二扫描信号SCAN2为高电平信号，使第八晶体管T8导通。第一初始信号线INIT1提供的第一初始信号被提供至第五节点N5和第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。第二初始信号线INIT2提供的第二初始信号被提供至第四节点N4，对第四节点N4进行初始化。第一扫描信号线GL1提供的第一扫描信号SCAN1为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、以及第六晶体管T6断开。此阶段发光元件EL不发光。
第二阶段t2，称为数据写入阶段或者阈值补偿阶段。第一扫描信号线GL1提供的第一扫描信号SCAN1为低电平信号，第二扫描信号线GL2提供的第二扫描信号SCAN2、第三扫描信号线RST1提供的第一复位控制信号RESET1以及发光控制线EML提供的发光控制信号EM均为高电平信号，数 据线DL输出数据信号DATA。此阶段由于存储电容Cst的第一电容极板为低电平，因此，第三晶体管T3导通。第一扫描信号SCAN1为低电平信号，使第二晶体管T2和第四晶体管T4导通。第二晶体管T2、第四晶体管T4和第八晶体管T8导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2、第五节点N5和导通的第八晶体管T8提供至第一节点N1，并将数据线DL输出的数据电压Vdata与第三晶体管T3的阈值电压Vth之差充入存储电容Cst。第三扫描信号线RST1提供的第一复位控制信号RESET1为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光控制线EML提供的发光控制信号EM为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段t3，称为发光阶段。发光控制线EML提供的发光控制信号EM由高电平变为低电平信号，发光控制信号EM为低电平信号可以使第五晶体管T5和第六晶体管T6导通。第二扫描信号线GL2提供的第二扫描信号SCAN2为低电平信号，使第八晶体管T8断开。第一扫描信号线GL1提供的第一扫描信号SCAN1和第三扫描信号线RST1提供的第一复位控制信号RESET1为高电平信号，使第二晶体管T2、第四晶体管T4、第七晶体管T7以及第一晶体管T1断开。第一电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过第三晶体管T3的驱动电流由其控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流可以为：
I＝K×(Vgs-Vth) 2＝K×[(Vdd-Vdata+|Vth|)-Vth] 2＝K×[Vdd-Vdata] 2；
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，Vdd为第一电源线VDD输出的第一电压信号。
由上式可以看到流经发光元件的电流与第三晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿第三晶体管T3的阈值电压。
图4为本公开至少一实施例的第一显示区的局部示意图。在一些示例中，如图4所示，在平行于显示基板的平面内，第一显示区A1可以包括：彼此隔开的多个显示岛区A11、位于相邻显示岛区A11之间的透光区A12、以及连接相邻显示岛区A11的连接区A13。每个显示岛区A11可以配置为进行图像显示，每个透光区A12可以配置为提供光线透射空间，每个连接区A13可以配置为设置信号走线。
在一些示例中，如图4所示，在平行于显示基板的平面内，多个显示岛区A11的形状可以大致相同，例如均为圆形。多个连接区A13可以将多个显示岛区A11互相连接。连接区A13可以为沿第一方向X或第二方向Y延伸的条形区域。例如，每个显示岛区A13可以连接有四个连接区A13。连接至一个显示岛区A11的四个连接区A13可以在不同的方向上延伸。比如，其中两个连接区A13可以沿第一方向X延伸，另两个连接区A13可以沿第二方向Y延伸。第一方向X和第二方向Y交叉，例如第一方向X和第二方向Y可以相互垂直。一个显示岛区A11可以通过四个连接线A13与围绕在该显示岛区A11周围的四个其他显示岛区连接。然而，本实施例对此并不限定。在另一些示例中，显示岛区可以为椭圆形；或者，显示岛区可以为不具有直角边的其他形状。在另一些示例中，多个显示岛区的形状可以不相同。
在一些示例中，如图4所示，在平行于显示基板的平面内，多个透光区A12的形状可以大致相同，例如，可以均为八边形。一个透光区A12可以由四个连接区A13和四个显示岛区A11围绕。透光区A12的边缘可以包括：与连接区A13接触的第一边缘A12-1、与显示岛区A11接触的第二边缘A12-2。第一边缘A12-1和第二边缘A12-2间隔连接。第一边缘A12-1为连接区A13靠近透光区A12的边缘。第一边缘A12-1可以为平坦边缘，例如可以为直线型。第二边缘A12-2为显示岛区A11靠近透光区A12的边缘。第二边缘A12-2可以为弧形。第二边缘A12-2可以为弧形的平坦边缘，或者可以是不平坦边缘，比如存在公差导致的一些小变形。在本示例中，透光区A12的第一边缘A12-1和第二边缘12-2连接不会形成直角边缘，可以降低光线衍射效果，例如，可以有利于降低显示基板的第一显示区下方的摄像头在拍摄时的衍射，从而提高拍摄效果。
图5为本公开至少一实施例的第一显示区的另一局部示意图。在一些示例中，如图5所示，在平行于显示基板的平面内，透光区A12的第二边缘A12-2可以为弧形。透光区A12的第一边缘A12-1可以为不平坦边缘。在本示例中，透光区A12的第一边缘A12-1和第二边缘12-2连接不会形成直角边缘，可以降低光线衍射效果。
图6A至图6D为本公开至少一实施例的第一边缘的局部放大示意图。在一些示例中，如图6A所示，在平行于显示基板的平面内，透光区的第一边缘A12-1可以为波浪型。第一边缘A12-1可以由连续的多个弧线段连接形成。例如，第一边缘A12-1可以包括间隔连接的凸出部和凹陷部，且凸出部和凹陷部可以为半圆形或半椭圆形。在另一些示例中，如图6B所示，透光区的第一边缘A12-1可以为折线型。第一边缘A12-1可以由连续的多个直线段连接形成。例如，第一边缘A12-1可以包括间隔连接的凸出部和凹陷部，且凸出部和凹陷部可以为三角形。在另一些示例中，如图6C所示，透光区的第一边缘A12-1可以包括多个凸出部，且凸出部可以为半圆形或半椭圆形。第一边缘A12-1可以由弧线端和直线段间隔连接形成。在另一些示例中，如图6D所示，透光区的第一边缘A12-1可以包括多个凸出部，且凸出部可以为三角形。第一边缘A12-1可以由倾斜方向不同的多个直线段连接形成。然而，本实施例对此并不限定。在另一些示例中，凸出部或凹陷部可以为四边形或五边形。在另一些示例中，透光区的第二边缘可以为不平坦边缘，比如具有凸出部或凹陷部。在第二边缘确保弧形形状的基础上，第二边缘的非平坦形状可以与第一边缘的非平坦形状类似，故于此不再赘述。
在一些示例中，透光区的第二边缘的形状可以由显示岛区内信号走线的外围边缘形状确定。透光区的第一边缘的形状可以由连接区的信号走线(例如遮光走线)的外围边缘形状确定。然而，本实施例对此并不限定。在另一些示例中，透光区的第一边缘和第二边缘的形状可以由黑矩阵的外围边缘形状确定。黑矩阵可以覆盖显示岛区的非发光区域和连接区。
在一些示例中，第一显示区A1可以包括：多个第一区域发光元件和多个第一区域像素电路。至少一个第一区域像素电路与至少一个第一区域发光元件电连接。例如，多个第一区域像素电路与多个第一区域发光元件可以一 一对应电连接。至少一个第一区域像素电路在衬底的正投影与电连接的至少一个第一区域发光元件在衬底的正投影可以至少部分交叠。
在一些示例中，第二显示区A2可以包括：多个第二区域发光元件和多个第二区域像素电路。至少一个第二区域像素电路与至少一个第二区域发光元件电连接。例如，多个第二区域发光元件与多个第二区域像素电路可以一一对应电连接。至少一个第二区域像素电路在衬底的正投影与电连接的至少一个第二区域发光元件在衬底的正投影可以至少部分交叠。
图7A为本公开至少一实施例的第一显示区的第一区域发光元件和第一区域像素电路的排布示意图。在一些示例中，如图7A所示，一个显示岛区A11可以包括一个第一像素单元P1。第一像素单元P1可以包括：三个出射不同颜色光的第一子像素，每个第一子像素可以包括：一个第一区域像素电路13和一个第一区域发光元件11。在本示例中，显示岛区A11的三个第一区域发光元件11可以包括：出射第一颜色光的第一发光元件11a、出射第二颜色光的第二发光元件11b、以及出射第三颜色光的第三发光元件11c。显示岛区A11的三个第一区域像素电路13可以包括：与第一发光元件11a电连接的第一像素电路13a、与第二发光元件11b电连接的第二像素电路13b、以及与第三发光元件11c电连接的第三像素电路13c。第一发光元件11a可以被配置为在第一像素电路13a的驱动下发光，第二发光元件11b可以被配置为在第二像素电路13b的驱动下发光，第三发光元件11c可以被配置为在第三像素电路13c的驱动下发光。第一发光元件11a在衬底的正投影与第一像素电路13a在衬底的正投影可以存在交叠，第二发光元件11b在衬底的正投影与第二像素电路13b在衬底的正投影可以存在交叠，第三发光元件11c在衬底的正投影与第三像素电路13c在衬底的正投影可以存在交叠。本示例中，在每个显示岛区A11设置独立的一个第一像素单元，而非多个第一像素单元聚集设置，可以使得像素单元分布更均匀，从而有效提升显示效果。
在一些示例中，第一颜色光可以为绿光，第二颜色光可以为红光，第三颜色光可以为蓝光。然而，本实施例对此并不限定。
在一些示例中，如图7A所示，显示岛区A11内的三个第一区域发光元件11可以呈品字形排布。其中，显示岛区A11内的第二发光元件11b和第 一发光元件11a可以沿第二方向Y依次排布，第三发光元件11c可以在第一方向X上位于第一发光元件11a和第二发光元件11c的同一侧。显示岛区A11内的三个第一区域像素电路13可以沿第一方向X并排设置。其中，显示岛区A11内的第一像素电路13a、第二像素电路13b和第三像素电路13c可以沿第一方向X依次排布。
在一些示例中，如图7A所示，显示岛区A11的第一发光元件11a可以具有第一发光区域，第二发光元件11b可以具有第二发光区域，第三发光元件11c可以具有第三发光区域。第一发光区域、第二发光区域和第三发光区域在整体上可以组合呈圆形。例如，第一发光元件11a的第一发光区域可以由两条直线边缘和一条弧线边缘围绕，且两条直线边缘可以相互垂直。第二发光元件11b的第二发光区域可以由两条直线边缘和一条弧线边缘围绕，且两条直线边缘可以相互垂直。第三发光元件11c的第三发光区域可以由一条直线边缘和一条弧线边缘围绕。例如，第一发光区域可以小于第二发光区域。第一发光区域和第二发光区域的形状可以类似四分之一圆形，第三发光区域的形状可以类似半圆形。
图7B为本公开至少一实施例的第二显示区的第二区域发光元件和第二区域像素电路的排布示意图。在一些示例中，如图7B所示，第二显示区A2可以包括多个规则排布的第二像素单元P2。第二像素单元P2可以包括：三个出射不同颜色光的第二子像素。每个第二子像素可以包括：一个第二区域像素电路14和一个第二区域发光元件12。在本示例中，第二显示区A2的一个第二像素单元P2的三个第二区域发光元件12可以包括：出射第一颜色光的第四发光元件12a、出射第二颜色光的第五发光元件12b、以及出射第三颜色光的第六发光元件12c。第二显示区A2的三个第二区域像素电路14可以包括：与第四发光元件12a电连接的第四像素电路14a、与第五发光元件12b电连接的第五像素电路14b、以及与第六发光元件12c电连接的第六像素电路14c。第四发光元件12a可以被配置为在第四像素电路14a的驱动下发光，第五发光元件12b可以被配置为在第五像素电路14b的驱动下发光，第六发光元件12c可以被配置为在第六像素电路14c的驱动下发光。第四发光元件12a在衬底的正投影与第四像素电路14a在衬底的正投影可以存在交叠，第 五发光元件12b在衬底的正投影与第五像素电路14b在衬底的正投影可以存在交叠，第六发光元件12c在衬底的正投影与第六像素电路14c在衬底的正投影可以存在交叠。
在一些示例中，如图7B所示，第二像素单元P2的三个第二区域发光元件12可以呈品字形排布。其中，第五发光元件12b和第四发光元件12a可以沿第二方向Y依次排布，第六发光元件12c可以在第一方向X上位于第四发光元件12a和第五发光元件12b的同一侧。第二像素单元P2的三个第二区域像素电路14可以沿第一方向X并排设置。其中，第四像素电路14a、第五像素电路14b和第六像素电路14c可以沿第一方向X依次排布。
在一些示例中，如图7B所示，第二像素单元P2的第四发光元件12a可以具有第四发光区域，第五发光元件12b可以具有第五发光区域，第六发光元件12c可以具有第六发光区域。第四发光区域、第五发光区域和第六发光区域在整体上可以组合呈矩形。例如，第四发光区域、第五发光区域和第六发光区域可以均为矩形。比如，第四发光区域可以小于第五发光区域。
图7C为图1中区域S1的局部示意图。图7C示意了第一显示区A1和第二显示区A2的交界处的发光元件和像素电路的排布。在一些示例中，如图7C所示，第一显示区A1的第一像素单元P1的密度可以小于第二显示区A2的第二像素单元P2的密度。第一显示区A1的第一区域发光元件11的密度可以小于第二显示区A2的第二区域发光元件12的密度。如此一来，可以提高第一显示区A1的光透过率。
在一些示例中，如图7C所示，第二显示区A2内的两行第二像素单元P2可以对应第一显示区A1内的一行第一像素单元P1，第二显示区A2内的两列第二像素单元P2可以对应第一显示区A1内的一列第一像素单元P1。
在本公开中，一行A可以表示沿第一方向X排布的多个A，一列A可以表示沿第二方向Y排布的多个A。
在一些示例中，如图7C所示，第一显示区A1内的第一区域像素电路13和第二显示区A2的第二区域像素电路14可以均为图2所示的8T1C结构。在第二显示区A2内，第2n行第j列的第二区域像素电路和第2n-1行第j列的第二区域像素电路可以电连接不同的数据线。第2n行第j列的第二区域像 素电路和第2n-1行第j列的第二区域像素电路接收的第一扫描信号、第二扫描信号、第一复位控制信号、第二复位控制信号、发光控制信号可以相同，并通过不同的数据线接收相同或不同的数据信号。其中，n和j均为正整数。例如，第二显示区A2内的第2n行和第2n-1行第二区域像素电路与第一显示区A1内的一行第一区域像素电路对应，第二显示区A2内的第2n行和第2n-1行第二区域像素电路和第一显示区A1内对应的一行第一区域像素电路可以接收相同的第一扫描信号、第二扫描信号、第一复位控制信号、第二复位控制信号和发光控制信号。第二显示区A2内的第k-1列和第k列第二像素单元与第一显示区A1内的一列第一像素单元对应。第k-1列和第k列第二像素单元一共包括六列第二区域像素电路，由于奇数行和偶数行的第二区域像素电路连接不同的数据线，六列第二区域像素电路可以与十二条数据线电连接，所述第十二条数据线中的六条数据线(例如，沿第一方向排布的第四条至第九条数据线)可以穿过对应的一列第一像素单元(例如包括三列第一区域像素电路)，其余六条数据线(例如，沿第一方向排布的第一条至第三条数据线以及第十条数据线至第十二条数据线)可以绕过该列第一像素单元排布。其中，k为正整数。本示例中，通过设置第二显示区内的奇数行和偶数行的第二区域像素电路连接不同的数据线，可以保证数据信号较好地匹配第二区域像素电路的寄生电容，从而提高显示效果。
图8为本公开至少一实施例的显示区域的局部剖面示意图。在一些示例中，在垂直于显示基板的方向上，显示基板可以包括：衬底101、依次设置在衬底101上的驱动电路层102、发光结构层103以及封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层、彩色滤光层等，本公开在此不做限定。
在一些示例中，衬底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括位于第二显示区A2的多个第二区域像素电路和位于第一显示区A1的多个第一区域像素电路。发光结构层103可以包括位于第一显示区A1的多个第一区域发光元件和位于第二显示区A2的多个第二区域发光元件。例如，发光结构层103可以至少包括阳极层301、像素定义层302、有机发光层303和阴极层304，阳极层301可以与驱动电路层的像素电路电 连接，有机发光层303与阳极层301连接，阴极层304与有机发光层303连接，有机发光层303在阳极层301和阴极层304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在一些示例中，驱动电路层102可以包括：依次设置在衬底101上的第一导电层、第一半导体层、第二导电层、第二半导体层、第三导电层、第四导电层、第五导电层和第六导电层。在一些示例中，驱动电路层102还可以包括：第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、第六绝缘层、第七绝缘层和第八绝缘层。其中，第一绝缘层可以设置在第一导电层和第一半导体层之间，第二绝缘层可以设置在第一半导体层和第二导电层之间，第三绝缘层可以设置在第二导电层和第二半导体层之间，第四绝缘层可以设置在第二半导体层和第三导电层之间，第五绝缘层可以设置在第三导电层和第四导电层之间，第六绝缘层可以设置在第四导电层和第五导电层之间，第七绝缘层可以设置在第五导电层和第六导电层之间，第八绝缘层可以设置在第六导电层远离衬底的一侧。在一些示例中，第一绝缘层至第五绝缘层可以为无机绝缘层，第六绝缘层至第八绝缘层可以为有机绝缘层。然而，本实施例对此并不限定。
下面参照图9A至图30B对显示基板的结构和制备过程进行示例性说明。在下述示例中，以第一显示区A1的一个显示岛区的第一像素单元和第二显示区A2的一个第二像素单元为例进行示意，且第二显示区A2的该第二像素单元所在行和下一行的第二像素单元可以与该第一像素单元所在行对应。
本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或 多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、提供衬底。在一些示例中，衬底可以为刚性基底或者柔性基底。例如，刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些示例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用硅氮化物(SiNx)或硅氧化物(SiOx)等，用于提高衬底的抗水氧能力。
(2)、形成第一导电层。在一些示例中，在衬底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成第一导电层。在一些示例中，第一导电层还可以称为光遮挡(LS，Light Shielding)层。
图9A为本公开至少一实施例的第一显示区形成第一导电层后的显示基板的局部放大示意图。在一些示例中，如图9A所示，第一显示区的单个显示岛区的第一导电层可以至少包括：第一遮挡走线211、第二遮挡走线212。第一遮挡走线211可以沿第一方向X延伸，且可以沿第一方向X延伸至显示岛区在第一方向X两侧的连接区。第二遮挡走线212可以沿第二方向Y延伸， 且可以沿第二方向Y延伸至显示岛区在第二方向Y两侧的连接区。第一遮挡走线211和第二遮挡走线212可以为一体结构。第一显示区的相邻显示岛区的第一遮挡走线211可以为一体结构，相邻显示岛区的第二遮挡走线212可以为一体结构。在第一显示区内，第一遮挡走线211和第二遮挡走线212可以连接形成网状结构。
在一些示例中，如图9A所示，第一遮挡走线211可以包括：三个第一遮挡部2111和三个第二遮挡部2112。第一遮挡部2111可以从第一遮挡走线211的主体部分沿第二方向Y向外延伸，第二遮挡部2112可以从第一遮挡部2111沿第二方向Y向外延伸。第一遮挡部2111在衬底的正投影可以为矩形，例如可以为圆角矩形。第二遮挡部2112在衬底的正投影可以为L字型。沿第一方向X排布的第二个第一遮挡部2111和第二个第二遮挡部2112可以与第二遮挡走线212电连接。
图9B为本公开至少一实施例的第二显示区形成第一导电层后的显示基板的局部放大示意图。在一些示例中，如图9B所示，第二显示区的第一导电层可以包括：第三遮挡走线213和第四遮挡走线214。第三遮挡走线213可以沿第一方向X延伸，且多个第三遮挡走线213可以沿第二方向Y依次排布。第四遮挡走线214沿第二方向Y延伸，且多个第四遮挡走线214可以沿第一方向X依次排布。第三遮挡走线213可以包括：第三遮挡部2131，第三遮挡部2131可以沿第二方向Y从第三遮挡走线213的主体部分向外延伸。第三遮挡部2131在衬底的正投影可以为矩形，例如圆角矩形。第三遮挡部2131与第四遮挡走线214电连接。第三遮挡走线213和第四遮挡走线214可以为一体结构。在第二显示区内，第三遮挡走线213和第四遮挡走线214可以连接形成网状结构。
在一些示例中，第二显示区的第三遮挡走线213可以与第一显示区的第一遮挡走线211电连接，例如可以为一体结构。第二显示区的第四遮挡走线214可以与第一显示区的第二遮挡走线212电连接，例如可以为一体结构。
在一些示例中，第一遮挡走线211、第二遮挡走线212、第三遮挡走线213和第四遮挡走线214可以与第一电源线电连接。例如，第一遮挡走线211和第三遮挡走线213可以沿第一方向X延伸至周边区域，并与周边区域的第 一电源线电连接。又如，第二遮挡走线212和第四遮挡走线214可以沿第二方向X延伸至周边区域，并与周边区域的第一电源线电连接。然而，本实施例对此并不限定。
在一些示例中，第一显示区的至少一个连接区的第一导电层可以包括：第一遮挡走线211或第二遮挡走线212。
(2)、形成第一半导体层。在一些示例中，在形成前述图案的衬底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成设置在衬底上的第一绝缘层和第一半导体层。在一些示例中，第一半导体层的材料可以采用非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料。
图10A为本公开至少一实施例的第一显示区形成第一半导体层后的显示基板的局部放大示意图。图11A为图10A中的第一半导体层的示意图。在一些示例中，如图10A和图11A所示，第一显示区的单个显示岛区的第一半导体层可以包括：三个第一区域像素电路(例如包括沿第一方向X依次排布的第一像素电路、第二像素电路和第三像素电路)的第一晶体管31的第一有源层310至第七晶体管37的第七有源层37。一个第一区域像素电路的第一晶体管31的第一有源层310至第七晶体管37的第七有源层370可以为相互连接的一体结构。
在一些示例中，如图11A所示，以第一像素电路的第一晶体管31的第一有源层310至第七晶体管37的第七有源层370为例进行说明。第一像素电路的第一有源层310、第二有源层320和第四有源层340可以位于第一像素电路的第三有源层330的第二方向Y的一侧，第五有源层350、第六有源层360和第七有源层370可以位于第一像素电路的第三有源层330的第二方向Y的另一侧。
在一些示例中，如图11A所示，第一像素电路的第一有源层310、第二有源层320、第四有源层340、第五有源层350、第六有源层360和第七有源层370的形状可以均为I字型。第三有源层330的形状可以为n字型。然而，本实施例对此并不限定。
在一些示例中，如图11A所示，第一像素电路的第一晶体管31的有源 层310至第七晶体管37的有源层370可以各自包括：第一区、第二区以及位于第一区和第二区之间的沟道区。第一有源层310的第一区310-1、第四有源层340的第一区340-1、第五有源层350的第一区350-1和第七有源层370的第一区370-1可以单独设置。第一有源层310的第二区310-2可以同时作为第二有源层320的第一区320-1。第二有源层320的第二区320-2可以同时作为第三有源层330的第二区330-2和第六有源层360的第一区360-1。第三有源层330的第一区330-1可以同时作为第四有源层340的第二区340-2和第五有源层350的第二区350-2。第六有源层360的第二区360-2可以同时作为第七有源层370的第二区370-2。
在一些示例中，如图10A所示，第一遮挡走线211的一个第一遮挡部2111在衬底的正投影可以覆盖第一像素电路的第三晶体管的第三有源层330的沟道区在衬底的正投影。第一遮挡走线211的一个第二遮挡部2112在衬底的正投影可以覆盖第一像素电路的第二晶体管的第二有源层320的沟道区在衬底的正投影。类似地，第一遮挡走线211在衬底的正投影还可以覆盖第二像素电路和第三像素电路的第三晶体管的第三有源层的沟道区和第二晶体管的第二有源层的沟道区在衬底的正投影。
图10B为本公开至少一实施例的第二显示区形成第一半导体层后的显示基板的局部放大示意图。图11B为图10B中的第一半导体层的示意图。在一些示例中，如图10B和图11B所示，第二显示区的第二导电层可以包括：多个第二区域像素电路(例如包括：沿第一方向X依次排布的第四像素电路、第五像素电路和第六像素电路)的第一晶体管41的第一有源层410至第七晶体管47的第七有源层470。一个第二区域像素电路的第一晶体管41的第一有源层410至第七晶体管47的第七有源层470可以为相互连接的一体结构。在本示例中，以一行第二区域像素电路的第一晶体管41至第六晶体管46以及上一行第二区域像素电路的第七晶体管47为例进行示意。
在一些示例中，如图11B所示，以第四像素电路的第一晶体管41的第一有源层410至第七晶体管47的第七有源层470为例进行说明。第四像素电路的第一有源层410、第二有源层420和第四有源层440可以位于第四像素电路的第三有源层430的第二方向Y的一侧，第五有源层450、第六有源层 460和第七有源层470可以位于第四像素电路的第三有源层430的第二方向Y的另一侧。
在一些示例中，如图11B所示，第四像素电路的第一有源层410、第四有源层440、第五有源层450和第七有源层470的形状可以均为I字型。第二有源层420的形状可以为L字型。第六有源层460的形状可以为折线型。第三有源层430的形状可以为n字型。然而，本实施例对此并不限定。
在一些示例中，如图11B所示，第四像素电路的第一晶体管41的有源层410至第七晶体管47的有源层470可以各自包括：第一区、第二区以及位于第一区和第二区之间的沟道区。第一有源层410的第一区410-1、第四有源层440的第一区440-1、第五有源层450的第一区450-1和第七有源层470的第一区470-1可以单独设置。第一有源层410的第二区410-2可以同时作为第二有源层420的第一区420-1。第二有源层420的第二区420-2可以同时作为第三有源层430的第二区430-2和第六有源层460的第一区460-1。第三有源层430的第一区430-1可以同时作为第四有源层440的第二区440-2和第五有源层450的第二区450-2。第六有源层460的第二区460-2可以同时作为第七有源层470的第二区470-2。
在一些示例中，如图10B所示，第三遮挡走线213的一个第三遮挡部2131在衬底的正投影可以覆盖第四像素电路的第三晶体管的第三有源层430的沟道区在衬底的正投影。类似地，第三遮挡走线213在衬底的正投影还可以覆盖第五像素电路和第六像素电路的第三晶体管的第三有源层的沟道区在衬底的正投影。
在一些示例中，在形成第一半导体层后，第一显示区的连接区可以包括：衬底以及依次设置在衬底上的第一导电层和第一绝缘层。第一显示区的透光区可以包括：衬底、以及设置在衬底上的第一绝缘层。
(3)、形成第二导电层。在一些示例中，在形成前述图案的衬底上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一半导体层的第二绝缘层以及设置在第二绝缘层上的第二导电层。在一些示例中，第二导电层还可以称为第一栅金属层。
图12A为本公开至少一实施例的第一显示区形成第二导电层后的显示基 板的局部放大示意图。图13A为图12A中的第二导电层的示意图。在一些示例中，如图12A和图13A所示，第一显示区的单个显示岛区的第二导电层可以包括：三个第一区域像素电路(即第一像素电路至第三像素电路)的第一晶体管31至第七晶体管37的栅极、存储电容的第一电容极板391、发光控制线EML(n)、第五遮挡走线221以及多条数据连接线(例如包括：第一数据连接线521、第二数据连接线522、第五数据连接线525、第六数据连接线526、第十五数据连接线535和第十六数据连接线536)。
在一些示例中，如图13A所示，以第一像素电路为例，第一像素电路的第一晶体管31的栅极311和第七晶体管37的栅极371在衬底的正投影可以大致相同，例如大致为钥匙形状。第二晶体管32的栅极321在衬底的正投影可以大致为U字型。一个第一区域像素电路的第四晶体管34的栅极341与相邻的第一区域像素电路的第二晶体管32的栅极321可以为一体结构。例如，显示岛区的第一像素电路的第四晶体管34的栅极341与第二像素电路的第二晶体管的栅极可以为一体结构，第二像素电路的第四晶体管的栅极、第三像素电路的第二像素电路的栅极以及第三像素电路的第四晶体管的栅极可以为一体结构。如此一来，可以合理节省排布空间。第一像素电路的第三晶体管33的栅极331与存储电容的第一电容极板391可以为一体结构，例如可以为圆角矩形。第一像素电路至第三像素电路的第五晶体管35的栅极351和第六晶体管36的栅极361、以及发光控制线EML(n)可以为一体结构。发光控制线EML(n)可以在显示岛区在第二方向Y上绕过存储电容的第一电容极板391，并沿第一方向X延伸至显示岛区两侧的连接区。
在一些示例中，如图13A所示，第五遮挡走线221可以在显示岛区内沿第一方向X延伸。第五遮挡走线221在第二方向Y上可以位于第一像素电路的第一晶体管31的栅极311和第二晶体管32的栅极321之间。
在一些示例中，如图13A所示，第一数据连接线521、第五数据连接线525和第十五数据连接线535可以在第二方向Y上位于第一晶体管31的栅极311远离第五遮挡走线221的一侧。第一数据连接线521、第五数据连接线525和第十五数据连接线535可以沿第一方向X依次排布。第一数据连接线521、第五数据连接线525和第十五数据连接线535可以在第二方向Y向远 离第一晶体管31的栅极311的一侧延伸至连接区。
在一些示例中，如图13A所示，第二数据连接线522、第六数据连接线526和第十六数据连接线536可以在第二方向Y上位于第七晶体管37的栅极371远离发光控制线EML(n)的一侧。第二数据连接线522、第六数据连接线526和第十六数据连接线536可以沿第一方向X依次排布。第二数据连接线522、第六数据连接线526和第十六数据连接线536可以在第二方向Y上向远离第七晶体管37的栅极371的一侧延伸至连接区。
在一些示例中，如图13A所示，第一数据连接线521、第二数据连接线522、第五数据连接线525、第六数据连接线526、第十五数据连接线535和第十六数据连接线536在衬底的正投影可以均大致为L字型。第一数据连接线521和第二数据连接线522可以关于显示岛区在第二方向Y上的中线大致对称，第五数据连接线525和第六数据连接线526可以关于显示岛区在第二方向Y上的中线大致对称，第十五数据连接线535和第十六数据连接线536可以关于显示岛区在第二方向Y上的中线大致对称。
图12B为本公开至少一实施例的第二显示区形成第二导电层后的显示基板的局部放大示意图。图13B为图12B中的第二导电层的示意图。在一些示例中，如图12B和图13B所示，第二显示区的第二导电层可以包括：多个第二区域像素电路(例如第四像素电路至第六像素电路)的第一晶体管41至第七晶体管47的栅极、存储电容的第一电容极板491、发光控制线EML(n)、以及第六遮挡走线222。发光控制线EML(n)可以沿第一方向X延伸。发光控制线EML(n)与第五晶体管45的有源层450的交叠区域可以作为第五晶体管45的栅极，发光控制线EML(n)与第六晶体管46的有源层460的交叠区域可以作为第六晶体管46的栅极。一个第二区域像素电路的第二晶体管42的栅极421与相邻的第二区域像素电路的第四晶体管的栅极可以为一体结构。例如，第四像素电路的第二晶体管的栅极与第五像素电路的第四晶体管的栅极可以为一体结构，第五像素电路的第二晶体管的栅极与第六像素电路的第四晶体管的栅极可以为一体结构。第n行的第二区域像素电路的第一晶体管41的栅极411与上一行的第二区域像素电路的第七晶体管47的栅极可以为一体结构。第六遮挡走线222可以沿第一方向X延伸。第六遮挡走线222可以位 于第二晶体管42的栅极421和第三晶体管43的栅极431之间。
在一些示例中，发光控制线EML(n)可以从第一显示区经由连接区延伸至第二显示区，或者可以从第一显示区直接延伸至第二显示区。
在一些示例中，第一显示区的至少一个连接区的第二导电层可以包括：沿第一方向延伸的发光控制线。
在一些示例中，在形成第二导电层后，第一显示区的透光区可以包括：衬底、以及依次设置在衬底上的第一绝缘层和第二绝缘层。
(4)、形成第二半导体层。在一些示例中，在形成前述图案的衬底上，依次沉积第三绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖第二导电层的第三绝缘层以及设置在第三绝缘层上的第二半导体层。在一些示例中，第二半导体层的材料可以采用非晶态氧化铟镓锌材料(a-IGZO)、氧化铟镓锌材料(IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)等材料，即本公开适用于基于氧化物(Oxide)技术的晶体管。
图14A为本公开至少一实施例的第一显示区形成第二半导体层后的显示基板的局部放大示意图。图15A为图14A中的第二半导体层的示意图。在一些示例中，如图14A和图15A所示，第一显示区的单个显示岛区的第二半导体层可以包括：三个第一区域像素电路(即第一像素电路至第三像素电路)的第八晶体管38的第八有源层380。以第一像素电路为例，第一像素电路的第八有源层380可以包括：第一区380-1、第二区380-2以及位于第一区380-1和第二区380-2之间的沟道区。第八有源层380的形状可以为I字型。第五遮挡走线221在衬底的正投影与第一像素电路至第三像素电路的第八晶体管38的第八有源层380在衬底的正投影可以均存在交叠。
图14B为本公开至少一实施例的第二显示区形成第二半导体层后的显示基板的局部放大示意图。图15B为图14B中的第二半导体层的示意图。在一些示例中，如图14B和图15B所示，第二显示区的第二半导体层可以包括：多个第二区域像素电路(例如第四像素电路至第六像素电路)的第八晶体管48的第八有源层480。以第四像素电路为例，第八有源层480可以包括：第一区480-1、第二区480-2以及位于第一区480-1和第二区480-2之间的沟道 区。第八有源层480的形状可以为I字型。第六遮挡走线222在衬底的正投影与多个第二区域像素电路的第八晶体管48的第八有源层480在衬底的正投影均可以存在交叠。
在一些示例中，在形成第二半导体层之后，第一显示区的连接区可以包括：衬底、以及依次设置在衬底上的第一导电层、第一绝缘层、第二绝缘层、第二导电层和第三绝缘层。第一显示区的透光区可以包括：衬底、以及依次设置在衬底上的第一绝缘层、第二绝缘层和第三绝缘层。
(5)、形成第三导电层。在一些示例中，在形成前述图案的衬底上，依次沉积第四绝缘薄膜和第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，形成覆盖第二半导体层的第四绝缘层以及设置在第四绝缘层上的第三导电层。在一些示例中，第三导电层还可以称为第二栅金属层。
图16A为本公开至少一实施例的第一显示区形成第三导电层后的显示基板的局部放大示意图。图17A为图16A中的第三导电层的示意图。在一些示例中，如图16A和图17A所示，第一显示区的单个显示岛区的第三导电层可以包括：三个第一区域像素电路(即第一像素电路至第三像素电路)的第八晶体管38的栅极381和存储电容的第二电容极板392、第二扫描信号线GL2(n)、第一初始传输线611、第十一初始传输线631、以及多条数据连接线(例如包括：第三数据连接线523、第四数据连接线524、第十三数据连接线533、第十四数据连接线534、第十七数据连接线537和第十八数据连接线538)。
在一些示例中，如图16A和图17A所示，第二扫描信号线GL2(n)可以在显示岛区内沿第二方向Y绕过存储电容的第二电容极板392，并沿第一方向X延伸至显示岛区两侧的连接区。以第一像素电路为例，第一像素电路的第八晶体管38的栅极381与第二扫描信号线GL2(n)可以为一体结构。第一像素电路的存储电容的第二电容极板392可以具有第一镂空结构K1，第一镂空结构K1在衬底的正投影可以位于第一电容极板391在衬底的正投影范围内。第一初始传输线611和第十一初始传输线631可以位于显示岛区内，并沿第一方向X延伸。例如，第十一初始传输线631沿第一方向X的长度可以小于第一初始传输线611沿第一方向X的长度。
在一些示例中，如图17A所示，第三数据连接线523、第十三数据连接 线533和第十七数据连接线537可以在第二方向Y上位于第一初始传输线611远离第二扫描信号线GL2(n)的一侧。第三数据连接线523、第十三数据连接线533和第十七数据连接线537可以沿第一方向X依次排布。第三数据连接线523、第十三数据连接线533和第十七数据连接线537可以在第二方向Y上向远离第一初始传输线611的一侧延伸至连接区。
在一些示例中，如图17A所示，第四数据连接线524、第十四数据连接线534和第十八数据连接线538可以在第二方向Y上位于第十一初始传输线631远离存储电容的第二电容极板392的一侧。第四数据连接线524、第十四数据连接线534和第十八数据连接线538可以沿第一方向X依次排布。第四数据连接线524、第十四数据连接线534和第十八数据连接线538可以在第二方向Y上向远离第二初始传输线631的一侧延伸至连接区。
在一些示例中，如图17A所示，第三数据连接线523、第四数据连接线524、第十三数据连接线533、第十四数据连接线534、第十七数据连接线537和第十八数据连接线538在衬底的正投影可以均大致为L字型。第三数据连接线523和第四数据连接线524可以关于显示岛区在第二方向Y上的中线大致对称。第十三数据连接线533和第十四数据连接线534可以关于显示岛区在第二方向Y上的中线大致对称。第十七数据连接线537和第十八数据连接线538可以关于显示岛区在第二方向Y上的中线大致对称。
在一些示例中，如图16A所示，第三数据连接线523在衬底的正投影可以位于第一数据连接线521和第五数据连接线525在衬底的正投影之间。第四数据连接线524在衬底的正投影可以位于第二数据连接线522和第六数据连接线526在衬底的正投影之间。第十三数据连接线533在衬底的正投影可以位于第五数据连接线525和第十五数据连接线535在衬底的正投影之间。第十四数据连接线534在衬底的正投影可以位于第六数据连接线526和第十六数据连接线536在衬底的正投影之间。第十七数据连接线537在衬底的正投影可以在第一方向X上位于第十五数据连接线535在衬底的正投影远离第十三数据连接线533的一侧。第十八数据连接线538在衬底的正投影可以在第一方向X上位于第十六数据连接线536在衬底的正投影远离第十四数据连接线534的一侧。
图16B为本公开至少一实施例的第二显示区形成第三导电层后的显示基板的局部放大示意图。图17B为图16B中的第三导电层的示意图。在一些示例中，如图16B和图17B所示，第二显示区的第三导电层可以包括：多个第二区域像素电路(例如第四像素电路至第六像素电路)的第八晶体管48的栅极481和存储电容的第二电容极板492、第二扫描信号线GL2(n)、第四初始传输线614以及第十四初始传输线634。
在一些示例中，如图17B所示，第二扫描信号线GL2(n)在第二显示区可以沿第一方向X延伸。以第四像素电路为例，第四像素电路的第八晶体管48的栅极481与第二扫描信号线GL2(n)可以为一体结构。第四像素电路的存储电容的第二电容极板492可以具有第二镂空结构K2，第二镂空结构K2在衬底的正投影可以位于第一电容极板491在衬底的正投影范围内。第四初始传输线614和第十四初始传输线634可以均沿第一方向X延伸。第四初始传输线614在第二方向Y上位于第十四初始传输线634远离对第二扫描信号线GL2(n)的一侧。
在一些示例中，第二扫描信号线GL2(n)可以从第一显示区经由连接区延伸至第二显示区，或者可以从第一显示区直接延伸至第二显示区。第一初始传输线611和第四初始传输线614可以被配置为传输第一初始信号，第十一初始传输线631和第十四初始传输线634可以被配置为传输第二初始信号。
在一些示例中，第一显示区的至少一个连接区的第三导电层可以包括：第二扫描信号线。在形成第三导电层后，第一显示区的透光区可以包括：衬底、以及依次设置在衬底上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
(6)、形成第五绝缘层。在一些示例中，在形成前述图案的衬底上，沉积第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化，形成第五绝缘层。
图18A为本公开至少一实施例的第一显示区形成第五绝缘层后的显示基板的局部放大示意图。在一些示例中，如图18A所示，第一显示区的单个显示岛区的第五绝缘层可以开设有多个过孔，例如可以包括：第一过孔V1至第十八过孔V18、第二十一过孔V21至第四十六过孔V46、以及第五十一过 孔V51至第六十九过孔V69。其中，第一过孔V1至第十八过孔V18内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被去掉，暴露出第一半导体层的表面。第二十一过孔V21至第四十过孔V40内的第五绝缘层、第四绝缘层和第三绝缘层被去掉，暴露出第二导电层的表面。第四十一过孔V41和第四十六过孔V46内的第五绝缘层和第四绝缘层被去掉，暴露出第二半导体层的表面。第五十一过孔V51至第六十九过孔V69内的第五绝缘层被去掉，暴露出第三导电层的表面。
图18B为本公开至少一实施例的第二显示区形成第五绝缘层后的显示基板的局部放大示意图。在一些示例中，如图18B所示，第二显示区的第五绝缘层可以开设由多个过孔。以第二显示区的第四像素电路为例，第四像素电路所在区域的第五绝缘层开设的过孔例如可以包括：第七十一过孔V71至第七十六过孔V76、第八十一过孔V81至第八十六过孔V86、第九十一过孔V91至第九十五过孔V95。第七十一过孔V71至第七十六过孔V76内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被去掉，暴露出第一半导体层的表面。第八十一过孔V81至第八十四过孔V84内的第五绝缘层、第四绝缘层和第三绝缘层被去掉，暴露出第二导电层的表面。第八十五过孔V85和第八十六过孔V86内的第五绝缘层和第四绝缘层被去掉，暴露出第二半导体层的表面。第九十一过孔V91至第九十五过孔V95内的第五绝缘层被去掉，暴露出第三导电层的表面。
在一些示例中，在形成第五绝缘层后，第一显示区的连接区可以包括：衬底、以及依次设置在衬底上的第一导电层、第一绝缘层、第二绝缘层、第二导电层、第三绝缘层、第四绝缘层、第三导电层和第五绝缘层。第一显示区的透光区可以包括：衬底、以及依次设置在衬底上的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层。
(7)、形成第四导电层。在一些示例中，在形成前述图案的衬底上，沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，形成设置在第五绝缘层上的第四导电层。在一些示例中，第四导电层还可以称为第一源漏金属层。
图19A为本公开至少一实施例的第一显示区形成第四导电层后的显示基 板的局部放大示意图。图20A为图19A中的第四导电层的示意图。在一些示例中，如图19A和图20A所示，第一显示区的单个显示岛区的第四导电层可以至少包括：多个连接电极(例如包括：第一连接电极231至第二十连接电极250)、第二初始传输线612、第三初始传输线613、第一电源传输线661、第一扫描信号线GL1(n)和GL1(n+1)、以及第四扫描信号线RST2(n)。
在一些示例中，如图18A、图19A和图20A所示，第一连接电极231可以通过第一过孔V1与第一像素电路的第一晶体管的第一有源层的第一区电连接，还可以通过第五十五过孔V55与第一初始传输线611电连接。第二连接电极232可以通过第二过孔V2与第一像素电路的第二晶体管的第二有源层的第一区电连接，还可以通过第四十一过孔V41与第一像素电路的第八晶体管的第八有源层的第一区电连接。第三连接电极233可以通过第三过孔V3与第一像素电路的第四晶体管的第四有源层的第一区电连接。第四连接电极234可以通过第四十二过孔V42与第一像素电路的第八晶体管的第八有源层的第二区电连接，还可以通过第二十九过孔V29与第一像素电路的第三晶体管的栅极电连接。第五连接电极235可以通过第五过孔V5与第一像素电路的第六晶体管的第六有源层的第二区电连接。第六连接电极236可以通过第六过孔V6与第一像素电路的第七晶体管的第七有源层的第一区电连接，还可以通过第六十四过孔V64与第十一初始传输线631电连接。
在一些示例中，如图18A、图19A和图20A所示，第七连接电极237可以通过第七过孔V7与第二像素电路的第一晶体管的第一有源层的第一区电连接，还可以通过第五十六过孔V56与第一初始传输线611电连接。第八连接电极238可以通过第八过孔V8与第二像素电路的第二晶体管的第二有源层的第一区电连接，还可以通过第四十三过孔V43与第二像素电路的第八晶体管的第八有源层的第一区电连接。第九连接电极239可以通过第九过孔V9与第二像素电路的第四晶体管的第四有源层的第一区电连接。第十连接电极240可以通过第四十四过孔V44与第二像素电路的第八晶体管的第八有源层的第二区电连接，还可以通过第三十过孔V30与第二像素电路的第三晶体管的栅极电连接。第十一连接电极241可以通过第十一过孔V11与第二像素电路的第六晶体管的第六有源层的第二区电连接。第十二连接电极242可以 通过第十二过孔V12与第二像素电路的第七晶体管的第七有源层的第一区电连接，还可以通过第六十五过孔V65与第十一初始传输线631电连接。
在一些示例中，如图18A、图19A和图20A所示，第十三连接电极243可以通过第十三过孔V13与第三像素电路的第一晶体管的第一有源层的第一区电连接，还可以通过第五十七过孔V57与第一初始传输线611电连接。第十四连接电极244可以通过第十四过孔V14与第三像素电路的第二晶体管的第二有源层的第一区电连接，还可以通过第四十五过孔V45与第三像素电路的第八晶体管的第八有源层的第一区电连接。第十五连接电极245可以通过第十五过孔V15与第三像素电路的第四晶体管的第四有源层的第一区电连接。第十六连接电极246可以通过第四十六过孔V46与第三像素电路的第八晶体管的第八有源层的第二区电连接，还可以通过第三十一过孔V31与第三像素电路的第三晶体管的栅极电连接。第十七连接电极247可以通过第十七过孔V17与第三像素电路的第六晶体管的第六有源层的第二区电连接。第十八连接电极248可以通过第十八过孔V18与第三像素电路的第七晶体管的第七有源层的第一区电连接，还可以通过第六十六过孔V66与第十一初始传输线631电连接。
在一些示例中，如图18A、图19A和图20A所示，第十九连接电极249可以通过第二十四过孔V24与位于第二导电层的第五遮挡走线221电连接，还可以通过第五十九过孔V59与位于第三导电层的第二扫描信号线GL2(n)电连接。第二十连接电极250可以通过第二十五过孔V24与位于第二导电层的第五遮挡走线221电连接，还可以通过第六十过孔V60与位于第三导电层的第二扫描信号线GL2(n)电连接。第十九连接电极249和第二十连接电极250可以关于显示岛区在第一方向X上的中线大致对称。在本示例中，第五遮挡走线221与第八晶体管38的第八有源层380的交叠区域可以作为第八晶体管38的底栅。
在一些示例中，如图18A、图19A和图20A所示，第二初始传输线612可以沿第一方向X从连接区延伸至显示岛区，并在显示岛区沿第二方向Y延伸。第三初始传输线613可以沿第一方向X从连接区延伸至显示岛区，并在显示岛区沿第二方向Y延伸。第二初始传输线612和第三初始传输线613可 以关于显示岛区沿第一方向X的中线大致对称。第二初始传输线612可以通过第五十四过孔V54与第一初始传输线611的一端电连接，第三初始传输线613可以通过第五十八过孔V58与第一初始传输线611的另一端电连接。在本示例中，通过第一初始传输线611至第三初始传输线613、以及第一连接电极231、第七连接电极237和第十三连接电极243的电连接，可以实现向显示岛区的三个第一区域像素电路传输第一初始信号。
在一些示例中，如图18A和图20A所示，在第二方向Y上，第一扫描信号线GL1(n)和GL1(n+1)可以位于第四扫描信号线RST2(n)的相对两侧。第三扫描信号线RST1(n)可以位于第一扫描信号线GL1(n)远离第四扫描信号线RST2(n)的一侧。第一扫描信号线GL1(n)可以沿第一方向X从连接区延伸至显示岛区，再从显示岛区延伸至另一连接区。第一扫描信号线GL1(n)在显示岛区可以通过第三十八过孔V38与第一像素电路的第二晶体管的栅极电连接，还可以通过第三十九过孔V39与第二像素电路的第二晶体管的栅极电连接，还可以通过第四十过孔V40与第三像素电路的第二晶体管的栅极电连接。第一扫描信号线GL1(n)可以被配置为向显示岛区的三个第一区域像素电路提供第一扫描信号。
在一些示例中，如图18A和图20A所示，第四扫描信号线RST2(n)可以沿第一方向X从连接区延伸至显示岛区，在显示岛区在第二方向Y上绕过第三晶体管后，再沿第一方向X延伸至另一连接区。第四扫描信号线RST2(n)可以通过第三十二过孔V32与第一像素电路的第七晶体管的栅极电连接，还可以通过第三十三过孔V33与第二像素电路的第七晶体管的栅极电连接，还可以通过第三十四过孔V34与第三像素电路的第七晶体管的栅极电连接。第四扫描信号线RST2(n)可以被配置为向显示岛区的三个第一区域像素电路提供第二复位控制信号。
在一些示例中，如图18A和图20A所示，第一扫描信号线GL1(n+1)可以沿第一方向X从连接区延伸至显示岛区，在显示岛区在第二方向Y上绕过第三晶体管后，再沿第一方向X延伸至另一连接区。第一扫描信号线GL1(n+1)在第二方向Y上可以位于第四扫描信号线RST2(n)远离第一扫描信号线GL1(n)的一侧。通过设置第一扫描信号GL1(n+1)横穿显示岛区，可以使得第 一显示区在第一方向X上两侧的第n+1行第二区域像素电路电连接的第一扫描信号线连通，可以确保信号均一性。
在一些示例中，如图18A和图20A所示，第一电源传输线661可以位于显示岛区内，可以包括沿第一方向X延伸的第一主体部分以及沿第二方向Y从第一主体部分的同侧凸出的三个第一凸出部。第一电源传输线661的第一个第一凸出部可以通过第四过孔V4与第一像素电路的第五晶体管的第五有源层的第一区电连接，第二个第一凸出部可以通过第十过孔V10与第二像素电路的第五晶体管的第五有源层的第一区电连接，第三个第一凸出部可以通过第十六过孔V16与第三像素电路的第五晶体管的第五有源层的第一区电连接。第一电源传输线661的第一主体部分可以通过第六十一过孔V61与第一像素电路的存储电容的第二电容极板电连接，还可以通过第六十二过孔V62与第二像素电路的存储电容的第二电容极板电连接，还可以通过第六十三过孔V63与第三像素电路的存储电容的第二电容极板电连接。
在一些示例中，如图18A、图19A和图20A所示，第一显示区的单个显示岛区的第四导电层还可以包括：多个数据连接电极(例如包括：第一数据连接电极541、第四数据连接电极544、第五数据连接电极545、第八数据连接电极548、第九数据连接电极549、第十三数据连接电极553、第十六数据连接电极556、第十七数据连接电极557、第二十数据连接电极560、第二十一数据连接电极561、第二十四数据连接电极564)、以及多条数据连接线(例如包括：第七数据连接线527、第八数据连接线528、第九数据连接线529、第十数据连接线530、第十一数据连接线531和第十二数据连接线532)。
在一些示例中，如图20A所示，第七数据连接线527、第九数据连接线529和第十一数据连接线531可以在第二方向Y位于第三扫描信号线RST1(n)远离第一扫描信号线GL1(n)的一侧。第七数据连接线527、第九数据连接线529和第十一数据连接线531可以沿第一方向X依次排布。第八数据连接线528、第十数据连接线530和第十二数据连接线532可以在第二方向Y位于第一扫描信号线GL1(n+1)远离第四扫描信号线RST2(n)的一侧。第八数据连接线528、第十数据连接线530和第十二数据连接线532可以沿第一方向X依次排布。
在一些示例中，如图18A、图19A和图20A所示，第一数据连接电极541可以通过第十二过孔V12与位于第二导电层的第一数据连接线521电连接。第四数据连接电极544可以通过第三十六过孔V36与位于第二导电层的第二数据连接线522电连接。第五数据连接电极545可以通过第五十一过孔V51与位于第三导电层的第三数据连接线523电连接。第八数据连接电极548可以通过第六十八过孔V68与位于第三导电层的第四数据连接线524电连接。第九数据连接电极549可以通过第二十三过孔V23与位于第二导电层的第五数据连接线525电连接。第十二数据连接电极552可以通过第三十五过孔V35与位于第二导电层的第六数据连接线526电连接。
在一些示例中，如图18A、图19A和图20A所示，第十三数据连接电极553可以通过第五十三过孔V53与位于第三导电层的第十三数据连接线533电连接。第十六数据连接电极556可以通过第六十七过孔V67与位于第三导电层的第十四数据连接线534电连接。第十七数据连接电极557可以通过第二十二过孔V22与位于第二导电层的第十五数据连接线535电连接。第二十数据连接电极560可以通过第三十七过孔V37与位于第二导电层的第十六数据连接线536电连接。第二十一数据连接电极561可以通过第五十二过孔V52与位于第三导电层的第十七数据连接线537电连接。第二十四数据连接电极564可以通过第六十九过孔V69与位于第三导电层的第十八数据连接线538电连接。
图19B为本公开至少一实施例的第二显示区形成第四导电层后的显示基板的局部放大示意图。图20B为图19B中的第四导电层的示意图。在一些示例中，第二显示区的第四导电层可以包括：多个连接电极(例如包括：第二十一连接电极251至第三十二连接电极262)、第三扫描信号线RST1(n)、第一扫描信号线GL1(n)以及第四电源传输线664。
在一些示例中，如图19B和图20B所示，以第二显示区的一个第四像素电路为例进行说明。第二十一连接电极251可以通过第七十一过孔V71与第四像素电路的第一晶体管的第一有源层的第一区电连接，还可以通过第九十五过孔V95与第四初始传输线614电连接。第二十二连接电极252可以通过第七十六过孔V76与上一行的第四像素电路的第七晶体管的第七有源层的第 一区电连接，还可以通过第九十二过孔V92与第十四初始传输线634电连接。第二十三连接电极253可以通过第七十三过孔V73与第四像素电路的第四晶体管的第四有源层的第一区电连接。第二十四连接电极254可以通过第七十二过孔V72与第四像素电路的第二晶体管的第二有源层的第一区电连接，还可以通过第八十五过孔V85与第四像素电路的第八晶体管的第八有源层的第一区电连接。第二十五连接电极255可以通过第八十六过孔V86与第四像素电路的第八晶体管的第八有源层的第二区电连接，还可以通过第八十四过孔V84与第四像素电路的第三晶体管的栅极电连接。第二十六连接电极256可以通过第七十五过孔V75与第四像素电路的第六晶体管的第六有源层的第二区电连接。第二十七连接电极257可以通过第九十一过孔V91与第四初始传输线614电连接。第二十八连接电极258可以通过第九十三过孔V93与第十四初始传输线634电连接。第二十九连接电极259可以与第五像素电路的第四晶体管的第四有源层的第一区电连接。第三十连接电极260可以与第五像素电路的第六晶体管的第六有源层的第二区电连接。第三十一连接电极261可以与第六像素电路的第四晶体管的第四有源层的第一区电连接。第三十二连接电极262可以与第六像素电路的第六晶体管的第六有源层的第二区电连接。
在一些示例中，如图19B和图20B所示，第一扫描信号线GL1(n)可以沿第一方向X延伸，可以通过第八十二过孔V82与第四像素电路的第四晶体管的栅极电连接，还可以通过第八十三过孔V83与第四像素电路的第二晶体管的栅极电连接。第三扫描信号线RST1(n)可以沿第一方向X延伸，可以通过第八十一过孔V81与第四像素电路的第一晶体管的栅极电连接。
在一些示例中，如图19B和图20B所示，第四电源传输线664可以包括沿第一方向X延伸的第二主体部分以及沿第二方向Y在第二主体部分的同侧凸出的三个第二凸出部。第四电源传输线664的一个第二凸出部可以通过第七十四过孔V74与第四像素电路的第五晶体管的第五有源层的第一区电连接，其余两个第二凸出部可以分别与第五像素电路和第六像素电路的第五晶体管的第五有源层的第一区电连接。第四电源传输线664的第二主体部分可以通过第九十四过孔V94与第四像素电路的存储电容的第二电容极板电连接，还 可以与第五像素电路和第六像素电路的存储电容的第二电容极板电连接。
在一些示例中，第一显示区的至少一个连接区的第四导电层可以包括：沿第一方向X延伸的第二初始传输线、第三初始传输线、第一扫描信号线以及第三扫描信号线；或者，可以包括沿第二方向Y延伸的多条数据连接线。
在一些示例中，在形成第四导电层后，第一显示区的透光区的膜层结构没有变化。
(8)、形成第六绝缘层。在一些示例中，在形成前述图案的衬底上，涂覆第六绝缘薄膜，通过图案化工艺对第六绝缘薄膜进行图案化，形成第六绝缘层。
图21A为本公开至少一实施例的第一显示区形成第六绝缘层后的显示基板的局部放大示意图。在一些示例中，如图21A所示，第一显示区的单个显示岛区的第六绝缘层可以开设有多个过孔，例如可以包括：第一百零一过孔V101至第一百三十三过孔V133。第一百零一过孔V101至第一百三十三过孔V133内的第六绝缘层被去掉，暴露出第四导电层的表面。
图21B为本公开至少一实施例的第二显示区形成第六绝缘层后的显示基板的局部放大示意图。在一些示例中，如图21B所示，第二显示区的第六绝缘层可以开设有多个过孔。一个第二像素单元所在区域的第六绝缘层开设的过孔例如可以包括：第一百四十一过孔V141至第一百四十六过孔V146。第一百四十一过孔V141至第一百四十六过孔V146内的第六绝缘层被去掉，暴露出第四导电层的表面。
(9)、形成第五导电层。在一些示例中，在形成前述图案的衬底上，沉积第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，形成设置在第六绝缘层上的第五导电层。在一些示例中，第五导电层还可以称为第二源漏金属层。
图22A为本公开至少一实施例的第一显示区形成第五导电层后的显示基板的局部放大示意图。图23A为图22A中的第五导电层的示意图。在一些示例中，如图22A和图23A所示，第一显示区的单个显示岛区的第五导电层可以至少包括：多个连接电极(例如包括第四十一连接电极271至第四十六连接电极276)、第一扫描连接线651、第二扫描连接线652、第二电源传输线 662、第三电源传输线663、第十二初始传输线632、第十三初始传输线633。
在一些示例中，如图21A、图22A和图23A所示，第四十一连接电极271可以通过第一百十九过孔V119与第五连接电极235电连接，以实现与第一像素电路的第六晶体管的第六有源层的第二区电连接。第四十二连接电极272可以通过第一百二十过孔V120与第十一连接电极241电连接，以实现与第二像素电路的第六晶体管的第六有源层的第二区电连接。第四十三连接电极273可以通过第一百二十一过孔V121与第十七连接电极247电连接，以实现与第三像素电路的第六晶体管的第六有源层的第二区电连接。
在一些示例中，如图21A、图22A和图23A所示，第四十四连接电极274可以通过第一百十过孔V110与第七连接电极237电连接，以实现与第一初始传输线611电连接。第四十五连接电极275可以通过第一百十七过孔V117与第一电源传输线661电连接。第四十六连接电极276可以通过第一百二十三过孔V123与第十二连接电极242电连接，以实现与第十一初始传输线631电连接。
在一些示例中，如图21A、图22A和图23A所示，第一扫描连接线651和第二扫描连接线652可以在第一方向X的相对两侧的连接区分别延伸至显示岛区，并在显示岛区沿第二方向Y延伸。第一扫描连接线651可以通过第一百十一过孔V111与第三扫描信号线RST1(n)的一端电连接，第二扫描连接线652可以通过第一百十二过孔V112与第三扫描信号线RST1(n)的另一端电连接。在本示例中，通过第一扫描连接线651、第三扫描信号线和第二扫描连接线652的电连接，可以实现第一复位控制信号在第一显示区内的传输。
在一些示例中，如图21A、图22A和图23A所示，第二电源传输线662和第三电源传输线663可以在第一方向X上从显示岛区两侧的连接区延伸至显示岛区。第二电源传输线662可以通过第一百十六过孔V116与第一电源传输线661的一端电连接，第三电源传输线663可以通过第一百十八过孔V118与第一电源传输线661的另一端电连接。
在一些示例中，如图21A、图22A和图23A所示，第十二初始传输线632和第十三初始传输线633可以在第一方向X从显示岛区两侧的连接区延伸至显示岛区。第十二初始传输线632可以通过第一百二十二过孔V122与 第六连接电极236电连接，从而实现与第十一初始传输线631的电连接。第十三初始传输线633可以通过第一百二十四过孔V124与第十八连接电极248电连接，从而实现与第十一初始传输线631的电连接。
在一些示例中，如图22A和图23A所示，第一显示区的单个显示岛区的第五导电层还可以包括：多个数据连接电极(例如包括：第二数据连接电极542、第三数据连接电极543、第六数据连接电极546、第七数据连接电极547、第十数据连接电极550、第十一数据连接电极551、第十四数据连接电极554、第十五数据连接电极555、第十八数据连接电极558、第十九数据连接电极559、第二十二数据连接电极562和第二十三数据连接电极563)、以及多条数据线(例如包括：第四数据线514至第九数据线519)。
在一些示例中，如图21A、图22A和图23A所示，第二数据连接电极542可以通过第一百零一过孔V101与第一数据连接电极541电连接。第三数据连接电极543可以通过第一百二十八过孔V128与第四数据连接电极544电连接。第六数据连接电极546可以通过第一百零三过孔V103与第五数据连接电极545电连接。第七数据连接电极547可以通过第一百二十七过孔V127与第八数据连接电极548电连接。第十数据连接电极550可以通过第一百零五过孔V105与第九数据连接电极549电连接。第十一数据连接电极551可以通过第一百二十六过孔V126与第十二数据连接电极552电连接。第十四数据连接电极554可以通过第一百零六过孔V106与第十三数据连接电极553电连接。第十五数据连接电极555可以通过第一百三十过孔V130与第十六数据连接电极556电连接。第十八数据连接电极558可以通过第一百零四过孔V104与第十七数据连接电极557电连接。第十九数据连接电极559可以通过第一百三十一过孔V131与第二十数据连接电极560电连接。第二十二数据连接电极562可以通过第一百零二过孔V102与第二十一数据连接电极561电连接。第二十三数据连接电极563可以通过第一百三十二过孔V132与第二十四数据连接电极564电连接。
在一些示例中，如图21A、图22A和图23A所示，第四数据线514、第六数据线516和第八数据线518在显示岛区内沿第二方向Y延伸。第五数据线515、第七数据线517和第九数据线519沿第二方向Y从连接区延伸至显 示岛区，在延伸至另一连接区。第四数据线514至第九数据线519可以沿第一方向X依次排布。第四数据线514的一端可以通过第一百零七过孔V107与第七数据连接线527电连接，另一端可以通过第一百二十九过孔V129与第八数据连接线528电连接。第四数据线514还可以通过第一百十三过孔V113与第三连接电极233电连接，从而实现与第一像素电路的第四晶体管的第四有源层的第一区的电连接。第六数据线516的一端可以通过第一百零八过孔V108与第九数据连接线529电连接，另一端可以通过第一百二十五过孔V125与第十数据连接线530电连接。第六数据线516还可以通过第一百十四过孔V114与第九连接电极239电连接，从而实现与第二像素电路的第四晶体管的第四有源层的第一区的电连接。第八数据线518的一端可以通过第一百零九过孔V109与第十一数据连接线531电连接，另一端可以通过第一百三十三过孔V133与第十二数据连接线532电连接。第八数据线518还可以通过第一百十五过孔V115与第十五连接电极245电连接，从而实现与第三像素电路的第四晶体管的第四有源层的第一区的电连接。
在本示例中，第四数据线514可以被配置为给第一像素电路提供数据信号，第六数据线516可以被配置为给第二像素电路提供数据信号，第八数据线518可以被配置为给第三像素电路提供数据信号。第五数据线515可以从第一像素电路所在区域穿过显示岛区，第七数据线517可以从第二像素电路所在区域穿过显示岛区，第九数据线519可以从第三像素电路所在区域穿过显示岛区。第五数据线515、第七数据线517和第九数据线519可以直接沿第二方向Y延伸至连接区。第四数据线514、第六数据线516和第八数据线518可以分别与连接区的数据连接线电连接。
在本示例中，一个第一区域像素电路在衬底的正投影可以与两条数据线在衬底的正投影存在交叠。其中，一个第一区域像素电路的第一半导体层在衬底的正投影可以与两条数据线在衬底的正投影存在交叠。具体而言，第一像素电路的第一半导体层(包括多个第一类型晶体管的有源层)在衬底的正投影可以与第四数据线514和第五数据线515在衬底的正投影存在交叠。第二像素电路的第一半导体层在衬底的正投影可以与第六数据线516和第七数据线517在衬底的正投影存在交叠。第三像素电路的第一半导体层在衬底的 正投影可以与第八数据线518和第九数据线519在衬底的正投影存在交叠。
图22B为本公开至少一实施例的第二显示区形成第五导电层后的显示基板的局部放大示意图。图23B为图22B中的第五导电层的示意图。在一些示例中，如图22B和图23B所示，第二显示区的第五导电层可以包括：多个连接电极(例如包括：第四十七连接电极277至第四十九连接电极279)、沿第二方向Y延伸的多条数据线(例如包括：数据线DL1a、DL1b、DL2a、DL2b、DL3a和DL3b)。数据线DL1a、DL1b、DL2a、DL2b、DL3a和DL3b可以沿第一方向X依次排布。第四十七连接电极277可以通过第一百四十二过孔V142与第二十六连接电极256电连接。第四十八连接电极278可以通过第一百四十四过孔V144与第三十连接电极260电连接。第四十九连接电极279可以通过第一百四十六过孔V146与第三十二连接电极262电连接。
在一些示例中，以第四像素电路位于第j-1列第n行，第五像素电路位于第j列第n行，第六像素电路位于第j+1列第n行为例。数据线DL1a可以通过第一百四十一过孔V141与第二十三连接电极253电连接，配置为给位于第j-1列第n行的第四像素电路提供数据信号。数据线DL2a可以通过第一百四十三过孔V143与第二十九连接电极259电连接，配置为给位于第j列第n行的第五像素电路提供数据信号。数据线DL3a可以通过第一百四十五过孔V145与第三十一连接电极261电连接，配置为给位于第j+1列第n行的第六像素电路提供数据信号。
在一些示例中，数据线DL1b可以被配置为给位于第j-1列第n-1行的第四像素电路提供数据信号，数据线DL2b可以被配置为给位于第j列第n行的第五像素电路提供数据信号，数据线DL3b可以被配置为给位于第j+1列第n行的第六像素电路提供数据信号。在本示例中，奇数行和偶数行的第二区域像素电路电连接不同的数据线，可以保证数据信号较好地匹配第二区域像素电路的寄生电容，从而确保显示效果。
在一些示例中，第一显示区的至少一个连接区的第五导电层可以包括：沿第一方向X延伸的第一扫描连接线651和第二扫描连接线652、第二电源传输线662和第三电源传输线663、第十二初始传输线632和第十三初始传输线633；或者可以包括沿第二方向Y延伸的第五数据线515、第七数据线 517和第九数据线519。
在一些示例中，在形成第五导电层后，第一显示区的透光区的膜层结构没有变化。
(10)、形成第七绝缘层。在一些示例中，在形成前述图案的衬底上，涂覆第七绝缘薄膜，通过图案化工艺对第七绝缘薄膜进行图案化，形成第七绝缘层。
图24A为本公开至少一实施例的第一显示区形成第七绝缘层后的显示基板的局部放大示意图。在一些示例中，如图24A所示，第一显示区的单个显示岛区的第七绝缘层可以开设有多个过孔，例如可以包括：第一百五十一过孔V151至第一百六十八过孔V168。第一百五十一过孔V151至第一百六十八过孔V168内的第七绝缘层被去掉，暴露出第五导电层的表面。
图24B为本公开至少一实施例的第二显示区形成第七绝缘层后的显示基板的局部放大示意图。在一些示例中，如图24B所示，第二显示区的第七绝缘层可以开设有多个过孔。第二显示区的一个第二像素单元所在区域的第七绝缘层开设的过孔例如可以包括：第一百七十一过孔V171至第一百七十六过孔V176。第一百七十一过孔V171至第一百七十三过孔V173内的第七绝缘层和第六绝缘层被去掉，暴露出第四导电层的表面。第一百七十四过孔V174和第一百七十六过孔V176内的第七绝缘层被去掉，暴露出第五导电层的表面。
在一些示例中，在形成第七绝缘层后，第一显示区的连接区可以包括衬底、以及依次设置在衬底上的第一导电层、第一绝缘层、第二绝缘层、第二导电层、第三绝缘层、第四绝缘层、第三导电层、第五绝缘层、第四导电层、第六绝缘层、第五导电层以及第七绝缘层。第一显示区的透光区可以包括衬底、以及依次设置在衬底上的第一绝缘层至第七绝缘层。
(11)、形成第六导电层。在一些示例中，在形成前述图案的衬底上，沉积第六导电薄膜，通过图案化工艺对第六导电薄膜进行图案化，形成设置在第七绝缘层上的第六导电层。在一些示例中，第六导电层还可以称为第三源漏金属层。
图25A为本公开至少一实施例的第一显示区形成第六导电层后的显示基 板的局部放大示意图。图26A为图25A中的第六导电层的示意图。在一些示例中，如图25A和图26A所示，第一显示区的单个显示岛区的第六导电层可以至少包括：多个连接电极(例如包括：第五十一连接电极281至第五十三连接电极583)、多条数据线(例如包括第一数据线511至第三数据线513、第十数据线520至第十二数据线522)、第五初始传输线615、第十五初始传输线635、第五电源传输线665、以及第七电源传输线667。
在一些示例中，如图24A、图25A和图26A所示，第五十一连接电极281可以通过第一百五十八过孔V158与第四十一连接电极271电连接。第五十二连接电极282可以通过第一百六十过孔V160与第四十二连接电极272电连接。第五十三连接电极283可以通过第一百六十一过孔V161与第四十三连接电极273电连接。
在一些示例中，如图25A和图26A所示，第一数据线511、第二数据线512和第三数据线513可以位于显示岛区内且沿第一方向X依次排布，并位于第五电源传输线665远离第五初始传输线615的一侧。第一数据线511、第二数据线512和第三数据线513可以为弧线型。第十数据线520、第十一数据线521和第十二数据线522可以位于显示岛区内且沿第一方向X依次排布，并位于第七电源传输线668远离第十五初始传输线635的一侧。第十数据线520、第十一数据线521和第十二数据线522可以为弧线型。
在一些示例中，如图24A、图25A和图26A所示，第一数据线511的一端可以通过第一百五十一过孔V151与第二数据连接电极542电连接，另一端可以通过第一百六十七过孔V167与第三数据连接电极543电连接。第二数据线512的一端可以通过第一百五十三过孔V153与第六数据连接电极546电连接，另一端可以通过第一百六十五过孔V165与第七数据连接电极547电连接。第三数据线513的一端可以通过第一百五十五过孔V155与第十数据连接电极550电连接，另一端可以通过第一百六十三过孔V163与第十一数据连接电极551电连接。第十数据线520的一端可以通过第一百五十六过孔V156与第十四数据连接电极554电连接，另一端可以通过第一百六十四过孔V164与第十五数据连接电极555电连接。第十一数据线521的一端可以通过第一百五十四过孔V154与第十八数据连接电极558电连接，另一端 可以通过第一百六十六过孔V166与第十九数据连接电极559电连接。第十二数据线522的一端可以通过第一百五十二过孔V152与第二十二数据连接电极562电连接，另一端可以通过第一百六十八过孔V168与第二十三数据连接电极563电连接。
在本示例中，第一数据线511至第三数据线513、第十数据线520至第十二数据线522在显示岛区可以围绕在三个第一区域像素电路的外围，且绕过第一区域像素电路所在区域。而且第一数据线511至第三数据线513、第十数据线520至第十二数据线522可以分别为弧线型，第一数据线511至第三数据线513在第一方向X可以向远离第一像素电路的一侧弯曲，第十数据线520至第十二数据线522在第一方向X可以向远离第三像素电路的一侧弯曲。如此一来，可以使得显示岛区的边缘为弧形边缘，并可以减少上述多条数据线与第一区域像素电路之间的干扰。
在一些示例中，在第一显示区内，第五电源传输线665可以在第二方向Y传输第一电压信号，通过电连接第一电源传输线661、第二电源传输线662和第三电源传输线663可以在第一方向X传输第一电压信号。位于第六导电层的第五电源传输线665通过位于第五导电层的第四十五连接电极275与位于第四导电层的第一电源传输线661电连接，可以在第一显示区提供第一电压信号的网状传输路径，从而可以降低第一电压信号的传输走线的负载，改善第一显示区的第一电压信号的传输均一性。
在一些示例中，在第一显示区内，第七电源传输线667可以被配置为传输第二电压信号。
在一些示例中，在第一显示区内，第五初始传输线615可以在第二方向Y上传输第一初始信号。通过电连接第二初始传输线612、第一初始传输线611和第三初始传输线613可以在第一方向X传输第一初始信号。位于第六导电层的第五初始传输线615可以通过位于第五导电层的第四十四连接电极274和位于第四导电层的第七连接电极237与位于第三导电层的第一初始传输线611电连接，可以在第一显示区提供第一初始信号的网状传输路径，从而可以降低第一初始信号的传输走线的负载，提高第一显示区的第一初始信号的传输均一性。
在一些示例中，在第一显示区内，第十五初始传输线635可以在第二方向Y上传输第二初始信号。通过电连接第十二初始传输线632、第十一初始传输线631和第十三初始传输线633可以在第一方向X上传输第二初始信号。位于第六导电层的第十五初始传输线635可以通过位于第五导电层的第四十六连接电极276和位于第四导电层的第十二连接电极242与位于第三导电层的第十一初始传输线631电连接，可以在第一显示区提供第二初始信号的网状传输路径，从而可以降低第二初始信号的传输走线的负载，改善第一显示区的第二初始信号的传输均一性。
在一些示例中，第一显示区的单个显示岛区可以设置十二条数据线，其中六条数据线可以穿过第一区域像素电路所在的区域，其余六条数据线可以围绕在三个第一区域像素电路的外围。
图25B为本公开至少一实施例的第二显示区形成第六导电层后的显示基板的局部放大示意图。图26B为图25B中的第六导电层的示意图。在一些示例中，如图25B和图26B所示，第二显示区的第六导电层可以包括：多个连接电极(例如包括第五十四连接电极284至第五十六连接电极286)、第六初始传输线616、第十六初始传输线636、第六电源传输线666以及第八电源传输线668。
在一些示例中，第五十四连接电极284可以通过第一百七十四过孔V174与第四十七连接电极277电连接。第五十五连接电极285可以通过第一百七十五过孔V175与第四十八连接电极278电连接。第五十五连接电极285可以沿第二方向Y延伸。第五十六连接电极286可以通过第一百七十六过孔V176与第四十九连接电极279电连接。
在一些示例中，第六初始传输线616、第十六初始传输线636、第六电源传输线666以及第八电源传输线668可以均沿第二方向Y延伸。第六初始传输线616可以通过第一百七十一过孔V171与位于第四导电层的第二十七连接电极257电连接，以实现与第四初始传输线614的电连接。位于第六导电层的第十六初始传输线636可以在第二方向Y上传输第二初始信号。位于第三导电层的第十四初始传输线634可以在第一方向X传输第二初始信号。第十六初始传输线636通过与第十四初始传输线634电连接，可以在第二显示 区提供第二初始信号的网状传输路径，从而可以降低第二初始信号的传输走线的负载，改善第二显示区的第二初始信号的传输均一性。
在一些示例中，第十六初始传输线636可以通过第一百七十二过孔V172与第二十八连接电极258电连接，以实现与第十四初始传输线634的电连接。位于第六导电层的第六初始传输线616可以在第二方向Y上传输第一初始信号。位于第三导电层的第四初始传输线614可以在第一方向X传输第一初始信号。第六初始传输线616通过与第四初始传输线614电连接，可以在第二显示区提供第一初始信号的网状传输路径，从而可以降低第一初始信号的传输走线的负载，改善第二显示区的第一初始信号的传输均一性。
在一些示例中，第六电源传输线666可以通过第一百七十三过孔V173与位于第四导电层的第四电源传输线664电连接。第六电源传输线666通过与第四电源传输线664电连接，可以在第二显示区提供第一电压信号的网状传输路径，从而可以降低第一电压信号的传输走线的负载，改善第二显示区的第一电压信号的传输均一性。
在一些示例中，在第二显示区的第二像素单元内，第十六初始传输线636可以位于第四像素电路和第五像素电路之间，第六初始传输线634可以位于第四像素电路与相邻的第二像素单元的第六像素电路之间，第八电源传输线668可以位于第五像素电路与第六像素电路之间。
在一些示例中，第一显示区的至少一个连接区的第六导电层可以包括：沿第二方向Y延伸的第五电源传输线665、第五初始传输线615、第十五初始传输线635和第七电源传输线667。
在一些示例中，在形成第六导电层后，第一显示区的透光区的膜层结构没有变化。
至此，可以制备完成驱动电路层102。在本示例中，第一显示区的显示岛区和第二显示区的驱动电路层102可以包括叠设在衬底上的第一导电层、第一绝缘层、第一半导体层、第二绝缘层、第二导电层、第三绝缘层、第二半导体层、第四绝缘层、第三导电层、第五绝缘层、第四导电层、第六绝缘层、第五导电层、第七绝缘层和第六导电层。第一显示区的连接区的驱动电路层102可以包括叠设在衬底上的第一导电层、第一绝缘层、第二绝缘层、 第二导电层、第三绝缘层、第四绝缘层、第三导电层、第五绝缘层、第四导电层、第六绝缘层、第五导电层、第七绝缘层和第六导电层。第一显示区的透光区的驱动电路层102可以包括叠设在衬底上的第一绝缘层至第七绝缘层。
在一些示例中，显示岛区内的第一数据线511至第三数据线513以及第十数据线520至第十二数据线522呈弧线型，可以使得显示岛区的外围边缘(即透光区的与显示岛区接触的第二边缘)呈弧形。连接区内设置的位于多个导电膜层的信号走线(例如包括数据连接线、数据线、以及扫描信号线等)可以均为线段或条形状体，可以使得连接区的外围边缘(即透光区的与连接区接触的第一边缘)沿一个方向延伸。透光区的第一边缘的形状可以由连接区内最靠近透光区的信号走线(例如，位于第五导电层的第二初始传输线612、第三初始传输线613、第一扫描信号线GL1(n+1)等)的外围边缘形状确定。然而，本实施例对此并不限定。在另一些示例中，在连接区内，位于第一导电层的第一遮挡走线211在衬底的正投影可以覆盖其余导电层的信号走线在衬底的正投影，第二遮挡走线212在衬底的正投影可以覆盖其余导电层的信号走线在衬底的正投影。如此一来，连接区靠近透光区的边缘(即透光区的第一边缘)的形状可以由第一遮挡走线和第二遮挡走线的外围边缘形状确定。
(12)、形成第八绝缘层。在一些示例中，在形成前述图案的衬底上，涂覆第八绝缘薄膜，通过图案化工艺对第八绝缘薄膜进行图案化，形成第八绝缘层。
图27A为本公开至少一实施例的第一显示区形成第八绝缘层后的显示基板的局部放大示意图。在一些示例中，如图27A所示，第一显示区的单个显示岛区的第八绝缘层可以开设有多个过孔，例如可以包括第一百八十一过孔V181至第一百八十三过孔V183。第一百八十一过孔V181至第一百八十三过孔V183内的第八绝缘层可以被去掉，暴露出第六导电层的表面。
图27B为本公开至少一实施例的第二显示区形成第八绝缘层后的显示基板的局部放大示意图。在一些示例中，如图27B所示，第二显示区的第八绝缘层可以开设有多个过孔。第二显示区的一个第二像素单元所在区域的第八绝缘层开设的过孔例如可以包括第一百八十四过孔V184至第一百八十六过孔V186。第一百八十四过孔V184至第一百八十六过孔V186内的第八绝缘 层被去掉，暴露出第七导电层的表面。
(13)、形成阳极层。在一些示例中，在形成前述图案的衬底上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。
图28A为本公开至少一实施例的第一显示区形成阳极层后的显示基板的局部放大示意图。图29A为图28A中的阳极层的示意图。在一些示例中，如图28A和图29A所示，第一显示区的单个显示岛区的阳极层可以包括：第一发光元件的第一阳极671、第二发光元件的第二阳极672和第三发光元件的第三阳极673。第一阳极671、第二阳极672可以沿第二方向Y排布，第三阳极673可以在第一方向X位于第一阳极671和第二阳极672的同一侧。第一阳极671、第二阳极672和第三阳极673的整体形状可以大致组合为圆形。
在一些示例中，如图28A和图29A所示，第一阳极671可以通过第一百八十一过孔V181与位于第六导电层的第五十一连接电极281电连接，从而可以通过位于第五导电层的第四十一连接电极271和位于第四导电层的第五连接电极235与第一像素电路的第六晶体管的第六有源层的第二区电连接。第二阳极672可以通过第一百八十二过孔V182与位于第六导电层的第五十二连接电极282电连接，从而可以通过位于第五导电层的第四十二连接电极272和位于第四导电层的第十一连接电极241与第二像素电路的第六晶体管的第六有源层的第二区电连接。第三阳极673可以通过第一百八十三过孔V183与位于第六导电层的第五十三连接电极283电连接，从而可以通过位于第五导电层的第四十三连接电极273和位于第四导电层的第十七连接电极247与第三像素电路的第六晶体管的第六有源层的第二区电连接。
图28B为本公开至少一实施例的第二显示区形成阳极层后的显示基板的局部放大示意图。图29B为图28B中的阳极层的示意图。在一些示例中，如图29A和图29B所示，第二显示区的阳极层可以包括：多个阳极(例如包括第四发光元件的第四阳极674、第五发光元件的第五阳极675和第六发光元件的第六阳极676)。第四阳极674和第五阳极675可以沿第二方向Y排布，第六阳极676可以在第一方向X位于第四阳极674和第五阳极675的同一侧。第四阳极674、第五阳极675和第六阳极676的整体形状可以大致为矩形。
在一些示例中，如图29A和图29B所示，第四阳极674可以通过第一百 八十四过孔V184与位于第六导电层的第五十四连接电极284电连接，从而可以通过位于第五导电层的第四十七连接电极277和位于第四导电层的第二十六连接电极256与第四像素电路的第六晶体管的第六有源层的第二区电连接。第五阳极675可以通过第一百八十五过孔V185与位于第六导电层的第五十五连接电极285电连接，从而可以通过位于第五导电层的第四十八连接电极278和位于第四导电层的第三十连接电极260与第五像素电路的第六晶体管的第六有源层的第二区电连接。第六阳极676可以通过第一百八十六过孔V186与位于第六导电层的第五十六连接电极286电连接，从而可以通过位于第五导电层的第四十九连接电极279和位于第四导电层的第三十二连接电极262与第六像素电路的第六晶体管的第六有源层的第二区电连接。
(14)、形成像素定义层。在一些示例中，在形成前述图案的衬底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)。
图30A为本公开至少一实施例的第一显示区形成像素定义层后的显示基板的局部放大示意图。在一些示例中，如图30A所示，第一显示区的单个显示岛区的像素定义层可以形成第一像素开口OP1、第二像素开口OP2和第三像素开口OP3。第一像素开口OP1可以暴露出第一阳极671的表面，第二像素开口OP2可以暴露出第二阳极672的表面，第三像素开口OP3可以暴露出第三阳极673的表面。
图30B为本公开至少一实施例的第二显示区形成像素定义层后的显示基板的局部放大示意图。在一些示例中，如图30B所示，第二显示区的像素定义层可以形成多个像素开口(例如包括第四像素开口OP4至第六像素开口OP6)。第四像素开口OP4可以暴露出第四阳极674的表面，第五像素开口OP5可以暴露出第五阳极675的表面，第六像素开口OP6可以暴露出第六阳极676的表面。
(15)、形成有机发光层、阴极层和封装层。在一些示例中，在前述形成的像素开口内可以形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极层，阴极层分别与有机发光层和第二电源线电连接。随后，在阴极层上形成封装层，封装 层可以包括无机材料/有机材料/无机材料的叠层结构。
图31为图30A中沿Q-Q’方向的局部剖面示意图。在一些示例中，如图31所示，在垂直于显示基板的方向上，第一显示区的单个显示岛区可以包括：衬底101、以及设置在衬底101上的驱动电路层102和发光结构层103。驱动电路层102可以包括：第一导电层21、第一绝缘层201、第一半导体层27、第二绝缘层202、第二导电层22、第三绝缘层203、第二半导体层28、第四绝缘层204、第三导电层23、第五绝缘层205、第四导电层24、第六绝缘层206、第五导电层25、第七绝缘层207和第六导电层26。驱动电路层102和发光结构层103之间设置第八绝缘层208。发光结构层103可以包括：阳极层301、像素定义层302、有机发光层和阴极层。关于每个膜层的结构如前所示，故于此不再赘述。
在一些示例性实施方式中，第一导电层至第六导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层至第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第六绝缘层至第八绝缘层还可以称为平坦层，可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极层可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例提供的显示基板，通过调整显示岛区的走线可以降低显示岛区的四个角区域的布线空间，使得显示岛区为圆形或椭圆形，从而降低显示基板的衍射不良，例如可以改善显示基板下方的摄像头的拍摄效果；而且可以增加透光区的面积，从而提高第一显示区的光透过率。而且，显示基板的第二显示区采用奇偶行第二区域像素电路连接不同的数据线，可以保证数据信号匹配像素电路的寄生电容。第一显示区的布线可以与第二显示区的布线保持一致，并将多条数据线围绕第一区域像素电路的外围，以减小穿过显示岛区的数据线对第一区域像素电路的干扰。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，可以无需设置第一导电层。然而，本实施例对此并不限定。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图32A为本公开至少一实施例的第一显示区的局部示意图。图32B为公开至少一实施例的第一显示区形成黑矩阵之后的显示基板的局部示意图。图32C为图32B中的黑矩阵的示意图。图32A中示意了多个第一像素单元的阳极层(例如包括第一发光元件的第一阳极671、第二发光元件的第二阳极672和第三发光元件的第三阳极673)和像素定义层的像素开口(例如第一像素开口OP1、第二像素开口OP2和第三像素开口OP3)。
在一些示例中，黑矩阵105可以位于封装层远离衬底的一侧。例如，可以在第一显示区和第二显示区均设置黑矩阵，或者可以仅在第一显示区设置黑矩阵。在第一显示区，黑矩阵105可以位于连接区和显示岛区。黑矩阵105在衬底的正投影与透光区可以没有交叠。显示岛区的黑矩阵105可以包括：第一矩阵开口105a、第二矩阵开口105b和第三矩阵开口105c。第一像素开口OP1在衬底的正投影可以位于第一矩阵开口105a在衬底的正投影范围内。第二像素开口OP2在衬底的正投影可以位于第二矩阵开口105b在衬底的正投影范围内。第三像素开口OP3在衬底的正投影可以位于第三矩阵开口105c在衬底的正投影范围内。第一矩阵开口105a在衬底的正投影可以位于第一阳极671在衬底的正投影范围内。第二矩阵开口105b在衬底的正投影可以位于第二阳极672在衬底的正投影范围内。第三矩阵开口105c在衬底的正投影可以位于第三阳极673在衬底的正投影范围内。在本示例中，显示岛区的阳极层可以覆盖黑矩阵105与像素定义层的像素开口之间的缝隙，可以避免缝隙漏光，降低缝隙带来的衍射。而且，连接区可以被黑矩阵覆盖，可以降低走线间缝隙带来的延伸。在另一些示例中，第二显示区的阳极层也可以覆盖黑矩阵与像素定义层的像素开口之间的缝隙。然而，本实施例对此并不限定。
在本示例中，黑矩阵可以覆盖显示岛区的非发光区域和连接区。透光区 的第一边缘和第二边缘的形状可以由黑矩阵的外围边缘形状确定。例如，透光区的第一边缘和第二边缘可以均为平坦边缘。或者，透光区的第一边缘和第二边缘可以为不平坦边缘，比如可以存在公差导致的一些小变形。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图33为本公开至少一实施例的显示装置的示意图。如图33所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的发光结构层的出光侧的感光传感器92。感光传感器92位于显示基板91的非显示面一侧。感光传感器92在显示基板91上的正投影与第一显示区A1存在交叠。
在一些示例性实施方式中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为具有图像(包括静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。例如，显示装置可以是：显示器、电视机、广告牌、数码相框、具有显示功能的激光打印机、电话、手机、画屏、个人数字助理(PDA，Personal Digital Assistant)、数码相机、便携式摄录机、取景器、导航仪、车辆、大面积墙壁、信息查询设备(比如电子政务、银行、医院、电力等部门的业务查询设备)、监视器等中的任一种产品。又如，显示装置还可以是微显示器，包含微显示器的VR设备或AR设备等中的任一种产品。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (22)

  1. 一种显示基板，包括：第一显示区，所述第一显示区包括：彼此隔开的多个显示岛区、位于相邻显示岛区之间的透光区以及连接相邻显示岛区的连接区；
    所述显示岛区包括：设置在衬底上的第一像素单元，所述第一像素单元包括：第一区域像素电路和与所述第一区域像素电路电连接的第一区域发光元件；所述第一区域像素电路在所述衬底的正投影与电连接的所述第一区域发光元件在所述衬底的正投影存在交叠；
    所述显示岛区具有弧形边缘。
  2. 根据权利要求1所述的显示基板，其中，所述显示岛区为圆形或椭圆形。
  3. 根据权利要求1或2所述的显示基板，其中，所述透光区的边缘包括：与所述连接区接触的第一边缘、以及与所述显示岛区接触的第二边缘；所述第一边缘与所述第二边缘间隔连接，所述第二边缘为弧形。
  4. 根据权利要求3所述的显示基板，其中，所述透光区为八边形。
  5. 根据权利要求3或4所述的显示基板，其中，所述第一边缘为直线型、波浪型或者折线型。
  6. 根据权利要求1至5中任一项所述的显示基板，其中，所述显示岛区包括一个第一像素单元，所述第一像素单元包括：三个第一区域发光元件；所述三个第一区域发光元件包括：出射第一颜色光的第一发光元件、出射第二颜色光的第二发光元件、以及出射第三颜色光的第三发光元件。
  7. 根据权利要求6所述的显示基板，其中，所述第一发光元件、所述第二发光元件和所述第三发光元件的发光区域整体组成圆形或椭圆形。
  8. 根据权利要求6或7所述的显示基板，其中，所述第一像素单元还包括：三个第一区域像素电路，所述三个第一区域像素电路和所述三个第一区域发光元件一一对应电连接；
    所述三个第一区域像素电路沿第一方向依次排布；所述第一发光元件和第二发光元件在第二方向上依次排布，所述第三发光元件在所述第一方向上 位于所述第一发光元件和第二发光元件的同一侧；其中，所述第一方向与所述第二方向交叉。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述显示岛区还包括：多条数据线；所述第一区域像素电路与一条数据线电连接，且所述第一区域像素电路在所述衬底的正投影与两条数据线在所述衬底的正投影存在交叠；
    所述多条数据线中的至少一条数据线围绕在所述第一像素单元的全部第一区域像素电路的外侧。
  10. 根据权利要求9所述的显示基板，其中，所述第一像素单元包括三个第一区域像素电路；所述三个第一区域像素电路包括沿第一方向依次排布的第一像素电路、第二像素电路和第三像素电路；
    所述显示岛区包括：沿所述第一方向依次排布的第一数据线至第十二数据线；
    所述第一数据线至第三数据线在所述第一方向上位于所述三个第一区域像素电路的一侧，第十数据线至第十二数据线在所述第一方向上位于所述三个第一区域像素电路的另一侧；
    所述第一像素电路与第四数据线电连接，且所述第一像素电路在所述衬底的正投影与所述第四数据线和第五数据线在所述衬底的正投影存在交叠；
    所述第二像素电路与第六数据线电连接，且所述第二像素电路在所述衬底的正投影与所述第六数据线和第七数据线在所述衬底的正投影存在交叠；
    所述第三像素电路与第八数据线电连接，且所述第三像素电路在所述衬底的正投影与所述第八数据线和第九数据线在衬底的正投影存在交叠。
  11. 根据权利要求10所述的显示基板，其中，所述第一数据线至第三数据线、第十数据线至第十二数据线均为在所述第一方向往远离所述第一区域像素电路的方向弯曲的弧状走线，其中，所述第一数据线至第三数据线的弯曲方向不同于所述第十数据线至第十二数据线的弯曲方向。
  12. 根据权利要求10或11所述的显示基板，其中，所述第一数据线至第三数据线、所述第十数据线至第十二数据线为同层结构，且位于第四数据 线至第九数据线远离所述衬底的一侧。
  13. 根据权利要求9至12中任一项所述的显示基板，其中，所述第一区域像素电路包括：至少一个第一类型晶体管、至少一个第二类型晶体管、以及存储电容，所述第一类型晶体管和第二类型晶体管的晶体管类型不同。
  14. 根据权利要求13所述的显示基板，其中，在垂直于显示基板的方向上，所述第一显示区至少包括：衬底以及设置在所述衬底上的第一半导体层、第二导电层、第二半导体层、第三导电层、第四导电层、第五导电层和第六导电层；
    所述第一半导体层至少包括：所述第一区域像素电路的第一类型晶体管的有源层；
    所述第二导电层至少包括：所述第一区域像素电路的第一类型晶体管的栅极；
    所述第二半导体层至少包括：所述第一区域像素电路的第二类型晶体管的有源层；
    所述第三导电层至少包括：所述第一区域像素电路的第二类型晶体管的栅极；
    所述第四导电层至少包括：所述第一区域像素电路电连接的多条扫描信号线；
    所述第五导电层至少包括：与所述第一区域像素电路电连接或交叠的多条数据线；
    所述第六导电层至少包括：位于所述第一区域像素电路外围的多条数据线。
  15. 根据权利要求14所述的显示基板，其中，所述第一半导体层、所述第二导电层、所述第二半导体层、所述第三导电层、所述第四导电层、所述第五导电层和所述第六导电层依次设置在所述衬底上。
  16. 根据权利要求14或15所述的显示基板，其中，所述显示岛区的第六导电层还包括：传输第一电压信号的电源传输线、传输第二电压信号的电源传输线、传输第一初始信号的初始传输线、以及传输第二初始信号的初始 传输线。
  17. 根据权利要求1至16中任一项所述的显示基板，还包括：位于所述第一显示区至少一侧的第二显示区；所述第二显示区包括：设置在所述衬底上的第二像素单元，所述第二像素单元包括：第二区域像素电路和与所述第二区域像素电路电连接的第二区域发光元件；所述第二区域像素电路在所述衬底的正投影与电连接的所述第二区域发光元件在所述衬底的正投影存在交叠；
    其中，所述第一显示区的第一像素单元的密度小于所述第二显示区的第二像素单元的密度。
  18. 根据权利要求17所述的显示基板，其中，所述第二显示区的两行第二像素单元与所述第一显示区的一行第一像素单元对应，所述第二显示区的两列第二像素单元与所述第一显示区的一列第一像素单元对应。
  19. 根据权利要求17或18所述的显示基板，其中，所述第二显示区还包括：多条数据线，第2n行第j列的第二区域像素电路与第2n-1行第j列的第二区域像素电路连接不同的数据线，其中，n和j均为整数。
  20. 根据权利要求1至19中任一项所述的显示基板，其中，所述第一显示区还包括：像素定义层和位于所述像素定义层远离所述衬底一侧的黑矩阵；
    所述显示岛区的像素定义层具有像素开口，所述像素开口暴露出第一区域发光元件的阳极的部分；所述黑矩阵具有矩阵开口；所述矩阵开口在所述衬底的正投影覆盖所述像素开口在所述衬底的正投影，所述第一区域发光元件的阳极在所述衬底的正投影覆盖所述矩阵开口在所述衬底的正投影。
  21. 根据权利要求20所述的显示基板，其中，所述黑矩阵覆盖所述连接区。
  22. 一种显示装置，包括如权利要求1至21中任一项所述的显示基板、以及位于所述显示基板的非显示面一侧的传感器，所述传感器在所述显示基板的正投影与所述显示基板的第一显示区存在交叠。
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