WO2024000310A1 - 透明显示面板及显示装置 - Google Patents

透明显示面板及显示装置 Download PDF

Info

Publication number
WO2024000310A1
WO2024000310A1 PCT/CN2022/102500 CN2022102500W WO2024000310A1 WO 2024000310 A1 WO2024000310 A1 WO 2024000310A1 CN 2022102500 W CN2022102500 W CN 2022102500W WO 2024000310 A1 WO2024000310 A1 WO 2024000310A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
line
substrate
display panel
signal
Prior art date
Application number
PCT/CN2022/102500
Other languages
English (en)
French (fr)
Inventor
刘冬妮
玄明花
张振宇
郑皓亮
张舜航
陈婉芝
齐琪
刘静
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102500 priority Critical patent/WO2024000310A1/zh
Priority to CN202280002075.6A priority patent/CN117642790A/zh
Priority to TW112115103A priority patent/TW202401398A/zh
Publication of WO2024000310A1 publication Critical patent/WO2024000310A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a transparent display panel and a display device.
  • Transparent display technology can not only present the image on the display screen, but also the physical object behind the display screen, and has broad application prospects.
  • Transparent display technology has been widely used in display windows, transparent TVs, vehicles, virtual displays (VR, Virtual Reality), augmented reality (AR, Augmented Reality) and other fields.
  • Embodiments of the present disclosure provide a transparent display panel and a display device.
  • embodiments of the present disclosure provide a transparent display panel, including: a substrate and a plurality of repeating units arranged in an array on the substrate.
  • the repeating unit includes: a non-light-transmitting area and a plurality of light-transmitting sub-areas, and adjacent light-transmitting sub-areas are separated by non-light-transmitting areas.
  • the non-light-transmitting area includes: at least one pixel unit, and N sets of first traces extending along the first direction and M sets of second traces extending along the second direction and electrically connected to the pixel unit.
  • the first direction intersects the second direction, N and M are both positive integers, and N and M are not greater than 1 at the same time.
  • At least one group of first traces includes: a plurality of first signal lines and at least one second signal line, and the at least one second signal line covers at least two first signal lines in an orthographic projection of the substrate.
  • a size of the at least one second signal line along the second direction is greater than a size of the at least two first signal lines along the second direction.
  • the at least one second signal line is located on a side of the at least two first signal lines away from the substrate.
  • a size of the at least one fourth signal line along the first direction is greater than a size of the at least two third signal lines along the first direction.
  • the at least one fourth signal line is located on a side of the at least two third signal lines away from the substrate.
  • the at least one second signal line or the at least one fourth signal line is a power line.
  • N and M are both 1.
  • a set of first traces includes a plurality of first signal lines
  • a set of second traces includes a plurality of third signal lines and at least one fourth signal line.
  • the at least one fourth signal line includes: a first power line and a second power line; at least one of the first power line and the second power line covers the plurality of third signal lines in an orthographic projection of the substrate. Three signal lines are in orthographic projection of the substrate.
  • a plurality of first signal lines of a group of first wirings include: scanning lines, light emitting control lines, first power connection lines, and second power connection lines; the first power connection lines and The first power line is electrically connected, and the second power connection line is electrically connected to the second power line.
  • the transparent display panel further includes: a shift scanning circuit; an orthographic projection of the at least one fourth signal line on the substrate overlaps with the shift scanning circuit.
  • the non-light-transmitting area of the repeating unit includes: three pixel units arranged sequentially along the first direction, and the set of second wiring lines is adjacent to the second pixel unit.
  • a set of first traces includes a plurality of first signal lines and at least one second signal line
  • a set of second traces includes a plurality of third signal lines.
  • the at least one second signal line includes: a first power line and a second power line; at least one of the first power line and the second power line covers at least two first power lines in an orthographic projection of the substrate.
  • the signal line is an orthographic projection of the substrate.
  • the plurality of first signal lines include: at least one scanning line and at least one light emitting control line electrically connected to the at least one pixel unit.
  • the plurality of third signal lines at least include: a plurality of data lines electrically connected to the at least one pixel unit.
  • the orthographic projection of the second power line on the substrate overlaps with the orthographic projection of the at least one pixel unit on the substrate, and the first power line is located on the substrate.
  • the second power line is away from the side of the pixel unit.
  • the at least one pixel unit includes: a plurality of sub-pixels emitting different colors, each sub-pixel includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element, and the first electrode of the light-emitting element passes through an anode.
  • the soldering pad is electrically connected to the pixel circuit, the second electrode of the light-emitting element is electrically connected to the cathode pad, and the cathode pad and the second power line have an integrated structure.
  • the first voltage signal provided by the first power line is greater than the second voltage signal provided by the second power line.
  • the repeating units are quadrilateral.
  • the non-light-transmitting area includes: two pixel units, a set of first wirings and a set of second wirings, the two pixel units are arranged along the first direction and There is a misalignment.
  • a set of first traces includes: a plurality of first signal lines, and the first signal lines include: first line segments extending along the first direction and sequentially connected first line segments extending along the second direction. the second line segment; both sets of second traces include: a plurality of third traces and at least one fourth trace, the orthographic projection of the at least one fourth trace on the substrate and the second trace of the plurality of first signal lines The line segments overlap in the orthographic projection of the substrate.
  • the at least one pixel unit includes: a plurality of sub-pixels emitting different colors, each sub-pixel includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element, and the light-emitting element of the sub-pixel is electrically connected to the light-emitting element.
  • the connected pixel circuits overlap in the orthographic projection of the substrate.
  • embodiments of the present disclosure provide a display device including the transparent display panel as described above.
  • FIG. 1 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a working timing diagram of the pixel circuit shown in Figure 1;
  • Figure 3 is a partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 5 is a partial cross-sectional view of a transparent display panel according to at least one embodiment of the present disclosure
  • FIG. 6A is a schematic diagram of a semiconductor layer of a repeating unit according to at least one embodiment of the present disclosure
  • Figure 6B is a schematic diagram of the first conductive layer of the repeating unit according to at least one embodiment of the present disclosure
  • Figure 6C is a schematic diagram of the second conductive layer of the repeating unit according to at least one embodiment of the present disclosure.
  • Figure 6D is a schematic diagram of the third insulating layer of the repeating unit according to at least one embodiment of the present disclosure.
  • Figure 6E is a schematic diagram of a third conductive layer of a repeating unit according to at least one embodiment of the present disclosure.
  • Figure 6F is a schematic diagram of a fifth insulating layer of a repeating unit according to at least one embodiment of the present disclosure.
  • Figure 6G is a schematic diagram of the fourth conductive layer of the repeating unit according to at least one embodiment of the present disclosure.
  • Figure 6H is a schematic diagram of a seventh insulating layer of a repeating unit according to at least one embodiment of the present disclosure
  • FIG. 7 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 9 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 11 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 13 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 15 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 16 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 17 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 18 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • Figure 19 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 20 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • components with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source or drain
  • the second pole can be is the drain or source.
  • the gate of the transistor can be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it may include a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it may include a state in which the angle is 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small differences caused by tolerances. Deformation can include leading angles, arc edges, deformation, etc.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • thickness and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.
  • a transparent display panel includes a light-transmitting area and a non-light-transmitting area.
  • light-transmitting areas and non-light-transmitting areas can be arranged alternately. If the area of some light-transmitting areas is too small and the distribution is periodic, based on the principle of small hole diffraction, diffraction will occur. The smaller the size of the light-transmitting area, the less diffraction will occur. The phenomenon becomes more obvious.
  • the resolution (PPI) of the transparent display panel increases, the area of each light-transmitting area will decrease, and strong ambient light will occur when passing through the transparent display panel. Diffraction, resulting in obvious ghosting when viewing the picture of the transparent display panel, reducing the display quality of the transparent display panel.
  • This embodiment provides a transparent display panel, including: a substrate and a plurality of repeating units arranged in an array on the substrate.
  • the repeating unit includes: a non-light-transmitting area and a plurality of light-transmitting sub-areas, and adjacent light-transmitting sub-areas are separated by a non-light-transmitting area.
  • the non-light-transmitting area includes: at least one pixel unit, and N groups of first wiring lines extending along the first direction and M groups of second wiring lines extending along the second direction that are electrically connected to the pixel unit.
  • the first direction intersects the second direction, for example, the first direction may be perpendicular to the second direction.
  • N and M are both positive integers, and N and M are not greater than 1 at the same time. For example, N and M can both be 1; or N can be 1 and M can be greater than 1; or M can be 1 and N can be greater than 1.
  • At least one set of first traces includes: a plurality of first signal lines and at least one second signal line.
  • the orthographic projection of at least one second signal line on the substrate covers the orthographic projection of at least two first signal lines on the substrate.
  • at least one set of second traces includes: a plurality of third signal lines and at least one fourth signal line.
  • the orthographic projection of at least one fourth signal line on the substrate covers the orthographic projection of at least two third signal lines on the substrate.
  • the multiple signal lines within each set of traces are aggregated. There is an overlay design between signal lines located on different film layers in a set of first traces or a set of second traces.
  • the superposition design of two structures means that the orthographic projections of the two structures overlap, and more than 90% of the orthographic projection of one structure can fall within the orthographic projection range of the other structure.
  • Aggregation design refers to the centralized arrangement of multiple signal lines. For example, among the multiple signal lines arranged in a centralized manner, the distance between two adjacent signal lines is less than 2 times the line width of any one of the two signal lines. times. The area between adjacent signal lines of the same film layer that adopts a polymeric design can be ignored and not included in the light transmission area. For example, the spacing between adjacent signal lines of a polymeric design located on the same film layer may be approximately 3 microns to 5 microns.
  • the non-light-transmitting area refers to an area with pixel units or signal traces that display images, and cannot transmit the background light on the back of the transparent display panel or has a low background light transmittance.
  • the light-transmitting area refers to an area that does not have pixel units and signal traces that display images, and can transmit the background light on the back of the transparent display panel or has a high background light transmittance.
  • the light-transmitting area of this disclosure does not include the area between adjacent signal lines using aggregation design. For example, the spacing between two adjacent signal lines exceeds at least 5 times the line width of any one of the two lines. Then the area between the two adjacent signal lines constitutes a light-transmitting area.
  • structure A extending along direction B means that structure A may include a main part and a secondary part connected to the main part.
  • the main part is generally in the shape of a strip extending in a certain direction, and the shape of the secondary part does not vary. limit, the main part is at least 60% of the structure A; the main part extends along direction B, and the size of the main part extending along direction B is greater than the size of the minor part extending along other directions.
  • structure A extends along direction B all means “the main part of structure A extends along direction B.”
  • the transparent display panel provided in this embodiment can use the superimposed design of the signal wiring to increase the light transmission area, reduce diffraction, and improve the display clarity while ensuring the transmittance of the transparent display panel, thereby improving the transparency of the transparent display panel. transmittance and display quality.
  • one pixel unit may include three sub-pixels.
  • the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
  • the shape of the subpixel may be a rectangle, a diamond, a pentagon, or a hexagon.
  • a pixel unit When a pixel unit includes three sub-pixels, the three sub-pixels can be sequentially spaced along a certain direction, or can be arranged in a Z-shaped manner; when a pixel unit includes four sub-pixels, the four sub-pixels can be sequentially spaced along a certain direction.
  • Set or set in an array However, this embodiment is not limited to this.
  • each sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the orthographic projection of the light-emitting element of the sub-pixel and the electrically connected pixel circuit on the substrate may overlap.
  • the area of the light-transmitting area can be increased and the light transmittance can be improved.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C structure, a 7T1C structure, a 5T1C structure, an 8T1C structure or an 8T2C structure, etc., where T in the above circuit structure refers to Thin film transistor, C refers to the capacitor, the number in front of T represents the number of thin film transistors in the circuit, and the number in front of C represents the number of capacitors in the circuit.
  • the light-emitting element may be an element with a light-emitting area no larger than 1 ⁇ 10 5 um 2 , such as a micro-light emitting diode (Micro-LED, Micro Light Emitting Diode), a mini-diode (Mini-LED), or an organic light-emitting diode.
  • Diode OLED, Organic Light Emitting Diode
  • QLED Quantum dot Light Emitting Diode
  • FIG. 1 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this example may adopt a 7T1C structure, that is, first to seventh transistors T1 to T7 and a storage capacitor Cst.
  • the gate electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.
  • the first transistor T1 may also be called a driving transistor.
  • the gate electrode of the second transistor T2 is electrically connected to the first scan line SL1, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the second node N2.
  • the second transistor T2 may also be called a data writing transistor.
  • the gate electrode of the third transistor T3 is electrically connected to the first scan line SL1, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the third node N3.
  • the third transistor T3 may also be called a threshold compensation transistor.
  • the gate electrode of the fourth transistor T4 is electrically connected to the light emitting control line EML, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the fourth node N4.
  • the gate electrode of the seventh transistor T7 is electrically connected to the light emission control line EML, the first electrode is electrically connected to the first power supply line VDD, and the second electrode is electrically connected to the second node N2.
  • the fourth transistor T4 and the seventh transistor T7 may also be called light emission control transistors.
  • the gate electrode of the fifth transistor T5 is electrically connected to the second scan line SL2, the first electrode is electrically connected to the initial signal line INIT, and the second electrode is electrically connected to the first node N1.
  • the gate electrode of the sixth transistor T6 is electrically connected to the second scan line SL2, the first electrode is electrically connected to the initial signal line INIT, and the second electrode is electrically connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 may also be called reset control transistors.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the first node N1, and the second capacitor plate is electrically connected to the first power line VDD.
  • the first electrode of the light-emitting element LD is electrically connected to the fourth node N4, and the second electrode is electrically connected to the second power supply line VSS.
  • the first electrode of the light-emitting element LD may be an anode, and the second electrode may be a cathode.
  • the first node N1 may be a connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the fifth transistor T5.
  • the second node N2 may be a connection point of the first transistor T1, the second transistor T2, and the seventh transistor T7.
  • the third node N3 may be a connection point of the first transistor T1, the third transistor T3, and the fourth transistor T4.
  • the fourth node N4 may be a connection point of the fourth transistor T4, the sixth transistor T6, and the light emitting element LD.
  • the first to seventh transistors T1 to T7 may all be P-type transistors, or all may be N-type transistors. Using the same type of transistors in pixel circuits can simplify the process flow, reduce the process difficulty of transparent display panels, and improve product yields. In some possible implementations, some of the first to seventh transistors T1 to T7 may be N-type transistors (for example, the third transistor T3 and the fifth transistor T5), and the remaining transistors may be P-type transistors.
  • the first power line VDD may be configured to provide a constant first voltage signal to the pixel circuit
  • the second power line VSS may be configured to provide a constant second voltage signal to the pixel circuit.
  • the first voltage signal may be greater than the second voltage signal.
  • the first scan line SL1 may be configured to provide the first scan signal S1 to the pixel circuit
  • the second scan line SL2 may be configured to provide the second scan signal S2 to the pixel circuit.
  • the second scan line electrically connected to the n-th row of pixel circuits may be electrically connected to the first scan line of the n-1th row of pixel circuits to receive the first scan signal S1(n-1), that is, the first scan line of the n-th row of pixel circuits.
  • the second scanning signal S2(n) may be the same as the first scanning signal S1(n-1), and n may be an integer greater than 0. In this way, the signal lines of the transparent display panel can be reduced and the narrow frame design of the transparent display panel can be achieved.
  • the data line DL may be configured to provide data signals to the pixel circuit.
  • the light emission control line EML may be configured to provide the light emission control signal EM to the pixel circuit.
  • the initial signal line INIT may be configured to provide an initial signal to the pixel circuit. The size of the initial signal may be between the first voltage signal and the second voltage signal, but is not limited thereto.
  • FIG. 2 is an operating timing diagram of the pixel circuit shown in FIG. 1 .
  • the pixel circuit shown in FIG. 1 includes a plurality of transistors that are all P-type transistors as an example for explanation.
  • the working process of the pixel circuit may include: a first period of time t1 , a second period of time t2 and a third period of time t3 .
  • the second scan line SL2 provides a low-level second scan signal S2, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the fifth transistor T5 is turned on, providing an initial signal to the first node N1, and initializing the first node N1;
  • the sixth transistor T6 is turned on, providing an initial signal to the fourth node N4, and initializing the fourth node N4.
  • the light-emitting control line EML provides a high-level light-emitting control signal EM, and the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the first scan line SL1 provides a high-level first scan signal S2, and the second transistor T2 and the third transistor T3 are turned off.
  • the first scan line SL1 provides a low-level first scan signal S1, the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 can be connected in a diode form through the third transistor T3. status.
  • the data line DL provides a data signal, and the data signal is transmitted to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3.
  • the first transistor T1 is in a diode-connected state such that the difference between the voltage of the data signal and the threshold voltage of the first transistor T1 is transmitted to the first node N1, and the voltage of the first node N1 is stored in the storage capacitor Cst. .
  • the first scan line SL1 provides a high-level first scan signal S1
  • the second scan line SL2 provides a high-level second scan signal S2
  • the emission control line EML provides a low-level emission control signal.
  • the fourth transistor T4 and the seventh transistor T7 are turned on, and the driving current flows from the first power supply line VDD to the second power supply line VSS through the seventh transistor T7, the first transistor T1, the fourth transistor T4 and the light-emitting element LD.
  • the drive current is controlled by the voltage of the first node N1, and the voltage of the data signal corresponds to the voltage of the threshold voltage of the first transistor T1.
  • the threshold voltage of the first transistor T1 can be offset, so that the drive current is consistent with the data signal.
  • the signal corresponds to and is independent of the threshold voltage shift of the first transistor T1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the first transistor T1.
  • FIG. 3 is a partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 3 is formed by the four repeating units shown in Figure 4 arranged in a 2 ⁇ 2 array.
  • the transparent display panel may include a plurality of repeating units 10 arranged in an array on a substrate.
  • the repeating unit 10 is generally quadrangular, such as a rectangle.
  • Each repeating unit 10 may include a non-light-transmitting region A1 and a plurality of light-transmitting sub-regions (for example, including: a first light-transmitting sub-region A21, a second light-transmitting sub-region A22, a third light-transmitting sub-region A23 and a fourth light-transmitting sub-region A23).
  • Photon area A24 adjacent light-transmitting sub-areas may be separated by a non-light-transmitting area A1.
  • the non-light-transmitting regions A1 of adjacent repeating units 10 can be connected; the light-transmitting sub-regions of adjacent repeating units 10 can be connected with each other.
  • the light-transmitting sub-regions of four repeating units 10 arranged in a 2 ⁇ 2 array can be connected to each other to form a larger light-transmitting region A2.
  • the light-transmitting sub-region A22 and the first light-transmitting sub-region A21 of the repeating unit in the second row and second column may be connected to form a larger light-transmitting region A2.
  • the light-transmitting area A2 may be surrounded by the non-light-transmitting area A1.
  • the total area of the light-transmissive sub-regions in a repeating unit may be greater than the area of the non-light-transmissive regions.
  • the total area of the light-transmitting area of the transparent display panel may account for greater than 45% of the total area of the transparent display panel, for example, may be approximately 48.5%, 79.3%, 82.1%, or 85%.
  • this embodiment is not limited to this.
  • the area ratio of the light-transmitting area can be set according to actual application requirements. The greater the area ratio of the light-transmitting area, the greater the transmittance of the transparent display panel, the higher the transparency of the transparent display panel, that is, the better the transparent display effect.
  • the non-light-transmitting area A1 of a repeating unit 10 may include: a pixel unit P and a set of first wirings 11 and a set of first wirings 11 electrically connected to the pixel unit P.
  • the group of first traces 11 may include: a plurality of first signal lines 111 extending along the first direction X.
  • the plurality of first signal lines 111 may be arranged sequentially along the second direction Y.
  • the plurality of first signal lines 111 may have the same layer structure.
  • the set of second traces 12 may include: a plurality of third signal lines 121 and a plurality of fourth signal lines 122 extending along the second direction Y.
  • the plurality of third signal lines 121 may be arranged in sequence along the first direction X, and the plurality of fourth signal lines 122 may be arranged in sequence along the first direction X.
  • the plurality of third signal lines 121 may have the same layer structure, and the plurality of fourth signal lines 122 may have the same layer structure.
  • the plurality of fourth signal lines 122 may be located on a side of the plurality of third signal lines 121 away from the substrate.
  • the orthographic projection of at least one fourth signal line 122 on the substrate may cover the orthographic projection of at least two third signal lines 121 on the substrate.
  • the orthographic projection of one fourth signal line 122 on the substrate may cover the orthographic projection of two third signal lines 121 on the substrate.
  • the plurality of fourth signal lines 122 of the group of second traces 12 may include: a first power line and a second power line.
  • the second power supply line may be located on a side of the first power supply line close to the pixel unit P in the first direction X.
  • the second power supply line may be adjacent to the pixel unit P, and the first power supply line may be located on a side of the second power supply line away from the pixel unit P.
  • multiple repeating units 10 are arranged in an array so that the non-light-transmitting areas A1 of adjacent repeating units 10 can be connected.
  • the plurality of first signal lines 111 in the non-light-transmitting areas A1 of the repeating units 10 adjacent along the first direction The third signal lines 121 may be connected correspondingly, and the plurality of fourth signal lines 122 may be connected correspondingly.
  • the plurality of first signal lines 111 can transmit signals along the first direction X
  • the plurality of third signal lines 121 and the plurality of fourth signal lines 122 can transmit signals along the second direction Y.
  • a pixel unit P in the non-light-transmitting area A1 of the repeating unit 10 may include: a first sub-pixel P1 that emits light of the first color, a first sub-pixel P1 that emits light of the second color.
  • the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 may be arranged in a Z-shaped manner.
  • the first color light may be red light
  • the second color light may be blue light
  • the third color light may be green light.
  • this embodiment is not limited to this.
  • the first sub-pixel P1 may include: a first pixel circuit and a first light-emitting element electrically connected to the first pixel circuit.
  • the second sub-pixel P2 may include: a second pixel circuit and a second light-emitting element electrically connected to the second pixel circuit.
  • the third sub-pixel P3 may include: a third pixel circuit and a third light-emitting element electrically connected to the third pixel circuit.
  • the orthographic projection of the first light-emitting element on the substrate overlaps with the orthographic projection of the first pixel circuit on the substrate.
  • the orthographic projection of the second light-emitting element on the substrate overlaps with the orthographic projection of the second pixel circuit on the substrate.
  • the orthographic projection of the third light-emitting element on the substrate overlaps with the orthographic projection of the third pixel circuit on the substrate.
  • the first pixel circuit, the second pixel circuit and the third pixel circuit may have a 7T1C structure as shown in Figure 1, and the first light-emitting element, the second light-emitting element and the third light-emitting element may have a light-emitting area of no more than 1 ⁇ 10
  • the 5 um 2 component may be a Micro-LED, for example.
  • the pixel circuit and the corresponding electrically connected light-emitting element adopt a stacked design, which can reduce the area of the non-light-transmitting area A1 and increase the pixel aperture ratio, thereby increasing the area of the light-transmitting area.
  • the size of the first transistor in the pixel circuit electrically connected to the light-emitting elements that emit light of different colors may be different.
  • the channel width-to-length ratio ie, the ratio of the size along the first direction to the size along the second direction
  • the channel width-to-length ratio of the first transistor of the pixel circuit electrically connected to the light-emitting element that emits red light may be greater than that of the pixel circuit that emits blue light or green light.
  • FIG. 5 is a partial cross-sectional view of a transparent display panel according to at least one embodiment of the present disclosure.
  • the non-light-transmitting area A1 of the repeating unit may include: a substrate 100 , and a circuit structure layer 21 sequentially disposed on the substrate 100 .
  • the circuit structure layer 21 may include at least a plurality of pixel circuits (eg, a first pixel circuit, a second pixel circuit, and a third pixel circuit).
  • the circuit structure layer 21 may include: a semiconductor layer 210, a first conductive layer 211, a second conductive layer 212, a third conductive layer 213 and a fourth conductive layer 214 which are sequentially disposed on the substrate 100.
  • semiconductor layer 210 may include an active layer of transistors of a plurality of pixel circuits.
  • the first conductive layer 211 may include at least: gates of transistors of a plurality of pixel circuits and a capacitor plate of a storage capacitor.
  • the second conductive layer 212 may include at least another capacitor plate of storage capacitors of the plurality of pixel circuits.
  • the third conductive layer 213 may include at least a plurality of connection electrodes.
  • the fourth conductive layer 214 may include at least a first conductive part, a second conductive part, and a second power line VSS.
  • a first insulating layer 101 may be disposed between the semiconductor layer 210 and the first conductive layer 211
  • a second insulating layer may be disposed between the first conductive layer 211 and the second conductive layer 212 .
  • Layer 102, a third insulating layer 103 may be disposed between the second conductive layer 212 and the third conductive layer 213, and a fourth insulating layer 104 and a fifth insulating layer may be disposed between the third conductive layer 213 and the fourth conductive layer 214.
  • a sixth insulating layer 106 and a seventh insulating layer 107 may be provided on the side of the fourth conductive layer 214 away from the substrate 100 .
  • the first to fourth insulating layers 101 to 104 and the sixth insulating layer 106 may be inorganic insulating layers, and the fifth insulating layer 105 and the seventh insulating layer 107 may be organic insulating layers.
  • this embodiment is not limited to this.
  • the light-emitting structure layer 22 may include a plurality of light-emitting elements (eg, a first light-emitting element, a second light-emitting element, and a third light-emitting element).
  • the light-emitting element may include: a light-emitting part 220 , a first electrode 221 and a second electrode 222 connected to the light-emitting part 220 .
  • the first electrode 221 is connected to the first end of the light-emitting part 220
  • the second electrode 222 is connected to the second end of the light-emitting part 220 .
  • the first electrode 221 of the light-emitting element may be an anode
  • the second electrode 222 may be a cathode.
  • the first electrode 221 may be electrically connected to the pixel circuit through the first conductive part
  • the second electrode 222 may be electrically connected to the second power supply line VSS through the second conductive part.
  • a protective layer 23 may also be provided on the side of the light-emitting element away from the substrate 100 to prevent the light-emitting element from falling off due to external force (such as scratches) during subsequent manufacturing or transportation.
  • the material of protective layer 23 can be silica gel.
  • the light-transmitting area A2 may include: a substrate 100 , and first to sixth insulating layers 101 to sixth insulating layers sequentially provided on the substrate 100 106 and covering layer 23.
  • the seventh insulating layer 107 can be hollowed out in the light-transmitting area A2 to improve the light transmittance of the light-transmitting area A2.
  • this embodiment is not limited to this.
  • the fifth insulating layer and the seventh insulating layer may be hollowed out in the light-transmitting area A2 to further improve the light transmittance of the light-transmitting area A2.
  • the following is an exemplary description through the preparation process of a transparent display panel.
  • the "patterning process” or “patterning process” mentioned in this disclosure includes coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes.
  • For organic materials this includes processes such as coating organic materials, mask exposure, and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • E and F are arranged on the same layer means that E and F are formed at the same time through the same patterning process or the distance between the surfaces of E and F close to the substrate and the substrate is basically the same, or E and F The surface close to the substrate is in direct contact with the same film layer.
  • the "thickness" of a film is the dimension of the film in a plane perpendicular to the substrate.
  • the orthographic projection of E includes the orthographic projection of F means that the boundary of the orthographic projection of E falls within the boundary range of the orthographic projection of F, or that the boundary of the orthographic projection of E is consistent with the orthographic projection of F. The projected boundaries overlap.
  • the preparation process of the transparent display panel may include the following operations.
  • the substrate may be a rigid substrate, such as a glass substrate or a quartz substrate, or may be a flexible substrate, such as an organic resin substrate.
  • the substrate may be a glass substrate.
  • this embodiment is not limited to this.
  • a semiconductor film is deposited on the substrate, the semiconductor film is patterned through a patterning process, and a semiconductor layer is formed in the non-light-transmitting area.
  • the semiconductor layer of the non-light-transmitting region of the repeating unit may at least include: an active layer of a plurality of transistors of a plurality of pixel circuits (for example, including: an active layer of a first transistor of a first pixel circuit).
  • the third active layer 330 and the fifth active layer 350 of the first pixel circuit may be an integrated structure
  • the third active layer 430 and the fifth active layer 450 of the second pixel circuit may be an integrated structure
  • the third active layer 330 and the fifth active layer 350 of the second pixel circuit may be an integrated structure
  • the third active layer 530 and the fifth active layer 550 of the pixel circuit may be an integrated structure.
  • the semiconductor layer may use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p -Si), hexathiophene, polythiophene and other one or more materials, that is, the present disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology and organic technology.
  • the material of the semiconductor layer may be polycrystalline silicon (p-Si).
  • this embodiment is not limited to this.
  • a first insulating film is deposited on the substrate forming the foregoing structure, and the first insulating film is patterned through a patterning process to form a first insulating layer covering the semiconductor layer. Subsequently, a first conductive film is deposited, and the first conductive film is patterned through a patterning process to form a first conductive layer in the non-light-transmitting area.
  • FIG. 6B is a schematic diagram of a first conductive layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the first conductive layer of the non-light-transmitting region of the repeating unit may at least include: gates of multiple transistors of multiple pixel circuits and a capacitor plate of a storage capacitor (for example, including: The gate electrode 311 of the first transistor, the gate electrode 321 of the second transistor, the gate electrode 331 of the third transistor, the gate electrode 341 of the fourth transistor, the gate electrode 351 of the fifth transistor, and the gate electrode of the sixth transistor of the first pixel circuit
  • the gate electrode 341 of the fourth transistor and the gate electrode 371 of the seventh transistor of the first pixel circuit may be an integral structure
  • the gate electrode 321 of the second transistor and the gate electrode of the third transistor may be an integral structure
  • 331 may be of an integrated structure
  • the gate electrode 351 of the fifth transistor and the gate electrode 361 of the sixth transistor may be of an integrated structure.
  • the first to seventh transistors of the first pixel circuit may all be double-gate transistors.
  • the gate electrode 441 of the fourth transistor and the gate electrode 471 of the seventh transistor of the second pixel circuit may be of an integrated structure
  • the gate electrode 421 of the second transistor and the gate electrode 431 of the third transistor may be of an integrated structure
  • the gate electrode of the fifth transistor may be of an integrated structure
  • the electrode 451 and the gate electrode 461 of the sixth transistor may have an integrated structure.
  • the first to seventh transistors of the second pixel circuit may all be double-gate transistors.
  • the gate electrode 541 of the fourth transistor and the gate electrode 571 of the seventh transistor of the third pixel circuit may be of an integrated structure
  • the gate electrode 521 of the second transistor and the gate electrode 531 of the third transistor may be of an integrated structure
  • the gate electrode of the fifth transistor may be of an integrated structure.
  • the electrode 551 and the gate electrode 561 of the sixth transistor may have an integrated structure.
  • the first to seventh transistors of the third pixel circuit may all be double-gate transistors.
  • the use of a double-gate transistor can enhance the driving capability, increase the current saturation of the light-emitting element, and prevent and reduce the occurrence of leakage current.
  • the second power connection line 602, the light emitting control line EML(n), the first scan line SL1(n), the second scan line SL2(n) and the first power connection line 601 They can be arranged sequentially along the second direction Y and extend along the first direction X.
  • the second power connection line 602, the light emission control line EML(n), the first scan line SL1(n), the second scan line SL2(n) and the first power connection line 601 may be located at the first pixel in the second direction Y. circuit and the second pixel circuit.
  • the first power connection line 601 and the second capacitor plate 582 of the storage capacitor of the third pixel circuit may be an integral structure.
  • the light emission control line EML(n) and the gate electrode 571 of the seventh transistor and the gate electrode 541 of the fourth transistor of the third pixel circuit may have an integrated structure.
  • the first scan line SL1(n) and the gate electrode 521 of the second transistor and the gate electrode 531 of the third transistor of the third pixel circuit may have an integrated structure.
  • the second scan line SL2(n) and the gate electrode 551 of the fifth transistor and the gate electrode 561 of the sixth transistor of the third pixel circuit may have an integrated structure.
  • this embodiment is not limited to this.
  • a second insulating film is deposited on the substrate forming the foregoing structure, and the second insulating film is patterned through a patterning process to form a second insulating layer covering the first conductive layer; subsequently, a second conductive layer is deposited The second conductive film is patterned through a patterning process to form a second conductive layer in the non-light-transmitting area.
  • FIG. 6C is a schematic diagram of a second conductive layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the second conductive layer of the non-transmissive area of the repeating unit may at least include: another capacitor plate of storage capacitors of the plurality of pixel circuits (for example, include: storage capacitors of the first pixel circuit).
  • a third insulating film is deposited on the substrate forming the foregoing structure, and the third insulating film is patterned through a patterning process to form a third insulating layer.
  • FIG. 6D is a schematic diagram of a third insulating layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the third insulating layer of the non-transmissive area of the repeating unit is provided with a plurality of via holes, which may include, for example: first via holes V1 to 46 that expose the surface of the semiconductor layer. Via V46, 51st to 82nd vias V51 to 82nd vias V82 exposing the surface of the first conductive layer, 91st to 93rd vias V91 to 93rd vias exposing the surface of the second conductive layer V93.
  • a third conductive film is deposited on the substrate forming the foregoing structure, the third conductive film is patterned through a patterning process, and a third conductive layer is formed in the non-light-transmitting area.
  • FIG. 6E is a schematic diagram of a third conductive layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the third conductive layer of the non-light-transmitting region of the repeating unit may at least include: a plurality of connection electrodes (for example, the eleventh connection electrode 701 to the thirty-seventh connection electrode 727 ), The third capacitor plate 383 of the first pixel circuit, the third capacitor plate 483 of the second pixel circuit, the third capacitor plate 583 of the third pixel circuit, a plurality of data lines (for example, data lines DL1 to DL3 ), and the initial signal line INIT.
  • the data lines DL1 to DL3 and the initial signal line INIT may be adjacent and arranged in sequence along the first direction X, and all extend along the second direction Y.
  • the data lines DL1 to DL3 and the initial signal line INIT may be located on a side of the first pixel circuit and the second pixel circuit away from the third pixel circuit in the first direction X.
  • the orthographic projection of the data lines DL1 to DL3 located on the third conductive layer and the initial signal line INIT on the substrate can be connected with the light emitting control line EML(n), the first scan line SL1(n), the first scan line SL1(n), the The two scan lines SL2(n), the first power connection line 601 and the second power connection line 602 overlap in the orthographic projection of the substrate.
  • the eleventh connection electrode 701 may be connected to the first pixel circuit through three first via holes V1 arranged side by side and three third via holes V3 arranged side by side.
  • the seventh active layer 370 of the seven transistors is electrically connected, and can also be electrically connected to the second capacitor plate 382 through two fifty-eighth vias V58 arranged vertically.
  • the eleventh connection electrode 701 and the third capacitor plate 383 may have an integrated structure.
  • the twelfth connection electrode 702 may be electrically connected to the first active layer 310 of the first transistor of the first pixel circuit through six sixth via holes V6 arranged side by side and six eighth via holes V8 arranged side by side, or may be It is electrically connected to the seventh active layer 370 of the seventh transistor through three second via holes V2 arranged side by side, and it is also electrically connected to the second active layer 320 of the second transistor through the fifth via hole V5.
  • the thirteenth connection electrode 703 can be electrically connected to the first active layer 310 of the first transistor through six seventh via holes V7 arranged side by side, and can also be electrically connected to the fourth transistor through three tenth via holes V10 arranged side by side.
  • the fourth active layer 340 is electrically connected, and can also be electrically connected to the third active layer 330 of the third transistor through the twelfth via V12.
  • the fourteenth connection electrode 704 may be electrically connected to the fourth active layer 340 of the fourth transistor through three ninth via holes V9 and three eleventh via holes V11 arranged side by side, and may also be electrically connected through the fifteenth via hole V9
  • the via V15 is electrically connected to the sixth active layer 360 of the sixth transistor.
  • the fifteenth connection electrode 705 may be electrically connected to the second active layer 320 of the second transistor through the fourth via hole V4, and may also be electrically connected to the first connection electrode 401 through the fifty-second via hole V52.
  • the first connection electrode 401 may be electrically connected to the first data line DL1 through the fifty-third via hole V53.
  • the sixteenth connection electrode 706 can be electrically connected to the gate electrode 311 of the first transistor through the fifty-first via hole V51, and can also be electrically connected to the fifth active layer 350 of the fifth transistor through the thirteenth via hole V13. It can be electrically connected to the first capacitor plate 381 of the storage capacitor through the ninety-first via hole V91, and can also be electrically connected to the second connection electrode 402 through the fifty-seventh via hole V57.
  • the seventeenth connection electrode 707 can be electrically connected to the fifth active layer 350 of the fifth transistor through the fourteenth via hole V14, and can also be electrically connected to the sixth active layer 360 of the sixth transistor through the sixteenth via hole V16. , and can also be electrically connected to the third connection electrode 403 through the sixtieth via hole V60.
  • the third connection electrode 403 can be electrically connected to the initial signal line INIT through the two fifty-ninth via holes V59 arranged in a vertical row, and can also be electrically connected to the thirty-seventh connection electrode 727 through the sixty-first via hole V61.
  • the eighteenth connection electrode 708 may be connected to the second pixel circuit through three seventeenth via holes V17 arranged side by side and a nineteenth via hole V19 arranged side by side.
  • the seventh active layer 470 of the seven transistors is electrically connected to the second capacitor plate 382 of the storage capacitor of the second pixel circuit through the two sixty-fourth vias V64 arranged side by side.
  • the two seventy-eighth via holes V78 are electrically connected to the first power connection line 601.
  • the eighteenth connection electrode 708 and the third capacitor plate 483 of the second pixel circuit may have an integrated structure.
  • the eighteenth connection electrode 708 and the eleventh connection electrode 701 may have an integrated structure.
  • the nineteenth connection electrode 709 can be electrically connected to the seventh active layer 470 through three eighteenth via holes V18 arranged side by side, and can also be electrically connected to the first active layer 410 through two twentieth via holes V20 arranged side by side.
  • the electrical connection can also be electrically connected to the second active layer 420 through the twenty-third via hole V23.
  • the twentieth connection electrode 710 may be electrically connected to the fourth active layer 440 through the three twenty-fourth via holes V24 arranged side by side and the three twenty-sixth via holes V26 arranged side by side, and may also be connected through the thirtieth via hole V26 arranged side by side.
  • the hole V30 is electrically connected to the sixth active layer 460.
  • the twenty-first connection electrode 711 can be electrically connected to the first active layer 410 through two twenty-first via holes V21 arranged side by side, and can also be electrically connected to the fourth active layer 410 through three twenty-fifth via holes V25 arranged side by side.
  • the source layer 440 is electrically connected, and can also be electrically connected to the third active layer 430 through the twenty-seventh via hole V27.
  • the twenty-second connection electrode 712 may be electrically connected to the second active layer 420 through the twenty-second via hole V22, and may also be electrically connected to the fourth connection electrode 404 through the sixty-seventh via hole V67.
  • the fourth connection electrode 404 may be electrically connected to the data line DL2 through the sixty-sixth via hole V66.
  • the twenty-third connection electrode 713 can be electrically connected to the gate electrode 411 of the first transistor through the sixty-first via hole V61, and can also be electrically connected to the fifth active layer 450 of the fifth transistor through the twenty-eighth via hole V28. , can also be electrically connected to the fifth connection electrode 405 through the sixty-fifth via hole V65, and can also be electrically connected to the first capacitor plate 481 of the storage capacitor through the ninety-second via hole V92.
  • the twenty-fourth connection electrode 714 can be electrically connected to the fifth active layer 450 through the twenty-ninth via hole V29, and can also be electrically connected to the sixth active layer 460 through the thirty-first via hole V31.
  • the two sixty-ninth via holes V69 provided are electrically connected to the sixth connection electrode 406 .
  • the twenty-fifth connection electrode 715 may be connected to the third via hole V32 through the three thirty-second via hole V32 arranged side by side and the three thirty-fourth via hole V34 arranged side by side.
  • the seventh active layer 570 of the three-pixel circuit is electrically connected, and can also be electrically connected to the second capacitor plate 582 of the storage capacitor through two 72nd vias V72 arranged side by side.
  • the twenty-fifth connecting electrode 715 and the third capacitor plate 583 may have an integrated structure.
  • the twenty-sixth connection electrode 716 can be electrically connected to the seventh active layer 570 through three thirty-third via holes V33 arranged side by side, and can also be electrically connected to the first active layer 570 through two thirty-seventh via holes V37 arranged side by side.
  • the source layer 510 is electrically connected and can also be electrically connected to the second active layer 520 through the thirty-sixth via hole V36.
  • the twenty-seventh connection electrode 717 can be electrically connected to the first active layer 510 through the two thirty-eighth via holes V38 arranged side by side, and can also be electrically connected to the fourth active layer 510 through the three fortieth via holes V40 arranged side by side.
  • the layer 540 is electrically connected and can also be electrically connected to the third active layer 530 through the forty-second via hole V42.
  • the twenty-eighth connection electrode 718 can be electrically connected to the fourth active layer 540 through the three thirty-ninth via holes V39 arranged side by side and the three forty-first via holes V41 arranged side by side, and can also be connected through the forty-first via hole V41 arranged side by side.
  • the fifth via hole V45 is electrically connected to the sixth active layer 560 .
  • the twenty-ninth connection electrode 719 can be electrically connected to the second active layer 520 through the thirty-fifth via hole V35, and can also be electrically connected to the seventh connection electrode 407 through the seventy-fifth via hole V75.
  • the seventh connection electrode 407 may be electrically connected to the data line DL3 through the seventy-sixth via hole V76.
  • the thirtieth connection electrode 720 can be electrically connected to the gate electrode 511 of the first transistor through the seventy-fourth via hole V74, and can also be electrically connected to the fifth active layer 550 through the forty-third via hole V43.
  • the seventy-third via hole V73 is electrically connected to the eighth connection electrode 408, and can also be electrically connected to the first capacitor plate 581 through the ninety-third via hole V93.
  • the thirty-first connection electrode 721 can be electrically connected to the sixth connection electrode 406 through the two seventy-first via holes V71 arranged side by side, and can also be electrically connected to the fifth active layer 550 through the forty-fourth via hole V44. It can also be electrically connected to the sixth active layer 560 through the forty-sixth via hole V46.
  • the thirty-second connection electrode 722 may be electrically connected to the first power connection line 601 through two seventy-seventh via holes V77 arranged side by side.
  • the thirty-third connection electrode 723 may be electrically connected to the second power connection line 602 through two eightieth via holes V80 arranged side by side.
  • the thirty-fourth connection electrode 724 can be electrically connected to the gate electrode 341 of the fourth transistor of the first pixel circuit through the fifty-fourth via hole V54, and can also be connected to the emission control line EML(n) through the seventy-ninth via hole V79.
  • the electrical connection may also be electrically connected to the gate 341 of the fourth transistor of the second pixel circuit through the sixty-eighth via V68.
  • the light emission control line EML(n) and the gate electrode 571 of the seventh transistor and the gate electrode 541 of the fourth transistor of the third pixel circuit may have an integrated structure.
  • the thirty-fifth connection electrode 725 can be electrically connected to the gate electrode 331 of the third transistor of the first pixel circuit through the fifty-fifth via hole V55, and can also be connected to the first scan line SL1(n through the eighty-first via hole V81 ) is electrically connected, and can also be electrically connected to the gate 431 of the third transistor of the second pixel circuit through the sixty-second via hole V62.
  • the first scan line SL1(n) and the gate electrode 521 of the second transistor and the gate electrode 531 of the third transistor of the third pixel circuit may have an integrated structure.
  • the thirty-sixth connection electrode 726 can be electrically connected to the gate electrode 361 of the sixth transistor of the first pixel circuit through the fifty-sixth via hole V56, and can also be connected to the second scan line SL2(n through the eighty-second via hole V82 ) is electrically connected, and can also be electrically connected to the gate 461 of the sixth transistor of the second pixel circuit through the sixty-third via hole V63.
  • the second scan line SL2(n) and the gate electrode 551 of the fifth transistor and the gate electrode 561 of the sixth transistor of the third pixel circuit may have an integrated structure.
  • the thirty-seventh connection electrode 727 may be electrically connected to the sixth connection electrode 406 through the seventieth via hole V70.
  • the initial signal can be transmitted through the initial signal line INIT, the third connection electrode 403, the thirty-seventh connection electrode 727, the sixth connection electrode 406, and the thirty-first connection electrode 721.
  • side-by-side arrangement means arrangement along the first direction X
  • vertical arrangement means arrangement along the second direction Y.
  • a fourth insulating film is deposited on the substrate forming the foregoing structure, and then a fifth insulating film is coated, and the fifth insulating film and the fourth insulating film are patterned through a patterning process to form a fifth insulating film. layer and the fourth insulating layer.
  • FIG. 6F is a schematic diagram of a fifth insulating layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the fifth insulating layer in the non-transmissive area of the repeating unit has multiple via holes, which may include, for example: the ninety-fourth via holes V94 to V94 that expose the surface of the third conductive layer.
  • the ninety-fourth via hole V94 may expose the surface of the fourteenth connection electrode 704 .
  • the ninety-fifth via hole V95 may expose the surface of the twentieth connection electrode 710 .
  • the ninety-sixth via hole V96 may expose the surface of the twenty-eighth connection electrode 718 .
  • the ninety-seventh via hole V97 may expose the surface of the thirty-second connection electrode 722 .
  • the ninety-eighth via hole V98 may expose the surface of the thirty-third connection electrode 723 .
  • a fourth conductive film is deposited on the substrate forming the foregoing structure, the fourth conductive film is patterned through a patterning process, and a fourth conductive layer is formed in the non-light-transmitting area.
  • FIG. 6G is a schematic diagram of a fourth conductive layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the fourth conductive layer of the non-light-transmitting area of the repeating unit may at least include: a first power line VDD, a second power line VSS, a first conductive part 301, a second conductive part 302 , the third conductive part 401, the fourth conductive part 402, the fifth conductive part 501, and the sixth conductive part 502.
  • the second power line VSS and the first power line VDD may extend along the second direction Y.
  • the first power supply line VDD may be located on a side of the second power supply line VSS away from the first pixel circuit and the second pixel circuit in the first direction X.
  • the second power line VSS and the second conductive part 302, the fourth conductive part 402 and the sixth conductive part 502 may have an integrated structure.
  • the area of the non-light-transmitting area can be reduced, thereby increasing the area of the light-transmitting area. area.
  • the front projection of the first power line VDD on the substrate may cover the front projection of the data lines DL1 and DL2 on the substrate, and the front projection of the second power line VSS on the substrate.
  • the orthographic projection of the data line DL3 and the initial signal line INIT on the substrate can be covered.
  • the first conductive part 301 may be electrically connected to the fourteenth connection electrode 704 through the ninety-fourth via hole V94 to achieve electrical connection with the first pixel circuit.
  • the third conductive portion 401 can be electrically connected to the twentieth connection electrode 710 through the ninety-fifth via hole V95, thereby achieving electrical connection with the second pixel circuit.
  • the fifth conductive part 501 may be electrically connected to the twenty-eighth connection electrode 718 through the ninety-sixth via hole V96, thereby achieving electrical connection with the third pixel circuit.
  • the sixth conductive portion 502 can be electrically connected to the thirty-third connection electrode 723 through the ninety-eighth via hole V98, thereby achieving electrical connection with the second power connection line 602.
  • the second power line VSS can be electrically connected to the second power connection line 602 through the sixth conductive portion 502 and the thirty-third connection electrode 723, thereby realizing a mesh transmission path of the second voltage signal.
  • the first power line VDD can be electrically connected to the thirty-second connection electrode 722 through the ninety-seventh via hole V97, thereby achieving electrical connection with the first power connection line 601.
  • the first power line VDD can be electrically connected to the first power connection line 601 through the thirty-second connection electrode 722, thereby realizing a mesh transmission path of the first voltage signal.
  • the resistances of the first power line and the second power line can be reduced.
  • a sixth insulating film is deposited on the substrate forming the foregoing structure, and then a seventh insulating film is coated, and the seventh insulating film and the sixth insulating film are patterned through a patterning process to form a seventh insulating film. layer and the sixth insulating layer.
  • FIG. 6H is a schematic diagram of a seventh insulating layer of a repeating unit according to at least one embodiment of the present disclosure.
  • the seventh insulating layer 107 of the non-transmissive area of the repeating unit may be provided with multiple openings, for example, may include first to sixth openings K1 to sixth openings that expose the surface of the fourth conductive layer. K6.
  • the first opening K1 can expose the surface of the second conductive part 302, and the area of the second conductive part 302 exposed by the first opening K1 can be used as a cathode pad, and is subsequently bonded and connected to the second electrode of the first light-emitting element.
  • the second opening K2 can expose the surface of the first conductive part 301, and the area of the first conductive part 301 exposed by the second opening K2 can be used as an anode pad, and is subsequently bonded and connected to the first electrode of the first light-emitting element.
  • the third opening K3 can expose the surface of the third conductive part 401, and the area of the third conductive part 401 exposed by the third opening K3 can be used as an anode pad, and is subsequently bonded and connected to the first electrode of the second light-emitting element.
  • the fourth opening K4 can expose the surface of the fourth conductive part 402, and the area of the fourth conductive part 402 exposed by the fourth opening K4 can be used as a cathode pad, and is subsequently bonded and connected to the second electrode of the second light-emitting element.
  • the fifth opening K5 can expose the surface of the fifth conductive part 501, and the area of the fifth conductive part 501 exposed by the fifth opening K5 can be used as an anode pad, and is subsequently bonded and connected to the first electrode of the third light-emitting element.
  • the sixth opening K6 can expose the surface of the sixth conductive part 502, and the area of the sixth conductive part 502 exposed by the sixth opening K6 can be used as a cathode pad, and is subsequently bonded and connected to the second electrode of the third light-emitting element.
  • the orthographic projection of the first opening K1 and the fourth opening K4 on the substrate may overlap with the orthographic projection of the second power line VSS on the substrate.
  • the non-light-transmitting area except the first to sixth openings K1 to K6 may be covered by the seventh insulating layer and the sixth insulating layer.
  • the seventh insulating layer in the light-transmitting sub-region (for example, the first to fourth light-transmitting sub-regions A21 to A24) other than the non-light-transmitting region of the repeating unit can be removed, and the sixth insulating layer can be retained.
  • this embodiment is not limited to this.
  • the circuit structure layer is prepared and formed in the non-light-transmitting area.
  • the light-transmitting area may only include: the substrate, and the first to sixth insulating layers sequentially provided on the substrate.
  • the first to fourth insulating layers and the sixth insulating layer may be made of any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).
  • the combination can be single layer, multi-layer or composite layer.
  • the fifth insulating layer and the seventh insulating layer may be made of organic insulating materials, such as resin materials.
  • the first conductive layer to the fourth conductive layer may be made of metal materials, such as any one or more of aluminum (Al), molybdenum (Mo) and titanium (Ti), or alloy materials of the above metals, such as aluminum neodymium. Alloy (AlNd) or molybdenum-niobium alloy (MoNb) can be a single-layer structure or a multi-layer composite structure. However, this embodiment is not limited to this.
  • a glue dispensing machine is used to add binding material (such as solder paste) into the first opening K1 to the sixth opening K6, and the connection between the light-emitting element and the substrate is completed through a die bonding process.
  • binding material such as solder paste
  • the first electrode of the first light-emitting element is bonded to the anode pad through the binding material in the second opening K2
  • the second electrode of the first light-emitting element is bonded to the cathode pad through the bonding material in the first opening K1. Definite connection.
  • the binding connection of the second light-emitting element and the third light-emitting element can be realized.
  • the light-transmitting area may include: a substrate, and first to sixth insulating layers and a covering layer sequentially disposed on the substrate.
  • the structure of the transparent display panel and its preparation process in this exemplary embodiment are only an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the data lines DL1 to DL2 and the initial signal line INIT may both be covered by the first power supply line VDD, or may both be covered by the second power supply line VSS.
  • the first power line VDD may be located on the third conductive layer.
  • the first power line VDD can cover three data lines
  • the second power line VDD can cover the initial signal line.
  • the first power line VDD can cover the initial signal line
  • the second power line VSS can cover the three data lines.
  • the preparation process of this exemplary embodiment can be realized by using existing mature preparation equipment, and the improvement to the existing process is small. It can be well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, has high production efficiency and high production efficiency. Low cost and high yield.
  • the plurality of first signal lines included in the group of first signal lines 11 in the repeating unit may include: a first power connection line 601, a second power connection line 602, a light emitting control line EML(n), a A scan line SL1(n) and a second scan line SL2(n).
  • the light emission control line EML(n), the first scan line SL1(n) and the second scan line SL2(n) may be electrically connected to the pixel circuits of three sub-pixels in the pixel unit of the same row.
  • the plurality of third signal lines included in the group of second signal lines 12 may include: data lines DL1 to DL3 and the initial signal line INIT; the plurality of fourth signal lines included in the group of second signal lines may include: first power lines VDD and the second power line VSS.
  • the front projection of the first power line VDD on the substrate can cover the front projection of the data lines DL1 and DL2 on the substrate, and the front projection of the second power line VSS on the substrate can cover the data line DL3 and the initial signal line INIT on the substrate. Orthographic projection.
  • the line width of the data line may be determined according to the data load and the metal line process manufacturing capability, and the line widths of the first power line VDD and the second power line VSS may be determined by the voltage drop and the metal line process manufacturing capability.
  • the sizes (ie, line widths) of the data lines DL1 to DL3 and the initial signal line INIT along the first direction X may be substantially the same.
  • the size of the first power line VDD along the first direction X may be greater than twice the size of the data line DL1 along the first direction X, and the size of the second power line VSS along the first direction Twice the size of It is approximately equal to the sum of the dimensions of the two data lines DL1 along the first direction X and the spacing between the two adjacent data lines DL1 along the first direction X.
  • the spacing between adjacent data lines located on the third conductive layer or between the data lines and adjacent initial signal lines may be approximately 3 microns, and the first power line VDD and the second power line VDD located on the fourth conductive layer
  • the spacing between power lines VSS can be approximately 5 microns.
  • a plurality of first signal lines are aggregated and designed, a plurality of third signal lines and a fourth signal line are aggregated and designed, the first power line and the second power line are arranged to extend along the second direction Y, and the first power line
  • the second power line, the data line and the initial signal line extending along the second direction Y can adopt a superimposed design, which can maximize the area of the light-transmitting area of the smallest unit surrounded by the non-light-transmitting area, thereby reducing diffraction and improving transparency.
  • the display quality of the display panel can be adopted.
  • FIG. 7 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 7 is formed by the four repeating units shown in Figure 8 arranged in a 2 ⁇ 2 array.
  • the repeating unit 10 is generally quadrangular, for example, may be rectangular.
  • the light-transmitting sub-areas of four repeating units 10 arranged in a 2 ⁇ 2 array can be connected to form a light-transmitting area A2.
  • the light-transmitting area A2 may be surrounded by the non-light-transmitting area A1.
  • the non-light-transmitting area A1 of the repeating unit 10 may include: one pixel unit P and a set of first wiring lines 11 and a set of second wiring lines 12 electrically connected to the pixel unit P.
  • the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 of the pixel unit P may be sequentially arranged along the second direction Y.
  • a group of first traces 11 may include a plurality of first signal lines 111 extending along the first direction X.
  • the plurality of first signal lines 111 may include: first scanning lines, second scanning lines, light emission control lines, first power supply connection lines and second power supply connection lines electrically connected to the pixel unit P.
  • the group of second traces 12 may include a plurality of third signal lines 121 and a plurality of fourth signal lines 122 extending along the second direction Y.
  • the plurality of fourth signal lines 122 and the plurality of third signal lines 121 may be located on different film layers.
  • the plurality of third signal lines 121 may include at least three data lines electrically connected to the pixel unit P.
  • the plurality of fourth signal lines 122 may include first power lines and second power lines.
  • the fourth signal line 122 that overlaps the pixel unit P in the orthographic projection of the substrate may be a second power line, and the other fourth signal line 122 may be a first power line.
  • the initial signal line may extend along the second direction Y, such as belonging to the third signal line; or the initial signal line may extend along the first direction X, such as belonging to the first signal line.
  • this embodiment is not limited to this.
  • the first power line may be electrically connected to the first power connection line
  • the second power line may be electrically connected to the second power connection line, thereby realizing a mesh transmission route of the first voltage signal and the second voltage signal.
  • the orthographic projection of a fourth signal line 122 located on the fourth conductive layer on the substrate may cover multiple lines located on the third conductive layer.
  • Orthographic projection of the third signal line 121 (for example, three or four) on the substrate.
  • the front projection of the other fourth signal line 122 located on the fourth conductive layer on the substrate may not overlap with the front projection of the third signal line 121 on the substrate.
  • the plurality of third signal lines 121 may be electrically connected to the plurality of pixel circuits of the pixel unit P through connection electrodes.
  • the transparent display panel provided in this example has an aggregated design of multiple first signal lines, an aggregated design of multiple third signal lines and fourth signal lines, and a fourth signal line and multiple third signal lines adopt a superimposed design, which can The area of the smallest unit of light-transmitting area surrounded by the non-light-transmitting area is maximized, thereby reducing diffraction and improving the display quality of the transparent display panel.
  • the rest of the structure of the transparent display panel of this embodiment reference can be made to the description of the previous embodiment, so the details will not be described again.
  • FIG. 9 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 9 is formed by the four repeating units shown in Figure 10 arranged in a 2 ⁇ 2 array.
  • the repeating units 10 are generally quadrangular, for example, may be rectangular.
  • the light-transmitting sub-areas of four repeating units 10 arranged in a 2 ⁇ 2 array can be connected to form a light-transmitting area A2.
  • the light-transmitting area A2 may be surrounded by the non-light-transmitting area A1.
  • the non-light-transmitting area A1 of the repeating unit 10 may include: one pixel unit P and a set of first wiring lines 11 and a set of second wiring lines 12 electrically connected to the pixel unit P.
  • the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 of the pixel unit P may be sequentially arranged along the first direction X.
  • the group of first traces 11 may include: a plurality of first signal lines 111 and a plurality of second signal lines 112 extending along the first direction X.
  • the plurality of first signal lines 111 may be arranged sequentially along the second direction Y and have the same layer structure, such as being located on the first conductive layer.
  • the plurality of first signal lines 111 may include: a first scan line, a second scan line, a light emission control line and an initial signal line that are electrically connected to the pixel unit P.
  • the plurality of second signal lines 112 may have the same layer structure, such as being located on the fourth conductive layer.
  • the plurality of second signal lines 112 may include: first power lines and second power lines.
  • the second signal line 112 that overlaps the pixel unit P in the orthographic projection of the substrate may be a second power line
  • the other second signal line 112 may be a first power line
  • the set of second traces 12 may include: a plurality of third signal lines 121 extending along the second direction Y.
  • the plurality of third signal lines 121 may be arranged sequentially along the first direction X and have the same layer structure, such as being located on the third conductive layer.
  • the plurality of third signal lines may further include: a first power connection line and a second power connection line.
  • the first power connection line may be electrically connected to the first power line
  • the second power connection line may be electrically connected to the second power connection line.
  • the power lines are electrically connected to realize a mesh transmission route of the first voltage signal and the second voltage signal.
  • the orthographic projection of a second signal line 112 may cover the orthographic projection of multiple first signal lines 111 on the substrate.
  • the orthographic projection of the other second signal line 112 (for example, the first power line) on the substrate may not overlap with the orthographic projection of the first signal line 111 on the substrate.
  • the size (ie, line width) of the at least one second signal line 112 along the second direction Y may be larger than the size of the at least two first signal lines 111 along the second direction Y.
  • this embodiment is not limited to this.
  • the orthographic projections of the two second signal lines on the substrate can both cover the orthographic projections of the plurality of first signal lines on the substrate.
  • the transparent display panel provided in this example has an aggregated design of multiple first signal lines, an aggregated design of multiple third signal lines and fourth signal lines, and at least one second signal line and multiple first signal lines adopt a superimposed design. It is possible to maximize the area of the smallest unit of light-transmitting area surrounded by the non-light-transmitting area, thereby reducing diffraction and improving the display quality of the transparent display panel. Regarding the rest of the structure of the transparent display panel of this embodiment, reference can be made to the description of the previous embodiment, so the details will not be described again.
  • FIG. 11 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 12 is formed by the four repeating units shown in Figure 11 arranged in a 2 ⁇ 2 array.
  • one repeating unit 10 may include: two pixel units P, a set of first wirings 11 and a set of second wirings 12 .
  • the two pixel units P may be arranged sequentially along the first direction X.
  • Each pixel unit P may include: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the second direction Y.
  • a set of first traces 11 may include: a plurality of first signal lines 111 extending along the first direction X (for example, may include: a first scan line, a second scan line, Lighting control line, initial signal line, first power connection line and second power connection line).
  • the plurality of first signal lines 111 may have the same layer structure, such as being located on the first conductive layer.
  • the set of second traces 12 may include: a plurality of third signal lines 121 and a plurality of fourth signal lines 122 extending along the second direction Y.
  • the plurality of third signal lines 121 may be arranged sequentially along the first direction X and have the same layer structure, such as being located on the third conductive layer.
  • the plurality of third signal lines 121 may include: a plurality of data lines electrically connected to the two pixel units P.
  • the plurality of fourth signal lines 122 may be located on the fourth conductive layer, and may include, for example, first power lines and second power lines.
  • the orthographic projection of the second power line on the substrate may overlap with the orthographic projection of one of the pixel units on the substrate.
  • the orthographic projection of a fourth signal line 122 (eg, a first power line) on the substrate may cover multiple third signal lines (eg, with the pixel unit on the left P electrically connected multiple data lines) on the front projection of the substrate, another fourth signal line 122 (for example, a second power line) on the front projection of the substrate can cover a plurality of third signal lines (for example, with the right side
  • the pixel unit P is electrically connected to a plurality of data lines) in the orthographic projection of the substrate.
  • this embodiment is not limited to this.
  • the front projection of one fourth signal line on the substrate may cover the front projection of multiple data lines electrically connected to the two pixel units on the substrate, and the other fourth signal line is on the front projection of the substrate.
  • the projection may not overlap with the orthographic projection of the data lines on the substrate.
  • a pixel unit P that is far away from a group of second traces 12 may be connected to the group of second traces 12 through a connection line (not shown) extending along the first direction X.
  • the second wiring (for example, including: data line) 12 is electrically connected.
  • multiple data lines that are electrically connected to two adjacent pixel units in the same row are aggregated and designed, and the first and second power lines that are electrically connected to two adjacent pixel units in the same row are aggregated and designed, and Providing at least one fourth signal line and multiple third signal lines in a superimposed design can maximize the area of the smallest unit of light-transmitting area surrounded by the non-light-transmitting area, thereby reducing diffraction and improving the display quality of the transparent display panel.
  • FIG. 13 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 14 is formed by the four repeating units shown in Figure 13 arranged in a 2 ⁇ 2 array.
  • one repeating unit 10 may include: two pixel units P, a set of first wirings 11 and a set of second wirings 12 .
  • the two pixel units P may be arranged sequentially along the second direction Y.
  • Each pixel unit P may include: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the first direction X.
  • a set of first traces 11 may include: a plurality of first signal lines 111 extending along the first direction X (for example, may include: a first scan line, a second scan line, light emission control line and initial signal line) and a plurality of second signal lines 112 (for example, including a first power supply line and a second power supply line).
  • the second signal line 112 that overlaps with the orthographic projection of one pixel unit P in the repeating unit 10 may be a second power line, and the other second signal line 112 may be a first power line.
  • the first power line and the second power line may have the same layer structure, for example, they may be located on the fourth conductive layer.
  • Another pixel unit P in the repeating unit 10 can be connected to a plurality of first signal lines 111 (for example, including: a first scan line, a second scan line and a light emitting line) through a plurality of first connection lines 131 extending along the second direction Y. control wires, etc.) electrical connection.
  • the plurality of first signal lines 111 may be in the same layer structure, for example, located on the first conductive layer.
  • the plurality of first connection lines 131 may be in the same layer structure, such as being located on the second conductive layer or the third conductive layer.
  • the front projection of one second signal line 112 (for example, a second power line) on the substrate can cover multiple first signal lines 111 (for example, the first signal line electrically connected to the previous pixel unit P) on the front surface of the substrate.
  • the front projection of another second signal line 112 (for example, the first power line) on the substrate can cover multiple first signal lines 111 (for example, the first signal line electrically connected to the next pixel unit P) on the substrate.
  • the set of second traces 12 may include a plurality of third signal lines 121 , and the plurality of third signal lines 121 may be a plurality of data lines electrically connected to the two pixel units P.
  • this embodiment is not limited to this.
  • the front projection of one of the second signal lines on the substrate can cover the front projection of the plurality of first signal lines electrically connected to the two pixel units on the substrate, and the other second signal line is on the substrate.
  • the orthographic projection may not overlap with the orthographic projection of the first signal line on the substrate.
  • multiple data lines that are electrically connected to two adjacent pixel units in the same column are aggregated and designed, and the first and second power lines that are electrically connected to two adjacent pixel units in the same column are aggregated and designed, and
  • the area of the smallest unit of light-transmitting area surrounded by the non-light-transmitting area can be maximized, thereby reducing diffraction and improving the display quality of the transparent display panel.
  • FIG. 15 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • Figure 15 is formed by the four repeating units shown in Figure 16 arranged in a 2 ⁇ 2 array.
  • one repeating unit 10 may include: three pixel units P, a set of first wirings 11 and a set of second wirings 12 .
  • the three pixel units P may be arranged sequentially along the first direction X.
  • Each pixel unit P may include: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the second direction Y.
  • a set of first traces 11 may include: a plurality of first signal lines 111 extending along the first direction X (for example, may include: a first scan line, a second scan line, Lighting control line, initial signal line, first power connection line and second power connection line).
  • the plurality of first signal lines 111 may have the same layer structure, such as being located on the first conductive layer.
  • the set of second traces 12 may include: a plurality of third signal lines 121 and a plurality of fourth signal lines 122 extending along the second direction Y.
  • the plurality of third signal lines 121 may be arranged sequentially along the first direction X and have the same layer structure, such as being located on the third conductive layer.
  • the plurality of third signal lines 121 may include: a plurality of data lines electrically connected to the three pixel units P.
  • the plurality of fourth signal lines 122 may be located on the fourth conductive layer, and may include, for example, first power lines and second power lines.
  • the orthographic projection of the second power line on the substrate may overlap with the orthographic projection of the middle pixel unit P on the substrate.
  • the first power line may be located on a side of the second power line away from the middle pixel unit P in the first direction X.
  • the orthographic projection of a fourth signal line 122 (eg, a first power line) on the substrate may cover multiple third signal lines (eg, with three pixel units P There may be no need for a plurality of electrically connected data lines) on the front projection of the substrate, another fourth signal line 122 (for example, a second power line) on the front projection of the substrate, and a plurality of third signal lines on the front projection of the substrate. overlap.
  • this embodiment is not limited to this.
  • the orthographic projections of the two fourth signal lines on the substrate and the orthographic projections of the plurality of third signal lines on the substrate may both overlap.
  • a pixel unit P that is far away from a group of second traces 12 may be connected to the group of second traces 12 through a connection line (not shown) extending along the first direction X.
  • the second wiring (for example, including: data line) 12 is electrically connected.
  • the orthographic projection of one of the fourth signal lines 122 on the substrate and the orthographic projection of the shift scanning circuit 15 on the substrate may overlap.
  • the shift scanning circuit 15 may be configured to provide a first scanning signal, a second scanning signal or a light emission control signal to the pixel circuit.
  • the orthographic projection of a fourth signal line 122 (eg, a second power line) of a repeating unit on the substrate may overlap with the orthographic projection of the shift scanning circuit that provides the first scanning signal on the substrate, and another
  • the front projection of a fourth signal line 122 (eg, the second power line) of the repeating unit on the substrate may overlap with the front projection of the shift scanning circuit that provides the light emission control signal on the substrate.
  • the second power supply line that overlaps with the shift scanning circuit that provides the first scanning signal and the second power supply line that overlaps with the shift scanning circuit that provides the light emission control signal may be adjacent.
  • this embodiment is not limited to this.
  • the two second power lines may not be adjacent.
  • the shift scanning circuits respectively used to provide the first scanning signal and the light emission control signal may overlap with the orthographic projection of the same second power line on the substrate.
  • a shift scanning circuit may include a plurality of cascaded shift register units, and each shift register unit may provide a first scanning signal, a second scanning signal or a light emission control signal to a row of pixel units.
  • the extending direction of the fourth signal line that overlaps with the orthographic projection of a shift scanning circuit may be consistent with the cascading direction of multiple shift register units in the shift scanning circuit.
  • an area of a fourth signal line eg, a second power line
  • the orthographic projection of a fourth signal line on the substrate may cover the orthographic projection of at least one shift scanning circuit on the substrate.
  • a shift scan circuit may overlap with orthogonal projections of the fourth signal lines on the substrate.
  • the orthographic projection of a fourth signal line on the substrate may overlap with the orthographic projection of at least one shift register unit of the shift scanning circuit on the substrate.
  • a plurality of fourth signal lines that overlap with the orthographic projection of the same shift scanning circuit on the substrate may be adjacent.
  • this embodiment is not limited to this.
  • the transparent display panel may include two shift scanning circuits, one of which may be used to provide the first scanning signal and the second scanning signal, and the other of which may be used to provide the lighting control signal.
  • the two shift scanning circuits may overlap with orthographic projections of different fourth signal lines on the substrate.
  • a shift scan circuit overlaps with the orthographic projection of a fourth signal line on the substrate.
  • the two fourth signal lines can be as far away from each other as possible to reduce the possibility of interference between signals.
  • one of the fourth signal lines may be adjacent to the left frame of the transparent display panel, and the other fourth signal line may be adjacent to the right frame.
  • multiple data lines that are electrically connected to three adjacent pixel units in the same row are aggregated and designed, and the first and second power lines that are electrically connected to three adjacent pixel units in the same row are aggregated and designed.
  • Providing at least one fourth signal line and multiple third signal lines in a superimposed design can maximize the area of the smallest unit of light-transmitting area surrounded by the non-light-transmitting area, thereby reducing diffraction and improving the display quality of the transparent display panel.
  • the shift scanning circuit in a non-light-transmitting area and overlaying it with the fourth signal line, a narrow frame or even frameless design can be achieved.
  • FIG. 17 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • one repeating unit 10 may include: a non-light-transmitting area A1 and five light-transmitting sub-areas (for example, the first light-transmitting sub-area A21 to the fifth light-transmitting sub-area A25 ).
  • a non-light-transmitting area A1 is spaced between adjacent light-transmitting sub-regions.
  • repeating unit 10 can be generally octagonal in shape.
  • the non-light-transmitting area A1 of the repeating unit 10 may include: two pixel units P, a set of first wirings 11 and a set of second wirings 12 .
  • the two pixel units P may be arranged along the first direction X and may be dislocated in the first direction X.
  • One pixel unit P may include: a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3 sequentially arranged along the second direction Y.
  • a set of first wiring lines 11 may include: a plurality of first signal lines 111 (for example, may include: a first scanning line, a second scanning line, a light emitting control line, an initial signal line that are electrically connected to the two pixel units P , the first power connection cable and the second power connection cable).
  • the plurality of first signal lines 111 may have the same layer structure, such as being located on the first conductive layer.
  • the plurality of first signal lines 111 may be in a zigzag shape in the first direction X.
  • Each first signal line 111 may be composed of a first line segment extending along the first direction Connections are formed.
  • Each group of second traces 12 may include: a plurality of third signal lines 121 and a plurality of fourth signal lines 122 extending along the second direction Y.
  • the plurality of third signal lines 121 may be arranged sequentially along the first direction X and have the same layer structure, such as being located on the third conductive layer.
  • the plurality of third signal lines 121 of each group of second wiring lines 12 may include: a plurality of data lines electrically connected to one pixel unit P.
  • the plurality of fourth signal lines 122 of each group of second traces 12 may be located on the fourth conductive layer, and may include, for example, first power lines and second power lines.
  • the orthographic projection of the second power line on the substrate may overlap with the orthographic projection of one pixel unit P on the substrate.
  • the first power line may be located on a side of the second power line away from the pixel unit P in the first direction X.
  • the front projection of one of the fourth signal lines 122 (for example, the first power line) of each group of second traces 12 on the substrate can cover multiple third signal lines. (for example, a plurality of data lines electrically connected to one pixel unit P) on the front projection of the substrate, another fourth signal line 122 (for example, a second power line) on the front projection of the substrate and a plurality of third signal lines
  • the front projection of the fourth signal line 122 (for example, the second power line) on the substrate may not overlap with the front projection of the second line segments of the plurality of first signal lines 111 on the substrate. There is overlap.
  • this embodiment is not limited to this.
  • the orthographic projection of each fourth signal line on the substrate and the orthographic projection of the plurality of third signal lines on the substrate may overlap.
  • two adjacent pixel units in the same row are arranged in a staggered manner, and multiple data lines, first power lines, and second power lines that are electrically connected to the pixel units in the same column are aggregated and designed, and at least one fourth power line is arranged.
  • the signal line and multiple third signal lines adopt a superimposed design, which can maximize the area of the light-transmitting area of the smallest unit surrounded by the non-light-transmitting area, thereby reducing diffraction and improving the display quality of the transparent display panel.
  • FIG. 19 is another partial schematic diagram of a transparent display panel according to at least one embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a repeating unit of a transparent display panel according to at least one embodiment of the present disclosure.
  • the non-light-transmitting area of the repeating unit 10 may include: two pixel units P, two sets of first wirings 11 and one set of second wirings 12 .
  • the two pixel units P may be arranged along the second direction Y and may be dislocated in the second direction Y.
  • Each pixel unit P may include: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the first direction X.
  • Each group of first wiring lines 11 may include: a plurality of first signal lines 111 extending along the first direction and an initial signal line) and a plurality of second signal lines 112 (for example, including a first power line and a second power line).
  • the orthographic projection of one of the second signal lines 112 (for example, the second power line) of each group of first traces 11 on the substrate may overlap with the orthographic projection of the plurality of first signal lines 111 on the substrate.
  • the orthographic projection of the two signal lines 112 (for example, the first power line) on the substrate may not overlap with the orthographic projection of the first signal line 111 on the substrate.
  • the set of second traces 12 may include a plurality of third signal lines 121 , and the plurality of third signal lines 121 may be a plurality of data lines electrically connected to the two pixel units P.
  • the plurality of third signal lines 121 may be in a zigzag shape in the second direction Y.
  • each third signal line 121 may be formed by sequentially connecting a third line segment extending along the first direction X and a fourth line segment extending along the second direction Y.
  • two adjacent pixel units in the same column are dislocated, and the first scanning line, the second scanning line, the light-emitting control line, the first power line, and the second power line of the pixel unit in the same row are aggregated and designed.
  • the at least one second signal line and multiple first signal lines to adopt a superimposed design, which can maximize the area of the light-transmitting area of the smallest unit surrounded by the non-light-transmitting area, thereby reducing diffraction and improving the display of the transparent display panel quality.
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • this embodiment provides a display device 91 including a transparent display panel 910 .
  • the transparent display panel 910 may be a Micro-LED display panel or a Mini-LED display panel.
  • the display device 91 can be any product or component with a transparent display function, such as car window glass, shopping mall cabinets, augmented reality (AR, Augmented Reality) equipment, virtual reality (VR, Virtual Reality) equipment, etc. However, this embodiment is not limited to this.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种透明显示面板(910)，包括：衬底(100)、以及在衬底(100)上阵列排布的多个重复单元(10)。重复单元(10)的非透光区(A1)包括：至少一个像素单元(P)以及与像素单元(P)电连接的沿第一方向(X)延伸的N组第一走线(11)和沿第二方向(Y)延伸的M组第二走线(12)。一组第一走线(11)包括：多条第一信号线(111)和至少一条第二信号线(112)，至少一条第二信号线(112)在衬底(100)的正投影覆盖至少两条第一信号线(111)在衬底(100)的正投影；或者，一组第二走线(12)包括：多条第三信号线(121)和至少一条第四信号线(122)，至少一条第四信号线(122)在衬底(100)的正投影覆盖至少两条第三信号线(121)在衬底(100)的正投影。

Description

透明显示面板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种透明显示面板及显示装置。
背景技术
透明显示技术不仅可以呈现显示屏中的图像，而且可以呈现显示屏后方的实物，具有广阔的应用前景。透明显示技术已被广泛应用于展示橱窗、透明电视、车载、虚拟显示(VR，Virtual Reality)、增强现实(AR，Augmented Reality)等领域。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种透明显示面板及显示装置。
一方面，本公开实施例提供一种透明显示面板，包括：衬底以及在衬底上阵列排布的多个重复单元。所述重复单元包括：非透光区和多个透光子区，相邻透光子区之间由非透光区间隔。所述非透光区包括：至少一个像素单元以及与所述像素单元电连接的沿第一方向延伸的N组第一走线和沿第二方向延伸的M组第二走线。所述第一方向与所述第二方向交叉，N和M均为正整数，且N和M不同时大于1。其中，至少一组第一走线包括：多条第一信号线和至少一条第二信号线，所述至少一条第二信号线在所述衬底的正投影覆盖至少两条第一信号线在所述衬底的正投影；或者，至少一组第二走线包括：多条第三信号线和至少一条第四信号线，所述至少一条第四信号线在所述衬底的正投影覆盖至少两条第三信号线在所述衬底的正投影。
在一些示例性实施方式中，所述至少一条第二信号线沿所述第二方向的尺寸大于所述至少两条第一信号线沿所述第二方向的尺寸。
在一些示例性实施方式中，所述至少一条第二信号线位于所述至少两条 第一信号线远离所述衬底的一侧。
在一些示例性实施方式中，所述至少一条第四信号线沿所述第一方向的尺寸大于所述至少两条第三信号线沿所述第一方向的尺寸。
在一些示例性实施方式中，所述至少一条第四信号线位于所述至少两条第三信号线远离所述衬底的一侧。
在一些示例性实施方式中，所述至少一条第二信号线或所述至少一条第四信号线为电源线。
在一些示例性实施方式中，N和M均为1。
在一些示例性实施方式中，一组第一走线包括多条第一信号线，一组第二走线包括多条第三信号线和至少一条第四信号线。所述至少一条第四信号线包括：第一电源线和第二电源线；所述第一电源线和第二电源线中的至少之一在所述衬底的正投影覆盖所述多条第三信号线在所述衬底的正投影。
在一些示例性实施方式中，一组第一走线的多条第一信号线包括：扫描线、发光控制线、第一电源连接线、第二电源连接线；所述第一电源连接线与所述第一电源线电连接，所述第二电源连接线与所述第二电源线电连接。
在一些示例性实施方式中，透明显示面板还包括：移位扫描电路；所述至少一条第四信号线在所述衬底的正投影与所述移位扫描电路存在交叠。
在一些示例性实施方式中，所述重复单元的非透光区包括：三个沿所述第一方向依次排布的像素单元，该组第二走线与第二个像素单元相邻。
在一些示例性实施方式中，一组第一走线包括：多条第一信号线和至少一条第二信号线，一组第二走线包括多条第三信号线。所述至少一条第二信号线包括：第一电源线和第二电源线；所述第一电源线和第二电源线中的至少之一在所述衬底的正投影覆盖至少两条第一信号线在所述衬底的正投影。
在一些示例性实施方式中，所述多条第一信号线包括：与所述至少一个像素单元电连接的至少一条扫描线和至少一条发光控制线。
在一些示例性实施方式中，所述多条第三信号线至少包括：所述至少一个像素单元电连接的多条数据线。
在一些示例性实施方式中，所述第二电源线在所述衬底的正投影与所述 至少一个像素单元在所述衬底的正投影存在交叠，所述第一电源线位于所述第二电源线远离所述像素单元的一侧。
在一些示例性实施方式中，所述至少一个像素单元包括：出射不同颜色的多个子像素，每个子像素包括发光元件和与发光元件电连接的像素电路，所述发光元件的第一电极通过阳极焊盘与所述像素电路电连接，所述发光元件的第二电极与阴极焊盘电连接，所述阴极焊盘与所述第二电源线为一体结构。
在一些示例性实施方式中，所述第一电源线提供的第一电压信号大于第二电源线提供的第二电压信号。
在一些示例性实施方式中，所述重复单元为四边形。
在一些示例性实施方式中，所述非透光区包括：两个像素单元、一组第一走线和两组第二走线，所述两个像素单元沿所述第一方向排布且存在错位。
在一些示例性实施方式中，一组第一走线包括：多条第一信号线，所述第一信号线包括：依次连接的沿第一方向延伸的第一线段和沿第二方向延伸的第二线段；两组第二走线均包括：多条第三走线和至少一条第四走线，至少一条第四走线在衬底的正投影与多条第一信号线的第二线段在衬底的正投影存在交叠。
在一些示例性实施方式中，所述至少一个像素单元包括：出射不同颜色的多个子像素，每个子像素包括发光元件和与发光元件电连接的像素电路，所述子像素的发光元件与所电连接的像素电路在所述衬底的正投影存在交叠。
另一方面，本公开实施例提供一种显示装置，包括如上所述的透明显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例， 目的只是示意说明本公开内容。
图1为本公开至少一实施例的像素电路的等效电路图；
图2为图1所示的像素电路的工作时序图；
图3为本公开至少一实施例的透明显示面板的局部示意图；
图4为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图5本公开至少一实施例的透明显示面板的局部剖面示意图；
图6A为本公开至少一实施例的重复单元的半导体层的示意图；
图6B为本公开至少一实施例的重复单元的第一导电层的示意图；
图6C为本公开至少一实施例的重复单元的第二导电层的示意图；
图6D为本公开至少一实施例的重复单元的第三绝缘层的示意图；
图6E为本公开至少一实施例的重复单元的第三导电层的示意图；
图6F为本公开至少一实施例的重复单元的第五绝缘层的示意图；
图6G为本公开至少一实施例的重复单元的第四导电层的示意图；
图6H为本公开至少一实施例的重复单元的第七绝缘层的示意图；
图7为本公开至少一实施例的透明显示面板的另一局部示意图；
图8为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图9为本公开至少一实施例的透明显示面板的另一局部示意图；
图10本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图11为本公开至少一实施例的透明显示面板的另一局部示意图；
图12为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图13为本公开至少一实施例的透明显示面板的另一局部示意图；
图14为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图15为本公开至少一实施例的透明显示面板的另一局部示意图；
图16为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图17为本公开至少一实施例的透明显示面板的另一局部示意图；
图18为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图19为本公开至少一实施例的透明显示面板的另一局部示意图；
图20为本公开至少一实施例的透明显示面板的一个重复单元的示意图；
图21为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”可以包括两个以及两个以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接； 可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。另外，将晶体管的栅极可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”可以是指数值相差10％以内的 情况。
在本公开中，“厚度”、“高度”，是指膜层远离衬底一侧表面至靠近衬底一侧表面之间的垂直距离。
在一些实现方式中，透明显示面板包括透光区和非透光区。其中，透光区与非透光区可以交替排布，若部分透光区的面积过小且分布具有周期性，基于小孔衍射原理，则会出现衍射现象，透光区尺寸越小，衍射现象越明显。相关技术中，在不变更布线设计的情况下，随着透明显示面板的分辨率(PPI)升高，会使得各个透光区的面积减小，环境光穿过透明显示面板时会发生较强的衍射，从而导致观看透明显示面板的画面时产生明显的重影现象，降低透明显示面板的显示质量。
本实施例提供一种透明显示面板，包括：衬底以及在衬底上阵列排布的多个重复单元。重复单元包括：非透光区和多个透光子区，相邻透光子区之间由非透光区间隔。非透光区包括：至少一个像素单元以及与所述像素单元电连接的沿第一方向延伸的N组第一走线和沿第二方向延伸的M组第二走线。第一方向与第二方向交叉，例如，第一方向可以垂直于第二方向。N和M均为正整数，且N和M不同时大于1。例如，N和M可以均为1；或者，N可以为1，M可以大于1；或者，M可以为1，N可以大于1。
在一些示例中，至少一组第一走线包括：多条第一信号线和至少一条第二信号线。至少一条第二信号线在衬底的正投影覆盖至少两条第一信号线在衬底的正投影。或者，至少一组第二走线包括：多条第三信号线和至少一条第四信号线。至少一条第四信号线在衬底的正投影覆盖至少两条第三信号线在衬底的正投影。在本示例中，每组走线内的多条信号线采用聚合设计。一组第一走线或者一组第二走线中位于不同膜层的信号线之间存在叠合设计。
本公开中，两个结构采用叠合设计是指两者的正投影存在交叠，且其中一个结构的正投影的超过90％的部分可以落入另一个结构的正投影范围内。聚合设计是指多条信号线集中排布，例如集中排布的多条信号线中，相邻的两条信号线之间的间距小于这两条信号线中任意一条信号线的线宽的2倍。采用聚合设计且位于同一膜层的相邻信号线之间的区域可以忽略不计入透光区。例如，位于同一膜层且聚合设计的相邻信号线之间的间距可以约为3微 米至5微米。
在一些示例中，非透光区是指具有显示图像的像素单元或信号走线等，不能透射透明显示面板背面的背景光或背景光透射率较小的区域。透光区是指不具有显示图像的像素单元以及信号走线等，可以透射透明显示面板背面的背景光或背景光透过率较大的区域。本公开的透光区不包括采用聚合设计的相邻信号线之间的区域，例如相邻的两条信号线之间的间距超过这两根线中任意一条线的线宽的至少5倍，则该相邻的两条信号线之间的区域构成透光区。
在本公开中，结构A沿着方向B延伸是指，结构A可以包括主体部分和与主体部分连接的次要部分，主体部分大致呈沿某一个方向延伸的条状，次要部分的形状不限，主体部分至少为结构A的60％的部分；主体部分沿着方向B伸展，且主体部分沿着方向B伸展的尺寸大于沿着其它方向伸展的次要部分的尺寸。以下描述中所说的“结构A沿着方向B延伸”均是指“结构A的主体部分沿着方向B延伸”。
本实施例提供的透明显示面板，利用信号走线的叠合设计，可以实现增大透光区，降低衍射，在确保透明显示面板的透过率的同时提高显示清晰度，从而提高透明显示面板的透过率和显示品质。
在一些示例性实施方式中，一个像素单元可以包括三个子像素。三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以依次沿某一方向间隔设置，或者，可以呈品字型方式设置；一个像素单元包括四个子像素时，四个子像素可以依次沿某一方向间隔设置或以阵列方式设置。然而，本实施例对此并不限定。
在一些示例中，每个子像素可以包括：像素电路以及与像素电路连接的发光元件。子像素的发光元件与所电连接的像素电路在衬底的正投影可以存在交叠。本示例通过将发光元件和像素电路进行叠合设计，可以增加透光区的面积，提高光透过率。
在一些示例中，像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C结构、7T1C结构、5T1C结构、8T1C结构或者8T2C结构等，其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，发光元件可以为发光面积不大于1×10 5um 2的元件，例如，微发光二极管(Micro-LED，Micro Light Emitting Diode)、或迷你二极管(Mini-LED)、或有机发光二极管(OLED，Organic Light Emitting Diode)、或量子点发光二极管(QLED，Quantum dot Light Emitting Diode)。
图1为本公开至少一实施例的像素电路的等效电路图。在一些示例中，如图1所示，本示例的像素电路可以采用7T1C的结构，即第一晶体管T1至第七晶体管T7以及一个存储电容Cst。其中，第一晶体管T1的栅极与第一节点N1电连接，第一极与第二节点N2电连接，第二极与第三节点N3电连接。第一晶体管T1还可以称为驱动晶体管。第二晶体管T2的栅极与第一扫描线SL1电连接，第一极与数据线DL电连接，第二极与第二节点N2电连接。第二晶体管T2还可以称为数据写入晶体管。第三晶体管T3的栅极与第一扫描线SL1电连接，第一极与第一节点N1电连接，第二极与第三节点N3电连接。第三晶体管T3还可以称为阈值补偿晶体管。第四晶体管T4的栅极与发光控制线EML电连接，第一极与第三节点N3电连接，第二极与第四节点N4电连接。第七晶体管T7的栅极与发光控制线EML电连接，第一极与第一电源线VDD电连接，第二极与第二节点N2电连接。第四晶体管T4和第七晶体管T7还可以称为发光控制晶体管。第五晶体管T5的栅极与第二扫描线SL2电连接，第一极与初始信号线INIT电连接，第二极与第一节点N1电连接。第六晶体管T6的栅极与第二扫描线SL2电连接，第一极与初始信号线INIT电连接，第二极与第四节点N4电连接。第五晶体管T5和第六晶体管T6还可以称为复位控制晶体管。存储电容Cst的第一电容极板与第一节点N1电连接，第二电容极板与第一电源线VDD电连接。发光元件LD的第一电极与第四节点N4电连接，第二电极与第二电源线VSS电连接。例如，发光元件LD的第一电极可以为阳极，第二电极可以为阴极。
在本示例中，第一节点N1可以为存储电容Cst、第一晶体管T1、第三晶体管T3和第五晶体管T5的连接点。第二节点N2可以为第一晶体管T1、第二晶体管T2和第七晶体管T7的连接点。第三节点N3可以为第一晶体管T1、第三晶体管T3和第四晶体管T4的连接点。第四节点N4可以为第四晶体管T4、第六晶体管T6和发光元件LD的连接点。
在一些示例中，第一晶体管T1到第七晶体管T7可以全部是P型晶体管，或者全部可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少透明显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7中的部分晶体管可以为N型晶体管(例如第三晶体管T3和第五晶体管T5)，其余晶体管可以为P型晶体管。
在一些示例中，第一电源线VDD可以配置为向像素电路提供恒定的第一电压信号，第二电源线VSS可以配置为向像素电路提供恒定的第二电压信号。其中，第一电压信号可以大于第二电压信号。第一扫描线SL1可以配置为向像素电路提供第一扫描信号S1，第二扫描线SL2可以配置为向像素电路提供第二扫描信号S2。在一些示例中，第n行像素电路电连接的第二扫描线可以与第n-1行像素电路的第一扫描线电连接，以被输入第一扫描信号S1(n-1)，即第二扫描信号S2(n)与第一扫描信号S1(n-1)可以相同，n可以为大于0的整数。如此，可以减少透明显示面板的信号线，实现透明显示面板的窄边框设计。数据线DL可以配置为向像素电路提供数据信号。发光控制线EML可以配置为向像素电路提供发光控制信号EM。初始信号线INIT可以配置为向像素电路提供初始信号。初始信号的大小可以介于第一电压信号和第二电压信号之间，但不限于此。
下面对像素电路的工作过程进行说明。图2为图1所示的像素电路的工作时序图。以图1所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图2所示，在一帧显示时间段，像素电路的工作过程可以包括：第一时间段t1、第二时间段t2和第三时间段t3。
第一时间段t1，第二扫描线SL2提供低电平的第二扫描信号S2，第五晶体管T5和第六晶体管T6导通。第五晶体管T5导通，向第一节点N1提供 初始信号，对第一节点N1进行初始化；第六晶体管T6导通，向第四节点N4提供初始信号，对第四节点N4进行初始化。发光控制线EML提供高电平的发光控制信号EM，第四晶体管T4和第七晶体管T7截止。第一扫描线SL1提供高电平的第一扫描信号S2，第二晶体管T2和第三晶体管T3截止。
第二时间段t2，第一扫描线SL1提供低电平的第一扫描信号S1，第二晶体管T2和第三晶体管T3导通，第一晶体管T1可以通过第三晶体管T3而处于以二极管形式连接的状态。数据线DL提供数据信号，数据信号通过第二晶体管T2、第一晶体管T1和第三晶体管T3传输到第一节点N1。第一晶体管T1处于以二极管形式连接的状态，使得数据信号的电压与第一晶体管T1的阈值电压之间的差被传输到第一节点N1，第一节点N1的电压被存储在存储电容Cst中。
第三时间段t3，第一扫描线SL1提供高电平的第一扫描信号S1，第二扫描线SL2提供高电平的第二扫描信号S2，发光控制线EML提供低电平的发光控制信号EM。第四晶体管T4和第七晶体管T7导通，驱动电流从第一电源线VDD通过第七晶体管T7、第一晶体管T1、第四晶体管T4和发光元件LD流到第二电源线VSS。通过第一节点N1的电压来控制驱动电流，并且数据信号的电压与第一晶体管T1的阈值电压对应的电压，在第四时间段t4可以抵消第一晶体管T1的阈值电压，使得驱动电流与数据信号对应，且与第一晶体管T1的阈值电压偏移无关。本实施例的像素电路可以较好地补偿第一晶体管T1的阈值电压。
下面通过多个示例对本实施例的方案进行举例说明。
图3为本公开至少一实施例的透明显示面板的局部示意图。图4为本公开至少一实施例的透明显示面板的一个重复单元的示意图。图3由图4所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图3和图4所示，透明显示面板可以包括：在衬底上阵列排布的多个重复单元10。例如，重复单元10大致呈四边形，例如为矩形。每个重复单元10可以包括非透光区A1和多个透光子区(例如包括：第一透光子区A21、第二透光子区A22、第三透光子区A23和第四透光子区A24)，相邻透光子区之间可以由非透光区A1间隔。相邻重复单元10的非 透光区A1可以连通；相邻重复单元10的透光子区可以相互连通。例如，以2×2阵列排布的四个重复单元10的透光子区可以相互连通成一个更大的透光区A2。例如，第一行第一列的重复单元的第四透光子区A24、第一行第二列的重复单元的第三透光子区A23、第二行第一列的重复单元的第二透光子区A22和第二行第二列的重复单元的第一透光子区A21可以连通成一个更大的透光区A2。透光区A2的四周可以由非透光区A1围绕。
在一些示例中，一个重复单元中的透光子区的总面积可以大于非透光区的面积。透明显示面板的透光区的总面积在透明显示面板的总面积中的占比可以大于45％，例如，可以约为48.5％、79.3％、82.1％或者85％。然而，本实施例对此并不限定。在一些示例中，可以根据实际应用需求来设置透光区的面积占比。透光区的面积占比越大，透明显示面板的透过率越大，透明显示面板的透明度越高，即透明显示效果越好。
在一些示例中，如图3和图4所示，一个重复单元10的非透光区A1可以包括：一个像素单元P以及与像素单元P电连接的一组第一走线11和一组第二走线12。一组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111。多条第一信号线111可以沿第二方向Y依次排布。多条第一信号线111可以为同层结构。一组第二走线12可以包括：沿第二方向Y延伸的多条第三信号线121和多条第四信号线122。多条第三信号线121可以沿第一方向X依次排布，多条第四信号线122可以沿第一方向X依次排布。多条第三信号线121可以为同层结构，多条第四信号线122可以为同层结构。例如，多条第四信号线122可以位于多条第三信号线121远离衬底的一侧。至少一条第四信号线122在衬底的正投影可以覆盖至少两条第三信号线121在衬底的正投影。例如，一条第四信号线122在衬底的正投影可以覆盖两条第三信号线121在衬底的正投影。在一些示例中，一组第二走线12的多条第四信号线122可以包括：一条第一电源线和一条第二电源线。第二电源线在第一方向X上可以位于第一电源线靠近像素单元P的一侧。换言之，第二电源线可以与像素单元P相邻，第一电源线可以位于第二电源线远离像素单元P的一侧。
在一些示例中，如图3所示，多个重复单元10阵列排布使得相邻重复单 元10的非透光区A1可以连通。沿第一方向X相邻的重复单元10的非透光区A1内的多条第一信号线111可以对应连通，沿第二方向Y相邻的重复单元10的非透光区A1内的多条第三信号线121可以对应连通，多条第四信号线122可以对应连通。在多个重复单元10阵列排布之后，多条第一信号线111可以沿第一方向X传输信号，多条第三信号线121和多条第四信号线122可以沿第二方向Y传输信号。
在一些示例中，如图3和图4所示，重复单元10的非透光区A1内的一个像素单元P可以包括：出射第一颜色光的第一子像素P1、出射第二颜色光的第二子像素P2、以及出射第三颜色光的第三子像素P3。第一子像素P1、第二子像素P2和第三子像素P3可以呈品字型方式设置。例如，第一颜色光可以为红光，第二颜色光可以为蓝光，第三颜色光可以为绿光。然而，本实施例对此并不限定。
在一些示例中，第一子像素P1可以包括：第一像素电路和与第一像素电路电连接的第一发光元件。第二子像素P2可以包括：第二像素电路和与第二像素电路电连接的第二发光元件。第三子像素P3可以包括：第三像素电路和与第三像素电路电连接的第三发光元件。第一发光元件在衬底的正投影与第一像素电路在衬底的正投影存在交叠。第二发光元件在衬底的正投影与第二像素电路在衬底的正投影存在交叠。第三发光元件在衬底的正投影与第三像素电路在衬底的正投影存在交叠。例如，第一像素电路、第二像素电路和第三像素电路可以为如图1所示的7T1C结构，第一发光元件、第二发光元件和第三发光元件可以为发光面积不大于1×10 5um 2的元件，例如可以为Micro-LED。本示例中，像素电路与对应电连接的发光元件采用叠合设计，可以减小非透光区A1的面积，提升像素开口率，从而增加透光区的面积。
在一些示例中，由于出射不同颜色光的发光元件的光电特性存在差异，因此与出射不同颜色光的发光元件电连接的像素电路中，第一晶体管的尺寸可以不同。例如，出射红光的发光元件电连接的像素电路的第一晶体管的沟道宽长比(即沿第一方向的尺寸与沿第二方向的尺寸之比)可以大于出射蓝光或绿光的发光元件电连接的像素电路的第一晶体管的沟道宽长比。
图5本公开至少一实施例的透明显示面板的局部剖面示意图。在一些示 例中，如图5所示，在垂直于透明显示面板的方向上，重复单元的非透光区A1可以包括：衬底100、以及依次设置在衬底100上的电路结构层21、发光结构层22以及覆盖层23。电路结构层21可以至少包括：多个像素电路(例如，第一像素电路、第二像素电路和第三像素电路)。图5中的电路结构层21仅以一个像素电路的一个晶体管和一个存储电容的部分结构为例进行示意图。电路结构层21可以包括：依次设置在衬底100上的半导体层210、第一导电层211、第二导电层212、第三导电层213和第四导电层214。在一些示例中，半导体层210可以包括：多个像素电路的晶体管的有源层。第一导电层211可以至少包括：多个像素电路的晶体管的栅极以及存储电容的一个电容极板。第二导电层212可以至少包括：多个像素电路的存储电容的另一个电容极板。第三导电层213可以至少包括：多个连接电极。第四导电层214可以至少包括：第一导电部、第二导电部以及第二电源线VSS。
在一些示例中，如图5所示，半导体层210和第一导电层211之间可以设置有第一绝缘层101，第一导电层211和第二导电层212之间可以设置有第二绝缘层102，第二导电层212和第三导电层213之间可以设置有第三绝缘层103，第三导电层213和第四导电层214之间可以设置有第四绝缘层104和第五绝缘层105。第四导电层214远离衬底100一侧可以设置有第六绝缘层106和第七绝缘层107。例如，第一绝缘层101至第四绝缘层104、以及第六绝缘层106可以为无机绝缘层，第五绝缘层105和第七绝缘层107可以为有机绝缘层。然而，本实施例对此并不限定。
在一些示例中，发光结构层22可以包括：多个发光元件(例如，第一发光元件、第二发光元件和第三发光元件)。以一个发光元件为例，如图5所示，发光元件可以包括：发光部220、与发光部220连接的第一电极221和第二电极222。第一电极221与发光部220的第一端连接，第二电极222与发光部220的第二端连接。例如，发光元件的第一电极221可以为阳极，第二电极222可以为阴极。第一电极221可以通过第一导电部与像素电路电连接，第二电极222可以通过第二导电部与第二电源线VSS电连接。然而，本实施例对此并不限定。发光元件远离衬底100的一侧还可以设置有保护层23，防止发光元件在后续制程或者运输过程中受到外力(例如剐蹭)而脱落。保 护层23的材料可以为硅胶。
在一些示例中，如图5所示，在垂直于透明显示面板的方向上，透光区A2可以包括：衬底100、依次设置在衬底100上的第一绝缘层101至第六绝缘层106以及覆盖层23。在透光区A2可以对第七绝缘层107进行镂空设计，以提升透光区A2的光透过率。然而，本实施例对此并不限定。在另一些示例中，在透光区A2可以对第五绝缘层和第七绝缘层进行镂空设计，以进一步提升透光区A2的光透过率。
下面通过透明显示面板的制备过程进行示例性说明。本公开所说的“构图工艺”或“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本公开所说的“E和F同层设置”是指，E和F通过同一次图案化工艺同时形成或者E和F靠近衬底一侧的表面与衬底的距离基本相同，或者E和F靠近衬底一侧的表面与同一个膜层直接接触。膜层的“厚度”为膜层在垂直于衬底所在平面上的尺寸。本公开示例性实施例中，“E的正投影包含F的正投影”，是指E的正投影的边界落入F的正投影的边界范围内，或者E的正投影的边界与F的正投影的边界重叠。
在一些示例性实施方式中，透明显示面板的制备过程可以包括如下操作。
(1)、提供衬底。在一些示例中，衬底可以为刚性基底，例如玻璃基底或石英基底，或者，可以为柔性基底，例如有机树脂基底。在一些示例中，衬底可以为玻璃基底。然而，本实施例对此并不限定。
(2)、形成半导体层。在一些示例中，在衬底上沉积半导体薄膜，通过 图案化工艺对半导体薄膜进行图案化，在非透光区形成半导体层。
图6A为本公开至少一实施例的重复单元的半导体层的示意图。在一些示例中，如图6A所示，重复单元的非透光区的半导体层可以至少包括：多个像素电路的多个晶体管的有源层(例如包括：第一像素电路的第一晶体管的第一有源层310至第七晶体管的第七有源层370、第二像素电路的第一晶体管的第一有源层410至第七晶体管的第七有源层470、以及第三像素电路的第一晶体管的第一有源层510至第七晶体管的第七有源层570)。例如，第一像素电路的第三有源层330和第五有源层350可以为一体结构，第二像素电路的第三有源层430和第五有源层450可以为一体结构，第三像素电路的第三有源层530和第五有源层550可以为一体结构。
在一些示例中，半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。例如，半导体层的材料可以为多晶硅(p-Si)。然而，本实施例对此并不限定。
(3)、形成第一导电层。在一些示例中，在形成前述结构的衬底上沉积第一绝缘薄膜，通过图案化工艺对第一绝缘薄膜进行图案化，形成覆盖半导体层的第一绝缘层。随后，沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，在非透光区形成第一导电层。
图6B为本公开至少一实施例的重复单元的第一导电层的示意图。在一些示例中，如图6B所示，重复单元的非透光区的第一导电层可以至少包括：多个像素电路的多个晶体管的栅极和存储电容的一个电容极板(例如包括：第一像素电路的第一晶体管的栅极311、第二晶体管的栅极321、第三晶体管的栅极331、第四晶体管的栅极341、第五晶体管的栅极351、第六晶体管的栅极361、第七晶体管的栅极371以及存储电容的第二电容极板382；第二像素电路的第一晶体管的栅极411、第二晶体管的栅极421、第三晶体管的栅极431、第四晶体管的栅极441、第五晶体管的栅极451、第六晶体管的栅极461、第七晶体管的栅极471以及存储电容的第二电容极板482；第三像素电路的第一晶体管的栅极511、第二晶体管的栅极521、第三晶体管的栅极531、第 四晶体管的栅极541、第五晶体管的栅极551、第六晶体管的栅极561、第七晶体管的栅极571以及存储电容的第二电容极板582)、多个连接电极(例如，第一连接电极401至第八连接电极408)、发光控制线EML(n)、第一扫描线SL1(n)、第二扫描线SL2(n)、第一电源连接线601以及第二电源连接线602。
在一些示例中，如图6B所示，第一像素电路的第四晶体管的栅极341与第七晶体管的栅极371可以为一体结构，第二晶体管的栅极321和第三晶体管的栅极331可以为一体结构，第五晶体管的栅极351和第六晶体管的栅极361可以为一体结构。第一像素电路的第一晶体管至第七晶体管可以均为双栅晶体管。第二像素电路的第四晶体管的栅极441与第七晶体管的栅极471可以为一体结构，第二晶体管的栅极421和第三晶体管的栅极431可以为一体结构，第五晶体管的栅极451和第六晶体管的栅极461可以为一体结构。第二像素电路的第一晶体管至第七晶体管可以均为双栅晶体管。第三像素电路的第四晶体管的栅极541与第七晶体管的栅极571可以为一体结构，第二晶体管的栅极521和第三晶体管的栅极531可以为一体结构，第五晶体管的栅极551和第六晶体管的栅极561可以为一体结构。第三像素电路的第一晶体管至第七晶体管可以均为双栅晶体管。本示例通过采用双栅晶体管可以增强驱动能力，提高发光元件的电流饱和度，防止和减少漏电流的发生。
在一些示例中，如图6B所示，第二电源连接线602、发光控制线EML(n)、第一扫描线SL1(n)、第二扫描线SL2(n)以及第一电源连接线601可以沿第二方向Y依次排布，并沿第一方向X延伸。第二电源连接线602、发光控制线EML(n)、第一扫描线SL1(n)、第二扫描线SL2(n)以及第一电源连接线601在第二方向Y上可以位于第一像素电路和第二像素电路之间。
在一些示例中，如图6B所示，第一电源连接线601与第三像素电路的存储电容的第二电容极板582可以为一体结构。发光控制线EML(n)与第三像素电路的第七晶体管的栅极571和第四晶体管的栅极541可以为一体结构。第一扫描线SL1(n)与第三像素电路的第二晶体管的栅极521和第三晶体管的栅极531可以为一体结构。第二扫描线SL2(n)与第三像素电路的第五晶体管的栅极551和第六晶体管的栅极561可以为一体结构。然而，本实施例对此 并不限定。
(4)、形成第二导电层。在一些示例中，在形成前述结构的衬底上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化，形成覆盖第一导电层的第二绝缘层；随后，沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，在非透光区形成第二导电层。
图6C为本公开至少一实施例的重复单元的第二导电层的示意图。在一些示例中，如图6C所示，重复单元的非透光区的第二导电层可以至少包括：多个像素电路的存储电容的另一个电容极板(例如包括：第一像素电路的存储电容的第一电容极板381、第二像素电路的存储电容的第一电容极板481、第三像素电路的第一电容极板581)。
(5)、形成第三绝缘层。在一些示例中，在形成前述结构的衬底上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层。
图6D为本公开至少一实施例的重复单元的第三绝缘层的示意图。在一些示例中，如图6D所示，重复单元的非透光区的第三绝缘层开设有多个过孔，例如可以包括：暴露出半导体层表面的第一过孔V1至第四十六过孔V46、暴露出第一导电层表面的第五十一过孔V51至第八十二过孔V82、暴露出第二导电层表面的第九十一过孔V91至第九十三过孔V93。
(6)、形成第三导电层。在一些示例中，在形成前述结构的衬底上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在非透光区形成第三导电层。
图6E为本公开至少一实施例的重复单元的第三导电层的示意图。在一些示例中，如图6E所示，重复单元的非透光区的第三导电层可以至少包括：多个连接电极(例如，第十一连接电极701至第三十七连接电极727)、第一像素电路的第三电容极板383、第二像素电路的第三电容极板483、第三像素电路的第三电容极板583、多条数据线(例如，数据线DL1至数据线DL3)、以及初始信号线INIT。
在一些示例中，如图6E所示，数据线DL1至数据线DL3、初始信号线INIT可以相邻，且沿第一方向X依次排布，并均沿第二方向Y延伸。数据 线DL1至数据线DL3、初始信号线INIT在第一方向X上可以位于第一像素电路和第二像素电路远离第三像素电路的一侧。位于第三导电层的数据线DL1至数据线DL3以及初始信号线INIT在衬底的正投影可以与位于第一导电层的发光控制线EML(n)、第一扫描线SL1(n)、第二扫描线SL2(n)、第一电源连接线601和第二电源连接线602在衬底的正投影存在交叠。
在一些示例中，如图6A至图6E所示，第十一连接电极701可以通过并排设置的三个第一过孔V1和并排设置的三个第三过孔V3与第一像素电路的第七晶体管的第七有源层370电连接，还可以通过竖排设置的两个第五十八过孔V58与第二电容极板382电连接。第十一连接电极701与第三电容极板383可以为一体结构。第十二连接电极702可以通过并排设置的六个第六过孔V6和并排设置的六个第八过孔V8与第一像素电路的第一晶体管的第一有源层310电连接，还可以通过并排设置的三个第二过孔V2与第七晶体管的第七有源层370电连接，还可以通过第五过孔V5与第二晶体管的第二有源层320电连接。第十三连接电极703可以通过并排设置的六个第七过孔V7与第一晶体管的第一有源层310电连接，还可以通过并排设置的三个第十过孔V10与第四晶体管的第四有源层340电连接，还可以通过第十二过孔V12与第三晶体管的第三有源层330电连接。第十四连接电极704可以通过并排设置的三个第九过孔V9以及并排设置的三个第十一过孔V11与第四晶体管的第四有源层340电连接，还可以通过第十五过孔V15与第六晶体管的第六有源层360电连接。第十五连接电极705可以通过第四过孔V4与第二晶体管的第二有源层320电连接，还可以通过第五十二过孔V52与第一连接电极401电连接。第一连接电极401可以通过第五十三过孔V53与第一数据线DL1电连接。第十六连接电极706可以通过第五十一过孔V51与第一晶体管的栅极311电连接，还可以通过第十三过孔V13与第五晶体管的第五有源层350电连接，还可以通过第九十一过孔V91与存储电容的第一电容极板381电连接，还可以通过第五十七过孔V57与第二连接电极402电连接。第十七连接电极707可以通过第十四过孔V14与第五晶体管的第五有源层350电连接，还可以通过第十六过孔V16与第六晶体管的第六有源层360电连接，还可以通过第六十过孔V60与第三连接电极403电连接。第三连接电极403可以通过竖排设置的两个第五十九过孔V59与初始信号线INIT电连接，还可以通 过第六十一过孔V61与第三十七连接电极727电连接。
在一些示例中，如图6A至图6E所示，第十八连接电极708可以通过并排设置的三个第十七过孔V17和并排设置的第十九过孔V19与第二像素电路的第七晶体管的第七有源层470电连接，还可以通过并排设置的两个第六十四过孔V64与第二像素电路的存储电容的第二电容极板382电连接，还可以通过并排设置的两个第七十八过孔V78与第一电源连接线601电连接。第十八连接电极708与第二像素电路的第三电容极板483可以为一体结构。第十八连接电极708与第十一连接电极701可以为一体结构。第十九连接电极709可以通过并排设置的三个第十八过孔V18与第七有源层470电连接，还可以通过并排设置的两个第二十过孔V20与第一有源层410电连接，还可以通过第二十三过孔V23与第二有源层420电连接。第二十连接电极710可以通过并排设置的三个第二十四过孔V24和并排设置的三个第二十六过孔V26与第四有源层440电连接，还可以通过第三十过孔V30与第六有源层460电连接。第二十一连接电极711可以通过并排设置的两个第二十一过孔V21与第一有源层410电连接，还可以通过并排设置的三个第二十五过孔V25与第四有源层440电连接，还可以通过第二十七过孔V27与第三有源层430电连接。第二十二连接电极712可以通过第二十二过孔V22与第二有源层420电连接，还可以通过第六十七过孔V67与第四连接电极404电连接。第四连接电极404可以通过第六十六过孔V66与数据线DL2电连接。第二十三连接电极713可以通过第六十一过孔V61与第一晶体管的栅极411电连接，还可以通过第二十八过孔V28与第五晶体管的第五有源层450电连接，还可以通过第六十五过孔V65与第五连接电极405电连接，还可以通过第九十二过孔V92与存储电容的第一电容极板481电连接。第二十四连接电极714可以通过第二十九过孔V29与第五有源层450电连接，还可以通过第三十一过孔V31与第六有源层460电连接，还可以通过并排设置的两个第六十九过孔V69与第六连接电极406电连接。
在一些示例中，如图6A至图6E所示，第二十五连接电极715可以通过并排设置的三个第三十二过孔V32和并排设置的三个第三十四过孔V34与第三像素电路的第七有源层570电连接，还可以通过并排设置的两个第七十二 过孔V72与存储电容的第二电容极板582电连接。第二十五连接电极715与第三电容极板583可以为一体结构。第二十六连接电极716可以通过并排设置的三个第三十三过孔V33与第七有源层570电连接，还可以通过并排设置的两个第三十七过孔V37与第一有源层510电连接，还可以通过第三十六过孔V36与第二有源层520电连接。第二十七连接电极717可以通过并排设置的两个第三十八过孔V38与第一有源层510电连接，还可以通过并排设置的三个第四十过孔V40与第四有源层540电连接，还可以通过第四十二过孔V42与第三有源层530电连接。第二十八连接电极718可以通过并排设置的三个第三十九过孔V39和并排设置的三个第四十一过孔V41与第四有源层540电连接，还可以通过第四十五过孔V45与第六有源层560电连接。第二十九连接电极719可以通过第三十五过孔V35与第二有源层520电连接，还可以通过第七十五过孔V75与第七连接电极407电连接。第七连接电极407可以通过第七十六过孔V76与数据线DL3电连接。第三十连接电极720可以通过第七十四过孔V74与第一晶体管的栅极511电连接，还可以通过第四十三过孔V43与第五有源层550电连接，还可以通过第七十三过孔V73与第八连接电极408电连接，还可以通过第九十三过孔V93与第一电容极板581电连接。第三十一连接电极721可以通过并排设置的两个第七十一过孔V71与第六连接电极406电连接，还可以通过第四十四过孔V44与第五有源层550电连接，还可以通过第四十六过孔V46与第六有源层560电连接。
在一些示例中，如图6A至图6E所示，第三十二连接电极722可以通过并排设置的两个第七十七过孔V77与第一电源连接线601电连接。第三十三连接电极723可以通过并排设置的两个第八十过孔V80与第二电源连接线602电连接。第三十四连接电极724可以通过第五十四过孔V54与第一像素电路的第四晶体管的栅极341电连接，还可以通过第七十九过孔V79与发光控制线EML(n)电连接，还可以通过第六十八过孔V68与第二像素电路的第四晶体管的栅极341电连接。发光控制线EML(n)与第三像素电路的第七晶体管的栅极571和第四晶体管的栅极541可以为一体结构。第三十五连接电极725可以通过第五十五过孔V55与第一像素电路的第三晶体管的栅极331电连接，还可以通过第八十一过孔V81与第一扫描线SL1(n)电连接，还可以通过第六十二过孔V62与第二像素电路的第三晶体管的栅极431电连接。第 一扫描线SL1(n)与第三像素电路的第二晶体管的栅极521和第三晶体管的栅极531可以为一体结构。第三十六连接电极726可以通过第五十六过孔V56与第一像素电路的第六晶体管的栅极361电连接，还可以通过第八十二过孔V82与第二扫描线SL2(n)电连接，还可以通过第六十三过孔V63与第二像素电路的第六晶体管的栅极461电连接。第二扫描线SL2(n)与第三像素电路的第五晶体管的栅极551和第六晶体管的栅极561可以为一体结构。第三十七连接电极727可以通过第七十过孔V70与第六连接电极406电连接。通过初始信号线INIT、第三连接电极403、第三十七连接电极727、第六连接电极406以及第三十一连接电极721可以传输初始信号。
在本公开中，并排设置表示沿第一方向X排布，竖排设置表示沿第二方向Y排布。
(7)、形成第四绝缘层和第五绝缘层。在一些示例中，在形成前述结构的衬底上沉积第四绝缘薄膜，随后，涂覆第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜和第四绝缘薄膜进行图案化，形成第五绝缘层和第四绝缘层。
图6F为本公开至少一实施例的重复单元的第五绝缘层的示意图。在一些示例中，如图6F所示，重复单元的非透光区的第五绝缘层开设有多个过孔，例如可以包括：暴露出第三导电层表面的第九十四过孔V94至第九十八过孔V98。第九十四过孔V94可以暴露出第十四连接电极704的表面。第九十五过孔V95可以暴露出第二十连接电极710的表面。第九十六过孔V96可以暴露出第二十八连接电极718的表面。第九十七过孔V97可以暴露出第三十二连接电极722的表面。第九十八过孔V98可以暴露出第三十三连接电极723的表面。
(8)、形成第四导电层。在一些示例中，在形成前述结构的衬底上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，在非透光区形成第四导电层。
图6G为本公开至少一实施例的重复单元的第四导电层的示意图。在一些示例中，如图6G所示，重复单元的非透光区的第四导电层可以至少包括：第一电源线VDD、第二电源线VSS、第一导电部301、第二导电部302、第三导电部401、第四导电部402、第五导电部501、以及第六导电部502。第 二电源线VSS和第一电源线VDD可以沿第二方向Y延伸。第一电源线VDD在第一方向X上可以位于第二电源线VSS远离第一像素电路和第二像素电路的一侧。第二电源线VSS与第二导电部302、第四导电部402和第六导电部502可以为一体结构。在本示例中，通过设置第二电源线VSS与第二导电部302、第四导电部402和第六导电部502为一体结构，可以减小非透光区的面积，从而增加透光区的面积。
在一些示例中，如图6G和图6E所示，第一电源线VDD在衬底的正投影可以覆盖数据线DL1和DL2在衬底的正投影，第二电源线VSS在衬底的正投影可以覆盖数据线DL3和初始信号线INIT在衬底的正投影。
在一些示例中，如图6E至图6G所示，第一导电部301可以通过第九十四过孔V94与第十四连接电极704电连接，从而实现与第一像素电路电连接。第三导电部401可以通过第九十五过孔V95与第二十连接电极710电连接，从而实现与第二像素电路电连接。第五导电部501可以通过第九十六过孔V96与第二十八连接电极718电连接，从而实现与第三像素电路电连接。第六导电部502可以通过第九十八过孔V98与第三十三连接电极723电连接，从而实现与第二电源连接线602电连接。第二电源线VSS可以通过第六导电部502、第三十三连接电极723实现与第二电源连接线602电连接，从而实现第二电压信号的网状传输路线。第一电源线VDD可以通过第九十七过孔V97与第三十二连接电极722电连接，从而实现与第一电源连接线601电连接。第一电源线VDD可以通过第三十二连接电极722实现与第一电源连接线601电连接，从而实现第一电压信号的网状传输路线。本示例中，通过实现第二电源线的网状连接、第一电源线的网状连接，可以降低第一电源线和第二电源线的电阻。
(9)、形成第六绝缘层和第七绝缘层。在一些示例中，在形成前述结构的衬底上沉积第六绝缘薄膜，随后，涂覆第七绝缘薄膜，通过图案化工艺对第七绝缘薄膜和第六绝缘薄膜进行图案化，形成第七绝缘层和第六绝缘层。
图6H为本公开至少一实施例的重复单元的第七绝缘层的示意图。在一些示例中，如图6H所示，重复单元的非透光区的第七绝缘层107可以开设有多个开口，例如可以包括暴露出第四导电层表面的第一开口K1至第六开 口K6。第一开口K1可以暴露出第二导电部302的表面，第二导电部302被第一开口K1暴露的区域可以作为阴极焊盘，后续与第一发光元件的第二电极绑定连接。第二开口K2可以暴露出第一导电部301的表面，第一导电部301被第二开口K2暴露的区域可以作为阳极焊盘，后续与第一发光元件的第一电极绑定连接。第三开口K3可以暴露出第三导电部401的表面，第三导电部401被第三开口K3暴露的区域可以作为阳极焊盘，后续与第二发光元件的第一电极绑定连接。第四开口K4可以暴露出第四导电部402的表面，第四导电部402被第四开口K4暴露的区域可以作为阴极焊盘，后续与第二发光元件的第二电极绑定连接。第五开口K5可以暴露出第五导电部501的表面，第五导电部501被第五开口K5暴露的区域可以作为阳极焊盘，后续与第三发光元件的第一电极绑定连接。第六开口K6可以暴露出第六导电部502的表面，第六导电部502被第六开口K6暴露的区域可以作为阴极焊盘，后续与第三发光元件的第二电极绑定连接。例如，第一开口K1和第四开口K4在衬底的正投影可以与第二电源线VSS在衬底的正投影存在交叠。非透光区除第一开口K1至第六开口K6以外的区域可以被第七绝缘层和第六绝缘层覆盖。重复单元的非透光区以外的透光子区(例如，第一透光子区A21至第四透光子区A24)内的第七绝缘层可以被去掉，第六绝缘层可以保留。然而，本实施例对此并不限定。
至此，在非透光区制备形成电路结构层。在本次工艺之后，透光区可以仅包括：衬底、以及依次设置在衬底上的第一绝缘层至第六绝缘层。
在一些示例中，第一绝缘层至第四绝缘层以及第六绝缘层可以采用硅氮化物(SiNx)、硅氧化物(SiOx)、氮氧化硅(SiON)中的任意一种或多种的组合，可以是单层、多层或复合层。第五绝缘层和第七绝缘层可以采用有机绝缘材料，例如可以采用树脂材料。第一导电层至第四导电层可以采用金属材料，例如，铝(Al)、钼(Mo)和钛(Ti)中的任意一种或等多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构。然而，本实施例对此并不限定。
(10)、形成发光结构层。在一些示例中，利用点胶机向第一开口K1至第六开口K6内加入绑定材料(例如锡膏)，通过固晶工艺完成发光元件 与衬底实现连接。例如，第一发光元件的第一电极通过第二开口K2的绑定材料与阳极焊盘绑定连接，第一发光元件的第二电极通过第一开口K1内的绑定材料与阴极焊盘绑定连接。同理，可以实现第二发光元件和第三发光元件的绑定连接。
在本次工艺后，透光区的膜层结构没有变化。
(11)、形成覆盖层。在一些示例中，在形成前述结构的衬底上涂覆覆盖薄膜形成覆盖层。覆盖层可以覆盖重复单元。在本次工艺之后，透光区可以包括：衬底、以及依次设置在衬底上的第一绝缘层至第六绝缘层以及覆盖层。通过设置覆盖层可以对发光结构层进行封装保护，而且不会降低出射光线的光透过率。
本示例性实施例的透明显示面板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，数据线DL1至DL2和初始信号线INIT可以均由第一电源线VDD覆盖，或者，可以均由第二电源线VSS覆盖。又如，第一电源线VDD可以位于第三导电层。又如，第一电源线VDD可以覆盖三条数据线，第二电源线VDD可以覆盖初始信号线。又如，第一电源线VDD可以覆盖初始信号线，第二电源线VSS可以覆盖三条数据线。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在本示例中，重复单元内的一组第一信号线11包括的多条第一信号线可以包括：第一电源连接线601、第二电源连接线602、发光控制线EML(n)、第一扫描线SL1(n)和第二扫描线SL2(n)。发光控制线EML(n)、第一扫描线SL1(n)和第二扫描线SL2(n)可以与同一行的像素单元内的三个子像素的像素电路电连接。一组第二信号线12包括的多条第三信号线可以包括：数据线DL1至DL3以及初始信号线INIT，该组第二信号线包括的多条第四信号线可以包括：第一电源线VDD和第二电源线VSS。第一电源线VDD在衬底的正投影可以覆盖数据线DL1和DL2在衬底的正投影，第二电源线VSS在衬底的正投影可以覆盖数据线DL3和初始信号线INIT在衬底的正投影。
在一些示例中，数据线的线宽可以根据数据负载和金属线工艺制备能力确定，第一电源线VDD和第二电源线VSS的线宽可以由压降和金属线工艺制备能力确定。在一些示例中，数据线DL1至DL3以及初始信号线INIT沿第一方向X的尺寸(即线宽)可以大致相同。第一电源线VDD沿第一方向X的尺寸可以大于数据线DL1沿第一方向X的尺寸的两倍，第二电源线VSS沿第一方向X的尺寸可以大于数据线DL1沿第一方向X的尺寸的两倍，例如，两根数据线DL1在衬底上的正投影落入一根第二电源线VSS在衬底上的正投影内，第二电源线VSS沿第一方向X的尺寸大致等于两根数据线DL1沿第一方向X的尺寸与相邻两根数据线DL1沿第一方向X的间距之和。
在一些示例中，位于第三导电层的相邻数据线之间或者数据线与相邻初始信号线之间的间距可以约为3微米，位于第四导电层的第一电源线VDD和第二电源线VSS之间的间距可以约为5微米。
本示例中，多条第一信号线聚合设计，多条第三信号线和第四信号线聚合设计，第一电源线和第二电源线设置为沿第二方向Y延伸，并且第一电源线和第二电源线与沿第二方向Y延伸的数据线和初始信号线可以采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，改善透明显示面板的显示品质。
图7为本公开至少一实施例的透明显示面板的另一局部示意图。图8为本公开至少一实施例的透明显示面板的一个重复单元的示意图。图7由图8所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图7和图8所示，重复单元10大致呈四边形，例如可以为矩形。按照2×2阵列排布的四个重复单元10的透光子区可以连通成一个透光区A2。透光区A2的四周可以由非透光区A1围绕。重复单元10的非透光区A1可以包括：一个像素单元P以及与像素单元P电连接的一组第一走线11和一组第二走线12。像素单元P的第一子像素P1、第二子像素P2和第三子像素P3可以沿第二方向Y依次排布。一组第一走线11可以包括沿第一方向X延伸的多条第一信号线111。多条第一信号线111可以包括：与像素单元P电连接的第一扫描线、第二扫描线、发光控制线、第一电源连接线以及第二电源连接线。一组第二走线12可以包括沿第二方向Y延伸的多 条第三信号线121和多条第四信号线122。多条第四信号线122和多条第三信号线121可以位于不同膜层。多条第三信号线121可以至少包括：与像素单元P电连接的三条数据线。多条第四信号线122可以包括第一电源线和第二电源线。例如，在衬底的正投影与像素单元P存在交叠的第四信号线122可以为第二电源线，另一条第四信号线122可以为第一电源线。在一些示例中，初始信号线可以沿第二方向Y延伸，例如属于第三信号线；或者，初始信号线可以沿第一方向X延伸，例如属于第一信号线。然而，本实施例对此并不限定。在一些示例中，第一电源线可以与第一电源连接线电连接，第二电源线可以与第二电源连接线电连接，从而实现第一电压信号和第二电压信号的网状传输路线。
在一些示例中，如图7和图8所示，位于第四导电层的一条第四信号线122(例如，第一电源线)在衬底的正投影可以覆盖位于第三导电层的多条(例如，三条或四条)第三信号线121在衬底的正投影。位于第四导电层的另一条第四信号线122(例如，第二电源线)在衬底的正投影与第三信号线121在衬底的正投影可以没有交叠。多条第三信号线121可以通过连接电极与像素单元P的多个像素电路电连接。
本示例提供的透明显示面板，多条第一信号线聚合设计，多条第三信号线和第四信号线聚合设计，并且一条第四信号线与多条第三信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图9为本公开至少一实施例的透明显示面板的另一局部示意图。图10本公开至少一实施例的透明显示面板的一个重复单元的示意图。图9由图10所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图9和图10所示，重复单元10大致呈四边形，例如可以为矩形。按照2×2阵列排布的四个重复单元10的透光子区可以连通成一个透光区A2。透光区A2的四周可以由非透光区A1围绕。重复单元10的非透光区A1可以包括：一个像素单元P以及与像素单元P电连接的一组第一走线11和一组第二走线12。像素单元P的第一子像素P1、第二子像素 P2和第三子像素P3可以沿第一方向X依次排布。一组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111和多条第二信号线112。多条第一信号线111可以沿第二方向Y依次排布，且为同层结构，比如位于第一导电层。例如，多条第一信号线111可以包括：与像素单元P电连接的第一扫描线、第二扫描线、发光控制线和初始信号线。多条第二信号线112可以为同层结构，比如位于第四导电层。例如，多条第二信号线112可以包括：第一电源线和第二电源线。例如，在衬底的正投影与像素单元P存在交叠的第二信号线112可以为第二电源线，另一条第二信号线112可以为第一电源线。一组第二走线12可以包括：沿第二方向Y延伸的多条第三信号线121。多条第三信号线121可以沿第一方向X依次排布，且为同层结构，比如位于第三导电层。在一些示例中，多条第三信号线还可以包括：第一电源连接线和第二电源连接线，第一电源连接线可以与第一电源线电连接，第二电源连接线可以与第二电源线电连接，从而实现第一电压信号和第二电压信号的网状传输路线。
在一些示例中，如图9和图10所示，一条第二信号线112(例如第二电源线)在衬底的正投影可以覆盖多条第一信号线111在衬底的正投影。另一条第二信号线112(例如第一电源线)在衬底的正投影与第一信号线111在衬底的正投影可以没有交叠。在一些示例中，至少一条第二信号线112沿第二方向Y的尺寸(即线宽)可以大于至少两条第一信号线111沿第二方向Y的尺寸。然而，本实施例对此并不限定。在另一些示例中，两条第二信号线在衬底的正投影均可以覆盖多条第一信号线在衬底的正投影。
本示例提供的透明显示面板，多条第一信号线聚合设计，多条第三信号线和第四信号线聚合设计，并且至少一条第二信号线与多条第一信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图11为本公开至少一实施例的透明显示面板的另一局部示意图。图12为本公开至少一实施例的透明显示面板的一个重复单元的示意图。图12由图11所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图11和图12所示，一个重复单元10可以包括：两个像素单元P、一组第一走线11和一组第二走线12。两个像素单元P可以沿第一方向X依次排布。每个像素单元P可以包括：沿第二方向Y依次排布的第一子像素P1、第二子像素P2和第三子像素P3。一组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111(例如可以包括：与所述两个像素单元P电连接的第一扫描线、第二扫描线、发光控制线、初始信号线、第一电源连接线和第二电源连接线)。多条第一信号线111可以为同层结构，比如位于第一导电层。一组第二走线12可以包括：沿第二方向Y延伸的多条第三信号线121和多条第四信号线122。多条第三信号线121可以沿第一方向X依次排布，且为同层结构，比如位于第三导电层。多条第三信号线121可以包括：与两个像素单元P电连接的多条数据线。多条第四信号线122可以位于第四导电层，例如可以包括第一电源线和第二电源线。第二电源线在衬底的正投影可以与其中一个像素单元在衬底的正投影存在交叠。
在一些示例中，如图11和图12所示，一条第四信号线122(例如第一电源线)在衬底的正投影可以覆盖多条第三信号线(例如，与左侧的像素单元P电连接的多条数据线)在衬底的正投影，另一条第四信号线122(例如第二电源线)在衬底的正投影可以覆盖多条第三信号线(例如，与右侧的像素单元P电连接的多条数据线)在衬底的正投影。然而，本实施例对此并不限定。在另一些示例中，其中一条第四信号线在衬底的正投影可以覆盖与两个像素单元电连接的多条数据线在衬底的正投影，另一条第四信号线在衬底的正投影可以与数据线在衬底的正投影没有交叠。
在一些示例中，如图11和图12所示，与一组第二走线12距离较远的一个像素单元P可以通过沿第一方向X延伸的连接线(未示出)实现与该组第二走线(例如包括：数据线)12电连接。
本示例将同一行的相邻两个像素单元电连接的多条数据线进行聚合设计，将同一行的相邻两个像素单元电连接的第一电源线和第二电源线进行聚合设计，并设置至少一条第四信号线与多条第三信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前 述实施例的说明，故于此不再赘述。
图13为本公开至少一实施例的透明显示面板的另一局部示意图。图14为本公开至少一实施例的透明显示面板的一个重复单元的示意图。图14由图13所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图13和图14所示，一个重复单元10可以包括：两个像素单元P、一组第一走线11和一组第二走线12。两个像素单元P可以沿第二方向Y依次排布。每个像素单元P可以包括：沿第一方向X依次排布的第一子像素P1、第二子像素P2和第三子像素P3。一组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111(例如可以包括：与所述两个像素单元P电连接的第一扫描线、第二扫描线、发光控制线以及初始信号线)以及多条第二信号线112(例如包括第一电源线和第二电源线)。与重复单元10中的一个像素单元P的正投影存在交叠的第二信号线112可以为第二电源线，另一条第二信号线112可以为第一电源线。第一电源线和第二电源线可以为同层结构，例如可以位于第四导电层。重复单元10中的另一个像素单元P可以通过沿第二方向Y延伸的多条第一连接线131实现与多条第一信号线111(例如包括：第一扫描线、第二扫描线以及发光控制线等)电连接。多条第一信号线111可以为同层结构，例如位于第一导电层。多条第一连接线131可以为同层结构，例如位于第二导电层或第三导电层。其中一条第二信号线112(例如第二电源线)在衬底的正投影可以覆盖多条第一信号线111(例如与上一个像素单元P电连接的第一信号线)在衬底的正投影，另一条第二信号线112(例如第一电源线)在衬底的正投影可以覆盖多条第一信号线111(例如，与下一个像素单元P电连接的第一信号线)在衬底的正投影。一组第二走线12可以包括多条第三信号线121，多条第三信号线121可以为与两个像素单元P电连接的多条数据线。然而，本实施例对此并不限定。在另一些示例中，其中一条第二信号线在衬底的正投影可以覆盖与两个像素单元电连接的多条第一信号线在衬底的正投影，另一条第二信号线在衬底的正投影可以与第一信号线在衬底的正投影没有交叠。
本示例将同一列的相邻两个像素单元电连接的多条数据线进行聚合设计，将同一列的相邻两个像素单元电连接的第一电源线和第二电源线进行聚合设 计，并设置至少一条第二信号线与多条第一信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图15为本公开至少一实施例的透明显示面板的另一局部示意图。图16为本公开至少一实施例的透明显示面板的一个重复单元的示意图。图15由图16所示的四个重复单元按照2×2阵列排布形成。
在一些示例中，如图15和图16所示，一个重复单元10可以包括：三个像素单元P、一组第一走线11和一组第二走线12。三个像素单元P可以沿第一方向X依次排布。每个像素单元P可以包括：沿第二方向Y依次排布的第一子像素P1、第二子像素P2和第三子像素P3。一组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111(例如可以包括：与所述三个像素单元P电连接的第一扫描线、第二扫描线、发光控制线、初始信号线、第一电源连接线和第二电源连接线)。多条第一信号线111可以为同层结构，比如位于第一导电层。一组第二走线12可以包括：沿第二方向Y延伸的多条第三信号线121和多条第四信号线122。多条第三信号线121可以沿第一方向X依次排布，且为同层结构，比如位于第三导电层。多条第三信号线121可以包括：与三个像素单元P电连接的多条数据线。多条第四信号线122可以位于第四导电层，例如可以包括第一电源线和第二电源线。第二电源线在衬底的正投影可以与中间一个像素单元P在衬底的正投影存在交叠。第一电源线在第一方向X可以位于第二电源线远离中间一个像素单元P的一侧。
在一些示例中，如图15和图16所示，一条第四信号线122(例如第一电源线)在衬底的正投影可以覆盖多条第三信号线(例如，与三个像素单元P电连接的多条数据线)在衬底的正投影，另一条第四信号线122(例如第二电源线)在衬底的正投影与多条第三信号线在衬底的正投影可以没有交叠。然而，本实施例对此并不限定。在另一些示例中，两条第四信号线在衬底的正投影与多条第三信号线在衬底的正投影可以均存在交叠。
在一些示例中，如图15和图16所示，与一组第二走线12距离较远的一个像素单元P可以通过沿第一方向X延伸的连接线(未示出)实现与该组第 二走线(例如包括：数据线)12电连接。
在一些示例中，如图15所示，其中一条第四信号线122在衬底的正投影与移位扫描电路15在衬底的正投影可以存在交叠。移位扫描电路15可以配置为给像素电路提供第一扫描信号、第二扫描信号或发光控制信号。例如，一个重复单元的一条第四信号线122(例如，第二电源线)在衬底的正投影可以与提供第一扫描信号的移位扫描电路在衬底的正投影存在交叠，另一个重复单元的一条第四信号线122(例如，第二电源线)在衬底的正投影可以与提供发光控制信号的移位扫描电路在衬底的正投影存在交叠。与提供第一扫描信号的移位扫描电路存在交叠的第二电源线和与提供发光控制信号的移位扫描电路存在交叠的第二电源线可以相邻。然而，本实施例对此并不限定。例如，前述两条第二电源线可以不相邻。在另一些示例中，分别用于提供第一扫描信号和发光控制信号的移位扫描电路可以与同一条第二电源线在衬底的正投影存在交叠。
在一些示例中，一个移位扫描电路可以包括多个级联的移位寄存器单元，每个移位寄存器单元可以给一行像素单元提供第一扫描信号、第二扫描信号或发光控制信号。例如，与一个移位扫描电路的正投影存在交叠的第四信号线的延伸方向，可以与该移位扫描电路中多个移位寄存器单元的级联方向一致。在一些示例中，一条第四信号线(例如第二电源线)的面积可以大于与该条第四信号线存在交叠的移位扫描电路的正投影面积。例如，一条第四信号线在衬底的正投影可以覆盖至少一个移位扫描电路在衬底的正投影。
在一些示例中，一个移位扫描电路可以与多条第四信号线在衬底的正投影存在交叠。例如，一条第四信号线在衬底的正投影可以与所述移位扫描电路的至少一个移位寄存器单元在衬底的正投影存在交叠。与同一个移位扫描电路在衬底的正投影存在交叠的多条第四信号线可以相邻。然而，本实施例对此并不限定。
在一些示例中，透明显示面板可以包括两个移位扫描电路，其中一个移位扫描电路可以用于提供第一扫描信号和第二扫描信号，另一个移位扫描电路可以用于提供发光控制信号。两个移位扫描电路可以分别与不同的第四信号线在衬底的正投影存在交叠。例如，一个移位扫描电路与一条第四信号线 在衬底的正投影存在交叠。所述两根第四信号线可以尽量相互远离，以降低信号之间干扰的可能性。例如，其中一根第四信号线可以与透明显示面板的左侧边框相邻，另一根第四信号线可以与右侧边框相邻。
本示例将同一行的相邻三个像素单元电连接的多条数据线进行聚合设计，将同一行的相邻三个像素单元电连接的第一电源线和第二电源线进行聚合设计，并设置至少一条第四信号线与多条第三信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。而且，将移位扫描电路设置在非透光区，并与第四信号线进行叠合设计，可以实现窄边框甚至无边框的设计。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图17为本公开至少一实施例的透明显示面板的另一局部示意图。图18为本公开至少一实施例的透明显示面板的一个重复单元的示意图。在一些示例中，如图17和图18所示，一个重复单元10可以包括：非透光区A1和五个透光子区(例如第一透光子区A21至第五透光子区A25)。相邻透光子区之间间隔非透光区A1。
在一些示例中，如图17和图18所示，重复单元10可以大致呈八边形。重复单元10的非透光区A1可以包括：两个像素单元P、一组第一走线11和两组第二走线12。两个像素单元P可以沿第一方向X排布且在第一方向X上可以存在错位。一个像素单元P可以包括：沿第二方向Y依次排布的第一子像素P1、第二子像素P2和第三子像素P3。一组第一走线11可以包括：多条第一信号线111(例如可以包括：与所述两个像素单元P电连接的第一扫描线、第二扫描线、发光控制线、初始信号线、第一电源连接线和第二电源连接线)。多条第一信号线111可以为同层结构，比如位于第一导电层。多条第一信号线111在第一方向X上可以呈折线型，每条第一信号线111可以由沿第一方向X延伸的第一线段和沿第二方向Y延伸的第二线段依次连接形成。每组第二走线12可以包括：沿第二方向Y延伸的多条第三信号线121和多条第四信号线122。多条第三信号线121可以沿第一方向X依次排布，且为同层结构，比如位于第三导电层。每组第二走线12的多条第三信号线121可以包括：与一个像素单元P电连接的多条数据线。每组第二走线12的 多条第四信号线122可以位于第四导电层，例如可以包括第一电源线和第二电源线。第二电源线在衬底的正投影可以与一个像素单元P在衬底的正投影存在交叠。第一电源线在第一方向X可以位于第二电源线远离该像素单元P的一侧。
在一些示例中，如图17和图18所示，每组第二走线12的其中一条第四信号线122(例如第一电源线)在衬底的正投影可以覆盖多条第三信号线(例如，与一个像素单元P电连接的多条数据线)在衬底的正投影，另一条第四信号线122(例如第二电源线)在衬底的正投影与多条第三信号线在衬底的正投影可以没有交叠，该条第四信号线122(例如第二电源线)在衬底的正投影可以与多条第一信号线111的第二线段在衬底的正投影存在交叠。然而，本实施例对此并不限定。在另一些示例中，每条第四信号线在衬底的正投影与多条第三信号线在衬底的正投影可以均存在交叠。
本示例将同一行的两个相邻像素单元进行错位设置，并将同一列的像素单元电连接的多条数据线、第一电源线和第二电源线进行聚合设计，并设置至少一条第四信号线与多条第三信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图19为本公开至少一实施例的透明显示面板的另一局部示意图。图20为本公开至少一实施例的透明显示面板的一个重复单元的示意图。在一些示例中，如图19和图20所示，重复单元10的非透光区可以包括：两个像素单元P、两组第一走线11和一组第二走线12。两个像素单元P可以沿第二方向Y排布且在第二方向Y上可以存在错位。每个像素单元P可以包括：沿第一方向X依次排布的第一子像素P1、第二子像素P2和第三子像素P3。每组第一走线11可以包括：沿第一方向X延伸的多条第一信号线111(例如可以包括：与一个像素单元P电连接的第一扫描线、第二扫描线、发光控制线以及初始信号线)以及多条第二信号线112(例如包括第一电源线和第二电源线)。每组第一走线11的其中一条第二信号线112(例如第二电源线)在衬底的正投影可以与多条第一信号线111在衬底的正投影存在交叠，另一条第 二信号线112(例如，第一电源线)在衬底的正投影可以与第一信号线111在衬底的正投影没有交叠。一组第二走线12可以包括多条第三信号线121，多条第三信号线121可以为与两个像素单元P电连接的多条数据线。多条第三信号线121在第二方向Y上可以呈折线型。例如，每条第三信号线121可以由沿第一方向X延伸的第三线段和沿第二方向Y延伸的第四线段依次连接形成。
本示例将同一列的两个相邻像素单元进行错位设置，并将同一行的像素单元的第一扫描线、第二扫描线、发光控制线、第一电源线和第二电源线进行聚合设计，并设置至少一条第二信号线与多条第一信号线采用叠合设计，可以实现由非透光区围绕的最小单位的透光区的面积最大，从而降低衍射，提高透明显示面板的显示品质。关于本实施例的透明显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图21为本公开至少一实施例的显示装置的示意图。如图21所示，本实施例提供一种显示装置91，包括：透明显示面板910。其中，透明显示面板910可以为Micro-LED显示面板或者Mini-LED显示面板。显示装置91可以为：车窗玻璃、商场橱柜、增强现实(AR，Augmented Reality)设备、虚拟现实(VR，Virtual Reality)设备等任何具有透明显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (22)

  1. 一种透明显示面板，包括：
    衬底；
    在所述衬底上阵列排布的多个重复单元，所述重复单元包括：非透光区和多个透光子区，相邻透光子区之间由非透光区间隔；
    所述非透光区包括：至少一个像素单元以及与所述像素单元电连接的沿第一方向延伸的N组第一走线和沿第二方向延伸的M组第二走线，所述第一方向与所述第二方向交叉，N和M均为正整数，且N和M不同时大于1；
    其中，至少一组第一走线包括：多条第一信号线和至少一条第二信号线，所述至少一条第二信号线在所述衬底的正投影覆盖至少两条第一信号线在所述衬底的正投影；或者，至少一组第二走线包括：多条第三信号线和至少一条第四信号线，所述至少一条第四信号线在所述衬底的正投影覆盖至少两条第三信号线在所述衬底的正投影。
  2. 根据权利要求1所述的透明显示面板，其中，所述至少一条第二信号线沿所述第二方向的尺寸大于所述至少两条第一信号线沿所述第二方向的尺寸。
  3. 根据权利要求1或2所述的透明显示面板，其中，所述至少一条第二信号线位于所述至少两条第一信号线远离所述衬底的一侧。
  4. 根据权利要求1所述的透明显示面板，其中，所述至少一条第四信号线沿所述第一方向的尺寸大于所述至少两条第三信号线沿所述第一方向的尺寸。
  5. 根据权利要求1或4所述的透明显示面板，其中，所述至少一条第四信号线位于所述至少两条第三信号线远离所述衬底的一侧。
  6. 根据权利要求1至5中任一项所述的透明显示面板，其中，所述至少一条第二信号线或所述至少一条第四信号线为电源线。
  7. 根据权利要求1至6中任一项所述的透明显示面板，其中，N和M均为1。
  8. 根据权利要求7所述的透明显示面板，其中，一组第一走线包括多条第一信号线，一组第二走线包括多条第三信号线和至少一条第四信号线；
    所述至少一条第四信号线包括：第一电源线和第二电源线；所述第一电源线和第二电源线中的至少之一在所述衬底的正投影覆盖所述多条第三信号线在所述衬底的正投影。
  9. 根据权利要求8所述的透明显示面板，其中，一组第一走线的多条第一信号线包括：扫描线、发光控制线、第一电源连接线、第二电源连接线；所述第一电源连接线与所述第一电源线电连接，所述第二电源连接线与所述第二电源线电连接。
  10. 根据权利要求8所述的透明显示面板，还包括：移位扫描电路；所述至少一条第四信号线在所述衬底的正投影与所述移位扫描电路存在交叠。
  11. 根据权利要求10所述的透明显示面板，其中，所述重复单元的非透光区包括：三个沿所述第一方向依次排布的像素单元，该组第二走线与第二个像素单元相邻。
  12. 根据权利要求7所述的透明显示面板，其中，一组第一走线包括：多条第一信号线和至少一条第二信号线，一组第二走线包括多条第三信号线；
    所述至少一条第二信号线包括：第一电源线和第二电源线；所述第一电源线和第二电源线中的至少之一在所述衬底的正投影覆盖至少两条第一信号线在所述衬底的正投影。
  13. 根据权利要求12所述的透明显示面板，其中，所述多条第一信号线包括：与所述至少一个像素单元电连接的至少一条扫描线和至少一条发光控制线。
  14. 根据权利要求8至13中任一项所述的透明显示面板，其中，所述多条第三信号线至少包括：所述至少一个像素单元电连接的多条数据线。
  15. 根据权利要求8至14中任一项所述的透明显示面板，其中，所述第二电源线在所述衬底的正投影与所述至少一个像素单元在所述衬底的正投影存在交叠，所述第一电源线位于所述第二电源线远离所述像素单元的一侧。
  16. 根据权利要求8至15中任一项所述的透明显示面板，其中，所述至 少一个像素单元包括：出射不同颜色的多个子像素，每个子像素包括发光元件和与所述发光元件电连接的像素电路，所述发光元件的第一电极通过阳极焊盘与所述像素电路电连接，所述发光元件的第二电极与阴极焊盘电连接，所述阴极焊盘与所述第二电源线为一体结构。
  17. 根据权利要求8至16中任一项所述的透明显示面板，其中，所述第一电源线提供的第一电压信号大于第二电源线提供的第二电压信号。
  18. 根据权利要求1至17中任一项所述的透明显示面板，其中，所述重复单元为四边形。
  19. 根据权利要求1至6中任一项所述的透明显示面板，其中，所述非透光区包括：两个像素单元、一组第一走线和两组第二走线，所述两个像素单元沿所述第一方向排布且存在错位。
  20. 根据权利要求19所述的透明显示面板，其中，一组第一走线包括：多条第一信号线，所述第一信号线包括：依次连接的沿所述第一方向延伸的第一线段和沿所述第二方向延伸的第二线段；两组第二走线均包括：多条第三走线和至少一条第四走线，所述至少一条第四走线在所述衬底的正投影与所述多条第一信号线的第二线段在所述衬底的正投影存在交叠。
  21. 根据权利要求1至20中任一项所述的透明显示面板，其中，所述至少一个像素单元包括：出射不同颜色的多个子像素，每个子像素包括发光元件和与所述发光元件电连接的像素电路，所述子像素的发光元件与所电连接的像素电路在所述衬底的正投影存在交叠。
  22. 一种显示装置，包括如权利要求1至21中任一项所述的透明显示面板。
PCT/CN2022/102500 2022-06-29 2022-06-29 透明显示面板及显示装置 WO2024000310A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2022/102500 WO2024000310A1 (zh) 2022-06-29 2022-06-29 透明显示面板及显示装置
CN202280002075.6A CN117642790A (zh) 2022-06-29 2022-06-29 透明显示面板及显示装置
TW112115103A TW202401398A (zh) 2022-06-29 2023-04-24 透明顯示面板及顯示裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/102500 WO2024000310A1 (zh) 2022-06-29 2022-06-29 透明显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2024000310A1 true WO2024000310A1 (zh) 2024-01-04

Family

ID=89383453

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/102500 WO2024000310A1 (zh) 2022-06-29 2022-06-29 透明显示面板及显示装置

Country Status (3)

Country Link
CN (1) CN117642790A (zh)
TW (1) TW202401398A (zh)
WO (1) WO2024000310A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286298A1 (en) * 2011-05-12 2012-11-15 Universal Display Corporation Bus line designs for large-area oled lighting
CN104134683A (zh) * 2014-05-20 2014-11-05 友达光电股份有限公司 透明显示面板
CN106981585A (zh) * 2017-05-23 2017-07-25 上海天马微电子有限公司 透明oled面板和显示装置
CN107703689A (zh) * 2017-09-18 2018-02-16 上海天马微电子有限公司 一种透明显示面板及显示装置
CN109118956A (zh) * 2018-08-24 2019-01-01 京东方科技集团股份有限公司 一种透明显示面板、显示装置和透明显示面板的制作方法
CN109950293A (zh) * 2019-04-10 2019-06-28 京东方科技集团股份有限公司 一种显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286298A1 (en) * 2011-05-12 2012-11-15 Universal Display Corporation Bus line designs for large-area oled lighting
CN104134683A (zh) * 2014-05-20 2014-11-05 友达光电股份有限公司 透明显示面板
CN106981585A (zh) * 2017-05-23 2017-07-25 上海天马微电子有限公司 透明oled面板和显示装置
CN107703689A (zh) * 2017-09-18 2018-02-16 上海天马微电子有限公司 一种透明显示面板及显示装置
CN109118956A (zh) * 2018-08-24 2019-01-01 京东方科技集团股份有限公司 一种透明显示面板、显示装置和透明显示面板的制作方法
CN109950293A (zh) * 2019-04-10 2019-06-28 京东方科技集团股份有限公司 一种显示面板及显示装置

Also Published As

Publication number Publication date
CN117642790A (zh) 2024-03-01
TW202401398A (zh) 2024-01-01

Similar Documents

Publication Publication Date Title
US9767741B2 (en) Organic electroluminescent display device, driving method thereof
WO2023241490A1 (zh) 显示基板和显示装置
WO2023246338A1 (zh) 显示基板及显示装置
CN115294889B (zh) 显示基板、显示面板及显示装置
WO2023231737A1 (zh) 显示基板及显示装置
WO2024109358A1 (zh) 显示面板及其制备方法、显示装置
CN116229866A (zh) 显示基板及其控制方法、显示装置
WO2024000310A1 (zh) 透明显示面板及显示装置
WO2023246388A1 (zh) 发光二极管器件及其制备方法、显示基板和显示装置
WO2023230785A1 (zh) 显示基板及显示装置
WO2024130634A1 (zh) 显示基板及其制备方法、显示装置
WO2024130652A1 (zh) 显示基板及其制备方法、显示装置
WO2021035538A1 (zh) 显示装置及制备方法、散热膜层以及电子设备
WO2023216200A1 (zh) 显示基板及显示装置
WO2024036511A1 (zh) 显示基板及显示装置
WO2023155138A1 (zh) 显示基板及其制备方法、显示装置
CN220342749U (zh) 显示基板及显示装置
WO2023066104A1 (zh) 显示基板及显示装置
WO2023241296A1 (zh) 显示基板及显示装置
WO2024113181A1 (zh) 显示基板及其制备方法、显示装置
TW201926723A (zh) 顯示裝置
CN217903120U (zh) 显示基板及显示装置
WO2023005795A1 (zh) 一种显示面板和显示装置
WO2023245557A1 (zh) 显示基板及其制备方法、显示装置
WO2024065425A9 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280002075.6

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 18020258

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22948425

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022948425

Country of ref document: EP

Effective date: 20240509