WO2023216200A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023216200A1
WO2023216200A1 PCT/CN2022/092554 CN2022092554W WO2023216200A1 WO 2023216200 A1 WO2023216200 A1 WO 2023216200A1 CN 2022092554 W CN2022092554 W CN 2022092554W WO 2023216200 A1 WO2023216200 A1 WO 2023216200A1
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Prior art keywords
line
electrically connected
conductive layer
layer
trace
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PCT/CN2022/092554
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English (en)
French (fr)
Inventor
陈家兴
龙跃
杜丽丽
李�杰
张毅
尚庭华
李德
刘彪
龙祎璇
牛佐吉
邓江涛
杨小燕
李锡平
李孟
陈渡
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/092554 priority Critical patent/WO2023216200A1/zh
Priority to CN202280001189.9A priority patent/CN117413633A/zh
Publication of WO2023216200A1 publication Critical patent/WO2023216200A1/zh

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  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • Under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of display devices.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • this embodiment provides a display substrate, including: a substrate, a circuit structure layer provided on the substrate, and a light-emitting structure layer located on a side of the circuit structure layer away from the substrate.
  • the substrate includes a display area and a peripheral area located at the periphery of the display area.
  • the display area may include: a first display area and a second display area.
  • the first display area at least partially surrounds the second display area.
  • the circuit structure layer may include: a plurality of pixel circuits located in the first display area, at least one first wiring extending along the first direction, at least one second wiring extending along the second direction, and at least one third wiring located in the peripheral area. Three traces.
  • the light-emitting structure layer may include: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • the plurality of pixel circuits may include a plurality of first pixel circuits and a plurality of second pixel circuits. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements in the first display area, and at least one second pixel among the plurality of second pixel circuits
  • the circuit is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements in the second display area. At least one first trace and at least one second trace in the first display area are electrically connected. At least one third trace is electrically connected to at least one of the following: at least one first trace and at least one second trace. Wherein, the first direction and the second direction intersect.
  • the at least one first trace and the at least one second trace are an integral structure.
  • the plurality of pixel circuits further include: a plurality of inactive pixel circuits, the at least one second trace is in an orthographic projection of the substrate and the at least one inactive pixel circuit is in the substrate. There is overlap in the orthographic projections of .
  • the at least one first trace is located between two adjacent rows of pixel circuits in an orthographic projection of the substrate.
  • the peripheral area includes: a first frame area and a second frame area located on opposite sides of the display area along the second direction; the at least one third trace includes: located on The first power supply line in the first frame area and the first power connection line located in the second frame area; the at least one second wiring and the first power connection line and the first power line At least one of the electrical connections.
  • the first power line includes a first sub-power line and a second sub-power line that are stacked and electrically connected to each other; the at least one second wiring line, the first power connection line It has an integrated structure with the first sub-power cord.
  • the circuit structure layer of the first display area includes: a semiconductor layer, a first conductive layer, a second conductive layer disposed on the substrate. layer and a third conductive layer.
  • the semiconductor layer includes at least: an active layer of a transistor of at least one pixel circuit.
  • the first conductive layer at least includes: a gate of a transistor of the at least one pixel circuit and a first capacitor plate of a storage capacitor.
  • the second conductive layer at least includes: a second capacitor plate of a storage capacitor of the at least one pixel circuit.
  • the third conductive layer at least includes: the first wiring and the second wiring.
  • the circuit structure layer of the first display area further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate.
  • the fourth conductive layer at least includes: data lines, dummy data lines and first power transmission lines.
  • the data line is electrically connected to a plurality of first pixel circuits or a plurality of second pixel circuits
  • the first power transmission line is electrically connected to the plurality of pixel circuits
  • the dummy data line is electrically connected to the second wiring line. connect.
  • the dummy data line and the first power transmission line are both electrically connected to the third wiring.
  • the second conductive layer further includes: a first initial signal line and a second initial signal line; both the first initial signal line and the second initial signal line extend along the first direction.
  • the peripheral area further includes: a first initial peripheral trace and a second initial peripheral trace; the first initial peripheral trace and the second initial peripheral trace extend along the second direction.
  • the first initial signal line is electrically connected to the first initial peripheral wiring through a first initial adapter line; the second initial signal line is electrically connected to the second initial peripheral wiring through a second initial adapter line;
  • the first initial transfer line and the second initial transfer line are located on the third conductive layer.
  • the first conductive layer further includes: scanning lines and light emission control lines extending along the first direction.
  • the peripheral area also includes: scanning output lines and light emission control output lines.
  • the scan line is electrically connected to the scan output line through a scan adapter line;
  • the luminescence control line is electrically connected to the luminescence control output line through a luminescence control adapter line.
  • the scanning transfer line and the lighting control switching line are located on the third conductive layer, and the scanning output line and the lighting control output line are located on the second conductive layer or the first conductive layer.
  • the pixel circuit at least includes: a driving transistor and a first light-emitting control transistor; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control line, and the first electrode is electrically connected to the first power line. connection, the second pole is electrically connected to the first pole of the driving transistor; the third conductive layer also includes: a first shielding electrode; the orthographic projection of the first shielding electrode on the substrate at least partially covers the The channel region of the active layer of the first light emission control transistor is an orthographic projection of the substrate.
  • the pixel circuit further includes: a first reset transistor; a gate electrode of the first reset transistor is electrically connected to a first reset control line, and a first electrode is electrically connected to a first initial signal line, The second electrode is electrically connected to the gate of the driving transistor.
  • the third conductive layer further includes: a second shielding electrode; an orthographic projection of the second shielding electrode on the substrate at least partially covers the channel region of the active layer of the first reset transistor on the substrate. orthographic projection.
  • a third insulating layer is provided between the second conductive layer and the third conductive layer, and the third insulating layer of the first display area is provided with a plurality of via holes; at least one The distance in the second direction between the orthographic projection of the via hole on the substrate and the orthographic projection of at least one trace of the first conductive layer or the second conductive layer on the substrate is greater than or equal to 2 microns in the second direction.
  • this embodiment provides a display device including the display substrate as described above.
  • the display device further includes: a sensor located on a non-display side of the display substrate, where an orthographic projection of the display substrate intersects with the second display area of the display substrate. Stack.
  • Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of the wiring arrangement of the display substrate according to at least one embodiment of the present disclosure.
  • Figure 5 is a partial enlarged schematic diagram of the circuit structure layer of area S1 in Figure 4;
  • Figure 6 is a partial cross-sectional schematic diagram along the Q-Q’ direction in Figure 5;
  • Figure 7 is a partial enlarged schematic diagram of the circuit structure layer of area S2 in Figure 4.
  • Figure 8 is a partial enlarged schematic diagram of the circuit structure layer of area S3 in Figure 4;
  • Figure 9A is a schematic diagram of the circuit structure layer after the semiconductor layer is formed in Figure 5;
  • Figure 9B is a schematic diagram of the circuit structure layer after forming the semiconductor layer in Figure 7;
  • Figure 9C is a schematic diagram of the circuit structure layer after the semiconductor layer is formed in Figure 8.
  • Figure 10A is a schematic diagram of the circuit structure layer after forming the first conductive layer in Figure 5;
  • Figure 10B is a schematic diagram of the circuit structure layer after forming the first conductive layer in Figure 7;
  • Figure 10C is a schematic diagram of the circuit structure layer after forming the first conductive layer in Figure 8.
  • Figure 11A is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 5;
  • Figure 11B is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 7;
  • Figure 11C is a schematic diagram of the circuit structure layer after forming the second conductive layer in Figure 8.
  • Figure 12A is a schematic diagram of the circuit structure layer after forming the third insulating layer in Figure 5;
  • Figure 12B is a schematic diagram of the circuit structure layer after forming the third insulating layer in Figure 7;
  • Figure 12C is a schematic diagram of the circuit structure layer after forming the third insulating layer in Figure 8.
  • Figure 13A is a schematic diagram of the circuit structure layer after forming the third conductive layer in Figure 5;
  • Figure 13B is a schematic diagram of the circuit structure layer after forming the third conductive layer in Figure 7;
  • Figure 13C is a schematic diagram of the circuit structure layer after forming the third conductive layer in Figure 8.
  • Figure 14A is a schematic diagram of the third conductive layer in Figure 5;
  • Figure 14B is a schematic diagram of the third conductive layer in Figure 7;
  • Figure 14C is a schematic diagram of the third conductive layer in Figure 8.
  • Figure 15A is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in Figure 5;
  • Figure 15B is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in Figure 7;
  • Figure 15C is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in Figure 8.
  • Figure 16A is another partially enlarged schematic diagram of the circuit structure layer in area S2 in Figure 5;
  • Figure 16B is a schematic diagram of the circuit structure layer after forming the third conductive layer in Figure 16A;
  • FIG. 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small differences caused by tolerances. Deformation can include leading angles, arc edges, deformation, etc.
  • Light transmittance in this disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • Static electricity will be generated during the process of the pixel circuit of the display substrate due to the antenna effect (for example, exposed metal lines or polysilicon and other conductors, like antennas, will collect charges (such as charged particles generated by plasma etching) Potential increases), static electricity easily accumulates in long wires, resulting in the risk of electrostatic discharge (ESD, Electro-Static Discharge) in the display area.
  • ESD Electro-Static Discharge
  • Embodiments of the present disclosure provide a display substrate, including: a substrate, a circuit structure layer disposed on the substrate, and a light-emitting structure layer located on a side of the circuit structure layer away from the substrate.
  • the substrate includes a display area and a peripheral area located at the periphery of the display area.
  • the display area may include: a first display area and a second display area.
  • the first display area at least partially surrounds the second display area.
  • the circuit structure layer may include: a plurality of pixel circuits located in the first display area, at least one first wiring extending along the first direction, at least one second wiring extending along the second direction, and at least one third wiring located in the peripheral area. Three traces.
  • the light-emitting structure layer may include: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area.
  • the plurality of pixel circuits may include a plurality of first pixel circuits and a plurality of second pixel circuits. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements in the first display area, and at least one second pixel among the plurality of second pixel circuits The circuit is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements in the second display area.
  • At least one first trace and at least one second trace in the first display area are electrically connected.
  • At least one third trace is electrically connected to at least one of the following: at least one first trace and at least one second trace.
  • the first direction and the second direction intersect.
  • the first direction and the second direction may be perpendicular to each other.
  • At least one third trace may be electrically connected to at least one second trace.
  • at least one third trace may extend in the first direction in the peripheral area.
  • at least one third trace may be electrically connected to at least one first trace.
  • at least one third trace may extend in the second direction within the peripheral area.
  • at least one third trace may be electrically connected to at least one first trace and at least one second trace simultaneously.
  • this embodiment is not limited to this.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part The length of the portion extending along direction B is greater than the length of the minor portion extending along the other directions.
  • a extends along direction B means “the main body part of A extends along direction B".
  • first wiring and second wiring that are electrically connected to each other in the first display area, and electrically connecting with the third wiring in the peripheral area through the second wiring, it can be used through the first
  • the traces and second traces establish a static electricity derivation path from the display area to the surrounding area, which can help to deduct static electricity generated during the display substrate process from the display area, thereby effectively reducing ESD risks in the display area.
  • At least one third trace and at least one second trace may be arranged on the same layer.
  • at least one third trace and at least one second trace may be an integral structure.
  • the third trace may be a double-layer trace, and one of the sub- traces may be placed on the same layer as the second trace.
  • at least one third trace and at least one first trace may be arranged on the same layer.
  • at least one third trace, at least one first trace, and at least one second trace may be arranged on the same layer.
  • the first trace and the second trace may be arranged on the same layer. However, this embodiment is not limited to this. In other examples, the first trace and the second trace may be located on different conductive layers and are electrically connected through via holes opened in the insulating layer.
  • At least one first trace and at least one second trace may be an integral structure.
  • at least one first wiring line and at least one second wiring line in the first display area may be electrically connected to form a mesh connection structure.
  • the plurality of pixel circuits in the first display area may further include: a plurality of inactive pixel circuits, at least one second wiring on the front projection of the substrate and at least one inactive pixel circuit on the front surface of the substrate. Projections overlap.
  • the second wiring can be arranged in an area where the inactive pixel circuit is located, which can avoid occupying the space of the effective pixel circuit and can support the extension of the second wiring in the second direction.
  • the orthographic projection of the at least one first trace on the substrate may be located between two adjacent rows of pixel circuits.
  • the first wiring arrangement in this example can avoid occupying the space of the effective pixel circuit and can support the extension of the first wiring in the first direction.
  • the peripheral area may include: a first frame area and a second frame area located on opposite sides of the display area along the second direction.
  • At least one third trace may include: a first power line located in the first frame area and a first power connection line located in the second frame area.
  • At least one second trace may be electrically connected to at least one of the first power connection line and the first power line.
  • at least one second trace may be directly electrically connected to the first power connection line, for example, the two may be an integral structure.
  • the first power line and the first power connection line may extend along the first direction.
  • the second trace is electrically connected to the first power line in the first frame area, and is electrically connected to the first power connection line in the second frame area, which can provide multiple paths for static electricity to be discharged, which is conducive to the discharge of static electricity from the display area.
  • the third trace may be other long wires in the surrounding area.
  • the third trace may include a second power line.
  • the peripheral area may include: a third frame area and a fourth frame area located on opposite sides of the display area along the first direction, the third trace may be located in the third frame area and the fourth frame area, at least one The first trace may extend to the third frame area and the fourth frame area may be electrically connected to the third trace.
  • the third trace may be located in the first frame area, the second frame area, the third frame area and the fourth frame area. In the first frame area and the second frame area, the third trace is connected to at least one The second trace is electrically connected.
  • the third trace can be electrically connected to at least one first trace.
  • a path can be provided for static electricity in the display area to be discharged during the process preparation process, thereby improving the product preparation yield.
  • the first power line may include a first sub-power line and a second sub-power line that are stacked and electrically connected to each other. At least one second trace, the first power connection line and the first sub-power line may be of an integrated structure. In this example, the first power line may have a double-layer wiring structure. However, this embodiment is not limited to this.
  • the circuit structure layer of the first display area may include: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer disposed on the substrate. layer.
  • the semiconductor layer may include at least: an active layer of a transistor of at least one pixel circuit.
  • the first conductive layer may at least include: a gate of a transistor of at least one pixel circuit and a first capacitor plate of a storage capacitor.
  • the second conductive layer may at least include: a second capacitor plate of a storage capacitor of at least one pixel circuit.
  • the third conductive layer may include at least: a first trace and a second trace.
  • the static electricity generated in the process of the display substrate and accumulated in the first conductive layer and the second conductive layer can be removed from the display area. Export to avoid damaging the transistor in the first display area.
  • the circuit structure layer of the first display area may further include: a fourth conductive layer located on a side of the third conductive layer away from the substrate.
  • the fourth conductive layer may include at least: data lines, dummy data lines and first power transmission lines.
  • the data line may be electrically connected to the plurality of first pixel circuits or the plurality of second pixel circuits.
  • the first power transmission line is electrically connected to the plurality of pixel circuits.
  • the dummy data line is electrically connected to the second trace. Both the dummy data line and the first power transmission line are electrically connected to the third trace.
  • the second trace can also be electrically connected to the first power line through a dummy data line, which can provide an electrostatic discharge path in the fourth conductive layer.
  • the second conductive layer may further include: a first initial signal line and a second initial signal line.
  • the first initial signal line and the second initial signal line both extend along the first direction.
  • the peripheral area may further include: a first initial peripheral trace and a second initial peripheral trace.
  • the first initial peripheral trace and the second initial peripheral trace extend along the second direction.
  • the first initial signal line may be electrically connected to the first initial peripheral wiring through the first initial switching wire;
  • the second initial signal line may be electrically connected to the second initial peripheral wiring through the second initial switching wire.
  • the first initial transfer line and the second initial transfer line may be located on the third conductive layer. In this example, using the first initial transfer line and the second initial transfer line of the third conductive layer for signal transfer can be beneficial to conduct static electricity accumulated in the second conductive layer out of the display area.
  • the first conductive layer may further include: scanning lines and light emission control lines extending along the first direction.
  • the surrounding area also includes: scan output lines and lighting control output lines.
  • the scan line can be electrically connected to the scan output line through a scan adapter line.
  • the light-emitting control line can be electrically connected to the light-emitting control output line through the light-emitting control adapter line.
  • the scanning adapter line and the lighting control adapter line may be located on the third conductive layer. In this example, using the scanning transfer line and the light-emitting control transfer line of the third conductive layer for signal transfer can be advantageous in guiding the static electricity accumulated in the first conductive layer out of the display area.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA of the display substrate may include: a first display area A1 and a second display area A2.
  • the first display area A1 at least partially surrounds the second display area A2.
  • the first display area A1 may surround the second display area A2.
  • the second display area A2 can be a light-transmitting display area, which can also be called an under-screen camera (FDC, Full Display With Camera) area; the first display area A1 can be a normal display area.
  • the orthographic projection of the photosensitive sensor (eg, camera and other hardware) on the display substrate may be located in the second display area A2 of the display substrate.
  • the second display area A2 may be circular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be smaller than or equal to the size of the second display area A2 .
  • this embodiment is not limited to this.
  • the second display area A2 may be rectangular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be less than or equal to the size of the inscribed circle of the second display area A2.
  • the second display area A2 may be located at the top middle position of the display area AA.
  • the first display area A1 may surround the second display area A2.
  • this embodiment is not limited to this.
  • the second display area A2 may be located at other locations such as the upper left corner or the upper right corner of the display area AA.
  • the first display area A1 may surround at least one side of the second display area A2.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the second display area A2 may be circular or elliptical. However, this embodiment is not limited to this.
  • the second display area A2 may be in a rectangular, semicircular, pentagonal or other shape.
  • the display area AA may be provided with multiple sub-pixels.
  • At least one sub-pixel may include a pixel circuit and a light emitting element.
  • the pixel circuit is configured to drive the connected light emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light emitting element to emit light.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C (ie, 3 transistors and 1 capacitor) structure, a 7T1C (ie, 7 transistors and 1 capacitor) structure, or a 5T1C (ie, 5 transistors) structure. and 1 capacitor) structure, 8T1C (ie 8 transistors and 1 capacitor) structure or 8T2C (ie 8 transistors and 2 capacitors) structure, etc.
  • the light-emitting element may be a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diodes), or a micro-LED (including: Any of mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the color of the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • one pixel unit of the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels respectively.
  • the shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically or vertically.
  • the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically or squarely.
  • this embodiment is not limited to this.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this exemplary embodiment is explained by taking the 7T1C structure as an example. However, this embodiment is not limited to this.
  • the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst.
  • the six switching transistors may be respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7.
  • the light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the drive transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switching transistors may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Polysilicon
  • oxide thin film transistors uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO).
  • LTPO low-temperature polycrystalline Oxide
  • the display substrate may include: a scan line GL, a data line DL, a first power line PL1 , a second power line PL2 , an emission control line EML, and a first initial signal line INIT1 , the second initial signal line INIT2, the first reset control line RST1 and the second reset control line RST2.
  • the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the scan line GL may be configured to provide the scan signal SCAN to the pixel circuit
  • the data line DL may be configured to provide the data signal DATA to the pixel circuit
  • the emission control line EML may be configured to provide the emission control signal EM to the pixel circuit
  • the first reset control line RST1 The second reset control line RST2 may be configured to provide the first reset control signal RESET1 to the pixel circuit
  • the second reset control line RST2 may be configured to provide the second reset control signal RESET2 to the pixel circuit.
  • the first reset control line RST1 may be electrically connected to the scan line GL of the n-1-th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first The reset control signal RESET1(n) is the same as the scan signal SCAN(n-1).
  • the second reset control line RST2 may be electrically connected to the scan line GL of the n-th row pixel circuit to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n).
  • the second reset control line RST2 electrically connected to the nth row of pixel circuits and the first reset control line RST1 electrically connected to the n+1th row of pixel circuits may be an integrated structure.
  • n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced and the narrow frame design of the display substrate can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the driving transistor T3 is electrically connected to the light-emitting element EL and is controlled by the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.
  • a driving current is output to drive the light-emitting element EL to emit light.
  • the gate electrode of the data writing transistor T4 is electrically connected to the scan line GL
  • the first electrode of the data writing transistor T4 is electrically connected to the data line DL
  • the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan line GL
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3.
  • the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML.
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power line PL1.
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3.
  • the second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML.
  • the anode of element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3.
  • the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the gate of the light-emitting element EL.
  • the anode is reset.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the driving transistor T3.
  • the gate is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the light-emitting element EL. anode electrical connection.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, and the second node N2 is the connection point of the first light emission control transistor T5, the data writing transistor T4 and the threshold compensation transistor T2.
  • the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6.
  • the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting transistor T7. Connection point of component EL.
  • the working process of the pixel circuit is explained below.
  • the pixel circuit shown in FIG. 2 includes a plurality of transistors that are all P-type transistors as an example for explanation.
  • the working process of the pixel driving circuit may include: a first stage, a second stage and a third stage.
  • the first stage is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1.
  • the first node N1 is initialized and the original data voltage in the storage capacitor Cst is cleared.
  • the scanning signal SCAN provided by the scanning line GL is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, causing data to be written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, and the third light-emitting control transistor T5.
  • the two light-emitting control transistors T6 and the second reset transistor T7 are turned off. At this stage, the light-emitting element EL does not emit light.
  • the second stage is called the data writing stage or threshold compensation stage.
  • the scan signal SCAN provided by the scan line GL is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light-emitting control signal EM provided by the light-emitting control line EML are both high-level signals
  • the data line DL outputs Data signal DATA.
  • the driving transistor T3 since the first capacitor plate of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low-level signal, turning on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the third node N2 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2.
  • a node N1 and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst.
  • the voltage of the first capacitor plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. , ensure that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, causing the first reset transistor T1 to turn off.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the third stage is called the luminous stage.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal
  • the scanning signal SCAN provided by the scanning line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on, and the first voltage signal VDD output by the first power line PL1 passes through the turned-on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 .
  • I is the driving current flowing through the driving transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3
  • Vth is the driving transistor T3
  • the threshold voltage of , Vdata is the data voltage output by the data line DL
  • VDD is the first voltage signal output by the first power line PL1.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 3 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the first display area A1 of the display substrate may include: a transition area A1a and a non-transition area A1b.
  • the transition area A1a may be located on at least one side outside the second display area A2 (for example, one side; another example, all around, including the upper and lower sides and the left and right sides).
  • the second display area A2 may include a plurality of second light-emitting elements 14 arranged in an array.
  • the transition area A1a may include a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 arranged in an array, and may also include a plurality of first light-emitting elements.
  • At least one first pixel circuit 11 in the transition area A1a may be electrically connected to at least one first light-emitting element and configured to drive the first light-emitting element to emit light.
  • the front projection of the first light-emitting element on the substrate and the front projection of the electrically connected first pixel circuit 11 on the substrate may at least partially overlap.
  • At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 14 provided in the second display area A2 through a conductive line L (for example, a transparent conductive line), and be configured to drive the second light-emitting element 14 to emit light.
  • a conductive line L for example, a transparent conductive line
  • one end of the conductive line L may be electrically connected to the second pixel circuit 12, and the other end may be electrically connected to the second light-emitting element 14.
  • the conductive line L may extend from the transition area A1a to the second display area A2.
  • the front projection of the second pixel circuit 12 on the substrate and the front projection of the electrically connected second light-emitting element 14 on the substrate may not overlap.
  • each second light-emitting element 14 in the second display area A2 may be electrically connected to the second pixel circuit 12 in the transition area A1a through at least one conductive line L.
  • the second pixel circuit 12 that drives the second light-emitting element 14 in the transition area A1a By disposing the second pixel circuit 12 that drives the second light-emitting element 14 in the transition area A1a, the pixel circuit's blocking of light can be reduced, thereby increasing the light transmittance of the second display area A2.
  • the conductive line L may be made of a transparent conductive material, for example, a conductive oxide material, such as indium tin oxide (ITO), may be used.
  • a transparent conductive material for example, a conductive oxide material, such as indium tin oxide (ITO), may be used.
  • ITO indium tin oxide
  • the non-transition area A1b may include a plurality of first pixel circuits 11 and a plurality of invalid pixel circuits 15 arranged in an array, and may also include a plurality of first light-emitting elements. At least one first pixel circuit 11 in the non-transition area A1b may be electrically connected to at least one first light-emitting element, and the front projection of the first light-emitting element on the substrate is the same as the front projection of the electrically connected first pixel circuit 11 on the substrate. Can at least partially overlap.
  • the transition region A1a and the non-transition region A1b may further include: a plurality of invalid pixel circuits 15 .
  • the invalid pixel circuit may have substantially the same structure as the first pixel circuit and the second pixel circuit in the row or column in which it is located, except that it is not electrically connected to any light-emitting element.
  • the first display area A1 is not only provided with a first pixel circuit electrically connected to the first light-emitting element, but also provided with a second pixel circuit electrically connected to the second light-emitting element, the first display area A1
  • the number of pixel circuits may be greater than the number of first light-emitting elements.
  • the area where the newly added pixel circuit (including the second pixel circuit and the invalid pixel circuit) is provided can be obtained by reducing the size of the first pixel circuit 11 in the first direction D1.
  • the size of the pixel circuit in the first direction D1 may be smaller than the size of the first light emitting element in the first direction D1.
  • the original pixel circuits of each column a can be compressed along the first direction D1, thereby adding an arrangement space for a column of pixel circuits, and the pixel circuits of column a before compression and the pixel circuits after compression
  • the space occupied by the pixel circuits of the a+1 column can be the same.
  • a can be an integer greater than 1.
  • a can be equal to 4.
  • this embodiment is not limited to this.
  • a can be equal to 2 or 3.
  • the original b-row pixel circuits can be compressed along the second direction D2, thereby adding a new row of pixel circuit arrangement space, and the b-row pixel circuits before compression and the b+1 row pixels after compression
  • the space occupied by the circuit is the same.
  • b can be an integer greater than 1.
  • the area where the newly added pixel circuit is provided may be obtained by reducing the size of the first pixel circuit in the first direction D1 and the second direction D2.
  • a row of light-emitting elements may mean that the pixel circuits connected to the row of light-emitting elements are all connected to the same gate line (for example, a scan line).
  • a row of pixel circuits may mean that the row of pixel circuits are all connected to the same gate line.
  • this embodiment is not limited to this.
  • FIG. 4 is a schematic diagram of a wiring arrangement of a display substrate according to at least one embodiment of the present disclosure.
  • the first display area A1 may be provided with a plurality of first traces 231 and a plurality of second traces 232 .
  • the first trace 231 may extend along the first direction D1 in the first display area A1, and the plurality of first traces 231 may be sequentially arranged along the second direction D2.
  • the plurality of second traces 232 may extend along the second direction D2, and the plurality of second traces 232 may be sequentially arranged along the first direction D1.
  • At least one first trace 231 is electrically connected to at least one second trace 232 .
  • first traces 231 in the second direction D2 may be electrically connected to at least one identical second trace 232.
  • a plurality of first wiring lines 231 and a plurality of second wiring lines 232 may be electrically connected in the first display area A1 to form a mesh connection structure.
  • the second wiring 232 may not be provided in the transition area A1a to prevent the arrangement of the second wiring 232 from affecting the arrangement of the data lines electrically connected to the second pixel circuit.
  • the second display area A2 will divide at least one data line into a first sub-data line, a second sub-data line and a third sub-data line.
  • the first sub-data line may be connected to the lower side of the second display area A2 A column of first pixel circuits in the first display area A1 is electrically connected, the second sub-data line can be electrically connected to a column of second pixel circuits in the transition area A1a on the left or right side of the second display area A2, and the third sub-data line
  • the data line may be electrically connected to a column of first pixel circuits in the first display area A1 above the second display area A2.
  • the first sub-data line and the second sub-data line can be electrically connected through the data connection line, and the second sub-data line and the third sub-data line can be electrically connected through the data connection line.
  • the data connection line may extend along the first direction D1.
  • the data connection lines may be arranged in the first display area A1 and located in an area of the first display area A1 close to the second display area A2.
  • the first trace 231 may not extend to the area where the data connection line is located.
  • the first trace 231 may not be provided in the area where the data connection line is located, thereby preventing the trace arrangement from affecting the light transmittance and display effect.
  • the display substrate may further include a fingerprint recognition area, and the first trace may not be provided in the fingerprint recognition area to avoid affecting light transmittance.
  • this embodiment is not limited to this.
  • the peripheral area BB may include: a first frame area B1, a second frame area B2, a third frame area B3, and a fourth frame area B4.
  • the first frame area B1 is connected to the third frame area B3 and the fourth frame area B4, and the second frame area B2 is connected to the third frame area B3 and the fourth frame area B4.
  • the first frame area B1 and the second frame area B2 may be located on opposite sides of the display area AA in the second direction D2, and the third frame area B3 and the fourth frame area B4 may be located on the display area AA in the first direction D1. Opposite sides.
  • the first frame area B1 may be the lower frame of the display substrate
  • the second frame area B2 may be the upper frame of the display substrate
  • the third frame area B3 may be the left frame of the display substrate
  • the fourth frame area B4 may be the display substrate. right border.
  • the structures in the third frame area B3 and the fourth frame area B4 are substantially the same. In the following example, the structure in the third frame area B3 is used as an example for description.
  • the first frame area B1 may include a first power line 26 extending along the first direction D1.
  • the first frame area B1 may include: a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area AA.
  • the first power line 26 may be disposed in the fan-out area.
  • the fan-out area is connected to the display area and may include multiple data lead-out lines. The multiple data lead-out lines are configured to connect the data lines of the display area in a fan-out wiring manner.
  • the bending area may be connected to the fan-out area, may include a composite insulating layer provided with grooves, and be configured to bend the driver chip area and the bonding pin area to the back of the display area AA.
  • the driver chip area can be provided with an integrated circuit (IC, Integrated Circuit), and the integrated circuit can be configured to be connected to multiple data fan-out lines.
  • the bonding pin area can include a bonding pad, and the bonding pad can be configured to be bonded to an external flexible circuit board (FPC, Flexible Printed Circuit).
  • the first power line 26 may be electrically connected to the bonding pad in the bonding pin area to receive the first voltage signal. In some examples, the first power line 26 may be a double-layer wiring.
  • the first sub-power line may include a first sub-power line and a second sub-power line that are electrically connected to each other.
  • the first sub-power line and the second sub-power line may be disposed on Different conductive layers. Orthographic projections of the first sub-power line and the second sub-power line on the substrate may overlap.
  • this embodiment is not limited to this.
  • the first power line may be a single-layer trace.
  • the second frame area B2 may include a first power connection line 233 extending along the first direction D1.
  • the second wiring 232 extending along the second direction D2 in the first display area A1 may be electrically connected to the first power connection line 233 of the second frame area B2, and may also be electrically connected to the first power supply line 26 of the first frame area B1. connect.
  • one end of the second trace 232 may extend to the second frame area B2 and be electrically connected to the first power connection line 233 , and the other end may extend to the first frame area B1 and be electrically connected to the first power line 26 .
  • a static electricity derivation path from the display area to the surrounding area can be provided through the second wiring 232 .
  • the first power line 26 and the first power connection line 233 can be connected in the second direction D2 through the second wiring 232, and there is no need to provide power connection lines in the third frame area B3 and the fourth frame area B4.
  • the third wiring may include: the first power line 26 and the first power connection line 233 .
  • this embodiment is not limited to this.
  • the third trace may include other long wires located in the peripheral area. Through the electrical connection of the first trace, the second trace and the third trace, a path is provided for static electricity in the display area to be discharged.
  • the third frame area B3 may include a circuit area, a power line area, a crack dam area, and a cutting area that are sequentially arranged in a direction away from the display area AA.
  • the circuit area may be connected to the display area AA and may include at least a gate driving circuit, a first initial peripheral wiring 27 and a second initial peripheral wiring 28 .
  • the gate driving circuit may be located on a side of the second initial peripheral wiring 28 away from the display area AA, and the first initial peripheral wiring 27 may be located on a side of the second initial peripheral wiring 28 close to the display area AA.
  • the first initial peripheral trace 27 and the second initial peripheral trace 28 may extend from the third frame area B3 to the first frame area B1, and may, for example, be electrically connected to the bonding pads of the bonding pin area to respectively receive the third frame area B1.
  • the gate driving circuit may be electrically connected to the scanning lines and light emission control lines to which the pixel circuits in the display area are connected.
  • the power line area may be connected to the circuit area and may include at least a frame power lead.
  • the frame power lead may extend in a direction parallel to the edge of the display area and be electrically connected to the cathode of the light emitting element in the display area AA.
  • the crack dam area may be connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area may be connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer.
  • the cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the first initial peripheral trace 27 and the second initial peripheral trace 28 may both be double-layer traces, and the first initial peripheral trace 27 may include first initial sub- traces that are stacked and electrically connected to each other. 271 and the third initial sub-trace 272, the second initial peripheral trace 28 may include a second initial sub-trace 281 and a fourth initial sub-trace 282 that are stacked and electrically connected to each other.
  • this embodiment is not limited to this.
  • the first initial peripheral trace 27 and the second initial peripheral trace 28 may be single-layer traces.
  • FIG. 5 is a partial enlarged schematic diagram of the circuit structure layer in area S1 in FIG. 4 .
  • Figure 6 is a partial cross-sectional view along the Q-Q’ direction in Figure 5.
  • FIG. 7 is a partial enlarged schematic diagram of the circuit structure layer in area S2 in FIG. 4 .
  • FIG. 8 is a partial enlarged schematic diagram of the circuit structure layer in area S3 in FIG. 4 .
  • the first display area A1 may include first circuit areas A11 and second circuit areas A12 that are spaced apart in the first direction D1.
  • the first circuit area A11 may be provided with multiple columns of first pixel circuits 11 (for example, four columns of first pixel circuits), and the second circuit area A12 may be provided with one column of inactive pixel circuits 15 (for example, including multiple inactive pixel circuits) or may be provided with A column of pixel circuits including an inactive pixel circuit and a second pixel circuit.
  • the invalid pixel circuit included in the second circuit area A12 is taken as an example for schematic diagrams.
  • the second wiring may not be provided, or the first wiring and the second wiring may not be provided.
  • the film structure and preparation process of the gate drive circuit in the peripheral area are omitted in the following examples.
  • the display substrate of the first display area A1 may include: a substrate 100 and a semiconductor layer 20 sequentially disposed on the substrate 100 , the first conductive layer 21, the second conductive layer 22, the third conductive layer 23 and the fourth conductive layer 24.
  • a first insulating layer 101 can be disposed between the semiconductor layer 20 and the first conductive layer 21, a second insulating layer 102 can be disposed between the first conductive layer 21 and the second conductive layer 22, and the second conductive layer 22 and the third conductive layer A third insulating layer 103 may be disposed between 23 , and a fourth insulating layer 104 and a fifth insulating layer 105 may be disposed between the third conductive layer 23 and the fourth conductive layer 24 .
  • the first to fourth insulating layers 101 to 104 may all be inorganic insulating layers, and the fifth insulating layer 105 may be an organic insulating layer.
  • the first conductive layer 21 can also be called the first gate metal layer
  • the second conductive layer 22 can also be called the second gate metal layer
  • the third conductive layer 23 can also be called the first source and drain metal layer
  • the fourth conductive layer 24 can also be called the second source and drain metal layer.
  • this embodiment is not limited to this.
  • FIG. 9A is a schematic diagram of the circuit structure layer after forming the semiconductor layer in FIG. 5 .
  • FIG. 9B is a schematic diagram of the circuit structure layer after forming the semiconductor layer in FIG. 7 .
  • FIG. 9C is a schematic diagram of the circuit structure layer after forming the semiconductor layer in FIG. 8 .
  • the semiconductor layer 20 of the first display area A1 may include at least: an active layer of a plurality of transistors of a plurality of pixel circuits (for example, including: a first layer of an inactive pixel circuit).
  • Active layer 510 of the reset transistor, active layer 520 of the threshold compensation transistor, active layer 530 of the driving transistor, active layer 540 of the data writing transistor, active layer 550 of the first light emission control transistor, second light emission control transistor The active layer 560 of the transistor, and the active layer 570 of the second reset transistor; the active layer 310 of the first reset transistor of the first pixel circuit, the active layer 320 of the threshold compensation transistor, the active layer 330 of the driving transistor, The active layer 340 of the data writing transistor, the active layer 350 of the first emission control transistor, the active layer 360 of the second emission control transistor, and the active layer 370 of the second reset transistor).
  • the active layer of seven transistors of one pixel circuit may be an integrated structure.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first and second regions of the active layer may be interpreted as source or drain electrodes of the transistor.
  • Portions of the active layer between transistors can be interpreted as wiring doped with impurities that can be used to electrically connect the transistors.
  • the semiconductor layer 20 of the second frame region B2 may include a plurality of invalid semiconductor blocks 201 .
  • the plurality of invalid semiconductor blocks 201 in the second frame area B2 may be close to the edge of the first display area A1 and may be arranged sequentially along the first direction D1.
  • the semiconductor layer 20 of the first frame area B1 may include a plurality of inactive semiconductor blocks 201.
  • the plurality of invalid semiconductor blocks 201 in the first frame area B1 may be close to the edge of the first display area A1 and may be regularly arranged along the first direction D1 and the second direction D2.
  • a plurality of invalid semiconductor blocks may be provided in the third frame area B3 and the fourth frame area B4, and the invalid semiconductor blocks may be close to the edge of the first display area A1.
  • the invalid semiconductor blocks may be close to the edge of the first display area A1.
  • the material of semiconductor layer 20 may include polysilicon, for example.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the first region and the second region located on both sides of the channel region may be doped with impurities and thus have electrical conductivity. Impurities can vary depending on the type of transistor. However, this embodiment is not limited to this.
  • FIG. 10A is a schematic diagram of the circuit structure layer after forming the first conductive layer in FIG. 5 .
  • FIG. 10B is a schematic diagram of the circuit structure layer after forming the first conductive layer in FIG. 7 .
  • FIG. 10C is a schematic diagram of the circuit structure layer after forming the first conductive layer in FIG. 8 .
  • the first conductive layer 21 of the first display area A1 may at least include: gates of a plurality of transistors of a plurality of pixel circuits and a first capacitor plate of a storage capacitor (for example, the first capacitor plate 581 of the storage capacitor of the inactive pixel circuit, the first capacitor plate 381 of the storage capacitor of the first pixel circuit), the scan lines (for example, the scan lines GL(1), GL(n), GL (N)), light emission control lines (for example, light emission control lines EML(1), EML(n-1), EML(n), EML(N-1) and EML(N)), first reset control lines ( For example, the first reset control lines RST1(1), RST1(n), and RST1(N)) and the second reset control lines (eg, the second reset control lines RST2(1), RST2(n), and RST2(N) ).
  • the scan lines for example, the scan lines GL(1), GL(n), GL (N)
  • light emission control lines for example, light
  • N is greater than or equal to n, and n and N are both integers.
  • the scan line, the light emitting control line, the first reset control line and the second reset control line may all be in the shape of a line with the main body portion extending along the first direction D1.
  • the scan line electrically connected to a row of pixel circuits may be located between the first reset control line and the light-emitting control line electrically connected to the row of pixel circuits.
  • the second reset control line electrically connected to one row of pixel circuits is the first reset control line electrically connected to the next row of pixel circuits.
  • the first reset control line RST1 ( 1 ) overlaps the active layer 310 of the first reset transistor of the first pixel circuit of this row.
  • the area may be used as the gate electrode of the first reset transistor of the first pixel circuit, and the overlapping area with the active layer 510 of the first reset transistor of the inactive pixel circuit of this row may be used as the gate electrode of the first reset transistor of the inactive pixel circuit. .
  • the overlapping area of the scan line GL(1) and the active layer 320 of the threshold compensation transistor of the first pixel circuit of this row can be used as the gate of the threshold compensation transistor of the first pixel circuit, and the overlap area of the threshold compensation transistor of the first pixel circuit of this row.
  • the overlapping area of the active layer 340 of the data writing transistor can be used as the gate electrode of the data writing transistor of the first pixel circuit, and the overlapping area of the active layer 520 of the threshold compensation transistor of the invalid pixel circuit of this row can be used as the gate electrode.
  • the overlapping area of the gate of the threshold compensation transistor of the invalid pixel circuit and the active layer 540 of the data writing transistor of the invalid pixel circuit in this row can serve as the gate of the data writing transistor of the invalid pixel circuit.
  • the overlapping area of the emission control line EML(1) and the active layer 350 of the first emission control transistor of the first pixel circuit of this row can be used as the gate electrode of the first emission control transistor of the first pixel circuit, and the overlap region of the first emission control transistor of this row.
  • the overlapping area of the active layer 360 of the second light-emitting control transistor of the first pixel circuit can be used as the gate of the second light-emitting control transistor of the first pixel circuit, and the overlapped area of the first light-emitting control transistor of the inactive pixel circuit of this row.
  • the overlapping area of the source layer 550 can be used as the gate electrode of the first light-emitting control transistor of the inactive pixel circuit, and the overlapping area of the active layer 560 of the second light-emitting control transistor of the inactive pixel circuit of this row can be used as the gate electrode of the inactive pixel circuit.
  • the overlapping area of the second reset control line RST2(1) and the active layer 370 of the second reset transistor of the first pixel circuit of this row can be used as the gate of the second reset transistor of the first pixel circuit, and the overlapped area of the second reset transistor of the first pixel circuit of this row.
  • the overlapping area of the active layer 570 of the second reset transistor of the inactive pixel circuit may serve as the gate of the second reset transistor of the inactive pixel circuit, and the intersection area with the active layer of the first reset transistor of the first pixel circuit of the next row.
  • the overlapping area can be used as the gate of the first reset transistor of the first pixel circuit of the next row, and the overlapping area with the active layer of the first reset transistor of the inactive pixel circuit of the next row can be used as the first reset of the inactive pixel circuit of the next row.
  • the gate of the transistor is not limited to the gate of the transistor.
  • the shape of the first capacitor plate 381 of the storage capacitor of the first pixel circuit may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projection of the first capacitor plate 381 on the substrate overlaps with the orthographic projection of the active layer 330 of the driving transistor of the first pixel circuit on the substrate.
  • the first capacitor plate 381 of the first pixel circuit can simultaneously serve as a plate of the storage capacitor and the gate of the driving transistor.
  • the shape of the first capacitor plate 581 of the storage capacitor of the invalid pixel circuit may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projection of the first capacitor plate 581 on the substrate overlaps with the orthographic projection of the active layer 530 of the driving transistor of the inactive pixel circuit on the substrate.
  • the first capacitor plate 581 of the inactive pixel circuit can simultaneously serve as a plate of the storage capacitor and the gate of the driving transistor.
  • one end of the first reset control line RST1(n) may extend to the third frame area B3.
  • One end of the second reset control line RST2(n) may extend to the third frame area B3.
  • One end of the light emission control line EML(n) may extend to the third frame area B3.
  • One end of the scan line GL(n) may extend to the third frame area B3.
  • the first conductive layer 21 of the first frame area B1 may include: a plurality of first data fan-out lines 211 .
  • the first data fan-out line 211 may be configured to be electrically connected to the data lines of the first display area A1 in a fan-out wiring manner, and may also be electrically connected to the integrated circuit provided in the driver chip area of the first frame area B1.
  • the first data fanout line 211 may be configured to transmit a data signal to the data line of the first display area A1.
  • FIG. 11A is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 5 .
  • FIG. 11B is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 7 .
  • FIG. 11C is a schematic diagram of the circuit structure layer after forming the second conductive layer in FIG. 8 .
  • the second conductive layer 22 of the first display area A1 may include: second capacitor plates of storage capacitors of a plurality of pixel circuits (for example, a second capacitor plate of the first pixel circuit). Two capacitor plates 382, a second capacitor plate 582 of the invalid pixel circuit, a plurality of first initial signal lines INIT1 and a plurality of second initial signal lines INIT2.
  • the shape of the first initial signal line INIT1 and the second initial signal line INIT2 may be a line shape in which the main body portion extends along the first direction D1.
  • the orthographic projection of the second capacitive plate 382 of the first pixel circuit on the substrate overlaps with the orthographic projection of the first capacitive plate 381 on the substrate.
  • the orthographic projection of the second capacitive plate 582 of the invalid pixel circuit on the substrate overlaps with the orthographic projection of the first capacitive plate 581 on the substrate.
  • the second capacitor plates of storage capacitors of adjacent pixel circuits may be electrically connected to each other, for example, the second capacitor plate 382 of the storage capacitor of the first pixel circuit is connected to the storage capacitor of the inactive pixel circuit.
  • the second capacitor plates 582 of the capacitor may form an integral structure connected to each other.
  • the integrated second capacitor plate can be reused as a power signal connection line to ensure that multiple second capacitor plates in a row of pixel circuits have the same potential, which is beneficial to improving the uniformity of the display substrate and avoiding poor display of the display substrate. , to ensure the display effect of the display substrate.
  • the second capacitive plate 382 of the first pixel circuit may have an opening exposing the first capacitive plate 381 .
  • the second capacitive plate 582 of the inactive pixel circuit may have an opening exposing the first capacitive plate 581 .
  • the second conductive layer 22 of the first frame area B1 may include: a plurality of second data fan-out lines 221 .
  • the second data fan-out line 221 may be configured to be electrically connected to the data lines of the first display area A1 in a fan-out wiring manner, and may also be electrically connected to the integrated circuit provided in the driver chip area of the first frame area B1.
  • the second data fanout line 221 may be configured to transmit a data signal to the data line of the first display area A1.
  • the first data fan-out lines 211 and the second data fan-out lines 221 may be arranged at intervals.
  • both one end of the first initial signal line INIT1 and one end of the second initial signal line INIT2 may extend to the third frame area B3.
  • the second conductive layer 22 of the third frame area B3 may include: a third initial transfer line 222 , a fourth initial transfer line 223 , a scan output line 224 and a lighting control output line 225 .
  • the third initial transfer line 222 is configured to subsequently connect the first initial signal line INIT1 and the first initial peripheral wiring.
  • the fourth initial transfer line 223 is configured to subsequently connect the second initial signal line INIT2 and the second initial peripheral wiring.
  • the scan output line 224 is configured to connect the scan line GL(n) and the scan signal output terminal of the gate driving circuit.
  • the emission control output line 225 is configured to connect the emission control line EML(n) and the emission control signal output terminal of the gate driving circuit.
  • the third initial patching line 222 and the fourth initial patching line 223 may be located on the first conductive layer. However, this embodiment is not limited to this.
  • FIG. 12A is a schematic diagram of the circuit structure layer after forming the third insulating layer in FIG. 5 .
  • FIG. 12B is a schematic diagram of the circuit structure layer after forming the third insulating layer in FIG. 7 .
  • FIG. 12C is a schematic diagram of the circuit structure layer after forming the third insulating layer in FIG. 8 .
  • the third insulating layer 103 of the first display area A1 may be provided with a plurality of via holes, which may include, for example, the first to twentieth via holes V1 to V20 .
  • the third insulating layer 103, the second insulating layer 102 and the first insulating layer 101 in the first to sixth vias V1 to V6 and the eleventh to sixteenth vias V11 to V16 are removed, exposing the semiconductor surface of layer 20.
  • the third insulating layer 103 and the second insulating layer 102 in the seventh via hole V7 and the seventeenth via hole V17 are removed, exposing the surface of the first conductive layer 21 .
  • the third insulating layer 103 in the eighth to tenth via holes V8 to V10 and the eighteenth to twentieth via holes V18 to V20 is removed, exposing the surface of the second conductive layer 22 .
  • At least one of the plurality of vias opened in the third insulating layer 103 is in the orthographic projection of the substrate and at least one trace of the first conductive layer or the second conductive layer.
  • the distance of the orthographic projection of the substrate in the second direction D2 may be greater than or equal to 2 microns.
  • the distance R1 between the upper edge of the fourth via hole V4 in the second direction D2 and the lower edge of the emission control line EML(1) in the second direction D2 may be greater than or equal to 2 microns.
  • the ESD risk is improved by increasing the distance between the vias and the traces of the first conductive layer or the second conductive layer.
  • the third insulating layer 103 of the second frame region B2 may be provided with a plurality of via holes, for example, may include a plurality of twenty-first via holes V21.
  • the third insulating layer 103, the second insulating layer 102 and the first insulating layer 101 in the twenty-first via hole V21 are removed, exposing the surface of the semiconductor layer 20.
  • a twenty-first via V21 may expose a surface of the inactive semiconductor block 201 .
  • the third insulating layer 103 of the first frame area B1 may be provided with multiple via holes, for example, may include multiple twenty-first via holes V21 and twenty-second via holes V22 and the twenty-third via hole V23.
  • the third insulating layer 103, the second insulating layer 102 and the first insulating layer 101 in the twenty-first via hole V21 are removed, exposing the surface of the semiconductor layer 20.
  • the third insulating layer 103 in the twenty-second via hole V22 is removed, exposing the surface of the second data fan-out line 221 of the second conductive layer 22 .
  • the third insulating layer 103 and the second insulating layer 102 in the twenty-third via hole V23 are removed, exposing the surface of the first data fan-out line 211 of the first conductive layer 21 .
  • the third insulating layer 103 of the third frame region B3 may be provided with a plurality of via holes, which may include, for example, the twenty-fourth via hole V24 to the thirty-fourth via hole V34.
  • the third insulating layer 103 in the twenty-fourth via V24 to the thirty-first via V31 is removed, exposing the surface of the second conductive layer 22 .
  • the third insulating layer 103 and the second insulating layer 102 in the thirty-second via hole V32 and the thirty-third via hole V33 are removed, exposing the surface of the first conductive layer 21 .
  • FIG. 13A is a schematic diagram of the circuit structure layer after forming the third conductive layer in FIG. 5 .
  • FIG. 13B is a schematic diagram of the circuit structure layer after forming the third conductive layer in FIG. 7 .
  • FIG. 13C is a schematic diagram of the circuit structure layer after forming the third conductive layer in FIG. 8 .
  • FIG. 14A is a schematic diagram of the third conductive layer in FIG. 5 .
  • FIG. 14B is a schematic diagram of the third conductive layer in FIG. 7 .
  • FIG. 14C is a schematic diagram of the third conductive layer in FIG. 8 .
  • the third conductive layer 23 of the first display area A1 may include: a plurality of connection electrodes (for example, including: the first connection electrode 332, The second connection electrode 322, the third connection electrode 342, the fourth connection electrode 352, the fifth connection electrode 362, the sixth connection electrode 372, the seventh connection electrode 532, the eighth connection electrode 522, the ninth connection electrode 542, the tenth connection electrode
  • the connection electrode 552, the eleventh connection electrode 562 and the twelfth connection electrode 572 a plurality of first wiring lines 231 and a plurality of second wiring lines 232.
  • the first connection electrode 332 may be electrically connected to the first region of the active layer 310 of the first reset transistor 31 of the first pixel circuit through the first via V1.
  • the connection can also be electrically connected to the first initial signal line INIT1 through the eighth via hole V8.
  • the second connection electrode 322 can be electrically connected to the first region of the active layer 320 of the threshold writing transistor 32 of the first pixel circuit through the second via hole V2, and can also be electrically connected to the gate of the driving transistor 33 through the seventh via hole V7. Electrical connection.
  • the third connection electrode 342 may be electrically connected to the first region of the active layer 340 of the data writing transistor 34 of the first pixel circuit through the third via hole V3.
  • the fourth connection electrode 352 can be electrically connected to the first area of the active layer 350 of the first light emission control transistor 35 of the first pixel circuit through the fourth via hole V4, and can also be electrically connected to the third area of the storage capacitor 38 through the seventh via hole V7.
  • the two capacitor plates 382 are electrically connected.
  • the fifth connection electrode 362 may be electrically connected to the second region of the active layer 360 of the second light emission control transistor 36 through the fifth via hole V5.
  • the sixth connection electrode 372 can be electrically connected to the first region of the active layer 370 of the second reset transistor 37 of the first pixel circuit through the sixth via hole V6, and can also be electrically connected to the second initial signal line INIT2 through the tenth via hole V10. Electrical connection.
  • the seventh connection electrode 532 may be electrically connected to the first region of the active layer 510 of the first reset transistor 51 of the invalid pixel circuit through the eleventh via hole V11.
  • the connection can also be electrically connected to the first initial signal line INIT1 through the eighteenth via V18.
  • the eighth connection electrode 522 can be electrically connected to the first region of the active layer 520 of the threshold writing transistor 52 of the invalid pixel circuit through the twelfth via hole V12, and can also be electrically connected to the gate of the driving transistor 53 through the seventeenth via hole V7. Electrical connection.
  • the ninth connection electrode 542 may be electrically connected to the first region of the active layer 540 of the data writing transistor 54 of the invalid pixel circuit through the thirteenth via hole V13.
  • the tenth connection electrode 552 can be electrically connected to the first area of the active layer 550 of the first light emission control transistor 55 of the ineffective pixel circuit through the fourteenth via hole V14, and can also be connected to the storage capacitor 58 through the seventeenth via hole V17.
  • the second capacitor plate 582 is electrically connected.
  • the eleventh connection electrode 562 may be electrically connected to the second region of the active layer 560 of the second light emission control transistor 56 through the fifteenth via hole V15.
  • the twelfth connection electrode 572 can be electrically connected to the first area of the active layer 570 of the second reset transistor 57 of the invalid pixel circuit through the sixteenth via hole V16, and can also be connected to the second initial signal through the twentieth via hole V20.
  • Line INIT2 is electrically connected.
  • the second shielding electrode may include a first connection electrode 332 and a seventh connection electrode 532 .
  • the first shielding electrode may include: a fourth connection electrode 352 and a tenth connection electrode 552 .
  • Orthographic projections of the first connection electrode 332 and the seventh connection electrode 532 on the substrate may be substantially in the shape of a rectangular ring.
  • the orthographic projection of the first connection electrode 332 on the substrate may cover the channel region of the active layer 310 of the first reset transistor 31 of the first pixel circuit.
  • the orthographic projection of the seventh connection electrode 532 on the substrate may at least partially cover the channel region of the active layer 510 of the first reset transistor 51 of the inactive pixel circuit.
  • the orthographic projection of the fourth connection electrode 352 and the tenth connection electrode 552 on the substrate may be approximately D-shaped.
  • the orthographic projection of the fourth connection electrode 352 on the substrate may at least partially cover the channel region of the active layer 350 of the first light emission control transistor 35 of the first pixel circuit.
  • the orthographic projection of the tenth connection electrode 552 on the substrate may at least partially cover the channel region of the active layer 550 of the first light emission control transistor 55 of the inactive pixel circuit.
  • the channel region of the active layer of the first reset transistor and the first light emission control transistor is shielded by the first shielding electrode and the second shielding electrode of the third conductive layer, which can prevent electrostatic accumulation from damaging the active layer. layer, thereby reducing the ESD risk in the display area.
  • the shape of the first trace 231 of the first display area A1 may be a strip trace whose main body portion extends along the first direction D1 .
  • the first wiring 231 may be electrically connected to the fourth connection electrode 352 of the first circuit area A11 and the tenth connection electrode 552 of the second circuit area A12, and may be an integrated structure, for example.
  • the first trace 231 may also be electrically connected to the second trace 232 .
  • the end of the first trace 231 in the first direction D1 may be electrically connected to the second trace 232 .
  • the first trace 231 is located in the first display area A1, is electrically connected to at least one second trace 232, and does not extend to the surrounding area.
  • the front projection of the first trace 231 on the substrate may be located between two adjacent pixel circuit rows, for example, it may be located between the front projection of the light emission control line and the second initial signal line on the substrate.
  • the shape of the second trace 232 may be a line segment whose main body portion extends along the second direction D2.
  • the second trace 232 may be located in the second circuit area A12.
  • the front projection of the second trace 232 on the substrate may overlap with the front projection of at least one invalid pixel circuit in the second circuit area A12 on the substrate.
  • the second wiring 232 may be electrically connected to the ninth connection electrode 542 and the tenth connection electrode 552 of the inactive pixel circuit in the second circuit area A12.
  • the second wiring 232 and the ninth connection electrode 542 and the tenth connection electrode 552 may have an integrated structure.
  • the second trace 232 may include multiple sub-line segments.
  • a sub-line segment may be connected between two adjacent first traces 231 .
  • one end of the sub-line segment may be directly electrically connected to one first wiring 231 , and the other end may be electrically connected to another first wiring 231 through the tenth connection electrode 552 .
  • the plurality of sub-line segments of the second trace 232 may be misaligned in the first direction D1.
  • the first trace 231 and the second trace 232 may be an integral structure.
  • the first wiring 231 and the second wiring 232 are electrically connected to form a mesh connection structure.
  • the third conductive layer 23 of the second frame area B2 may include: a first power connection line 233 .
  • the shape of the first power connection line 233 may be a strip trace whose main body part extends along the first direction D1.
  • the orthographic projection of the first power connection line 233 on the substrate may be located on a side of the plurality of inactive semiconductor blocks 201 away from the first display area A1.
  • the first power connection line 233 is electrically connected to at least one second trace 232 .
  • the first power connection line 233 and the second wiring line 232 may have an integrated structure.
  • the third conductive layer 23 of the first frame area B1 may include: a plurality of data extraction electrodes (for example, the first data extraction electrode 234 and the second data extraction electrode 235 ). , and the first sub-power line 261.
  • the first data lead-out electrode 234 may be electrically connected to the second data fan-out line 221 through two twenty-second via holes V22 arranged side by side.
  • the second data lead-out electrode 235 may be electrically connected to the first data fan-out line 211 through two twenty-third via holes V23 arranged side by side.
  • the main body portion of the first sub-power line 261 may extend along the first direction D1.
  • the first sub-power line 261 may have a plurality of protrusions 2611 facing the first display area A1.
  • the first data extraction electrode 234 may be located between two adjacent protrusions 2611
  • the second data extraction electrode 235 may be located between two adjacent protrusions 2611 .
  • a data extraction electrode may be provided between two adjacent protrusions 2611.
  • At least one second trace 232 may be electrically connected to the first sub-power line 261.
  • a second trace 232 is electrically connected to a protruding portion 2611 of the first sub-power line 261 .
  • the second wiring 232 and the first sub-power line 261 may have an integrated structure.
  • side-by-side arrangement means arrangement along the first direction D1
  • vertical arrangement means arrangement along the second direction D2.
  • the third conductive layer 23 of the third frame area B3 may include: a first initial transfer line 236, a second initial transfer line 237, a first scan transfer block 238, The second scanning transfer block 239, the first lighting control switching block 240, and the second lighting control switching block 241.
  • one end of the first initial transfer line 236 can be electrically connected to the first initial signal line INIT1 through two twenty-fourth vias V24 arranged vertically, and the other end can be
  • the third initial switching line 222 is electrically connected through the two twenty-fifth via holes V25 arranged vertically.
  • the first initial sub-trace 271 may be electrically connected to the third initial transfer line 222 through the two twenty-sixth vias V26 arranged vertically.
  • the electrical connection between the first initial signal line INIT1 and the first initial sub-trace 271 can be achieved through the first initial transfer line 236 of the third conductive layer and the third initial transfer line 222 of the second conductive layer. After the third conductive layer is prepared, the static electricity accumulated on the first initial signal line INIT1 can be guided to the surrounding area through the first initial transfer line 236 and the third initial transfer line 222 .
  • one end of the second initial transfer line 237 can be electrically connected to the second initial signal line INIT2 through two twenty-seventh vias V27 arranged vertically, and the other end can be
  • the fourth initial switching line 223 is electrically connected through two twenty-eighth via holes V28 arranged in a vertical row.
  • the second initial sub-trace 281 may be electrically connected to the fourth initial transfer line 223 through the two twenty-ninth vias V29 arranged vertically.
  • the electrical connection between the second initial signal line INIT2 and the second initial sub-trace 281 can be achieved through the second initial transfer line 237 of the third conductive layer and the fourth initial transfer line 223 of the second conductive layer. After the third conductive layer is prepared, the static electricity accumulated on the second initial signal line INIT2 can be guided to the surrounding area through the second initial transfer line 237 and the fourth initial transfer line 223 .
  • the first scan adapter block 238 may be electrically connected to the scan output line 224 through two thirtieth vias V30 arranged vertically.
  • One end of the second scan adapter block 239 can be electrically connected to one end of the scan line GL(n) through two thirty-fourth vias V34 arranged vertically, and the other end can be electrically connected to one end of the scan line GL(n) through two thirty-third vias V34 arranged horizontally.
  • the via V33 is electrically connected to one end of the second reset control line RST2(n).
  • the orthographic projection of the first scan adapter block 238 on the substrate may be a rounded rectangle, and the orthographic projection of the second scan adapter block 239 on the substrate may be approximately in the shape of a single-sided parenthesis.
  • this embodiment is not limited to this.
  • the first lighting control adapter block 240 may be electrically connected to the lighting control output line 225 through two thirty-first vias V31 arranged vertically.
  • the second light-emitting control adapter block 241 can be electrically connected to one end of the light-emitting control line EML(n) through two thirty-second via holes V32 arranged vertically.
  • the first lighting control adapter block 240 and the second lighting control adapter block 241 are arranged opposite to each other in the first direction D1.
  • the orthographic projections of the first light emission control adapter block 240 and the second light emission control adapter block 241 on the substrate may both be rounded rectangles. However, this embodiment is not limited to this.
  • the wiring 241, the end of the second initial switching wire 237 close to the first display area A1, and the connection end of the second scanning switching block 239 and the second reset control line may be aligned in the second direction D2 and arranged in sequence.
  • the end of the first initial switching line 236 away from the first display area A1, the first scanning switching block 238, the first lighting control switching block 240, and the end of the second initial switching wire 237 away from the first display area A1 The parts may be aligned in the second direction D2 and arranged sequentially.
  • FIG. 15A is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in FIG. 5 .
  • FIG. 15B is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in FIG. 7 .
  • FIG. 15C is a schematic diagram of the circuit structure layer after forming the fifth insulating layer in FIG. 8 .
  • the fifth insulating layer 105 of the first display area A1 may be provided with multiple via holes, for example, may include the 41st to 46th via holes V41 to 46th via holes. V46.
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the forty-first to forty-sixth via holes V41 to V46 are removed, exposing the surface of the third conductive layer 23 .
  • the fifth insulating layer 105 of the second frame region B2 may be provided with multiple via holes, for example, may include a plurality of forty-seventh via holes V47.
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the forty-seventh via hole V47 are removed, exposing the surface of the first power connection line 233 of the third conductive layer 23 .
  • the fifth insulating layer 105 of the first frame region B1 may be provided with multiple via holes, which may include, for example, the forty-eighth via hole V48 and the forty-ninth via hole V49.
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the forty-eighth via hole V48 are removed, exposing the surface of the first data extraction electrode 234 of the third conductive layer 23 .
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the forty-ninth via hole V49 are removed, exposing the surface of the second data lead-out electrode 235 of the third conductive layer 23.
  • the fifth insulating layer 105 of the first frame area B1 may also be provided with via holes or grooves that expose the surface of the first sub-power line 261 .
  • the fifth insulating layer 105 of the third frame region B3 may be provided with multiple via holes and multiple grooves, for example, may include fifty-first to fifty-eighth via holes V51 to fifty-eighth.
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the first groove K1 are removed, exposing the surface of the first initial sub-trace 271 of the third conductive layer 23 .
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the second groove K2 are removed, exposing the surface of the second initial sub-trace 281 of the third conductive layer 23 .
  • the fifth insulating layer 105 and the fourth insulating layer 104 in the fifty-first via hole V51 to the fifty-eighth via hole V58 are removed, exposing the surface of the third conductive layer 23 .
  • the fourth conductive layer 24 of the first display area A1 may include: a plurality of anode connection electrodes (for example, the first anode connection electrode 242 and the inactive anode connection electrode 243), a plurality of data lines 244, a plurality of dummy data lines 245, and a plurality of first power transmission lines 246 and 247.
  • the data line 244, the dummy data line 245, and the first power transmission lines 246 and 247 may all extend along the second direction D2.
  • the first anode connection electrode 242 may be located in the first circuit area A11 and be electrically connected to the fifth connection electrode 362 through the forty-second via hole V42.
  • the first anode connection electrode 242 may subsequently be electrically connected to the anode of the first light-emitting element to achieve electrical connection between the first pixel circuit and the first light-emitting element.
  • the inactive anode connection electrode 243 may be electrically connected to the eleventh connection electrode 562 through the forty-fifth via hole V45.
  • the inactive anode connection electrode 243 does not need to be electrically connected to the anode of the light-emitting element subsequently.
  • the data line 244 may be located within the first circuit area A11.
  • the data line 244 may be electrically connected to the third connection electrode 342 through the forty-first via hole V41.
  • Data line 244 may be configured to provide a data signal to data write transistor 34 of the first pixel circuit.
  • the dummy data line 245 may be located within the second circuit area A12.
  • the dummy data line 245 may be electrically connected to the ninth connection electrode 542 through the forty-fourth via hole V44. Since the ninth connection electrode 542 and the second wiring 232 have an integrated structure, the dummy data line 245 is electrically connected to the second wiring 232 .
  • the orthographic projection of the dummy data line 245 on the substrate and the orthographic projection of the second trace 232 on the substrate may overlap.
  • the dummy data line 245 may provide the first voltage signal as a data signal to the data writing transistor 54 of the inactive pixel circuit.
  • the first power transmission line 246 may be located in the first circuit area A11 and be electrically connected to the fourth connection electrode 352 through the forty-third via hole V43.
  • the first power transmission line 246 may be configured to provide the first voltage signal to the first pixel circuit.
  • the first power transmission line 247 may be located in the second circuit area A12 and be electrically connected to the tenth connection electrode 552 through the forty-sixth via hole V46. Since the tenth connection electrode 552 and the second wiring 232 have an integrated structure, the first power transmission line 247 and the second wiring 232 are electrically connected.
  • the front projection of the first power transmission line 247 on the substrate and the front projection of the second trace 232 on the substrate may overlap.
  • the first power transmission lines 246 and 247 can extend to the second frame area B2, and are each electrically connected to the first power connection line 233 through the forty-seventh via hole V47.
  • static electricity in the display area may be led out to the surrounding area via the first power transmission lines 246 and 247 through the second trace 232 .
  • the fourth conductive layer 24 of the first frame area B1 may include: a second sub-power line 262 .
  • the second sub-power line 262 may extend along the first direction D1 and be electrically connected to the first sub-power line 261 through a via hole or groove opened in the fifth insulation layer 105 .
  • the dummy data line 245 may extend to the first frame area B1 and be electrically connected to the second sub-power line 262 .
  • the dummy data line 245 and the second sub-power line 262 may have an integrated structure.
  • the first power transmission lines 246 and 247 may extend to the first frame area B1 and be electrically connected to the second sub-power line 262 .
  • the first power transmission lines 246 and 247 and the second sub-power line 262 may have an integrated structure.
  • the fourth conductive layer 24 of the third frame area B3 may include: a fifth initial transfer line 252, a sixth initial transfer line 253, a scanning transfer line 254, a lighting control transfer line 255, The third initial sub-trace 272, and the fourth initial sub-trace 282.
  • One end of the fifth initial transfer line 252 can be electrically connected to one end of the first initial transfer line 236 through the fifty-first via V51, and the other end can be connected to the other end of the first initial transfer line 236 through the fifty-second via V52. Electrical connection.
  • One end of the sixth initial transfer line 253 can be electrically connected to one end of the second initial transfer line 237 through the fifty-third via V53, and the other end can be connected to the other end of the second initial transfer line 237 through the fifty-fourth via V54. Electrical connection.
  • One end of the scan adapter line 254 can be electrically connected to the second scan adapter block 239 through the 55th via hole V55, and the other end can be electrically connected to the first scan adapter block 238 through the 56th via hole V56.
  • One end of the lighting control adapter line 255 can be electrically connected to the second lighting control adapter block 241 through the 57th via V57, and the other end can be electrically connected to the first lighting control adapter block 240 through the 58th via V58. .
  • the fifth initial switching wire 252, the scanning switching wire 254, the lighting control switching wire 255 and the sixth initial switching wire 253 are sequentially arranged along the second direction D2.
  • the fifth initial transfer line 252 and the sixth initial transfer line 253 are sequentially arranged along the second direction D2.
  • both the third initial sub-trace 272 and the fourth initial sub-trace 282 extend along the second direction D2.
  • the third initial sub-trace 272 may be electrically connected to the first initial sub-trace 271 through the first groove K1.
  • the fourth initial sub-trace 282 may be electrically connected to the second initial sub-trace 281 through the second groove K2.
  • both the first initial peripheral trace 27 and the second initial peripheral trace 28 may be double-layer traces.
  • the film layer structure of the second pixel circuit may be referred to the structure of the first pixel circuit, and therefore will not be described again.
  • the structure of the fourth frame area can refer to the structure of the third frame area, so no details are given here.
  • the preparation process of the display substrate is exemplified below.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the preparation process of the display substrate may include the following operations.
  • a semiconductor film is deposited on the substrate 100, the semiconductor film is patterned through a patterning process, and the first display area A1 and the surrounding area form the semiconductor layer 20, as shown in FIGS. 9A to 9C.
  • the substrate 100 may be a rigid substrate, such as a glass substrate.
  • the base substrate may be a flexible substrate.
  • a first insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned through a patterning process to form a third layer covering the semiconductor layer 20 .
  • the first conductive layer 21 can be used as a shield to perform a conductive process on the semiconductor layer 20 , and the semiconductor layer 20 in the area blocked by the first conductive layer 21 can form a channel of a transistor. Areas of the semiconductor layer 20 that are not blocked by the first conductive layer 21 may be conductive, that is, both the first area and the second area of the active layer of the seven transistors of the pixel circuit may be conductive.
  • a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form the second insulating layer 102, and a second conductive layer 22 disposed on the second insulating layer 102, as shown in FIGS. 11A to 11C.
  • a third insulating film is deposited on the substrate 100 on which the foregoing pattern is formed, and the third insulating film is patterned through a patterning process to form a third insulating layer 103, as shown in FIGS. 12A to 12C Show.
  • the third insulating layer 103 may be provided with a plurality of via holes.
  • the plurality of via holes may expose the surfaces of the semiconductor layer 20 , the first conductive layer 21 and the second conductive layer 22 respectively.
  • a third conductive film is deposited on the substrate 100 on which the foregoing pattern is formed, the third conductive film is patterned through a patterning process, and the third conductive layer 23 is formed on the third insulating layer 103, As shown in Figures 13A to 13C and 14A to 14C.
  • the third conductive layer 23 of the first display area A1 may include first wiring lines 231 and second wiring lines 232 forming a mesh connection structure.
  • the second trace 232 may be located in the second circuit area A12.
  • the first trace 231 may be located between adjacent rows of pixel circuits.
  • the second trace 232 can extend to the second frame area B2 to be electrically connected to the first power connection line 233 , and can also extend to the first frame area B1 to be electrically connected to the first sub-power line 261 of the first power line 26 .
  • the long wires of the first conductive layer and the second conductive layer are prone to accumulate static electricity because they have no path to transfer other signal wires.
  • the first conductive layer and the second conductive layer are connected to the active layer of the transistor through the third conductive layer, since the resistance value at the channel formed by the active layer changes from small resistance to large resistance, static electricity easily changes in the resistance value. Released anywhere, causing damage to the transistor.
  • the static electricity accumulated in the first conductive layer and the second conductive layer can be passed through the first wiring and the second trace are conducted to the surrounding area to prevent ESD from damaging the transistors in the display area, which can reduce the ESD risk in the display area.
  • static electricity generated during the process accumulates at the second conductive layer of the first light-emitting control transistor.
  • the static electricity can be connected to the second trace through the first trace. line, and then introduced into the surrounding area through the second trace.
  • a connection electrode that can cover the channel region of the active layer of the first light emitting transistor and a connection electrode that covers the channel region of the active layer of the first reset control transistor ESD risks in the display area can be reduced.
  • a first initial transfer line located on the third conductive layer is electrically connected to the first initial peripheral trace and the first initial signal line
  • a second initial transfer line is electrically connected to the second initial peripheral trace.
  • the static electricity generated in the second conductive layer can be facilitated to be guided out of the display area through the third conductive layer.
  • static electricity generated by the process will accumulate on the first initial signal line and the second initial signal line.
  • the static electricity can pass through the first initial signal line of the third conductive layer.
  • the initial transfer line and the second initial transfer line are introduced into the surrounding area to avoid ESD damage to the transistor.
  • a fourth insulating film is deposited on the substrate 100 on which the foregoing pattern is formed to form the fourth insulating layer 104; subsequently, a fifth insulating film is coated, and the fifth insulating film is subjected to a patterning process. Patterning is performed to form a fifth insulating layer 105, as shown in FIGS. 15A to 15C.
  • the fourth insulating layer 104 can be etched to form the via holes or grooves opened in the fourth insulating layer 104 to expose the third insulating layer 104 . surface of the conductive layer.
  • a fourth conductive film is deposited on the substrate 100 on which the foregoing pattern is formed, and the fourth conductive film is patterned through a patterning process to form the fourth conductive layer 24, as shown in Figures 5, 7, and As shown in Figure 8.
  • the second display area A2 may include a substrate 100 and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104 and a fifth insulating layer 105 stacked on the substrate 100.
  • the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer.
  • a first flat film is coated on the base substrate on which the foregoing pattern is formed, and the first flat film is patterned through a patterning process to form a first flat layer.
  • a transparent conductive film is deposited on the substrate with the foregoing pattern, and the transparent conductive film is patterned through a patterning process to form a transparent conductive layer.
  • the transparent conductive layer may include transparent conductive lines electrically connecting the second pixel circuit and the second light emitting element.
  • a second flat film is coated on the base substrate with the foregoing pattern, and the second flat film is patterned through a patterning process to form a second flat layer.
  • an anode film is deposited on the base substrate with the foregoing pattern, and the anode film is patterned through a patterning process to form an anode layer.
  • a pixel definition film is coated on the substrate on which the foregoing pattern is formed, and a pixel definition layer is formed through masking, exposure and development processes.
  • the pixel definition layer is formed with a plurality of pixel openings exposing the anode layer.
  • an organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode layer.
  • the cathode layer is electrically connected to the organic light-emitting layer and the second power line respectively.
  • an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • multiple transparent conductive layers may be provided, and multiple transparent conductive lines may be arranged in the multiple transparent conductive layers. At least one flat layer may be disposed between adjacent transparent conductive layers.
  • the first conductive layer 21 , the second conductive layer 22 , the third conductive layer 23 and the fourth conductive layer 24 may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al). ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, Such as Mo/Cu/Mo, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al).
  • Mo molybdenum
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, Such as Mo/Cu/Mo, etc.
  • the first insulating layer 101, the second insulating layer 102, the third insulating layer 103 and the fourth insulating layer 104 can be made of any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Or more, it can be single layer, multi-layer or composite layer.
  • the first insulation layer 101 and the second insulation layer 102 may be called gate insulation (GI) layers
  • the third insulation layer 103 may be called an interlayer insulation (ILD) layer
  • the fourth insulation layer 104 may be called passivation. layer.
  • the fifth insulating layer 105, the first flat layer and the second flat layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials.
  • this embodiment is not limited to this.
  • the structure of the display substrate and its preparation process in this embodiment are only illustrative. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the first trace may be located on the second conductive layer
  • the second trace may be located on the third conductive layer
  • the first trace and the second trace may be electrically connected through a via hole opened in the third insulating layer.
  • the first power line may extend to the third frame area and the fourth frame area
  • the first wiring may extend to the third frame area and the fourth frame area, and be directly electrically connected to the first power line.
  • this embodiment is not limited to this.
  • the preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, and is well compatible with existing preparation processes.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • the display substrate provided in this embodiment forms a mesh connection structure by arranging first wiring and second wiring in the display area, and the second wiring can be connected with the third wiring in the peripheral area (for example, including the first power supply).
  • the electrical connection between the first power supply connection line and the first power supply connection line can facilitate the conduction of static electricity generated during the process to the display area.
  • arranging the first initial transfer line and the second initial transfer line located on the third conductive layer in the peripheral area realizes the electrical connection between the initial signal line and the initial peripheral wiring, which can be beneficial to ESD generated in the second conductive layer. Exporting the display area reduces the incidence of ESD defects in the display area and improves the product yield of the display substrate.
  • FIG. 16A is another partially enlarged schematic diagram of the circuit structure layer in area S2 in FIG. 5 .
  • FIG. 16B is a schematic diagram of the circuit structure layer after forming the third conductive layer in FIG. 16A.
  • the third conductive layer 23 of the third frame area B3 may include: a first initial transfer line 236 , a second initial transfer line 237 , a scanning transfer line 254 , a lighting control transfer line Wiring 255, second scan switching block 239, first initial sub-trace 271 and second initial sub-trace 281.
  • the first initial transfer line 236 may be electrically connected to the first initial signal line INIT1 and electrically connected to the first initial sub-line 271 of the third conductive layer 23 through the third initial transfer line of the second conductive layer 22 .
  • the second initial transfer line 237 may be electrically connected to the second initial signal line INIT2 and electrically connected to the second initial sub-line 281 of the third conductive layer 23 through the fourth initial transfer line of the second conductive layer 22 .
  • the scan adapter line 254 may be an integral structure with the second scan adapter block 239 .
  • the scan adapter line 254 can realize the electrical connection between the scan line and the scan output line located on the second conductive layer.
  • the light-emitting control adapter line 255 can realize the electrical connection between the light-emitting control line and the light-emitting control output line located on the second conductive layer.
  • arranging scanning transfer lines and light emission control transfer lines located on the third conductive layer in the peripheral area can help static electricity generated in the first conductive layer to be exported to the display area through the third conductive layer.
  • static electricity generated by the process will accumulate on the scan lines, light emission control lines, first reset control lines and second reset control lines.
  • the static electricity can pass through The scanning transfer lines and light-emitting control transfer lines of the third conductive layer are introduced into the surrounding area to avoid ESD damage to the transistors.
  • At least one embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • FIG. 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • this embodiment provides a display device, including: a display substrate 91 and a photosensitive sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91 .
  • the photosensitive sensor 92 is located on the non-display surface side of the display substrate 91 .
  • the orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the first display area A1.
  • the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be a product with a function of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • the display device can be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a camcorder, Any product including viewfinders, navigators, vehicles, large-area walls, information query equipment (such as business query equipment for e-government, banks, hospitals, electric power and other departments), monitors, etc.
  • the display device may also be a microdisplay, a VR device or an AR device including a microdisplay, or any other product.

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Abstract

一种显示基板，包括：衬底(100)、设置在衬底(100)上的电路结构层以及发光结构层。电路结构层包括：位于第一显示区(A1)的多个像素电路、沿第一方向(D1)延伸的至少一条第一走线231、沿第二方向(D2)延伸的至少一条第二走线232、以及位于周边区域(BB)的至少一条第三走线。至少一条第一走线(231)与至少一条第二走线(232)电连接，至少一条第三走线与以下至少一项电连接：至少一条第一条走线(231)、至少一条第二走线(232)。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：衬底、设置在衬底上的电路结构层、以及位于电路结构层远离衬底一侧的发光结构层。衬底包括显示区域以及位于显示区域外围的周边区域。显示区域可以包括：第一显示区和第二显示区。第一显示区至少部分围绕第二显示区。电路结构层可以包括：位于第一显示区的多个像素电路、沿第一方向延伸的至少一条第一走线、沿第二方向延伸的至少一条第二走线以及位于周边区域的至少一条第三走线。发光结构层可以包括：位于第一显示区的多个第一发光元件以及位于第二显示区的多个第二发光元件。多个像素电路可以包括多个第一像素电路和多个第二像素电路。多个第一像素电路中的至少一个第一像素电路与第一显示区的多个第一发光元件中的至少一个第一发光元件电连接，多个第二像素电路中的至少一个第二像素电路与第二显示区的多个第二发光元件中的至少一个第二发光元件电连接。第一显示区的至少一条第一走线和至少一条第二走线 电连接。至少一条第三走线与以下至少一项电连接：至少一条第一走线、至少一条第二走线。其中，第一方向与第二方向交叉。
在一些示例性实施方式中，所述至少一条第一走线与所述至少一条第二走线为一体结构。
在一些示例性实施方式中，所述多个像素电路还包括：多个无效像素电路，所述至少一条第二走线在所述衬底的正投影与至少一个无效像素电路在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述至少一条第一走线在所述衬底的正投影位于相邻两行像素电路之间。
在一些示例性实施方式中，所述周边区域包括：沿所述第二方向位于所述显示区域相对两侧的第一边框区和第二边框区；所述至少一条第三走线包括：位于所述第一边框区的第一电源线以及位于所述第二边框区的第一电源连接线；所述至少一条第二走线与所述第一电源连接线和所述第一电源线中的至少之一电连接。
在一些示例性实施方式中，所述第一电源线包括叠设且相互电连接的第一子电源线和第二子电源线；所述至少一条第二走线、所述第一电源连接线和所述第一子电源线为一体结构。
在一些示例性实施方式中，在垂直于所述显示基板的方向上，所述第一显示区的电路结构层包括：设置在所述衬底上的半导体层、第一导电层、第二导电层和第三导电层。所述半导体层至少包括：至少一个像素电路的晶体管的有源层。所述第一导电层至少包括：所述至少一个像素电路的晶体管的栅极以及存储电容的第一电容极板。所述第二导电层至少包括：所述至少一个像素电路的存储电容的第二电容极板。所述第三导电层至少包括：所述第一走线和所述第二走线。
在一些示例性实施方式中，所述第一显示区的电路结构层还包括：位于所述第三导电层远离所述衬底一侧的第四导电层。所述第四导电层至少包括：数据线、虚设数据线以及第一电源传输线。所述数据线与多个第一像素电路或多个第二像素电路电连接，所述第一电源传输线与所述多个像素电路电连接，所述虚设数据线与所述第二走线电连接。所述虚设数据线和所述第一电 源传输线均与所述第三走线电连接。
在一些示例性实施方式中，所述第二导电层还包括：第一初始信号线和第二初始信号线；所述第一初始信号线和第二初始信号线均沿所述第一方向延伸。所述周边区域还包括：第一初始周边走线和第二初始周边走线；所述第一初始周边走线和第二初始周边走线沿所述第二方向延伸。所述第一初始信号线通过第一初始转接线与所述第一初始周边走线电连接；所述第二初始信号线通过第二初始转接线与所述第二初始周边走线电连接；所述第一初始转接线与所述第二初始转接线位于所述第三导电层。
在一些示例性实施方式中，所述第一导电层还包括：沿所述第一方向延伸的扫描线和发光控制线。所述周边区域还包括：扫描输出线和发光控制输出线。所述扫描线通过扫描转接线与所述扫描输出线电连接；所述发光控制线通过发光控制转接线与所述发光控制输出线电连接。所述扫描转接线和所述发光控制转接线位于所述第三导电层，所述扫描输出线和发光控制输出线位于所述第二导电层或第一导电层。
在一些示例性实施方式中，所述像素电路至少包括：驱动晶体管、第一发光控制晶体管；所述第一发光控制晶体管的栅极与发光控制线电连接，第一极与第一电源线电连接，第二极与所述驱动晶体管的第一极电连接；所述第三导电层还包括：第一遮挡电极；所述第一遮挡电极在所述衬底的正投影至少部分覆盖所述第一发光控制晶体管的有源层的沟道区在所述衬底的正投影。
在一些示例性实施方式中，所述像素电路还包括：第一复位晶体管；所述第一复位晶体管的栅极与第一复位控制线电连接，第一极与第一初始信号线电连接，第二极与所述驱动晶体管的栅极电连接。所述第三导电层还包括：第二遮挡电极；所述第二遮挡电极在所述衬底的正投影至少部分覆盖所述第一复位晶体管的有源层的沟道区在所述衬底的正投影。
在一些示例性实施方式中，所述第二导电层与所述第三导电层之间设置有第三绝缘层，所述第一显示区的第三绝缘层开设有多个过孔；至少一个过孔在所述衬底的正投影与所述第一导电层或第二导电层的至少一条走线在所述衬底的正投影在所述第二方向的距离大于或等于2微米。
另一方面，本实施例提供一种显示装置，包括如上所述的显示基板。
在一些示例性实施方式中，显示装置还包括：位于所述显示基板的非显示面一侧的传感器，所述传感器在所述显示基板的正投影与所述显示基板的第二显示区存在交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为本公开至少一实施例的显示基板的局部示意图；
图4为本公开至少一实施例的显示基板的走线排布示意图；
图5为图4中区域S1的电路结构层的局部放大示意图；
图6为图5中沿Q-Q’方向的局部剖面示意图；
图7为图4中区域S2的电路结构层的局部放大示意图；
图8为图4中区域S3的电路结构层的局部放大示意图；
图9A为图5中形成半导体层后的电路结构层的示意图；
图9B为图7中形成半导体层后的电路结构层的示意图；
图9C为图8中形成半导体层后的电路结构层的示意图；
图10A为图5中形成第一导电层后的电路结构层的示意图；
图10B为图7中形成第一导电层后的电路结构层的示意图；
图10C为图8中形成第一导电层后的电路结构层的示意图；
图11A为图5中形成第二导电层后的电路结构层的示意图；
图11B为图7中形成第二导电层后的电路结构层的示意图；
图11C为图8中形成第二导电层后的电路结构层的示意图；
图12A为图5中形成第三绝缘层后的电路结构层的示意图；
图12B为图7中形成第三绝缘层后的电路结构层的示意图；
图12C为图8中形成第三绝缘层后的电路结构层的示意图；
图13A为图5中形成第三导电层后的电路结构层的示意图；
图13B为图7中形成第三导电层后的电路结构层的示意图；
图13C为图8中形成第三导电层后的电路结构层的示意图；
图14A为图5中的第三导电层的示意图；
图14B为图7中的第三导电层的示意图；
图14C为图8中的第三导电层的示意图；
图15A为图5中形成第五绝缘层后的电路结构层的示意图；
图15B为图7中形成第五绝缘层后的电路结构层的示意图；
图15C为图8中形成第五绝缘层后的电路结构层的示意图；
图16A为图5中区域S2的电路结构层的另一局部放大示意图；
图16B为图16A中形成第三导电层后的电路结构层的示意图；
图17为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、 层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作 中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在显示基板的像素电路的工艺制程中会产生静电，由于天线效应(例如，暴露的金属线或者多晶硅等导体，就像一根根天线，会收集电荷(如等离子刻蚀产生的带电粒子)导致电位升高)，静电容易在长导线中聚集，导致在显示区域产生静电释放(ESD，Electro-Static Discharge)风险。在采用屏下摄像头技术的显示基板的像素电路的生产工艺制程中存在严重的ESD问题，会导致良率损失较大。
本公开实施例提供一种显示基板，包括：衬底、设置在衬底上的电路结构层、以及位于电路结构层远离衬底一侧的发光结构层。衬底包括显示区域以及位于显示区域外围的周边区域。显示区域可以包括：第一显示区和第二显示区。第一显示区至少部分围绕第二显示区。电路结构层可以包括：位于第一显示区的多个像素电路、沿第一方向延伸的至少一条第一走线、沿第二方向延伸的至少一条第二走线以及位于周边区域的至少一条第三走线。发光结构层可以包括：位于第一显示区的多个第一发光元件以及位于第二显示区的多个第二发光元件。多个像素电路可以包括多个第一像素电路和多个第二 像素电路。多个第一像素电路中的至少一个第一像素电路与第一显示区的多个第一发光元件中的至少一个第一发光元件电连接，多个第二像素电路中的至少一个第二像素电路与第二显示区的多个第二发光元件中的至少一个第二发光元件电连接。第一显示区的至少一条第一走线和至少一条第二走线电连接。至少一条第三走线与以下至少一项电连接：至少一条第一走线、至少一条第二走线。其中，第一方向与第二方向交叉。例如，第一方向与第二方向可以相互垂直。
在一些示例中，至少一条第三走线可以与至少一条第二走线电连接。例如，至少一条第三走线可以在周边区域沿第一方向延伸。或者，至少一条第三走线可以与至少一条第一走线电连接。例如，至少一条第三走线可以在周边区域内沿第二方向延伸。或者，至少一条第三走线可以同时与至少一条第一走线和至少一条第二走线电连接。然而，本实施例对此并不限定。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本实施例提供的显示基板，通过在第一显示区设置相互电连接的第一走线和第二走线，并通过第二走线与周边区域的第三走线电连接，可以通过第一走线和第二走线建立显示区域到周边区域的静电导出途径，可以有利于将显示基板的工艺制程中产生的静电从显示区域导出，从而有效降低显示区域的ESD风险。
在一些示例中，至少一条第三走线与至少一条第二走线可以同层设置。例如，至少一条第三走线与至少一条第二走线可以为一体结构。又如，第三走线可以为双层走线，其中一个子走线可以与第二走线同层设置。在另一些示例中，至少一条第三走线与至少一条第一走线可以同层设置。在另一些示例中，至少一条第三走线、至少一条第一走线和至少一条第二走线可以同层设置。
在一些示例中，第一走线与第二走线可以同层设置。然而，本实施例对 此并不限定。在另一些示例中，第一走线与第二走线可以位于不同的导电层，通过绝缘层开设的过孔电连接。
在一些示例性实施方式中，至少一条第一走线与至少一条第二走线可以为一体结构。例如，第一显示区的至少一条第一走线和至少一条第二走线可以电连接形成网状连接结构。
在一些示例性实施方式中，第一显示区的多个像素电路还可以包括：多个无效像素电路，至少一条第二走线在衬底的正投影与至少一个无效像素电路在衬底的正投影存在交叠。在本示例中，第二走线可以排布的无效像素电路所在区域，可以避免占用有效像素电路的空间，并可以支持第二走线在第二方向上的延伸。
在一些示例性实施方式中，至少一条第一走线在衬底的正投影可以位于相邻两行像素电路之间。本示例的第一走线排布方式可以避免占用有效像素电路的空间，并可以支持第一走线在第一方向上的延伸。
在一些示例性实施方式中，周边区域可以包括：沿第二方向位于显示区域相对两侧的第一边框区和第二边框区。至少一条第三走线可以包括：位于第一边框区的第一电源线以及位于第二边框区的第一电源连接线。至少一条第二走线可以与第一电源连接线和第一电源线中的至少之一电连接。在一些示例中，至少一条第二走线可以与第一电源连接线直接电连接，例如两者可以为一体结构。第一电源线与第一电源连接线可以沿第一方向延伸。第二走线在第一边框区与第一电源线电连接，在第二边框区与第一电源连接线电连接，可以给静电导出提供多个途径，有利于静电从显示区域导出。
在另一些示例中，第三走线可以为周边区域的其它长导线。例如，第三走线可以包括第二电源线。在另一些示例中，周边区域可以包括：沿第一方向位于显示区域相对两侧的第三边框区和第四边框区，第三走线可以位于第三边框区和第四边框区，至少一条第一走线可以延伸至第三边框区和第四边框区与第三走线电连接。在另一些示例中，第三走线可以位于第一边框区、第二边框区、第三边框区和第四边框区，在第一边框区和第二边框区，第三走线与至少一条第二走线电连接，在第三边框区和第四边框区，第三走线可以与至少一条第一走线电连接。本示例通过第一走线、第二走线和第三走线 的电连接，可以在工艺制备过程中，给显示区域的静电提供导出途径，从而提高产品制备良率。
在一些示例性实施方式中，第一电源线可以包括叠设且相互电连接的第一子电源线和第二子电源线。至少一条第二走线、第一电源连接线和第一子电源线可以为一体结构。在本示例中，第一电源线可以为双层走线结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，在垂直于显示基板的方向上，第一显示区的电路结构层可以包括：设置在衬底上的半导体层、第一导电层、第二导电层和第三导电层。半导体层至少可以包括：至少一个像素电路的晶体管的有源层。第一导电层至少可以包括：至少一个像素电路的晶体管的栅极以及存储电容的第一电容极板。第二导电层至少可以包括：至少一个像素电路的存储电容的第二电容极板。第三导电层至少可以包括：第一走线和第二走线。在本示例中，通过将第一走线和第二走线设置在第三导电层，可以将显示基板的工艺制程中产生的、聚集在第一导电层和第二导电层的静电从显示区域导出，避免击伤第一显示区的晶体管。
在一些示例性实施方式中，第一显示区的电路结构层还可以包括：位于第三导电层远离衬底一侧的第四导电层。第四导电层至少可以包括：数据线、虚设数据线和第一电源传输线。数据线可以与多个第一像素电路或多个第二像素电路电连接。第一电源传输线与多个像素电路电连接。虚设数据线与第二走线电连接。虚设数据线和第一电源传输线均与第三走线电连接。在本示例中，第二走线还可以通过虚设数据线与第一电源线电连接，可以在第四导电层提供静电导出途径。
在一些示例性实施方式中，第二导电层还可以包括：第一初始信号线和第二初始信号线。第一初始信号线和第二初始信号线均沿第一方向延伸。周边区域还可以包括：第一初始周边走线和第二初始周边走线。第一初始周边走线和第二初始周边走线沿第二方向延伸。第一初始信号线可以通过第一初始转接线与第一初始周边走线电连接；第二初始信号线可以通过第二初始转接线与第二初始周边走线电连接。第一初始转接线与第二初始转接线可以位于第三导电层。在本示例中，利用第三导电层的第一初始转接线和第二初始 转接线进行信号转接，可以有利于将聚集在第二导电层的静电导出显示区域。
在一些示例性实施方式中，第一导电层还可以包括：沿第一方向延伸的扫描线和发光控制线。周边区域还包括：扫描输出线和发光控制输出线。扫描线可以通过扫描转接线与扫描输出线电连接。发光控制线可以通过发光控制转接线与发光控制输出线电连接。扫描转接线和发光控制转接线可以位于第三导电层。在本示例中，利用第三导电层的扫描转接线和发光控制转接线进行信号转接，可以有利于将聚集在第一导电层的静电导出显示区域。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA外围的周边区域BB。显示基板的显示区域AA可以包括：第一显示区A1和第二显示区A2。第一显示区A1至少部分围绕第二显示区A2。在本示例中，第一显示区A1可以围绕在第二显示区A2的四周。
在一些示例中，如图1所示，第二显示区A2可以为透光显示区，还可以称为屏下摄像头(FDC，Full Display With Camera)区域；第一显示区A1可以为正常显示区。例如，感光传感器(如，摄像头等硬件)在显示基板上的正投影可以位于显示基板的第二显示区A2内。在一些示例中，如图1所示，第二显示区A2可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第二显示区A2的尺寸。然而，本实施例对此并不限定。在另一些示例中，第二显示区A2可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第二显示区A2的内切圆的尺寸。
在一些示例中，如图1所示，第二显示区A2可以位于显示区域AA的顶部正中间位置。第一显示区A1可以围绕在第二显示区A2的四周。然而，本实施例对此并不限定。例如，第二显示区A2可以位于显示区域AA的左上角或者右上角等其他位置。例如，第一显示区A1可以围绕在第二显示区A2的至少一侧。
在一些示例中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。第二显示区A2可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第二显示区A2可以为矩形、半圆形、五边形等其他形状。
在一些示例中，显示区域AA可以设置有多个子像素。至少一个子像素可以包括像素电路和发光元件。像素电路配置为驱动所连接的发光元件。例如，像素电路被配置为提供驱动电流以驱动发光元件发光。像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(即3个晶体管和1个电容)结构、7T1C(即7个晶体管和1个电容)结构、5T1C(即5个晶体管和1个电容)结构、8T1C(即8个晶体管和1个电容)结构或者8T2C(即8个晶体管和2个电容)结构等。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例中，显示区域的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列。一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。本示例性实施例的像素电路以7T1C结构为例进行说明。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，本示例的像素电路可以包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管可以分别为数据写入晶体管T4、阈值补偿晶体管T2、 第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL可以包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图2所示，显示基板可以包括：扫描线GL、数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1可以配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2可以配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GL可以配置为向像素电路提供扫描信号SCAN，数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM，第一复位控制线RST1可以配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2可以配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号 SCAN(n-1)相同。第二复位控制线RST2可以与第n行像素电路的扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)相同。在一些示例中，第n行像素电路所电连接的第二复位控制线RST2与第n+1行像素电路所电连接的第一复位控制线RST1可以为一体结构。其中，n为大于0的整数。如此，可以减少显示基板的信号线，实现显示基板的窄边框设计。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些示例性实施方式中，如图2所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GL电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线GL电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线PL1电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的 第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二初始信号线INIT2电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电容极板与驱动晶体管T3的栅极电连接，存储电容Cst的第二电容极板与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面对像素电路的工作过程进行说明。以图2所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，在一帧显示时间段，像素驱动电路的工作过程可以包括：第一阶段、第二阶段和第三阶段。
第一阶段，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GL提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段，称为数据写入阶段或者阈值补偿阶段。扫描线GL提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第一电容极板为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值 补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电容极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GL提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2。
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电 压。
图3为本公开至少一实施例的显示基板的局部示意图。在一些示例中，如图3所示，显示基板的第一显示区A1可以包括：过渡区域A1a和非过渡区域A1b。过渡区域A1a可以位于第二显示区A2外的至少一侧(例如，一侧；又如，四周，即包括上下两侧和左右两侧)。
在一些示例中，第二显示区A2可以包括阵列排布的多个第二发光元件14。过渡区域A1a可以包括阵列排布的多个第一像素电路11和多个第二像素电路12，还可以包括：多个第一发光元件。过渡区域A1a内的至少一个第一像素电路11可以与至少一个第一发光元件电连接，被配置为驱动第一发光元件发光。第一发光元件在衬底的正投影与所电连接的第一像素电路11在衬底的正投影可以至少部分交叠。至少一个第二像素电路12可以通过导电线L(例如，透明导电线)与第二显示区A2内设置的至少一个第二发光元件14电连接，被配置为驱动第二发光元件14发光。例如，导电线L的一端可以与第二像素电路12电连接，另一端可以与第二发光元件14电连接，导电线L可以从过渡区域A1a延伸至第二显示区A2。第二像素电路12在衬底的正投影与所电连接的第二发光元件14在衬底的正投影可以没有交叠。在本示例中，第二显示区A2中的每个第二发光元件14均可以通过至少一条导电线L与过渡区域A1a内的第二像素电路12电连接。通过将驱动第二发光元件14的第二像素电路12设置在过渡区域A1a，可以减少像素电路对光线的遮挡，从而增加第二显示区A2的光透过率。
在一些示例中，导电线L可以采用透明导电材料，例如，可以采用导电氧化物材料，比如，氧化铟锡(ITO)。然而，本实施例对此并不限定。
在一些示例中，如图3所示，非过渡区域A1b可以包括阵列排布的多个第一像素电路11和多个无效像素电路15，还可以包括多个第一发光元件。非过渡区域A1b内的至少一个第一像素电路11可以与至少一个第一发光元件电连接，第一发光元件在衬底的正投影与所电连接的第一像素电路11在衬底的正投影可以至少部分交叠。
在一些示例中，如图3所示，过渡区域A1a和非过渡区域A1b还可以包括：多个无效像素电路15。通过设置无效像素电路可以利于提高多个膜层的 部件在刻蚀工艺中的均一性。例如，无效像素电路与其所在行或所在列的第一像素电路和第二像素电路的结构可以大致相同，只是其不与任何发光元件电连接。
在一些示例中，由于第一显示区A1不仅设置有与第一发光元件电连接的第一像素电路，还设置有与第二发光元件电连接的第二像素电路，因此，第一显示区A1的像素电路的数目可以大于第一发光元件的数目。在一些示例中，如图3所示，可以通过减小第一像素电路11在第一方向D1上的尺寸来获得设置新增像素电路(包括第二像素电路和无效像素电路)的区域。例如，像素电路在第一方向D1上的尺寸可以小于第一发光元件在第一方向D1上的尺寸。在本示例中，如图3所示，可以将原来的每a列像素电路通过沿第一方向D1压缩，从而新增一列像素电路的排布空间，且压缩前的a列像素电路和压缩后的a+1列像素电路所占用的空间可以是相同。其中，a可以为大于1的整数。在本示例中，a可以等于4。然而，本实施例对此并不限定。例如，a可以等于2或3。
在另一些示例中，可以将原来的b行像素电路通过沿第二方向D2压缩，从而新增一行像素电路的排布空间，且压缩前的b行像素电路和压缩后的b+1行像素电路所占用的空间是相同。其中，b可以为大于1的整数。或者，可以通过减小第一像素电路在第一方向D1和第二方向D2上的尺寸来获得设置新增像素电路的区域。
在本公开实施例中，一行发光元件可以指与该行发光元件相连的像素电路均与同一条栅线(例如，扫描线)相连。一行像素电路可以指该行像素电路均与同一条栅线相连。然而，本实施例对此并不限定。
图4为本公开至少一实施例的显示基板的走线排布示意图。在一些示例中，第一显示区A1可以设置有多条第一走线231和多条第二走线232。第一走线231可以在第一显示区A1内沿第一方向D1延伸，多条第一走线231可以沿第二方向D2依次排布。多条第二走线232可以沿第二方向D2延伸，且多条第二走线232可以沿第一方向D1依次排布。至少一条第一走线231与至少一条第二走线232电连接。例如，在第二方向D2上的相邻两条第一走线231可以电连接至少一条相同的第二走线232。多条第一走线231和多 条第二走线232可以在第一显示区A1电连接形成网状连接结构。
在一些示例中，如图4所示，过渡区域A1a内可以不设置第二走线232，以避免第二走线232的排布影响第二像素电路电连接的数据线的排布。
在一些示例中，第二显示区A2会把至少一条数据线隔断为第一子数据线、第二子数据线和第三子数据线，第一子数据线可以与第二显示区A2下侧的第一显示区A1内的一列第一像素电路电连接，第二子数据线可以与第二显示区A2左侧或右侧的过渡区域A1a内的一列第二像素电路电连接，第三子数据线可以与第二显示区A2上侧的第一显示区A1内的一列第一像素电路电连接。第一子数据线与第二子数据线可以通过数据连接线电连接，第二子数据线和第三子数据线可以通过数据连接线电连接。数据连接线可以沿第一方向D1延伸。例如，数据连接线可以排布第一显示区A1内，且位于第一显示区A1内靠近第二显示区A2的区域内。第一走线231可以不延伸至数据连接线的所在区域，例如，数据连接线的所在区域可以不设置第一走线231，从而避免走线排布集中影响光透过率和显示效果。在另一些示例中，显示基板还可以包括指纹识别区域，在指纹识别区域可以不设置第一走线，以避免影响光透过率。然而，本实施例对此并不限定。
在一些示例中，如图4所示，周边区域BB可以包括：第一边框区B1、第二边框区B2、第三边框区B3和第四边框区B4。第一边框区B1与第三边框区B3和第四边框区B4连通，第二边框区B2与第三边框区B3和第四边框区B4连通。第一边框区B1与第二边框区B2可以在第二方向D2上位于显示区域AA的相对两侧，第三边框区B3和第四边框区B4可以在第一方向D1上位于显示区域AA的相对两侧。例如，第一边框区B1可以为显示基板的下边框，第二边框区B2可以为显示基板的上边框，第三边框区B3可以为显示基板的左边框，第四边框区B4可以为显示基板的右边框。第三边框区B3和第四边框区B4内的结构大致相同，下述示例中以第三边框区B3内的结构为例进行说明。
在一些示例中，如图4所示，第一边框区B1可以包括沿第一方向D1延伸的第一电源线26。在一些示例中，第一边框区B1可以包括：沿着远离显示区域AA的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。 第一电源线26可以设置在扇出区。扇出区连接到显示区域，可以包括多条数据引出线，多条数据引出线被配置为以扇出走线方式连接显示区域的数据线。弯折区可以连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使驱动芯片区和绑定引脚区弯折到显示区域AA的背面。驱动芯片区可以设置集成电路(IC，Integrated Circuit)，集成电路可以被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，绑定焊盘可以被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接。第一电源线26可以与绑定引脚区的绑定焊盘电连接，以接收第一电压信号。在一些示例中，第一电源线26可以为双层走线，例如可以包括相互电连接的第一子电源线和第二子电源线，第一子电源线和第二子电源线可以设置在不同导电层。第一子电源线和第二子电源线在衬底的正投影可以存在交叠。然而，本实施例对此并不限定。例如，第一电源线可以为单层走线。
在一些示例中，如图4所示，第二边框区B2可以包括沿第一方向D1延伸的第一电源连接线233。第一显示区A1内沿第二方向D2延伸的第二走线232可以与第二边框区B2的第一电源连接线233电连接，还可以与第一边框区B1的第一电源线26电连接。例如，第二走线232的一端可以延伸至第二边框区B2，与第一电源连接线233电连接，另一端可以延伸至第一边框区B1，与第一电源线26电连接。本示例中，通过第二走线232可以提供从显示区域到周边区域的静电导出路径。另外，通过第二走线232在第二方向D2可以连通第一电源线26与第一电源连接线233，可以无需在第三边框区B3和第四边框区B4设置电源连接线。
在本示例中，第三走线可以包括：第一电源线26和第一电源连接线233。然而，本实施例对此并不限定。在另一些示例中，第三走线可以包括位于周边区域的其它长导线。通过第一走线、第二走线和第三走线的电连接，给显示区域的静电提供了导出途径。
在一些示例中，如图4所示，第三边框区B3可以包括沿着远离显示区域AA的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区可以连接到显示区域AA，可以至少包括栅极驱动电路、第一初始周边走线27和第二初始周边走线28。栅极驱动电路可以位于第二初始周边走线28远离 显示区域AA的一侧，第一初始周边走线27可以位于第二初始周边走线28靠近显示区域AA的一侧。第一初始周边走线27和第二初始周边走线28可以从第三边框区B3延伸至第一边框区B1，例如可以与绑定引脚区的绑定焊盘电连接，以分别接收第一初始信号和第二初始信号。栅极驱动电路可以与显示区域中的像素电路所连接的扫描线和发光控制线电连接。电源线区可以连接到电路区，可以至少包括边框电源引线，边框电源引线可以沿着平行于显示区域边缘的方向延伸，与显示区域AA中的发光元件的阴极电连接。裂缝坝区可以连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区可以连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在一些示例中，第一初始周边走线27和第二初始周边走线28可以均为双层走线，第一初始周边走线27可以包括叠设且相互电连接的第一初始子走线271和第三初始子走线272，第二初始周边走线28可以包括叠设且相互电连接的第二初始子走线281和第四初始子走线282。然而，本实施例对此并不限定。例如，第一初始周边走线27和第二初始周边走线28可以为单层走线。
图5为图4中区域S1的电路结构层的局部放大示意图。图6为图5中沿Q-Q’方向的局部剖面示意图。图7为图4中区域S2的电路结构层的局部放大示意图。图8为图4中区域S3的电路结构层的局部放大示意图。
在一些示例中，第一显示区A1在第一方向D1上可以包括间隔排布的第一电路区A11和第二电路区A12。第一电路区A11可以设置多列第一像素电路11(例如，四列第一像素电路)，第二电路区A12可以设置一列无效像素电路15(例如，包括多个无效像素电路)或者可以设置包括无效像素电路和第二像素电路的一列像素电路。在图5、图7和图8中以第二电路区A12包括的无效像素电路为例进行示意图。在第二电路区A12包括第二像素电路时，可以不设置第二走线，或者可以不设置第一走线和第二走线。下述示例中省略了周边区域的栅极驱动电路的膜层结构和制备过程。
在一些示例中，如图5和图6所示，在垂直于显示基板的方向上，第一 显示区A1的显示基板可以包括：衬底100、以及依次设置在衬底100上的半导体层20、第一导电层21、第二导电层22、第三导电层23以及第四导电层24。半导体层20和第一导电层21之间可以设置第一绝缘层101，第一导电层21和第二导电层22之间可以设置第二绝缘层102，第二导电层22和第三导电层23之间可以设置第三绝缘层103，第三导电层23和第四导电层24之间可以设置第四绝缘层104和第五绝缘层105。在一些示例中，第一绝缘层101至第四绝缘层104可以均为无机绝缘层，第五绝缘层105可以为有机绝缘层。第一导电层21还可以称为第一栅金属层，第二导电层22还可以称为第二栅金属层，第三导电层23还可以称为第一源漏金属层，第四导电层24还可以称为第二源漏金属层。然而，本实施例对此并不限定。
图9A为图5中形成半导体层后的电路结构层的示意图。图9B为图7中形成半导体层后的电路结构层的示意图。图9C为图8中形成半导体层后的电路结构层的示意图。
在一些示例中，如图9A至图9C所示，第一显示区A1的半导体层20可以至少包括：多个像素电路的多个晶体管的有源层(例如，包括：无效像素电路的第一复位晶体管的有源层510、阈值补偿晶体管的有源层520、驱动晶体管的有源层530、数据写入晶体管的有源层540、第一发光控制晶体管的有源层550、第二发光控制晶体管的有源层560、以及第二复位晶体管的有源层570；第一像素电路的第一复位晶体管的有源层310、阈值补偿晶体管的有源层320、驱动晶体管的有源层330、数据写入晶体管的有源层340、第一发光控制晶体管的有源层350、第二发光控制晶体管的有源层360以及第二复位晶体管的有源层370)。在本示例中，一个像素电路的七个晶体管的有源层可以为一体结构。每个晶体管的有源层可以包括：第一区、第二区以及位于第一区和第二区之间的沟道区。在一些示例中，有源层的第一区和第二区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
在一些示例中，如图9A所示，第二边框区B2的半导体层20可以包括多个无效半导体块201。第二边框区B2的多个无效半导体块201可以靠近第一显示区A1的边缘，且可以沿第一方向D1依次排布。如图9C所示，第一 边框区B1的半导体层20可以包括多个无效半导体块201。第一边框区B1的多个无效半导体块201可以靠近第一显示区A1的边缘，且可以沿第一方向D1和第二方向D2规则排布。在一些示例中，在第三边框区B3和第四边框区B4内，可以设置多个无效半导体块，无效半导体块可以靠近第一显示区A1的边缘。在本示例中，通过在周边区域设置多个无效半导体块，有利于提高制备过程中的膜层均一性。
在一些示例中，半导体层20的材料例如可以包括多晶硅。沟道区可以不掺杂杂质，并具有半导体特性。位于沟道区两侧的第一区和第二区可以掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。然而，本实施例对此并不限定。
图10A为图5中形成第一导电层后的电路结构层的示意图。图10B为图7中形成第一导电层后的电路结构层的示意图。图10C为图8中形成第一导电层后的电路结构层的示意图。
在一些示例中，如图10A至图10C所示，第一显示区A1的第一导电层21可以至少包括：多个像素电路的多个晶体管的栅极和存储电容的第一电容极板(例如，无效像素电路的存储电容的第一电容极板581、第一像素电路的存储电容的第一电容极板381)、扫描线(例如，扫描线GL(1)、GL(n)、GL(N))、发光控制线(例如，发光控制线EML(1)、EML(n-1)、EML(n)、EML(N-1)和EML(N))、第一复位控制线(例如，第一复位控制线RST1(1)、RST1(n)和RST1(N))和第二复位控制线(例如，第二复位控制线RST2(1)、RST2(n)和RST2(N))。其中，N大于或等于n，n和N均为整数。扫描线、发光控制线、第一复位控制线和第二复位控制线可以均为主体部分沿第一方向D1延伸的线形状。一行像素电路所电连接的扫描线可以位于该行像素电路所电连接的第一复位控制线和发光控制线之间。在本示例中，一行像素电路电连接的第二复位控制线即为下一行像素电路电连接的第一复位控制线。
在一些示例中，如图10A所示，以第一行像素电路为例，第一复位控制线RST1(1)与本行的第一像素电路的第一复位晶体管的有源层310的交叠区域可以作为第一像素电路的第一复位晶体管的栅极，与本行的无效像素电路的第一复位晶体管的有源层510的交叠区域可以作为无效像素电路的第一复 位晶体管的栅极。扫描线GL(1)与本行的第一像素电路的阈值补偿晶体管的有源层320的交叠区域可以作为第一像素电路的阈值补偿晶体管的栅极，与本行的第一像素电路的数据写入晶体管的有源层340的交叠区域可以作为第一像素电路的数据写入晶体管的栅极，与本行的无效像素电路的阈值补偿晶体管的有源层520的交叠区域可以作为无效像素电路的阈值补偿晶体管的栅极，与本行的无效像素电路的数据写入晶体管的有源层540的交叠区域可以作为无效像素电路的数据写入晶体管的栅极。发光控制线EML(1)与本行的第一像素电路的第一发光控制晶体管的有源层350的交叠区域可以作为第一像素电路的第一发光控制晶体管的栅极，与本行的第一像素电路的第二发光控制晶体管的有源层360的交叠区域可以作为第一像素电路的第二发光控制晶体管的栅极，与本行的无效像素电路的第一发光控制晶体管的有源层550的交叠区域可以作为无效像素电路的第一发光控制晶体管的栅极，与本行的无效像素电路的第二发光控制晶体管的有源层560的交叠区域可以作为无效像素电路的第二发光控制晶体管的栅极。第二复位控制线RST2(1)与本行的第一像素电路的第二复位晶体管的有源层370的交叠区域可以作为第一像素电路的第二复位晶体管的栅极，与本行的无效像素电路的第二复位晶体管的有源层570的交叠区域可以作为无效像素电路的第二复位晶体管的栅极，与下一行的第一像素电路的第一复位晶体管的有源层的交叠区域可以作为下一行第一像素电路的第一复位晶体管的栅极，与下一行的无效像素电路的第一复位晶体管的有源层的交叠区域可以作为下一行无效像素电路的第一复位晶体管的栅极。
在一些示例中，如图10A所示，第一像素电路的存储电容的第一电容极板381的形状可以为矩形，矩形的角部可以设置倒角。第一电容极板381在衬底的正投影与第一像素电路的驱动晶体管的有源层330在衬底基板的正投影存在交叠。第一像素电路的第一电容极板381可以同时作为存储电容的一个极板和驱动晶体管的栅极。无效像素电路的存储电容的第一电容极板581的形状可以为矩形，矩形的角部可以设置倒角。第一电容极板581在衬底的正投影与无效像素电路的驱动晶体管的有源层530在衬底基板的正投影存在交叠。无效像素电路的第一电容极板581可以同时作为存储电容的一个极板和驱动晶体管的栅极。
在一些示例中，如图10B所示，第一复位控制线RST1(n)的一端可以延伸至第三边框区B3。第二复位控制线RST2(n)的一端可以延伸至第三边框区B3。发光控制线EML(n)的一端可以延伸至第三边框区B3。扫描线GL(n)的一端可以延伸至第三边框区B3。
在一些示例中，如图10C所示，第一边框区B1的第一导电层21可以包括：多条第一数据扇出线211。第一数据扇出线211可以被配置为以扇出走线方式与第一显示区A1的数据线电连接，还可以与第一边框区B1的驱动芯片区设置的集成电路电连接。第一数据扇出线211可以被配置为向第一显示区A1的数据线传输数据信号。
图11A为图5中形成第二导电层后的电路结构层的示意图。图11B为图7中形成第二导电层后的电路结构层的示意图。图11C为图8中形成第二导电层后的电路结构层的示意图。
在一些示例中，如图11A至图11C所示，第一显示区A1的第二导电层22可以包括：多个像素电路的存储电容的第二电容极板(例如，第一像素电路的第二电容极板382、无效像素电路的第二电容极板582)、多条第一初始信号线INIT1和多条第二初始信号线INIT2。第一初始信号线INIT1和第二初始信号线INIT2的形状可以为主体部分沿第一方向D1延伸的线形状。第一像素电路的第二电容极板382在衬底的正投影与第一电容极板381在衬底的正投影存在交叠。无效像素电路的第二电容极板582在衬底的正投影与第一电容极板581在衬底的正投影存在交叠。在一些示例中，一行像素电路中，相邻像素电路的存储电容的第二电容极板可以相互电连接，例如，第一像素电路的存储电容的第二电容极板382与无效像素电路的存储电容的第二电容极板582可以形成相互连接的一体结构。一体结构的第二电容极板可以复用为电源信号连接线，保证一行像素电路中的多个第二电容极板具有相同的电位，有利于提高显示基板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在一些示例中，如图11A所示，第一像素电路的第二电容极板382可以具有暴露出第一电容极板381的开口。无效像素电路的第二电容极板582可以具有暴露出第一电容极板581的开口。
在一些示例中，如图11C所示，第一边框区B1的第二导电层22可以包括：多条第二数据扇出线221。第二数据扇出线221可以被配置为以扇出走线方式与第一显示区A1的数据线电连接，还可以与第一边框区B1的驱动芯片区设置的集成电路电连接。第二数据扇出线221可以被配置为向第一显示区A1的数据线传输数据信号。在本示例中，第一数据扇出线211和第二数据扇出线221可以间隔排布。
在一些示例中，如图11B所示，第一初始信号线INIT1的一端和第二初始信号线INIT2的一端均可以延伸至第三边框区B3。
在一些示例中，如图11B所示，第三边框区B3的第二导电层22可以包括：第三初始转接线222、第四初始转接线223、扫描输出线224以及发光控制输出线225。第三初始转接线222被配置为后续连接第一初始信号线INIT1和第一初始周边走线。第四初始转接线223被配置为后续连接第二初始信号线INIT2和第二初始周边走线。扫描输出线224被配置为连接扫描线GL(n)与栅极驱动电路的扫描信号输出端。发光控制输出线225被配置为连接发光控制线EML(n)与栅极驱动电路的发光控制信号输出端。在另一些示例中，第三初始转接线222和第四初始转接线223可以位于第一导电层。然而，本实施例对此并不限定。
图12A为图5中形成第三绝缘层后的电路结构层的示意图。图12B为图7中形成第三绝缘层后的电路结构层的示意图。图12C为图8中形成第三绝缘层后的电路结构层的示意图。
在一些示例中，如图12A至图12C所示，第一显示区A1的第三绝缘层103可以开设有多个过孔，例如可以包括：第一过孔V1至第二十过孔V20。第一过孔V1至第六过孔V6以及第十一过孔V11至第十六过孔V16内的第三绝缘层103、第二绝缘层102和第一绝缘层101被去掉，暴露出半导体层20的表面。第七过孔V7和第十七过孔V17内的第三绝缘层103和第二绝缘层102被去掉，暴露出第一导电层21的表面。第八过孔V8至第十过孔V10以及第十八过孔V18至第二十过孔V20内的第三绝缘层103被去掉，暴露出第二导电层22的表面。
在一些示例中，如图12A所示，第三绝缘层103开设的多个过孔中的至 少一个过孔在衬底的正投影与第一导电层或第二导电层的至少一条走线在衬底的正投影在第二方向D2上的距离可以大于或等于2微米。例如，第四过孔V4在第二方向D2的上边缘与发光控制线EML(1)在第二方向D2的下边缘之间的距离R1可以大于或等于2微米。在本示例中，通过增大过孔与第一导电层或第二导电层的走线之间的距离来改善ESD风险。
在一些示例中，如图12A所示，第二边框区B2的第三绝缘层103可以开设有多个过孔，例如可以包括多个第二十一过孔V21。第二十一过孔V21内的第三绝缘层103、第二绝缘层102和第一绝缘层101被去掉，暴露出半导体层20的表面。一个第二十一过孔V21可以暴露出一个无效半导体块201的表面。通过设置暴露出无效半导体块的过孔，可以释放制备过程中产生的气体，避免膜层凸起或破损等情况。
在一些示例中，如图12C所示，第一边框区B1的第三绝缘层103可以开设有多个过孔，例如可以包括多个第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。第二十一过孔V21内的第三绝缘层103、第二绝缘层102和第一绝缘层101被去掉，暴露出半导体层20的表面。第二十二过孔V22内的第三绝缘层103被去掉，暴露出第二导电层22的第二数据扇出线221的表面。第二十三过孔V23内的第三绝缘层103和第二绝缘层102被去掉，暴露出第一导电层21的第一数据扇出线211的表面。
在一些示例中，如图12B所示，第三边框区B3的第三绝缘层103可以开设有多个过孔，例如可以包括第二十四过孔V24至第三十四过孔V34。第二十四过孔V24至第三十一过孔V31内的第三绝缘层103被去掉，暴露出第二导电层22的表面。第三十二过孔V32和第三十三过孔V33内的第三绝缘层103和第二绝缘层102被去掉，暴露出第一导电层21的表面。
图13A为图5中形成第三导电层后的电路结构层的示意图。图13B为图7中形成第三导电层后的电路结构层的示意图。图13C为图8中形成第三导电层后的电路结构层的示意图。图14A为图5中的第三导电层的示意图。图14B为图7中的第三导电层的示意图。图14C为图8中的第三导电层的示意图。
在一些示例中，如图13A至图13C、以及图14A至图14C所示，第一 显示区A1的第三导电层23可以包括：多个连接电极(例如，包括：第一连接电极332、第二连接电极322、第三连接电极342、第四连接电极352、第五连接电极362、第六连接电极372、第七连接电极532、第八连接电极522、第九连接电极542、第十连接电极552、第十一连接电极562和第十二连接电极572)、多条第一走线231以及多条第二走线232。
在一些示例中，如图12A、图13A和图14A所示，第一连接电极332可以通过第一过孔V1与第一像素电路的第一复位晶体管31的有源层310的第一区电连接，还可以通过第八过孔V8与第一初始信号线INIT1电连接。第二连接电极322可以通过第二过孔V2与第一像素电路的阈值写入晶体管32的有源层320的第一区电连接，还可以通过第七过孔V7与驱动晶体管33的栅极电连接。第三连接电极342可以通过第三过孔V3与第一像素电路的数据写入晶体管34的有源层340的第一区电连接。第四连接电极352可以通过第四过孔V4与第一像素电路的第一发光控制晶体管35的有源层350的第一区电连接，还可以通过第七过孔V7与存储电容38的第二电容极板382电连接。第五连接电极362可以通过第五过孔V5与第二发光控制晶体管36的有源层360的第二区电连接。第六连接电极372可以通过第六过孔V6与第一像素电路的第二复位晶体管37的有源层370的第一区电连接，还可以通过第十过孔V10与第二初始信号线INIT2电连接。
在一些示例中，如图12A、图13A和图14A所示，第七连接电极532可以通过第十一过孔V11与无效像素电路的第一复位晶体管51的有源层510的第一区电连接，还可以通过第十八过孔V18与第一初始信号线INIT1电连接。第八连接电极522可以通过第十二过孔V12与无效像素电路的阈值写入晶体管52的有源层520的第一区电连接，还可以通过第十七过孔V7与驱动晶体管53的栅极电连接。第九连接电极542可以通过第十三过孔V13与无效像素电路的数据写入晶体管54的有源层540的第一区电连接。第十连接电极552可以通过第十四过孔V14与无效像素电路的第一发光控制晶体管55的有源层550的第一区电连接，还可以通过第十七过孔V17与存储电容58的第二电容极板582电连接。第十一连接电极562可以通过第十五过孔V15与第二发光控制晶体管56的有源层560的第二区电连接。第十二连接电极 572可以通过第十六过孔V16与无效像素电路的第二复位晶体管57的有源层570的第一区电连接，还可以通过第二十过孔V20与第二初始信号线INIT2电连接。
在一些示例中，如图13A和图14A所示，第二遮挡电极可以包括第一连接电极332和第七连接电极532。第一遮挡电极可以包括：第四连接电极352和第十连接电极552。第一连接电极332和第七连接电极532在衬底的正投影可以大致为矩形环形状。第一连接电极332在衬底的正投影可以覆盖第一像素电路的第一复位晶体管31的有源层310的沟道区。第七连接电极532在衬底的正投影可以至少部分覆盖无效像素电路的第一复位晶体管51的有源层510的沟道区。第四连接电极352和第十连接电极552在衬底的正投影可以大致为d字型。第四连接电极352在衬底的正投影可以至少部分覆盖第一像素电路的第一发光控制晶体管35的有源层350的沟道区。第十连接电极552在衬底的正投影可以至少部分覆盖无效像素电路的第一发光控制晶体管55的有源层550的沟道区。在本示例中，通过第三导电层的第一遮挡电极和第二遮挡电极对第一复位晶体管和第一发光控制晶体管的有源层的沟道区进行遮挡，可以防止静电聚集击伤有源层，从而降低显示区域的ESD风险。
在一些示例中，如图13A至图13C以及图14A至图14C所示，第一显示区A1的第一走线231的形状可以为主体部分沿第一方向D1延伸的条形走线。第一走线231可以与第一电路区A11的第四连接电极352和第二电路区A12的第十连接电极552电连接，例如可以为一体结构。第一走线231还可以与第二走线232电连接。如图13B所示，第一走线231在第一方向D1上的端部可以与第二走线232电连接。第一走线231位于第一显示区A1内，与至少一条第二走线232电连接，没有延伸至周边区域。第一走线231在衬底的正投影可以位于相邻两个像素电路行之间，例如可以位于发光控制线和第二初始信号线在衬底的正投影之间。
在一些示例中，如图13A至图13C以及图14A至图14C所示，第二走线232的形状可以为主体部分沿第二方向D2延伸的线段状。第二走线232可以位于第二电路区A12。第二走线232在衬底的正投影可以与第二电路区A12内的至少一个无效像素电路在衬底的正投影存在交叠。第二走线232可 以与第二电路区A12内的无效像素电路的第九连接电极542和第十连接电极552电连接。例如，第二走线232与第九连接电极542和第十连接电极552可以为一体结构。例如，第二走线232可以包括多个子线段。一个子线段可以连接在相邻两条第一走线231之间。例如，子线段的一端可以与一条第一走线231直接电连接，另一端可以通过第十连接电极552与另一条第一走线231电连接。第二走线232的多个子线段在第一方向D1上可以存在错位。然而，本实施例对此并不限定。在本示例中，第一走线231与第二走线232可以为一体结构。在第一显示区A1内，第一走线231和第二走线232电连接形成网状连接结构。
在一些示例中，如图13A和图14A所示，第二边框区B2的第三导电层23可以包括：第一电源连接线233。第一电源连接线233的形状可以为主体部分沿第一方向D1延伸的条状走线。第一电源连接线233在衬底的正投影可以位于多个无效半导体块201远离第一显示区A1的一侧。第一电源连接线233与至少一条第二走线232电连接。例如，第一电源连接线233与第二走线232可以为一体结构。
在一些示例中，如图13C和图14C所示，第一边框区B1的第三导电层23可以包括：多个数据引出电极(例如，第一数据引出电极234和第二数据引出电极235)、以及第一子电源线261。第一数据引出电极234可以通过并排设置的两个第二十二过孔V22与第二数据扇出线221电连接。第二数据引出电极235可以通过并排设置的两个第二十三过孔V23与第一数据扇出线211电连接。第一子电源线261的主体部分可以沿第一方向D1延伸。第一子电源线261可以具有面向第一显示区A1的多个凸起部2611。第一数据引出电极234可以位于相邻两个凸起部2611之间，第二数据引出电极235可以位于相邻两个凸起部2611之间。相邻两个凸起部2611之间可以设置一个数据引出电极。至少一条第二走线232可以与第一子电源线261电连接。例如，一条第二走线232与第一子电源线261的一个凸起部2611电连接。第二走线232与第一子电源线261可以为一体结构。
在本公开中，并排设置表示沿第一方向D1排布，竖排设置表示沿第二方向D2排布。
在一些示例中，如图13B和图14B所示，第三边框区B3的第三导电层23可以包括：第一初始转接线236、第二初始转接线237、第一扫描转接块238、第二扫描转接块239、第一发光控制转接块240、第二发光控制转接块241。
在一些示例中，如图13B和图14B所示，第一初始转接线236的一端可以通过竖排设置的两个第二十四过孔V24与第一初始信号线INIT1电连接，另一端可以通过竖排设置的两个第二十五过孔V25与第三初始转接线222电连接。第一初始子走线271可以通过竖排设置的两个第二十六过孔V26与第三初始转接线222电连接。通过第三导电层的第一初始转接线236和第二导电层的第三初始转接线222可以实现第一初始信号线INIT1和第一初始子走线271的电连接。在制备完成第三导电层后，可以通过第一初始转接线236和第三初始转接线222将聚集在第一初始信号线INIT1上的静电导出至周边区域。
在一些示例中，如图13B和图14B所示，第二初始转接线237的一端可以通过竖排设置的两个第二十七过孔V27与第二初始信号线INIT2电连接，另一端可以通过竖排设置的两个第二十八过孔V28与第四初始转接线223电连接。第二初始子走线281可以通过竖排设置的两个第二十九过孔V29与第四初始转接线223电连接。通过第三导电层的第二初始转接线237和第二导电层的第四初始转接线223可以实现第二初始信号线INIT2与第二初始子走线281的电连接。在制备完成第三导电层后，可以通过第二初始转接线237和第四初始转接线223将聚集在第二初始信号线INIT2上的静电导出至周边区域。
在一些示例中，如图13B和图14B所示，第一扫描转接块238可以通过竖排设置的两个第三十过孔V30与扫描输出线224电连接。第二扫描转接块239的一端可以通过竖排设置的两个第三十四过孔V34与扫描线GL(n)的一端电连接，另一端可以通过横排设置的两个第三十三过孔V33与第二复位控制线RST2(n)的一端电连接。第一扫描转接块238在衬底的正投影可以为圆角矩形，第二扫描转接块239在衬底的正投影可以大致为单边圆括号形状。然而，本实施例对此并不限定。
在一些示例中，如图13B和图14B所示，第一发光控制转接块240可以通过竖排设置的两个第三十一过孔V31与发光控制输出线225电连接。第二发光控制转接块241可以通过竖排设置的两个第三十二过孔V32与发光控制线EML(n)的一端电连接。第一发光控制转接块240和第二发光控制转接块241在第一方向D1上相对设置。第一发光控制转接块240和第二发光控制转接块241在衬底的正投影可以均为圆角矩形。然而，本实施例对此并不限定。
在一些示例中，如图13B和图14B所示，第一初始转接线236的靠近第一显示区A1的端部、第二扫描转接块239与扫描线的连接端、第二发光控制转接线241、第二初始转接线237的靠近第一显示区A1的端部以及第二扫描转接块239与第二复位控制线的连接端可以在第二方向D2上对齐并依次排布。第一初始转接线236的远离第一显示区A1的端部、第一扫描转接块238、第一发光控制转接块240、以及第二初始转接线237的远离第一显示区A1的端部可以在第二方向D2上对齐并依次排布。
图15A为图5中形成第五绝缘层后的电路结构层的示意图。图15B为图7中形成第五绝缘层后的电路结构层的示意图。图15C为图8中形成第五绝缘层后的电路结构层的示意图。
在一些示例中，如图15A至图15C所示，第一显示区A1的第五绝缘层105可以开设有多个过孔，例如可以包括第四十一过孔V41至第四十六过孔V46。第四十一过孔V41至第四十六过孔V46内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的表面。
在一些示例中，如图15A所示，第二边框区B2的第五绝缘层105可以开设有多个过孔，例如可以包括多个第四十七过孔V47。第四十七过孔V47内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的第一电源连接线233的表面。
在一些示例中，如图15C所示，第一边框区B1的第五绝缘层105可以开设有多个过孔，例如可以包括第四十八过孔V48和第四十九过孔V49。第四十八过孔V48内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的第一数据引出电极234的表面。第四十九过孔V49内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的第二数据引出电 极235的表面。第一边框区B1的第五绝缘层105还可以开设有暴露出第一子电源线261的表面的过孔或凹槽。
在一些示例中，如图15B所示，第三边框区B3的第五绝缘层105可以开设有多个过孔和多个凹槽，例如可以包括第五十一过孔V51至第五十八过孔V58以及第一凹槽K1和第二凹槽K2。第一凹槽K1内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的第一初始子走线271的表面。第二凹槽K2内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的第二初始子走线281的表面。第五十一过孔V51至第五十八过孔V58内的第五绝缘层105和第四绝缘层104被去掉，暴露出第三导电层23的表面。
在一些示例中，如图5、图7和图8所示，第一显示区A1的第四导电层24可以包括：多个阳极连接电极(例如，第一阳极连接电极242和无效阳极连接电极243)、多条数据线244、多条虚设数据线245以及多条第一电源传输线246和247。数据线244、虚设数据线245和第一电源传输线246和247可以均沿第二方向D2延伸。
在一些示例中，如图5所示，第一阳极连接电极242可以位于第一电路区A11，并通过第四十二过孔V42与第五连接电极362电连接。第一阳极连接电极242后续可以与第一发光元件的阳极电连接，以实现第一像素电路与第一发光元件之间的电连接。无效阳极连接电极243可以通过第四十五过孔V45与第十一连接电极562电连接。无效阳极连接电极243后续无需与发光元件的阳极电连接。
在一些示例中，如图5所示，数据线244可以位于第一电路区A11内。数据线244可以通过第四十一过孔V41与第三连接电极342电连接。数据线244可以配置为给第一像素电路的数据写入晶体管34提供数据信号。虚设数据线245可以位于第二电路区A12内。虚设数据线245可以通过第四十四过孔V44与第九连接电极542电连接。由于第九连接电极542与第二走线232为一体结构，由此虚设数据线245与第二走线232电连接。虚设数据线245在衬底的正投影与第二走线232在衬底的正投影可以存在交叠。虚设数据线245可以将第一电压信号作为数据信号提供给无效像素电路的数据写入晶体 管54。
在一些示例中，如图5所示，第一电源传输线246可以位于第一电路区A11，并通过第四十三过孔V43与第四连接电极352电连接。第一电源传输线246可以被配置为向第一像素电路提供第一电压信号。第一电源传输线247可以位于第二电路区A12，并通过第四十六过孔V46与第十连接电极552电连接。由于第十连接电极552与第二走线232为一体结构，由此第一电源传输线247与第二走线232电连接。第一电源传输线247在衬底的正投影与第二走线232在衬底的正投影可以存在交叠。
在一些示例中，如图5所示，第一电源传输线246和247可以延伸至第二边框区B2，并各自通过第四十七过孔V47与第一电源连接线233电连接。在本示例中，显示区域的静电可以通过第二走线232经由第一电源传输线246和247导出至周边区域。
在一些示例中，如图8所示，第一边框区B1的第四导电层24可以包括：第二子电源线262。第二子电源线262可以沿第一方向D1延伸，并通过第五绝缘层105开设的过孔或凹槽与第一子电源线261电连接。虚设数据线245可以延伸至第一边框区B1，并与第二子电源线262电连接。例如，虚设数据线245与第二子电源线262可以为一体结构。第一电源传输线246和247可以延伸至第一边框区B1，并与第二子电源线262电连接。例如，第一电源传输线246和247与第二子电源线262可以为一体结构。
在一些示例中，如图7所示，第三边框区B3的第四导电层24可以包括：第五初始转接线252、第六初始转接线253、扫描转接线254、发光控制转接线255、第三初始子走线272、以及第四初始子走线282。第五初始转接线252的一端可以通过第五十一过孔V51与第一初始转接线236的一端电连接，另一端可以通过第五十二过孔V52与第一初始转接线236的另一端电连接。第六初始转接线253的一端可以通过第五十三过孔V53与第二初始转接线237的一端电连接，另一端可以通过第五十四过孔V54与第二初始转接线237的另一端电连接。扫描转接线254的一端可以通过第五十五过孔V55与第二扫描转接块239电连接，另一端可以通过第五十六过孔V56与第一扫描转接块238电连接。发光控制转接线255的一端可以通过第五十七过孔V57与第二 发光控制转接块241电连接，另一端可以通过第五十八过孔V58与第一发光控制转接块240电连接。在本示例中，第五初始转接线252、扫描转接线254、发光控制转接线255和第六初始转接线253沿第二方向D2依次排布。通过在第四导电层设置第五初始转接线252和第六初始转接线253，可以确保第四导电层的膜层结构一致性，有利于工艺制备。
在一些示例中，如图7所示，第三初始子走线272和第四初始子走线282均沿第二方向D2延伸。第三初始子走线272可以通过第一凹槽K1与第一初始子走线271电连接。第四初始子走线282可以通过第二凹槽K2与第二初始子走线281电连接。在本示例中，第一初始周边走线27和第二初始周边走线28可以均为双层走线。
在一些示例中，关于第二像素电路的膜层结构可以参照第一像素电路的结构，故于此不再赘述。第四边框区的结构可以参照第三边框区的结构，故于此不再赘述。
下面对显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层。
在一些示例性实施方式中，在衬底100上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，第一显示区A1和周边区域形成半导体层20，如图9A至图9C所示。
在一些示例性实施方式中，衬底100可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如衬底基板可以为柔性基板。
(2)、形成第一导电层。
在一些示例性实施方式中，在形成前述结构的衬底100上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层20的第一绝缘层101，以及设置在第一绝缘层101上的第一导电层21，如图10A至图10C所示。
在一些示例中，形成第一导电层21后，可以利用第一导电层21作为遮挡，对半导体层20进行导体化处理，被第一导电层21遮挡区域的半导体层20可以形成晶体管的沟道区域，未被第一导电层21遮挡区域的半导体层20可以被导体化，即像素电路的七个晶体管的有源层的第一区和第二区均被导电化。
(3)、形成第二导电层。
在一些示例性实施方式中，在形成前述结构的衬底100上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成第二绝缘层102，以及设置在第二绝缘层102上的第二导电层22，如图11A至图11C所示。
(4)、形成第三绝缘层。
在一些示例性实施方式中，在形成前述图案的衬底100上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层103，如图12A至图12C所示。第三绝缘层103可以开设有多个过孔，例如多个过孔可以分别暴露出半导体层20、第一导电层21和第二导电层22的表面。
(5)、形成第三导电层。
在一些示例性实施方式中，在形成前述图案的衬底100上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第三绝缘层103上形成第三导电层23，如图13A至图13C以及图14A至图14C所示。
在本示例中，第一显示区A1的第三导电层23可以包括形成网状连接结构的第一走线231和第二走线232。第二走线232可以位于第二电路区A12。 第一走线231可以位于相邻像素电路行之间。第二走线232可以延伸至第二边框区域B2与第一电源连接线233电连接，还可以延伸至第一边框区B1与第一电源线26的第一子电源线261电连接。
在一些实现方式中，在制备第三导电层之前，第一导电层和第二导电层的长导线由于没有转接其他信号走线的途径，容易积累静电。在第一导电层和第二导电层通过第三导电层与晶体管的有源层连接时，由于有源层形成沟道处的阻值存在小电阻到大电阻的变化，静电容易在阻值变化处释放，导致击伤晶体管。本示例通过在第三导电层设置第一走线和第二走线，并与周边区域的第一电源线电连接，可以将第一导电层和第二导电层聚集的静电经由第一走线和第二走线传导至周边区域，避免显示区域产生ESD击伤晶体管，可以降低显示区域的ESD风险。例如，在制备第三导电层之前，工艺制程产生的静电聚集在第一发光控制晶体管的第二导电层处，在第三导电层制备完成后，静电可以经由第一走线接入第二走线中，再经由第二走线导入周边区域。而且，通过设置可以覆盖第一发光晶体管的有源层的沟道区域的连接电极、以及覆盖第一复位控制晶体管的有源层的沟道区域的连接电极，可以降低显示区域ESD风险。
在本示例中，在周边区域，设置位于第三导电层的第一初始转接线电连接第一初始周边走线与第一初始信号线，以及第二初始转接线电连接第二初始周边走线与第二初始信号线，可以有利于第二导电层中产生的静电通过第三导电层导出显示区域。例如，在制备第三导电层之前，工艺制程产生的静电会聚集在第一初始信号线和第二初始信号线上，在第三导电层制备完成后，静电可以经由第三导电层的第一初始转接线和第二初始转接线导入周边区域，从而避免产生ESD击伤晶体管。
(6)、形成第四绝缘层和第五绝缘层。
在一些示例性实施方式中，在形成前述图案的衬底100上沉积第四绝缘薄膜，形成第四绝缘层104；随后，涂覆第五绝缘薄膜，并通过图案化工艺对第五绝缘薄膜进行图案化，形成第五绝缘层105，如图15A至图15C所示。在一些示例中，可以在第五绝缘层105形成过孔或凹槽之后，再对第四绝缘层104进行刻蚀，形成第四绝缘层104开设的过孔或凹槽，以暴露出第三导 电层的表面。
(7)、形成第四导电层。
在一些示例性实施方式中，在形成前述图案的衬底100上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，形成第四导电层24，如图5、图7和图8所示。
至此，制备完成第一显示区A1的电路结构层。第二显示区A2可以包括衬底100以及叠设在衬底100上的第一绝缘层101、第二绝缘层102、第三绝缘层103、第四绝缘层104以及第五绝缘层105。
(8)、依次形成至少一个透明导电层以及发光结构层，发光结构层可以包括：阳极层、像素定义层、有机发光层以及阴极层。
在一些示例性实施方式中，在形成前述图案的衬底基板上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成第一平坦层。在在形成前述图案的衬底上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成透明导电层。透明导电层可以包括电连接第二像素电路和第二发光元件的透明导电线。随后，在形成前述图案的衬底基板上涂覆第二平坦薄膜，通过图案化工艺对第二平坦薄膜进行图案化，形成第二平坦层。随后，在形成前述图案的衬底基板上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。随后，在形成前述图案的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层。像素定义层形成有暴露出阳极层的多个像素开口。随后，在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极层，阴极层分别与有机发光层和第二电源线电连接。在一些示例中，在阴极层上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。在另一些示例中，可以设置多个透明导电层，多条透明导电线可以排布在多个透明导电层中。相邻透明导电层之间可以设置至少一个平坦层。
在一些示例性实施方式中，第一导电层21、第二导电层22、第三导电层23和第四导电层24可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金 (AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层101、第二绝缘层102、第三绝缘层103和第四绝缘层104可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层101和第二绝缘层102可以称之为栅绝缘(GI)层，第三绝缘层103可以称之为层间绝缘(ILD)层，第四绝缘层104可以称之为钝化层。第五绝缘层105、第一平坦层和第二平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极层可以采用金属等反射材料，阴极层可以采用透明导电材料。然而，本实施例对此并不限定。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一走线可以位于第二导电层，第二走线可以位于第三导电层，第一走线和第二走线可以通过第三绝缘层开设的过孔电连接。又如，第一电源线可以延伸至第三边框区和第四边框区，第一走线可以延伸至第三边框区和第四边框区，并与第一电源线直接电连接。然而，本实施例对此并不限定。
本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与已有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本实施例提供的显示基板，通过在显示区域设置第一走线和第二走线，形成网状连接结构，且第二走线可以与周边区域的第三走线(例如，包括第一电源线和第一电源连接线)电连接，可以有利于将工艺制程中产生的静电导出显示区域。而且，在周边区域设置位于第三导电层的第一初始转接线和第二初始转接线实现初始信号线与初始周边走线之间的电连接，可以有利于将第二导电层中产生的ESD导出显示区域，降低显示区域的ESD不良的发生率，可以提高显示基板的产品良率。
图16A为图5中区域S2的电路结构层的另一局部放大示意图。图16B为图16A中形成第三导电层后的电路结构层的示意图。在一些示例中，如图16A和图16B所示，第三边框区B3的第三导电层23可以包括：第一初始转 接线236、第二初始转接线237、扫描转接线254、发光控制转接线255、第二扫描转接块239、第一初始子走线271和第二初始子走线281。第一初始转接线236可以电连接第一初始信号线INIT1，并通过第二导电层22的第三初始转接线与第三导电层23的第一初始子走线271电连接。第二初始转接线237可以电连接第二初始信号线INIT2，并通过第二导电层22的第四初始转接线与第三导电层23的第二初始子走线281电连接。扫描转接线254可以与第二扫描转接块239为一体结构。扫描转接线254可以实现扫描线与位于第二导电层的扫描输出线的电连接。发光控制转接线255可以实现发光控制线与位于第二导电层的发光控制输出线的电连接。
在本示例中，在周边区域，设置位于第三导电层的扫描转接线和发光控制转接线，可以有利于第一导电层中产生的静电通过第三导电层导出显示区域。例如，在制备第三导电层之前，工艺制程产生的静电会聚集在扫描线、发光控制线、第一复位控制线和第二复位控制线上，在第三导电层制备完成后，静电可以经由第三导电层的扫描转接线和发光控制转接线导入周边区域，从而避免产生ESD击伤晶体管。
关于本实施例的显示基板的其余结构可以如前所述，故于此不再赘述。
本公开至少一实施例还提供一种显示装置，包括如上所述的显示基板。
图17为本公开至少一实施例的显示装置的示意图。如图17所示，本实施例提供一种显示装置，包括：显示基板91以及位于远离显示基板91的发光结构层的出光侧的感光传感器92。感光传感器92位于显示基板91的非显示面一侧。感光传感器92在显示基板91上的正投影与第一显示区A1存在交叠。
在一些示例性实施方式中，显示基板91可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为具有图像(包括静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。例如，显示装置可以是：显示器、电视机、广告牌、数码相框、具有显示功能的激光打印机、电话、手机、画屏、个人数字助理(PDA，Personal Digital Assistant)、数码相机、便携式摄录机、取景器、导航仪、车辆、大面积墙壁、信息查询设备(比如电子政务、银行、医院、电力等部门 的业务查询设备)、监视器等中的任一种产品。又如，显示装置还可以是微显示器，包含微显示器的VR设备或AR设备等中的任一种产品。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种显示基板，包括：
    衬底，包括显示区域以及位于所述显示区域外围的周边区域；所述显示区域包括：第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
    电路结构层，位于所述衬底上，包括：多个像素电路、沿第一方向延伸的至少一条第一走线、沿第二方向延伸的至少一条第二走线、以及位于所述周边区域的至少一条第三走线；所述第一方向与所述第二方向交叉；所述多个像素电路、所述第一走线和第二走线位于所述第一显示区；
    发光结构层，位于所述电路结构层远离所述衬底的一侧，包括：位于所述第一显示区的多个第一发光元件以及位于所述第二显示区的多个第二发光元件；
    所述多个像素电路包括：多个第一像素电路和多个第二像素电路；所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件电连接，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件电连接；
    所述至少一条第一走线与所述至少一条第二走线电连接，所述至少一条第三走线与以下至少一项电连接：所述至少一条第一走线、所述至少一条第二走线。
  2. 根据权利要求1所述的显示基板，其中，所述至少一条第一走线与所述至少一条第二走线为一体结构。
  3. 根据权利要求1或2所述的显示基板，其中，所述多个像素电路还包括：多个无效像素电路，所述至少一条第二走线在所述衬底的正投影与至少一个无效像素电路在所述衬底的正投影存在交叠。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述至少一条第一走线在所述衬底的正投影位于相邻两行像素电路之间。
  5. 根据权利要求1至4中任一项所述的显示基板，其中，所述周边区域包括：沿所述第二方向位于所述显示区域相对两侧的第一边框区和第二边框 区；所述至少一条第三走线包括：位于所述第一边框区的第一电源线以及位于所述第二边框区的第一电源连接线；所述至少一条第二走线与所述第一电源连接线和所述第一电源线中的至少之一电连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一电源线包括叠设且相互电连接的第一子电源线和第二子电源线；所述至少一条第二走线、所述第一电源连接线和所述第一子电源线为一体结构。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，在垂直于所述显示基板的方向上，所述第一显示区的电路结构层包括：设置在所述衬底上的半导体层、第一导电层、第二导电层和第三导电层；
    所述半导体层至少包括：至少一个像素电路的晶体管的有源层；
    所述第一导电层至少包括：所述至少一个像素电路的晶体管的栅极以及存储电容的第一电容极板；
    所述第二导电层至少包括：所述至少一个像素电路的存储电容的第二电容极板；
    所述第三导电层至少包括：所述第一走线和所述第二走线。
  8. 根据权利要求7所述的显示基板，其中，所述第一显示区的电路结构层还包括：位于所述第三导电层远离所述衬底一侧的第四导电层；
    所述第四导电层至少包括：数据线、虚设数据线以及第一电源传输线；
    所述数据线与多个第一像素电路或多个第二像素电路电连接，所述第一电源传输线与所述多个像素电路电连接，所述虚设数据线与所述第二走线电连接；
    所述虚设数据线和所述第一电源传输线均与所述第三走线电连接。
  9. 根据权利要求7至8中任一项所述的显示基板，其中，所述第二导电层还包括：第一初始信号线和第二初始信号线；所述第一初始信号线和第二初始信号线均沿所述第一方向延伸；
    所述周边区域还包括：第一初始周边走线和第二初始周边走线；所述第一初始周边走线和第二初始周边走线沿所述第二方向延伸；
    所述第一初始信号线通过第一初始转接线与所述第一初始周边走线电连接；所述第二初始信号线通过第二初始转接线与所述第二初始周边走线电连接；所述第一初始转接线与所述第二初始转接线位于所述第三导电层。
  10. 根据权利要求7至9中任一项所述的显示基板，其中，所述第一导电层还包括：沿所述第一方向延伸的扫描线和发光控制线；
    所述周边区域还包括：扫描输出线和发光控制输出线；
    所述扫描线通过扫描转接线与所述扫描输出线电连接；所述发光控制线通过发光控制转接线与所述发光控制输出线电连接；
    所述扫描转接线和所述发光控制转接线位于所述第三导电层，所述扫描输出线和发光控制输出线位于所述第二导电层或第一导电层。
  11. 根据权利要求7至10中任一项所述的显示基板，其中，所述像素电路至少包括：驱动晶体管、第一发光控制晶体管；所述第一发光控制晶体管的栅极与发光控制线电连接，第一极与第一电源线电连接，第二极与所述驱动晶体管的第一极电连接；所述第三导电层还包括：第一遮挡电极；所述第一遮挡电极在所述衬底的正投影至少部分覆盖所述第一发光控制晶体管的有源层的沟道区在所述衬底的正投影。
  12. 根据权利要求11所述的显示基板，其中，所述像素电路还包括：第一复位晶体管；所述第一复位晶体管的栅极与第一复位控制线电连接，第一极与第一初始信号线电连接，第二极与所述驱动晶体管的栅极电连接；
    所述第三导电层还包括：第二遮挡电极；所述第二遮挡电极在所述衬底的正投影至少部分覆盖所述第一复位晶体管的有源层的沟道区在所述衬底的正投影。
  13. 根据权利要求7至12中任一项所述的显示基板，其中，所述第二导电层与所述第三导电层之间设置有第三绝缘层，所述第一显示区的第三绝缘层开设有多个过孔；至少一个过孔在所述衬底的正投影与所述第一导电层或第二导电层的至少一条走线在所述衬底的正投影在所述第二方向的距离大于或等于2微米。
  14. 一种显示装置，包括如权利要求1至13中任一项所述的显示基板。
  15. 根据权利要求14所述的显示装置，还包括：位于所述显示基板的非显示面一侧的传感器，所述传感器在所述显示基板的正投影与所述显示基板的第二显示区存在交叠。
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