WO2021147083A1 - 像素电路、显示基板和显示装置 - Google Patents

像素电路、显示基板和显示装置 Download PDF

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Publication number
WO2021147083A1
WO2021147083A1 PCT/CN2020/073996 CN2020073996W WO2021147083A1 WO 2021147083 A1 WO2021147083 A1 WO 2021147083A1 CN 2020073996 W CN2020073996 W CN 2020073996W WO 2021147083 A1 WO2021147083 A1 WO 2021147083A1
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WIPO (PCT)
Prior art keywords
circuit
pixel
terminal
light
control
Prior art date
Application number
PCT/CN2020/073996
Other languages
English (en)
French (fr)
Inventor
黄耀
邱远游
黄炜赟
肖星亮
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000102.7A priority Critical patent/CN113508430B/zh
Priority to PCT/CN2020/073996 priority patent/WO2021147083A1/zh
Priority to CN202010130251.7A priority patent/CN111326560B/zh
Priority to PCT/CN2020/080182 priority patent/WO2021147160A1/zh
Priority to KR1020217038802A priority patent/KR20220129999A/ko
Priority to CN202080000311.1A priority patent/CN113508466A/zh
Priority to EP20891410.1A priority patent/EP4095921A4/en
Priority to US17/297,641 priority patent/US11968865B2/en
Priority to JP2022502521A priority patent/JP2023520267A/ja
Priority to PCT/CN2021/073243 priority patent/WO2021147987A1/zh
Priority to US17/428,847 priority patent/US11980071B2/en
Publication of WO2021147083A1 publication Critical patent/WO2021147083A1/zh
Priority to US18/390,381 priority patent/US20240172497A1/en
Priority to US18/396,840 priority patent/US20240138214A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the embodiments of the present disclosure relate to a pixel circuit, a display substrate, and a display device.
  • Organic Light Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, and fast response speed. In addition, compared with inorganic light-emitting display devices, organic light-emitting diode display devices have advantages such as higher light-emitting brightness and lower driving voltage. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, and instrumentation.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a first driving circuit, a second driving circuit, a data writing circuit, and a signal storage circuit.
  • the data writing circuit is configured to receive a data signal;
  • the first driving circuit is connected to the data writing circuit, and is configured to receive the data signal from the data writing circuit and allow the data signal to be Written to the control terminal of the first drive circuit;
  • the control terminal of the second drive circuit is configured to receive the data signal written to the control terminal of the first drive circuit;
  • the signal storage circuit is Is configured to store the data signal written to the control terminal of the first drive circuit at the control terminal of the first drive circuit;
  • the first terminal of the first drive circuit and the first terminal of the second drive circuit One end is configured to receive the first power supply voltage from the first power supply voltage terminal, and the second end of the first driving circuit and the second end of the second driving circuit are both configured to be electrically connected to the first power supply voltage terminal of the light emitting element.
  • the first drive circuit and the second drive circuit are configured to, based on the data signal stored in the signal storage circuit and the received first power supply voltage, control to flow through
  • the first driving circuit and the second driving circuit have a driving current from the first power supply voltage terminal to the light-emitting element for driving the light-emitting element.
  • control terminal of the first drive circuit and the control terminal of the second drive circuit are electrically connected to each other.
  • the pixel circuit further includes a compensation connection circuit.
  • the data writing circuit writes the data signal to the first end of the first drive circuit; and the compensation connection circuit is connected to the second end of the first drive circuit and the first drive circuit Between the control terminals of and configured to write the data signal written to the first terminal of the first drive circuit to the control terminal of the first drive circuit via the first drive circuit.
  • control terminal of the compensation connection circuit and the control terminal of the data writing circuit are connected to the same scan signal line.
  • the pixel circuit further includes a first reset circuit.
  • the first reset circuit is connected to the signal storage circuit; and the first reset circuit is configured to receive a first reset signal, and write the first reset signal to the signal storage circuit, so as to correct the The signal storage circuit is reset.
  • the pixel circuit further includes a first control circuit and a second control circuit.
  • the first control circuit is connected between the first terminal of the first driving circuit and the first power supply voltage terminal, and is configured to control whether the first driving circuit is electrically connected to the first power supply terminal
  • the second control circuit is connected between the first terminal of the second drive circuit and the first power supply voltage terminal, and is configured to control whether the second drive circuit is connected to the first power supply terminal Electric connection.
  • control terminal of the first control circuit and the control terminal of the second control circuit are connected to the same light emission control line.
  • the pixel circuit further includes a second reset circuit.
  • the second reset circuit is configured to receive a second reset signal and write the second reset signal to the first end of the light-emitting element to reset the first end of the light-emitting element.
  • the pixel circuit further includes a third control circuit and a fourth control circuit.
  • the third control circuit is connected between the second end of the first drive circuit and the first end of the light-emitting element, and is configured to control whether the first drive circuit is connected to the first end of the light-emitting element. Terminal is electrically connected; and the fourth control circuit is connected between the second terminal of the second drive circuit and the first terminal of the light-emitting element, and is configured to control whether the second drive circuit is connected to the The first end of the light-emitting element is electrically connected.
  • control terminal of the third control circuit and the control terminal of the fourth control circuit are connected to the same light-emitting control line.
  • the first driving circuit includes a first transistor
  • the second driving circuit includes a second transistor
  • the threshold voltage of the first transistor and the second transistor The threshold voltages are equal.
  • At least one embodiment of the present disclosure further provides a display substrate, which includes any pixel circuit provided in at least one embodiment of the present disclosure.
  • the at least one pixel circuit includes a plurality of pixel circuits;
  • the display substrate has a display area, and the display area includes a first display area and a second display area;
  • the first display area includes a plurality of first pixel units arranged in an array,
  • the second display area includes a plurality of second pixel units arranged in an array;
  • the distribution density per unit area is smaller than the distribution density per unit area of the plurality of second pixel units in the second display area; each of the plurality of first pixel units includes the light-emitting element; and the plurality of pixel circuits
  • the plurality of light-emitting elements are electrically connected in a one-to-one correspondence.
  • the first display area further includes a first sub-display area and a second sub-display area that do not overlap each other; the first sub-display area includes the plurality of second sub-display areas.
  • a first group of pixel units, the second sub-display area includes a second group of the plurality of first pixel units, the first group and the second group do not overlap with each other;
  • the pixel circuits connected to the second group of light-emitting elements of a pixel unit are arranged in the first sub-display area in a one-to-one correspondence.
  • the display substrate further includes a plurality of transparent wires.
  • the plurality of transparent wirings electrically connect the light-emitting elements of the second group of the plurality of first pixel units and the pixel circuits connected in a one-to-one correspondence with the light-emitting elements of the second group of the plurality of first pixel units.
  • the display substrate further has a peripheral area at least partially surrounding the display area, and the plurality of pixel circuits are at least partially disposed in the peripheral area.
  • the display substrate further includes a sensor.
  • the sensor is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area.
  • the light signal of the display area is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area. The light signal of the display area.
  • At least one embodiment of the present disclosure further provides a display device, which includes any pixel circuit or any display substrate provided in at least one embodiment of the present disclosure.
  • Fig. 1A is a schematic cross-sectional view of a display substrate
  • FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A;
  • FIG. 1C is a schematic diagram of a partial area of the display substrate shown in FIG. 1B;
  • FIG. 2A is a schematic diagram of a structure of a 7T1C pixel circuit
  • FIG. 2B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 2A;
  • FIG. 3 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 4A is an example of the pixel circuit shown in FIG. 3;
  • FIG. 4B is a driving timing diagram of the pixel circuit shown in FIG. 4A;
  • FIG. 5A is an exemplary block diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 5B is a schematic cross-sectional view of the display substrate shown in FIG. 5A;
  • Fig. 6 is a schematic plan view of an example of the display substrate shown in Fig. 5B;
  • FIG. 7A is a schematic diagram of a partial area of the first display area of the display substrate shown in FIG. 6; FIG.
  • FIG. 7B shows a schematic diagram of a first group of a plurality of first pixel units shown in FIG. 7A;
  • FIG. 7C shows a schematic diagram of a second group of a plurality of first pixel units shown in FIG. 7A;
  • FIG. 8A is a schematic diagram of a partial area of a second display area of the display substrate shown in FIG. 6;
  • FIG. 8B shows an example of the first pixel unit shown in FIG. 7A
  • FIG. 8C shows another example of the first pixel unit shown in FIG. 7A
  • FIG. 8D shows a schematic diagram of the second pixel unit shown in FIG. 8A
  • FIG. 8E shows a schematic diagram of the redundant pixel unit shown in FIG. 7A
  • FIG. 9 is a schematic plan view of another example of the display substrate shown in FIG. 5B.
  • FIG. 10 is a schematic plan view of still another example of the display substrate shown in FIG. 5B.
  • FIG. 11 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the inventors of the present disclosure noticed that the current display substrates with under-screen sensors (cameras) have relatively low luminous brightness in the display areas corresponding to the under-screen sensors (cameras), thereby affecting the quality of images displayed by the display substrates. Exemplary description will be given below in conjunction with FIG. 1A, FIG. 1B, FIG. 2A, and FIG. 2B.
  • FIG. 1A is a schematic cross-sectional view of a display substrate 500
  • FIG. 1B is a schematic plan view of the display substrate 500 shown in FIG. 1A
  • FIG. 1C is a schematic diagram of a partial area 513 of the display substrate 500 shown in FIG. 1B.
  • the display substrate 500 shown in FIG. 1B corresponds to the BB' line of the display substrate 10 shown in FIG. 1A.
  • the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on the non-display side of the display substrate 500.
  • the display layer 510 includes a first display area 511 and a second display area 512; the first display area 511 includes a plurality of first light-emitting elements 531 arranged in an array, and the second display area 512 includes an array A plurality of second light emitting elements 532 are arranged.
  • the plurality of first light-emitting elements 531 and the plurality of second light-emitting elements 532 have the same structure and performance characteristics.
  • the sensing layer 520 includes a sensor 521.
  • the sensor 521 and the first display area 511 overlap in the normal direction of the display surface of the display substrate 500, and are configured to receive and process the first display area. 511 light signal.
  • the light-emitting elements 531 in the first display area 511 are The distribution density per unit area is smaller than the distribution density per unit area of the plurality of second light-emitting elements 532 in the second display area 512.
  • this makes the effective light-emitting area of the first display area 511 smaller than the effective light-emitting area of the second display area 512, and makes the brightness of the image area corresponding to the first display area 511 in the image displayed by the display substrate 500 and the brightness of the image area corresponding to the second display area 511 smaller than that of the second display area 512.
  • the brightness difference of the image area of the display area 512 is relatively large.
  • the display layer 510 further includes a plurality of first pixel circuits and a plurality of second pixel circuits (not shown in FIGS. 1A-1C, see FIG. 2A); the plurality of first pixel circuits are configured to drive multiple pixels in one-to-one correspondence.
  • One first light-emitting element 531, and multiple second pixel circuits are configured to drive multiple second light-emitting elements 532 in a one-to-one correspondence.
  • the plurality of first pixel circuits and the plurality of second pixel circuits have the same circuit structure.
  • the data signal (e.g., data voltage) received by the plurality of first pixel circuits that drive the plurality of first light-emitting elements is equal to the data signal (e.g., data voltage) received by the plurality of second pixel circuits that drive the plurality of second light-emitting elements.
  • the light-emitting brightness of the plurality of first light-emitting elements is smaller than the light-emitting brightness of the plurality of second light-emitting elements, and therefore the brightness of the image area corresponding to the first display area 511 in the image displayed by the display substrate may be lower than Schedule brightness.
  • each of the plurality of first pixel circuits and the plurality of second pixel circuits can be implemented as a 2T1C pixel circuit, a 3T1C pixel circuit, a 5T1C pixel circuit, a 7T1C pixel circuit, or other applicable pixel circuits.
  • the 2T1C pixel circuit is a pixel circuit including two transistors and a storage capacitor Cst
  • the 7T1C pixel circuit is a pixel circuit including seven transistors and a storage capacitor Cst.
  • the display substrate 500 shown in FIG. 1A and FIG. 1B will be exemplarily described by taking each of the plurality of first pixel circuits and the plurality of second pixel circuits as a 7T1C pixel circuit 580.
  • FIG. 2A is a schematic structural diagram of a 7T1C pixel circuit 580.
  • the 7T1C pixel circuit 580 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a storage capacitor Cst.
  • the first transistor CT1-the seventh transistor CT7 are all P-type transistors.
  • the first terminal of the storage capacitor Cst is connected to the first power supply voltage terminal VDD to receive the first power supply voltage V1; the second terminal of the storage capacitor Cst is connected to the first node N1; the first terminal of the light emitting element EL Terminal is connected to the fourth node N4, the second terminal of the light emitting element EL is connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2; the control terminal of the first transistor CT1 is connected to the first node N1; the first transistor CT1 The first terminal of the first transistor CT1 is connected to the second node N2, the second terminal of the first transistor CT1 is connected to the third node N3; the first terminal of the second transistor CT2 is connected to the second node N2, and the second terminal of the second transistor CT2 is connected to The data signal terminal DAT is connected to receive a data signal (for example, a data voltage) Vdata; the first terminal of the third transistor CT3 is connected to the first node N1, and the second terminal of the third transistor CT3
  • control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown in the figure);
  • control terminal EM1 of the fifth transistor CT5 and the control terminal of the seventh transistor CT7 EM2 are all connected to the light-emitting control terminal EM (not shown in the figure);
  • the control terminal of the fourth transistor CT4 is configured as the first reset control terminal RST1;
  • the control terminal of the sixth transistor CT6 is configured as the second reset control terminal RST2.
  • FIG. 2A also shows the first node N1, the second node N2, the third node N3, the fourth node N4, and the light emitting element EL.
  • FIG. 2B is a driving timing diagram of the 7T1C pixel circuit 580 shown in FIG. 2A. As shown in FIG. 2B, each driving cycle of the 7T1C pixel circuit 580 includes a first phase t1, a second phase t2, and a third phase t3.
  • the first reset control terminal RST1 receives the active level, and the scan signal terminal GAT, the second reset control terminal RST2 and the light-emitting control terminal EM all receive the invalid level; this
  • the fourth transistor CT4 is turned on, the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive the first reset signal (for example, Reset voltage) Vinit1, and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value.
  • the first transistor CT1 is turned on.
  • the scan signal terminal GAT and the second reset control terminal RST2 receive the valid level
  • the first reset control terminal RST1 and the light-emitting control terminal EM receive the invalid level
  • the first transistor CT1-the third transistor CT3 and the sixth transistor CT6 are turned on
  • the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off
  • the second transistor CT2 receives the data signal Vdata
  • the data signal Vdata is turned on
  • the first transistor CT1 and the third transistor CT3 are written to the control terminal of the first transistor CT1.
  • the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1.
  • the voltage of a node N1 is Vdata+Vth; the sixth transistor CT6 is configured to receive a second reset signal (for example, a reset voltage) Vinit2, and write the second reset signal Vinit2 to the first end of the light-emitting element EL to emit light
  • a second reset signal for example, a reset voltage
  • Vinit2 The first terminal of the element EL is reset
  • Vinit2 Vinit2
  • Vinit2 is, for example, a negative value.
  • the light-emitting control terminal EM receives the valid level
  • the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive the invalid level
  • the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on
  • the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off
  • the first transistor CT1 is configured to be based on storage
  • the data signal (for example, the data voltage) Vdata in the storage capacitor Cst and the received first power supply voltage V1 are controlled to flow through the first transistor CT1 and from the first power supply voltage terminal VDD to the light emitting element EL for driving the light emitting element.
  • the driving current of EL; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD; the driving current Id can be expressed by the following formula.
  • k ⁇ Cox ⁇ W/L; ⁇ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, and W/L is the channel of the first transistor CT1
  • Vth is the threshold voltage of the first transistor CT1
  • Vth is the gate-source voltage of the first transistor CT1
  • Vg is the gate voltage of the first transistor CT1
  • Vs is the source voltage of the first transistor CT1.
  • the 7T1C pixel circuit 580 shown in FIGS. 2A and 2B has a threshold compensation function.
  • At least one embodiment of the present disclosure provides a pixel circuit, a display substrate, and a display device.
  • the pixel circuit includes: a first driving circuit, a second driving circuit, a data writing circuit, and a signal storage circuit.
  • the data writing circuit is configured to receive a data signal;
  • the first driving circuit is connected to the data writing circuit, and is configured to receive the data signal from the data writing circuit and allow the data signal to be written to the control terminal of the first driving circuit;
  • the control terminal of the second driving circuit is configured to receive the data signal written to the control terminal of the first driving circuit;
  • the signal storage circuit is configured to store the data written to the control terminal of the first driving circuit on the control terminal of the first driving circuit.
  • the first terminal of the first driving circuit and the first terminal of the second driving circuit are both configured to receive the first power supply voltage from the first power supply voltage terminal, the second terminal of the first driving circuit and the second driving circuit
  • the second terminals are each configured to be electrically connected to the first terminal of the light emitting element; and the first driving circuit and the second driving circuit are configured to, based on the data signal stored in the signal storage circuit and the received first power supply voltage, Controlling the driving current flowing through the first driving circuit and the second driving circuit from the first power supply voltage terminal to the light emitting element for driving the light emitting element.
  • the pixel circuit can increase the value of the driving current flowing through the light-emitting element electrically connected to the pixel circuit and the brightness of the light-emitting element electrically connected to the pixel circuit.
  • FIG. 3 is a schematic diagram of a pixel circuit 100 provided by at least one embodiment of the present disclosure.
  • the pixel circuit 100 includes a first driving circuit 101, a second driving circuit 102, a data writing circuit 103, and a signal storage circuit 104.
  • the data writing circuit 103 is configured to receive a data signal.
  • the data writing circuit 103 is configured to be connected to the data signal terminal DAT to receive the data signal provided by the data signal terminal DAT.
  • the data signal is a voltage signal.
  • the first driving circuit 101 is connected to the data writing circuit 103, and is configured to receive data signals from the data writing circuit 103 and allow the data signals to be written to the control terminal of the first driving circuit 101;
  • the control terminal of the driving circuit 102 is configured to receive the data signal written to the control terminal of the first driving circuit 101;
  • the signal storage circuit 104 is configured to store the data signal written to the control terminal of the first driving circuit 101 at the control terminal of the first driving circuit 101.
  • the signal storage circuit 104 is connected between the first power supply voltage terminal VDD and the control terminal of the first driving circuit 101.
  • the first terminal of the first driving circuit 101 and the first terminal of the second driving circuit 102 are both configured to receive the first power supply voltage from the first power supply voltage terminal VDD, and the second terminal of the first driving circuit 101 Terminal and the second terminal of the second driving circuit 102 are both configured to be electrically connected to the first terminal of the light emitting element 116; the first driving circuit 101 and the second driving circuit 102 are configured to be based on the information stored in the signal storage circuit 104
  • the data signal and the received first power supply voltage control the driving current flowing through the first driving circuit 101 and the second driving circuit 102 from the first power supply voltage terminal VDD to the light-emitting element 116 for driving the light-emitting element 116, respectively.
  • the first driving circuit 101 and the second driving circuit 102 generate flow through the first driving circuit 101 and the second driving circuit, respectively.
  • the circuit 102 and the driving current from the first power supply voltage terminal VDD to the light-emitting element 116 are used to drive the light-emitting element 116, so that the pixel circuit 100 can increase the driving current flowing through the light-emitting element 116 electrically connected to the pixel circuit 100 Value and the brightness of the light-emitting element 116 electrically connected to the pixel circuit 100.
  • At least one embodiment of the present disclosure can increase the brightness of the light-emitting element 116 electrically connected to the pixel circuit 100 by connecting a simple first driving circuit 101 in parallel to the pixel circuit 100 shown in FIG. 2A. This can improve the brightness of the light-emitting element 116 electrically connected to the pixel circuit 100 while keeping the structure of the pixel circuit 100 as simple as possible.
  • control terminal of the first drive circuit 101 and the control terminal of the second drive circuit 102 are electrically connected to each other, so that the control terminal of the second drive circuit 102 can receive data written to the first drive circuit.
  • the data signal of the control terminal of 101 For example, the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 102 are directly connected.
  • the pixel circuit 100 further includes a compensation connection circuit 105.
  • the data writing circuit 103 writes the data signal to the first end of the first drive circuit 101;
  • the compensation connection circuit 105 is connected between the second end of the first drive circuit 101 and the control end of the first drive circuit 101, And it is configured to write the data signal written to the first terminal of the first driving circuit 101 to the control terminal of the first driving circuit 101 via the first driving circuit 101.
  • the compensation connection circuit 105 to write the data signal written to the first terminal of the first driving circuit 101 to the control terminal of the first driving circuit 101 via the first driving circuit 101, the first The threshold characteristic of the driving circuit 101 is written into the control terminal of the first driving circuit 101 and stored in the signal storage circuit 104, thereby eliminating the effect of the threshold characteristic of the first driving circuit 101 on the flow through the first driving circuit 101.
  • the driving circuit 101 is connected from the first power supply voltage terminal VDD to the light-emitting element 116, and the driving current for driving the light-emitting element 116 is adversely affected, that is, by setting the compensation connection circuit 105, it is possible to make the at least one embodiment of the present disclosure provide
  • the pixel circuit 100 has a threshold compensation function.
  • the threshold characteristic of the first driving circuit 101 and the threshold characteristic of the second driving circuit 102 are similar, so that the compensation connection circuit 105 can also reduce the impact of the threshold characteristic of the second driving circuit 102 on the flow through the second driving circuit 102.
  • the second driving circuit 102 and the driving current from the first power supply voltage terminal VDD to the light-emitting element 116 are adversely affected.
  • that the threshold characteristic of the first driving circuit 101 and the threshold characteristic of the second driving circuit 102 are similar means that the ratio of the difference between the threshold of the first driving circuit 101 and the threshold of the second driving circuit 102 to the threshold of the first driving circuit 101 Less than 10% (for example, less than 5%, 3%, or 1%).
  • the first driving circuit 101 and the second driving circuit 102 have the same threshold characteristics; in this case, the compensation connection circuit 105 can also eliminate the threshold characteristics of the second driving circuit 102 to the second driving circuit 102 and the flow through the second The driving circuit 102 and the driving current from the first power supply voltage terminal VDD to the light-emitting element 116 are adversely affected, thereby further improving the threshold compensation function of the pixel circuit 100 provided by at least one embodiment of the present disclosure.
  • the control terminal GAT1 of the data writing circuit 103 and the control terminal GAT2 of the compensation connection circuit 105 are configured to receive the same scan signal, thereby causing the first drive circuit 101 to be written to
  • the data signal at the terminal can be written to the control terminal of the first drive circuit 101 by turning on the first drive circuit 101 and the compensation connection circuit 105 during the data writing stage of the pixel circuit 100.
  • the data writing stage is also This is called the data writing and compensation stage of the pixel circuit 100.
  • the control terminal of the compensation connection circuit 105 and the control terminal of the data writing circuit 103 are connected to the same scan signal terminal GAT or scan signal line (not shown in the figure), which can simplify the display substrate including the pixel circuit 100. structure.
  • the pixel circuit 100 further includes a first reset circuit 106.
  • the first reset circuit 106 is connected to the signal storage circuit 104; the first reset circuit 106 is configured to receive the first reset signal and write the first reset signal to the signal storage circuit 104 to reset the signal storage circuit 104.
  • the first reset signal may be the first reset voltage.
  • the first reset voltage is a negative value (for example, -3V), so that the first driving circuit 101 can still be turned on after the storage circuit is reset in the case of a process deviation.
  • the first reset circuit 106 may reset the signal storage circuit 104 during the reset phase of the pixel circuit 100.
  • the first terminal of the first reset circuit 106 is connected to the signal storage circuit 104; the second terminal of the first reset circuit 106 is connected to the first reset signal terminal Init1 to receive the first reset signal provided by the first reset signal terminal Init1 ;
  • the control terminal of the first reset circuit 106 is configured as the first reset control terminal RST1.
  • the pixel circuit 100 further includes a first control circuit 111; the first control circuit 111 is connected between the first terminal of the first driving circuit 101 and the first power supply voltage terminal VDD, and is configured to control Whether the first driving circuit 101 is electrically connected to the first power supply voltage terminal VDD.
  • the first control circuit 111 by providing the first control circuit 111, the first power supply voltage provided by the first power supply voltage terminal VDD can be prevented from adversely affecting the data signal written to the first terminal of the first driving circuit 101 during the data writing and compensation stage.
  • the pixel circuit 100 further includes a second reset circuit 115.
  • the second reset circuit 115 is configured to receive the second reset signal and write the second reset signal to the first end of the light-emitting element 116 to reset the first end of the light-emitting element 116.
  • the first terminal of the second reset circuit 115 is connected to the first terminal of the light-emitting element 116; the second terminal of the second reset circuit 115 is connected to the second reset signal terminal Init2 to receive the first terminal provided by the second reset signal terminal Init2.
  • Two reset signals; the control terminal of the second reset circuit 115 is configured as a second reset control terminal RST2.
  • the second reset circuit 115 is configured to eliminate the electric charge that may remain on the light-emitting element 116.
  • the first end of the light-emitting element 116 may be reset before the light-emitting stage to improve the accuracy of the brightness of the light-emitting element 116 and the contrast of the display substrate including the pixel circuit 100.
  • the first end of the light-emitting element 116 may be reset during the data writing and compensation phase or the reset phase of the pixel circuit 100.
  • the second reset signal may be a second reset voltage.
  • the second terminal of the light-emitting element 116 is connected to the second power supply voltage terminal VSS to receive the second power supply voltage provided by the second power supply voltage terminal VSS.
  • the second reset voltage is equal to the second power supply voltage to prevent the light-emitting element 116 from emitting light during the resetting of the first terminal of the light-emitting element 116.
  • the second reset voltage and the second power supply voltage are both negative values (for example, -3V).
  • the second power supply voltage is less than the first power supply voltage.
  • the pixel circuit 100 further includes a third control circuit 113.
  • the third control circuit 113 is connected between the second end of the first driving circuit 101 and the first end of the light emitting element 116 and is configured to control whether the first driving circuit 101 is electrically connected to the first end of the light emitting element 116.
  • the third control circuit 113 by providing the third control circuit 113, the voltage at the second terminal of the first driving circuit 101 and the voltage at the first terminal of the light-emitting element 116 can be prevented from interfering with each other during the data writing and compensation stage.
  • the third control circuit 113 by providing the third control circuit 113, during the data writing and compensation stage, the voltage at the second end of the first driving circuit 101 can be prevented from adversely affecting the resetting of the first end of the light-emitting element 116 and the light-emitting element 116 can be prevented from emitting light.
  • the third control circuit 113 by providing the third control circuit 113, during the data writing and compensation stage, the voltage at the first end of the light-emitting element 116 can be prevented from adversely affecting the voltage at the second end of the first driving circuit 101 and threshold compensation.
  • the pixel circuit 100 further includes a second control circuit 112; the second control circuit 112 is connected between the first terminal of the second driving circuit 102 and the first power supply voltage terminal VDD, and is configured to control Whether the second driving circuit 102 is electrically connected to the first power supply voltage terminal VDD.
  • the second control circuit 112 it is possible to prevent the second driving circuit 102 from driving the light-emitting element 116 to emit light at a stage other than the light-emitting stage.
  • the pixel circuit 100 further includes a fourth control circuit 114; the fourth control circuit 114 is connected between the second end of the second driving circuit 102 and the first end of the light-emitting element 116, and is configured to It is controlled whether the second driving circuit 102 is electrically connected to the first end of the light-emitting element 116.
  • the fourth control circuit 114 by providing the fourth control circuit 114, the driving current generated by the first driving circuit 101 flowing through the first driving circuit 101 and from the first power supply voltage terminal VDD to the light emitting element 116 and the current generated by the second driving circuit 102 can be made
  • the electrical environment experienced by the second driving circuit 102 and the driving current from the first power supply voltage terminal VDD to the light-emitting element 116 is similar.
  • control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are configured to receive the same light emission control signal Therefore, the first control circuit 111, the second control circuit 112, the third control circuit 113, and the fourth control circuit 114 are turned on at the same time, and the first driving circuit 101 and the second driving circuit 102 can drive the light emitting element 116 synchronously.
  • control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are connected to the same light emission control terminal EM or light emission.
  • the control line (not shown in the figure) can simplify the structure of the display substrate including the pixel circuit 100.
  • the pixel circuit 100 provided by at least one embodiment of the present disclosure is not limited to include the second control circuit 112 and the fourth control circuit 114 at the same time; according to actual application requirements, the pixel circuit 100 provided by at least one embodiment of the present disclosure It is also possible to include only one of the second control circuit 112 and the fourth control circuit 114.
  • the embodiment shown in FIG. 3 exemplarily describes at least one embodiment of the present disclosure by taking the pixel circuit simultaneously having a compensation function, a reset function, and a light emission control function as an example, but at least one embodiment of the present disclosure is not limited to Therefore, for example, according to actual application requirements, the pixel circuit provided by at least one embodiment of the present disclosure may not have the above three functions, or have partial functions of the above three functions (that is, less than three functions), as long as the pixel
  • the circuit may have a first driving circuit and a second driving circuit connected in parallel.
  • FIG. 4A is an example of the pixel circuit 100 shown in FIG. 3, and FIG. 4B is a driving timing chart of the pixel circuit 100 shown in FIG. 4A.
  • the pixel circuit 100 shown in FIG. 3 will be exemplarily described below in conjunction with FIG. 4A and FIG. 4B.
  • the first driving circuit 101 includes a first transistor T1, the control terminal of the first transistor T1 is connected to the first node N1, the first terminal of the first transistor T1 is connected to the second node N2, and the first transistor T1 is connected to the second node N2.
  • the second terminal of a transistor T1 is connected to the third node N3;
  • the second driving circuit 102 includes a second transistor T2, and the control terminal of the second transistor T2 is connected to the first node N1.
  • the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 are equal.
  • the width and length of the channel of the first transistor T1 are substantially the same as the width and length of the channel of the second transistor T2, respectively.
  • the aspect ratio of the channel of the first transistor T1 (that is, the ratio of the channel width to the length) is substantially the same as the aspect ratio of the channel of the second transistor T2; the gate oxide layer of the first transistor T1
  • the capacitance of is substantially the same as the capacitance of the gate oxide of the second transistor T2; the mobility of carriers in the first transistor T1 is substantially the same as the mobility of carriers in the second transistor T2.
  • the value of the A parameter and the value of the B parameter are substantially equal to mean that the ratio of the difference between the value of the A parameter and the value of the B parameter to the value of the A parameter is less than 3% (for example, less than 1%).
  • the first transistor T1 and the second transistor T2 can be prepared in a symmetrical manner.
  • the data writing circuit 103 includes a third transistor T3, the signal storage circuit 104 includes a storage capacitor Cst; the first end of the third transistor T3 is connected to the second node N2; the third transistor T3 The two terminals are connected to the data signal terminal DAT to receive the data signal Vdata provided by the data signal terminal DAT; the first terminal of the storage capacitor Cst is connected to the first power supply voltage terminal VDD, and the second terminal of the storage capacitor Cst is connected to the first node N1 .
  • the compensation connection circuit 105 includes a fourth transistor T4; the first end of the fourth transistor T4 is connected to the first node N1, and the second end of the fourth transistor T4 is connected to the third node N3.
  • control terminal GAT1 of the third transistor T3 and the control terminal GAT2 of the fourth transistor T4 are both connected to the same scan signal terminal GAT or the same scan signal line (not shown in the figure).
  • the light emitting element 116 may be an organic light emitting element EL, and the organic light emitting element EL may be, for example, an organic light emitting diode, but the embodiment of the present disclosure is not limited thereto.
  • the light-emitting element 116 may be an inorganic light-emitting element.
  • the first reset circuit 106 includes a fifth transistor T5.
  • the control terminal of the fifth transistor T5 is configured as the first reset control terminal RST1, and the first terminal of the fifth transistor T5 is connected to the first node. N1, the second terminal of the fifth transistor T5 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init1;
  • the first control circuit 111 includes a sixth transistor T6, and the second control circuit 112 includes a seventh transistor T7; the first terminal of the sixth transistor T6 is connected to the first power supply voltage terminal VDD to receive The first power supply voltage, the second terminal of the sixth transistor T6 is connected to the second node N2; the first terminal of the seventh transistor T7 is connected to the first power supply voltage terminal VDD to receive the first power supply voltage, the second terminal of the seventh transistor T7 The two ends are connected to the first end of the second transistor T2.
  • the second reset circuit 115 includes an eighth transistor T8, the third control circuit 113 includes a ninth transistor T9, and the fourth control circuit 114 includes a tenth transistor T10; the control terminal of the eighth transistor T8 is Configured as the second reset control terminal RST2, the first terminal of the eighth transistor T8 is connected to the fourth node N4, and the second terminal of the eighth transistor T8 is connected to the second reset signal terminal Init2 to receive the second reset signal terminal Init2.
  • control terminal EM1 of the sixth transistor T6 the control terminal EM2 of the seventh transistor T7, the control terminal EM3 of the ninth transistor T9, and the control terminal EM4 of the tenth transistor T10 are connected to the same light-emitting control terminal EM or the same light-emitting control line ( Not shown in the figure).
  • the first transistor T1 to the tenth transistor T10 may all be P-type transistors (for example, PMOS transistors, that is, an n-type substrate, p-channel, MOS transistors that carry current through the flow of holes).
  • the first transistor T1-tenth transistor T10 is turned off when receiving a high level (first level), and turned on when receiving a low level (second level, the second level is less than the first level)
  • the high level (the first level) is the inactive level (that is, the level that makes the transistor turn off)
  • the low level (the second level) is the active level (that is, the transistor is turned on).
  • the level of the pass is the high level (the first level) is the inactive level (that is, the level that makes the transistor turn off), and the low level (the second level) is the active level (that is, the transistor is turned on).
  • first transistor T1-the tenth transistor T10 are not limited to all be implemented as P-type transistors. According to actual application requirements, one or more of the first transistor T1-the tenth transistor T10 can also be implemented as N-type transistors.
  • first node N1 to the fourth node N4 is intended to more conveniently describe the connection relationship between the components, and it is not necessary to provide, for example, solder joints or pads as actual nodes in the pixel circuit 100.
  • each driving cycle of the pixel circuit 100 shown in FIG. 4A includes a reset phase S_re, a data writing and compensation phase S_wc, and a light emitting phase S_EM.
  • the first reset control terminal RST1 receives the active level, and the scan signal terminal GAT (corresponding to the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3) ), the second reset control terminal RST2 and the light emission control terminal EM (corresponding to the control terminal EM1 of the fifth transistor CT5 and the control terminal EM2 of the seventh transistor CT7) receive an invalid level; in this case, the fifth transistor T5 is turned on, The third transistor T3, the fourth transistor T4, and the sixth transistor T6-the tenth transistor T10 are turned off; the fifth transistor T5 is configured to receive the first reset signal Vinit1 and write the first reset signal Vinit1 to the storage capacitor Cst to correct The storage capacitor Cst is reset; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value (for example, -3V). For example, after the first reset signal Vinit1 is written into the storage capacitor
  • the scan signal terminal GAT and the second reset control terminal RST2 receive the valid level
  • the first reset control terminal RST1 and the light-emitting control terminal EM receive the invalid level
  • the first transistor T1-the fourth transistor T4 and the eighth transistor T8 are turned on (the first transistor T1 and the second transistor T2 are turned on because of the first reset signal Vinit1 written to the storage capacitor Cst), and the fifth transistor T5-The seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned off; the third transistor T3 receives the data signal Vdata, and the data signal Vdata is written to the first transistor through the turned-on first transistor T1 and the fourth transistor T4 At the control terminal of T1, the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor T1 at the control terminal of the first transistor T1.
  • the voltage of the first node N1 is Vdata+Vth, where Vth is the first The threshold voltage of the transistor; the eighth transistor T8 is configured to receive the second reset signal Vinit2 and write the second reset signal Vinit2 to the first end of the organic light emitting element EL to reset the first end of the organic light emitting element EL.
  • the voltage of the four-node N4 is Vinit2, and Vinit2 is, for example, a negative value (for example, -3V).
  • the light-emitting control terminal EM receives the valid level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive the invalid level; in this case, the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned on, and the third transistor T3-the fifth transistor T5 and the eighth transistor T8 are turned off;
  • a transistor T1 is configured to control the flow through the first transistor T1 and from the first power supply voltage terminal VDD to the organic light emitting element EL based on the data signal Vdata stored in the storage capacitor Cst and the received first power supply voltage VDD.
  • the second transistor T2 is configured to control the flow through the second transistor T2 and from the first power supply voltage VDD based on the data signal Vdata stored in the storage capacitor Cst and the received first power supply voltage VDD.
  • the power supply voltage terminal VDD to the organic light emitting element EL is a driving current for driving the organic light emitting element EL; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD.
  • the inventors of the present disclosure performed simulation calculations on a display substrate including the pixel circuit 100 shown in FIG. 4A, and determined that the pixel circuit 100 shown in FIG. 4A can improve the organic light-emitting element driven by the pixel circuit 100 shown in FIG. 4A.
  • the brightness of the EL (compared to the pixel circuit 580 shown in FIG. 2A). The following is an illustrative description with a simulation example.
  • the display substrate includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B
  • each of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B includes FIG. 4A
  • the first power supply voltage VDD is 4.6V
  • the voltages Vdata of the data signals received by the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are 2.7V, 3.3V, and 2.28V, respectively.
  • the obtained voltage values of the first node N1-the fourth node N4 of the pixel circuit of each of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B and the value of the driving current Id can be referred to Table 1.
  • the ratio of the driving current of the red sub-pixel R including the pixel circuit 100 shown in FIG. 4B to the driving current of the red sub-pixel R including the pixel circuit 580 shown in FIG. 2A is 229.0%, including FIG. 4B
  • the ratio of the driving current of the green sub-pixel G of the pixel circuit 100 shown in FIG. 2A to the driving current of the green sub-pixel G including the pixel circuit 580 shown in FIG. 2A is 277.1%, including the blue color of the pixel circuit 100 shown in FIG. 4B
  • the ratio of the driving current of the sub-pixel B to the driving current of the blue sub-pixel B including the pixel circuit 580 shown in FIG. 2A is 252.2%, that is, for the above example, the driving current of the pixel circuit 100 is the driving current of the pixel circuit 580 At least 2.2 times the current.
  • the inventor of the present disclosure also found through simulation that by increasing (for example, from 6.5V to 7.0V) the voltage value of the data signal of the pixel circuit 100 (compared to the pixel circuit 580 shown in FIG. 2A), it is possible to make
  • the driving current of the pixel circuit 100 corresponds to the driving current of zero gray scale.
  • the drive current corresponding to zero gray scale is less than 1 picoamp (pA).
  • the eighth transistor T8 receives the invalid level, and in the reset phase S_re, the eighth transistor T8 receives the valid level, that is, the eighth transistor T8 resets the first end of the organic light-emitting element EL in the reset phase S_re, instead of resetting the first end of the organic light-emitting element EL in the data writing and compensation phase S_wc.
  • At least one embodiment of the present disclosure further provides a display substrate, which includes any pixel circuit provided in at least one embodiment of the present disclosure.
  • the display substrate may be an organic light emitting diode display panel.
  • FIG. 5A is an exemplary block diagram of a display substrate 10 provided by at least one embodiment of the present disclosure. As shown in FIG. 5A, the display substrate 10 includes at least one pixel circuit 100 provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a display side and a non-display side, and the displayed screen of the display substrate 10 is configured to be displayed on the display side of the display substrate 10, that is, the display side of the display substrate 10 is the light-emitting side of the display substrate 10.
  • the display side and the non-display side face each other in the normal direction of the display surface of the display substrate 10 (for example, a direction perpendicular to the display substrate 10).
  • FIG. 5B is a schematic cross-sectional view of the display substrate 10 shown in FIG. 5A.
  • the display substrate 10 includes a display layer 260 and a sensing layer 250, the sensing layer 250 is disposed on the non-display side of the display substrate 10;
  • the display layer 260 includes a display area 201, and the display area 201 includes a first The display area 210 and the second display area 220;
  • the sensing layer 250 includes a sensor 251, and the sensor 251 and the first display area 210 overlap in the normal direction of the display surface of the display substrate 10 and are configured to receive and process The light signal of the first display area 210.
  • the senor 251 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 251.
  • the sensor 251 can be used to implement a camera of the mobile terminal such as a mobile phone or a notebook.
  • the sensor 251 may include sensor pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching transistor).
  • the photodiode can convert the light signal irradiated on it into an electrical signal, and the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • FIG. 6 is a schematic plan view of an example of the display substrate 10 shown in FIG. 5B.
  • the display substrate 10 shown in FIG. 5B corresponds to the line AA' of the display substrate 10 shown in FIG. 6.
  • the display substrate 10 (for example, the display layer 260 of the display substrate 10) includes a display area 201 and a peripheral area 202 at least partially surrounding the display area 201; the display area 201 includes a first display area 210 and a second display area 210. Two display area 220.
  • the second display area 220 at least partially surrounds the first display area 210.
  • FIG. 7A is a schematic diagram of a partial area REG1 of the first display area 210 of the display substrate 10 shown in FIG. 6, and FIG. 8A is a schematic diagram of a partial area REG2 of the second display area 220 of the display substrate 10 shown in FIG. 6.
  • the first display area 210 includes a plurality of first pixel units 270 arranged in an array;
  • the second display area 220 includes a plurality of second pixel units 290 arranged in an array.
  • the multiple pixel units included in the display area 201 of the display substrate 10 may include pixel units of different colors (for example, red pixel units, green pixel units, and blue pixel units), and the light-emitting areas of light-emitting elements in the pixel units of different colors Can be the same or not exactly the same.
  • the light emitting area of the light emitting element in the red pixel unit, the light emitting area of the light emitting element in the green pixel unit, and the light emitting area of the light emitting element in the blue pixel unit are different from each other.
  • FIG. 8B shows an example of the first pixel unit 270 shown in FIG. 7A
  • FIG. 8C shows another example of the first pixel unit 270 shown in FIG. 7A
  • FIG. 8D shows the first pixel unit 270 shown in FIG. 8A.
  • each of the plurality of first pixel units 270 includes a light emitting element 301; each of the plurality of second pixel units 290 includes a second light emitting element 302.
  • both the light-emitting element 301 and the second light-emitting element 302 may be organic light-emitting elements, and the organic light-emitting elements may be, for example, organic light-emitting diodes, but the embodiments of the present disclosure are not limited thereto.
  • both the light-emitting element 301 and the second light-emitting element 302 may be inorganic light-emitting elements.
  • the light-emitting element 301 and the second light-emitting element 302 can achieve the same structure and performance characteristics.
  • the number of light emitting elements 301 included in each of the plurality of first pixel units 270 is equal to the number of second light emitting elements 302 included in each of the plurality of second pixel units 290 (for example, all are equal to one).
  • the light-emitting areas are different from each other.
  • the first color can be red, green, blue, or other suitable colors.
  • the distribution density per unit area of the plurality of first pixel units 270 in the first display area 210 is smaller than the distribution density per unit area of the plurality of second pixel units 290 in the second display area 220.
  • the distribution density per unit area of the plurality of light-emitting elements 301 in the first display area 210 is smaller than the distribution density per unit area of the plurality of second light-emitting elements 302 in the second display area 220.
  • the display area of the first display area 210 may be referred to as a low-resolution area of the display substrate 10.
  • the distance between two adjacent first pixel units 270 in the first direction D1 is greater than the size of the first pixel unit 270 in the first direction D1, and the distance between the adjacent first pixel units 270 in the second direction D2
  • the distance between the two first pixel units 270 is greater than or equal to the size of the first pixel unit 270 in the second direction D2.
  • the distance between two adjacent first pixel units 270 in the first direction D1 is equal to three times the size of the first pixel unit 270 in the first direction D1; two adjacent first pixel units 270 in the second direction D2
  • the pitch of one pixel unit 270 is equal to the size of the first pixel unit 270 in the second direction D2.
  • the pitch of two adjacent first pixel units 270 in the first direction D1 is in the range of 280-380 microns
  • the pitch of two adjacent first pixel units 270 in the second direction D2 is in the range of 100- Within the range of 160 microns
  • the size of the first pixel unit 270 in the first direction D1 and the second direction D2 is within the range of 110-130 microns.
  • the distance between two cells refers to the distance between the centers of the two cells.
  • the distance between two adjacent second pixel units 290 in the first direction D1 is smaller than the size of the second pixel unit 290 in the first direction D1, and the distance between two adjacent second pixel units 290 in the second direction D2
  • the distance between the two second pixel units 290 is smaller than the size of the second pixel unit 290 in the second direction D2.
  • the distance between two adjacent second pixel units 290 in the first direction D1 is less than one-fifth of the size of the second pixel unit 290 in the first direction D1.
  • the distance between two adjacent second pixel units 290 on D2 is less than one-fifth of the size of the second pixel unit 290 in the second direction D2.
  • the display substrate 10 includes a plurality of pixel circuits 100, and the plurality of pixel circuits 100 are electrically connected to the plurality of light-emitting elements 301 included in the plurality of first pixel units 270 in a one-to-one correspondence.
  • the display substrate 10 further includes a plurality of pixel circuits 580, and the plurality of pixel circuits 580 are electrically connected to the plurality of second light-emitting elements 302 included in the plurality of second pixel units 290 in a one-to-one correspondence.
  • each second pixel unit 290 includes a second light-emitting element 302 and a pixel circuit 580 for driving the second light-emitting element 302.
  • FIG. 8B is only used to show that the pixel unit 273 includes the light-emitting element 301 and the pixel circuit 100
  • FIG. 8C is only used to show that the pixel circuit 100 included in the pixel driving unit 281 and the light-emitting element 301 included in the pixel unit 274 are mutually connected.
  • the second pixel unit 290 includes the second light-emitting element 302 and the pixel circuit 580, and does not limit the specific shapes of the light-emitting element 301, the second light-emitting element 302, the pixel circuit 100, and the pixel circuit 580 As well as the relative positional relationship, the specific shapes and relative positional relationship of the light-emitting element 301, the second light-emitting element 302, the pixel circuit 100, and the pixel circuit 580 can be set according to actual application requirements.
  • the light-emitting elements of the plurality of first pixel units 270 can be improved. Therefore, the brightness of the first display area 210 including the plurality of first pixel units 270 of the display substrate 10 can be improved (that is, the brightness of the low-resolution area of the display substrate 10 can be improved).
  • the first display area 210 includes a first sub display area 211 and a second sub display area 212 that do not overlap each other.
  • the first sub-display area 211 at least partially surrounds (for example, completely surrounds) the second sub-display area 212.
  • the first sub-display area 211 includes a first group 271 of a plurality of first pixel units
  • the second sub-display area 212 includes a second group 272 of a plurality of first pixel units.
  • One group and the second group do not overlap each other.
  • the first group 271 of the plurality of first pixel units 270 includes a first number of first pixel units 270 (that is, a first number of pixel units 273)
  • the second group 272 includes a second number of first pixel cells 270 (ie, a second number of pixel cells 274).
  • the pixel unit 274 included in the second group 272 includes only the light-emitting element 301, and does not include the pixel circuit 100; as shown in FIGS. 8C and 7A, it is used to drive the light-emitting element 301 included in the pixel unit 274.
  • the pixel circuit 100 is provided in the pixel driving unit 281 included in the first sub-display area 211.
  • the pixel circuits 100 connected in a one-to-one correspondence with the light-emitting elements of the second group 272 of the plurality of first pixel units are arranged in the first sub-display area 211 (respectively arranged in the plurality of pixels included in the first sub-display area 211).
  • the pixel driving unit 281 does not include a light emitting element.
  • the pixel circuits 100 connected to the light-emitting elements of the second group 272 of the plurality of first pixel units in a one-to-one correspondence in the first sub-display area 211, it is not necessary to provide pixel circuits in the second sub-display area 212.
  • the transmittance of the second sub-display area 212 and the aperture ratio of the first pixel unit 270 included in the second sub-display area 212 can be improved; in this case, the sensor 251 and the second sub-display area 212 can be displayed
  • the substrate 10 is stacked in the normal direction of the display surface (see FIG.
  • the second sub display area 212 may be referred to as a high light transmission area of a low resolution area of the display substrate 10.
  • the display substrate 10 further includes a plurality of wires 213.
  • the multiple wirings 213 connect the light-emitting elements of the second group 272 of the multiple first pixel units and the pixel circuit 100 (pixel driving unit 281) in a one-to-one correspondence with the light-emitting elements of the second group 272 of the multiple first pixel units. Electric connection.
  • each of the above-mentioned multiple wires 213 may be implemented as a transparent wire, thereby further improving the transmittance of the second sub-display area 212 and the signal-to-noise ratio of the image output by the sensor 251.
  • the pixels connected to the light-emitting elements of the second group 272 of the plurality of first pixel units are not limited to being arranged in the first sub-display area 211.
  • the second sub-display area is not considered.
  • at least part of the pixels connected in a one-to-one correspondence with the light-emitting elements of the second group 272 of the plurality of first pixel units can also be provided in the second sub-display area 212.
  • the pixel unit 273 included in the first group 271 includes the light-emitting element 301 and the pixel circuit 100 at the same time.
  • the pixel circuits 100 connected to the light-emitting elements of the first group 271 of the plurality of first pixel units in a one-to-one correspondence are also arranged in the first sub-display area 211.
  • each first pixel unit 270 of the first group 271 of the plurality of first pixel units further includes a pixel circuit for driving a light-emitting element.
  • each first pixel unit 270 of the first group 271 of the plurality of first pixel units includes a pixel circuit and a light emitting element as shown in FIG. 4A.
  • the first sub-display area 211 may also include a redundant pixel unit 282. As shown in FIG. element.
  • the electrical environment of the first sub-display area 211 can be made uniform (for example, the load of the resistance and the capacitance can be made uniform).
  • the display substrate 10 may further include a plurality of scanning signal lines (for example, gate lines) and a plurality of data lines arranged to cross each other (for example, perpendicularly), and a plurality of voltage control lines arranged in parallel with the scanning signal lines.
  • each pixel circuit is connected to a corresponding scanning signal line and a corresponding data line.
  • the scanning signal terminal corresponding to each pixel circuit may be connected to the corresponding scanning signal line
  • the data signal terminal corresponding to each pixel circuit may be connected to the corresponding scanning signal line.
  • the first power supply voltage terminal and the second power supply voltage terminal corresponding to each pixel circuit can be connected to the corresponding voltage control line.
  • the plurality of scan signal lines respectively extend along the row direction of the display substrate 10 (for example, the first direction D1), and the plurality of scan data lines respectively have portions extending along the column direction of the display substrate 10 (for example, the second direction D2).
  • the first direction D1 and the second direction D2 cross (e.g., perpendicular).
  • the data line DL electrically connected to the pixel driving unit 281 for driving the light-emitting element is routed from the area between the first sub-display area 211 and the second sub-display area 212 to the first sub-display area.
  • the area 211, therefore, the data line DL further includes a portion extending in the first direction D1.
  • the peripheral area 202 includes a driving chip 230.
  • the driving chip 230 may include a data driver, and the data driver of the driving chip 230 may be bonded to the display substrate 10 via a flexible circuit board, and provide data signals for display to a plurality of data lines via the flexible circuit to drive the display substrate 10. Realize the display function.
  • the peripheral area 202 may also include gate drive integration (GOA, not shown in the figure) on the array substrate, and multiple output terminals of the GOA are respectively connected to multiple gate lines GL to provide gate scan signals to the multiple gate lines. .
  • GOA gate drive integration
  • FIG. 9 is a schematic plan view of another example of the display substrate 10 shown in FIG. 5B.
  • the display substrate 10 shown in FIG. 5B corresponds to the line AA' of the display substrate 10 shown in FIG. 9.
  • the display substrate 10 shown in FIG. 9 is similar to the display substrate 10 shown in FIG. 6. Therefore, only the differences between the display substrate 10 shown in FIG. 9 and the display substrate 10 shown in FIG. No longer.
  • the difference between the display substrate 10 shown in FIG. 9 and the display substrate 10 shown in FIG. 6 includes: the peripheral area 202 of the display substrate 10 shown in FIG.
  • the plurality of pixel circuits that are electrically connected are at least partially (for example, all) disposed in the pixel driving area 240; in this case, the first display area 210 of the display substrate 10 shown in FIG.
  • the size of the first display area 210 can be reduced, that is, the low-resolution of the display substrate 10 can be reduced.
  • the size of the area can thereby improve the quality of the image displayed on the display substrate 10.
  • the second display area 220 surrounds the first display area 210.
  • the pixel driving area 240 and the first display area 210 are arranged side by side in the row direction of the display substrate 10 (for example, corresponding to the first direction D1 of FIGS. 7A and 8A), and the pixel driving area 240 and The first display area 210 is separated by the second display area 220.
  • the multiple wires 213 respectively extend along the row direction of the display substrate 10.
  • the pixel driving area 240 and the first display area 210 are not limited to being arranged side by side in the row direction of the display substrate 10. According to actual application requirements, as shown in FIG. 10, the pixel driving area 240 and the first display area 210 may be arranged in a row.
  • the display substrate 10 is arranged side by side in the column direction (for example, corresponding to the second direction D2 in FIGS. 7A and 8A ). In this case, a plurality of wires 213 respectively extend along the column direction of the display substrate 10.
  • an additional pair of The data signal of the pixel circuit 100 in the first display area 210 is compensated.
  • a timing controller may be used to compensate the data signal provided to the pixel circuit 100 of the first display area 210.
  • the shape of the first display area 210 is a circle, but the embodiment of the present disclosure is not limited thereto. According to actual application requirements, the shape of the first display area 210 may also be implemented as a rectangle or other suitable shapes.
  • At least one embodiment of the present disclosure further provides a display device, which includes any pixel circuit or any display substrate provided in at least one embodiment of the present disclosure.
  • FIG. 11 is an exemplary block diagram of a display device 20 provided by at least one embodiment of the present disclosure. As shown in FIG. 11, the display device 20 includes any pixel circuit 100 or any display substrate 10 provided by at least one embodiment of the present disclosure.
  • the display substrate and the display device can improve the brightness (for example, the overall brightness) of the low-resolution region (that is, the first display region) of the display substrate and the display device.

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Abstract

一种像素电路（100）、显示基板（10）和显示装置（20），像素电路（100）包括第一驱动电路（101）、第二驱动电路（102）、数据写入电路（103）和信号存储电路（104）；数据写入电路（103）被配置为接收数据信号；第一驱动电路（101）与数据写入电路（103）连接，被配置为从数据写入电路（103）接收数据信号且允许数据信号被写入至第一驱动电路（101）的控制端；第二驱动电路（102）的控制端被配置为接收被写入至第一驱动电路（101）的控制端的数据信号；信号存储电路（104）被配置为在第一驱动电路（101）的控制端存储被写入至第一驱动电路（101）的控制端的数据信号；第一驱动电路（101）的第一端和第二驱动电路（102）的第一端均被配置为从第一电源电压端（VDD）接收第一电源电压，第一驱动电路（101）的第二端和第二驱动电路（102）的第二端均被配置为电连接到发光元件（116）的第一端；第一驱动电路（101）和第二驱动电路（102）被配置为，基于存储在信号存储电路（104）中的数据信号以及所接收的第一电源电压，控制分别流经第一驱动电路（101）和第二驱动电路（102）且从第一电源电压端（VDD）至发光元件（116）、用于驱动发光元件（116）的驱动电流；可以提升与像素电路（100）电连接的发光元件（116）的亮度。

Description

像素电路、显示基板和显示装置 技术领域
本公开的实施例涉及一种像素电路、显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快等特点。并且，相比于无机发光显示器件，有机发光二极管显示器件具有更高的发光亮度、更低的驱动电压等优势。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的至少一个实施例提供了一种像素电路，其包括：第一驱动电路、第二驱动电路、数据写入电路和信号存储电路。所述数据写入电路被配置为接收数据信号；所述第一驱动电路与所述数据写入电路连接，被配置为从所述数据写入电路接收所述数据信号且允许所述数据信号被写入至所述第一驱动电路的控制端；所述第二驱动电路的控制端被配置为接收被写入至所述第一驱动电路的控制端的所述数据信号；所述信号存储电路被配置为在所述第一驱动电路的控制端存储被写入至所述第一驱动电路的控制端的所述数据信号；所述第一驱动电路的第一端和所述第二驱动电路的第一端均被配置为从第一电源电压端接收第一电源电压，所述第一驱动电路的第二端和所述第二驱动电路的第二端均被配置为电连接到发光元件的第一端；以及所述第一驱动电路和所述第二驱动电路被配置为，基于存储在所述信号存储电路中的所述数据信号以及所接收的所述第一电源电压，控制分别流经所述第一驱动电路和所述第二驱动电路且从所述第一电源电压端至所述发光元件、用于驱动所述发光元件的驱动电流。
例如，在所述像素电路的至少一个示例中，所述第一驱动电路的控制端和所述第二驱动电路的控制端彼此电连接。
例如，在所述像素电路的至少一个示例中，所述像素电路还包括补偿连接电路。所述数据写入电路将所述数据信号写入至所述第一驱动电路的第一端；以及所述补偿连接电路连接在所述第一驱动电路的第二端和所述第一驱动电路的控制端之间，并且被配置为将被写入至所述第一驱动电路的第一端的数据信号经由所述第一驱动电路写入至所述第一驱动电路的控制端。
例如，在所述像素电路的至少一个示例中，所述补偿连接电路的控制端和所述数据写入电路的控制端连接至同一扫描信号线。
例如，在所述像素电路的至少一个示例中，所述像素电路还包括第一复位电路。所述第一复位电路与所述信号存储电路相连；以及所述第一复位电路被配置接收第一复位信号，且将所述第一复位信号写入至所述信号存储电路，以对所述信号存储电路复位。
例如，在所述像素电路的至少一个示例中，所述像素电路还包括第一控制电路和第二控制电路。所述第一控制电路连接在所述第一驱动电路的第一端和所述第一电源电压端之间，且被配置为控制所述第一驱动电路是否与所述第一电源端电连接；以及所述第二控制电路连接在所述第二驱动电路的第一端和所述第一电源电压端之间，且被配置为控制所述第二驱动电路是否与所述第一电源端电连接。
例如，在所述像素电路的至少一个示例中，所述第一控制电路的控制端和所述第二控制电路的控制端连接至同一发光控制线。
例如，在所述像素电路的至少一个示例中，所述像素电路还包括第二复位电路。所述第二复位电路被配置为接收第二复位信号，且将所述第二复位信号写入至所述发光元件的第一端，以对所述发光元件的第一端复位。
例如，在所述像素电路的至少一个示例中，所述像素电路还包括第三控制电路和第四控制电路。所述第三控制电路连接在所述第一驱动电路的第二端与所述发光元件的第一端之间，且被配置为控制所述第一驱动电路是否与所述发光元件的第一端电连接；以及所述第四控制电路连接在所述第二驱动电路的第二端与所述发光元件的第一端之间，且被配置为控制所述第二驱动电路是否与所述发光元件的第一端电连接。
例如，在所述像素电路的至少一个示例中，所述第三控制电路的控制端和所述第四控制电路的控制端连接至同一发光控制线。
例如，在所述像素电路的至少一个示例中，所述第一驱动电路包括第一 晶体管，所述第二驱动电路包括第二晶体管；以及所述第一晶体管的阈值电压和所述第二晶体管的阈值电压相等。
本公开的至少一个实施例还提供了一种显示基板，其包括本公开的至少一个实施例提供的任一像素电路。
例如，在所述显示基板的至少一个示例中，所述至少一个像素电路包括多个像素电路；所述显示基板具有显示区域，所述显示区域包括第一显示区域和第二显示区域；所述第一显示区域包括阵列排布的多个第一像素单元，所述第二显示区域包括阵列排布的多个第二像素单元；所述第一显示区域中所述多个第一像素单元的单位面积分布密度小于所述第二显示区域中所述多个第二像素单元的单位面积分布密度；所述多个第一像素单元的每个包括所述发光元件；以及所述多个像素电路与所述多个发光元件一一对应电连接。
例如，在所述显示基板的至少一个示例中，所述第一显示区域还包互不重叠的第一子显示区域和第二子显示区域；所述第一子显示区域包括所述多个第一像素单元的第一组，所述第二子显示区域包括所述多个第一像素单元的第二组，所述第一组和第二组彼此互不重叠；以及与所述多个第一像素单元的第二组的发光元件一一对应连接的像素电路设置在所述第一子显示区域中。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括多条透明走线。所述多条透明走线将所述多个第一像素单元的第二组的发光元件和与所述多个第一像素单元的第二组的发光元件一一对应连接的像素电路电连接。
例如，在所述显示基板的至少一个示例中，所述显示基板还具有至少部分围绕所述显示区域的周边区域，所述多个像素电路至少部分设置于所述周边区域中。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括传感器。所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一像素电路或任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种显示基板的截面示意图；
图1B是图1A所示的显示基板的平面示意图；
图1C是图1B所示的显示基板的部分区域的示意图；
图2A为一种7T1C像素电路的结构示意图；
图2B为图2A所示的7T1C像素电路的驱动时序图；
图3是本公开的至少一个实施例提供的像素电路的示意图；
图4A是图3所示的像素电路的一个示例；
图4B是图4A所示的像素电路的驱动时序图；
图5A是本公开的至少一个实施例提供的显示基板的示例性框图；
图5B是图5A所示的显示基板的截面示意图；
图6是图5B所示的显示基板的一个示例的平面示意图；
图7A是图6所示的显示基板的第一显示区域的部分区域的示意图；
图7B示出了图7A所示的多个第一像素单元的第一组的示意图；
图7C示出了图7A所示的多个第一像素单元的第二组的示意图；
图8A是图6所示的显示基板的第二显示区域的部分区域的示意图；
图8B示出了图7A所示的第一像素单元的一个示例；
图8C示出了图7A所示的第一像素单元的另一个示例；
图8D示出了图8A所示的第二像素单元的示意图；
图8E示出了图7A所示的冗余像素单元的示意图；
图9是图5B所示的显示基板的另一个示例的平面示意图；
图10是图5B所示的显示基板的再一个示例的平面示意图；以及
图11是本公开的至少一个实施例提供的显示装置的示例性框图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人注意到，当前的具有屏下传感器(摄像头)的显示基板的对应于屏下传感器(摄像头)的显示区域的发光亮度较低，由此影响了显示基板显示的图像的质量。下面结合图1A、图1B、图2A和图2B进行示例性说明。
图1A是一种显示基板500的截面示意图，图1B是图1A所示的显示基板500的平面示意图，图1C是图1B所示的显示基板500的部分区域513的示意图。图1B所示的显示基板500对应于图1A所示的显示基板10的BB’线。
如图1A所示，该显示基板500包括显示层510和感测层520，感测层520设置在显示基板500的非显示侧。如图1A-图1C所示，显示层510包括第一显示区域511和第二显示区域512；第一显示区域511包括阵列排布的多个第一发光元件531，第二显示区域512包括阵列排布的多个第二发光元件532。例如，多个第一发光元件531和多个第二发光元件532具有相同的结构和性能特性。
如图1A所示，感测层520包括传感器521，传感器521与第一显示区域511在显示基板500的显示面的法线方向上叠置，且被配置为接收并处理穿过第一显示区域511的光信号。
如图1C所示，为了减小第一显示区域511中的元件对入射至第一显示区域511并朝向传感器521传输的光信号的遮挡，第一显示区域511中多个 第一发光元件531的单位面积分布密度小于第二显示区域512中多个第二发光元件532的单位面积分布密度。然而，这使得第一显示区域511的有效发光面积小于第二显示区域512的有效发光面积，并使得显示基板500显示的图像中对应于第一显示区域511的图像区域的亮度与对应于第二显示区域512的图像区域的亮度差距相对较大。
例如，显示层510还包括多个第一像素电路和多个第二像素电路(图1A-图1C未示出，参见图2A)；多个第一像素电路被配置为一一对应的驱动多个第一发光元件531，多第二像素电路被配置为一一对应的驱动多个第二发光元件532。例如，多个第一像素电路和多个第二像素电路具有相同的电路结构。
例如，在驱动多个第一发光元件的多个第一像素电路接收的数据信号(例如，数据电压)等于驱动多个第二发光元件的多个第二像素电路接收的数据信号(例如，数据电压)的情况下，多个第一发光元件的发光亮度小于多个第二发光元件的发光亮度，并因此使得显示基板显示的图像中对应于第一显示区域511的图像区域的亮度可能低于预定亮度。
多个第一像素电路和多个第二像素电路的电路结构可以根据实际应用需求进行设定。例如，多个第一像素电路和多个第二像素电路的每个可以实现为2T1C像素电路、3T1C像素电路、5T1C像素电路7T1C像素电路或其它适用的像素电路。需要说明的是，2T1C像素电路为包括两个晶体管和一个存储电容Cst的像素电路，7T1C像素电路为包括七个晶体管和一个存储电容Cst的像素电路。
下面以多个第一像素电路和多个第二像素电路的每个实现为7T1C像素电路580对图1A和图1B所示的显示基板500做示例性说明。
图2A为一种7T1C像素电路580的结构示意图。如图2A所示，该7T1C像素电路580包括第一晶体管CT1、第二晶体管CT2、第三晶体管CT3、第四晶体管CT4、第五晶体管CT5、第六晶体管CT6、第七晶体管CT7和存储电容Cst。例如，第一晶体管CT1-第七晶体管CT7均为P型晶体管。
如图2A所示，存储电容Cst的第一端与第一电源电压端VDD相连，以接收第一电源电压V1；存储电容Cst的第二端与第一节点N1相连；发光元件EL的第一端与第四节点N4相连，发光元件EL的第二端与第二电源电压端VSS相连，以接收第二电源电压V2；第一晶体管CT1的控制端与第一节 点N1相连；第一晶体管CT1的第一端与第二节点N2相连，第一晶体管CT1的第二端与第三节点N3相连；第二晶体管CT2的第一端与第二节点N2相连，第二晶体管CT2的第二端与数据信号端DAT相连，以接收数据信号(例如，数据电压)Vdata；第三晶体管CT3的第一端与第一节点N1相连，第三晶体管CT3的第二端与第三节点N3相连；第四晶体管CT4的第一端与第一节点N1相连；第四晶体管CT4的第二端与第一复位信号端Init1相连，以接收第一复位信号端Init1提供的第一复位信号Vinit1；第五晶体管CT5的第一端与第一电源电压端VDD相连，第五晶体管CT5的第一端与第二节点N2相连；第六晶体管CT6的第一端与第四节点N4相连；第六晶体管CT6的第二端与第二复位信号端Init2相连，以接收第二复位信号Vinit2；第七晶体管CT7的第一端与第三节点N3相连，第七晶体管CT7的第二端与第四节点N4相连。例如，第二晶体管CT2的控制端GAT1和第三晶体管CT3的控制端GAT2均连接至扫描信号端GAT(图中未示出)；第五晶体管CT5的控制端EM1和第七晶体管CT7的控制端EM2均连接至发光控制端EM(图中未示出)；第四晶体管CT4的控制端被配置为第一复位控制端RST1；第六晶体管CT6的控制端被配置为第二复位控制端RST2。
为描述方便，图2A还示出了第一节点N1、第二节点N2、第三节点N3、第四节点N4和发光元件EL。
图2B为图2A所示的7T1C像素电路580的驱动时序图。如图2B所示，该7T1C像素电路580的每个驱动周期包括第一阶段t1、第二阶段t2和第三阶段t3。
如图2A和图2B所示，在第一阶段t1中，第一复位控制端RST1接收有效电平，扫描信号端GAT、第二复位控制端RST2和发光控制端EM均接收无效电平；此种情况下，第四晶体管CT4开启，第二晶体管CT2、第三晶体管CT3、第五晶体管CT5、第六晶体管CT6和第七晶体管CT7关闭；第四晶体管CT4被配置接收第一复位信号(例如，复位电压)Vinit1，且将第一复位信号Vinit1写入至存储电容Cst，以对存储电容Cst复位；第一节点N1的电压为Vinit1，Vinit1例如为负值。例如，在对存储电容Cst复位之后，第一晶体管CT1开启.
如图2A和图2B所示，在第二阶段t2中，扫描信号端GAT和第二复位控制端RST2接收有效电平，第一复位控制端RST1和发光控制端EM接收 无效电平；此种情况下，第一晶体管CT1-第三晶体管CT3以及第六晶体管CT6开启，第四晶体管CT4、第五晶体管CT5和第七晶体管CT7关闭；第二晶体管CT2接收数据信号Vdata，且数据信号Vdata经由开启的第一晶体管CT1和第三晶体管CT3被写入至第一晶体管CT1的控制端，存储电容Cst在第一晶体管CT1的控制端存储被写入至第一晶体管CT1的控制端的数据信号Vdata，第一节点N1的电压为Vdata+Vth；第六晶体管CT6被配置接收第二复位信号(例如，复位电压)Vinit2，且将第二复位信号Vinit2写入至发光元件EL的第一端，以对发光元件EL的第一端复位，第四节点N4的电压为Vinit2，Vinit2例如为负值。
如图2A和图2B所示，在第三阶段t3中，发光控制端EM接收有效电平，第一复位控制端RST1、扫描信号端GAT和第二复位控制端RST2接收无效电平；此种情况下，第一晶体管CT1、第五晶体管CT5和第七晶体管CT7开启，第二晶体管CT2、第三晶体管CT3、第四晶体管CT4和第六晶体管CT6关闭；第一晶体管CT1被配置为，基于存储在存储电容Cst中的数据信号(例如，数据电压)Vdata以及所接收的第一电源电压V1，控制流经第一晶体管CT1且从第一电源电压端VDD至发光元件EL、用于驱动发光元件EL的驱动电流；第一节点N1的电压为Vdata+Vth，第二节点N2的电压为VDD；驱动电流Id可以由以下的公式表示。
Figure PCTCN2020073996-appb-000001
此处，k＝μ×Cox×W/L；μ为第一晶体管CT1中载流子的迁移率，Cox为第一晶体管CT1的栅氧化层的电容，W/L为第一晶体管CT1的沟道的宽长比，Vth为第一晶体管CT1的阈值电压，Vth为第一晶体管CT1的栅源电压，Vg为第一晶体管CT1的栅极电压，Vs为第一晶体管CT1的源极电压。
由上述公式可知，第一晶体管CT1生成的驱动电流Id与第一晶体管CT1的阈值电压无关，因此，图2A和图2B所示的7T1C像素电路580具有阈值补偿功能。
本公开的至少一个实施例提供了一种像素电路、显示基板和显示装置。该像素电路包括：第一驱动电路、第二驱动电路、数据写入电路和信号存储电路。数据写入电路被配置为接收数据信号；第一驱动电路与数据写入电路连接，被配置为从数据写入电路接收数据信号且允许数据信号被写入至第一驱动电路的控制端；第二驱动电路的控制端被配置为接收被写入至第一驱动电路的控制端的数据信号；信号存储电路被配置为在第一驱动电路的控制端存储被写入至第一驱动电路的控制端的数据信号；第一驱动电路的第一端和第二驱动电路的第一端均被配置为从第一电源电压端接收第一电源电压，第一驱动电路的第二端和第二驱动电路的第二端均被配置为电连接到发光元件的第一端；以及第一驱动电路和第二驱动电路被配置为，基于存储在信号存储电路中的数据信号以及所接收的第一电源电压，控制分别流经第一驱动电路和第二驱动电路且从第一电源电压端至发光元件、用于驱动发光元件的驱动电流。
例如，通过设置与第一驱动电路并联的第二驱动电路，该像素电路可以提升流经与该像素电路电连接的发光元件的驱动电流的值以及与该像素电路电连接的发光元件的亮度。
下面通过几个示例或实施例对根据本公开的至少一个实施例提供的像素电路进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例或实施例中不同特征可以相互组合，从而得到新的示例或实施例，这些新的示例或实施例也都属于本公开保护的范围。
图3是本公开的至少一个实施例提供的像素电路100的示意图。如图3所示，该像素电路100包括第一驱动电路101、第二驱动电路102、数据写入电路103和信号存储电路104。
如图3所示，数据写入电路103被配置为接收数据信号，例如，数据写入电路103被配置为与数据信号端DAT相连，以接收数据信号端DAT提供的数据信号。例如，数据信号为电压信号。
如图3所示，第一驱动电路101与数据写入电路103连接，被配置为从数据写入电路103接收数据信号且允许数据信号被写入至第一驱动电路101的控制端；第二驱动电路102的控制端被配置为接收被写入至第一驱动电路101的控制端的数据信号；
如图3所示，信号存储电路104被配置为在第一驱动电路101的控制端 存储被写入至第一驱动电路101的控制端的数据信号。例如，信号存储电路104连接在第一电源电压端VDD和第一驱动电路101的控制端之间。
如图3所示，第一驱动电路101的第一端和第二驱动电路102的第一端均被配置为从第一电源电压端VDD接收第一电源电压，第一驱动电路101的第二端和第二驱动电路102的第二端均被配置为电连接到发光元件116的第一端；第一驱动电路101和第二驱动电路102被配置为，基于存储在信号存储电路104中的数据信号以及所接收的第一电源电压，控制分别流经第一驱动电路101和第二驱动电路102且从第一电源电压端VDD至发光元件116、用于驱动发光元件116的驱动电流。
例如，通过设置与第一驱动电路101并联的第二驱动电路102，在像素电路100的发光阶段，第一驱动电路101和第二驱动电路102分别生成流经第一驱动电路101和第二驱动电路102且从第一电源电压端VDD至发光元件116、用于驱动发光元件116的驱动电流，由此该像素电路100可以提升流经与该像素电路100电连接的发光元件116的驱动电流的值以及与该像素电路100电连接的发光元件116的亮度。
例如，本公开的至少一个实施例可以通过在图2A所示的像素电路100的基础上并联一个简单的第一驱动电路101即可提升与该像素电路100电连接的发光元件116的亮度，由此可以在使得像素电路100的结构尽可能的简单的情况下，提升与该像素电路100电连接的发光元件116的亮度。
例如，如图3所示，第一驱动电路101的控制端和第二驱动电路102的控制端彼此电连接，由此使得第二驱动电路102的控制端可以接收被写入至第一驱动电路101的控制端的数据信号。例如，第一驱动电路101的控制端和第二驱动电路102的控制端直接相连。
例如，如图3所示，像素电路100还包括补偿连接电路105。例如，数据写入电路103将数据信号写入至第一驱动电路101的第一端；补偿连接电路105连接在第一驱动电路101的第二端和第一驱动电路101的控制端之间，并且被配置为将被写入至第一驱动电路101的第一端的数据信号经由第一驱动电路101写入至第一驱动电路101的控制端。
例如，通过使得补偿连接电路105被配置为将被写入至第一驱动电路101的第一端的数据信号经由第一驱动电路101写入至第一驱动电路101的控制端，可以将第一驱动电路101的阈值特性写入第一驱动电路101的控制端， 并存储在信号存储电路104中，由此可以消除第一驱动电路101的阈值特性对第一驱动电路101生成的流经第一驱动电路101且从第一电源电压端VDD至发光元件116、用于驱动发光元件116的驱动电流的不利影响，也即，通过设置补偿连接电路105，可以使得本公开的至少一个实施例提供的像素电路100具有阈值补偿功能。
例如，第一驱动电路101的阈值特性和第二驱动电路102的阈值特性相近，由此使得补偿连接电路105还可以减轻第二驱动电路102的阈值特性对第二驱动电路102生成的流经第二驱动电路102且从第一电源电压端VDD至发光元件116的驱动电流的不利影响。例如，第一驱动电路101的阈值特性和第二驱动电路102的阈值特性相近是指第一驱动电路101的阈值和第二驱动电路102的阈值的差值与第一驱动电路101的阈值的比值小于10％(例如，小于5％、3％或1％)。
例如，第一驱动电路101和第二驱动电路102具有相同阈值特性；此种情况下，补偿连接电路105还可以消除第二驱动电路102的阈值特性对第二驱动电路102生成的流经第二驱动电路102且从第一电源电压端VDD至发光元件116的驱动电流的不利影响，由此可以进一步地提升本公开的至少一个实施例提供的像素电路100的阈值补偿功能。
例如，如图3所示，数据写入电路103的控制端GAT1和补偿连接电路105的控制端GAT2被配置为接收相同的扫描信号，由此使得被写入至第一驱动电路101的第一端的数据信号可以在像素电路100的数据写入阶段，经由开启第一驱动电路101和补偿连接电路105写入至第一驱动电路101的控制端，此种情况下，数据写入阶段也被称为像素电路100的数据写入和补偿阶段。例如，补偿连接电路105的控制端和数据写入电路103的控制端连接至同一扫描信号端GAT或扫描信号线(图中未示出)，由此可以简化包括该像素电路100的显示基板的结构。
例如，如图3所示，像素电路100还包括第一复位电路106。第一复位电路106与信号存储电路104相连；第一复位电路106被配置接收第一复位信号，且将第一复位信号写入至信号存储电路104，以对信号存储电路104复位。例如，第一复位信号可以为第一复位电压。例如，该第一复位电压为负值(例如，-3V)，以使得在存在工艺偏差的情况下，在对存储电路复位之后，第一驱动电路101依然能够开启。例如，第一复位电路106可以在像素电路100 的复位阶段对信号存储电路104复位。
例如，第一复位电路106的第一端与信号存储电路104相连；第一复位电路106的第二端与第一复位信号端Init1相连，以接收第一复位信号端Init1提供的第一复位信号；第一复位电路106的控制端被配置为第一复位控制端RST1。
例如，如图3所示，像素电路100还包括第一控制电路111；第一控制电路111连接在第一驱动电路101的第一端和第一电源电压端VDD之间，且被配置为控制第一驱动电路101是否与第一电源电压端VDD电连接。例如，通过设置第一控制电路111，可以避免第一电源电压端VDD提供的第一电源电压在数据写入和补偿阶段对写入至第一驱动电路101第一端的数据信号产生不利影响。
例如，如图3所示，像素电路100还包括第二复位电路115。第二复位电路115被配置为接收第二复位信号，且将第二复位信号写入至发光元件116的第一端，以对发光元件116的第一端复位。例如，第二复位电路115的第一端与发光元件116的第一端相连；第二复位电路115的第二端与第二复位信号端Init2相连，以接收第二复位信号端Init2提供的第二复位信号；第二复位电路115的控制端被配置为第二复位控制端RST2。
例如，第二复位电路115被配置为消除发光元件116上可能残留的电荷。例如，可以在发光阶段之前对发光元件116的第一端复位，以提升发光元件116的亮度的准确性以及包括该像素电路100的显示基板的对比度。例如，可以在像素电路100的数据写入和补偿阶段或者复位阶段对发光元件116的第一端复位。
例如，第二复位信号可以为第二复位电压。例如，发光元件116的第二端与第二电源电压端VSS相连，以接收第二电源电压端VSS提供的第二电源电压。例如，第二复位电压等于第二电源电压，以避免在对发光元件116的第一端复位的过程中，发光元件116发光。例如，第二复位电压和第二电源电压均为负值(例如，-3V)。例如，第二电源电压小于第一电源电压。
例如，像素电路100还包括第三控制电路113。第三控制电路113连接在第一驱动电路101的第二端与发光元件116的第一端之间，且被配置为控制第一驱动电路101是否与发光元件116的第一端电连接。例如，通过设置第三控制电路113，可以在数据写入和补偿阶段避免第一驱动电路101第二端的 电压与发光元件116的第一端的电压相互干扰。例如，通过设置第三控制电路113，在数据写入和补偿阶段，可以避免第一驱动电路101第二端的电压对发光元件116的第一端的复位产生不利影响以及避免发光元件116发光。又例如，通过设置第三控制电路113，在数据写入和补偿阶段，可以避免发光元件116的第一端的电压对第一驱动电路101第二端的电压以及阈值补偿产生不利影响。
例如，如图3所示，像素电路100还包括第二控制电路112；第二控制电路112连接在第二驱动电路102的第一端和第一电源电压端VDD之间，且被配置为控制第二驱动电路102是否与第一电源电压端VDD电连接。例如，通过设置第二控制电路112，可以避免第二驱动电路102在发光阶段之外的阶段驱动发光元件116发光。
例如，如图3所示，像素电路100还包括第四控制电路114；第四控制电路114连接在第二驱动电路102的第二端与发光元件116的第一端之间，且被配置为控制第二驱动电路102是否与发光元件116的第一端电连接。例如，通过设置第四控制电路114，可以使得第一驱动电路101生成的流经第一驱动电路101且从第一电源电压端VDD至发光元件116的驱动电流以及第二驱动电路102生成的流经第二驱动电路102且从第一电源电压端VDD至发光元件116的驱动电流所经历的电学环境相似。
例如，第一控制电路111的控制端EM1、第二控制电路112的控制端EM2、第三控制电路113的控制端EM3和第四控制电路114的控制端EM4被配置为接收相同的发光控制信号，由此使得第一控制电路111、第二控制电路112、第三控制电路113和第四控制电路114同时开启，并使得第一驱动电路101和第二驱动电路102可以同步驱动发光元件116。
例如，第一控制电路111的控制端EM1、第二控制电路112的控制端EM2、第三控制电路113的控制端EM3和第四控制电路114的控制端EM4连接至同一发光控制端EM或发光控制线(图中未示出)，由此可以简化包括该像素电路100的显示基板的结构。
需要说明的是，本公开的至少一个实施例提供的像素电路100不限于包括同时第二控制电路112和第四控制电路114；根据实际应用需求，本公开的至少一个实施例提供的像素电路100还可以仅包括第二控制电路112和第四控制电路114的一个。
需要说明的是，图3所示的实施例以像素电路同时具有补偿功能、复位功能和发光控制功能为例对本公开的至少一个实施例进行示例性说明，但本公开的至少一个实施例不限于此，例如，根据实际应用需求，本公开的至少一个实施例提供的像素电路可以不具有上述三个功能，或者具有上述三个功能的部分功能(也即，少于三个功能)，只要像素电路具有并联的第一驱动电路和第二驱动电路即可。
图4A是图3所示的像素电路100的一个示例，图4B是图4A所示的像素电路100的驱动时序图。下面结合图4A和图4B对图3所示的像素电路100做示例性说明。
如图3和图4A所示，第一驱动电路101包括第一晶体管T1，第一晶体管T1的控制端连接至第一节点N1，第一晶体管T1的第一端连接至第二节点N2，第一晶体管T1的第二端连接至第三节点N3；第二驱动电路102包括第二晶体管T2，第二晶体管T2的控制端连接至第一节点N1。
例如，第一晶体管T1的阈值电压和第二晶体管T2的阈值电压相等。例如，第一晶体管T1的沟道的宽度和长度分别与第二晶体管T2的沟道的宽度和长度实质上相同。例如，第一晶体管T1的沟道的宽长比(也即，沟道的宽度和长度的比值)与第二晶体管T2的沟道的宽长比实质上相同；第一晶体管T1的栅氧化层的电容与第二晶体管T2的栅氧化层的电容实质上相同；第一晶体管T1中载流子的迁移率与第二晶体管T2中载流子的迁移率实质上相同。在一些示例中，A参数的值和B参数的值实质上相等是指：A参数的值和B参数的值的差值与A参数的值的比值小于3％(例如，小于1％)。例如，可以采用对称的方式制备第一晶体管T1和第二晶体管T2。
如图3和图4A所示，数据写入电路103包括第三晶体管T3，信号存储电路104包括存储电容Cst；第三晶体管T3的第一端连接至第二节点N2；第三晶体管T3的第二端连接至数据信号端DAT，以接收数据信号端DAT提供的数据信号Vdata；存储电容Cst的第一端连接至第一电源电压端VDD，存储电容Cst的第二端连接至第一节点N1。
如图3和图4A所示，补偿连接电路105包括第四晶体管T4；第四晶体管T4的第一端连接至第一节点N1，第四晶体管T4的第二端连接至第三节点N3。
例如，第三晶体管T3的控制端GAT1和第四晶体管T4的控制端GAT2 均连接至同一扫描信号端GAT或同一扫描信号线(图中未示出)。
例如，如图3和图4A所示，发光元件116可以是有机发光元件EL，有机发光元件EL例如可以为有机发光二极管，但本公开的实施例不限于此。例如，该发光元件116可以为无机发光元件。
如图3和图4A所示，第一复位电路106包括第五晶体管T5，第五晶体管T5的控制端被配置为第一复位控制端RST1，第五晶体管T5的第一端连接至第一节点N1，第五晶体管T5的第二端连接至第一复位信号端Init1，以接收第一复位信号端Init1提供的第一复位信号Vinit1；
如图3和图4A所示，第一控制电路111包括第六晶体管T6，第二控制电路112包括第七晶体管T7；第六晶体管T6的第一端连接至第一电源电压端VDD，以接收第一电源电压，第六晶体管T6的第二端连接至第二节点N2；第七晶体管T7的第一端连接至第一电源电压端VDD，以接收第一电源电压，第七晶体管T7的第二端连接至第二晶体管T2的第一端。
如图3和图4A所示，第二复位电路115包括第八晶体管T8，第三控制电路113包括第九晶体管T9，第四控制电路114包括第十晶体管T10；第八晶体管T8的控制端被配置为第二复位控制端RST2，第八晶体管T8的第一端连接至第四节点N4，第八晶体管T8的第二端连接至第二复位信号端Init2，以接收第二复位信号端Init2提供的第二复位信号Vinit2；第九晶体管T9的第一端连接至第三节点N3，第九晶体管T9的第二端连接至第四节点N4；第十晶体管T10的第一端连接至第二晶体管T2的第二端，第十晶体管T10的第二端连接至第四节点N4；有机发光元件EL的第一端连接至第四节点N4，有机发光元件EL的第二端连接至第二电源电压端VSS，以接收第二电源电压。
例如，第六晶体管T6的控制端EM1、第七晶体管T7的控制端EM2、第九晶体管T9的控制端EM3和第十晶体管T10的控制端EM4连接至同一发光控制端EM或同一发光控制线(图中未示出)。
例如，第一晶体管T1-第十晶体管T10可以均为P型晶体管(例如，PMOS管，也即，n型衬底、p沟道，靠空穴的流动运送电流的MOS管)，此种情况下，第一晶体管T1-第十晶体管T10在接收到高电平(第一电平)时截止，在接收到低电平(第二电平，第二电平小于第一电平)时导通，也即，高电平(第一电平)为无效电平(也即，使得晶体管关闭的电平)，低电平(第二电平)为有效电平(也即，使得晶体管导通的电平)。需要说明的是，第一晶体 管T1-第十晶体管T10不限于均实现为P型晶体管，根据实际应用需求，第一晶体管T1-第十晶体管T10的一个或多个还可以实现为N型晶体管。
需要说明的是，引入第一节点N1-第四节点N4旨在更为方便的描述各元件之间的连接关系，并非一定要在像素电路100中设置例如焊点或焊盘作为实际的节点。
例如，如图4B所示，图4A所示的像素电路100的每个驱动周期包括复位阶段S_re、数据写入和补偿阶段S_wc和发光阶段S_EM。
如图4A和图4B所示，在复位阶段S_re中，第一复位控制端RST1接收有效电平，扫描信号端GAT(对应于第二晶体管CT2的控制端GAT1和第三晶体管CT3的控制端GAT2)、第二复位控制端RST2和发光控制端EM(对应于第五晶体管CT5的控制端EM1和第七晶体管CT7的控制端EM2)接收无效电平；此种情况下，第五晶体管T5开启，第三晶体管T3、第四晶体管T4以及第六晶体管T6-第十晶体管T10关闭；第五晶体管T5被配置接收第一复位信号Vinit1，且将第一复位信号Vinit1写入至存储电容Cst，以对存储电容Cst复位；第一节点N1的电压为Vinit1，Vinit1例如为负值(例如，-3V)。例如，第一复位信号Vinit1写入至存储电容Cst之后，第一晶体管T1和第二晶体管T2开启。
如图4A和图4B所示，在数据写入和补偿阶段S_wc中，扫描信号端GAT和第二复位控制端RST2接收有效电平，第一复位控制端RST1和发光控制端EM接收无效电平；此种情况下，第一晶体管T1-第四晶体管T4以及第八晶体管T8开启(第一晶体管T1和第二晶体管T2因为写入至存储电容Cst的第一复位信号Vinit1开启)，第五晶体管T5-第七晶体管T7、第九晶体管T9以及第十晶体管T10关闭；第三晶体管T3接收数据信号Vdata，且数据信号Vdata经由开启的第一晶体管T1和第四晶体管T4被写入至第一晶体管T1的控制端，存储电容Cst在第一晶体管T1的控制端存储被写入至第一晶体管T1的控制端的数据信号Vdata，第一节点N1的电压为Vdata+Vth，此处，Vth为第一晶体管的阈值电压；第八晶体管T8被配置接收第二复位信号Vinit2，且将第二复位信号Vinit2写入至有机发光元件EL的第一端，以对有机发光元件EL的第一端复位，第四节点N4的电压为Vinit2，Vinit2例如为负值(例如，-3V)。
如图4A和图4B所示，在发光阶段S_EM中，发光控制端EM接收有效 电平，第一复位控制端RST1、扫描信号端GAT和第二复位控制端RST2接收无效电平；此种情况下，第一晶体管T1、第二晶体管T2、第六晶体管T6、第七晶体管T7、第九晶体管T9和第十晶体管T10开启，第三晶体管T3-第五晶体管T5以及第八晶体管T8关闭；第一晶体管T1被配置为，基于存储在存储电容Cst中的数据信号Vdata以及所接收的第一电源电压VDD，控制流经第一晶体管T1且从第一电源电压端VDD至有机发光元件EL、用于驱动有机发光元件EL的驱动电流，第二晶体管T2被配置为，基于存储在存储电容Cst中的数据信号Vdata以及所接收的第一电源电压VDD，控制流经第二晶体管T2且从第一电源电压端VDD至有机发光元件EL、用于驱动有机发光元件EL的驱动电流；第一节点N1的电压为Vdata+Vth，第二节点N2的电压为VDD。
例如，本公开的发明人通过对包括图4A所示的像素电路100的显示基板进行仿真计算，确定图4A所示的像素电路100可以提升被图4A所示的像素电路100驱动的有机发光元件EL的亮度(相比于图2A所示的像素电路580)。下面结合一个仿真示例进行示例性说明。
例如，对于如下的示例，也即，显示基板包括红色子像素R、绿色子像素G和蓝色子像素B，红色子像素R、绿色子像素G和蓝色子像素B的每个包括图4A所示的像素电路100，第一电源电压VDD为4.6V，红色子像素R、绿色子像素G和蓝色子像素B接收的数据信号的电压Vdata分别为2.7V、3.3V和2.28V，计算得到的红色子像素R、绿色子像素G和蓝色子像素B的每个的像素电路的第一节点N1-第四节点N4的电压值以及驱动电流Id的值可以参见表1。
表1
Figure PCTCN2020073996-appb-000002
如表1所示，包括图4B所示的像素电路100的红色子像素R的驱动电流与包括图2A所示的像素电路580的红色子像素R的驱动电流的比值为229.0％，包括图4B所示的像素电路100的绿色子像素G的驱动电流与包括图2A所示的像素电路580的绿色子像素G的驱动电流的比值为277.1％，包括图4B所示的像素电路100的蓝色子像素B的驱动电流与包括图2A所示的像素电路580的蓝色子像素B的驱动电流的比值为252.2％，也即，对于上述示例，像素电路100的驱动电流是像素电路580的驱动电流的至少2.2倍。
例如，本公开的发明人通过仿真还发现，通过增加(例如，从6.5V提高到7.0V)像素电路100的数据信号的电压值(相比于图2A所示的像素电路580)，可以使得像素电路100的驱动电流对应于零灰阶的驱动电流。例如，对应于零灰阶的驱动电流小于1皮安(pA)。
需要说明的是，在一些示例中，在数据写入和补偿阶段S_wc中，第八晶体管T8接收无效电平，在复位阶段S_re中，第八晶体管T8接收有效电平，也即，第八晶体管T8在复位阶段S_re对有机发光元件EL的第一端进行复位，而不是在数据写入和补偿阶段S_wc对有机发光元件EL的第一端进行复位。
本公开的至少一个实施例还提供了一种显示基板，其包括本公开的至少一个实施例提供的任一像素电路。例如，该显示基板可以为有机发光二极管显示面板。
图5A是本公开的至少一个实施例提供的显示基板10的示例性框图。如图5A所示，该显示基板10包括本公开的至少一个实施例提供的至少一个像素电路100。
例如，该显示基板10包括显示侧和非显示侧，显示基板10的显示的画面被配置为在显示基板10的显示侧显示，也即，显示基板10的显示侧为显示基板10的出光侧。显示侧和非显示侧在显示基板10的显示面的法线方向(例如，垂直于显示基板10的方向)上对置。
图5B是图5A所示的显示基板10的截面示意图。例如，如图5B所示，该显示基板10包括显示层260和感测层250，感测层250设置在显示基板10的非显示侧；显示层260包括显示区域201，显示区域201包括第一显示区域210和第二显示区域220；感测层250包括传感器251，传感器251与第一显 示区域210在显示基板10的显示面的法线方向上叠置，且被配置为接收并处理穿过第一显示区域210的光信号。
例如，传感器251可以是图像传感器，并可以用于采集传感器251的集光面面对的外部环境的图像。例如，在包括该显示基板10的显示装置20为诸如手机、笔记本的移动终端的情况下，该传感器251可用于实现诸如手机、笔记本的移动终端的摄像头。例如，该传感器251可以包括阵列排布传感像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，开关晶体管)。光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
图6是图5B所示的显示基板10的一个示例的平面示意图，图5B所示的显示基板10对应于图6所示的显示基板10的AA’线。
例如，如图6所示，该显示基板10(例如，显示基板10的显示层260)包括显示区域201以及至少部分围绕显示区域201的周边区域202；显示区域201包括第一显示区域210和第二显示区域220。例如，如图6所示，第二显示区域220至少部分围绕第一显示区域210。
图7A是图6所示的显示基板10的第一显示区域210的部分区域REG1的示意图，图8A是图6所示的显示基板10的第二显示区域220的部分区域REG2的示意图。如图7A所示，第一显示区域210包括阵列排布的多个第一像素单元270；如图8A所示，第二显示区域220包括阵列排布的多个第二像素单元290。
例如，显示基板10的显示区域201包括的多个像素单元可以包括不同颜色的像素单元(例如，红色像素单元、绿色像素单元和蓝色像素单元)，不同颜色的像素单元中发光元件的发光面积可以相同或者不完全相同。例如，红色像素单元中发光元件的发光面积，绿色像素单元中发光元件的发光面积和蓝色像素单元中发光元件的发光面积彼此不同。
图8B示出了图7A所示的第一像素单元270的一个示例，图8C示出了图7A所示的第一像素单元270的另一个示例，图8D示出了图8A所示的第二像素单元290的示意图。
例如，如图8B和图8C所示，多个第一像素单元270的每个包括发光元件301；多个第二像素单元290的每个包括第二发光元件302。例如，该发光 元件301和第二发光元件302均可以为有机发光元件，有机发光元件例如可以为有机发光二极管，但本公开的实施例不限于此。例如，该发光元件301和第二发光元件302均可以为无机发光元件。例如，发光元件301和第二发光元件302可以实现具有相同的结构和性能特性。例如，多个第一像素单元270的每个包括的发光元件301的数目等于多个第二像素单元290的每个包括的第二发光元件302的数目(例如，均等于一)。
例如，第一显示区域210的显示第一颜色的第一像素单元270包括的发光元件301的发光面积与第二显示区域220的显示第一颜色的第二像素单元290包括的第二发光元件302的发光面积彼此不同。例如，第一颜色可以为红色、绿色、蓝色或其它适用的颜色。
例如，第一显示区域210中多个第一像素单元270的单位面积分布密度小于第二显示区域220中多个第二像素单元290的单位面积分布密度。例如，第一显示区域210中多个发光元件301的单位面积分布密度小于第二显示区域220中多个第二发光元件302的单位面积分布密度。例如，由于第一显示区域210中多个第一像素单元270的单位面积分布密度小于第二显示区域220中多个第二像素单元290的单位面积分布密度，因此，第一显示区域210的显示分辨率低于第二显示区域220的显示分辨率，因此，第一显示区域210可以被称为显示基板10的低分辨率区域。
例如，如图7A所示，在第一方向D1上相邻的两个第一像素单元270的间距大于第一像素单元270在第一方向D1上的尺寸，在第二方向D2上相邻的两个第一像素单元270的间距大于等于第一像素单元270在第二方向D2上的尺寸。例如，在第一方向D1上相邻的两个第一像素单元270的间距等于第一像素单元270在第一方向D1上的尺寸的三倍；在第二方向D2上相邻的两个第一像素单元270的间距等于第一像素单元270在第二方向D2上的尺寸。例如，在第一方向D1上相邻的两个第一像素单元270的间距位于280-380微米的范围内，在第二方向D2上相邻的两个第一像素单元270的间距位于100-160微米的范围内，第一像素单元270在第一方向D1和第二方向D2上的尺寸位于110-130微米的范围内。在一些示例中，两个单元的间距是指两个单元的中心的间距。
例如，如图8A所示，在第一方向D1上相邻的两个第二像素单元290的间距小于第二像素单元290在第一方向D1上的尺寸，在第二方向D2上相邻 的两个第二像素单元290的间距小于第二像素单元290在第二方向D2上的尺寸。例如，如图8A所示，在第一方向D1上相邻的两个第二像素单元290的间距小于第二像素单元290在第一方向D1上的尺寸的五分之一，在第二方向D2上相邻的两个第二像素单元290的间距小于第二像素单元290在第二方向D2上的尺寸的五分之一。
例如，显示基板10包括多个像素电路100，且多个像素电路100与多个第一像素单元270包括的多个发光元件301一一对应电连接。例如，显示基板10还包括多个像素电路580，且多个像素电路580与多个第二像素单元290包括的多个第二发光元件302一一对应电连接。如图8D所示，每个第二像素单元290包括第二发光元件302以及用于驱动第二发光元件302的像素电路580。
需要说明的是，图8B仅用于示出像素单元273包含发光元件301和像素电路100，图8C仅用于示出像素驱动单元281包括的像素电路100与像素单元274包含的发光元件301彼此电连接，图8D仅用于示出第二像素单元290包括第二发光元件302和像素电路580，而并没有限定发光元件301、第二发光元件302、像素电路100和像素电路580的具体形状以及相对位置关系，发光元件301、第二发光元件302、像素电路100和像素电路580的具体形状以及相对位置关系可以根据实际应用需求进行设定。
例如，通过使得与多个第一像素单元270的发光元件一一对应连接的像素电路为本公开的至少一个实施例提供的任一像素电路100，可以提升多个第一像素单元270的发光元件的发光亮度，由此可以提升显示基板10的包括多个第一像素单元270的第一显示区域210的亮度(也即，提升显示基板10的低分辨率区域的亮度)。
例如，如图6和图7A所示，第一显示区域210包括包互不重叠的第一子显示区域211和第二子显示区域212。例如，如图6和图7A所示，第一子显示区域211至少部分围绕(例如，完全围绕)第二子显示区域212。
例如，如图7A-图7C所示，第一子显示区域211包括多个第一像素单元的第一组271，第二子显示区域212包括多个第一像素单元的第二组272，第一组和第二组彼此互不重叠。如图7A-图7C所示，多个第一像素单元270的第一组271包括第一数目的第一像素单元270(也即，第一数目的像素单元273)；多个第一像素单元的第二组272包括第二数目的第一像素单元270(也 即，第二数目的像素单元274)。
例如，如图8C所示，第二组272包括的像素单元274仅包括发光元件301，而不包括像素电路100；如图8C和图7A所示，用于驱动像素单元274包括的发光元件301的像素电路100设置在第一子显示区域211包括的像素驱动单元281。对应地，与多个第一像素单元的第二组272的发光元件一一对应连接的像素电路100设置在第一子显示区域211中(分别设置在第一子显示区域211包括的多个像素驱动单元281中)。例如，像素驱动单元281不包括发光元件。
例如，通过使得与多个第一像素单元的第二组272的发光元件一一对应连接的像素电路100设置在第一子显示区域211中，可以无需在第二子显示区域212设置像素电路，由此可以提升第二子显示区域212的透过率和第二子显示区域212包括的第一像素单元270的开口率；此种情况下，可以使得传感器251与第二子显示区域212在显示基板10的显示面的法线方向上叠置(参见图5B)，以减小第二子显示区域212中的元件对入射至第二子显示区域212并朝向传感器251传输的光信号的遮挡，由此可以提升传感器251输出的图像的信噪比。例如，第二子显示区域212可以被称为显示基板10的低分辨率区域的高透光区。
例如，显示基板10还包括多条走线213。多条走线213将多个第一像素单元的第二组272的发光元件和与多个第一像素单元的第二组272的发光元件一一对应连接的像素电路100(像素驱动单元281)电连接。例如，上述多条走线213的每条可以实现为透明走线，由此可以进一步地提升第二子显示区域212的透过率以及传感器251输出的图像的信噪比。
需要说明的是，与多个第一像素单元的第二组272的发光元件一一对应连接的像素不限于设置在第一子显示区域211，在一些示例中，在不考虑第二子显示区域212的透过率以及第二子显示区域212包括的第一像素单元270的开口率的情况下，与多个第一像素单元的第二组272的发光元件一一对应连接的像素的至少部分(例如，全部)还可以设置在第二子显示区域212。
例如，如图8B所示，第一组271包括的像素单元273同时包括发光元件301和像素电路100。对应地，多个第一像素单元的第一组271的发光元件一一对应连接的像素电路100也设置在第一子显示区域211中。例如，多个第一像素单元的第一组271的发光元件一一对应连接的像素电路100分别设置 在多个第一像素单元的第一组271的对应的第一像素单元270中，也即，多个第一像素单元的第一组271的每个第一像素单元270还包括用于驱动发光元件的像素电路。例如，多个第一像素单元的第一组271的每个第一像素单元270包括如图4A所示的像素电路和发光元件。
例如，如图7A所示，第一子显示区域211还可以包括冗余像素单元282，如图8E所示，该冗余像素单元282包括像素电路(例如，像素电路100)，但不包括发光元件。例如，通过设置该冗余像素单元282，可以使得第一子显示区域211的电学环境均匀(例如，使得电阻和电容的负载均匀)。
例如，该显示基板10还可以包括相互交叉(例如，垂直)设置的多条扫描信号线(例如，栅线)和多条数据线，以及与扫描信号线平行设置的多条电压控制线。例如，每个像素电路与对应扫描信号线和对应的数据线相连接，例如，每个像素电路对应的扫描信号端可以与对应的扫描信号线相连接，每个像素电路对应的数据信号端可以与对应的数据线相连接，每个像素电路对应的第一电源电压端和第二电源电压端可以与对应的电压控制线相连接。例如，多条扫描信号线分别沿显示基板10的行方向(例如，第一方向D1)延伸，多条扫描数据线分别具有沿显示基板10的列方向(例如，第二方向D2)延伸的部分。例如，第一方向D1与第二方向D2交叉(例如，垂直)。
例如，如图7A所示，与用于驱动发光元件的像素驱动单元281电连接的数据线DL从第一子显示区域211和第二子显示区域212之间的区域走线至第一子显示区域211，因此，数据线DL还包括沿第一方向D1延伸的部分。
例如，如图6所示，周边区域202包括驱动芯片230。例如，驱动芯片230可以包括数据驱动器，驱动芯片230的数据驱动器可经由柔性电路板邦定在显示基板10上，并经由柔性电路向多根数据线提供显示用的数据信号，以驱动显示基板10实现显示功能。例如，周边区域202还可以包括阵列基板上的栅驱动集成(GOA，图中未示出)，GOA的多个输出端分别与多根栅线GL相连，以向多根栅线提供栅扫描信号。
图9是图5B所示的显示基板10的另一个示例的平面示意图，图5B所示的显示基板10对应于图9所示的显示基板10的AA’线。
图9所示的显示基板10与图6所示的显示基板10相似，因此，此处将仅阐述图9所示的显示基板10与图6所示的显示基板10不同之处，相同之处不再赘述。图9所示的显示基板10与图6所示的显示基板10的不同之处 包括：图9所示的显示基板10的周边区域202包括像素驱动区域240，且与多个发光元件一一对应电连接的多个像素电路至少部分(例如，全部)设置于像素驱动区域240中；此种情况下，图9所示的显示基板10的第一显示区域210无需设置第一子显示区域211(仅设置第二子显示区域212或者显示基板10的低分辨率区域的高透光区)，由此可以减小第一显示区域210的尺寸，也即，可以减小显示基板10的低分辨率区域的尺寸，由此可以提升显示基板10显示的图像的质量。
例如，如图9所示，第二显示区域220围绕第一显示区域210。例如，如图9所示，像素驱动区域240与第一显示区域210在显示基板10的行方向(例如，对应于图7A和图8A的第一方向D1)上并列布置，像素驱动区域240和第一显示区域210被第二显示区域220间隔。此种情况下，多条走线213分别沿显示基板10的行方向延伸。
需要说明的是，像素驱动区域240与第一显示区域210不限于在显示基板10的行方向上并列布置，根据实际应用需求，如图10所示，像素驱动区域240与第一显示区域210可以在显示基板10的列方向(例如，对应于图7A和图8A的第二方向D2)上并列布置，此种情况下，多条走线213分别沿显示基板10的列方向延伸。
例如，为了使得第二显示区域220的亮度和第一显示区域210的亮度更为一致，可以在第一显示区域210采用本公开的至少一个实施例提供的像素电路100的基础上，额外对提供给第一显示区域210的像素电路100的数据信号进行补偿。例如，可以使用时序控制器对提供给第一显示区域210的像素电路100的数据信号进行补偿。
例如，如图9所示，该第一显示区域210的形状为圆形，但本公开的实施例不限于此。根据实际应用需求，该第一显示区域210的形状还可以实现为矩形或其它适用的形状。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一像素电路或任一显示基板。
图11是本公开的至少一个实施例提供的显示装置20的示例性框图。如图11所示，该显示装置20包括本公开的至少一个实施例提供的任一像素电路100或任一显示基板10。
需要说明的是，对于该显示基板和显示装置的其它组成部分(例如，图 像数据编码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。该显示基板和显示装置可以提升显示基板和显示装置的低分辨率区域(也即，第一显示区域)的亮度(例如，整体亮度)。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (18)

  1. 一种像素电路，包括：第一驱动电路、第二驱动电路、数据写入电路和信号存储电路，
    其中，所述数据写入电路被配置为接收数据信号；
    所述第一驱动电路与所述数据写入电路连接，被配置为从所述数据写入电路接收所述数据信号且允许所述数据信号被写入至所述第一驱动电路的控制端；
    所述第二驱动电路的控制端被配置为接收被写入至所述第一驱动电路的控制端的所述数据信号；
    所述信号存储电路被配置为在所述第一驱动电路的控制端存储被写入至所述第一驱动电路的控制端的所述数据信号；
    所述第一驱动电路的第一端和所述第二驱动电路的第一端均被配置为从第一电源电压端接收第一电源电压，所述第一驱动电路的第二端和所述第二驱动电路的第二端均被配置为电连接到发光元件的第一端；以及
    所述第一驱动电路和所述第二驱动电路被配置为，基于存储在所述信号存储电路中的所述数据信号以及所接收的所述第一电源电压，控制分别流经所述第一驱动电路和所述第二驱动电路且从所述第一电源电压端至所述发光元件、用于驱动所述发光元件的驱动电流。
  2. 根据权利要求1所述的像素电路，其中，所述第一驱动电路的控制端和所述第二驱动电路的控制端彼此电连接。
  3. 根据权利要求1或2所述的像素电路，还包括补偿连接电路，
    其中，所述数据写入电路将所述数据信号写入至所述第一驱动电路的第一端；以及
    所述补偿连接电路连接在所述第一驱动电路的第二端和所述第一驱动电路的控制端之间，并且被配置为将被写入至所述第一驱动电路的第一端的数据信号经由所述第一驱动电路写入至所述第一驱动电路的控制端。
  4. 根据权利要求3所述的像素电路，其中，所述补偿连接电路的控制端和所述数据写入电路的控制端连接至同一扫描信号线。
  5. 根据权利要求1-4任一所述的像素电路，还包括第一复位电路，
    其中，所述第一复位电路与所述信号存储电路相连；以及
    所述第一复位电路被配置接收第一复位信号，且将所述第一复位信号写入至所述信号存储电路，以对所述信号存储电路复位。
  6. 根据权利要求1-5任一所述的像素电路，还包括第一控制电路和第二控制电路，
    其中，所述第一控制电路连接在所述第一驱动电路的第一端和所述第一电源电压端之间，且被配置为控制所述第一驱动电路是否与所述第一电源端电连接；以及
    所述第二控制电路连接在所述第二驱动电路的第一端和所述第一电源电压端之间，且被配置为控制所述第二驱动电路是否与所述第一电源端电连接。
  7. 根据权利要求6所述的像素电路，其中，所述第一控制电路的控制端和所述第二控制电路的控制端连接至同一发光控制线。
  8. 根据权利要求1-7任一所述的像素电路，还包括第二复位电路,
    其中，所述第二复位电路被配置为接收第二复位信号，且将所述第二复位信号写入至所述发光元件的第一端，以对所述发光元件的第一端复位。
  9. 根据权利要求1-8任一所述的像素电路，还包括第三控制电路和第四控制电路，
    其中，所述第三控制电路连接在所述第一驱动电路的第二端与所述发光元件的第一端之间，且被配置为控制所述第一驱动电路是否与所述发光元件的第一端电连接；以及
    所述第四控制电路连接在所述第二驱动电路的第二端与所述发光元件的第一端之间，且被配置为控制所述第二驱动电路是否与所述发光元件的第一端电连接。
  10. 根据权利要求9所述的像素电路，其中，所述第三控制电路的控制端和所述第四控制电路的控制端连接至同一发光控制线。
  11. 根据权利要求1-10任一所述的像素电路，其中，所述第一驱动电路包括第一晶体管，所述第二驱动电路包括第二晶体管；以及
    所述第一晶体管的阈值电压和所述第二晶体管的阈值电压相等。
  12. 一种显示基板，包括如权利要求1-11任一所述的至少一个像素电路。
  13. 根据权利要求12所述的显示基板，其中，所述至少一个像素电路包 括多个像素电路；
    所述显示基板具有显示区域，所述显示区域包括第一显示区域和第二显示区域；
    所述第一显示区域包括阵列排布的多个第一像素单元，所述第二显示区域包括阵列排布的多个第二像素单元；
    所述第一显示区域中所述多个第一像素单元的单位面积分布密度小于所述第二显示区域中所述多个第二像素单元的单位面积分布密度；
    所述多个第一像素单元的每个包括所述发光元件；以及
    所述多个像素电路与所述多个发光元件一一对应电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第一显示区域还包互不重叠的第一子显示区域和第二子显示区域；
    所述第一子显示区域包括所述多个第一像素单元的第一组，所述第二子显示区域包括所述多个第一像素单元的第二组，所述第一组和第二组彼此互不重叠；以及
    与所述多个第一像素单元的第二组的发光元件一一对应连接的像素电路设置在所述第一子显示区域中。
  15. 根据权利要求14所述的显示基板，还包括多条透明走线，其中，所述多条透明走线将所述多个第一像素单元的第二组的发光元件和与所述多个第一像素单元的第二组的发光元件一一对应连接的像素电路电连接。
  16. 根据权利要求13所述的显示基板，其中，所述显示基板还具有至少部分围绕所述显示区域的周边区域，所述多个像素电路至少部分设置于所述周边区域中。
  17. 根据权利要求13-16任一所述的显示基板，还包括传感器，其中，所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
  18. 一种显示装置，包括如权利要求1-11任一所述的像素电路或如权利要求12-17任一所述的显示基板。
PCT/CN2020/073996 2020-01-23 2020-01-23 像素电路、显示基板和显示装置 WO2021147083A1 (zh)

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