WO2022227043A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022227043A1
WO2022227043A1 PCT/CN2021/091627 CN2021091627W WO2022227043A1 WO 2022227043 A1 WO2022227043 A1 WO 2022227043A1 CN 2021091627 W CN2021091627 W CN 2021091627W WO 2022227043 A1 WO2022227043 A1 WO 2022227043A1
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WIPO (PCT)
Prior art keywords
transparent
capacitance
light
display
display substrate
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PCT/CN2021/091627
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English (en)
French (fr)
Inventor
邱远游
黄耀
王琦伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/091627 priority Critical patent/WO2022227043A1/zh
Priority to CN202180001025.1A priority patent/CN115552622A/zh
Publication of WO2022227043A1 publication Critical patent/WO2022227043A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the display substrate includes a base substrate, and a pixel circuit layer, a transparent wiring layer, and a light-emitting element layer sequentially arranged on the base substrate;
  • the pixel The circuit layer includes a gate layer and a source and drain layer; each first light emitting element in the plurality of first light emitting elements is located in the light emitting element layer; each first pixel in the plurality of first pixel circuits
  • the circuit includes a thin film transistor, the thin film transistor includes a gate electrode, a source electrode and a drain electrode, the gate electrode is located in the gate electrode layer, and at least one of the source electrode and the drain electrode is located in the source and drain electrode layer;
  • Each transparent trace in the plurality of transparent traces is located in the transparent trace layer;
  • the at least one first capacitance compensation structure includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the One of the second capacitor electrodes is located on the gate layer, the source/drain layer or the transparent wiring layer.
  • the pixel circuit layer further includes a capacitor plate layer, and the other one of the first capacitor electrode and the second capacitor electrode is located on the capacitor plate layer .
  • the senor includes at least one of an image sensor, an infrared sensor, and a distance sensor.
  • 2A is a schematic diagram of an equivalent circuit in which a transparent wire is coupled to a first light-emitting element
  • FIG. 2B is a schematic diagram illustrating the variation of the driving current flowing through the first light-emitting element shown in FIG. 2A;
  • FIG. 4 is a schematic diagram of an equivalent circuit of a transparent trace coupled to a first capacitance compensation structure and a first light-emitting element according to some embodiments of the present disclosure
  • 5A is a schematic plan view of coupling of a pixel group, a transparent wiring group, a pixel circuit group, and a compensation structure group according to some embodiments of the present disclosure
  • 6A is a schematic diagram of a circuit structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 7A is a partial area layout of the overall structure of a display substrate according to some embodiments of the present disclosure.
  • FIG. 7B is a schematic cross-sectional view of the display substrate shown in FIG. 6A along the line M-N;
  • FIG. 7C is a schematic plan view of the first conductive layer in the display substrate shown in FIG. 7A;
  • FIG. 7D is a schematic plan view of the second conductive layer in the display substrate shown in FIG. 7A;
  • 7G is a schematic plan view of the stacking of the first conductive layer, the second conductive layer and the third conductive layer in the display substrate shown in FIG. 7A;
  • FIG. 7H is a schematic plan view of the fourth conductive layer in the display substrate shown in FIG. 7A;
  • 7I is a schematic plan view of the stacking of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer in the display substrate shown in FIG. 7A;
  • FIG. 8 is a schematic plan view of a display device according to some embodiments of the present disclosure.
  • part of the display area for installing sensors can be designed as a transparent display area, so that the transparent display area can display
  • sensors such as image sensors, infrared sensors, distance sensors
  • it provides convenience for the installation of sensors and other components, so that these sensors can perform functions such as imaging, infrared sensing, and distance sensing through the transparent display area without affecting the display function of the transparent display area.
  • FIG. 1A is a schematic plan view of a display substrate.
  • the display substrate 100 includes a display area and a peripheral area 40 surrounding the display area.
  • the display area includes a transparent display area 10 , a transition display area 20 and a main display area 30 .
  • the transparent display area 10 allows light to be transmitted from one side of the display substrate 100 to the other side of the display substrate 100 .
  • FIG. 1B is a schematic cross-sectional view of a partial structure of a display device.
  • the display device 100 includes the display substrate 110 and the sensor 120 shown in FIG. 1A .
  • the display substrate 110 has a first panel surface F1 and a second panel surface F2, wherein the first panel surface is used for display (ie, facing the user) during the operation of the display substrate 110 .
  • the sensor 120 is arranged on the side of the second board surface F2 (that is, the side of the display substrate 110 away from the user, that is, the non-display side of the display substrate 110 ), and the orthographic projection of the sensor 120 on the display substrate and the transparent display area 10 are at least Partially overlapping.
  • the sensor 120 is configured to receive light incident from the side of the first panel surface F1 (ie, the display side of the display substrate 110 ).
  • FIG. 1C is a partial enlarged schematic view of the display substrate shown in FIG. 1A .
  • the main display area 30 is the main display area (or referred to as a regular display area); compared with the transparent display area 10 and the transition display area 20 , the main display area 30 may have a higher resolution ( PPI, Pixel Per Inch), that is, pixels with high density for display are arranged in the main display area 30 (one pixel may include multiple sub-pixels).
  • PPI Pixel Per Inch
  • each sub-pixel (as indicated by the block P in the main display area 30) includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the transparent display area 10 and/or the transition display area 20 are arranged with the same density of pixels for display (one pixel may include multiple sub-pixels), and the transparent display area 10 and/or Or the area of the pixel driving circuit in the transition display area 20 is smaller than the area of the pixel driving circuit in the main display area 30 .
  • the transparent display area 10 can allow light incident from the display side of the display substrate 110 to pass through the display substrate 110 to reach the non-display side of the display substrate 110, so as to be used for the normal operation of components such as the sensor 120 located on the non-display side of the display substrate 110 .
  • the transparent display area 10 may also allow light emitted from the non-display side 120 of the display substrate 110 to pass through the display substrate 110 to reach the display side of the display substrate 110 .
  • the pixel circuits of the sub-pixels are generally opaque to light, in order to improve the transparency of the transparent display area 10 , the light-emitting elements of the sub-pixels of the transparent display area 10 and the pixel circuits driving the light-emitting elements may be physically separated.
  • the sub-pixels in the transparent display area 10 (as shown by the block A in the transparent display area 10 ) only retain light-emitting elements, and the pixel circuits of the sub-pixels in the transparent display area 10 can be arranged in the transition
  • the transitional display area 20 there may be an idle area in the transitional display area 20 (as shown by the block V in the transitional display area 20 ), and in the idle area, generally no light-emitting elements or pixel circuits are arranged.
  • the light-emitting elements of the sub-pixels in the transparent display area 10 are electrically connected to the corresponding pixel circuits in the transition display area 20 through traces L (shown by black line segments in FIG. 1C ).
  • the above-mentioned wiring L is usually a transparent wiring, or at least the part of the wiring L located in the transparent display area 10 is transparent (in this case, even if the wiring L is transparent The rest is opaque, and the trace L may also be considered as a transparent trace in the present disclosure).
  • a transparent conductive material such as a transparent metal oxide, such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc.
  • a transparent metal oxide such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc.
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • “transparent” and “transmittance” only need to have a certain transmittance, for example, the transmittance is greater than 0, and the transmittance is not required to be 100%.
  • the light transmittance of any structure or region is greater than a certain value (for example, 40%, 45%, 50%, etc.), the structure or region can be considered as “transparent” or “transparent” .
  • the block P may represent a sub-pixel
  • the block A may represent a light-emitting element
  • the block D may represent a pixel circuit
  • the trace L may represent the connection between a light-emitting element A and a pixel circuit A transparent trace of D; or, in FIG.
  • block P may represent a pixel (ie, a sub-pixel group, including a plurality of sub-pixels), and block A may represent a group of light-emitting elements (including Multiple light-emitting elements), block D may represent a group of pixel circuits (including multiple pixel circuits corresponding to multiple light-emitting elements in a pixel), and trace L may represent connecting a group of light-emitting elements A and a group of pixel circuits D A set of transparent traces (including multiple transparent traces).
  • FIG. 2A is a schematic diagram of an equivalent circuit in which the transparent trace L is coupled to the first light emitting element LE.
  • one end of the transparent trace L is coupled to the pixel circuit (not shown in FIG. 2A ), and the other end of the transparent trace L is coupled to the light-emitting element EL (eg, to the light-emitting element Anode coupling of EL).
  • the transparent trace L there is a coupling effect between the transparent trace L and components, wirings, and other electrical structures disposed near it. Therefore, there is usually a parasitic capacitance C_L on the transparent trace L.
  • FIG. 2B is a schematic diagram illustrating the variation of the driving current flowing through the first light-emitting element LE shown in FIG. 2A .
  • the first pixel circuit provides a driving current
  • a part of the driving current will be used to charge the parasitic capacitance C_L of the transparent trace L, and the remaining part of the driving current will flow through the first light-emitting element LE (refer to the straight arrow in FIG. 2A ), until the voltage of the parasitic capacitor C_L reaches electrical equilibrium (ie, the voltage does not change any more), the driving current will not fully act on the first light emitting element LE.
  • the driving current actually flowing through the first light-emitting element LE will undergo a process from small to large until stable (refer to the curve I1 or curve I2 in FIG. 2B ). The longer it takes for the drive current of the light-emitting element LE to reach a steady state.
  • the first light-emitting element LE1 does not stabilize according to the driving current in a relatively short period of time.
  • the first light-emitting element LE2 does not emit light according to the stable value of the driving current for a relatively long period of time. Therefore, relative to the expected luminous brightness corresponding to the displayed gray scale, the luminous brightness of the two first light emitting elements LE1 and LE2 are both reduced;
  • the reduction range of the light-emitting luminance of the light-emitting element LE1, that is, the luminance of the two first light-emitting elements LE1 and LE2 is uneven, and this phenomenon is more obvious at low gray scales.
  • At least some embodiments of the present disclosure provide a display substrate including a first display area and a first area at least partially surrounding the first display area; the first display area includes a plurality of first light emitting elements, the first area It includes a plurality of first pixel circuits and at least one first capacitance compensation structure, and the display substrate includes a plurality of transparent wirings extending from the first area to the first display area; at least one first pixel in the plurality of first pixel circuits The circuit is electrically connected to at least one light-emitting element of the plurality of first light-emitting elements through at least one transparent wire of the plurality of transparent wires, and is configured to control flow through the at least one first pixel circuit, the at least one a transparent wire and the at least one first light-emitting element and a driving current for driving the at least one first light-emitting element to emit light; the at least one first capacitance compensation structure is coupled to at least one transparent wire among the plurality of transparent wires, and is configured to compensate for parasitic capac
  • Some embodiments of the present disclosure also provide a display device corresponding to the above-mentioned display substrate.
  • the parasitic capacitance of the transparent trace can be compensated by the first capacitance compensation structure, so that the luminous brightness of different first light-emitting elements has better uniformity, so as to alleviate or solve the problem of the first light-emitting element.
  • the problem of uneven brightness in the display area especially the problem of uneven brightness when the first display area displays low grayscale, thereby improving the display effect of the first display area.
  • FIG. 3A is a schematic plan view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3B is a partial enlarged schematic view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3C is another schematic diagram of a display substrate provided by some embodiments of the present disclosure A partially enlarged schematic diagram of the display substrate.
  • the first display area Rb (ie, the first display area 10 ) includes a plurality of first light-emitting elements A, and the first area Ra includes a plurality of first light-emitting elements A
  • the display substrate 210 includes a plurality of transparent wirings L extending from the first region Ra to the first display region Rb; each first pixel circuit D passes through a corresponding transparent wiring.
  • the line L is electrically connected to a corresponding first light-emitting element A, and each first pixel circuit D is configured to control flow through the first pixel circuit D, the corresponding transparent trace L and the corresponding first light-emitting element A and the driving current for driving the corresponding first light-emitting element A to emit light;
  • the at least one first capacitance compensation structure C is coupled to at least one transparent wire among the plurality of transparent wires L, and is configured to compensate for the Parasitic capacitance due to at least one transparent trace.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a transparent trace L coupled with the first capacitance compensation structure C and the first light emitting element EL (ie, the first light emitting element A) according to some embodiments of the present disclosure.
  • one end of the transparent trace L (as shown in the line segment or the broken line segment connecting the first pixel circuit D and the first light-emitting element A in FIGS. 3B and 3C ) is connected to the first pixel.
  • the circuit D (not shown in FIG.
  • the compensation capacitance C provided by the first capacitance compensation structure C is connected in parallel with the parasitic capacitance C_L caused by the transparent trace L, so that the compensation capacitance C of the first capacitance compensation structure C can be used to compensate the transparent trace
  • the parasitic capacitance C_L caused by L is connected in parallel with the parasitic capacitance C_L caused by the transparent trace L, so that the compensation capacitance C of the first capacitance compensation structure C can be used to compensate the transparent trace
  • the sum of the parasitic capacitance value C_L of the transparent trace L and the compensation capacitance value of the first capacitance compensation structure C may be approximately equal to the same target capacitance value; In this way, the change curve of the driving current flowing through each of the first light emitting elements LE can be adjusted to be substantially consistent. That is to say, by arranging the first capacitance compensation structure C, the first light-emitting elements LE in the first display area 10 can have substantially the same luminous brightness when displaying the same gray scale, so that the first display area can be alleviated or solved. The problem of uneven brightness improves the display effect of the first display area.
  • a is approximately equal to b
  • x is within x% of the value of b; for example, the value of x may range from 3 to 10. Including but not limited to this.
  • x may be equal to 3, 5, 7, 10, etc., embodiments of the present disclosure include but are not limited thereto.
  • the above-mentioned target capacitance value may be greater than or equal to the maximum value of the parasitic capacitance value C_L of each transparent trace L.
  • the target capacitance value may be equal to the maximum value of the parasitic capacitance value C_L of each transparent trace L.
  • the transparent trace L whose parasitic capacitance value is approximately equal to the target capacitance value does not need to be compensated That is, the transparent trace L with the parasitic capacitance value approximately equal to the target capacitance value may not be coupled with the first capacitance compensation structure C; thus, the number of arrangements of the first capacitance compensation structure C can be reduced, and the space of the display substrate can be saved.
  • the first area Ra may include a peripheral area 40 , and the peripheral area 40 is located on at least one edge of the first display area 10 and the display substrate (as shown in FIG. 3B ) "border").
  • the first pixel circuits D and the first capacitance compensation structures C in the display substrate 210 may all be located in the peripheral region 40 , and each first capacitance compensation structure C is coupled to the corresponding first pixel circuit D catch.
  • FIG. 3B the first pixel circuits D and the first capacitance compensation structures C in the display substrate 210 may all be located in the peripheral region 40 , and each first capacitance compensation structure C is coupled to the corresponding first pixel circuit D catch.
  • the first capacitance compensation structure C, the first pixel circuit D and the transparent wiring L corresponding to each other are coupled to the same node (the first capacitance compensation structure C and the first pixel circuit are connected in FIG. 3B )
  • the end point of the line segment of D is shown in the box D, and the end point coincides with an end point of the transparent trace L).
  • the first region Ra may further include the second display area 20 and the third display area 30 .
  • the second display area includes a second pixel unit P
  • the second pixel unit P may include a second light emitting element (not shown in FIG. 3B ) and a second pixel circuit (not shown in FIG. 3B ).
  • the second pixel circuit is electrically connected to the second light-emitting element (transparent wiring L is not included in the connection path), and is configured to control the driving that flows through the second pixel circuit and the second light-emitting element and drives the second light-emitting element to emit light current.
  • the third display area 30 also includes the second pixel unit P.
  • the second pixel unit P for example, as shown in FIG. 3B , there may also be an idle area in the second display area 20 (as shown by the block V in the second display area 20 in FIG. 3B ).
  • No pixel circuit is provided.
  • the resolution of the second display area 20 may generally be greater than or equal to the resolution of the first display area 10
  • the resolution of the third display area 30 may generally be greater than or equal to the resolution of the second display area 20/first display area 10 Resolution, embodiments of the present disclosure include, but are not limited to.
  • At least part of the transparent traces L may extend through the second display area 20 .
  • the first pixel circuit D does not need to be arranged in the second display area 20 .
  • the second pixel unit P may have the same dense arrangement structure as the second pixel unit P in the third display area 30 . That is to say, in some embodiments, the second pixel unit may be arranged in the free area V in the second display area 20 of the display substrate shown in FIG. 3B , so that the second display area 20 has the same characteristics as the third display area. 30 of the same pixel unit arrangement structure, that is, the resolution of the second display area 20 is the same as the resolution of the third display area 30 .
  • the first region Ra may include a second display area 20 that at least partially surrounds the first display area 10 .
  • the second display area 20 includes a second pixel unit P, and the second pixel unit P may include a second light-emitting element (not shown in FIG. 3C ) and a second pixel circuit (not shown in FIG. 3C ) out).
  • the second pixel circuit is electrically connected to the second light-emitting element (the connection path does not include a transparent wire), and is configured to control a driving current that flows through the second pixel circuit and the second light-emitting element and drives the second light-emitting element to emit light .
  • the first pixel circuit D and the first capacitance compensation structure C in the display substrate 210 may all be located in the second display area 40 , and each first capacitance compensation structure C corresponds to the corresponding first pixel circuit D coupling.
  • FIG. 3C the first pixel circuit D and the first capacitance compensation structure C in the display substrate 210 may all be located in the second display area 40 , and each first capacitance compensation structure C corresponds to the corresponding first pixel circuit D coupling.
  • the corresponding first capacitance compensation structure C, the first pixel circuit D and the transparent wiring L are coupled to the same node (the first capacitance compensation structure C and the first pixel circuit are connected in FIG. 3C )
  • the end point of the line segment of D is shown in the box D, and the end point coincides with an end point of the transparent trace L).
  • a part of the first pixel circuit D and a part of the first capacitance compensation structure C may be located in the peripheral region 40, while another part of the first pixel circuit D and another part of the first The capacitance compensation structure C is located in the second display area 20 .
  • the layout and other details of the first pixel circuit D and the first capacitance compensation structure C located in the peripheral area 40 may refer to the related description of the embodiment shown in FIG. 3B .
  • FIG. 3C For the layout and other details of a pixel circuit D and the first capacitance compensation structure C, reference may be made to the related description of the embodiment shown in FIG. 3C , and details are not repeated here.
  • the transparent traces L may be compensated in groups.
  • a plurality of transparent wires may be divided into a plurality of transparent wire groups, and each transparent wire group includes at least one transparent wire.
  • the parasitic capacitance values of the plurality of transparent wirings are approximately equal.
  • an average value of parasitic capacitance values of the at least one transparent wiring in each transparent wiring group may be used as the average parasitic capacitance value of each transparent wiring group.
  • the parasitic capacitance value of the transparent trace (as the average value of the parasitic capacitance value) is taken as the average parasitic capacitance value of the transparent trace group;
  • the line group includes a plurality of transparent lines
  • the average value of parasitic capacitance values of the plurality of transparent lines is used as the average parasitic capacitance value of the transparent line group.
  • the target capacitance value is greater than or equal to the maximum value of the average parasitic capacitance value of each transparent trace group.
  • the first light-emitting element corresponding to the transparent wire in each transparent wire group may be regarded as a pixel group, and the pixel circuit corresponding to the transparent wire in each transparent wire group may be regarded as a pixel circuit.
  • the pixel circuits are grouped, and the first capacitance compensation structure corresponding to the transparent lines in each transparent line group is regarded as a compensation structure group.
  • the target capacitance value is equal to the maximum value of the average parasitic capacitance value of the transparent trace group, in which case the average parasitic capacitance value is approximately equal to the transparent traces in the transparent trace group of the target capacitance value Compensation is not required, that is, the transparent wiring group whose average parasitic capacitance value is approximately equal to the target capacitance value does not need to be provided with a corresponding compensation structure group. That is, the transparent trace whose parasitic capacitance value is approximately equal to the target capacitance value may not be coupled with the first capacitance compensation structure C. As shown in FIG. Therefore, the number of arrangements of the compensation structure groups can be reduced, that is, the number of arrangements of the first capacitance compensation structures C can be reduced, thereby saving the space of the display substrate.
  • block A, block D, and block C in FIG. 3B and FIG. 3C can be regarded as a pixel group (including the first light-emitting element) and a pixel circuit group, respectively. , a compensation structure group.
  • the block P in FIG. 3B and FIG. 3C can also be regarded as a pixel group (including the second light-emitting element and the second pixel circuit).
  • FIG. 5A is a schematic plan view of coupling of pixel groups, transparent wiring groups, pixel circuit groups, and compensation structure groups according to some embodiments of the present disclosure.
  • FIG. 5A shows a situation in which the pixel circuit group D and the compensation structure group C are located in the peripheral area 40 .
  • FIG. 5A shows that the pixel group A includes 3 first light-emitting elements, the transparent wiring group L includes 3 transparent wirings, the pixel circuit group includes 3 first pixel circuits, and the compensation structure group C includes 3 first pixel circuits. The case of the first capacitance compensation structure. As shown in FIG.
  • the first light-emitting element in each pixel group A is electrically connected to the first pixel circuit in the corresponding pixel circuit group through the transparent wires in the corresponding transparent wire group L, and the first pixel circuit in the pixel circuit group is electrically connected.
  • the first pixel circuit is also coupled to the first capacitance compensation structure in the corresponding compensation structure group.
  • the transparent trace and the first capacitance compensation structure are coupled to the same node (as shown by the gray circles in the pixel circuit group D of FIG. 5A ).
  • FIG. 5B is a schematic plan view of another coupling of pixel groups, transparent wiring groups, pixel circuit groups, and compensation structure groups provided by some embodiments of the present disclosure.
  • FIG. 5B shows a situation where the pixel circuit group D and the compensation structure group C are located in the second display area 20 .
  • FIG. 5B shows that the pixel group A includes 3 first light-emitting elements, the transparent wiring group L includes 3 transparent wirings, the pixel circuit group includes 3 first pixel circuits, and the compensation structure group C includes 3 first pixel circuits. The case of the first capacitance compensation structure. As shown in FIG.
  • the first light-emitting element in each pixel group A is electrically connected to the first pixel circuit in the corresponding pixel circuit group through the transparent wires in the corresponding transparent wire group L, and the first pixel circuit in the pixel circuit group is electrically connected.
  • the first pixel circuit is also coupled to the first capacitance compensation structure in the corresponding compensation structure group.
  • the transparent trace and the first capacitance compensation structure are coupled to the same node (as shown by the gray circles in the pixel circuit group D of FIG. 5B ).
  • the first light-emitting element, the first pixel circuit, the first capacitance compensation structure, and the second pixel unit are usually arranged in an array in the display area where they are located. cloth.
  • the layouts of the transparent traces L in FIG. 3B and FIG. 3C are both schematic, which are not limited by the embodiments of the present disclosure.
  • the transparent traces can be reasonably laid out according to actual needs, so as to minimize the difference in the parasitic capacitance value of each transparent trace, thereby reducing the compensation capacitance of the first capacitance compensation structure. value, thereby reducing the space occupied by the first capacitance compensation structure.
  • the embodiments of the present disclosure do not limit the specific structures of the first light-emitting element, the first pixel circuit, the first capacitance compensation structure, and the second pixel unit.
  • the specific structure of the first light-emitting element may be the same as that of the second light-emitting element in the second pixel unit
  • the specific structure of the first pixel circuit may be the same as that of the second light-emitting element in the second pixel unit.
  • the specific structure of the pixel circuit is the same, and embodiments of the present disclosure include but are not limited to this.
  • the projected area of the first light-emitting element on the base substrate is smaller than the projection area of the second light-emitting element in the second pixel unit on the base substrate
  • the projected area of the first pixel circuit on the base substrate is smaller than the projected area of the second pixel circuit in the second pixel unit on the base substrate, and embodiments of the present disclosure include but are not limited to this.
  • the first capacitance compensation structure may be disposed in a corresponding first pixel circuit away from the first display area 10 side, which can facilitate the layout of transparent traces.
  • capacitance compensation may be performed on the second pixel unit P in the second display area 20 .
  • the second display area 20 may further include a second capacitance compensation structure, the second capacitance compensation structure is coupled to the second pixel circuit and the second light emitting element in the second pixel unit P, and is configured to provide feedback to the second pixel circuit Compensation capacitors are provided.
  • the compensation capacitance value of the second capacitance compensation structure is approximately equal to the target capacitance value. Therefore, referring to the relevant description of FIG.
  • the change curve of the driving current flowing through the second light-emitting element can be adjusted to be the same as the target capacitance value.
  • the change curve of the driving current flowing through the first light-emitting element is basically the same, so that the brightness of the second display area 20 and the first display area 10 can be made uniform, and the overall display effect of the first display area 10 and the second display area 20 can be improved. .
  • the parasitic torch value of the transparent trace and the compensation capacitance value of the first capacitance compensation structure may be determined by technical means such as simulation and/or experimental measurement.
  • the first pixel circuit and the second pixel circuit may adopt common pixel driving circuits such as 2T1C, 4T1C, 4T2C, and 7T1C, but are not limited thereto.
  • the present disclosure does not limit the specific structures of the first pixel circuit and the second pixel circuit.
  • FIG. 6A shows a 7T1C pixel driving circuit.
  • the 7T1C pixel driving circuit includes first to seventh transistors T1-T7 and a storage capacitor Cst.
  • the gate of the first transistor T1 is connected to the first reset signal terminal (or the first reset signal line) to receive the first reset signal Reset1, and the first electrode of the first transistor T1 is connected to the first reset signal
  • the voltage terminal (or the first reset voltage line) is connected to receive the first reset voltage Vinit1, the second pole of the first transistor T1 is connected to the first node N1;
  • the gate of the second transistor T2 is connected to the scan signal terminal (or scan signal line) ) is connected to receive the scanning signal Gate
  • the first pole of the second transistor T2 is connected to the first node N1, the second pole of the second transistor T2 is connected to the third node N3;
  • the gate of the third transistor T3 is connected to the first node N1 connected, the first pole of the third transistor T2 is connected to the third node N3, the second pole of the second transistor T3 is connected to the second node N3;
  • the gate of the fourth transistor T4 is connected to the scan signal terminal (or scan signal line) In order to receive the scanning signal
  • the anode of the first light-emitting element EL is electrically connected to the fourth node N4 through a transparent wire, and the cathode of the first light-emitting element EL is connected to the second power supply terminal (or second power supply line) to Receiving the second power supply voltage VSS (eg, a low voltage), the first capacitance compensation structure (not shown in FIG. 6A ) is coupled to the fourth node N4 .
  • VSS eg, a low voltage
  • the anode of the second light-emitting element EL is directly coupled to the fourth node N4, and the cathode of the second light-emitting element EL is connected to the second power terminal (or the second power line) to receive the second Supply voltage VSS (eg, low voltage).
  • VSS the second Supply voltage
  • the second capacitance compensation structure (not shown in FIG. 6A) is coupled to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • FIG. 6A in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole, and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltages)
  • the turn-off voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (eg, 0V, -5V, -10V or other suitable voltages) voltage).
  • the first to seventh transistors T1-T7 are all P-type transistors, such as low temperature polysilicon thin film transistors.
  • the embodiment of the present disclosure does not limit the type of the transistor. When the type of the transistor is changed, the connection relationship in the circuit and the polarity of the signal can be adjusted accordingly.
  • the display process of each frame of image includes three stages, which are initialization stage 1 , data writing and compensation stage 2 , and light-emitting stage 3 .
  • the first reset control signal Reset1 is input to turn on the first transistor T1, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.
  • the scan signal Gate and the data signal Vdata are input, the second transistor T2 and the fourth transistor T4 are turned on, the data signal data is written into the second node N2 through the fourth transistor T4, and passes through the third transistor T3 and the second transistor T2 to charge the first node N1 until the potential of the first node N1 changes to Vdata+Vth when the third transistor T3 is turned off, where Vth is the threshold voltage of the third transistor T3.
  • the potential of the first node N1 is stored in the storage capacitor Cst to be maintained, that is to say, the voltage information with the data signal Vdata and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide the Grayscale display data and compensation for the threshold voltage of the third transistor T3 itself.
  • the second reset control signal Reset2 may also be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4, thereby resetting the fourth node N4.
  • the reset of the fourth node N4 may also be performed in the initialization phase 1, for example, the first reset control signal Reset1 and the second reset control signal Reset2 may be the same. The embodiments of the present disclosure do not limit this.
  • the light-emitting control signal EM is input to turn on the fifth transistor T5, the sixth transistor T6 and the third transistor T3, and the sixth transistor T6 applies a driving current to the light-emitting element EL to emit light.
  • the value of the driving current Id provided by the pixel driving circuit can be obtained according to the following formula:
  • Vth represents the threshold voltage of the first transistor T1
  • VGS represents the voltage between the gate and the source (here, the first electrode) of the third transistor T3
  • K is a voltage related to the third transistor T3 itself. constant value. It can be seen from the above calculation formula of Id that the driving current Id provided by the pixel driving circuit is no longer related to the threshold voltage Vth of the third transistor T3, so that the compensation of the pixel driving circuit can be realized, and the driving transistor (in this case) can be solved.
  • the threshold voltage drift of the third transistor T3) is caused by the process and long-term operation, which eliminates its influence on the driving current Id, thereby improving the display effect of the display device using the same.
  • FIG. 7A is a partial area layout of the overall structure of a display substrate according to some embodiments of the present disclosure.
  • FIG. 7A exemplarily shows the layout of the first pixel circuit D and the first capacitance compensation structure.
  • FIG. 7B is a schematic cross-sectional view of the display substrate shown in FIG. 7A along the line M-N.
  • the display substrate includes a base substrate SUB, and a pixel circuit layer LX1 , a transparent wiring layer LX2 and a light-emitting element layer LX3 sequentially arranged on the base substrate SUB.
  • the pixel circuit layer LX1 includes an active layer AL, a gate layer Gate1, and a source and drain layer SD (eg, includes a first source and drain layer SD1 and a second source and drain layer SD2).
  • the active layer AL may include a semiconductor material
  • the gate layer Gate1 , the first source and drain layers SD1 and the second source and drain layers SD2 may include a metal material or an alloy material.
  • the first pixel circuit includes a thin film transistor including a gate electrode, a source electrode and a drain electrode, the gate electrode is located in the gate electrode layer Gate1, and at least one of the source electrode and the drain electrode is located in the source and drain electrode layer SD.
  • FIG. 7B only schematically shows one thin film transistor in the first pixel circuit.
  • the thin film transistor may be the sixth transistor in the 7T1C pixel driving circuit shown in FIG. 6A . Examples include, but are not limited to.
  • the transparent wiring layer LX2 includes a first transparent wiring layer ITO1 , a second transparent wiring layer ITO2 and a third transparent wiring layer ITO3 .
  • each transparent trace is located on the transparent trace layer LX2.
  • each transparent wiring includes a portion located in the first transparent wiring layer ITO1, the second transparent wiring layer ITO2 and the third transparent wiring layer ITO3, and embodiments of the present disclosure include but are not limited thereto.
  • the first transparent wiring layer ITO1, the second transparent wiring layer ITO2 and the third transparent wiring layer ITO3 may include transparent conductive materials such as transparent metal oxides such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO) etc. to have good light transmittance.
  • the light-emitting element layer LX3 includes an anode layer Anode, a light-emitting layer ELL, and a cathode layer Cathode.
  • the first light-emitting element includes an anode at the anode layer Anode, a light-emitting material at the light-emitting layer ELL, and a cathode at the cathode layer Cathode.
  • the display substrate shown in FIG. 7B may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light emitting layer ELL may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light emitting materials or phosphorescent light emitting materials, and may emit red light, green light, and blue light. , or can emit white light, etc.; and, according to actual needs, the light-emitting layer ELL may further include one or more functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer ELL may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, telluride Cadmium quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the source or drain of the thin film transistor is electrically connected to the first light-emitting element (eg, to the anode of the first light-emitting element) through a transparent trace.
  • the first capacitance compensation structure includes a first capacitance electrode and a second capacitance electrode.
  • the compensation capacitance value of the first capacitance compensation structure is generally proportional to the overlapping area of the first capacitance electrode and the second capacitance electrode, and is proportional to the distance between the first capacitance electrode and the second capacitance electrode (in the vertical direction). distance in the direction of the display substrate) is inversely proportional.
  • the pixel circuit layer LX1 may further include a capacitor plate layer Gate2 .
  • FIG. 7B the pixel circuit layer LX1 may further include a capacitor plate layer Gate2 .
  • one of the first capacitor electrode and the second capacitor electrode is located on the gate layer Gate1
  • the other one of the first capacitor electrode and the second capacitor electrode is located on the capacitor plate layer Gate2 .
  • the source or drain of the thin film transistor is electrically connected to one of the first capacitor electrode and the second capacitor electrode.
  • the other one of the first capacitor electrode and the second capacitor electrode may be electrically connected to a DC signal, for example, may be electrically connected to the aforementioned first power supply line VDD or second power supply line VSS.
  • the other one of the first capacitance electrode and the second capacitance electrode of the plurality of capacitance compensation structures can be an integral structure, so that the manufacturing process can be simplified.
  • the setting manner of the first capacitance compensation structure shown in FIG. 7B is schematic, which is not limited by the embodiments of the present disclosure.
  • one of the first capacitor electrode and the second capacitor electrode may be located at one of the gate layer Gate1, the source and drain layers SD, the transparent wiring layer LX2, the capacitor plate layer Gate2, etc.
  • the other of the first capacitance electrode and the second capacitance electrode may be located in any layer except the one of the above layers, as long as the first capacitance compensation structure formed therefrom can meet the requirements of capacitance compensation.
  • the capacitor plate layer Gate2 can be omitted from the display substrate .
  • a plurality of elements, components, structures and/or parts located on the same layer or disposed on the same layer may generally be composed of the same material and may be formed by the same patterning process.
  • the same film forming process can be used to form a film layer for forming a specific pattern, and then a layer structure formed by patterning the film layer through one patterning process using the same mask.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous.
  • a conductive layer may also be specially provided on the display substrate to form a certain capacitance electrode in the first capacitance compensation structure.
  • the display substrate may further include a first gate insulating layer GI1 , a second gate insulating layer GI2 , an interlayer interlayer ILD, and a passivation layer PVX (for example, can be used as a planarization layer at the same time)
  • Functional layers such as PLN1), planarization layers PLN2-PLN5 and pixel defining layer PDL.
  • these functional layers may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin and other organic insulating materials. It should be noted that the embodiments of the present disclosure do not specifically limit the materials of the aforementioned various functional layers.
  • the setting method of the second pixel circuit may refer to the setting method of the first pixel circuit
  • the setting method of the second light-emitting element may refer to the setting method of the first light-emitting element.
  • the arrangement of the second capacitance compensation structure may refer to the arrangement of the first capacitance compensation structure, which is not limited by the embodiments of the present disclosure. .
  • each layer of the display substrate shown in FIG. 7B is schematic.
  • some functional layers shown can be reduced as required, as long as the display function of the display substrate and the capacitance compensation function of the first capacitance compensation structure are not affected; of course, also Some functional layers not shown (eg, buffer layers, encapsulation layers, etc.) may be added as needed. The embodiments of the present disclosure do not limit this.
  • FIG. 7C is a schematic plan view of the first conductive layer (ie, the gate layer Gate1 ) in the display substrate shown in FIG. 7A .
  • the capacitor plate M1 of the first capacitance compensation structure, the gate of the aforementioned thin film transistor, one capacitor plate Cst1 of the aforementioned storage capacitor Cst, the gate line W1 can all be located in the first conductive layer; it should be noted that the present disclosure includes but is not limited to this.
  • the capacitor plates M1 of each of the first capacitor compensation structures are provided separately.
  • FIG. 7D is a schematic plan view of the second conductive layer (ie, the aforementioned capacitor plate layer Gate2 ) in the display substrate shown in FIG. 7A .
  • the capacitor plate M2 of the first capacitance compensation structure, the other capacitor plate Cst2 of the aforementioned storage capacitor Cst, the reset voltage line W2, etc. can all be located in the second conductive layer; It should be noted that the present disclosure includes but is not limited to this.
  • the capacitor plates M2 of each of the first capacitance compensation structures may be integrally provided, and embodiments of the present disclosure include but are not limited to this.
  • FIG. 7E is a schematic plan view of the stacking of the first conductive layer and the second conductive layer in the display substrate shown in FIG. 7A .
  • the capacitor plate Cst1 and the capacitor plate Cst2 are overlapped to form the storage capacitor Cst; the capacitor plate M1 and the capacitor plate M2 are overlapped to form a capacitor structure.
  • the source or drain of the six transistors T6 are coupled, and the capacitance structure can be used as the first capacitance compensation structure.
  • a shielding part S2 may also be provided in the second conductive layer, and the shielding part is used to shield the active layer of some thin film transistors (for example, the second transistor in FIG. 6A ).
  • a first power supply line may also be disposed in the second conductive layer; for example, the first power supply line may be coupled to the capacitor plate M2 of the first capacitance compensation structure.
  • FIG. 7F is a schematic plan view of the third conductive layer (ie, the aforementioned first source and drain layer SD1 ) in the display substrate shown in FIG. 7A .
  • the capacitor plate M3, the first power line W31, the data signal line W32, etc. of the first capacitance compensation structure may all be located in the third conductive layer; it should be noted that this Disclosure includes, but is not limited to, this.
  • the capacitor plates M3 of each of the first capacitor compensation structures are provided separately.
  • FIG. 7G is a schematic plan view of the stacking of the first conductive layer, the second conductive layer and the third conductive layer in the display substrate shown in FIG. 7A .
  • the capacitor electrode plate M3 and the capacitor electrode plate M2 overlap to form a capacitor structure; in this case, the first capacitance compensation structure may include three capacitor electrode plates (ie, three capacitor electrode plates disposed on different layers)
  • the complex capacitive structure of the capacitor plates M1-M3), at least one of the capacitor plate M1 and the capacitor plate M3 may be coupled to the source or the drain of the sixth transistor T6.
  • an additional capacitance electrode plate is provided on the basis of the two capacitance electrode plates, which increases the way of adjusting the compensation capacitance value of the first capacitance compensation structure.
  • FIG. 7H is a schematic plan view of the fourth conductive layer (ie, the aforementioned second source and drain layer SD2 ) in the display substrate shown in FIG. 7A .
  • the capacitance plate M4 of the first capacitance compensation structure, the traces W4 (for connecting the first pixel circuit and the first capacitance compensation structure), etc. may all be located in the fourth conductive layer; it should be noted that the present disclosure includes but is not limited to this.
  • the capacitor plates M4 of each of the first capacitance compensation structures may be integrally provided, and embodiments of the present disclosure include but are not limited to this.
  • one end of the trace W4 may be coupled to the source or drain of the sixth transistor T6, and the other end of the trace W4 may be coupled to at least one of the capacitor plate M1 and the capacitor plate M3.
  • the first capacitance compensation structure may be a complex capacitance structure including four capacitance plates (ie, capacitance plates M1-M4) disposed on different layers, and at least one of the capacitance plate M1 and the capacitance plate M3 may be is coupled to the source or drain of the sixth transistor T6. It should be understood that, for the first capacitance compensation structure, two additional capacitance electrode plates are provided on the basis of the two capacitance electrode plates, which further increases the way of adjusting the compensation capacitance value of the first capacitance compensation structure.
  • each of the first capacitance compensation structures may include four conductive layers (ie, the first conductive layer, the second conductive layer, and the third conductive layer) disposed on the above-mentioned four conductive layers.
  • the capacitor plates of the first capacitance compensation structure are all in the shape of strips, and the present disclosure includes but is not limited to this.
  • the capacitance plate of the first capacitance compensation structure may also be in a wave shape, a broken line shape, or the like.
  • the capacitance plate of the second capacitance compensation structure may also be in the shape of a strip, a wave shape, a zigzag line, or the like.
  • the display substrate provided by the embodiments of the present disclosure may also include a first board surface F1 and a second board surface F2 , and the first board surface F1 is on the display substrate. It is used for display during operation; the first display area is a transparent display area, which is configured to transmit light incident from the side of the first panel surface F1 to the side of the second panel surface F2.
  • the embodiments of the present disclosure do not limit the shapes of the first display area, the first area, the second display area, the third display area, and the peripheral area.
  • the first display area may be any shape such as a circle (as shown in FIG. 3A ), a rectangle, a hexagon, an irregular figure, and the like.
  • the parasitic capacitance of the transparent trace can be compensated by the first capacitance compensation structure, so that the luminous brightness of different first light-emitting elements has better uniformity, so as to alleviate or solve the problem of the first light-emitting element.
  • the problem of uneven brightness in the display area especially the problem of uneven brightness when the first display area displays low grayscale, thereby improving the display effect of the first display area.
  • FIG. 8 is a schematic plan view of a display device according to some embodiments of the present disclosure.
  • the display device 300 may include the display substrate and the sensor S shown in FIG. 3A .
  • the sensor S (refer to the sensor 120 in the display device 100 ) may be disposed on the display substrate (refer to the display device 100 in the display device 100 ).
  • the orthographic projection of the sensor S on the display substrate at least partially overlaps the first display region Rb, and the sensor S is configured to receive light incident from the first panel surface F1 side.
  • the sensor S and the first display area Rb are stacked in the normal direction of the display substrate (ie, the direction perpendicular to the first panel F1 or the second panel F2 of the display substrate), and the sensor S can receive and process through
  • the light signal of the first display area Rb may be visible light, infrared light, or the like.
  • the first display region Rb allows light incident from the side of the first panel F1 to be at least partially transmitted to the side of the second panel F2.
  • only light-emitting elements ie, first light-emitting elements
  • no pixel circuits ie, first pixel circuits
  • the light transmittance of the first display region Rb can be improved.
  • the orthographic projection of the sensor S on the display substrate is located in the first display area Rb when the direct type setting is adopted.
  • the light can be directed from the direction parallel to the display substrate (ie, parallel to the first panel F1 or the second panel of the display substrate).
  • the orthographic projection of the sensor S on the display substrate partially overlaps with the first display area Rb. At this time, since the light can propagate laterally to the sensor S, it is not necessary for the sensor S to be completely located directly below the first display area Rb.
  • the sensor S may be an image sensor, which may be used to collect an image of the external environment facing the light collecting surface of the sensor S, such as a CMOS image sensor or a CCD image sensor.
  • the sensor S may also be an infrared sensor, a distance sensor, or the like.
  • the sensor S in the case where the display device 300 is a mobile terminal such as a mobile phone, a notebook, etc., the sensor S can be implemented as a camera of the mobile terminal such as a mobile phone, a notebook, etc., and can also include, for example, a lens, a reflector, or an optical waveguide as required. optics to modulate the optical path.
  • the sensor S may include photosensitive pixels arranged in an array.
  • each photosensitive pixel may include a photodetector (eg, photodiode, phototransistor) and a switching transistor (eg, thin film transistor).
  • a photodetector eg, photodiode, phototransistor
  • a switching transistor eg, thin film transistor
  • a photodiode can convert an optical signal irradiated thereon into an electrical signal
  • a switching transistor can be electrically connected to the photodiode to control whether the photodiode is in the state of collecting the optical signal and when the optical signal is collected.
  • the display device 300 can be any electronic device having a display function, such as a smart phone, a notebook computer, a tablet computer, a TV, and the like.
  • the smart phone or tablet computer can have a full-screen design; for example, for the display substrate shown in FIG. 3B and FIG. 3C , the peripheral area 40 that cannot be displayed can be bent Folded to the side or back of the display device to achieve a full-screen design; of course, for the display substrate shown in FIG. 3C , the display substrate may also not include the peripheral area 40 to achieve a full-screen design.
  • the smartphone or tablet computer can also perform operations such as image capturing, distance perception, light intensity perception, etc. through the under-screen sensor (eg, camera, infrared sensor, etc.).

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Abstract

一种显示基板及显示装置。该显示基板包括第一显示区和至少部分围绕第一显示区的第一区域；第一显示区包括多个第一发光元件，第一区域包括多个第一像素电路和至少一个第一电容补偿结构，显示基板包括从第一区域延伸到第一显示区的多条透明走线；至少一个第一像素电路通过至少一条对透明走线与至少一个发光元件电连接，且被配置为控制流经该至少一个第一像素电路、该至少一条透明走线以及该至少一个第一发光元件且驱动该至少一个第一发光元件发光的驱动电流；该至少一个第一电容补偿结构与至少一条透明走线耦接，且被配置为补偿由与该至少一个第一电容补偿结构耦接的该至少一条透明走线导致的寄生电容。

Description

显示基板及显示装置 技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
随着手机等显示电子产品的发展，显示屏的屏占比的提升成为一种产品趋势，前置摄像头等手机必备的功能元件成为制约屏占比提升的一大因素。针对这个问题，业界提出了将摄像头与显示基板结合到一显示装置中的被称为“屏下摄像头”的方案。在这样的方案中，显示装置包括显示基板和位于该显示基板下方的摄像头。显示装置的具有屏下摄像头的区域可以与其他区域一样发光并进行显示，并同时具有摄像功能。
发明内容
本公开至少一些实施例提供一种显示基板，该显示基板包括第一显示区和至少部分围绕所述第一显示区的第一区域。所述第一显示区包括多个第一发光元件，所述第一区域包括多个第一像素电路和至少一个第一电容补偿结构，所述显示基板包括从所述第一区域延伸到所述第一显示区的多条透明走线；所述多个第一像素电路中的至少一个第一像素电路通过所述多条透明走线中的至少一条透明走线与所述多个第一发光元件中的至少一个第一发光元件电连接，且被配置为控制流经所述至少一个第一像素电路、所述至少一条透明走线以及所述至少一个第一发光元件且驱动所述至少一个第一发光元件发光的驱动电流；所述至少一个第一电容补偿结构与所述多条透明走线中的至少一条透明走线耦接，且被配置为补偿由所述至少一条透明走线导致的寄生电容。
例如，在本公开的一些实施例提供的显示基板中，所述至少一个第一电容补偿结构提供的补偿电容和与所述至少一个第一电容补偿结构耦接的所述至少一条透明走线导致的寄生电容并联。
例如，在本公开的一些实施例提供的显示基板中，与所述至少一个第一电容补偿结构耦接的所述至少一条透明走线的寄生电容值与所述至少一个第一电容补偿结构的补偿电容值之和大致等于目标电容值。
例如，在本公开的一些实施例提供的显示基板中，所述目标电容值大于或等于所述多条透明走线的寄生电容值的最大值。
例如，在本公开的一些实施例提供的显示基板中，所述多条透明走线中至少存在一条透明走线，该条透明走线的寄生电容值大致等于所述目标电容值，且该条透明走线不与所述至少一个第一电容补偿结构耦接。
例如，在本公开的一些实施例提供的显示基板中，所述多条透明走线被划分为多个透明走线组，所述多个透明走线组中的每个透明走线组包括至少一条透明走线；所述每个透 明走线组中的所述至少一条透明走线的寄生电容值的平均值作为所述每个透明走线组的平均寄生电容值；所述目标电容值大于或等于所述多个透明走线组的平均寄生电容值的最大值。
例如，在本公开的一些实施例提供的显示基板中，所述多个透明走线组中至少存在一个透明走线组，该透明走线组的平均寄生电容值大致等于所述目标电容值，且该透明走线组中的所述至少一条透明走线不与所述至少一个第一电容补偿结构耦接。
例如，在本公开的一些实施例提供的显示基板中，所述第一区域包括周边区域，所述周边区域位于所述第一显示区和所述显示基板的至少一侧边缘之间；所述多个第一像素电路和所述多个第一电容补偿结构均位于所述周边区域中。
例如，在本公开的一些实施例提供的显示基板中，所述第一区域包括第二显示区，所述第二显示区至少部分围绕所述第一显示区，所述第二显示区包括第二像素单元，所述第二像素单元包括第二发光元件和第二像素电路，所述第二像素电路与所述第二发光元件电连接，且被配置为控制流经所述第二像素电路以及所述第二发光元件且驱动所述第二发光元件发光的驱动电流；所述多个第一像素电路和所述多个第一电容补偿结构均位于所述第二显示区中。
例如，在本公开的一些实施例提供的显示基板中，所述第一区域包括第二显示区和周边区域，所述第二显示区至少部分围绕所述第一显示区，所述周边区域位于所述第一显示区和所述显示基板的至少一侧边缘之间；所述第二显示区包括第二像素单元，所述第二像素单元包括第二发光元件和第二像素电路，所述第二像素电路与所述第二发光元件电连接，且被配置为控制流经所述第二像素电路以及所述第二发光元件且驱动所述第二发光元件发光的驱动电流；所述多个第一像素电路中的一部分第一像素电路和所述多个第一电容补偿结构中的一部分第一电容补偿结构位于所述周边区域中，所述多个第一像素电路中的另一部分第一像素电路和所述多个第一电容补偿结构中的另一部分第一电容补偿结构位于所述第二显示区中。
例如，在本公开的一些实施例提供的显示基板中，所述第二显示区还包括第二电容补偿结构，第二电容补偿结构与所述第二像素电路和所述第二发光元件耦接，且被配置为向所述第二像素电路提供补偿电容；所述第二电容补偿结构的补偿电容值大致等于所述目标电容值。
例如，在本公开的一些实施例提供的显示基板中，在所述显示基板所在平面内，所述至少一个第一电容补偿结构位于与所述至少一个第一电容补偿结构对应的第一像素电路的远离所述第一显示区的一侧。
例如，在本公开的一些实施例提供的显示基板中，所述显示基板包括衬底基板以及在所述衬底基板上依次设置的像素电路层、透明走线层和发光元件层；所述像素电路层包括栅极层和源漏极层；所述多个第一发光元件中的每个第一发光元件位于所述发光元件层；所述多个第一像素电路中的每个第一像素电路包括薄膜晶体管，所述薄膜晶体管包括栅极、 源极和漏极，所述栅极位于所述栅极层，所述源极和所述漏极至少之一位于所述源漏极层；所述多条透明走线中的每条透明走线位于所述透明走线层；所述至少一个第一电容补偿结构包括第一电容电极和第二电容电极，所述第一电容电极和所述第二电容电极之一位于所述栅极层、所述源漏极层或所述透明走线层。
例如，在本公开的一些实施例提供的显示基板中，所述源极或漏极与所述第一电容电极和所述第二电容电极之一电连接，所述源极或漏极还通过所述透明走线与所述第一发光元件电连接。
例如，在本公开的一些实施例提供的显示基板中，所述像素电路层还包括电容极板层，所述第一电容电极和所述第二电容电极之另一位于所述电容极板层。
例如，在本公开的一些实施例提供的显示基板中，所述至少一个第一电容补偿结构包括多个电容补偿结构，所述多个电容补偿结构的所述第一电容电极和所述第二电容电极之另一为一体结构。
例如，在本公开的一些实施例提供的显示基板中，所述显示基板包括第一板面和第二板面，所述第一板面在所述显示基板工作中用于显示；所述第一显示区为透明显示区，被配置为能将从所述第一板面一侧入射的光透射到所述第二板面一侧。
本公开至少一些实施例还提供一种显示装置，包括本公开任一实施例提供的显示基板。
例如，本公开的一些实施例提供的显示装置还包括传感器。所述显示基板包括第一板面和第二板面，所述第一板面在工作中用于显示；所述第一显示区为透明显示区，被配置为能将从所述第一板面一侧入射的光透射到所述第二板面一侧；所述传感器设置于所述显示基板的所述第二板面一侧，所述传感器在所述显示基板上的正投影与所述第一显示区至少部分重叠，所述传感器被配置为能接收从所述第一板面一侧入射的光。
例如，在本公开的一些实施例提供的显示装置中，所述传感器包括图像传感器、红外传感器、距离传感器至少之一。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的平面示意图；
图1B为一种显示装置的局部结构的截面示意图；
图1C为图1A所示的显示基板的局部放大示意图；
图2A为一种透明走线与第一发光元件耦接的等效电路示意图；
图2B为流经图2A所示的第一发光元件的驱动电流的变化示意图；
图3A为本公开一些实施例提供的一种显示基板的平面示意图；
图3B为本公开一些实施例提供的一种显示基板的局部放大示意图；
图3C为本公开一些实施例提供的另一种显示基板的局部放大示意图；
图4为本公开一些实施例提供的一种透明走线与第一电容补偿结构和第一发光元件耦接的等效电路示意图；
图5A为本公开一些实施例提供的一种像素分组、透明走线组、像素电路分组和补偿结构组耦接的平面示意图；
图5B为本公开一些实施例提供的另一种像素分组、透明走线组、像素电路分组和补偿结构组耦接的平面示意图；
图6A为本公开一些实施例提供的一种像素驱动电路的电路结构示意图；
图6B为本公开一些实施例提供的一种像素驱动电路的驱动方法的信号时序图；
图7A为本公开一些实施例提供的一种显示基板的整体结构的局部区域版图；
图7B为图6A所示的显示基板沿M-N线的截面示意图；
图7C为图7A所示的显示基板中的第一导电层的平面示意图；
图7D为图7A所示的显示基板中的第二导电层的平面示意图；
图7E为图7A所示的显示基板中的第一导电层与第二导电层堆叠的平面示意图；
图7F为图7A所示的显示基板中的第三导电层的平面示意图；
图7G为图7A所示的显示基板中的第一导电层、第二导电层与第三导电层堆叠的平面示意图；
图7H为图7A所示的显示基板中的第四导电层的平面示意图；
图7I为图7A所示的显示基板中的第一导电层、第二导电层、第三导电层与第四导电层堆叠的平面示意图；
图8为本公开一些实施例提供的一种显示装置的平面示意图。
具体实施方式
为了使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在“屏下摄像头”的设计方案中，可以将用于安装传感器(例如图像传感器、红外传感器、距离传感器)等部件的部分显示区设计为透明显示区，由此该透明显示区可以在实现显示功能的同时，为安装传感器等部件提供便利，从而在基本不影响透明显示区的显示功能的情形下，这些传感器能够通过透明显示区执行例如成像、红外感应、距离感应等功能，由此有助于实现具有全面屏的电子设备。
图1A为一种显示基板的平面示意图。例如，如图1A所示，该显示基板100包括显示区以及围绕该显示区的周边区域40，该显示区包括透明显示区10、过渡显示区20和主体显示区30。例如，透明显示区10允许光从显示基板100的一侧透射到显示基板100的另一侧。
图1B为一种显示装置的局部结构的截面示意图。例如，如图1B所示，该显示装置100包括图1A所示的显示基板110以及传感器120。显示基板110具有第一板面F1和第二板面F2，其中，第一板面在显示基板110工作中用于显示(即面向用户)。传感器120设置在第二板面F2一侧(即显示基板110的远离用户的一侧，也即显示基板110的非显示侧)，且传感器120在显示基板上的正投影与透明显示区10至少部分重叠。传感器120被配置为能接收从第一板面F1一侧(即显示基板110的显示侧)入射的光。
图1C为图1A所示的显示基板的局部放大示意图。例如，如图1C所示，主体显示区30为主要的显示区域(或称为常规显示区域)；相对于透明显示区10和过渡显示区20，主体显示区30可以具有较高的分辨率(PPI，Pixel Per Inch)，即主体显示区30内排布有密度较高的用于显示的像素(一个像素可以包括多个子像素)。例如，在主体显示区30中，每个子像素(如主体显示区30中的方框P所示)包括发光元件以及驱动发光元件的像素电路。
例如，如图1C所示，透明显示区10和/或过渡显示区20内排布有密度较低的用于显示的像素(一个像素可以包括多个子像素)。例如，透明显示区10和过渡显示区20具有相同的分辨率。
例如，与主体显示区30相比较，透明显示区10和/或过渡显示区20内排布有密度相等的用于显示的像素(一个像素可以包括多个子像素)，且透明显示区10和/或过渡显示区20内像素驱动电路面积小于主体显示区30内像素驱动电路面积。
透明显示区10可以允许从显示基板110的显示侧入射的光透过显示基板110而到达显示基板110的非显示侧，从而用于位于显示基板110的非显示侧的传感器120等部件的正常工作。当然，透明显示区10也可以允许从显示基板110的非显示侧120发出的光透过显示基板110而到达显示基板110的显示侧。但是，由于子像素的像素电路通常不透光，为了提高透明显示区10的透光性，可以将透明显示区10的子像素的发光元件与驱动该发光元件的像素电路从物理位置上分离。
例如，如图1C所示，透明显示区10中的子像素(如透明显示区10中的方框A所示)仅保留发光元件，透明显示区10中的子像素的像素电路可以设置在过渡显示区20，如过渡 显示区20中的方框D所示，因此占据了过渡显示区20的部分空间；而过渡显示区20的剩余空间的部分或全部用于设置过渡显示区20的子像素(如过渡显示区20中的方框P所示)，过渡显示区中的子像素包括发光元件与驱动该发光元件的像素电路。例如，如图1C所示，过渡显示区20中可以存在空闲区域(如过渡显示区20中的方框V所示)，在空闲区域中，通常不设置发光元件，也不设置像素电路。
例如，如图1C所示，透明显示区10中的子像素的发光元件通过走线L(如图1C中的黑色线段所示)与过渡显示区20中对应的像素电路电连接。为了提高透明显示区1的透光性，上述走线L通常为透明走线，或者，走线L的至少位于透明显示区10中的部分是透明的(在此情况下，即使走线L的其余部分不透明，在本公开中也可认为走线L为透明走线)。例如，透明走线可以采用透明导电材料，例如透明金属氧化物，例如氧化铟锡(ITO)、铟镓锌氧化物(IGZO)等，以具有良好的透光性。需要说明的是，在本公开中，“透明”、“透光”只要求具有一定的透光率即可，例如透光率大于0，而不要求透光率为100％。例如，一般地，若任一结构或区域等的透光率大于某一数值(例如，40％、45％、50％等)，即可认为该结构或区域等“透明”、“透光”。
需要说明的是，在图1C中，方框P可以表示一个子像素，方框A可以表示一个发光元件，方框D表示一个像素电路，走线L可以表示连接一个发光元件A和一个像素电路D的一条透明走线；或者，在图1C中，方框P可以表示一个像素(即一个子像素组，包括多个子像素)，方框A可以表示表示一组发光元件(包括一个像素中的多个发光元件)，方框D可以表示一组像素电路(包括一个像素中的多个发光元件对应的多个像素电路)，走线L可以表示连接一组发光元件A和一组像素电路D的一组透明走线(包括多条透明走线)。
图2A为一种透明走线L与第一发光元件LE耦接的等效电路示意图。例如，参考图1C和图2A所示，透明走线L的一端与像素电路(图2A中未示出)耦接，透明走线L的另一端与发光元件EL耦接(例如，与发光元件EL的阳极耦接)。参考图1C和图2A，透明走线L与设置于其附近的元器件、布线及其他电学结构等存在耦合效应，因而，透明走线L上通常存在寄生电容C_L。对于不同的透明走线L(通常可认为不同的透明走线L具有相同的宽度和相同的厚度)，其长度不尽相同，其跨越的像素区域(像素区域中通常存在各种元器件、布线及其他电学结构等)也不尽相同，因此，不同的透明走线L的寄生电容C_L的大小也不尽相同。一般地，透明走线L的长度越长、跨越的像素区域越多，其寄生电容C_L越大。
图2B为流经图2A所示的第一发光元件LE的驱动电流的变化示意图。参考图2A和图2B，在第一像素电路提供驱动电流时，首先，驱动电流的一部分会用于对透明走线L的寄生电容C_L进行充电，驱动电流的剩余部分会流经第一发光元件LE(参考图2A中的直线箭头所示)，直到寄生电容C_L的电压达到电学平衡(即电压不再变化)，驱动电流才会全部作用于第一发光元件LE。因此，实际流经第一发光元件LE的驱动电流会经历一个由小到大直至稳定的过程(参考图2B中的I1曲线或I2曲线所示)，寄生电容C_L越大，实 际流经第一发光元件LE的驱动电流到达稳定状态所需的时间越长。
考虑两个第一发光元件LE1和LE2，其对应的透明走线L的寄生电容为C_L1和C_L2(不防假设C_L1和C_L2)，同时忽略这两个第一发光元件LE1和LE2的差异及其对应的第一像素电路的差异，则在显示同一灰阶(即这两个第一发光元件LE1和LE2对应的第一像素电路提供的驱动电流的大小基本相同)的情况下，实际流经这两个第一发光元件LE1和LE2的的驱动电流的变化分别如图2B中的I1曲线和I2曲线所示，即第一发光元件LE1在一个相对较短的时间段内没有根据驱动电流的稳定值(即第一像素电路提供的驱动电流)进行发光，而第一发光元件LE2在一个相对较长的时间段内没有根据驱动电流的稳定值进行发光。因此，相对于所显示的灰阶对应的预期的发光亮度而言，两个第一发光元件LE1和LE2的发光亮度均降低了；而且，第一发光元件LE2的发光亮度的降低幅度大于第一发光元件LE1的发光亮度的降低幅度，即两个第一发光元件LE1和LE2亮度不均，该现象在低灰阶下表现得更为明显。
本公开至少一些实施例提供一种显示基板，该显示基板包括第一显示区和至少部分围绕所述第一显示区的第一区域；第一显示区包括多个第一发光元件，第一区域包括多个第一像素电路和至少一个第一电容补偿结构，显示基板包括从第一区域延伸到第一显示区的多条透明走线；该多个第一像素电路中的至少一个第一像素电路通过该多条透明走线中的至少一条透明走线与该多个第一发光元件中的至少一个发光元件电连接，且被配置为控制流经该至少一个第一像素电路、该至少一条透明走线以及该至少一个第一发光元件且驱动该至少一个第一发光元件发光的驱动电流；该至少一个第一电容补偿结构与该多条透明走线中的至少一条透明走线耦接，且被配置为补偿由与该至少一个第一电容补偿结构耦接的该至少一条透明走线导致的寄生电容。
本公开的一些实施例还提供对应于上述显示基板的显示装置。
本公开的实施例提供的显示基板，可以通过第一电容补偿结构对透明走线的寄生电容进行补偿，使得不同的第一发光元件的发光亮度具有较好的均一性，以缓解或解决第一显示区亮度不均的问题(尤其是第一显示区显示低灰阶时存在的亮度不均的问题)，进而改善第一显示区的显示效果。
下面结合附图对本公开的几个实施例进行详细说明。需要说明的是，为了保持本公开实施例的说明的清楚和简要，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
图3A为本公开一些实施例提供的一种显示基板的平面示意图，图3B为本公开一些实施例提供的一种显示基板的局部放大示意图，图3C为本公开一些实施例提供的另一种显示基板的局部放大示意图。
例如，如图3A所示，该显示基板210包括第一显示区Rb和至少部分围绕该第一显示区Rb的第一区域Ra。例如，参考图1A所示，类似于图1A所示的显示基板110，显示基 板210也可以包括显示区(参考显示基板110的显示区)以及围绕该显示区的周边区域40(参考显示基板110的周边区域40)，显示区可以包括第一显示区10(参考显示基板110的透明显示区10)、第二显示区20(参考显示基板110的过渡显示区20)和第三显示区30(参考显示基板110的过渡显示区10)；在此情况下，第一显示区Rb即为第一显示区10，第一区域Ra包括第二显示区20、第三显示区30以及周边区域40。
例如，在一些实施例中，结合图1A以及图3A-3C所示，第一显示区Rb(即第一显示区10)包括多个第一发光元件A，第一区域Ra包括多个第一像素电路D和至少一个第一电容补偿结构C，显示基板210包括从第一区域Ra延伸到第一显示区Rb的多条透明走线L；每个第一像素电路D通过一条对应的透明走线L与一个对应的第一发光元件A电连接，且每个第一像素电路D被配置为控制流经该第一像素电路D、该对应的透明走线L以及该对应的第一发光元件A且驱动该对应的第一发光元件A发光的驱动电流；该至少一个第一电容补偿结构C与该多条透明走线L中的至少一条透明走线耦接，且被配置为补偿由该至少一条透明走线导致的寄生电容。
图4为本公开一些实施例提供的一种透明走线L与第一电容补偿结构C和第一发光元件EL(即第一发光元件A)耦接的等效电路示意图。参考图3B、图3C和图4所示，透明走线L(如图3B和图3C中连接第一像素电路D和第一发光元件A的线段或折线段所示)的一端与第一像素电路D(图4中未示出)和第一补偿电容结构C耦接，透明走线L的另一端与发光元件EL耦接(例如，与发光元件EL的阳极耦接)。例如，如图4所示，第一电容补偿结构C提供的补偿电容C与透明走线L导致的寄生电容C_L并联，从而，第一电容补偿结构C的补偿电容C可以用于补偿透明走线L导致的寄生电容C_L。例如，在一些实施例中，透明走线L的寄生电容值C_L与第一电容补偿结构C的补偿电容值之和可以大致等于同一个目标电容值；从而，参考前述图2B的相关描述可知，通过这种方式，可以将流经各第一发光元件LE的驱动电流的变化曲线调整为基本一致。也即是说，通过设置第一电容补偿结构C，可以使第一显示区10中的第一发光元件LE在显示同一灰阶时的发光亮度基本一致，从而，可以缓解或者解决第一显示区亮度不均的问题，改善第一显示区的显示效果。
需要说明的是，在本公开中，“a大致等于b”表示a的取值在b的取值上下浮动x％以内；例如，x的取值范围可以为3～10，本公开的实施例包括但不限于此。例如，x可以等于3、5、7、10等，本公开的实施例包括但不限于此。
例如，在一些实施例中，上述目标电容值可以大于或等于各透明走线L的寄生电容值C_L的最大值。例如，在一些实施例中，目标电容值可以等于各透明走线L的寄生电容值C_L的最大值，在此情况下，寄生电容值大致等于该目标电容值的透明走线L不需要进行补偿，也即，寄生电容值大致等于该目标电容值的透明走线L可以不与第一电容补偿结构C耦接；从而，可以减少第一电容补偿结构C的布置数量，节省显示基板的空间。
例如，在一些实施例中，结合图3A和图3B所示，第一区域Ra可以包括周边区域40， 周边区域40位于第一显示区10和显示基板的至少一侧边缘(如图3B中的“边框”所示)。例如，如图3B所示，显示基板210中的第一像素电路D和第一电容补偿结构C可以全部位于周边区域40中，每个第一电容补偿结构C与对应的第一像素电路D耦接。例如，如图3B所示，互相对应的第一电容补偿结构C、第一像素电路D和透明走线L耦接于同一节点(如图3B中连接第一电容补偿结构C和第一像素电路D的线段的位于方框D中的端点所示，该端点与透明走线L的一个端点重合)。
例如，在一些实施例中，在图3B所示的显示基板中，第一区域Ra还可以包括第二显示区20和第三显示区30。如图3B所示，第二显示区包括第二像素单元P，第二像素单元P可以包括第二发光元件(图3B中未示出)和第二像素电路(图3B中未示出)。例如，第二像素电路与第二发光元件电连接(连接路径中不包括透明走线L)，且被配置为控制流经第二像素电路以及第二发光元件且驱动第二发光元件发光的驱动电流。同样地，第三显示区30也包括第二像素单元P。例如，如图3B所示，第二显示区20中还可以存在空闲区域(如图3B的第二显示区20中的方框V所示)，在空闲区域中，通常不设置发光元件，也不设置像素电路。例如，第二显示区20的分辨率通常可以大于或等于第一显示区10的分辨率，而第三显示区30的分辨率通常可以大于或等于第二显示区20/第一显示区10的分辨率，本公开的实施例包括但不限于此。
例如，在一些实施例中，在图3B所示的显示基板中，至少部分透明走线L可以延伸经过第二显示区20。
应当理解的是，与图1C所示的显示基板相比，在图3B所示的显示基板中，第二显示区20中不需要设置第一像素电路D，因此，第二显示区20中的第二像素单元P可以具有与第三显示区30中的第二像素单元P相同的密集排列结构。也就是说，在一些实施例中，可以在图3B所示的显示基板的第二显示区20中的空闲区域V中设置第二像素单元，从而使得第二显示区20具有与第三显示区30相同的像素单元排列结构，也即，第二显示区20的分辨率与第三显示区30的分辨率相同。
例如，在一些实施例中，结合图3A和图3C所示，第一区域Ra可以包括第二显示区20，第二显示区20至少部分围绕第一显示区10。例如，如图3C所示，第二显示区20包括第二像素单元P，第二像素单元P可以包括第二发光元件(图3C中未示出)和第二像素电路(图3C中未示出)。例如，第二像素电路与第二发光元件电连接(连接路径中不包括透明走线)，且被配置为控制流经第二像素电路以及第二发光元件且驱动第二发光元件发光的驱动电流。例如，如图3C所示，显示基板210中的第一像素电路D和第一电容补偿结构C可以全部位于第二显示区40中，每个第一电容补偿结构C与对应的第一像素电路D耦接。例如，如图3C所示，互相对应的第一电容补偿结构C、第一像素电路D和透明走线L耦接于同一节点(如图3C中连接第一电容补偿结构C和第一像素电路D的线段的位于方框D中的端点所示，该端点与透明走线L的一个端点重合)。例如，如图3C所示，第二显示区20中还可以存在空闲区域(如图3C的第二显示区20中的方框V所示)，在空闲区域中， 通常不设置发光元件，也不设置像素电路。
例如，在一些实施例中，结合图3A-3C所示，一部分第一像素电路D和一部分第一电容补偿结构C可以位于周边区域40中，而另一部分第一像素电路D和另一部分第一电容补偿结构C位于第二显示区20中。在此情况下，位于周边区域40中的第一像素电路D和第一电容补偿结构C的布局及其他细节可以参考图3B所示的实施例的相关描述，位于第二显示区20中的第一像素电路D和第一电容补偿结构C的布局及其他细节可以参考图3C所示的实施例的相关描述，在此均不再重复赘述。从而，一方面可以避免在周边区域40中设置过多的第一像素电路D和第一电容补偿结构C而导致的部分透明走线的寄生电容偏大的问题，另一方面还可以避免周边区域40占据过大的显示基板面积而导致显示区面积减小的问题。
例如，在一些实施例中，为了简化第一电容补偿结构C的设计和布局，可以对透明走线L进行分组补偿。例如，可以将多条透明走线划分为多个透明走线组，每个透明走线组包括至少一条透明走线。例如，在透明走线组包括多条透明走线的情况下，该多条透明走线的寄生电容值大致相等。例如，可以将每个透明走线组中的该至少一条透明走线的寄生电容值的平均值作为每个透明走线组的平均寄生电容值。例如，在透明走线组包括一条透明走线的情况下，该条透明走线的寄生电容值(视为寄生电容值的平均值)作为该透明走线组的平均寄生电容值；在透明走线组包括多条透明走线的情况下，该多条透明走线的寄生电容值的平均值作为该透明走线组的平均寄生电容值。例如，目标电容值大于或等于各透明走线组的平均寄生电容值的最大值。
例如，在一些实施例中，可以将每个透明走线组中的透明走线对应的第一发光元件作为一个像素分组，将每个透明走线组中的透明走线对应的像素电路作为一个像素电路分组，将每个透明走线组中的透明走线对应的第一电容补偿结构作为一个补偿结构组。例如，在一些实施例中，目标电容值等于透明走线组的平均寄生电容值的最大值，在此情况下，平均寄生电容值大致等于该目标电容值的透明走线组中的透明走线不需要进行补偿，也即，平均寄生电容值大致等于该目标电容值的透明走线组不需要设置与之对应的补偿结构组。也即，寄生电容值大致等于该目标电容值的透明走线可以不与第一电容补偿结构C耦接。从而，可以减少补偿结构组的布置数量，也即可以减少第一电容补偿结构C的布置数量，进而节省显示基板的空间。
应当理解的是，对应于上述分组补偿方案，可以将图3B和图3C中的方框A、方框D、方框C分别视作一个像素分组(包括第一发光元件)、一个像素电路分组、一个补偿结构组。类似地，也可以将图3B和图3C中的方框P视作一个像素分组(包括第二发光元件和第二像素电路)。
图5A为本公开一些实施例提供的一种像素分组、透明走线组、像素电路分组和补偿结构组耦接的平面示意图。图5A示出了像素电路分组D和补偿结构组C位于周边区域40中的情形。示意性地，图5A示出了像素分组A包括3个第一发光元件、透明走线组L包括3 条透明走线、像素电路分组包括3个第一像素电路、补偿结构组C包括3个第一电容补偿结构的情形。如图5A所示，每个像素分组A中的第一发光元件通过对应的透明走线组L中国的透明走线与对应的像素电路分组中的第一像素电路电连接，像素电路分组中的第一像素电路还与对应的补偿结构组中的第一电容补偿结构耦接。例如，如图5A所示，透明走线与第一电容补偿结构耦接于同一节点(如图5A的像素电路分组D中的灰色圆点所示)。
图5B为本公开一些实施例提供的另一种像素分组、透明走线组、像素电路分组和补偿结构组耦接的平面示意图。图5B示出了像素电路分组D和补偿结构组C位于第二显示区20中的情形。示意性地，图5B示出了像素分组A包括3个第一发光元件、透明走线组L包括3条透明走线、像素电路分组包括3个第一像素电路、补偿结构组C包括3个第一电容补偿结构的情形。如图5B所示，每个像素分组A中的第一发光元件通过对应的透明走线组L中国的透明走线与对应的像素电路分组中的第一像素电路电连接，像素电路分组中的第一像素电路还与对应的补偿结构组中的第一电容补偿结构耦接。例如，如图5B所示，透明走线与第一电容补偿结构耦接于同一节点(如图5B的像素电路分组D中的灰色圆点所示)。
需要说明的是，在实际应用中，如图3B和图3C所示，第一发光元件、第一像素电路、第一电容补偿结构、第二像素单元在各自所在的显示区中通常呈阵列排布。另外，图3B和图3C中的透明走线L的布局均是示意性的，本公开的实施例对此不作限制。在实际应用中，在方便制作的基础上，可以根据实际需要对透明走线进行合理布局，以尽量减小各透明走线的寄生电容值的差异，从而可以减少第一电容补偿结构的补偿电容值，进而可以减少第一电容补偿结构所占用的空间。
还需要说明的是，本公开的实施例对第一发光元件、第一像素电路、第一电容补偿结构、第二像素单元的具体结构均不作限制。例如，为了简化设计和便于制造，第一发光元件的具体结构可以与第二像素单元中的第二发光元件的具体结构相同，第一像素电路的具体结构可以与第二像素单元中的第二像素电路的具体结构相同，本公开的实施例包括但不限于此。
例如，为了实现第二显示区20与第一显示区10一致的PPI，第一发光元件在衬底基板上的投影面积小于与第二像素单元中的第二发光元件在衬底基板上的投影面积，第一像素电路在衬底基板上的投影面积小于第二像素单元中的第二像素电路在衬底基板上的投影面积，本公开的实施例包括但不限于此。例如，在一些实施例中，如图3B、图3C、图5A和图5B所示，在显示基板所在平面内，第一电容补偿结构可以设置于对应的第一像素电路的远离第一显示区10的一侧，从而可以方便透明走线的布局。
例如，在一些实施例中，为了使第二显示区20与第一显示区10的亮度均匀，可以对第二显示区20中的第二像素单元P进行电容补偿。例如，第二显示区20还可以包括第二电容补偿结构，第二电容补偿结构与第二像素单元P中的第二像素电路和第二发光元件耦接，且被配置为向第二像素电路提供补偿电容。例如，第二电容补偿结构的补偿电容值大 致等于目标电容值，从而，参考前述图2B的相关描述可知，通过这种方式，可以将流经第二发光元件的驱动电流的变化曲线调整为与流经第一发光元件的驱动电流的变化曲线基本一致，从而，可以使第二显示区20与第一显示区10的亮度均匀，改善第一显示区10和第二显示区20的整体显示效果。
需要说明的是，在实际应用中，可以通过仿真模拟和/或实验测量等技术手段确定透明走线的寄生电筒值和第一电容补偿结构的补偿电容值。
例如，在一些实施例中，第一像素电路和第二像素电路可以采用常见的2T1C、4T1C、4T2C、7T1C等像素驱动电路，但不限于此。本公开对第一像素电路和第二像素电路的具体结构不作限制。示例性地，图6A示出了一种7T1C像素驱动电路。如图6A所示，该7T1C像素驱动电路包括第一至第七晶体管T1-T7和存储电容Cst。
例如，如图6A所示，第一晶体管T1的栅极与第一复位信号端(或第一复位信号线)连接以接收第一复位信号Reset1，第一晶体管T1的第一极与第一复位电压端(或第一复位电压线)连接以接收第一复位电压Vinit1，第一晶体管T1的第二极与第一节点N1连接；第二晶体管T2的栅极与扫描信号端(或扫描信号线)连接以接收扫描信号Gate，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接；第三晶体管T3的栅极与第一节点N1连接，第三晶体管T2的第一极与第三节点N3连接，第二晶体管T3的第二极与第二节点N3连接；第四晶体管T4的栅极与扫描信号端(或扫描信号线)连接以接收扫描信号Gate，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与数据信号端(或数据信号线)连接以接收数据信号Vdata；第五晶体管T5的栅极与发光控制信号端(或发光控制信号线)连接以接收发光控制信号EM，第五晶体管T5的第一极与第二节点N2连接，第五晶体管T5的第二极与第一电源端(或第一电源线)连接以接收第一电源电压VDD(例如，高电压)；第六晶体管T6的栅极与发光控制信号端(或发光控制信号线)连接以接收发光控制信号EM，第六晶体管T6的第一极与第四节点N4连接，第六晶体管T6的第二极与第三节点N3连接；第七晶体管T7的栅极与第二复位信号端(或第二复位信号线)连接以接收第二复位信号Reset2，第七晶体管T7的第一极与第二复位电压端(或第二复位电压线)连接以接收第二复位电压Vinit2，第七晶体管T7的第二极与第四节点N4连接；存储电容Cst的第一端与第一节点N1耦接，存储电容Cst的第二端与第一电源端(或第一电源线)耦接以接收第一电源电压VDD。
例如，对于第一像素电路而言，第一发光元件EL的阳极通过透明走线与第四节点N4电连接，第一发光元件EL的阴极与第二电源端(或第二电源线)连接以接收第二电源电压VSS(例如，低电压)，第一电容补偿结构(图6A中未示出)与第四节点N4耦接。例如，对于第二像素电路而言，第二发光元件EL的阳极直接与第四节点N4耦接，第二发光元件EL的阴极与第二电源端(或第二电源线)连接以接收第二电源电压VSS(例如，低电压)。例如，对于第二显示区20中的第二像素电路而言，在设置第二电容补偿结构的情况下，第二电容补偿结构(图6A中未示出)与第四节点N4耦接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在图6A所示的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。例如，在图6A所示的像素驱动电路中，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本公开实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系以及信号的极性即可。
以下结合图6B所示的信号时序图，对图6A所示的像素驱动电路的工作原理进行说明。如图6B所示，每一帧图像的显示过程包括三个阶段，分别为初始化阶段1、数据写入及补偿阶段2、和发光阶段3。
在初始化阶段1，输入第一复位控制信号Reset1以开启第一晶体管T1，将第一复位电压Vinit1施加至第一晶体管T1的栅极，从而对第一节点N1进行复位。
在数据写入及补偿阶段2，输入扫描信号Gate以及数据信号Vdata，第二晶体管T2和第四晶体管T4开启，数据信号data经由第四晶体管T4写入第二节点N2，并经过第三晶体管T3和第二晶体管T2对第一节点N1充电，直至第一节点N1的电位变化至Vdata+Vth时第三晶体管T3截止，其中Vth为第三晶体管T3的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号Vdata和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿。
在数据写入及补偿阶段2，还可以输入第二复位控制信号Reset2以开启第七晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Reset1和第二复位控制信号Reset2可以相同。本公开的实施例对此不作限制。
在发光阶段3，输入发光控制信号EM以开启第五晶体管T5、第六晶体管T6和第三晶体管T3，第六晶体管T6将驱动电流施加至发光元件EL以使其发光。像素驱动电路提供的驱动电流Id的值可以根据下述公式得出：
Id＝K(VGS-Vth) 2＝K[(Vdata+Vth-VDD)-Vth] 2＝K(Vdata-VDD) 2，
其中，K为常数。
在上述公式中，Vth表示第一晶体管T1的阈值电压，VGS表示第三晶体管T3的栅极和源极(这里为第一极)之间的电压，K为与第三晶体管T3本身相关的一常数值。从上述 Id的计算公式可以看出，像素驱动电路提供的驱动电流Id不再与第三晶体管T3的阈值电压Vth有关，由此可以实现对该像素驱动电路的补偿，解决了驱动晶体管(在本公开的实施例中为第三晶体管T3)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流Id的影响，从而可以改善采用其的显示装置的显示效果。
图7A为本公开一些实施例提供的一种显示基板的整体结构的局部区域版图。图7A示例性地示出了第一像素电路D和第一电容补偿结构的布局。图7B为图7A所示的显示基板沿M-N线的截面示意图。例如，如图7B所示，该显示基板包括衬底基板SUB以及在衬底基板SUB上依次设置的像素电路层LX1、透明走线层LX2和发光元件层LX3。
例如，如图7B所示，像素电路层LX1包括有源层AL、栅极层Gate1和源漏极层SD(例如，包括第一源漏极层SD1和第二源漏极层SD2)。例如，有源层AL可以包括半导体材料，栅极层Gate1、第一源漏极层SD1和第二源漏极层SD2可以包括金属材料或者合金材料。例如，第一像素电路包括薄膜晶体管，该薄膜晶体管包括栅极、源极和漏极，栅极位于栅极层Gate1，源极和漏极至少之一位于源漏极层SD。需要说明的是，图7B中仅示意性地示出了第一像素电路中的一个薄膜晶体管，例如，该薄膜晶体管可以是图6A所示的7T1C像素驱动电路中的第六晶体管，本公开的实施例包括但不限于此。
例如，如图7B所示，透明走线层LX2包括第一透明走线层ITO1、第二透明走线层ITO2和第三透明走线层ITO3。例如，每条透明走线位于透明走线层LX2。例如，每条透明走线均包括位于第一透明走线层ITO1、第二透明走线层ITO2和第三透明走线层ITO3中的部分，本公开的实施例包括但不限于此。例如，第一透明走线层ITO1、第二透明走线层ITO2和第三透明走线层ITO3可以包括透明导电材料，例如透明金属氧化物，例如氧化铟锡(ITO)、铟镓锌氧化物(IGZO)等，以具有良好的透光性。
例如，如图7B所示，发光元件层LX3包括阳极层Anode、发光层ELL和阴极层Cathode。例如，第一发光元件包括位于阳极层Anode的阳极、位于发光层ELL的发光材料以及位于阴极层Cathode的阴极。例如，图7B所示的显示基板可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等，本公开的实施例对显示基板的具体种类不做限定。例如，在显示基板为有机发光二极管显示基板的情况下，发光层ELL可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等；并且，根据实际需要，发光层ELL还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层中的一种或多种。例如，在显示基板为量子点发光二极管(QLED)显示基板的情形，发光层ELL可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等。例如，如图7B所示，薄膜晶体管的源极或漏极通过透明走线与第一发光元件电连接(例如，与第一发光元件的阳极)电连接。
例如，第一电容补偿结构包括第一电容电极和第二电容电极。例如，第一电容补偿结 构的补偿电容值的大小通常与第一电容电极和第二电容电极的交叠面积的大小呈正比例关系，而与第一电容电极和第二电容电极的距离(在垂直于显示基板的方向上的距离)呈反比例关系。例如，如图7B所示，像素电路层LX1还可以包括电容极板层Gate2。例如，如图7B所示，第一电容电极和第二电容电极之一位于栅极层Gate1，第一电容电极和第二电容电极之另一位于电容极板层Gate2。例如，如图7B所示，薄膜晶体管的源极或漏极与第一电容电极和第二电容电极之一电连接。例如，第一电容电极和第二电容电极之另一可以与直流信号电连接，例如可以与前述第一电源线VDD或第二电源线VSS等电连接。例如，在一些实施例中，多个电容补偿结构的第一电容电极和第二电容电极之另一可以为一体结构，从而，在制作过程中可以简化工艺。
需要说明的是，图7B所示的第一电容补偿结构的设置方式是示意性的，本公开的实施例对此不作限制。例如，在一些实施例中，第一电容电极和第二电容电极之一可以位于栅极层Gate1、源漏极层SD、透明走线层LX2和电容极板层Gate2等中的某一层，第一电容电极和第二电容电极之另一可以位于上述各层中除该某一层之外的任一层，只要由此形成的第一电容补偿结构能够满足电容补偿的要求即可。当然，在第一电容电极和第二电容电极分别位于栅极层Gate1、源漏极层SD和透明走线层LX2中的某两层的情况下，则显示基板中可以省略电容极板层Gate2。
需要说明的是，位于同一层或者同层设置的多个元件、部件、结构和/或部分，通常可以由相同的材料构成，并可以通过同一次构图工艺形成。具体地，可以采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。
通过将第一电容补偿结构中的某一电容电极与显示基板的某一层同层设置，可以简化工艺，节省成本。当然，在一些实施例中，也可以在显示基板上专门设置一个导电层用于形成第一电容补偿结构中的某一电容电极。
例如，如图7B所示，根据需要，显示基板还可以包括第一栅绝缘层GI1、第二栅绝缘层GI2、层间介定层ILD、钝化层PVX(例如，可以同时作为平坦化层PLN1)、平坦化层PLN2-PLN5和像素限定层PDL等功能层。例如，这些功能层可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。需要说明的是，本公开的实施例对前述各种功能层的材料均不做具体限定。
例如，在一些实施例中，第二像素电路的设置方式可以参考第一像素电路的设置方式，第二发光元件的设置方式可以参考第一发光元件的设置方式，本公开的实施例对此均不作限制。例如，在一些实施例中，在显示基板包括第二电容补偿结构的情况下，第二电容补偿结构的设置方式可以参考第一电容补偿结构的设置方式，本公开的实施例对此亦不作限制。
应当理解的是，图7B所示的显示基板的各层结构是示意性的。在实际应用中，基于图7B所示的显示基板，可以根据需要减少一些已示出的功能层，只要不影响显示基板的显示功能及第一电容补偿结构的电容补偿功能即可；当然，也可以根据需要添加一些未示出的功能层(例如，缓冲层、封装层等)。本公开的实施例对此不作限制。
图7C为图7A所示的显示基板中的第一导电层(即前述栅极层Gate1)的平面示意图。例如，在一些实施例中，如图7C所示，第一电容补偿结构的电容极板M1、前述薄膜晶体管的栅极、前述存储电容Cst的一个电容极板Cst1、栅线W1(包括复位信号线、扫描信号线、发光控制信号线)等均可以位于第一导电层；需要说明的是，本公开包括但不限于此。例如，如图7C所示，各第一电容补偿结构的电容极板M1分立设置。
图7D为图7A所示的显示基板中的第二导电层(即前述电容极板层Gate2)的平面示意图。例如，在一些实施例中，如图7D所示，第一电容补偿结构的电容极板M2、前述存储电容Cst的另一个电容极板Cst2、复位电压线W2等均可以位于第二导电层；需要说明的是，本公开包括但不限于此。例如，如图7D所示，各第一电容补偿结构的电容极板M2可以一体设置，本公开的实施例包括但不限于此。
图7E为图7A所示的显示基板中的第一导电层与第二导电层堆叠的平面示意图。例如，如图7E所示，电容极板Cst1和电容极板Cst2交叠以形成存储电容Cst；电容极板M1和电容极板M2交叠以形成一个电容结构，若将电容极板M1与第六晶体管T6的源极或漏极耦接，该电容结构即可作为第一电容补偿结构。例如，在一些实施例中，如图7E所示，第二导电层中还可以设置遮挡部S2，遮挡部用于遮挡某些薄膜晶体管(例如，图6A中的第二晶体管)的有源层。例如，在一些实施例中，第二导电层中还可以设置第一电源线；例如，第一电源线可以与第一电容补偿结构的电容极板M2耦接。
图7F为图7A所示的显示基板中的第三导电层(即前述第一源漏极层SD1)的平面示意图。例如，在一些实施例中，如图7F所示，第一电容补偿结构的电容极板M3、第一电源线W31、数据信号线W32等均可以位于第三导电层；需要说明的是，本公开包括但不限于此。例如，如图7F所示，各第一电容补偿结构的电容极板M3分立设置。
图7G为图7A所示的显示基板中的第一导电层、第二导电层与第三导电层堆叠的平面示意图。例如，如图7G所示，电容极板M3和电容极板M2交叠以形成一个电容结构；在此情况下，第一电容补偿结构可以为包括设置于不同层的三个电容极板(即电容极板M1-M3)的复杂电容结构，电容极板M1和电容极板M3至少之一可以与第六晶体管T6的源极或漏极耦接。应当理解的是，对于第一电容补偿结构而言，在两个电容极板的基础上再额外设置一个电容极板，增加了调节第一电容补偿结构的补偿电容值的方式。
图7H为图7A所示的显示基板中的第四导电层(即前述第二源漏极层SD2)的平面示意图。例如，在一些实施例中，如图7H所示，第一电容补偿结构的电容极板M4、走线W4(用于连接第一像素电路和第一电容补偿结构)等均可以位于第四导电层；需要说明的是，本公开包括但不限于此。例如，如图7H所示，各第一电容补偿结构的电容极板M4可 以一体设置，本公开的实施例包括但不限于此。例如，走线W4的一端可以与第六晶体管T6的源极或漏极耦接，走线W4的另一端可以与电容极板M1和电容极板M3至少之一耦接。
图7I为图7A所示的显示基板中的第一导电层、第二导电层、第三导电层与第四导电层堆叠的平面示意图。例如，如图7G所示，第一像素电路和第一电容补偿结构通过走线W4电连接。在此情况下，第一电容补偿结构可以为包括设置于不同层的四个电容极板(即电容极板M1-M4)的复杂电容结构，电容极板M1和电容极板M3至少之一可以与第六晶体管T6的源极或漏极耦接。应当理解的是，对于第一电容补偿结构而言，在两个电容极板的基础上再额外设置两个电容极板，进一步增加了调节第一电容补偿结构的补偿电容值的方式。
应当理解的是，在图7C-图7I所示的实施例中，每个第一电容补偿结构可以包括设置于上述四个导电层(即第一导电层、第二导电层、第三导电层与第四导电层)的任意X个导电层中的X个电容极板C0(每个导电层中设置该第一电容补偿结构的一个电容极板C0)，其中，X＝2,3,4，与第一像素电路电连接的电容极板C0在其所在的导电层中是分立的，不与第一像素电路电连接的电容极板C0在其所在的导电层中可以是分立的，也可以与同一导电层中的其余的电容极板C0一体设置。
还应当理解的是，在前述实施例中，第一电容补偿结构的电容极板都呈现为长条形，本公开包括但不限于此。例如，根据实际需要，第一电容补偿结构的电容极板还可以为波浪形、折线形等。同样地，在显示基板包括第二电容补偿结构的情况下，第二电容补偿结构的电容极板也可以为长条形、波浪形、折线形等。
例如，参考图1B所示，类似于图1B所示的显示基板，本公开的实施例提供的显示基板也可以包括第一板面F1和第二板面F2，第一板面F1在显示基板工作中用于显示；第一显示区为透明显示区，被配置为能将从第一板面F1一侧入射的光透射到第二板面F2一侧。
需要说明的是，本公开的实施例对第一显示区、第一区域、第二显示区、第三显示区、周边区域等的形状均不作限制。例如，第一显示区可以为圆形(如图3A所示)、矩形、六边形、不规则图形等任意形状。
本公开的实施例提供的显示基板，可以通过第一电容补偿结构对透明走线的寄生电容进行补偿，使得不同的第一发光元件的发光亮度具有较好的均一性，以缓解或解决第一显示区亮度不均的问题(尤其是第一显示区显示低灰阶时存在的亮度不均的问题)，进而改善第一显示区的显示效果。
本公开的一些实施例还提供一种显示装置。该显示装置包括本公开任一实施例提供的显示基板。图8为本公开一些实施例提供的一种显示装置的平面示意图。例如，如图8所示，该显示装置300可以包括图3A所示的显示基板以及传感器S。
例如，参考图1B所示，类似于图1B所示的显示装置100，在显示装置300中，传感器S(参考显示装置100中的传感器120)可以设置于显示基板(参考显示装置100中的显 示基板110)的第二板面F2一侧。例如，结合图1B和图8所示，传感器S在显示基板上的正投影与第一显示区Rb至少部分重叠，传感器S被配置为能接收从第一板面F1一侧入射的光。
例如，传感器S与第一显示区Rb在显示基板的法线方向(即垂直于显示基板的第一板面F1或第二板面F2的方向)上叠置，传感器S可以接收并处理穿过第一显示区Rb的光信号，该光信号可以为可见光、红外光等。例如，第一显示区Rb允许来自从第一板面F1一侧入射的光至少部分透射至第二板面F2一侧。例如，第一显示区Rb中仅设置发光元件(即第一发光元件)，而不设置像素电路(即第一像素电路)，在此情况下，可以提升第一显示区Rb的透光率。
例如，在一些实施例例中，当采用直下式设置方式时，传感器S在显示基板上的正投影位于第一显示区Rb内。例如，在另一些实施例中，当采用其他导光元件(例如导光板、导光管等)以使光线从例如平行于显示基板的方向(即平行于显示基板的第一板面F1或第二板面F2的方向)入射至传感器S上时，传感器S在显示基板上的正投影与第一显示区Rb部分重叠。此时，由于光线可以横向传播至传感器S，不需要传感器S完全位于第一显示区Rb的正下方。
例如，传感器S可以是图像传感器，可以用于采集传感器S的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器。该传感器S还可以是红外传感器、距离传感器等。例如，在该显示装置300为诸如手机、笔记本等移动终端的情形下，该传感器S可实现为诸如手机、笔记本等移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。例如，该传感器S可以包括阵列排布感光像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，薄膜晶体管)。例如，光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
该显示装置300可以为任何具有显示功能的电子装置，例如智能手机、笔记本电脑、平板电脑、电视等。例如，当显示装置300为智能手机或平板电脑时，该智能手机或平板电脑可以具有全面屏设计；例如，对于图3B和图3C所示的显示基板，可以将无法进行显示的周边区域40弯折到显示装置的侧面或背面，从而实现全面屏设计；当然，对于图3C所示的显示基板，还可以是显示基板不包括周边区域40，从而实现全面板设计。。并且，该智能手机或平板电脑还可以通过屏下传感器(例如摄像头、红外传感器等)进行图像拍摄、距离感知、光强感知等操作。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置300的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
本公开的实施例提供的显示装置的技术效果可以参考上述实施例中关于显示驱动装置 的相应描述，这里不再赘述。
对于本公开，有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括第一显示区和至少部分围绕所述第一显示区的第一区域；其中，
    所述第一显示区包括多个第一发光元件，
    所述第一区域包括多个第一像素电路和至少一个第一电容补偿结构，
    所述显示基板包括从所述第一区域延伸到所述第一显示区的多条透明走线，
    所述多个第一像素电路中的至少一个第一像素电路通过所述多条透明走线中的至少一条透明走线与所述多个第一发光元件中的至少一个第一发光元件电连接，且被配置为控制流经所述至少一个第一像素电路、所述至少一条透明走线以及所述至少一个第一发光元件且驱动所述至少一个第一发光元件发光的驱动电流，
    所述至少一个第一电容补偿结构与所述多条透明走线中的至少一条透明走线耦接，且被配置为补偿由与所述至少一个第一电容补偿结构耦接的所述至少一条透明走线导致的寄生电容。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个第一电容补偿结构提供的补偿电容和与所述至少一个第一电容补偿结构耦接的所述至少一条透明走线导致的寄生电容并联。
  3. 根据权利要求2所述的显示基板，其中，与所述至少一个第一电容补偿结构耦接的所述至少一条透明走线的寄生电容值与所述至少一个第一电容补偿结构的补偿电容值之和大致等于目标电容值。
  4. 根据权利要求3所述的显示基板，其中，所述目标电容值大于或等于所述多条透明走线的寄生电容值的最大值。
  5. 根据权利要求4所述的显示基板，其中，所述多条透明走线中至少存在一条透明走线，该条透明走线的寄生电容值大致等于所述目标电容值，且该条透明走线不与所述至少一个第一电容补偿结构耦接。
  6. 根据权利要求1-3任一项所述的显示基板，其中，
    所述多条透明走线被划分为多个透明走线组，所述多个透明走线组中的每个透明走线组包括至少一条透明走线；
    所述每个透明走线组中的所述至少一条透明走线的寄生电容值的平均值作为所述每个透明走线组的平均寄生电容值；
    所述目标电容值大于或等于所述多个透明走线组的平均寄生电容值的最大值。
  7. 根据权利要求6所述的显示基板，其中，所述多个透明走线组中至少存在一个透明走线组，该透明走线组的平均寄生电容值大致等于所述目标电容值，且该透明走线组中的所述至少一条透明走线不与所述至少一个第一电容补偿结构耦接。
  8. 根据权利要求1-7任一项所述的显示基板，其中，所述第一区域包括周边区域，所述周边区域位于所述第一显示区和所述显示基板的至少一侧边缘之间；
    所述多个第一像素电路和所述多个第一电容补偿结构均位于所述周边区域中。
  9. 根据权利要求1-7任一项所述的显示基板，其中，所述第一区域包括第二显示区，所述第二显示区至少部分围绕所述第一显示区，所述第二显示区包括第二像素单元，
    所述第二像素单元包括第二发光元件和第二像素电路，
    所述第二像素电路与所述第二发光元件电连接，且被配置为控制流经所述第二像素电路以及所述第二发光元件且驱动所述第二发光元件发光的驱动电流；
    所述多个第一像素电路和所述多个第一电容补偿结构均位于所述第二显示区中。
  10. 根据权利要求1-7任一项所述的显示基板，其中，所述第一区域包括第二显示区和周边区域，所述第二显示区至少部分围绕所述第一显示区，所述周边区域位于所述第一显示区和所述显示基板的至少一侧边缘之间；
    所述第二显示区包括第二像素单元，所述第二像素单元包括第二发光元件和第二像素电路，所述第二像素电路与所述第二发光元件电连接，且被配置为控制流经所述第二像素电路以及所述第二发光元件且驱动所述第二发光元件发光的驱动电流；
    所述多个第一像素电路中的一部分第一像素电路和所述多个第一电容补偿结构中的一部分第一电容补偿结构位于所述周边区域中，所述多个第一像素电路中的另一部分第一像素电路和所述多个第一电容补偿结构中的另一部分第一电容补偿结构位于所述第二显示区中。
  11. 根据权利要求9或10所述的显示基板，其中，所述第二显示区还包括第二电容补偿结构，
    第二电容补偿结构与所述第二像素电路和所述第二发光元件耦接，且被配置为向所述第二像素电路提供补偿电容，
    所述第二电容补偿结构的补偿电容值大致等于所述目标电容值。
  12. 根据权利要求8-11任一项所述的显示基板，其中，在所述显示基板所在平面内，所述至少一个第一电容补偿结构位于与所述至少一个第一电容补偿结构对应的第一像素电路的远离所述第一显示区的一侧。
  13. 根据权利要求1-12任一项所述的显示基板，其中，所述显示基板包括衬底基板以及在所述衬底基板上依次设置的像素电路层、透明走线层和发光元件层；
    所述像素电路层包括栅极层和源漏极层；
    所述多个第一发光元件中的每个第一发光元件位于所述发光元件层；
    所述多个第一像素电路中的每个第一像素电路包括薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极，所述栅极位于所述栅极层，所述源极和所述漏极至少之一位于所述源漏极层；
    所述多条透明走线中的每条透明走线位于所述透明走线层；
    所述至少一个第一电容补偿结构包括第一电容电极和第二电容电极，所述第一电容电极和所述第二电容电极之一位于所述栅极层、所述源漏极层或所述透明走线层。
  14. 根据权利要求13所述的显示基板，其中，所述源极或漏极与所述第一电容电极和 所述第二电容电极之一电连接，所述源极或漏极还通过所述透明走线与所述第一发光元件电连接。
  15. 根据权利要求14所述的显示基板，其中，所述像素电路层还包括电容极板层，所述第一电容电极和所述第二电容电极之另一位于所述电容极板层。
  16. 根据权利要求15任一项所述的显示基板，其中，所述至少一个第一电容补偿结构包括多个电容补偿结构，所述多个电容补偿结构的所述第一电容电极和所述第二电容电极之另一为一体结构。
  17. 根据权利要求1-16任一项所述的显示基板，其中，所述显示基板包括第一板面和第二板面，所述第一板面在所述显示基板工作中用于显示，
    所述第一显示区为透明显示区，被配置为能将从所述第一板面一侧入射的光透射到所述第二板面一侧。
  18. 一种显示装置，包括根据权利要求1-17任一所述的显示基板。
  19. 根据权利要求18所述的显示装置，还包括传感器，其中，
    所述显示基板包括第一板面和第二板面，所述第一板面在工作中用于显示，
    所述第一显示区为透明显示区，被配置为能将从所述第一板面一侧入射的光透射到所述第二板面一侧，
    所述传感器设置于所述显示基板的所述第二板面一侧，所述传感器在所述显示基板上的正投影与所述第一显示区至少部分重叠，所述传感器被配置为能接收从所述第一板面一侧入射的光。
  20. 根据权利要求19所述的显示装置，其中，所述传感器包括图像传感器、红外传感器、距离传感器至少之一。
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CN111834425A (zh) * 2020-07-02 2020-10-27 合肥维信诺科技有限公司 显示面板及显示装置
CN211789021U (zh) * 2020-06-08 2020-10-27 京东方科技集团股份有限公司 显示面板和显示装置
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