WO2022174420A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022174420A1
WO2022174420A1 PCT/CN2021/077084 CN2021077084W WO2022174420A1 WO 2022174420 A1 WO2022174420 A1 WO 2022174420A1 CN 2021077084 W CN2021077084 W CN 2021077084W WO 2022174420 A1 WO2022174420 A1 WO 2022174420A1
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WIPO (PCT)
Prior art keywords
transistor
light
line
gate
signal line
Prior art date
Application number
PCT/CN2021/077084
Other languages
English (en)
French (fr)
Inventor
黄耀
黄炜赟
蔡建畅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/610,527 priority Critical patent/US20230337465A1/en
Priority to EP21926138.5A priority patent/EP4123717A4/en
Priority to CN202180000254.1A priority patent/CN115226415A/zh
Priority to PCT/CN2021/077084 priority patent/WO2022174420A1/zh
Priority to CN202280000024.XA priority patent/CN115226412A/zh
Priority to US18/018,876 priority patent/US20230306904A1/en
Priority to PCT/CN2022/071125 priority patent/WO2022174692A1/zh
Publication of WO2022174420A1 publication Critical patent/WO2022174420A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of the display device.
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel, including: a base substrate; a pixel unit, located on the base substrate, including a pixel circuit and a light-emitting element, the pixel circuit is configured to drive the light-emitting element, and the pixel unit is configured to drive the light-emitting element.
  • the pixel circuit includes a drive transistor, the drive transistor includes a gate; a first gate signal line is connected to the gate of the drive transistor; a constant voltage line is configured to provide a first constant voltage to the pixel circuit; a shield electrode is connected to the constant voltage line, and the orthographic projection of the first gate signal line on the base substrate falls within the orthographic projection of the shielding electrode on the base substrate.
  • the orthographic projection of the shielding electrode on the base substrate covers the orthographic projection of the first gate signal line on the base substrate, and the orthographic projection of the shielding electrode on the base substrate The area is larger than the area of the orthographic projection of the first gate signal line on the base substrate.
  • the distance between the orthographic projection of the first gate signal line on the base substrate and the boundary of the orthographic projection of the shield electrode on the base substrate is greater than or equal to 1.75 ⁇ m.
  • the orthographic projection of the gate of the driving transistor on the base substrate falls within the orthographic projection of the shield electrode on the base substrate.
  • the display panel further includes a second gate signal line, the second gate signal line is connected to the first gate signal line, and the orthographic projection of the second gate signal line on the base substrate falls into the The shield electrode is in an orthographic projection on the base substrate.
  • the materials of the first gate signal line and the second gate signal line are different.
  • the material of the first gate signal line includes metal
  • the material of the second gate signal line includes a conductive material formed by conducting semiconductor material.
  • the pixel circuit further includes a first reset transistor and a first initialization signal line, the first reset transistor is connected to a second gate signal line, and a first pole of the first reset transistor is connected to the first initialization signal
  • the lines are connected to each other, and the second gate signal line is multiplexed as the second pole of the first reset transistor.
  • the constant voltage line includes the first initialization signal line.
  • the display panel further includes a first power supply line, the first power supply line is configured to provide a first power supply voltage to the pixel circuit, the pixel circuit further includes a storage capacitor, the first end of the storage capacitor is connected to The gate of the driving transistor is connected to the gate, and the second end of the storage capacitor is connected to the first power line.
  • the constant voltage line includes the first power line.
  • the display panel further includes a third power supply line, the third power supply line is connected in parallel with the first power supply line, the shielding electrode and the third power supply line are integrated into a structure, and the third power supply line is connected to the The extension directions of the first power lines are the same.
  • the display panel includes a first display area and a second display area, the first display area is located on at least one side of the second display area, and the pixel unit includes a first pixel unit and a second pixel unit, Both the pixel circuit and the light-emitting element of the first pixel unit are located in the first display area, the pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the first display area.
  • the element is located in the second display area, the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive line, and the conductive line is on the positive side of the base substrate.
  • the projection overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the base substrate, and in a direction perpendicular to the base substrate, the shielding electrode is located between the conductive line and the base substrate. between the first gate signal lines.
  • the orthographic projection of the conductive line on the base substrate partially overlaps the orthographic projection of the first gate signal line in the pixel circuit of the first pixel unit.
  • the display panel further includes gate lines and data lines, the gate lines are configured to provide scan signals to the pixel circuits, and the data lines are configured to provide data signals to the pixel circuits; the pixel circuits further include data writing The gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the second pole of the data writing transistor is connected to the driving The first poles of the transistors are connected.
  • the display panel further includes a stopper connected to the first power line
  • the pixel circuit further includes a threshold compensation transistor, the first pole of the threshold compensation transistor and the second pole of the driving transistor
  • the second pole of the threshold compensation transistor is connected to the gate of the driving transistor;
  • the gate of the threshold compensation transistor is connected to the gate line;
  • the gate of the driving transistor passes the first gate signal a line is connected to the second pole of the threshold compensation transistor,
  • the threshold compensation transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive connection; the The orthographic projection of the stopper on the base substrate at least partially overlaps the orthographic projection of the conductive connection portion of the threshold compensation transistor on the base substrate.
  • the orthographic projection of the stopper on the base substrate partially overlaps the orthographic projection of the second gate signal line on the base substrate.
  • the display panel further includes a second reset control signal line
  • the pixel circuit further includes a second reset transistor
  • the gate of the second reset transistor is connected to the second reset control signal line
  • the second reset transistor The first pole of the second reset transistor is connected to the second initialization signal line
  • the second pole of the second reset transistor is connected to the first pole of the light-emitting element.
  • the display panel further includes a light-emitting control signal line
  • the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, the gate of the first light-emitting control transistor is connected to the light-emitting control signal line, the The first electrode of the first light-emitting control transistor is connected to the first power supply line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor; the gate of the second light-emitting control transistor connected to the light-emitting control signal line, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element extremely connected.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • the display device further includes a sensor located at one side of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first display area and a second display area in a display panel according to an embodiment of the present disclosure.
  • 5A to 5E are partial plan views of a display panel according to an embodiment of the present disclosure.
  • FIG. 6A is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6B is a layout diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6C is a cross-sectional view along line A-B of FIG. 6B .
  • FIG. 6D is a layout diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • 6E is a cross-sectional view taken along line C-D of FIG. 6D.
  • FIG. 6F is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 6G is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 6H is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7A is a layout diagram of a first pixel circuit or a second pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 7B is a layout diagram of a first pixel circuit or a second pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIGS. 8A and 8B are schematic diagrams of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is an operation timing diagram of the pixel circuit shown in FIG. 6A .
  • a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera.
  • the second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element, and is used to drive the light-emitting element to emit light, and the mutually connected pixel circuits and light-emitting elements are perpendicular to the display panel. overlapping in direction.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include: a base substrate BS.
  • the display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located at at least one side of the second display area R2.
  • the first display region R1 surrounds the second display region R2. That is, the second display area R2 may be surrounded by the first display area R1.
  • the second display area R2 may also be set at other positions, and the setting position of the second display area R2 may be determined as required.
  • the second display area R2 may be located at the top middle position of the base substrate BS, or may be located at the upper left corner position or the upper right corner position of the base substrate BS.
  • hardware such as a photosensitive sensor (eg, a camera) is disposed in the second display area R2 of the display panel.
  • the second display area R2 is a light-transmitting display area
  • the first display area R1 is a display area.
  • the first display area R1 is opaque and only used for display.
  • FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a pixel unit 100, and the pixel unit 100 is located on the base substrate.
  • the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b.
  • the pixel circuit 100a is configured to supply a drive current to drive the light-emitting element 100b to emit light.
  • the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit 100b.
  • the color of light emitted by the light-emitting element 100b may be determined as required.
  • the light transmittance of the second display area R2 In order to improve the light transmittance of the second display area R2, only light emitting elements may be arranged in the second display area R2, and the pixel circuits driving the light emitting elements of the second display area R2 may be arranged in the first display area R1. That is, the light transmittance of the second display region R2 is improved by arranging the light-emitting element and the pixel circuit separately.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes: a plurality of first pixel circuits 10 , a plurality of second pixel circuits 20 and a plurality of first light emitting elements 30 located in the first display area R1 , and a plurality of first pixel circuits 30 located in the second display area R2 A plurality of second light emitting elements 40 .
  • the plurality of second pixel circuits 20 may be distributed among the plurality of first pixel circuits 10 at intervals.
  • At least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light emitting element 30 among the plurality of first light emitting elements 30 , and at least one first pixel circuit 10 may The orthographic projection of the circuit 10 on the base substrate BS and the orthographic projection of the at least one first light-emitting element 30 on the base substrate BS may at least partially overlap.
  • the at least one first pixel circuit 10 can be used to provide a driving signal for the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.
  • At least one second pixel circuit 20 of the plurality of second pixel circuits 20 may be connected to at least one second light emitting element 40 of the plurality of second light emitting elements 40 through a conductive line L1 , which at least A second pixel circuit 20 can be used to provide a driving signal for the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light.
  • the orthographic projection of the at least one second pixel circuit 20 on the base substrate BS is the same as the at least one second light-emitting element 40 on the base substrate.
  • the orthographic projections on the BS do not have overlapping parts.
  • the first display area R1 may be set as a non-transmissive display area
  • the second display area R2 may be set as a light-transmissive display area.
  • the first display region R1 cannot transmit light
  • the second display region R2 can transmit light.
  • the display panel provided by the embodiment of the present disclosure does not need to perform hole-digging processing on the display panel, and required hardware structures such as a photosensitive sensor can be directly disposed at a position corresponding to the second display area R2 on one side of the display panel, which is The realization of true full screen lays a solid foundation.
  • the second display region R2 only includes light-emitting elements and does not include pixel circuits, it is beneficial to improve the light transmittance of the second display region R2, so that the display panel has a better display effect.
  • the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102 , the pixel circuit 100 a and the light-emitting element 100 b of the first pixel unit 101 are located in the first display area R1 , and the pixels of the second pixel unit 101 The circuit 100a is located in the first display region R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display region R2.
  • the pixel circuit 100 a of the first pixel unit 101 is the first pixel circuit 10
  • the light-emitting element 100 b of the first pixel unit 101 is the first light-emitting element 30
  • the pixel circuit of the second pixel unit 101 100 a is the second pixel circuit 20
  • the light-emitting element 100 b of the second pixel unit 102 is the second light-emitting element 40
  • the first light-emitting element 30 may be referred to as an in-situ light-emitting element.
  • the first pixel circuit 10 may be referred to as an in-situ pixel circuit
  • the second pixel circuit 20 may be referred to as an ex-situ pixel circuit.
  • the second light-emitting element 40 and the second pixel circuit 20 connected to the second light-emitting element 40 are located in the same row. That is, the light-emitting signal of the second light-emitting element 40 comes from the second pixel circuit in the same row.
  • pixel circuits of the same row of pixel units are connected to the same gate line.
  • the pixel circuit (the second pixel circuit 20 ) of the second pixel unit 102 is connected to the light-emitting element (the second light-emitting element 40 ) of the second pixel unit 102 through the conductive line L1 .
  • the conductive line L1 is made of transparent conductive material.
  • the conductive line L1 is made of conductive oxide material.
  • the conductive oxide material includes, but is not limited to, indium tin oxide (ITO).
  • one end of the conductive line L1 is connected to the second pixel circuit 20 , and the other end of the conductive line L1 is connected to the second light-emitting element 40 .
  • the conductive line L1 extends from the first display region R1 to the second display region R2 .
  • the display panel further includes an auxiliary region Ra, and the second pixel circuit 20 can be provided in the auxiliary region Ra.
  • FIG. 4 is a schematic diagram of a first display area and a second display area in a display panel according to an embodiment of the present disclosure.
  • a light-transmitting region R0 is provided between adjacent second light-emitting elements 40 .
  • a plurality of light-transmitting regions R0 are connected to each other to form continuous light-transmitting regions separated by a plurality of second light-emitting elements 40 .
  • the conductive line L1 is made of a transparent conductive material to improve the light transmittance of the light-transmitting region R0 as much as possible.
  • the regions of the second display region R2 except where the second light-emitting element 40 is disposed may be all light-transmitting regions.
  • 5A to 5E are partial plan views of a display panel according to an embodiment of the present disclosure. 5A to 5E are described below.
  • FIG. 5A is a schematic diagram of a first display area and a second display area of a display panel according to an embodiment of the present disclosure.
  • the second display area R2 is a light-transmitting display area
  • the first display area R1 is a display area.
  • FIG. 5B is a schematic diagram of a first light-emitting element in a first display area and a second light-emitting element in a second display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 5B shows the first light emitting element 30 and the second light emitting element 40 .
  • the density of the second light emitting element 40 may be equal to that of the first light emitting element 30 . That is, the resolution of the second display region R2 is the same as the resolution of the first display region R1.
  • the density of the second light-emitting element 40 may be greater or less than that of the first light-emitting element 30 . That is, the resolution of the second display region R2 may be larger or smaller than that of the first display region R1. For example, as shown in FIGS.
  • the light-emitting area of the second light-emitting element 40 is smaller than the light-emitting area of the first light-emitting element 30 .
  • FIG. 4 shows the light emitting area of the second light emitting element 40 and the light emitting area of the first light emitting element 30 with dotted lines.
  • the light emitting area of the light emitting element may correspond to the area of the opening of the pixel definition layer.
  • FIG. 5C is a schematic diagram of conductive lines in a display panel according to an embodiment of the disclosure.
  • FIG. 5C shows a plurality of conductive lines L1.
  • FIG. 5D is a schematic diagram of conductive lines in a display panel according to an embodiment of the disclosure.
  • FIG. 5D shows conductive line L1.
  • the conductive line L1 includes a first conductive line L11 , a second conductive line L12 , and a third conductive line L13 .
  • a plurality of conductor pattern layers may be formed.
  • An insulating layer is arranged between different conductor pattern layers. For example, the first conductive line L11 is located in the first conductive pattern layer, the second conductive line L12 is located in the second conductive pattern layer, and the third conductive line L13 is located in the third conductive pattern layer.
  • a plurality of conductive lines in other forms may also be provided.
  • one conductive line L1 is formed of conductive parts located in different conductive pattern layers.
  • conductive parts located in different conductor pattern layers may be connected by via holes penetrating through the insulating layers.
  • FIG. 5E shows the first light emitting element 30, the second light emitting element 40, the first pixel circuit 10, the second pixel circuit 20, the connecting element CE0, and the conductive line L1.
  • Each pixel circuit is connected to the light emitting element through the connection element CE0. That is, each pixel unit has one connection element CE0. That is, the first pixel circuit 10 is connected to the first light-emitting element 30 through the connection element CE0, and the second pixel circuit 20 is connected to the second light-emitting element 40 through the connection element CE0.
  • one end of the conductive line L1 is connected to the second pixel circuit 20 through the connecting element CE0 , and the other end of the conductive line L1 is connected to the second light emitting element 40 .
  • a conductive line L1 passes through the area where the pixel circuit of the pixel unit is located to connect the second pixel circuit 20 and the second light emitting element 40 on both sides of the pixel unit respectively.
  • the area where the pixel circuit of the pixel unit is located overlaps with a plurality of conductive lines L1 passing through the area, so that the pixel circuit is coupled with the conductive lines overlapping the pixel circuit to form parasitic capacitance, resulting in differences in brightness and display defects such as forming Stripes (Mura).
  • the area in the first display area R1 where the second pixel circuit 20 is disposed may be called an auxiliary area Ra (as shown in FIG. 1 and FIG.
  • the auxiliary area Ra may also be called a transition area, because the conductive line is coupled with the pixel circuit
  • the dark pixel unit is the pixel unit (first pixel unit) in the first display area R1, not the second display area R2.
  • Light-emitting element 40 if the auxiliary area is dark, the lower gray level is obvious in the case of high gray level.
  • FIG. 5E takes as an example that one first pixel circuit 10 overlaps with two conductive lines L1 at most. In other embodiments, one first pixel circuit 10 may also overlap with more conductive lines L1 . For example, as shown in FIG. 5C, in some embodiments, one first pixel circuit 10 may overlap with 10-15 conductive lines L1. How many conductive lines L1 one first pixel circuit 10 overlaps can be determined as required.
  • the area where the second pixel circuit 20 is disposed may be obtained by compressing the size of the first pixel circuit 10 in the first direction X.
  • FIG. 5E in the auxiliary area, one column of the second pixel circuits 20 is provided for every set column of the first pixel circuits 10 .
  • the number of columns of the first pixel circuits 10 between two adjacent columns of the second pixel circuits 20 may be determined as required.
  • FIG. 6A is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.
  • 6B is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.
  • FIG. 6C is a cross-sectional view along line A-B of FIG. 6B .
  • FIG. 6D is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.
  • 6E is a cross-sectional view taken along line C-D of FIG. 6D.
  • FIG. 6F is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the pixel circuit shown in FIG. 6A may be a pixel circuit of a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) AMOLED that is common in the related art.
  • LTPS Low Temperature Poly-silicon
  • FIG. 6A shows a pixel circuit of a pixel unit of a display panel.
  • the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b.
  • the pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1 and one storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
  • the light-emitting element 100b includes a first electrode E1 and a second electrode E2 and a light-emitting functional layer between the first electrode E1 and the second electrode E2.
  • the first electrode E1 is an anode
  • the second electrode E2 is a cathode
  • the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (Thin Film Transistor, TFT) to reduce leakage.
  • TFT Thin Film Transistor
  • the display panel includes gate lines GT, data lines DT, first power supply lines PL1 , second power supply lines PL2 , light emission control signal lines EML, initialization signal lines INT, reset control signal lines RST, and the like.
  • the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2.
  • the first power supply line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100
  • the second power supply line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the gate line GT is configured to provide a scan signal SCAN to the pixel unit 100
  • the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100
  • the light emission control signal line EML is configured to provide the pixel unit 100 with a light emission control signal EM
  • the first reset control signal line RST1 is configured to provide the pixel unit 100 with the first reset control signal RESET1
  • the second reset control signal line RST2 is configured to provide the pixel unit 100 with the scan signal SCAN.
  • the first initialization signal line INT1 is configured to provide the first initialization signal Vinit1 to the pixel unit 100
  • the second initialization signal line INT2 is configured to provide the second initialization signal Vinit2 to the pixel unit 100 .
  • the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, for example, the magnitude of which may be between the first voltage signal VDD and the second voltage signal VSS, but is not limited thereto, for example, the first initialization signal Both Vinit1 and the second initialization signal Vinit2 may be less than or equal to the second voltage signal VSS.
  • the first initialization signal line INT1 and the second initialization signal line INT1 are connected, and both are configured to provide the initialization signal Vinit to the pixel unit 100 , that is, the first initialization signal line INT1 and the second initialization signal line INT2 Both are called initialization signal lines INT, the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and both are Vinit.
  • the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light-emitting element 100b glow.
  • the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit 100a.
  • OLED organic light emitting diode
  • one pixel includes a plurality of pixel units.
  • One pixel may include a plurality of pixel units that emit light of different colors.
  • one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
  • the number of pixel units included in a pixel and the light output of each pixel unit can be determined as required.
  • the gate T20 of the data writing transistor T2 is connected to the gate line GT
  • the first electrode T21 of the data writing transistor T2 is connected to the data line DT
  • the second electrode T22 of the data writing transistor T2 is connected to the data line DT.
  • the first pole T11 of the driving transistor T1 is connected.
  • the pixel circuit 100a further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, and the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1
  • the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
  • the display panel further includes an emission control signal line EML
  • the pixel circuit 100a further includes a first emission control transistor T4 and a second emission control transistor T5, and the gate T40 of the first emission control transistor T4 is connected to the emission control transistor T4.
  • the signal line EML is connected, the first pole T41 of the first light-emitting control transistor T4 is connected to the first power supply line PL1, and the second pole T42 of the first light-emitting control transistor T4 is connected to the first pole T11 of the driving transistor T1;
  • the gate T50 of the transistor T5 is connected to the light-emitting control signal line EML, the first electrode T51 of the second light-emitting control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is connected to the light-emitting element.
  • the first pole E1 of 100b is connected.
  • the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, and is configured to reset the gate of the driving transistor T1
  • the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b, and is configured to reset the first pole E1 of the light-emitting element 100b.
  • the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6.
  • the second initialization signal line INT2 is connected to the first electrode E1 of the light emitting element 100b through the second reset transistor T7.
  • first initialization signal line INT1 and the second initialization signal line INT2 are connected to receive the same initialization signal, but not limited thereto, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are also Can be isolated from each other and configured to input signals separately.
  • the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1
  • the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1
  • the second reset transistor T6 is connected to the gate T10 of the driving transistor T1.
  • the first electrode T71 of the transistor T7 is connected to the second initialization signal line INT2
  • the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b.
  • the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1
  • the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.
  • the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit further includes a storage capacitor Cst, and the first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, The second pole Cb of the storage capacitor Cst is connected to the first power line PL1.
  • the display panel further includes a second power supply line PL2, and the second power supply line PL2 is connected to the second pole 201 of the light-emitting element 100b.
  • FIG. 6A shows a first node N1, a second node N2, a third node N3 and a fourth node N4.
  • a capacitance is formed between the first node N1 and the conductive line L1
  • the conductive line L1 and the fourth node N4 form a capacitance
  • the conductive line L1 and the first node N1 and The fourth nodes N4 are respectively coupled, thereby causing a difference in brightness, forming display defects such as forming streaks (Mura), and affecting the display quality.
  • Mura forming streaks
  • the pixel circuit includes a driving transistor T1, and the driving transistor includes a gate electrode T10.
  • the second electrode Cb of the storage capacitor Cst has an opening OPN1
  • one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1.
  • the connection electrode CE1 may also be referred to as a first gate signal line SL1.
  • the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.
  • the first gate signal line SL1 is connected to the second gate signal line SL2.
  • the gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute a gate signal portion PT1.
  • the potential on the gate signal portion PT1 is the same.
  • the second gate signal line SL2 may not be provided.
  • the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal portion PT1.
  • the second gate signal line SL2 is the second pole T62 of the first reset transistor T6.
  • the display panel provided by the embodiments of the present disclosure provides shield electrodes SE and a constant voltage line L0 configured to provide a constant voltage to the pixel circuit.
  • the shielding electrode SE is connected to the constant voltage line L0, so that the voltage on the shielding electrode SE is stable, which can play a shielding role and prevent the conductive line L1 from affecting the potential on the gate signal portion PT1.
  • the orthographic projection of the first gate signal line SL1 on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS.
  • the orthographic projection of the first gate signal line SL1 on the base substrate BS completely falls into the shielding electrode SE on the base substrate BS. in the orthographic projection.
  • the distance between the orthographic projection of the first gate signal line SL1 on the base substrate BS and the boundary of the orthographic projection of the shield electrode SE on the base substrate BS is greater than or is equal to 1.75 ⁇ m. Since the area occupied by the pixel unit is limited, the distance that the shielding electrode SE exceeds the first gate signal line SL1 may be limited. For example, in some embodiments, in order to obtain a better shielding effect, the distance between the orthographic projection of the first gate signal line SL1 on the base substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the base substrate BS is greater than or equal to 2.33 ⁇ m.
  • the display panel further includes a stopper BK, which is connected to the first power line PL1, and the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN1
  • the channel CN2 is connected by the conductive connection CP; the orthographic projection of the stopper BK on the base substrate BS at least partially overlaps the orthographic projection of the conductive connection CP of the threshold compensation transistor T3 on the base substrate BS.
  • the blocking block BK of the pixel unit in the adjacent column is used to block the conductive connection portion CP of the threshold compensation transistor T3 of the pixel unit in this column.
  • the second gate signal line SL2 is connected to the first gate signal line SL1
  • the second gate signal line SL2 is in the substrate
  • the orthographic projection on the substrate BS falls within the orthographic projection of the stopper BK on the base substrate BS.
  • the boundary of the orthographic projection of the stopper BK on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS.
  • the distance by which the boundary of the orthographic projection of the stopper BK on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS is greater than or equal to 1.75 ⁇ m.
  • the distance by which the boundary of the orthographic projection of the stopper BK on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS is greater than or equal to 2.33 ⁇ m.
  • the shielding electrode SE can also be used to replace the function of the stopper BK, or the orthographic projection of the second gate signal line SL2 on the base substrate BS both falls into the stopper BK on the base substrate
  • the orthographic projection on BS also falls within the orthographic projection of the shield electrode SE on the base substrate BS (as shown in FIG. 7A ).
  • the materials of the first gate signal line SL1 and the second gate signal line SL2 are different.
  • the material of the first gate signal line SL1 includes metal
  • the material of the second gate signal line SL2 includes a conductive material formed by conducting semiconductor material.
  • the first power supply line PL1 is used as the constant voltage line L0.
  • the first initialization signal line INL1 may also be used as a constant voltage line or the second initialization signal line INL2 may be used as a constant voltage line.
  • the constant voltage line L0 are not limited to the first power supply line PL1, the first initialization signal line INL1 and the second initialization signal line INL2, as long as the signal lines supplying constant voltage in the pixel circuit can be used as the constant voltage line L0.
  • the embodiments of the present disclosure are described by taking the first power supply line PL1 as the constant voltage line L0 as an example, and in the case of using a signal line other than the first power supply line PL1 that provides a constant voltage as the constant voltage line L0, the shielding can be adjusted
  • the electrode SE is shaped so that it is connected to the signal line supplying the constant voltage.
  • the conductive line L1 includes a first portion L1a, a second portion L1b, and a third portion L1c. Both the first portion L1a and the third portion L1c extend in the second direction Y, and the second portion L1b extends in the first direction X. For example, the first portion L1a and the third portion L1c are located in the same conductor pattern layer, and the second portion L1b is located in another conductor pattern layer.
  • the gray-filled areas in FIG. 6F represent vias used to connect different parts of the conductive lines.
  • FIG. 6F shows the via hole Ha and the via hole Hb.
  • the first portion L1a and the second portion L1b are connected through a via hole Ha through the insulating layer, and the second portion L1b and the third portion L1c are connected through a via hole Hb through the insulating layer.
  • FIG. 6F shows three conductive lines L1, and conductive lines L10 and L100 have similar structures.
  • the entire conductive wire may be located on the same wire pattern layer. That is, the first portion L1a, the second portion L1b and the third portion L1c are all located on the same conductor pattern layer.
  • the three adjacent conductive lines L1 in the second direction Y are located in the first conductive pattern layer, the second conductive pattern layer and the third conductive pattern layer, respectively. The arrangement of the conductive lines can be determined according to needs.
  • the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps the orthographic projection of the pixel circuit (the first pixel circuit 10 ) of the first pixel unit 101 on the base substrate BS.
  • the shield electrode SE is located between the conductive line L1 and the first gate signal line SL1.
  • the shield electrode SE is formed, the conductive line L1 is formed, and then the light-emitting element is formed, so that the shield electrode SE is located between the conductive line L1 and the first gate signal line SL1, and the shield electrode
  • the SE is located between the conductive line L1 and the gate T10 of the driving transistor (refer to FIGS. 6G and 6H ).
  • Conductive lines L1 are arranged in the auxiliary area, and conductive lines L1 are not arranged in the areas of the first display area other than the auxiliary area, so that the pixel circuits (No. The orthographic projection of a pixel circuit) on the base substrate BS does not overlap with the orthographic projection of the conductive line L1 on the base substrate BS.
  • the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps the orthographic projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101 .
  • FIG. 6F shows via HL and via HE. As shown in FIG. 6F , one end of the conductive line L10 is connected to the second pixel circuit 20 through the via hole HL, and the other end of the conductive line L10 is connected to the first electrode E1 of the second light emitting element 40 through the via hole HE.
  • a buffer layer BL is provided on the base substrate BS, an isolation layer BR is provided on the buffer layer BL, an active layer LY0 is provided on the isolation layer BR, and a first insulating layer ISL1 is provided on the active layer LY0
  • the first conductive layer LY1 is provided on the first insulating layer ISL1
  • the second insulating layer ISL2 is provided on the first insulating layer LY1
  • the second conductive layer LY2 is provided on the second insulating layer ISL2
  • the second conductive layer LY2 is provided on
  • the third insulating layer ISL3, a third conductive layer LY3 is provided on the third insulating layer ISL3, the third conductive layer LY3 includes a connecting electrode CE01, and the connecting electrode CE01 passes through the first insulating layer ISL1, the second insulating layer ISL2 and the third insulating layer
  • the via hole H3 of the layer ISL3 is connected to the second pole T52 of the second light-emitting
  • a fourth conductive layer LY4 is provided on the layer ISL5, the fourth conductive layer LY4 includes a connection electrode CE02, the connection electrode CE02 is connected to the connection electrode CE01 through the via hole H22 passing through the fourth insulating layer ISL4 and the fifth insulating layer ISL5, and the fourth conductive layer
  • a sixth insulating layer ISL6 is provided on LY4, and the light emitting element 100b (second light emitting element 30) is connected to the connection electrode CE02 through a via hole H31 (as shown in FIG. 6D and FIG. 6E ) passing through the sixth insulating layer ISL6.
  • the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL between the first electrode E1 and the second electrode E2.
  • the connection element CE0 includes a connection electrode CE01 and a connection electrode CE02.
  • connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the via hole H1, and the other end of the connection electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 through the via hole H2.
  • One end of the connection electrode CE2 is connected to the first initialization signal line INL1 through the via hole H4, and the other end of the connection electrode CE2 is connected to the first electrode T61 of the first reset transistor T6 through the via hole H5.
  • One end of the connection electrode CE3 is connected to the second initialization signal line INL2 through the via hole H6, and the other end of the connection electrode CE3 is connected to the first electrode T71 of the second reset transistor T7 through the via hole H7.
  • the first power line PL1 is connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole H8.
  • the first power line PL1 is connected to the second pole Cb of the storage capacitor Cst through the via hole H9.
  • the first power line PL1 is connected to the block BK through the via hole Hk.
  • the data line DT is connected to the first electrode T21 of the data writing transistor T2 through the via hole H0.
  • a self-alignment process is used to conduct conductorization treatment on the semiconductor pattern layer using the first conductive layer LY1 as a mask.
  • the semiconductor pattern layer can be formed by patterning a semiconductor thin film.
  • the semiconductor pattern layer is heavily doped by ion implantation, so that the part of the semiconductor pattern layer that is not covered by the first conductive layer LY1 is conductive, and the source region (the first electrode T11 ) and the drain electrode of the driving transistor T1 are formed region (the second electrode T12), the source region (the first electrode T21) and the drain region (the second electrode T22) of the data writing transistor T2, the source region (the first electrode T31) and the drain region of the threshold compensation transistor T3
  • the part of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, forming the channel region of the driving transistor T1, the channel region of the data writing transistor T2, the channel region of the threshold compensation transistor T3, and the first light-emitting control transistor T4. , the channel region of the second light emission control transistor T5, the channel region of the first reset transistor T6, and the channel region of the second reset transistor T7. For example, as shown in FIG.
  • the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are integrally formed; the first electrode T51 of the second light-emitting control transistor T5 and the first electrode T51 of the driving transistor T1
  • the diode T12 and the first electrode T31 of the threshold compensation transistor T3 are integrally formed; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2, and the second electrode T42 of the first light-emitting control transistor T4 are integrally formed;
  • the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.
  • the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 may be integrally formed.
  • the channel region of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polysilicon (eg, low temperature polysilicon), or metal oxide semiconductor material (eg, IGZO, AZO, etc.).
  • the transistors are all P-type low temperature polysilicon (LTPS) thin film transistors.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal-oxide-semiconductor thin-film transistors, that is, the channel material of the transistors is a metal-oxide-semiconductor material (such as IGZO , AZO, etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
  • the transistors employed in the embodiments of the present disclosure may include various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
  • the display panel further includes a pixel definition layer PDL and a spacer PS.
  • the pixel definition layer PDL has an opening OPN, and the opening OPN is configured to define a light emitting area (light emitting area, effective light emitting area) of the pixel unit.
  • the spacer PS is configured to support the fine metal mask when the light emitting functional layer FL is formed.
  • the opening OPN is the light emitting area of the pixel unit.
  • the light emitting functional layer FL is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting functional layer FL.
  • a packaging layer CPS is provided on the light emitting element 100b.
  • the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers
  • the second encapsulation layer CPS2 is an organic material layer.
  • the first electrode E1 is the anode of the light-emitting element 100b
  • the second electrode E2 is the cathode of the light-emitting element 100b, but it is not limited thereto.
  • FIG. 6G is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 6G shows a plurality of conductive lines L1.
  • the conductive lines L1 extend along the first direction X, and the plurality of conductive lines L1 are arranged along the second direction Y, but not limited thereto.
  • Figure 6G shows four conductive lines L1.
  • the conductive line L1 may be determined as required.
  • the pixel unit shown in FIG. 6G is the first pixel unit 101
  • the pixel circuit shown in FIG. 6G is the first pixel circuit 10 .
  • the display panel provided by the embodiment of the present disclosure further includes a first pixel unit 101 that does not overlap with the conductive line L1.
  • the first pixel unit 101 that does not overlap the conductive line L1 is located in the first display area except the auxiliary area.
  • Each conductive line L1 shown in FIG. 6G is used to connect the second pixel circuit 20 and the second light emitting element 40 respectively located on the left and right sides of the first pixel unit 101 .
  • FIG. 6H is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 6H shows a plurality of conductive lines L1.
  • the conductive lines L1 extend along the first direction X, and the plurality of conductive lines L1 are arranged along the second direction Y, but not limited thereto.
  • Figure 6G shows four conductive lines L1.
  • the conductive line L1 may be determined as required.
  • the pixel unit shown in FIG. 6G is the second pixel circuit 20 of the second pixel unit 102 .
  • one of the plurality of conductive lines L1 is connected to the second pixel unit 102 , and the remaining conductive lines L1 are not connected to the second pixel unit 102 .
  • the conductive line L10 (one of the plurality of conductive lines L1 ) is connected to the connection element CE0 of the second pixel unit 102 through a via hole HL penetrating the insulating layer.
  • the conductive line L10 is connected to the connection electrode CE02 of the connection element CE0 of the second pixel unit 102 through the via hole HL penetrating the insulating layer.
  • the conductive line L10 is used for connecting with the first pole E1 of the second light emitting element 40 in the second display area.
  • FIG. 7A is a layout diagram of a first pixel circuit or a second pixel circuit in a display panel according to an embodiment of the present disclosure.
  • the orthographic projection of the gate T10 of the driving transistor T1 on the base substrate BS falls within the orthographic projection of the shield electrode SE on the base substrate BS.
  • the second gate signal line SL2 is connected to the first gate signal line SL1, and the second gate signal line SL2 is on the base substrate BS.
  • the orthographic projection also falls within the orthographic projection of the shield electrode SE on the base substrate BS.
  • the boundary of the orthographic projection of the shield electrode SE on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS.
  • the distance by which the boundary of the orthographic projection of the shield electrode SE on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS is greater than or equal to 1.75 ⁇ m.
  • the distance by which the boundary of the orthographic projection of the shield electrode SE on the base substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the base substrate BS is greater than or equal to 2.33 ⁇ m.
  • the orthographic projections of the gate T10 of the driving transistor T1 , the first gate signal line SL1 , and the second gate signal line SL2 on the base substrate BS all fall into the shield electrode SE on the base substrate BS in the orthographic projection on.
  • the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the projection of the stopper BK on the base substrate BS The orthographic projection partially overlaps the orthographic projection of the second gate signal line SL2 on the base substrate BS.
  • the shield electrode SE and the stopper BK form a double-layer shield for the second gate signal line SL2.
  • the orthographic projection of the shield electrode SE on the base substrate BS partially overlaps the orthographic projection of the stopper BK on the base substrate BS.
  • the stopper BK may not be provided, or the orthographic projection of the stopper BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.
  • the fourth conductive layer LY4 further includes a third power supply line PL3, the third power supply line PL3 is integrally formed with the shielding electrode SE, and the third power supply line PL3 is connected to the first power supply line PL1 through the via hole H21 to form a parallel connection structure to reduce resistance.
  • the third power supply line PL3 extends in the second direction Y. As shown in FIG. 7B , the size of the third power supply line PL3 in the second direction Y is larger than the size of the shield electrode SE in the second direction Y.
  • the orthographic projection of the stopper BK on the base substrate BS partially overlaps the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the shielding electrode SE is at The orthographic projection on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 on the base substrate BS, so that the stopper BK and the shielding electrode SE work together to shield the gate signal portion PT1 .
  • the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS .
  • the stopper BK on the left extends to the pixel unit on the left side of the pixel unit shown in the figure, and blocks the conductive connection part CP of the threshold compensation transistor T3 ,
  • the block BK on the right is extended from the block BK connected to the pixel unit on the right side of the pixel unit shown in the figure.
  • the channel of each transistor and the first and second electrodes on both sides of the channel are located in the active layer LY0 ;
  • the first reset control signal line RST1 the gate The line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emission control signal line EML and the second reset control signal line RST2 are located in the first conductive layer LY1;
  • the second pole Cb and the second initialization signal line INL2 are located in the second conductive layer LY2;
  • the data line DT, the first power line PL1, the connection electrode CE1, the connection electrode CE2, the connection electrode CE3, the connection electrode CE01 are located in the third conductive layer LY3 ;
  • the shielding electrode SE is located in the fourth conductive layer LY4. As shown in FIG. 7B, the shield electrode SE and the third power supply line PL3 are located on the fourth
  • the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emission control signal line EML, the second initialization signal line INL2 and the second The reset control signal lines RST2 both extend along the first direction X.
  • the data lines DT and the first power lines PL1 both extend along the second direction Y.
  • the orthographic projection of the element A on the base substrate BS falls within the orthographic projection of the element B on the base substrate BS means that the orthographic projection of the element A on the base substrate BS completely falls into the element B is within the orthographic projection of element A on the underlying substrate BS, that is, the orthographic projection of element A on the underlying substrate BS covers the orthographic projection of element B on the underlying substrate BS, the orthographic projection of element A on the underlying substrate BS.
  • the area is less than or equal to the area of the orthographic projection of the element B on the base substrate BS.
  • each pixel circuit 100a is provided with any one of the shield electrodes SE as previously described. That is, whether it is the first pixel circuit 10 of the first pixel unit 101 or the second pixel circuit 20 of the second pixel unit 102 , any shielding electrode SE as described above is provided.
  • FIG. 6F shows that the first pixel circuit 10 of the first pixel unit 101 includes a shielding electrode SE, and the second pixel circuit 20 of the second pixel unit 102 includes a shielding electrode SE.
  • the shielding electrode SE can also take other forms, for example, The shield electrode shown in FIG. 6F can also be replaced with the shield electrode shown in FIG. 7A or the shield electrode shown in FIG. 7B .
  • the transistors in the pixel circuits of the embodiments of the present disclosure are all thin film transistors.
  • the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials.
  • the first conductive layer LY1 and the second conductive layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto.
  • the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium, aluminum, etc., but are not limited thereto.
  • the third conductive layer LY3 and the fourth conductive layer LY4 are structures formed by three sub-layers of Ti/AL/Ti, respectively, but not limited thereto.
  • a glass substrate or a polyimide substrate can be used as the base substrate, but it is not limited thereto, and can be selected as required.
  • the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer ISL5, and the sixth insulating layer ISL6 are all made of insulating materials .
  • the materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as required.
  • the first electrode E1 may use at least one of transparent conductive metal oxide and silver, but is not limited thereto.
  • the transparent conductive metal oxide includes, but is not limited to, indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first pole E1 may adopt a structure in which three sub-layers of ITO-Ag-ITO are provided.
  • the second electrode E2 may be a metal with low work function, and at least one of magnesium and silver may be used, but it is not limited thereto.
  • the display panel provided by at least one embodiment of the present disclosure may be fabricated by the following method.
  • the buffer layer BL and the isolation layer BR are formed on the base substrate BS.
  • a semiconductor thin film is formed on the isolation layer BR.
  • a first insulating film is formed on the semiconductor pattern layer.
  • a first conductive film is formed on the first insulating film, and the first conductive film is patterned to form the first conductive layer LY1.
  • a second insulating film is formed on the first conductive layer LY1.
  • a second conductive film is formed on the second insulating layer ISL2, and the second conductive film is patterned to form the second conductive layer LY2.
  • a third insulating film is formed on the second conductive layer LY2.
  • At least one of the first insulating film, the second insulating film, and the third insulating film is patterned, and the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3 are formed while forming the via hole.
  • a third conductive film is formed, and the third conductive film is patterned to form a third conductive layer LY3.
  • Each component in the third conductive layer LY3 is connected to the element located under it through the via hole through the via hole.
  • a fourth conductive film is formed, and the fourth conductive film is patterned to form a fourth conductive layer LY4.
  • At least one insulating layer is formed and at least one transparent conductive layer is formed, and the transparent conductive layer includes conductive lines L1.
  • the first electrode E1 of the light-emitting element is formed.
  • the light-emitting functional layer FL is formed.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display panels.
  • FIGS. 8A and 8B are schematic diagrams of a display device according to an embodiment of the present disclosure.
  • the sensor SS is located at one side of the display panel DS and is located in the second display area R2 .
  • the ambient light can be sensed by the sensor SS through the second display area R2.
  • the side of the display panel where the sensor SS is not provided is the display side, and an image can be displayed.
  • the display device is a full-screen display device with an under-screen camera.
  • the display device includes an OLED or a product including an OLED.
  • the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which contain the above-mentioned display panel.
  • FIG. 9 is an operation timing diagram of the pixel circuit shown in FIG. 6A .
  • the driving method of the pixel unit includes a first reset phase t1, data writing and threshold compensation, a second reset phase t2, and a light-emitting phase t3.
  • the reset control signal RESET is at a low level , resets the gate of the driving transistor T1, and resets the first electrode E1 (eg, the anode) of the light-emitting element 100b when the scan signal SCAN is at a low level.
  • the first electrode E1 eg, the anode
  • the storage capacitor is used to hold the voltage signal, so that the potential of the signal holding terminal can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form
  • the driving current drives the light-emitting element 100b to emit light.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the on voltage
  • the scan signal SCAN is set as the off voltage.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the off voltage
  • the scan signal SCAN is set as the on voltage.
  • the light-emitting control signal EM is set as the turn-on voltage
  • the reset control signal RESET is set as the turn-off voltage
  • the scan signal SCAN is set as the turn-off voltage.
  • the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals, for example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.
  • the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor
  • the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V)
  • the turn-on voltage is a high voltage (eg, 5V)
  • the turn-off voltage is high.
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 9 are all described by taking a P-type transistor as an example.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V), but not limited thereto.
  • the first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the drive transistor T1 and is stored by the storage capacitor Cst, resets the drive transistor T1 and erases the data stored in the last (last frame) light emission .
  • the light emission control signal EM is the off voltage
  • the reset control signal RESET is the off voltage
  • the scan signal SCAN is the on voltage.
  • the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state
  • the second reset transistor T7 is in the conducting state
  • the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the light-emitting element 100b
  • the first pole E1 to reset the light emitting element 100b.
  • the first light-emitting control transistor T4, the second light-emitting control transistor T5, and the first reset transistor T6 are in an off state.
  • the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and transmits the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN Write data voltage VDATA.
  • the threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1.
  • the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and adjusts the driving transistor according to the scan signal SCAN.
  • the gate voltage of T1 performs threshold voltage compensation. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.
  • the light-emitting control signal EM is the turn-on voltage
  • the reset control signal RESET is the turn-off voltage
  • the scan signal SCAN is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is kept as VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1 and the
  • the second light emission control transistor T5 flows into the light emitting element 100b, and the light emitting element 100b emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 100b to emit light according to the light emission control signal EM.
  • the luminous current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor T1
  • W and L are the channel width and channel length of the driving transistor T1, respectively
  • Vgs is the gate and source of the driving transistor T1 The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the pixel circuit of the present invention compensates the threshold voltage of the driving transistor T1 very well.
  • the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted.
  • the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display time period of one frame.
  • adjusting the ratio of the duration of the light-emitting phase t3 to the display duration of one frame is achieved by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.
  • the embodiment of the present disclosure is not limited to the specific pixel circuit shown in FIG. 6A , and other pixel circuits that can realize compensation for the driving transistor may be used. Based on the description and teaching of the present disclosure, other arrangements that can be easily conceived by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
  • the above description takes a 7T1C pixel circuit as an example, and embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display panel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • the display panel may also include pixel circuits with less than 7 transistors.
  • elements located on the same layer may be processed by the same patterning process from the same film layer.
  • elements located on the same layer may be located on a surface of the same element remote from the base substrate.
  • the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the lithography process refers to the process of film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • Corresponding patterning processes may be selected according to the structures formed in the embodiments of the present disclosure.

Abstract

提供一种显示面板和显示装置。该显示面板包括：像素单元，包括像素电路和发光元件，像素电路包括第一晶体管，像素单元包括位于同一行且位于相邻列的第一像素单元和第二像素单元；第一栅线，与第一像素单元的第一晶体管的栅极相连；第二栅线，与第二像素单元的第一晶体管的栅极相连；第一栅信号线，沿第一方向延伸，与第一像素单元相连，并配置为向与第一像素单元提供第一扫描信号；第二栅信号线，沿第一方向延伸，与第二像素单元相连，并配置为向与第二像素单元提供第二扫描信号；第一连接线，沿第二方向延伸，第一栅线通过第一连接线与第一栅信号线相连；以及第二连接线，沿第二方向延伸，第二栅线通过第二连接线与第二栅信号线相连。

Description

显示面板和显示装置 技术领域
本公开至少一实施例涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展，有源矩阵型有机发光二极管(Active-Matrix Organic Light-Emitting Diode，AMOLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经在手机、平板电脑、数码相机等显示装置上得到越来越多地应用。
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
本公开的至少一实施例提供一种显示面板，包括：衬底基板；像素单元，位于所述衬底基板上，包括像素电路和发光元件，所述像素电路配置为驱动所述发光元件，所述像素电路包括驱动晶体管，所述驱动晶体管包括栅极；第一栅信号线，与所述驱动晶体管的栅极相连；恒压线，配置为向所述像素电路提供第一恒定电压；屏蔽电极，与所述恒压线相连，所述第一栅信号线在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
例如，所述屏蔽电极在所述衬底基板上的正投影覆盖所述第一栅信号线在所述衬底基板上的正投影，所述屏蔽电极在所述衬底基板上的正投影的面积大于所述第一栅信号线在所述衬底基板上的正投影的面积。
例如，所述第一栅信号线在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影的边界之间的距离大于或等于1.75μm。
例如，所述驱动晶体管的栅极在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
例如，显示面板还包括第二栅信号线，所述第二栅信号线与所述第一栅信号线相连，所述第二栅信号线在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
例如，所述第一栅信号线和所述第二栅信号线的材料不同。
例如，所述第一栅信号线的材料包括金属，所述第二栅信号线的材料包括半导体材料经导体化形成的导电材料。
例如，所述像素电路还包括第一复位晶体管和第一初始化信号线，所述第一复位晶体管与第二栅信号线相连，所述第一复位晶体管的第一极与所述第一初始化信号线相连，所述第二栅信号线复用为所述第一复位晶体管的第二极。
例如，所述恒压线包括所述第一初始化信号线。
例如，所述显示面板还包括第一电源线，所述第一电源线配置为向所述像素电路提供第一电源电压，所述像素电路还包括存储电容，所述存储电容的第一端与所述驱动晶体管的栅极相连，所述存储电容的第二端与所述第一电源线相连。
例如，所述恒压线包括所述第一电源线。
例如，显示面板还包括第三电源线，所述第三电源线与所述第一电源线并联，所述屏蔽电极和所述第三电源线为一体结构，所述第三电源线与所述第一电源线的延伸方向相同。
例如，所述显示面板包括第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧，所述像素单元包括第一像素单元和第二像素单元，所述第一像素单元的像素电路和发光元件均位于所述第一显示区，所述第二像素单元的所述像素电路位于所述第一显示区，所述第二像素单元的所述发光元件位于所述第二显示区，所述第二像素单元的所述像素电路通过导电线与所述第二像素单元的所述发光元件相连，所述导电线在所述衬底基板上的正投影与所述第一像素单元的所述像素电路在所述衬底基板上的正投影部分交叠，在垂直于所述衬底基板的方向上，所述屏蔽电极位于所述导电线和所述第一栅信号线之间。
例如，所述导电线在所述衬底基板上的正投影与所述第一像素单元的像素电路中的所述第一栅信号线的正投影部分交叠。
例如，显示面板还包括栅线和数据线，所述栅线配置为向所述像素电路提供扫描信号，所述数据线配置为向所述像素电路提供数据信号；所述像素电路还包括数据写入晶体管，所述数据写入晶体管的栅极与所述栅线相连，所述数据写入晶体管的第一极与所述数据线相连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
例如，显示面板还包括挡块，所述挡块与所述第一电源线相连，所述像素电路还包括阈值补偿晶体管，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极相连；所述阈值补偿晶体管的栅极与所述栅线相连；所述驱动晶体管的栅极通过所述第一栅信号线与所述阈值补偿晶体管的第二极相连，所述阈值补偿晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电连接部相连；所述挡块在所述衬底基板上的正投影与所述阈值补偿晶体管的所述导电连接部在所述衬底基板上的正投影至少部分交叠。
例如，所述挡块在所述衬底基板上的正投影与所述第二栅信号线在所述衬底基板上的正投影部分交叠。
例如，显示面板还包括第二复位控制信号线，所述像素电路还包括第二复位晶体管，所述第二复位晶体管的栅极与所述第二复位控制信号线相连，所述第二复位晶体管的第一极与第二初始化信号线相连，所述第二复位晶体管的第二极与所述发光元件的第一极相连。
例如，显示面板还包括发光控制信号线，所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的栅极与所述发光控制信号线相连，所述 第一发光控制晶体管的第一极与所述第一电源线相连，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连；所述第二发光控制晶体管的栅极与所述发光控制信号线相连，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连，所述第二发光控制晶体管的第二极与所述发光元件的第一极相连。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示面板。
例如，显示装置还包括传感器，所述传感器位于所述显示面板的一侧。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一实施例提供的一种显示面板的结构示意图。
图2是本公开一实施例提供的一种显示面板的像素单元的示意图。
图3是本公开一实施例提供的一种显示面板的示意图。
图4为本公开一实施例提供的显示面板中的第一显示区和第二显示区的示意图。
图5A至图5E为本公开一实施例提供的显示面板的局部平面图。
图6A是本公开一实施例提供的一种像素电路的示意图。
图6B是本公开一实施例提供的一种像素电路的布局图。
图6C为图6B的沿线A-B的剖视图。
图6D是本公开一实施例提供的一种像素电路的布局图。
图6E为图6D的沿线C-D的剖视图。
图6F是本公开一实施例提供的一种显示面板的局部示意图。
图6G是本公开一实施例提供的一种显示面板的局部示意图。
图6H是本公开一实施例提供的一种显示面板的局部示意图。
图7A为本公开一实施例提供的显示面板中的第一像素电路或第二像素电路的布局图。
图7B为本公开一实施例提供的显示面板中的第一像素电路或第二像素电路的布局图。
图8A和图8B为本公开一实施例提供的显示装置的示意图。
图9为图6A所示的像素电路的工作时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一 般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，现有的刘海屏或水滴屏设计均逐渐不能满足用户对显示面板高屏占比的需求，一系列具有透光显示区的显示面板应运而生。该类显示面板中，可以将感光传感器(如，摄像头)等硬件设置于透光显示区，因无需打孔，故在确保显示面板实用性的前提下，使真全面屏成为可能。
相关技术中，具有屏下摄像头的显示面板一般包括用于正常显示的第一显示区以及用于设置摄像头的第二显示区。该第二显示区一般包括：多个发光元件和多个像素电路，每个像素电路与一个发光元件连接，并用于驱动发光元件发光，且相互连接的像素电路和发光元件在垂直于显示面板的方向上重叠。
由于相关技术中第二显示区内还设置有像素电路，因此第二显示区的透光率较差，相应的，显示面板的显示效果较差。
图1是本公开一实施例提供的一种显示面板的结构示意图。如图1所示，该显示面板可以包括：衬底基板BS。显示面板包括第一显示区R1和第二显示区R2，该第一显示区R1可以位于第二显示区R2的至少一侧。例如，在一些实施例中，第一显示区R1围绕第二显示区R2。即第二显示区R2可以被第一显示区R1包围。第二显示区R2也可以设置在其他位置处，第二显示区R2的设置位置可根据需要而定。例如，第二显示区R2可以位于衬底基板BS的顶部正中间位置处，也可以位于衬底基板BS的左上角位置或右上角位置处。例如，感光传感器(如，摄像头)等硬件设置于显示面板的第二显示区R2。例如，第二显示区R2为透光显示区，第一显示区R1为显示区。例如，第一显示区R1不透光仅用于显示。
图2是本公开一实施例提供的一种显示面板的像素单元的示意图。显示面板包括像素单元100，像素单元100位于衬底基板上。如图2所示，像素单元100包括像素电路100a和发光元件100b，像素电路100a配置为驱动发光元件100b。例如，像素电路100a配置为提供驱动电流以驱动发光元件100b发光。例如，发光元件100b为有机发光二极管(OLED)，发光元件100b在其对应的像素电路100b的驱动下发出红光、绿光、蓝光，或者白光等。发光元件100b发光的颜色可根据需要而定。
为了提高第二显示区R2的光透过率，可以在第二显示区R2仅设置发光元件，而将驱动第二显示区R2的发光元件的像素电路设置在第一显示区R1。即，通过发光元件和像素电路分离设置的方式来提高第二显示区R2的光透过率。
图3是本公开一实施例提供的一种显示面板的示意图。如图3所示，该显示面板包括： 位于第一显示区R1的多个第一像素电路10、多个第二像素电路20和多个第一发光元件30，以及位于第二显示区R2的多个第二发光元件40。例如，多个第二像素电路20可以间隔分布于多个第一像素电路10之间。
例如，如图3所示，多个第一像素电路10中的至少一个第一像素电路10可以与多个第一发光元件30中的至少一个第一发光元件30连接，且至少一个第一像素电路10在衬底基板BS上的正投影与至少一个第一发光元件30在衬底基板BS上的正投影可以至少部分重叠。该至少一个第一像素电路10可以用于为所连接的第一发光元件30提供驱动信号，以驱动该第一发光元件30发光。
例如，如图3所示，多个第二像素电路20中的至少一个第二像素电路20可以与多个第二发光元件40中的至少一个第二发光元件40通过导电线L1连接，该至少一个第二像素电路20可以用于为所连接的第二发光元件40提供驱动信号，以驱动该第二发光元件40发光。如图3所示，因第二发光元件40与第二像素电路20位于不同区域，至少一个第二像素电路20在衬底基板BS上的正投影与至少一个第二发光元件40在衬底基板BS上的正投影不存在重叠部分。
例如，在本公开实施例中，可以设置该第一显示区R1为非透光显示区，以及设置该第二显示区R2为透光显示区。例如，第一显示区R1不可透光，第二显示区R2可透光。如此，本公开实施例提供的显示面板，无需在显示面板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于显示面板的一侧的对应第二显示区R2的位置处，为真全面屏的实现奠定坚实的基础。并且，由于第二显示区R2内仅包括发光元件，而不包括像素电路，从而利于提高第二显示区R2的透光率，以使得显示面板具有较好的显示效果。
如图3所示，像素单元100包括第一像素单元101和第二像素单元102，第一像素单元101的像素电路100a和发光元件100b均位于第一显示区R1，第二像素单元101的像素电路100a位于第一显示区R1，第二像素单元102的发光元件100b位于第二显示区R2。在本公开的实施例中，第一像素单元101的像素电路100a即为第一像素电路10，第一像素单元101的发光元件100b即为第一发光元件30，第二像素单元101的像素电路100a即为第二像素电路20，第二像素单元102的发光元件100b即为第二发光元件40。例如，第一发光元件30可称作原位发光元件。例如，第一像素电路10可称作原位像素电路，第二像素电路20可称作非原位像素电路。
例如，如图3所示，第二发光元件40和与该第二发光元件40相连的第二像素电路20位于同一行。即，第二发光元件40的发光信号来自于同一行的第二像素电路。例如，同一行像素单元的像素电路与同一条栅线相连。
如图3所示，第二像素单元102的像素电路(第二像素电路20)通过导电线L1与第二像素单元102的发光元件(第二发光元件40)相连。例如，导电线L1采用透明导电材料制作。例如，导电线L1采用导电氧化物材料制作。例如，导电氧化物材料包括氧化铟锡(ITO)，但不限于此。
如图3所示，导电线L1的一端与第二像素电路20相连，导电线L1的另一端与第二 发光元件40相连。如图3所示，导电线L1从第一显示区R1延伸至第二显示区R2。
如图1和图3所示，在一些实施例中，显示面板还包括辅助区Ra，辅助区Ra可设置第二像素电路20。
图4为本公开一实施例提供的显示面板中的第一显示区和第二显示区的示意图。如图4所示，在第二显示区R2中，相邻的第二发光元件40之间设有透光区R0。例如，如图4所示，多个透光区R0彼此相连，形成被多个第二发光元件40间隔的连续透光区。导电线L1采用透明导电材料制作以尽可能的提高透光区R0的透光率。如图4所示，第二显示区R2的除了设置第二发光元件40之外的区域可均为透光区。
图5A至图5E为本公开一实施例提供的显示面板的局部平面图。以下对图5A至图5E进行描述。
图5A为本公开一实施例提供的一种显示面板的第一显示区和第二显示区的示意图。如图5A所示，第二显示区R2为透光显示区，第一显示区R1为显示区。
图5B为本公开一实施例提供的一种显示面板的第一显示区中的第一发光元件和第二显示区中的第二发光元件的示意图。图5B示出了第一发光元件30和第二发光元件40。
参考图5A、图5B和图3，为了提高显示效果，第二发光元件40的密度可等于第一发光元件30的密度。即，第二显示区R2的分辨率与第一显示区R1的分辨率相同。当然，在其他的实施例中，第二发光元件40的密度可大于或小于第一发光元件30的密度。即，第二显示区R2的分辨率可大于或小于第一显示区R1的分辨率。例如，如图5B和图4所示，第二发光元件40的发光面积小于第一发光元件30的发光面积。图4用虚线示出了第二发光元件40的发光面积和第一发光元件30的发光面积。例如，发光元件的发光面积可对应于像素定义层的开口的面积。
图5C为本公开一实施例提供的一种显示面板中的导电线的示意图。图5C示出了多条导电线L1。
图5D为本公开一实施例提供的一种显示面板中的导电线的示意图。图5D示出了导电线L1。如图5D所示，导电线L1包括第一导电线L11、第二导电线L12、以及第三导电线L13。在高PPI的显示面板中，为了避免导电过于密集，可以形成多个导线图案层。不同的导线图案层之间设置绝缘层。例如，第一导电线L11位于第一导线图案层，第二导电线L12位于第二导线图案层，第三导电线L13位于第三导线图案层。当然，在其他的实施例中，也可以设置其他形式的多条导电线。例如，一条导电线L1由位于不同导线图案层的导电部形成。例如，位于不同导线图案层的导电部可通过贯穿绝缘层的过孔相连。
图5E示出了第一发光元件30、第二发光元件40、第一像素电路10、第二像素电路20、连接元件CE0，以及导电线L1。每个像素电路通过连接元件CE0与发光元件相连。即，每个像素单元均具有一个连接元件CE0。即，第一像素电路10通过连接元件CE0与第一发光元件30相连，第二像素电路20通过连接元件CE0与第二发光元件40相连。例如，导电线L1的一端通过连接元件CE0与第二像素电路20相连，导电线L1的另一端与第二发光元件40相连。
如图5E所示，一条导电线L1通过像素单元的像素电路所在的区域以分别连接该像素单元两侧的第二像素电路20和第二发光元件40。例如，像素单元的像素电路所在的区域与多条通过该区域的导电线L1交叠，从而像素电路和与该像素电路交叠的导电线耦合形成寄生电容，造成亮度的差异形成显示缺陷例如形成条纹(Mura)。在第一显示区R1内的设置第二像素电路20的区域可称作辅助区Ra(如图1和图3所示)，辅助区Ra也可称作过渡区，因导电线与像素电路耦合而容易产生辅助区域(过渡区)存在亮度偏暗的现象，且偏暗的像素单元为第一显示区R1内的像素单元(第一像素单元)，并非为第二显示区R2内的第二发光元件40。例如，辅助区偏暗的情况在高灰阶的情况下较低灰阶明显。图5E以一个第一像素电路10最多与两条导电线L1交叠为例，在其他的实施例中，一个第一像素电路10还可以与更多条导电线L1交叠。例如，如图5C所示，在一些实施例中，一个第一像素电路10可以与10-15条导电线L1交叠。一个第一像素电路10与多少条导电线L1交叠可根据需要而定。
在一些实施例中，可通过在第一方向X上压缩第一像素电路10的尺寸以获得设置第二像素电路20的区域。例如，如图5E所示，在辅助区，每隔设定列第一像素电路10设置一列第二像素电路20。例如，相邻两列第二像素电路20之间的第一像素电路10的列数可根据需要而定。
图6A是本公开一实施例提供的一种显示面板中的像素电路的示意图。图6B是本公开一实施例提供的一种显示面板中的像素电路的布局图。图6C为图6B的沿线A-B的剖视图。图6D是本公开一实施例提供的一种显示面板中的像素电路的布局图。图6E为图6D的沿线C-D的剖视图。图6F是本公开一实施例提供的一种显示面板的局部示意图。
图6A所示的像素电路可为相关技术中常见的低温多晶硅(Low Temperature Poly-silicon，LTPS)AMOLED的像素电路。
图6A示出了显示面板的一个像素单元的像素电路，如图6A所示，像素单元100包括像素电路100a和发光元件100b。像素电路100a包括六个开关晶体管(T2-T7)、一个驱动晶体管T1和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、以及第二复位晶体管T7。发光元件100b包括第一极E1和第二极E2以及位于第一极E1和第二极E2之间的发光功能层。例如，第一极E1为阳极，第二极E2为阴极。通常，阈值补偿晶体管T3、第一复位晶体管T6采用双栅薄膜晶体管(Thin Film Transistor，TFT)的方式降低漏电。
如图6A所示，显示面板包括栅线GT、数据线DT、第一电源线PL1、第二电源线PL2、发光控制信号线EML、初始化信号线INT、复位控制信号线RST等。例如，复位控制信号线RST包括第一复位控制信号线RST1和第二复位控制信号线RST2。第一电源线PL1配置为向像素单元100提供恒定的第一电压信号VDD、第二电源线PL2配置为向像素单元100提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。栅线GT配置为向像素单元100提供扫描信号SCAN、数据线DT配置为向像素单 元100提供数据信号DATA(数据电压VDATA)、发光控制信号线EML配置为向像素单元100提供发光控制信号EM，第一复位控制信号线RST1配置为向像素单元100提供第一复位控制信号RESET1，第二复位控制信号线RST2配置为向像素单元100提供扫描信号SCAN。第一初始化信号线INT1配置为向像素单元100提供第一初始化信号Vinit1。第二初始化信号线INT2配置为向像素单元100提供第二初始化信号Vinit2。例如，第一初始化信号Vinit1和第二初始化信号Vinit2为恒定的电压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此，例如，第一初始化信号Vinit1和第二初始化信号Vinit2可均小于或等于第二电压信号VSS。例如，在一些实施例中，第一初始化信号线INT1和第二初始化信号线INT1相连，均配置为向像素单元100提供初始化信号Vinit，即，第一初始化信号线INT1和第二初始化信号线INT2均称作初始化信号线INT，第一初始化信号Vinit1和第二初始化信号Vinit2相等，均为Vinit。
如图6A所示，驱动晶体管T1与发光元件100b电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件100b发光。
例如，发光元件100b包括有机发光二极管(OLED)，发光元件100b在其对应的像素电路100a的驱动下发出红光、绿光、蓝光，或者白光等。例如，一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如，一个像素包括出射红光的像素单元，出射绿光的像素单元和出射蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
例如，如图6A所示，数据写入晶体管T2的栅极T20与栅线GT相连，数据写入晶体管T2的第一极T21与数据线DT相连，数据写入晶体管T2的第二极T22与驱动晶体管T1的第一极T11相连。
例如，如图6A所示，像素电路100a还包括阈值补偿晶体管T3，阈值补偿晶体管T3的栅极T30与栅线GT相连，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12相连，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如，如图6A所示，显示面板还包括发光控制信号线EML，像素电路100a还包括第一发光控制晶体管T4和第二发光控制晶体管T5，第一发光控制晶体管T4的栅极T40与发光控制信号线EML相连，第一发光控制晶体管T4的第一极T41与第一电源线PL1相连，第一发光控制晶体管T4的第二极T42与驱动晶体管T1的第一极T11相连；第二发光控制晶体管T5的栅极T50与发光控制信号线EML相连，第二发光控制晶体管T5的第一极T51与驱动晶体管T1的第二极T12相连，第二发光控制晶体管T5的第二极T52与发光元件100b的第一极E1相连。
如图6A所示，第一复位晶体管T6与驱动晶体管T1的栅极T10相连，并配置为对驱动晶体管T1的栅极进行复位，第二复位晶体管T7与发光元件100b的第一极E1相连，并配置为对发光元件100b的第一极E1进行复位。第一初始化信号线INT1通过第一复位晶体管T6与驱动晶体管T1的栅极相连。第二初始化信号线INT2通过第二复位晶体管 T7与发光元件100b的第一极E1相连。例如，第一初始化信号线INT1和第二初始化信号线INT2相连，以被输入相同的初始化信号，但不限于此，在一些实施例中，第一初始化信号线INT1和第二初始化信号线INT2也可以彼此绝缘，并配置为分别输入信号。
例如，如图6A所示，第一复位晶体管T6的第一极T61与第一初始化信号线INT1相连，第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10相连，第二复位晶体管T7的第一极T71与第二初始化信号线INT2相连，第二复位晶体管T7的第二极T72与发光元件100b的第一极E1相连。例如，如图6A所示，第一复位晶体管T6的栅极T60与第一复位控制信号线RST1相连，第二复位晶体管T7的栅极T70与第二复位控制信号线RST2相连。
如图6A所示，第一电源线PL1配置为向像素电路100a提供第一电压信号VDD；像素电路还包括存储电容Cst，存储电容Cst的第一极Ca与驱动晶体管T1的栅极T10相连，存储电容Cst的第二极Cb与第一电源线PL1相连。
例如，如图6A所示，显示面板还包括第二电源线PL2，第二电源线PL2与发光元件100b的第二极201相连。
图6A示出了第一节点N1、第二节点N2、第三节点N3和第四节点N4。例如，一些实施例中，参考图5C、图5E和图6A，第一节点N1与导电线L1之间形成电容，导电线L1与第四节点N4形成电容，导电线L1与第一节点N1与第四节点N4分别形成耦合，从而造成亮度差异，形成显示缺陷例如形成条纹(Mura)，影响显示品质。
如图6B所示，像素电路包括驱动晶体管T1，驱动晶体管包括栅极T10。参考图6B和图6C，存储电容Cst的第二极Cb具有开口OPN1，连接电极CE1的一端通过开口OPN1与驱动晶体管T1的栅极T10相连。连接电极CE1也可称作第一栅信号线SL1。如图6B所示，第一栅信号线SL1与驱动晶体管T1的栅极T10相连。
如图6B所示，第一栅信号线SL1与第二栅信号线SL2相连。驱动晶体管T1的栅极T10、第一栅信号线SL1、以及第二栅信号线SL2构成栅信号部PT1。栅信号部PT1上的电位相同。当然，在其他的实施例中，也可以不设置第二栅信号线SL2，此情况下，驱动晶体管T1的栅极T10以及第一栅信号线SL1构成栅信号部PT1。例如，第二栅信号线SL2为第一复位晶体管T6的第二极T62。
参考图6B和图6C，为了稳定栅信号部PT1上的电位，本公开的实施例提供的显示面板提供屏蔽电极SE和恒压线L0，恒压线L0配置为向像素电路提供恒定电压。屏蔽电极SE与恒压线L0相连，从而屏蔽电极SE上的电压稳定，可起到屏蔽作用，避免导电线L1影响栅信号部PT1上的电位。第一栅信号线SL1在衬底基板BS上的正投影落入屏蔽电极SE在衬底基板BS上的正投影内。
参考图6B至图6D，为了使得屏蔽电极起到较好的屏蔽作用，增加屏蔽量，第一栅信号线SL1在衬底基板BS上的正投影完全落入屏蔽电极SE在衬底基板BS上的正投影内。
例如，为了减轻显示不良(mura)和提高显示效果，第一栅信号线SL1在衬底基板 BS上的正投影与屏蔽电极SE在衬底基板BS上的正投影的边界之间的距离大于或等于1.75μm。因为像素单元所占用的区域的面积有限，可以对屏蔽电极SE超出第一栅信号线SL1的距离进行限定。例如，一些实施例中，为了获得较好的屏蔽效果，第一栅信号线SL1在衬底基板BS上的正投影与屏蔽电极SE在衬底基板BS上的正投影的边界之间的距离大于或等于2.33μm。
如图6B所示，显示面板还包括挡块BK，挡块BK与第一电源线PL1相连，阈值补偿晶体管T3包括第一沟道CN1和第二沟道CN2，第一沟道CN1和第二沟道CN2通过导电连接部CP相连；挡块BK在衬底基板BS上的正投影与阈值补偿晶体管T3的导电连接部CP在衬底基板BS上的正投影至少部分交叠。如图6B所示，相邻列像素单元的挡块BK用来遮挡本列像素单元的阈值补偿晶体管T3的导电连接部CP。
例如，如图6B、6G和6H所示，在显示面板包括第二栅信号线SL2的情况下，第二栅信号线SL2与第一栅信号线SL1相连，第二栅信号线SL2在衬底基板BS上的正投影落入挡块BK在衬底基板BS上的正投影内。进一步例如，挡块BK在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界。例如，挡块BK在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界的距离大于或等于1.75μm。例如，挡块BK在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界的距离大于或等于2.33μm。当然，在其他的实施例中，也可以采用屏蔽电极SE来替代挡块BK的作用，或者，第二栅信号线SL2在衬底基板BS上的正投影既落入挡块BK在衬底基板BS上的正投影内也落入屏蔽电极SE在衬底基板BS上的正投影内(如图7A所示)。
例如，第一栅信号线SL1和第二栅信号线SL2的材料不同。例如，第一栅信号线SL1的材料包括金属，第二栅信号线SL2的材料包括半导体材料经导体化形成的导电材料。
例如，如图6B和图6D所示，为了节省布线，第一电源线PL1作为恒压线L0。在其他的实施例中，为了节省布线，也可以第一初始化信号线INL1作为恒压线或者第二初始化信号线INL2作为恒压线。恒压线L0的示例不限于第一电源线PL1、第一初始化信号线INL1和第二初始化信号线INL2，只要是像素电路中提供恒定电压的信号线均可以作为恒压线L0。本公开的实施例以第一电源线PL1作为恒压线L0为示例进行说明，在采用除了第一电源线PL1之外的提供恒定电压的信号线作为恒压线L0的情况下，可以调整屏蔽电极SE的形状以使得其连接至该提供恒定电压的信号线。
如图6F所示，导电线L1包括第一部分L1a、第二部分L1b和第三部分L1c。第一部分L1a和第三部分L1c均沿第二方向Y延伸，第二部分L1b沿第一方向X延伸。例如，第一部分L1a和第三部分L1c位于同一导线图案层中，第二部分L1b位于另一导线图案层中。图6F中灰色填充的区域表示过孔用以连接导电线的不同的部分。
图6F示出了过孔Ha和过孔Hb。第一部分L1a和第二部分L1b通过贯穿绝缘层的过孔Ha相连，第二部分L1b和第三部分L1c通过贯穿绝缘层的过孔Hb相连。例如，图6F示出了三条导电线L1，导电线L10和导电线L100具有类似的结构。
当然，在其他的实施例中，也可以一整条导电线均位于同一导线图案层。即，第一部分L1a、第二部分L1b和第三部分L1c均位于同一导线图案层。例如，在另一些实施例中，在第二方向Y上相邻的三条导电线L1分别位于第一导线图案层、第二导线图案层和第三导线图案层。导电线的设置情况可依据需要而定。
如图6F所示，导电线L1在衬底基板BS上的正投影与第一像素单元101的像素电路(第一像素电路10)在衬底基板BS上的正投影部分交叠。如图6F所示，屏蔽电极SE位于导电线L1和第一栅信号线SL1之间。在本公开的实施例中，形成像素电路之后，形成屏蔽电极SE，再形成导电线L1，然后形成发光元件，从而，屏蔽电极SE位于导电线L1和第一栅信号线SL1之间，屏蔽电极SE位于导电线L1和驱动晶体管的栅极T10之间(参照图6G和图6H)。
为了图示清晰，图6F中仅示出了像素电路的一部分结构。辅助区内设置有导电线L1，在第一显示区的除了辅助区之外的区域内，不设置导电线L1，从而，第一显示区的除了辅助区之外的区域内的像素电路(第一像素电路)在衬底基板BS上的正投影不与导电线L1在衬底基板BS上的正投影交叠。
如图6F所示，导电线L1在衬底基板BS上的正投影与第一像素单元101的像素电路中的第一栅信号线SL1的正投影部分交叠。
图6F示出了过孔HL和过孔HE。如图6F所示，导电线L10的一端通过过孔HL与第二像素电路20相连，导电线L10的另一端通过过孔HE与第二发光元件40的第一极E1相连。
参考图6C和图6E，衬底基板BS上设置缓冲层BL，缓冲层BL上设置隔离层BR，在隔离层BR上设置有源层LY0，在有源层LY0上设置第一绝缘层ISL1，在第一绝缘层ISL1上设置第一导电层LY1，在第一导电层LY1上设置第二绝缘层ISL2，在第二绝缘层ISL2上设置第二导电层LY2，在第二导电层LY2上设置第三绝缘层ISL3，在第三绝缘层ISL3上设置第三导电层LY3，第三导电层LY3包括连接电极CE01，连接电极CE01通过贯穿第一绝缘层ISL1、第二绝缘层ISL2以及第三绝缘层ISL3的过孔H3与第二发光控制晶体管T5的第二极T52相连，在第三导电层LY3上设置第四绝缘层ISL4和第五绝缘层ISL5，在第四绝缘层ISL4和第五绝缘层ISL5上设置第四导电层LY4，第四导电层LY4包括连接电极CE02，连接电极CE02通过贯穿第四绝缘层ISL4和第五绝缘层ISL5的过孔H22与连接电极CE01相连，第四导电层LY4上设置第六绝缘层ISL6，发光元件100b(第二发光元件30)通过贯穿第六绝缘层ISL6的过孔H31(如图6D和图6E所示)与连接电极CE02相连。发光元件100b包括第一极E1、第二极E2以及位于第一极E1和第二极E2之间的发光功能层FL。例如，连接元件CE0包括连接电极CE01和连接电极CE02。
如图6B所示，连接电极CE1的一端通过过孔H1与驱动晶体管T1的栅极T10相连，连接电极CE1的另一端通过过孔H2与第一复位晶体管T6的第二极T62相连。连接电极CE2的一端通过过孔H4与第一初始化信号线INL1相连，连接电极CE2的另一端通过过孔H5与第一复位晶体管T6的第一极T61相连。连接电极CE3的一端通过过孔H6与第 二初始化信号线INL2相连，连接电极CE3的另一端通过过孔H7与第二复位晶体管T7的第一极T71相连。第一电源线PL1通过过孔H8与第一发光控制晶体管T4的第一极T41相连。第一电源线PL1通过过孔H9与存储电容Cst的第二极Cb相连。第一电源线PL1通过过孔Hk与挡块BK相连。数据线DT通过过孔H0与数据写入晶体管T2的第一极T21相连。
例如，在显示面板的制作过程中，采用自对准工艺，以第一导电层LY1为掩模对半导体图案层进行导体化处理。半导体图案层可通过对半导体薄膜进行构图而形成。例如，采用离子注入对半导体图案层进行重掺杂，从而使得半导体图案层未被第一导电层LY1覆盖的部分被导体化，形成驱动晶体管T1的源极区(第一极T11)和漏极区(第二极T12)、数据写入晶体管T2的源极区(第一极T21)和漏极区(第二极T22)、阈值补偿晶体管T3的源极区(第一极T31)和漏极区(第二极T32)、第一发光控制晶体管T4的源极区(第一极T41)和漏极区(第二极T42)、第二发光控制晶体管T5的源极区(第一极T51)和漏极区(第二极T52)、第一复位晶体管T6的源极区(第一极T61)和漏极区(第二极T62)、以及第二复位晶体管T7的源极区(第一极T71)和漏极区(第二极T72)。半导体图案层被第一导电层LY1覆盖的部分保留半导体特性，形成驱动晶体管T1的沟道区、数据写入晶体管T2的沟道区、阈值补偿晶体管T3的沟道区、第一发光控制晶体管T4的沟道区、第二发光控制晶体管T5的沟道区、第一复位晶体管T6的沟道区、以及第二复位晶体管T7的沟道区。例如，如图6B所示，第二复位晶体管T7的第二极T72和第二发光控制晶体管T5的第二极T52一体形成；第二发光控制晶体管T5的第一极T51、驱动晶体管T1的第二极T12和阈值补偿晶体管T3的第一极T31一体形成；驱动晶体管T1的第一极T11、数据写入晶体管T2的第二极T22、第一发光控制晶体管T4的第二极T42一体形成；阈值补偿晶体管T3的第二极T32和第一复位晶体管T6的第二极T62一体形成。在一些实施例中，如图6B所示，第二复位晶体管T7的第一极T71和第一复位晶体管T6的第一极T61可一体形成。
例如，本公开实施例采用的晶体管的沟道区可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个实施例中，该晶体管均为P型低温多晶硅(LTPS)薄膜晶体管。在另一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管，即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等)，金属氧化物半导体薄膜晶体管具有较低的漏电流，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，如图6E所示，显示面板还包括像素定义层PDL以及隔垫物PS，像素定义层PDL具有开口OPN，开口OPN配置为限定像素单元的发光面积(出光区域，有效发光面积)。隔垫物PS配置为在形成发光功能层FL时支撑精细金属掩膜。
例如，开口OPN为像素单元的出光区域。发光功能层FL位于发光元件100b的第一极E1之上，发光元件100b的第二极E2位于发光功能层FL上，如图6E所示，发光元件100b上设置封装层CPS。封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。例如，第一极E1为发光元件100b的阳极，第二电极E2为发光元件100b的阴极，但不限于此。
图6G是本公开一实施例提供的一种显示面板的局部示意图。图6G示出了多条导电线L1。例如，导电线L1沿第一方向X延伸，多条导电线L1沿第二方向Y排列，但不限于此。图6G示出了四条导电线L1。然而，导电线L1可根据需要而定。图6G示出的像素单元为第一像素单元101，图6G示出的像素电路为第一像素电路10。本公开的实施例提供的显示面板还包括不与导电线L1交叠的第一像素单元101。例如，不与导电线L1交叠的第一像素单元101位于除了辅助区之外的第一显示区内。图6G示出的每条导电线L1用于连接分别位于该第一像素单元101的左右两侧的第二像素电路20和第二发光元件40。
图6H是本公开一实施例提供的一种显示面板的局部示意图。图6H示出了多条导电线L1。例如，导电线L1沿第一方向X延伸，多条导电线L1沿第二方向Y排列，但不限于此。图6G示出了四条导电线L1。然而，导电线L1可根据需要而定。图6G示出的像素单元为第二像素单元102的第二像素电路20。如图6H所示，多条导电线L1中的一条与该第二像素单元102相连，其余的导电线L1不与该第二像素单元102相连。例如，导电线L10(多条导电线L1中的一条)通过贯穿绝缘层的过孔HL与第二像素单元102的连接元件CE0相连。进一步例如，导电线L10通过贯穿绝缘层的过孔HL与第二像素单元102的连接元件CE0的连接电极CE02相连。导电线L10用于与位于第二显示区的第二发光元件40的第一极E1相连。
图7A为本公开一实施例提供的显示面板中的第一像素电路或第二像素电路的布局图。例如，如图7A所示，驱动晶体管T1的栅极T10在衬底基板BS上的正投影落入屏蔽电极SE在衬底基板BS上的正投影内。
例如，如图7A所示，在显示面板包括第二栅信号线SL2的情况下，第二栅信号线SL2与第一栅信号线SL1相连，第二栅信号线SL2在衬底基板BS上的正投影也落入屏蔽电极SE在衬底基板BS上的正投影内。进一步例如，屏蔽电极SE在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界。例如，屏蔽电极SE在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界的距离大于或等于1.75μm。例如，屏蔽电极SE在衬底基板BS上的正投影的边界超出第二栅信号线SL2在衬底基板BS上的正投影的边界的距离大于或等于2.33μm。
例如，如图7A所示，驱动晶体管T1的栅极T10、第一栅信号线SL1、以及第二栅信号线SL2在衬底基板BS上的正投影均落入屏蔽电极SE在衬底基板BS上的正投影内。
例如，如图7A所示，屏蔽电极SE在衬底基板BS上的正投影与第二栅信号线SL2 在衬底基板BS上的正投影部分交叠，挡块BK在衬底基板BS上的正投影与第二栅信号线SL2在衬底基板BS上的正投影部分交叠。从而，在图7A所示的显示面板中，屏蔽电极SE和挡块BK对第二栅信号线SL2形成了双层屏蔽。
例如，如图7A所示，屏蔽电极SE在衬底基板BS上的正投影与挡块BK在衬底基板BS上的正投影部分交叠。
当然，在其他的实施例中，也可以不设置挡块BK，或者挡块BK在衬底基板BS上的正投影与第二栅信号线SL2在衬底基板BS上的正投影不交叠。
图7B为本公开一实施例提供的显示面板中的第一像素电路或第二像素电路的布局图。如图7B所示，第四导电层LY4还包括第三电源线PL3，第三电源线PL3与屏蔽电极SE一体形成，第三电源线PL3通过过孔H21与第一电源线PL1相连，形成并联结构以减小电阻。第三电源线PL3沿第二方向Y延伸。如图7B所示，第三电源线PL3在第二方向Y上的尺寸大于屏蔽电极SE在第二方向Y上的尺寸。
例如，如图6B，图6D、图7B所示，挡块BK在衬底基板BS上的正投影与第二栅信号线SL2在衬底基板BS上的正投影部分交叠，屏蔽电极SE在衬底基板BS上的正投影与第一栅信号线SL1在衬底基板BS上的正投影部分交叠，从而，挡块BK和屏蔽电极SE共同起到对栅信号部PT1的屏蔽作用。当然，在另外一些实施例中，也可以不设置挡块BK，或者，挡块BK在衬底基板BS上的正投影与第二栅信号线SL2在衬底基板BS上的正投影不交叠。
例如，如图6B，图6D、图7B所示，左侧的挡块BK延伸至图中所示的像素单元的左侧的像素单元，对其阈值补偿晶体管T3的导电连接部CP进行遮挡，而右侧的挡块BK由图中所示的像素单元右侧的像素单元相连的挡块BK延伸而来。
如图6B、图6D、图7A、以及图7B所示，各个晶体管的沟道和位于沟道两侧的第一极和第二极位于有源层LY0；第一复位控制信号线RST1、栅线GT、驱动晶体管的栅极T10(存储电容Cst的第一极Ca)、发光控制信号线EML和第二复位控制信号线RST2位于第一导电层LY1；第一初始化信号线INL1、存储电容Cst的第二极Cb、第二初始化信号线INL2位于第二导电层LY2；数据线DT、第一电源线PL1、连接电极CE1、连接电极CE2、连接电极CE3、连接电极CE01位于第三导电层LY3；屏蔽电极SE位于第四导电层LY4。如图7B所示，屏蔽电极SE和第三电源线PL3位于第四导电层LY4。
如图6B、图6D、图7A、以及图7B所示，第一初始化信号线INL1、第一复位控制信号线RST1、栅线GT、发光控制信号线EML、第二初始化信号线INL2和第二复位控制信号线RST2均沿第一方向X延伸，如图6B、图6D、图7A、以及图7B所示，数据线DT和第一电源线PL1均沿第二方向Y延伸。
在本公开的实施例中，元件A在衬底基板BS上的正投影落入元件B在衬底基板BS上的正投影内是指元件A在衬底基板BS上的正投影完全落入元件B在衬底基板BS上的正投影内，即，元件A在衬底基板BS上的正投影覆盖元件B在衬底基板BS上的正投影，元件A在衬底基板BS上的正投影的面积小于或等于元件B在衬底基板BS上的正投影的 面积。
例如，在本公开的一些实施例中，每个像素电路100a均设有如前所述的任一屏蔽电极SE。即，不论是第一像素单元101的第一像素电路10还是第二像素单元102的第二像素电路20，均设有如前所述的任一屏蔽电极SE。图6F示出了第一像素单元101的第一像素电路10包括屏蔽电极SE，第二像素单元102的第二像素电路20包括屏蔽电极SE，当然，屏蔽电极SE也可以采用其他形式，例如，图6F所示的屏蔽电极也可以替换为如图7A所示的屏蔽电极或者如图7B所示的屏蔽电极。
例如，本公开的实施例的像素电路中的晶体管均为薄膜晶体管。例如，第一导电层LY1、第二导电层LY2、第三导电层LY3、第四导电层LY4均采用金属材料制作。例如，第一导电层LY1和第二导电层LY2采用镍、铝等金属材料形成，但不限于此。例如，第三导电层LY3和第四导电层LY4采用钛、铝等材料形成，但不限于此。例如，第三导电层LY3和第四导电层LY4分别为Ti/AL/Ti三个子层形成的结构，但不限于此。例如，衬底基板可以采用玻璃基板或聚酰亚胺基板，但不限于此，可根据需要进行选择。例如，缓冲层BL、隔离层BR、第一绝缘层ISL1、第二绝缘层ISL2、第三绝缘层ISL3、第四绝缘层IS4、第五绝缘层ISL5、第六绝缘层ISL6均采用绝缘材料制作。发光元件的第一极E1和第二极E2的材料可根据需要进行选取。一些实施例中，第一极E1可采用透明导电金属氧化物和银至少之一，但不限于此。例如，透明导电金属氧化物包括氧化铟锡(ITO)，但不限于此。例如，第一极E1可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中，第二极E2可以为低功函的金属，可采用镁和银至少之一，但不限于此。
例如，参考本公开的实施例的布局图和剖视图，本公开至少一实施例提供的显示面板可采用以下方法制作。
(1)在衬底基板BS上形成缓冲层BL和隔离层BR。
(2)在隔离层BR上形成半导体薄膜。
(3)对半导体薄膜进行构图形成半导体图案层。
(4)在半导体图案层上形成第一绝缘薄膜。
(5)在第一绝缘薄膜上形成第一导电薄膜，并对第一导电薄膜进行构图以形成第一导电层LY1。
(6)以第一导电层LY1为掩膜版对半导体图案层进行掺杂，形成有源层LY0。
(7)在第一导电层LY1上形成第二绝缘薄膜。
(8)在第二绝缘层ISL2上形成第二导电薄膜，并对第二导电薄膜进行构图以形成第二导电层LY2。
(9)在第二导电层LY2上形成第三绝缘薄膜。
(10)对第一绝缘薄膜、第二绝缘薄膜、以及第三绝缘薄膜至少之一进行构图，形成过孔的同时形成第一绝缘层ISL1、第二绝缘层ISL2、以及第三绝缘层ISL3。
(11)形成第三导电薄膜，并对第三导电薄膜进行构图以形成第三导电层LY3。第三导电层LY3中的各个部件通过过孔与位于其下方的元件通过过孔相连。
(12)形成第四绝缘薄膜和第五绝缘薄膜，并对第四绝缘薄膜和第五绝缘薄膜进行构图，形成过孔的同时形成第四绝缘层ISL4和第五绝缘层ISL5。
(13)形成第四导电薄膜，并对第四导电薄膜进行构图以形成第四导电层LY4。
(14)形成至少一个绝缘层并形成至少一个透明导电层，透明导电层包括导电线L1。
(15)形成发光元件的第一极E1。
(16)形成像素定义层PDL和隔垫物层PS。
(17)形成发光功能层FL。
(18)形成发光元件的第二极E2。
(19)形成封装层CPS。
本公开的至少一实施例提供一种显示装置，包括上述任一显示面板。
图8A和图8B为本公开一实施例提供的显示装置的示意图。如图8A和图8B所示，传感器SS位于显示面板DS的一侧，并位于第二显示区R2。环境光可透过第二显示区R2而被传感器SS感知。如图8B所示，显示面板的未设置传感器SS的一侧为显示侧，可以显示图像。
例如，显示装置为屏下摄像头的全面屏显示装置。例如，显示装置包括OLED或包括OLED的产品。例如，显示装置包括含有上述显示面板的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
图9为图6A所示的像素电路的工作时序图。如图9所示，一帧显示时间段，像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2、和发光阶段t3，复位控制信号RESET为低电平时，给驱动晶体管T1的栅极复位，扫描信号SCAN为低电平时，给发光元件100b的第一极E1(例如，阳极)复位。例如，如图6A所示，扫描信号SCAN为低电平时，数据电压VDATA写入，同时获取驱动晶体管T1的阈值电压Vth，并将含有数据线上数据信息的数据电压VDADA存储在电容Cst内；发光控制信号线EML为低电平时，发光元件100b发光，第一节点N1(栅极点)的电压保持(发光元件100b的发光稳定性)靠存储电容Cst维持。在像素电路10的驱动过程中，在发光阶段，存储电容用以保持电压信号，使其信号保持端的电位得以保持恒定，在驱动晶体管的栅极和源极之间形成电压，从而控制驱动晶体管形成驱动电流，进而驱动发光元件100b发光。
如图9所示，在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为开启电压，设置扫描信号SCAN为关闭电压。
如图9所示，在数据写入及阈值补偿阶段和第二复位阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为开启电压。
如图9所示，在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为关闭电压。
如图9所示，第一电压信号ELVDD和第二电压信号ELVSS均为恒定的电压信号，例如，初始化信号Vinit介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如，本公开实施例中的开启电压是指能使相应晶体管的第一极和第二极导通的电压，关闭电压是指能使相应晶体管的第一极和第二极断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图9所示的驱动波形均以P型晶体管为例进行说明。例如，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)，但不限于此。
请一并参阅图6A和图9，在第一复位阶段t1，发光控制信号EM为关闭电压，复位控制信号RESET为开启电压，扫描信号SCAN为关闭电压。此时，第一复位晶体管T6处于导通状态，而第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将第一初始化信号(初始化电压Vinit)Vinit1传输到驱动晶体管T1的栅极并被存储电容Cst存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2，发光控制信号EM为关闭电压，复位控制信号RESET为关闭电压，扫描信号SCAN为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，第二复位晶体管T7处于导通状态，第二复位晶体管T7将第二初始化信号(初始化电压Vinit)Vinit2传输到发光元件100b的第一极E1，以将发光元件100b复位。而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6处于关闭状态。此时，数据写入晶体管T2将数据电压VDATA传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号SCAN和数据电压VDATA并根据扫描信号SCAN向驱动晶体管T1的第一极写入数据电压VDATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为VDATA+Vth，其中，VDATA为数据电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容Cst两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号RESET为关闭电压，扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电压信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为VDATA+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件100b，发光元件100b发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制发光元件100b发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(VDATA+Vth-ELVDD-Vth) 2＝K(VDATA-ELVDD) 2
其中，
Figure PCTCN2021077084-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件100b的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路非常好的补偿了驱动晶体管T1的阈值电压。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动电路或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如，本公开实施例不限于图6A所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
以上以7T1C的像素电路为例进行说明，本公开的实施例包括但不限于此。需要说明的是，本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如，在另外的一些实施例中，显示面板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。当然，显示面板也可以包括小于7个晶体管的像素电路。
在本公开的实施例中，位于同一层的元件可由同一膜层经同一构图工艺行程。例如，位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示面板，包括：
    衬底基板；
    像素单元，位于所述衬底基板上，包括像素电路和发光元件，所述像素电路配置为驱动所述发光元件，所述像素电路包括驱动晶体管，所述驱动晶体管包括栅极；
    第一栅信号线，与所述驱动晶体管的栅极相连；
    恒压线，配置为向所述像素电路提供第一恒定电压；
    屏蔽电极，与所述恒压线相连，所述第一栅信号线在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
  2. 根据权利要求1所述的显示面板，其中，所述屏蔽电极在所述衬底基板上的正投影覆盖所述第一栅信号线在所述衬底基板上的正投影，所述屏蔽电极在所述衬底基板上的正投影的面积大于所述第一栅信号线在所述衬底基板上的正投影的面积。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一栅信号线在所述衬底基板上的正投影与所述屏蔽电极在所述衬底基板上的正投影的边界之间的距离大于或等于1.75μm。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述驱动晶体管的栅极在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
  5. 根据权利要求1-4任一项所述的显示面板，还包括第二栅信号线，其中，所述第二栅信号线与所述第一栅信号线相连，所述第二栅信号线在所述衬底基板上的正投影落入所述屏蔽电极在所述衬底基板上的正投影内。
  6. 根据权利要求5所述的显示面板，其中，所述第一栅信号线和所述第二栅信号线的材料不同。
  7. 根据权利要求5或6所述的显示面板，其中，所述第一栅信号线的材料包括金属，所述第二栅信号线的材料包括半导体材料经导体化形成的导电材料。
  8. 根据权利要求1-7任一项所述的显示面板，其中，所述像素电路还包括第一复位晶体管和第一初始化信号线，所述第一复位晶体管与第二栅信号线相连，所述第一复位晶体管的第一极与所述第一初始化信号线相连，所述第二栅信号线复用为所述第一复位晶体管的第二极。
  9. 根据权利要求8所述的显示面板，其中，所述恒压线包括所述第一初始化信号线。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板还包括第一电源线，所述第一电源线配置为向所述像素电路提供第一电源电压，所述像素电路还包括存储电容，
    所述存储电容的第一端与所述驱动晶体管的栅极相连，所述存储电容的第二端与所述第一电源线相连。
  11. 根据权利要求10所述的显示面板，其中，所述恒压线包括所述第一电源线。
  12. 根据权利要求10或11所述的显示面板，还包括第三电源线，其中，所述第三电源线与所述第一电源线并联，所述屏蔽电极和所述第三电源线为一体结构，所述第三电源 线与所述第一电源线的延伸方向相同。
  13. 根据权利要求1-12任一项所述的显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧，
    所述像素单元包括第一像素单元和第二像素单元，
    所述第一像素单元的像素电路和发光元件均位于所述第一显示区，
    所述第二像素单元的所述像素电路位于所述第一显示区，所述第二像素单元的所述发光元件位于所述第二显示区，
    所述第二像素单元的所述像素电路通过导电线与所述第二像素单元的所述发光元件相连，
    所述导电线在所述衬底基板上的正投影与所述第一像素单元的所述像素电路在所述衬底基板上的正投影部分交叠，
    在垂直于所述衬底基板的方向上，所述屏蔽电极位于所述导电线和所述第一栅信号线之间。
  14. 根据权利要求13所述的显示面板，其中，所述导电线在所述衬底基板上的正投影与所述第一像素单元的像素电路中的所述第一栅信号线的正投影部分交叠。
  15. 根据权利要求1-14任一项所述的显示面板，还包括栅线和数据线，其中，所述栅线配置为向所述像素电路提供扫描信号，所述数据线配置为向所述像素电路提供数据信号；
    所述像素电路还包括数据写入晶体管，所述数据写入晶体管的栅极与所述栅线相连，所述数据写入晶体管的第一极与所述数据线相连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
  16. 根据权利要求10所述的显示面板，还包括挡块，所述挡块与所述第一电源线相连，
    所述像素电路还包括阈值补偿晶体管，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极相连；所述阈值补偿晶体管的栅极与所述栅线相连；
    所述驱动晶体管的栅极通过所述第一栅信号线与所述阈值补偿晶体管的第二极相连，
    所述阈值补偿晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电连接部相连；
    所述挡块在所述衬底基板上的正投影与所述阈值补偿晶体管的所述导电连接部在所述衬底基板上的正投影至少部分交叠。
  17. 根据权利要求16所述的显示面板，其中，所述挡块在所述衬底基板上的正投影与所述第二栅信号线在所述衬底基板上的正投影部分交叠。
  18. 根据权利要求1-17任一项所述的显示面板，还包括第二复位控制信号线，其中，所述像素电路还包括第二复位晶体管，所述第二复位晶体管的栅极与所述第二复位控制信号线相连，所述第二复位晶体管的第一极与第二初始化信号线相连，所述第二复位晶体管 的第二极与所述发光元件的第一极相连。
  19. 根据权利要求1-18任一项所述的显示面板，还包括发光控制信号线，其中，所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管，
    所述第一发光控制晶体管的栅极与所述发光控制信号线相连，所述第一发光控制晶体管的第一极与所述第一电源线相连，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连；
    所述第二发光控制晶体管的栅极与所述发光控制信号线相连，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连，所述第二发光控制晶体管的第二极与所述发光元件的第一极相连。
  20. 一种显示装置，包括根据权利要求1-19任一项所述的显示面板。
  21. 根据权利要求20所述的显示装置，还包括传感器，其中，所述传感器位于所述显示面板的一侧。
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