WO2022087821A1 - 显示面板及其驱动方法和显示装置 - Google Patents

显示面板及其驱动方法和显示装置 Download PDF

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Publication number
WO2022087821A1
WO2022087821A1 PCT/CN2020/123974 CN2020123974W WO2022087821A1 WO 2022087821 A1 WO2022087821 A1 WO 2022087821A1 CN 2020123974 W CN2020123974 W CN 2020123974W WO 2022087821 A1 WO2022087821 A1 WO 2022087821A1
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WIPO (PCT)
Prior art keywords
transistor
light
reset
gate
electrode
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PCT/CN2020/123974
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English (en)
French (fr)
Inventor
王丽
杨倩
董甜
盖人荣
王景泉
王博
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/435,249 priority Critical patent/US11798474B2/en
Priority to PCT/CN2020/123974 priority patent/WO2022087821A1/zh
Priority to CN202080002476.2A priority patent/CN114830222B/zh
Publication of WO2022087821A1 publication Critical patent/WO2022087821A1/zh
Priority to US18/244,368 priority patent/US20230419903A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • At least one embodiment of the present disclosure relates to a display panel, a driving method thereof, and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • OLED Unlike Liquid Crystal Display (LCD), which uses a stable voltage to control brightness, OLED is current-driven and requires a stable current to control its light emission.
  • the basic function of the pixel circuit in the AMOLED display device is to refresh the display signal at the beginning of the frame period, and use the storage capacitor Cst to maintain a stable signal voltage during the frame period and apply it to the control terminal of the driving device, such as the driving thin film transistor (TFT). , DTFT) between the gate and the source, so that the driving device can stably output the driving current in the frame period to drive the OLED to emit light.
  • TFT driving thin film transistor
  • At least one embodiment of the present disclosure relates to a display panel, a driving method thereof, and a display device.
  • At least one embodiment of the present disclosure provides a display panel including: a light-emitting unit including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor, a first reset transistor, and a second reset transistor; the first reset transistor is connected to the gate of the driving transistor and is configured to reset the gate of the driving transistor, and the second reset transistor is connected to the gate of the light-emitting element a first electrode is connected and configured to reset the first electrode of the light-emitting element; a first initialization signal line is connected to the gate of the driving transistor through the first reset transistor; and a second initialization A signal line is connected to the first electrode of the light-emitting element through the second reset transistor; the first initialization signal line and the second initialization signal line are insulated from each other and configured to input signals respectively.
  • a first electrode of the first reset transistor is connected to the first initialization signal line, and a second electrode of the first reset transistor is connected to the gate of the driving transistor , the first electrode of the second reset transistor is connected to the second initialization signal line, and the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element.
  • the first initialization signal line is configured to input an AC signal
  • the first initialization signal line is configured to send an AC signal to all the gates of the driving transistor in the stage of resetting the gate.
  • the first reset transistor inputs a first voltage, and is configured to input a second voltage, which is greater than the first voltage, to the first reset transistor during a light-emitting phase of the light-emitting element.
  • the second initialization signal line is configured to input a DC signal.
  • the first initialization signal line and the second initialization signal line extend substantially in the same direction.
  • both the first initialization signal line and the second initialization signal line extend along a first direction
  • the light emitting unit includes a first light emitting unit and a second light emitting unit adjacent in the second direction Two light-emitting units, the second direction intersects the first direction; in the second direction, the second initialization signal line of the second light-emitting unit and the first light-emitting unit of the first light-emitting unit
  • An initialization signal line is located between the driving transistor of the first light-emitting unit and the driving transistor of the second light-emitting unit; the second initialization signal line of the second light-emitting unit is longer than the first light-emitting unit.
  • the first initialization signal line of the light-emitting unit is closer to the driving transistor of the first light-emitting unit.
  • the display panel further includes a base substrate;
  • the first reset transistor is a double-gate transistor, the first reset transistor includes a first channel and a second channel, and the first channel The channel and the second channel are connected by a first conductive connection part, and the orthographic projection of the first conductive connection part of the first reset transistor of the first light emitting unit on the base substrate at least partially falls
  • the second initialization signal line entering the second light emitting unit is in the orthographic projection on the base substrate.
  • the first conductive connection portion of the first reset transistor of the first light-emitting unit and the second initialization signal line of the second light-emitting unit constitute a stabilization capacitor.
  • the orthographic projections of the first gate and the second gate of the first reset transistor on the base substrate are the same as the first channel and the second gate of the first reset transistor. Orthographic projections of the second channels on the base substrate respectively overlap.
  • the display panel further includes a reset control signal line; the first gate and the second gate of the first reset transistor are respectively a part of the reset control signal line.
  • the display panel further includes a first power supply line configured to provide a first voltage signal to the pixel circuit;
  • the pixel circuit further includes a storage capacitor, the storage capacitor The first pole of the capacitor is connected to the gate of the driving transistor, and the second pole of the storage capacitor is connected to the first power supply line;
  • the orthographic projection of the first power supply line on the base substrate is connected to the The orthographic projections of the first conductive connection portion on the base substrate at least partially overlap.
  • the first power line and the first conductive connection portion form a stable capacitance.
  • the orthographic projection of the first conductive connection portion on the base substrate falls within the orthographic projection of the first power line on the base substrate.
  • the gate of the driving transistor is connected to the second electrode of the first reset transistor through a connection line
  • the orthographic projection of the first power line on the base substrate is connected to the second electrode of the first power supply line. Orthographic projections of the connection lines on the base substrate at least partially overlap.
  • the orthographic projection of the connection line on the base substrate falls within the orthographic projection of the first power line on the base substrate.
  • connection line and the first power line form a stable capacitor.
  • the first power line is in a grid shape, and includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion and the second portion extending along the second direction.
  • the second part crosses.
  • the display panel further includes a power supply connection line, and the first power supply line is connected to the second pole of the storage capacitor through the power supply connection line.
  • the display panel further includes a connection electrode, one end of the connection electrode is electrically connected to the first initialization signal line, and the other end of the connection electrode is connected to the first reset transistor through a second end.
  • One pole is connected, and a plurality of connection electrodes and a plurality of power supply connection lines are provided, and the plurality of connection electrodes and the plurality of power supply connection lines are alternately arranged in the second direction.
  • the display panel further includes a gate line configured to input a scan signal to the pixel circuit and a data line configured to input a data signal to the pixel circuit
  • the pixel circuit further includes a data writing transistor, the gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the data writing transistor is connected to the gate line.
  • the second pole of the transistor is connected to the first pole of the driving transistor.
  • the pixel circuit further includes a threshold compensation transistor, a gate of the threshold compensation transistor is connected to the gate line, and a first electrode of the threshold compensation transistor is connected to a first electrode of the driving transistor.
  • the diodes are connected, and the second electrode of the threshold compensation transistor is connected to the gate of the driving transistor.
  • the threshold compensation transistor is a dual gate transistor, the threshold compensation transistor includes a first channel and a second channel, the first channel of the threshold compensation transistor and the The second channel is connected by a second conductive connection portion, the orthographic projection of the second conductive connection portion on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate .
  • the orthographic projection of the second conductive connection portion on the base substrate completely falls within the orthographic projection of the first power line on the base substrate.
  • the second conductive connection portion and the first power line form a stable capacitance.
  • the display panel further includes a stopper, the stopper is connected to the first power line, and the orthographic projection of the second conductive connection portion on the base substrate corresponds to the stopper
  • the orthographic projections of the blocks on the base substrate at least partially overlap, and the block and the second conductive connection portion form a stable capacitance.
  • the display panel further includes a light emission control signal line
  • the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, and a gate of the first light emission control transistor is connected to the light emission a control signal line is connected, the first pole of the first light-emitting control transistor is connected to the first power supply line, and the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor;
  • the gates of the second light-emitting control transistors are connected to the light-emitting control signal lines, the first electrodes of the second light-emitting control transistors are connected to the second electrodes of the driving transistors, and the second electrodes of the second light-emitting control transistors are connected to The first poles of the light emitting elements are connected.
  • the display panel further includes a second power supply terminal, and the second power supply terminal is connected to the second pole of the light-emitting element.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • At least one embodiment of the present disclosure also provides a method for driving a display panel, including: in a reset stage, resetting the gate of the driving transistor and resetting the first pole of the light-emitting element;
  • the resetting of the gate includes: setting the reset control signal to be the turn-on voltage, turning on the first reset transistor, and inputting the first voltage to the first electrode of the first reset transistor to convert the first voltage through the first reset transistor.
  • the reset control signal line is configured to input the reset control signal; in the light-emitting phase, the light-emitting element is driven to emit light, and a second voltage is input to the first electrode of the first reset transistor, and the second voltage is greater than the first voltage.
  • resetting the first electrode of the light-emitting element includes transmitting an initialization signal to the first electrode of the light-emitting element through a second reset transistor.
  • the initialization signal is a DC signal.
  • 1 is a schematic diagram of a 7T1C pixel circuit
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure
  • FIG. 4 is a working timing diagram of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of forming an active layer, a source electrode and a drain electrode of a thin film transistor in a display panel according to an embodiment of the present disclosure
  • FIG. 8 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure
  • FIG. 9 is a schematic plan view of a display panel after forming a second conductive pattern layer according to an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure.
  • FIG. 11 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the disclosure
  • FIG. 12 is a plan view of a fourth conductive pattern layer in a display panel provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to an embodiment of the disclosure
  • FIG. 14 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure
  • 15 is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • 16 is a plan view of a display panel according to an embodiment of the present disclosure.
  • 17 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 18 is a partial circuit schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a circuit for generating dual initialization signals of a display panel according to an embodiment of the present disclosure.
  • the pixel unit includes a pixel circuit and a light-emitting element, and the pixel circuit is configured to drive the light-emitting element to emit light.
  • the light-emitting element is an OLED as an example, but it is not limited thereto.
  • the pixel circuit is configured to provide a drive current to drive the light-emitting element to emit light.
  • the voltage holding ratio (Voltage Holding Ratio, VHR) of the storage capacitor Cst determines the stability and effective average value of the driving current of the light-emitting element in the pixel unit, thereby determining the The stability and effective brightness of the pixel unit's display light emission, and the leakage current of the relevant loop formed by the switch TFT (Switch TFT, STFT) in the pixel circuit has a direct impact on the voltage retention rate of the storage capacitor Cst, resulting in a visual flicker (Flicker) .
  • FIG. 1 is a schematic diagram of a 7T1C pixel circuit.
  • FIG. 2 is an operation timing diagram of the pixel circuit shown in FIG. 1 .
  • the pixel circuit shown in FIG. 1 may be a pixel circuit of a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) AMOLED common in the related art.
  • LTPS Low Temperature Poly-silicon
  • the pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20 .
  • the pixel circuit 10 includes six switching transistors ( T2 - T7 ), one driving transistor T1 and one storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
  • the light-emitting element 20 includes a first electrode 201 and a second electrode 202 and a light-emitting functional layer between the first electrode 201 and the second electrode 202 .
  • the first pole 201 is an anode
  • the second pole 202 is a cathode
  • the threshold compensation transistor T3 and the first reset transistor T6 are double-gate TFTs (ie, two sub-TFTs are connected in series) to reduce leakage.
  • the display panel includes a gate line GT, a data line DT, a first power supply terminal VDD, a second power supply terminal VSS, a light emission control signal line EML, an initialization signal line INT, a first reset control signal line RT1, a second power supply terminal The reset control signal line RT2 and the like.
  • the first power supply terminal VDD is configured to provide a constant first voltage signal ELVDD to the pixel unit 101
  • the second power supply terminal VSS is configured to provide a constant second voltage signal ELVSS to the pixel unit 101
  • the first voltage signal ELVDD is greater than the first voltage signal ELVDD.
  • Two voltage signals ELVSS Two voltage signals ELVSS.
  • the gate line GT is configured to provide a scan signal SCAN to the pixel unit 101
  • the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 101
  • the light emission control signal line EML is configured to provide light emission control to the pixel unit 101 signal EM
  • the first reset control signal line RT1 is configured to provide a reset control signal RESET to the pixel unit 101
  • the second reset control signal line RT1 is configured to provide a scan signal SCAN to the pixel unit 101
  • the initialization signal line INT is configured to provide the pixel unit 101 with a scan signal SCAN.
  • the pixel unit 101 provides the initialization signal Vinit.
  • the initialization signal Vinit is a constant voltage signal, and its magnitude may be between, but not limited to, the first voltage signal ELVDD and the second voltage signal ELVSS, for example, the initialization signal Vinit may be less than or equal to the second voltage signal ELVSS .
  • the driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS and other signals. glow.
  • the driving method of the pixel unit includes a first reset phase t1, data writing and threshold compensation, and a second reset phase t2 and light-emitting phase t3.
  • the reset control signal RESET is at a low level
  • the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode 201 (eg, the anode) of the light-emitting element 20 is reset.
  • the voltage of the gate of the driving transistor T1 is the voltage of the first node N1 .
  • the scan signal SCAN is at a low level
  • the data voltage VDATA is written, and the threshold voltage Vth of the driving transistor T1 is obtained at the same time, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; the light-emitting control signal line EML is at a low level
  • the light emitting element 20 emits light, and the voltage of the first node N1 (light emission stability of the light emitting element 20 ) is maintained by the storage capacitor Cst.
  • the storage capacitor is used to hold the voltage signal, so that the potential of the signal holding terminal can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form
  • the driving current drives the light-emitting element 20 to emit light.
  • the node since there is a leakage path at the node (the first node N1) where the signal holding terminal of the storage capacitor is coupled to the control electrode of the driving transistor, the node will leak electricity through the leakage path, so that the potential of the signal holding terminal of the storage capacitor cannot be If it remains constant for a long time, the driving current formed by the driving transistor is unstable, which affects the luminous brightness of the light-emitting device, thereby affecting the display effect of the display device.
  • the initialization signal Vinit is usually a low voltage, for example, about -3V.
  • the initialization signal Vinit is usually a low voltage, for example, about -3V.
  • L1 passing through the first reset transistor T6 is generated.
  • Path leakage since the potential of the first node N1 is lower than the voltage of the initialization signal Vinit, L1 passing through the first reset transistor T6 is generated.
  • Path leakage In the light-emitting stage t3, leakage current through the L2 path of the threshold compensation transistor T3 may also occur.
  • the leakage current causes the potential of the first node N1 to change, so that the display brightness fluctuates during the frame period, thereby generating a visual flicker (Flicker).
  • flicker visual flicker
  • FIG. 3 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is an operation timing diagram of the pixel circuit shown in FIG. 3 .
  • the display panel includes a plurality of pixel units 101 .
  • each pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20 .
  • the driving method of the pixel unit includes a first reset phase t1 , data writing and threshold compensation, a second reset phase t2 and a light-emitting phase t3 .
  • the pixel circuit includes a driving transistor T1, a first reset transistor T6 and a second reset transistor T7; the first reset transistor T6 is connected to the gate of the driving transistor T1 and is configured to connect to the gate of the driving transistor T1 For reset, the second reset transistor T7 is connected to the first electrode 201 of the light emitting element 20 and configured to reset the first electrode 201 of the light emitting element 20 .
  • the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6.
  • the second initialization signal line INT2 is connected to the first electrode 201 of the light emitting element 20 through the second reset transistor T7, the first initialization signal line INT1 and the second initialization signal line INT2 are insulated from each other, and are configured to input signals, respectively.
  • signals can be respectively input to the first initialization signal line INT1 and the second initialization signal line INT2 which are insulated from each other, and the potential of the first initialization signal line INT1 is increased in the light-emitting stage, so that in the light-emitting stage
  • the leakage current of the first node N1 is reduced, the voltage retention rate of the storage capacitor in the pixel circuit is improved, and the problem of flicker deterioration caused by excessive leakage current is improved, so as to realize the display without flicker, thereby improving the display quality of the display product.
  • the display panel provided by the embodiments of the present disclosure can improve the flicker problem caused by excessive leakage current in the case of low frame rate driving, and has good display quality.
  • the display panel including the first initialization signal line INT1 and the second initialization signal line INT2 as described above can realize driving at 30 Hz without affecting the display effect.
  • the light emitting element 20 is an organic light emitting diode (OLED), and the light emitting element 20 emits red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit 10 .
  • one pixel includes a plurality of pixel units.
  • One pixel may include a plurality of pixel units that emit light of different colors.
  • one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
  • the number of pixel units included in a pixel and the light output of each pixel unit can be determined as required.
  • the first pole of the first reset transistor T6 is connected to the first initialization signal line INT1
  • the second pole of the first reset transistor T6 is connected to the gate of the driving transistor T1
  • the second pole of the second reset transistor T7 is connected to the gate of the driving transistor T1.
  • the first electrode is connected to the second initialization signal line INT2
  • the second electrode of the second reset transistor T7 is connected to the first electrode 201 of the light emitting element 20 .
  • the gate of the first reset transistor T6 is connected to the first reset control signal line RT1
  • the gate of the second reset transistor T7 is connected to the second reset control signal line RT2.
  • the pixel circuit 10 further includes a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7 and a storage capacitor Cst.
  • the first electrode of the first reset transistor T6 and the first electrode of the second reset transistor T7 are connected with the first initialization signal line INT1 and the first reset transistor T7 respectively.
  • the two initialization signal lines INT2 are connected so as to input the first initialization signal Vinit1 and the second initialization signal Vinit2 respectively.
  • the first power supply terminal VDD is configured to provide a first voltage signal ELVDD to the pixel circuit 10; the pixel circuit further includes a storage capacitor Cst, and the first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1 , the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD.
  • the display panel further includes a gate line GT and a data line DT.
  • the gate line is configured to input the scan signal SCAN to the pixel circuit 10
  • the data line DT is configured to input the data signal DATA (data signal) to the pixel circuit 10 .
  • voltage VDATA voltage
  • the pixel circuit 10 further includes a data writing transistor T2, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first electrode T21 of the data writing transistor T2 is connected to the data line DT, The second pole T22 of the data writing transistor T2 is connected to the first pole T11 of the driving transistor T1.
  • the pixel circuit 10 further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, and the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1
  • the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
  • the display panel further includes an emission control signal line EML
  • the pixel circuit 10 further includes a first emission control transistor T4 and a second emission control transistor T5, and the gate T40 of the first emission control transistor T4 is connected to the emission control transistor T4.
  • the signal line EML is connected, the first electrode T41 of the first light-emitting control transistor T4 is connected to the first power supply terminal VDD, the second electrode T42 of the first light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1; the second light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1;
  • the gate T50 of the transistor T5 is connected to the light-emitting control signal line EML, the first electrode T51 of the second light-emitting control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is connected to the light-emitting element.
  • the first pole 201 of 20 is connected.
  • the first electrode T41 of the first light emission control transistor T4 is connected to the first power supply terminal VDD through the first power supply line VDD1 (refer to FIG. 10 and FIG. 11 ).
  • the display panel further includes a second power supply terminal VSS, and the second power supply terminal VSS is connected to the second pole 201 of the light-emitting element 20 .
  • the first initialization signal line INT1 is configured to input an AC signal
  • the first initialization signal line INT1 is configured to input the first reset transistor T6 to the first reset transistor T6 at the stage of resetting the gate of the driving transistor T1.
  • a voltage V1 and is configured to input a second voltage V2 to the first reset transistor T6 during the light-emitting phase of the light-emitting element, and the second voltage V2 is greater than the first voltage V1.
  • the second voltage V2 is a positive voltage and the first voltage is a negative voltage, but not limited thereto, as long as the second voltage V2 is greater than the first voltage V1, the flicker problem caused by the leakage of the L1 channel can be alleviated.
  • the first voltage V1 is about -3V, but not limited to this.
  • the second voltage V2 is about 1V-3V, but not limited thereto.
  • the second initialization signal line INT2 is configured to input a DC signal.
  • a DC signal is a constant voltage signal.
  • a DC signal is a constant negative voltage.
  • the DC signal is a voltage signal of about -3V, but is not limited to this.
  • the display panel adopts a pixel circuit design suitable for low frame rate driving.
  • the pixel circuit adopts a first initialization signal line and a second initialization signal line that are insulated from each other, and the signal of the first initialization signal line is designed as a pulse signal.
  • the node N1 passes through the L1 leakage path of the first reset transistor T6 to improve the brightness increase problem caused by the leakage of low grayscale.
  • the first voltage V1 is input to the first reset transistor T6.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the on voltage
  • the scan signal SCAN is set as the off voltage.
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the off voltage
  • the scan signal SCAN is set as the on voltage.
  • the light-emitting control signal EM is set to be the turn-on voltage
  • the reset control signal RESET is set to be the turn-off voltage
  • the scan signal SCAN is set to the turn-off voltage.
  • the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals, for example, the second initialization signal Vinit2 is between the first voltage signal ELVDD and the second voltage signal ELVSS.
  • the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor
  • the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V)
  • the turn-on voltage is a high voltage (eg, 5V)
  • the turn-off voltage is high.
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 4 are all described by taking a P-type transistor as an example.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V), but not limited thereto.
  • the first reset transistor T6 transmits the first initialization signal (initialization voltage) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resets the driving transistor T1 and erases the data stored in the last (last frame) light emission.
  • the light emission control signal EM is the off voltage
  • the reset control signal RESET is the off voltage
  • the scan signal SCAN is the on voltage.
  • the data writing transistor T2 and the threshold value compensation transistor T3 are in the conducting state
  • the second reset transistor T7 is in the conducting state
  • the second reset transistor T7 transmits the second initialization signal (initialization voltage) Vinit2 to the first light-emitting element 20.
  • An electrode 201 to reset the light-emitting element 20 is in an off state.
  • the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and transmits the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN Write data voltage VDATA.
  • the threshold compensation transistor T3 is turned on to connect the drive transistor T1 in a diode configuration, thereby charging the gate of the drive transistor T1.
  • the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and adjusts the driving transistor according to the scan signal SCAN.
  • the gate voltage of T1 performs threshold voltage compensation. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.
  • the light-emitting control signal EM is the turn-on voltage
  • the reset control signal RESET is the turn-off voltage
  • the scan signal SCAN is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is kept as VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1 and the
  • the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light according to the light emission control signal EM.
  • the luminous current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor T1
  • W and L are the channel width and channel length of the driving transistor T1, respectively
  • Vgs is the gate and source of the driving transistor T1 The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the pixel circuit of the present invention compensates the threshold voltage of the driving transistor T1 very well.
  • the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted.
  • the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display time period of one frame.
  • adjusting the ratio of the duration of the light-emitting phase t3 to the display duration of one frame is achieved by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.
  • the potential of the first initialization signal Vinit1 is increased to reduce the leakage current of the first node N1 and reduce the display flicker problem.
  • the embodiment of the present disclosure is not limited to the specific pixel circuit shown in FIG. 1 , and other pixel circuits that can realize compensation for the driving transistor may be used. Based on the description and teaching of the present disclosure, other arrangements that can be easily conceived by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
  • FIG. 5 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • 7 is a schematic diagram of forming an active layer, a source electrode and a drain electrode of a thin film transistor in a display panel according to an embodiment of the present disclosure.
  • 8 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of a display panel after forming a second conductive pattern layer according to an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure.
  • 11 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the disclosure.
  • 12 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure.
  • 13 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to an embodiment of the disclosure.
  • FIG. 14 is a flowchart of a method for fabricating a display panel according to an embodiment of the present disclosure.
  • 15 is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view taken along line CD in FIG. 13 .
  • FIG. 5 shows the semiconductor pattern SCP
  • FIG. 6 shows the first conductive pattern layer LY1, for example, a first gate insulating layer (the first gate insulating layer GI1, Refer to Figure 15).
  • the first conductive pattern layer LY1 includes a first reset control signal line RT1, a gate line GT, a first electrode Ca of the storage capacitor Cst (gate T10 of the driving transistor T1), a light emission control signal line EML, a Two reset control signal lines RT2.
  • the semiconductor pattern SCP is doped with the first conductive pattern layer LY1 as a mask, so that the area of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 retains semiconductor characteristics to form an active layer, while the semiconductor pattern SCP is not covered by the first conductive pattern layer LY1.
  • a region covered by a conductive pattern layer LY1 is conductorized to form the source and drain electrodes of the thin film transistor.
  • 7 shows the active layer ACT formed after the semiconductor pattern SCP is partially conductorized.
  • the gate line GT of the current stage is connected to the reset control signal line of the next stage.
  • the gate line GT and the second reset control signal line RT2 may be electrically connected to input the same signal at the same time.
  • a self-alignment process is used to conduct conductorization treatment on the semiconductor pattern layer SCP with the first conductive pattern layer LY1 as a mask.
  • the pattern layer SCP is heavily doped, so that the part of the semiconductor pattern layer SCP that is not covered by the first conductive pattern layer LY1 is conductive, forming the source region (the first electrode T11) and the drain region (the first electrode T11) of the driving transistor T1.
  • Diode T12 the source region (first electrode T21) and the drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and the drain region ( The second electrode T32), the source region (the first electrode T41) and the drain region (the second electrode T42) of the first light emission control transistor T4, the source region (the first electrode T51) of the second light emission control transistor T5 and the The drain region (the second electrode T52), the source region (the first electrode T61) and the drain region (the second electrode T62) of the first reset transistor T6, and the source region (the first electrode) of the second reset transistor T7 T71) and the drain region (the second electrode T72).
  • the part of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retains semiconductor characteristics, forming the channel region T13 of the driving transistor T1, the channel region T23 of the data writing transistor T2, the channel region T33 of the threshold compensation transistor T3, The channel region T43 of the first light emission control transistor T4, the channel region T53 of the second light emission control transistor T5, the channel region T63 of the first reset transistor T6, and the channel region T73 of the second reset transistor T7.
  • the channel region of each transistor constitutes the active layer ACT (refer to FIG. 7 ).
  • the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are integrally formed; the first electrode T51 of the second light-emitting control transistor T5 and the first electrode T51 of the driving transistor T1
  • the diode T12 and the first electrode T31 of the threshold compensation transistor T3 are integrally formed; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2, and the second electrode T42 of the first light-emitting control transistor T4 are integrally formed;
  • the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.
  • the channel region (active layer) of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polysilicon (eg, low temperature polysilicon) or metal oxide semiconductor material (eg IGZO, AZO, etc.).
  • the transistors are all P-type low temperature polysilicon (LTPS) thin film transistors.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal-oxide-semiconductor thin-film transistors, that is, the channel material of the transistors is a metal-oxide-semiconductor material (such as IGZO , AZO, etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
  • the transistors employed in the embodiments of the present disclosure may include various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
  • a part of the light emission control signal line EML serves as the gate T40 of the first light emission control transistor T4
  • a part of the light emission control signal line EML serves as the gate T50 of the second light emission control transistor T5
  • the first reset transistor The gate T60 of T6 is part of the first reset control signal line RT1
  • the gate T70 of the second reset transistor T7 is part of the second reset control signal line RT2
  • the gate T20 of the data writing transistor T2 is the gate line GT Part of the gate T30 of the threshold compensation transistor T3 is part of the gate line GT.
  • the first reset transistor T6 is a double-gate transistor
  • the first reset transistor T6 includes a first channel T631 and a second channel T632, and the first channel T631 and the second channel T632 are connected through a first conductive connection connected to CP1.
  • the threshold compensation transistor T3 is a double-gate transistor
  • the threshold compensation transistor T3 includes a first channel T331 and a second channel T332, and the first channel T331 and the second channel T332 are connected through a second conductive connection portion CP2.
  • the first conductive connection portion CP1 is the middle node of the first reset transistor T6, and the second conductive connection portion CP2 is the middle node of the threshold compensation transistor T3.
  • FIG. 8 shows the second conductive pattern layer LY2.
  • a second gate insulating layer (second gate insulating layer GI2, see FIG. 15 ) is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1.
  • the second conductive pattern layer LY2 includes a stopper BK, a first initialization signal line INT1, a second initialization signal line INT2, and a second pole Cb of the storage capacitor Cst.
  • the block BK can be connected to the first power line VDD1 to provide a constant voltage, the block BK is configured to block the second conductive connection CP2 between the two channels of the threshold compensation transistor T3, and the block BK is connected to the second conductive
  • the connection part CP2 forms a capacitor (stabilizing capacitor) to avoid leakage current generated by the threshold compensation transistor T3 and to avoid affecting the display effect.
  • the first power supply line VDD1 is connected to the first power supply terminal VDD, and the first power supply line VDD1 is configured to supply the first voltage signal ELVDD to the pixel circuit 10 .
  • the second pole Cb of the storage capacitor Cst is connected to the first power line VDD1.
  • the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD through the first power supply line VDD1.
  • the third conductive pattern layer LY3 includes a data line DT, a power supply connection line VDD0, a first connection electrode CEa, a second connection electrode CEb, a third connection electrode CEc, and a fourth connection electrode CEd.
  • An interlayer insulating layer (interlayer insulating layer ILD, see FIG. 15 ) is provided between the third conductive pattern layer LY3 and the second conductive pattern layer LY2 .
  • the data line DT is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole H1
  • the power connection line VDD0 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole H2.
  • the power connection line VDD0 is electrically connected to the second pole Cb of the storage capacitor Cst through the via holes H3 and H30, and the power supply connection line VDD0 is electrically connected to the conductive block BK through the via hole H0.
  • One end of the first connection electrode CEa is electrically connected to the first initialization signal line INT1 through the via hole H12, and the other end of the first connection electrode CEa is connected to the first electrode T61 of the first reset transistor T6 through the via hole H11, thereby making the first The first pole T61 of the reset transistor T6 is electrically connected to the first initialization signal line INT1.
  • One end of the second connection electrode CEb is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole H22, and the other end of the second connection electrode CEb is electrically connected to the gate T10 (that is, the storage capacitor) of the driving transistor T1 through the via hole H21.
  • the first electrode Ca) of Cst is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (ie, the first electrode Ca of the storage capacitor Cst).
  • connection electrode CEc One end of the third connection electrode CEc is electrically connected to the second initialization signal line INT2 through the via hole H32, and the other end of the third connection electrode CEc is connected to the first electrode T71 of the second reset transistor T7 through the via hole H31, so that the second The first electrode T71 of the reset transistor T7 is electrically connected to the second initialization signal line INT2.
  • the fourth connection electrode CEd is electrically connected to the second electrode T52 of the second light-emitting control transistor T5 through the via hole H40.
  • the fourth connection electrode CEd can be used to connect to the fifth connection electrode CEe formed later, and then to be electrically connected to the first electrode 201 (refer to FIG. 17 ) of the light-emitting element 20 .
  • FIG. 12 shows the fourth conductive pattern layer LY4.
  • the fourth conductive pattern layer LY4 includes the fifth connection electrode CEe and the first power supply line VDD1.
  • a passivation layer (passivation layer PVX, see FIG. 15 ) and a first planarization layer (first planarization layer PLN1 , see FIG. 15 ) are provided between the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 .
  • the first power supply line VDD1 is connected to the power supply connection line VDD0 through the via hole H6 passing through the passivation layer and the first planarization layer
  • the fifth connection electrode CEe is connected to the fourth power supply line VDD0 through the via hole H7 passing through the passivation layer and the first planarization layer.
  • the connecting electrodes CEd are connected.
  • FIG. 13 shows a plan view of the structure after the fourth conductive pattern layer LY4 is formed.
  • each fifth connection electrode CEe is connected to one light-emitting element, that is, each fifth connection electrode CEe corresponds to one pixel unit 101 .
  • the first initialization signal line INT1 and the second initialization signal line INT2 extend substantially in the same direction.
  • the first initialization signal line INT1 and the second initialization signal line INT2 are arranged along the second direction Y and extend along the first direction X respectively.
  • both the first initialization signal line INT1 and the second initialization signal line INT2 extend along the first direction X
  • the light emitting unit 101 includes the first light emitting unit 101 a and the first light emitting unit 101 a and the first light emitting unit 101 a which are adjacent in the second direction Y.
  • the second initialization signal line INT2 of the second light-emitting unit 101b and the first initialization signal line INT1 of the first light-emitting unit 101a are located at the driving transistor T1 of the first light-emitting unit 101a and the driving of the second light-emitting unit 101b between transistor T1.
  • the second initialization signal line INT2 of the second light emitting unit 101b is closer to the driving transistor T1 of the first light emitting unit 101a than the first initialization signal line INT1 of the first light emitting unit 101a.
  • the orthographic projection of the first conductive connection portion CP1 of the first reset transistor T6 of the first light emitting unit 101 a on the base substrate BS at least partially falls into the second light emitting unit 101 b
  • the two initialization signal lines INT2 are in the orthographic projection of the base substrate BS. Since the voltage on the second initialization signal line INT2 is a constant voltage during the light-emitting stage, a first stabilizing capacitor C1 is formed between the second initialization signal line INT2 and the first conductive connection portion CP1, and the intermediate node of the first reset transistor T6 is adjusted.
  • the orthographic projection of the first gate T601 and the second gate T602 of the first reset transistor T6 on the base substrate BS is the same as that of the first reset transistor T6 .
  • Orthographic projections of the channel T631 and the second channel T632 on the base substrate BS overlap, respectively.
  • the display panel includes a plurality of power supply connection lines VDD0 , the plurality of power supply connection lines VDD0 are arranged in an array, and between two adjacent power supply connection lines VDD0 in the second direction Y are provided A first connection electrode CEa.
  • a power supply connection line VDD0 is provided between two adjacent first connection electrodes CEa in the second direction Y.
  • the first power supply line VDD1 is connected to the second pole Cb of the storage capacitor Cst through the power supply connection line VDD0 .
  • the first power supply line VDD1 is in a grid shape, and includes a first portion VDDa extending along the first direction X and a second portion VDDb extending along the second direction Y, the first portion VDDa and the first portion VDDa extending along the second direction Y.
  • the two parts of VDDb are crossed.
  • the first part VDDa and the second part VDDb are integrally formed.
  • the orthographic projection of the first power supply line VDD1 on the base substrate BS and the orthographic projection of the first conductive connection portion CP1 on the base substrate BS are at least Partially overlapping.
  • the orthographic projection of the first conductive connection portion CP1 on the base substrate BS completely falls into the projection of the first power supply line VDD1 on the base substrate BS. in the orthographic projection.
  • the gate T10 of the driving transistor T1 is connected to the second electrode T62 of the first reset transistor T6 through a connecting line (the second connecting electrode CEb), in order to reduce the voltage jump on the data line for driving Due to the influence of the gate T10 of the transistor T1, the orthographic projection of the first power supply line VDD1 on the base substrate BS at least partially overlaps the orthographic projection of the connection line (the second connection electrode CEb) on the base substrate BS.
  • the orthographic projection of the connection line (the second connection electrode CEb) on the base substrate BS at least partially falls within the orthographic projection of the first power supply line VDD1 on the base substrate BS.
  • the threshold compensation transistor T3 is a double-gate transistor.
  • the orthographic projection of the first power line VDD1 on the base substrate BS is lined with the second conductive connection part CP2.
  • the orthographic projections on the base substrate BS overlap at least partially.
  • a stable capacitance is formed between the first power line VDD1 and the second conductive connection portion CP2.
  • the orthographic projection of the second conductive connection portion CP2 on the base substrate BS completely falls into the first power line VDD1 on the base substrate BS. in the orthographic projection.
  • FIG. 16 is a plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 16 shows the first pole 201 of the light-emitting element.
  • 17 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 17 is a cross-sectional view taken along line MN in FIG. 16 .
  • the film layer on the first pole 201 of the light-emitting element is omitted.
  • the arrangement and shape of the first pole 201 of the light emitting element are not limited to those shown in FIG. 16 , and those skilled in the art can adjust the arrangement and shape of the first pole 201 of the light emitting element as required.
  • FIGS. 15 and 17 show the third direction Z, which is a direction perpendicular to the base substrate BS, the third direction Z is perpendicular to the first direction X, and the third direction Z is perpendicular to the second direction Y.
  • the buffer layer BL is located on the base substrate BS
  • the isolation layer BR is located on the buffer layer BL
  • the channel region, source and drain of the transistor are located on the isolation layer BR
  • the channel region, the source electrode and the drain electrode of the transistor are located on the isolation layer BR.
  • a first gate insulating layer GI1 is formed on the source and drain electrodes, the first conductive pattern layer LY1 is located on the first gate insulating layer GI1, the second gate insulating layer GI2 is located on the first conductive pattern layer LY1, and the second conductive pattern layer LY2 is located on the second gate insulating layer GI2, the interlayer insulating layer ILD is located on the second conductive pattern layer LY2, the third conductive pattern layer LY3 is located on the interlayer insulating layer ILD, and the passivation layer PVX is located on the first conductive pattern layer LY,
  • the first planarization layer PLN1 is located on the passivation layer PVX, and the fourth conductive pattern layer LY4 is located on the first planarization layer PLN1.
  • the second planarization layer PLN2 is located on the fourth conductive pattern layer LY4, the first pole 201 of the light emitting element 20 is located on the second planarization layer PLN2, the pixel definition layer PDL and the spacer PS are located on the second planarization layer
  • the pixel defining layer PDL has an opening OPN, and the opening OPN is configured to define a light-emitting area (light-emitting area, effective light-emitting area) of the pixel unit.
  • the spacer PS is configured to support the fine metal mask when the light emitting functional layer 203 is formed.
  • the opening OPN is the light emitting area of the light emitting unit.
  • the light emitting functional layer 203 is located on the first pole 201 of the light emitting element 20
  • the second pole 202 of the light emitting element 20 is located on the light emitting functional layer 203
  • the encapsulation layer CPS is disposed on the light emitting element 20 .
  • the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers
  • the second encapsulation layer CPS2 is an organic material layer.
  • the first electrode 201 is the anode of the light-emitting element 20
  • the second electrode 202 is the cathode of the light-emitting element 20, but it is not limited thereto.
  • the light emitting element 20 includes an organic light emitting diode.
  • the light-emitting functional layer 203 is located between the second pole 202 and the first pole 201 .
  • the second electrode 202 is located on the side of the first electrode 201 away from the base substrate BS.
  • the light-emitting functional layer 203 includes at least a light-emitting layer, and may also include a hole transport layer, a hole injection layer, and at least one of the electron transport layer and the electron injection layer. one.
  • the second electrode Cb of the storage capacitor has an opening OPN1 , and the setting of the opening OPN1 facilitates that the second connecting electrode CEb is connected to the gate T10 of the driving transistor T1 .
  • FIG. 15 shows the connecting portion Cbs for connecting the adjacent second poles Cb.
  • FIG. 18 is a partial circuit schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 18 shows a first node N1, a second node N2, a third node N3 and a fourth node N4.
  • the potential of the first node N1 corresponds to the potential of the gate of the driving transistor T1
  • the potential of the third node N3 corresponds to the potential of the intermediate node (the second conductive connection portion CP2) of the threshold compensation transistor T3
  • the potential of the fourth node N4 corresponds to at the potential of the intermediate node (the first conductive connection portion CP1 ) of the first reset transistor T6 .
  • the first conductive connection portion CP1 and the second initialization signal line INT2 form a second stabilizing capacitor C2 to reduce leakage current.
  • the second conductive connection portion CP2 and the first power supply line VDD1 form a first stabilization capacitor C1 to reduce leakage current.
  • the threshold compensation transistor T3 includes two serially connected sub-TFTs: T3a and T3b
  • the first reset transistor T6 includes two serially connected sub-TFTs: T6a and T6b.
  • FIG. 19 is a schematic diagram of a circuit for dynamically generating a first initialization signal and a second initialization signal of a display panel according to an embodiment of the present disclosure.
  • the circuit for dynamically generating the first initialization signal and the second initialization signal in the embodiment of the present disclosure is not limited to that shown in FIG. 19 , and circuits of other structures may also be used to dynamically generate the first initialization signal Vinit1 and the second initialization signal Vinit2.
  • the circuit for dynamically generating the initialization signal includes a GOA (gate driver on array) unit 300 , an inverse switch unit 400 and a dual Vinit switch unit 500 .
  • GOA gate driver on array
  • the GOA unit 300 includes a gate signal GOA unit 301 , a lighting signal GOA unit 302 , a reset signal GOA unit 303 and a lighting signal GOA unit 304 .
  • the gate signal GOA unit 301 and the reset signal GOA unit 303 may be the same unit
  • the lighting signal GOA unit 302 and the lighting signal GOA unit 304 may be the same unit.
  • the reverse switching unit 400 includes two thin film transistors: TFT T01 and TFT T02.
  • the double initialization signal switch unit 500 includes two thin film transistors: TFT T03 and TFT T04.
  • the first pole of TFT T01 is connected to the high-level signal line SLH to be input with the high-level signal VGH
  • the second pole of TFT T01 is connected to the first pole of TFT T02
  • the second pole of TFT T02 is connected to the first pole of TFT T02.
  • the first electrode of the TFT T03 is connected to the first voltage signal line SL1 to receive the first voltage V1
  • the second electrode of the TFT T03 is connected to the second voltage signal line SL2 to receive the second voltage V2.
  • the first voltage signal line SL1 is a constant voltage signal line
  • the second voltage signal line SL2 is a constant voltage signal line.
  • the gate of TFT T01 and the gate of TFT T03 are connected to the light-emitting signal GOA unit 304, the gate of TFT T02 is connected to the reset signal GOA unit 303, and the gate of TFT T04 is connected to the second pole of TFT T01 (the first pole of TFT T02) is connected.
  • the output voltage of the first initialization signal Vinit1 is the first voltage V1 (higher voltage)
  • the reset signal RESET output is low
  • the lower voltage of the first initialization signal Vinit1 is output
  • XEMS_INV is the bootstrap voltage output by the reset signal GOA unit 303
  • the output voltage of the first initialization signal Vinit1 is the second voltage V2 at this time.
  • the second voltage V2 is about -3V
  • the range of the first voltage V1 is 1V to 3V, but not limited thereto.
  • XEMS_INV is the inverse signal of XEMS.
  • TFT T01 and TFT T03 are turned on, TFT T02 and TFT T04 are turned off, and in other stages except the light-emitting stage, TFT T01 and TFT T03 are turned off, and TFT T02 and TFT T04 are turned on.
  • Other stages except the light emitting stage may be the first reset stage t1
  • other stages except the light emitting stage may be the first reset stage t1 and the data writing and threshold compensation and the second reset stage t2.
  • the transistors in the pixel circuits of the embodiments of the present disclosure are all thin film transistors.
  • the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, and the fourth conductive pattern layer LY4 are all made of metal materials.
  • the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto.
  • the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are formed of materials such as titanium, aluminum, etc., but are not limited thereto.
  • the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are structures formed by three sub-layers of Ti/AL/Ti, respectively, but not limited thereto.
  • a glass substrate or a polyimide substrate can be used as the base substrate, but it is not limited thereto, and can be selected as required.
  • the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, the spacer PS All are made of insulating material.
  • the materials of the first pole 201 and the second pole 202 of the light-emitting element can be selected as required.
  • the first electrode 201 may be at least one of transparent conductive metal oxide and silver, but not limited thereto.
  • the transparent conductive metal oxide includes, but is not limited to, indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first pole 201 may adopt a structure in which three sub-layers of ITO-Ag-ITO are provided.
  • the second pole 202 may be a low work function metal, at least one of magnesium and silver may be used, but not limited thereto.
  • At least one embodiment of the present disclosure further provides a display device including any one of the above-mentioned display panels.
  • the display device includes an OLED or a low frame rate driven product including an OLED.
  • the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which contain the above-mentioned display panel.
  • At least one embodiment of the present disclosure further provides a method for driving a display panel, including: in a reset stage, resetting a gate of a driving transistor and resetting a first electrode of a light-emitting element;
  • Resetting the gate includes: setting the reset control signal to be a turn-on voltage, turning on a first reset transistor, and inputting a first voltage to a first pole of the first reset transistor to transmit the first voltage through the first reset transistor to the gate of the drive transistor, the second pole of the first reset transistor is connected to the gate of the drive transistor, the gate of the first reset transistor is connected to the reset control signal line, the reset The control signal line is configured to input the reset control signal; in the light-emitting phase, the light-emitting element is driven to emit light, and a second voltage is input to the first pole of the first reset transistor, and the second voltage is greater than the the first voltage.
  • resetting the first electrode of the light-emitting element includes transmitting an initialization signal to the first electrode of the light-emitting element through a second reset transistor.
  • the initialization signal is a DC signal.
  • the above description takes a 7T1C pixel circuit as an example, and embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display substrate may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • elements located on the same layer may be processed by the same patterning process from the same film layer.
  • elements located on the same layer may be located on a surface of the same element remote from the base substrate.
  • the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the lithography process refers to the process of film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • Corresponding patterning processes may be selected according to the structures formed in the embodiments of the present disclosure.

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Abstract

一种显示面板及其驱动方法和显示装置。显示面板包括：发光单元(101)，包括像素电路(10)和发光元件(20)，像素电路(10)被配置为驱动发光元件(20)，像素电路(10)包括驱动晶体管(T1)、第一复位晶体管(T6)和第二复位晶体管(T7)；第一复位晶体管(T6)与驱动晶体管(T1)的栅极相连，并被配置为对驱动晶体管(T1)的栅极进行复位，第二复位晶体管(T7)与发光元件(20)的第一极相连，并被配置为对发光元件(20)的第一极进行复位；第一初始化信号线(INT1)，通过第一复位晶体管(T6)与驱动晶体管(T1)的栅极相连；第二初始化信号线(INT2)，通过第二复位晶体管(T7)与发光元件(20)的第一极相连；第一初始化信号线(INT1)和第二初始化信号线(INT2)彼此绝缘，并被配置为分别输入信号。

Description

显示面板及其驱动方法和显示装置 技术领域
本公开至少一实施例涉及一种显示面板及其驱动方法和显示装置。
背景技术
随着显示技术的不断发展，有源矩阵型有机发光二极管(Active-Matrix Organic Light-Emitting Diode，AMOLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经在手机、平板电脑、数码相机等显示装置上得到越来越多地应用。
与液晶显示器(Liquid Crystal Display，LCD)利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制其发光。AMOLED显示装置中的像素电路的基本功能是：在帧周期开始时进行显示信号刷新，在帧周期中利用存储电容Cst保持稳定的信号电压并施加于驱动器件的控制端，例如驱动薄膜晶体管(TFT，DTFT)的栅极和源极之间，使驱动器件在帧周期内稳定地输出驱动电流以驱动OLED发光。
发明内容
本公开的至少一实施例涉及一种显示面板及其驱动方法和显示装置。
本公开至少一实施例提供一种显示面板，包括：发光单元，包括像素电路和发光元件，所述像素电路被配置为驱动所述发光元件，所述像素电路包括驱动晶体管、第一复位晶体管和第二复位晶体管；所述第一复位晶体管与所述驱动晶体管的栅极相连，并被配置为对所述驱动晶体管的所述栅极进行复位，所述第二复位晶体管与所述发光元件的第一极相连，并被配置为对所述发光元件的所述第一极进行复位；第一初始化信号线，通过所述第一复位晶体管与所述驱动晶体管的栅极相连；以及第二初始化信号线，通过所述第二复位晶体管与所述发光元件的所述第一极相连；所述第一初始化信号线和所述第二初始化信号线彼此绝缘，并被配置为分别输入信号。
在本公开的一些实施例中，所述第一复位晶体管的第一极与所述第一初始化信号线相连，所述第一复位晶体管的第二极与所述驱动晶体管的所述栅极相连，所述第二复位晶体管的第一极与所述第二初始化信号线相连，所述第二复位晶体管的第二极与所述发光元件的所述第一极相连。
在本公开的一些实施例中，所述第一初始化信号线被配置为输入交流信号，所述第一初始化信号线被配置为在对所述驱动晶体管的所述栅极进行复位的阶段向所述第一复位晶体管输入第一电压，并被配置为在所述发光元件的发光阶段向所述第一复位晶体管输入第二电压，所述第二电压大于所述第 一电压。
在本公开的一些实施例中，所述第二初始化信号线被配置为输入直流信号。
在本公开的一些实施例中，所述第一初始化信号线与所述第二初始化信号线大致沿相同的方向延伸。
在本公开的一些实施例中，所述第一初始化信号线和所述第二初始化信号线均沿第一方向延伸，所述发光单元包括在第二方向上相邻的第一发光单元和第二发光单元，所述第二方向与所述第一方向相交；在所述第二方向上，所述第二发光单元的所述第二初始化信号线和所述第一发光单元的所述第一初始化信号线位于所述第一发光单元的所述驱动晶体管和所述第二发光单元的所述驱动晶体管之间；所述第二发光单元的所述第二初始化信号线比所述第一发光单元的所述第一初始化信号线更靠近所述第一发光单元的所述驱动晶体管。
在本公开的一些实施例中，显示面板还包括衬底基板；所述第一复位晶体管为双栅晶体管，所述第一复位晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过第一导电连接部相连，所述第一发光单元的所述第一复位晶体管的所述第一导电连接部在所述衬底基板上的正投影至少部分落入所述第二发光单元的所述第二初始化信号线在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述第一发光单元的所述第一复位晶体管的所述第一导电连接部和所述第二发光单元的所述第二初始化信号线构成稳定电容。
在本公开的一些实施例中，所述第一复位晶体管的第一栅极和第二栅极在所述衬底基板上的正投影与所述第一复位晶体管的所述第一沟道和所述第二沟道在所述衬底基板上的正投影分别交叠。
在本公开的一些实施例中，显示面板还包括复位控制信号线；所述第一复位晶体管的第一栅极和第二栅极分别为所述复位控制信号线的一部分。
在本公开的一些实施例中，显示面板还包括第一电源线，所述第一电源线被配置为向所述像素电路提供第一电压信号；所述像素电路还包括存储电容，所述存储电容的第一极与所述驱动晶体管的栅极相连，所述存储电容的第二极与所述第一电源线相连；所述第一电源线在所述衬底基板上的正投影与所述第一导电连接部在所述衬底基板上的正投影至少部分交叠。
在本公开的一些实施例中，所述第一电源线与所述第一导电连接部构成稳定电容。
在本公开的一些实施例中，所述第一导电连接部在所述衬底基板上的正投影落入所述第一电源线在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述驱动晶体管的栅极通过连接线与所述第一复位晶体管的第二极相连，所述第一电源线在所述衬底基板上的正投影与所述连接线在所述衬底基板上的正投影至少部分交叠。
在本公开的一些实施例中，所述连接线在所述衬底基板上的正投影落入所述第一电源线在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述连接线与所述第一电源线构成稳定电容。
在本公开的一些实施例中，所述第一电源线呈网格状，包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一部分和所述第二部分交叉。
在本公开的一些实施例中，显示面板还包括电源连接线，所述第一电源线通过所述电源连接线与所述存储电容的第二极相连。
在本公开的一些实施例中，显示面板还包括连接电极，所述连接电极的一端与所述第一初始化信号线电连接，所述连接电极的另一端通过与所述第一复位晶体管的第一极相连，提供多个连接电极和多个电源连接线，所述多个连接电极和所述多个电源连接线在第二方向上交替排列。
在本公开的一些实施例中，显示面板还包括栅线和数据线，所述栅线被配置为向所述像素电路输入扫描信号，所述数据线被配置为向所述像素电路输入数据信号，所述像素电路还包括数据写入晶体管，所述数据写入晶体管的栅极与所述栅线相连，所述数据写入晶体管的第一极与所述数据线相连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
在本公开的一些实施例中，所述像素电路还包括阈值补偿晶体管，所述阈值补偿晶体管的栅极与所述栅线相连，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连，所述阈值补偿晶体管的第二极与驱动晶体管的栅极相连。
在本公开的一些实施例中，所述阈值补偿晶体管为双栅晶体管，所述阈值补偿晶体管包括第一沟道和第二沟道，所述阈值补偿晶体管的所述第一沟道和所述第二沟道通过第二导电连接部相连，所述第二导电连接部在所述衬底基板上的正投影与所述第一电源线在所述衬底基板上的正投影至少部分交叠。
在本公开的一些实施例中，所述第二导电连接部在所述衬底基板上的正投影完全落入所述第一电源线在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述第二导电连接部与所述第一电源线构成稳定电容。
在本公开的一些实施例中，显示面板还包括挡块，所述挡块与所述第一电源线相连，所述第二导电连接部在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠，所述挡块与所述第二导电连接部构 成稳定电容。
在本公开的一些实施例中，显示面板还包括发光控制信号线，所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的栅极与所述发光控制信号线相连，所述第一发光控制晶体管的第一极与所述第一电源线相连，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连；所述第二发光控制晶体管的栅极与所述发光控制信号线相连，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连，所述第二发光控制晶体管的第二极与所述发光元件的所述第一极相连。
在本公开的一些实施例中，显示面板还包括第二电源端，所述第二电源端与所述发光元件的第二极相连。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示面板。
本公开的至少一实施例还提供一种显示面板的驱动方法，包括：在复位阶段，对驱动晶体管的栅极进行复位，并对发光元件的第一极进行复位；对所述驱动晶体管的所述栅极进行复位包括：设置复位控制信号为开启电压，开启第一复位晶体管，向所述第一复位晶体管的第一极输入第一电压以通过所述第一复位晶体管将所述第一电压传输到所述驱动晶体管的所述栅极，所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连，所述第一复位晶体管的栅极与复位控制信号线相连，所述复位控制信号线被配置为输入所述复位控制信号；在发光阶段，驱动所述发光元件发光，并向所述第一复位晶体管的所述第一极输入第二电压，所述第二电压大于所述第一电压。
在本公开的一些实施例中，对所述发光元件的所述第一极进行复位包括：通过第二复位晶体管将初始化信号传输到发光元件的第一极。
在本公开的一些实施例中，所述初始化信号为直流信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种7T1C的像素电路的示意图；
图2为图1所示的像素电路的工作时序图；
图3为本公开一实施例提供的显示面板的像素电路示意图；
图4为图3所示的像素电路的工作时序图；
图5为本公开一实施例提供的一种显示面板中的半导体图形的平面图；
图6为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图；
图7为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源 层、源极和漏极的示意图；
图8为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图；
图9为本公开一实施例提供的一种显示面板中形成第二导电图案层后的平面示意图；
图10为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图；
图11为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面示意图；
图12为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图；
图13为本公开一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图；
图14为本公开的实施例提供的显示面板的制作方法的流程图；
图15为本公开的实施例提供的显示面板的局部剖视图；
图16为本公开一实施例提供的显示面板的平面图；
图17为本公开一实施例提供的显示面板的剖视图；
图18为本公开一实施例提供的显示面板的部分电路示意图；以及
图19为本公开一实施例提供的产生显示面板的双初始化信号的电路示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，市场有较大的低帧频AMOLED显示面板的需求，而低灰阶显示的主要问题在于一帧显示时间拉长，漏电恶化，低帧频AMOLED显示面板因漏电导致的闪烁问题亟待解决。
在显示装置中，像素单元包括像素电路和发光元件，像素电路被配置为驱动发光元件发光。在本公开的实施例中，以发光元件为OLED为例，但不限于此。例如，像素电路被配置为提供驱动电流以驱动发光元件发光。像素电路在两次信号刷新之间的帧周期中，存储电容Cst的电压保持率(Voltage Holding Ratio，VHR)决定了像素单元中的发光元件的驱动电流的稳定性和有效平均值，从而决定了像素单元的显示发光的稳定性和有效亮度，而像素电路中由开关TFT(Switch TFT，STFT)构成相关回路的漏电对存储电容Cst的电压保持率有直接影响，从而产生视觉闪烁感(Flicker)。
图1为一种7T1C的像素电路的示意图。图2为图1所示的像素电路的工作时序图。图1所示的像素电路可为相关技术中常见的低温多晶硅(Low Temperature Poly-silicon，LTPS)AMOLED的像素电路。
如图1所示，像素单元101包括像素电路10和发光元件20。像素电路10包括六个开关晶体管(T2-T7)、一个驱动晶体管T1和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、以及第二复位晶体管T7。发光元件20包括第一极201和第二极202以及位于第一极201和第二极202之间的发光功能层。例如，第一极201为阳极，第二极202为阴极。通常，阈值补偿晶体管T3、第一复位晶体管T6采用双栅TFT(即，2个子TFT串联)的方式降低漏电。
如图1所示，显示面板包括栅线GT、数据线DT、第一电源端VDD、第二电源端VSS、发光控制信号线EML、初始化信号线INT、第一复位控制信号线RT1、第二复位控制信号线RT2等。第一电源端VDD被配置为向像素单元101提供恒定的第一电压信号ELVDD、第二电源端VSS被配置为向像素单元101提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。栅线GT被配置为向像素单元101提供扫描信号SCAN、数据线DT被配置为向像素单元101提供数据信号DATA(数据电压VDATA)、发光控制信号线EML被配置为向像素单元101提供发光控制信号EM，第一复位控制信号线RT1被配置为向像素单元101提供复位控制信号RESET，第二复位控制信号线RT1被配置为向像素单元101提供扫描信号SCAN，初始化信号线INT被配置为向像素单元101提供初始化信号Vinit。例如，初始化信号Vinit为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vinit可小于或等于第二电压信号ELVSS。
如图1所示，驱动晶体管T1与发光元件20电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
如图2所示，一帧显示时间段，像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2和发光阶段t3，复位控制信号RESET为低电平时，给驱动晶体管T1的栅极复位，扫描信号SCAN为低电平时，给发光元件20的第一极201(例如，阳极)复位。例如，如图1所示，驱动晶体管T1的栅极的电压即为第一节点N1的电压。扫描信号SCAN为低电平时，数据电压VDATA写入，同时获取驱动晶体管T1的阈值电压Vth，并将含有数据线上数据信息的数据电压VDADA存储在电容Cst内；发光控制信号线EML为低电平时，发光元件20发光，第一节点N1的电压保持(发光元件20的发光稳定性)靠存储电容Cst维持。在像素电路10的驱动过程中，在发光阶段，存储电容用以保持电压信号，使其信号保持端的电位得以保持恒定，在驱动晶体管的栅极和源极之间形成电压，从而控制驱动晶体管形成驱动电流，进而驱动发光元件20发光。在该过程中，由于存储电容器的信号保持端与驱动晶体管的控制极耦接的节点(第一节点N1)处存在漏电通路，该节点会通过漏电通路漏电，使得存储电容器的信号保持端的电位无法长时间保持恒定，从而导致驱动晶体管所形成的驱动电流不稳定，影响发光器件的发光亮度，进而影响显示装置的显示效果。
参考图1和图2，初始化信号Vinit通常为低电压，例如-3V左右，在发光阶段t3，由于第一节点N1的电位比初始化信号Vinit的电压低，而产生通过第一复位晶体管T6的L1通路漏电。相应地，在发光阶段t3，也可能会产生通过阈值补偿晶体管T3的L2通路漏电。而漏电导致第一节点N1的电位发生变化，从而，在帧周期内显示亮度产生浮动，从而产生视觉闪烁感(Flicker)。通常，L1通路漏电比L2通路漏电对于显示效果的影响更为明显。
图3为本公开一实施例提供的显示面板的像素电路示意图。图4为图3所示的像素电路的工作时序图。显示面板包括多个像素单元101。如图3所示，每个像素单元101包括像素电路10和发光元件20。如图4所示，在一帧显示时间段内，像素单元的驱动方法包括像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2和发光阶段t3。
如图3所示，像素电路包括驱动晶体管T1、第一复位晶体管T6和第二复位晶体管T7；第一复位晶体管T6与驱动晶体管T1的栅极相连，并被配置为对驱动晶体管T1的栅极进行复位，第二复位晶体管T7与发光元件20的第一极201相连，并被配置为对发光元件20的第一极201进行复位。第一初始化信号线INT1通过第一复位晶体管T6与驱动晶体管T1的栅极相连。 第二初始化信号线INT2通过第二复位晶体管T7与发光元件20的第一极201相连，第一初始化信号线INT1和第二初始化信号线INT2彼此绝缘，并被配置为分别输入信号。
本公开的实施例提供的显示面板，可以向彼此绝缘的第一初始化信号线INT1和第二初始化信号线INT2分别输入信号，在可发光阶段提高第一初始化信号线INT1的电位，以在发光阶段降低第一节点N1的漏电，提高像素电路中存储电容的电压保持率，改善漏电流过大而导致的闪烁(Flicker)恶化问题，从而实现显示无闪烁感，进而提高显示产品的显示品质。例如，本公开的实施例提供的显示面板可在低帧频驱动的情况下改善漏电流过大而导致的闪烁问题，具有良好的显示品质。例如，一些实施例中，包括如上所述的第一初始化信号线INT1和第二初始化信号线INT2的显示面板在不影响显示效果的前提下可实现30Hz的驱动。
例如，发光元件20为有机发光二极管(OLED)，发光元件20在其对应的像素电路10的驱动下发出红光、绿光、蓝光，或者白光等。例如，一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如，一个像素包括出射红光的像素单元，出射绿光的像素单元和出射蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
例如，如图3所示，第一复位晶体管T6的第一极与第一初始化信号线INT1相连，第一复位晶体管T6的第二极与驱动晶体管T1的栅极相连，第二复位晶体管T7的第一极与第二初始化信号线INT2相连，第二复位晶体管T7的第二极与发光元件20的第一极201相连。例如，如图3所示，第一复位晶体管T6的栅极与第一复位控制信号线RT1相连，第二复位晶体管T7的栅极与第二复位控制信号线RT2相连。
如图3所示，像素电路10还包括数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容Cst。与图1所示的显示面板相比，在图3所示的显示面板中，第一复位晶体管T6的第一极和第二复位晶体管T7的第一极分别与第一初始化信号线INT1和第二初始化信号线INT2相连，以便于分别输入第一初始化信号Vinit1和第二初始化信号Vinit2。
如图3所示，第一电源端VDD被配置为向像素电路10提供第一电压信号ELVDD；像素电路还包括存储电容Cst，存储电容Cst的第一极Ca与驱动晶体管T1的栅极T10相连，存储电容Cst的第二极Cb与第一电源端VDD相连。
例如，如图3所示，显示面板还包括栅线GT和数据线DT，栅线被配置为向像素电路10输入扫描信号SCAN，数据线DT被配置为向像素电路10 输入数据信号DATA(数据电压VDATA)。
例如，如图3所示，像素电路10还包括数据写入晶体管T2，数据写入晶体管T2的栅极T20与栅线GT相连，数据写入晶体管T2的第一极T21与数据线DT相连，数据写入晶体管T2的第二极T22与驱动晶体管T1的第一极T11相连。
例如，如图3所示，像素电路10还包括阈值补偿晶体管T3，阈值补偿晶体管T3的栅极T30与栅线GT相连，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12相连，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如，如图3所示，显示面板还包括发光控制信号线EML，像素电路10还包括第一发光控制晶体管T4和第二发光控制晶体管T5，第一发光控制晶体管T4的栅极T40与发光控制信号线EML相连，第一发光控制晶体管T4的第一极T41与第一电源端VDD相连，第一发光控制晶体管T4的第二极T42与驱动晶体管T1的第一极T11相连；第二发光控制晶体管T5的栅极T50与发光控制信号线EML相连，第二发光控制晶体管T5的第一极T51与驱动晶体管T1的第二极T12相连，第二发光控制晶体管T5的第二极T52与发光元件20的第一极201相连。例如，第一发光控制晶体管T4的第一极T41通过第一电源线VDD1(参考图10、图11)与第一电源端VDD相连。
例如，如图3所示，显示面板还包括第二电源端VSS，第二电源端VSS与发光元件20的第二极201相连。
例如，如图4所示，第一初始化信号线INT1被配置为输入交流信号，第一初始化信号线INT1被配置为在对驱动晶体管T1的栅极进行复位的阶段向第一复位晶体管T6输入第一电压V1，并被配置为在发光元件的发光阶段向第一复位晶体管T6输入第二电压V2，第二电压V2大于第一电压V1。例如，第二电压V2为正电压，第一电压为负电压，但不限于此，只要第二电压V2大于第一电压V1即可达到减轻因L1通路漏电而导致的闪烁问题。例如，第一电压V1为-3V左右，但不限于此。例如，第二电压V2为1V-3V左右，但不限于此。
例如，如图4所示，第二初始化信号线INT2被配置为输入直流信号。例如，直流信号为恒定的电压信号。例如，直流信号为恒定的负电压。进一步例如，直流信号为-3V左右的电压信号，但不限于此。
例如，该显示面板采用适用于低帧频驱动的像素电路设计。该像素电路采用彼此绝缘的第一初始化信号线和第二初始化信号线，将第一初始化信号线的信号设计为脉冲信号，在发光阶段，第一初始化信号Vinit1设置为高电平，改善第一节点N1通过第一复位晶体管T6的L1漏电通路，改善低灰阶漏电导致的亮度上升问题。
例如，如图4所示，在数据写入及阈值补偿阶段t2，向第一复位晶体管T6输入第一电压V1。
如图4所示，在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为开启电压，设置扫描信号SCAN为关闭电压。
如图4所示，在数据写入及阈值补偿阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为开启电压。
如图4所示，在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为关闭电压。
如图4所示，第一电压信号ELVDD和第二电压信号ELVSS均为恒定的电压信号，例如，第二初始化信号Vinit2介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如，本公开实施例中的开启电压是指能使相应晶体管的第一极和第二极导通的电压，关闭电压是指能使相应晶体管的第一极和第二极断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图4所示的驱动波形均以P型晶体管为例进行说明。例如，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)，但不限于此。
请一并参阅图3和图4，在第一复位阶段t1，发光控制信号EM为关闭电压，复位控制信号RESET为开启电压，扫描信号SCAN为关闭电压。此时，第一复位晶体管T6处于导通状态，而第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将第一初始化信号(初始化电压)Vinit1传输到驱动晶体管T1的栅极并被存储电容Cst存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2，发光控制信号EM为关闭电压，复位控制信号RESET为关闭电压，扫描信号SCAN为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，第二复位晶体管T7处于导通状态，第二复位晶体管T7将第二初始化信号(初始化电压)Vinit2传输到发光元件20的第一电极201，以将发光元件20复位。而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6处于关闭状态。此时，数据写入晶体管T2将数据电压VDATA传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号SCAN和数据电压VDATA并根据扫描信号SCAN向驱动晶体管T1的第一极写入数据电压VDATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶 体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为VDATA+Vth，其中，VDATA为数据电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容Cst两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号RESET为关闭电压，扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电压信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为VDATA+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20，发光元件20发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制有发光元件20发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(VDATA+Vth-ELVDD-Vth) 2＝K(VDATA-ELVDD) 2
其中，
Figure PCTCN2020123974-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路非常好的补偿了驱动晶体管T1的阈值电压。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动电路或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
如图3和图4所示，在发光阶段t3，提高第一初始化信号Vinit1的电位，以减小第一节点N1的漏电流，减轻显示闪烁问题。
例如，本公开实施例不限于图1所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
以下结合图5至图15对本公开的实施例提供的显示面板进行说明。图5为本公开一实施例提供的一种显示面板中的半导体图形的平面图。图6为本 公开一实施例提供的一种显示面板中的第一导电图案层的平面图。图7为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源层、源极和漏极的示意图。图8为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图。图9为本公开一实施例提供的一种显示面板中形成第二导电图案层后的平面示意图。图10为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图。图11为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面示意图。图12为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图。图13为本公开一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图。图14为本公开的实施例提供的显示面板的制作方法的流程图。图15为本公开的实施例提供的显示面板的局部剖视图。在本公开的实施例中，为了图示清晰，平面图中，绝缘层以过孔的形式示出，绝缘层本身采用了透明化处理，并且第一导电图案层、第二导电图案层、第三导电图案层、第四导电图案层做了半透明处理。例如，图15为图13中沿CD线的剖视图。
图5示出了半导体图形SCP，图6示出了第一导电图案层LY1，例如，第一导电图案层LY1和半导体图形SCP之间设置有第一栅绝缘层(第一栅绝缘层GI1，参照图15)。如图6所示，第一导电图案层LY1包括第一复位控制信号线RT1、栅线GT、存储电容Cst的第一极Ca(驱动晶体管T1的栅极T10)、发光控制信号线EML、第二复位控制信号线RT2。以第一导电图案层LY1为掩模版对半导体图形SCP进行掺杂，使得半导体图形SCP的被第一导电图案层LY1覆盖的区域保留半导体特性，形成有源层，而半导体图形SCP的未被第一导电图案层LY1覆盖的区域被导体化，形成薄膜晶体管的源极和漏极。如7示出了半导体图形SCP被部分导体化之后形成的有源层ACT。例如，在本公开的实施例中，本级的栅线GT与下一级的复位控制信号线相连。例如，栅线GT和第二复位控制信号线RT2可以电连接以在同一时间输入相同的信号。
例如，如图7所示，在显示基板的制作过程中，采用自对准工艺，以第一导电图案层LY1为掩模对半导体图案层SCP进行导体化处理，例如，采用离子注入工艺对半导体图案层SCP进行重掺杂，从而使得半导体图案层SCP的未被第一导电图案层LY1覆盖的部分被导体化，形成驱动晶体管T1的源极区(第一极T11)和漏极区(第二极T12)、数据写入晶体管T2的源极区(第一极T21)和漏极区(第二极T22)、阈值补偿晶体管T3的源极区(第一极T31)和漏极区(第二极T32)、第一发光控制晶体管T4的源极区(第一极T41)和漏极区(第二极T42)、第二发光控制晶体管T5的源极区(第一极T51)和漏极区(第二极T52)、第一复位晶体管T6的源极区(第一极T61)和漏极区(第二极T62)、以及第二复位晶体管T7的源极区(第 一极T71)和漏极区(第二极T72)。半导体图案层SCP的被第一导电图案层L1覆盖的部分保留半导体特性，形成驱动晶体管T1的沟道区T13、数据写入晶体管T2的沟道区T23、阈值补偿晶体管T3的沟道区T33、第一发光控制晶体管T4的沟道区T43、第二发光控制晶体管T5的沟道区T53、第一复位晶体管T6的沟道区T63、以及第二复位晶体管T7的沟道区T73。各晶体管的沟道区构成有源层ACT(参考图7)。
例如，如图7所示，第二复位晶体管T7的第二极T72和第二发光控制晶体管T5的第二极T52一体形成；第二发光控制晶体管T5的第一极T51、驱动晶体管T1的第二极T12和阈值补偿晶体管T3的第一极T31一体形成；驱动晶体管T1的第一极T11、数据写入晶体管T2的第二极T22、第一发光控制晶体管T4的第二极T42一体形成；阈值补偿晶体管T3的第二极T32和第一复位晶体管T6的第二极T62一体形成。
例如，本公开实施例采用的晶体管的沟道区(有源层)可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个实施例中，该晶体管均为P型低温多晶硅(LTPS)薄膜晶体管。在另一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管，即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等)，金属氧化物半导体薄膜晶体管具有较低的漏电流，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一些实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，如图7所示，发光控制信号线EML的一部分作为第一发光控制晶体管T4的栅极T40，发光控制信号线EML的一部分作为第二发光控制晶体管T5的栅极T50，第一复位晶体管T6的栅极T60为第一复位控制信号线RT1的一部分，第二复位晶体管T7的栅极T70为第二复位控制信号线RT2的一部分，数据写入晶体管T2的栅极T20为栅线GT的一部分，阈值补偿晶体管T3的栅极T30为栅线GT的一部分。
如图7所示，第一复位晶体管T6为双栅晶体管，第一复位晶体管T6包括第一沟道T631和第二沟道T632，第一沟道T631和第二沟道T632通过第一导电连接部CP1相连。阈值补偿晶体管T3为双栅晶体管，阈值补偿晶体管T3包括第一沟道T331和第二沟道T332，第一沟道T331和第二沟道T332通过第二导电连接部CP2相连。第一导电连接部CP1为第一复位晶体管T6的中间节点，第二导电连接部CP2为阈值补偿晶体管T3的中间节点。
图8示出了第二导电图案层LY2。例如，第二导电图案层LY2和第一导 电图案层LY1之间设置有第二栅绝缘层(第二栅绝缘层GI2，参照图15)。第二导电图案层LY2包括挡块BK、第一初始化信号线INT1、第二初始化信号线INT2和存储电容Cst的第二极Cb。挡块BK可与第一电源线VDD1相连以提供恒定的电压，挡块BK被配置为遮挡阈值补偿晶体管T3的两个沟道之间的第二导电连接部CP2，挡块BK与第二导电连接部CP2形成电容(稳定电容)，避免阈值补偿晶体管T3产生漏电流，避免影响显示效果。第一电源线VDD1连接至第一电源端VDD，第一电源线VDD1被配置为向像素电路10提供第一电压信号ELVDD。存储电容Cst的第二极Cb与第一电源线VDD1相连。例如，存储电容Cst的第二极Cb通过第一电源线VDD1与第一电源端VDD相连。
如图10所示，第三导电图案层LY3包括数据线DT、电源连接线VDD0、第一连接电极CEa、第二连接电极CEb、第三连接电极CEc、第四连接电极CEd。第三导电图案层LY3和第二导电图案层LY2之间设有层间绝缘层(层间绝缘层ILD，参照图15)。参考图9至图11，数据线DT通过过孔H1与数据写入晶体管T2的第一极T21电连接，电源连接线VDD0通过过孔H2与第一发光控制晶体管T4的第一极T41电连接，电源连接线VDD0通过过孔H3和H30与存储电容Cst的第二极Cb电连接，电源连接线VDD0通过过孔H0与导电块BK电连接。第一连接电极CEa的一端通过过孔H12与第一初始化信号线INT1电连接，第一连接电极CEa的另一端通过过孔H11与第一复位晶体管T6的第一极T61相连，进而使得第一复位晶体管T6的第一极T61与第一初始化信号线INT1电连接。第二连接电极CEb的一端通过过孔H22与第一复位晶体管T6的第二极T62电连接，第二连接电极CEb的另一端通过过孔H21与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接，从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接。第三连接电极CEc的一端通过过孔H32与第二初始化信号线INT2电连接，第三连接电极CEc的另一端通过过孔H31与第二复位晶体管T7的第一极T71相连，进而使得第二复位晶体管T7的第一极T71与第二初始化信号线INT2电连接。第四连接电极CEd通过过孔H40与第二发光控制晶体管T5的第二极T52电连接。第四连接电极CEd可用来与后续形成的第五连接电极CEe相连，进而与发光元件20的第一电极201(参照图17)电连接。
图12示出了第四导电图案层LY4。第四导电图案层LY4包括第五连接电极CEe和第一电源线VDD1。第三导电图案层LY3与第四导电图案层LY4之间设有钝化层(钝化层PVX，参照图15)和第一平坦化层(第一平坦化层PLN1，参照图15)。第一电源线VDD1通过贯穿钝化层和第一平坦化层的过孔H6与电源连接线VDD0相连，第五连接电极CEe通过贯穿钝化层和 第一平坦化层的过孔H7与第四连接电极CEd相连。图13示出了形成第四导电图案层LY4后的结构的平面图。
图5至图13示出了第一方向X和第二方向Y，第二方向Y与第一方向X相交。例如，本公开的实施例以第一方向X与第二方向Y垂直为例。例如，第一方向X为像素单元的行方向，第二方向Y为像素单元的列方向。在图13中，每个第五连接电极CEe与一个发光元件相连，即，每个第五连接电极CEe对应一个像素单元101。
例如，参考图8、图9、图11和图13，第一初始化信号线INT1与第二初始化信号线INT2大致沿相同的方向延伸。例如，第一初始化信号线INT1与第二初始化信号线INT2沿第二方向Y排列，并分别沿第一方向X延伸。
例如，参考图7和图13，第一初始化信号线INT1和第二初始化信号线INT2均沿第一方向X延伸，发光单元101包括在第二方向Y上相邻的第一发光单元101a和第二发光单元101b。在第二方向Y上，第二发光单元101b的第二初始化信号线INT2和第一发光单元101a的第一初始化信号线INT1位于第一发光单元101a的驱动晶体管T1和第二发光单元101b的驱动晶体管T1之间。第二发光单元101b的第二初始化信号线INT2比第一发光单元101a的第一初始化信号线INT1更靠近第一发光单元101a的驱动晶体管T1。
例如，参考图11、图13和图15，第一发光单元101a的第一复位晶体管T6的第一导电连接部CP1在衬底基板BS上的正投影至少部分落入第二发光单元101b的第二初始化信号线INT2在衬底基板BS上的正投影内。因在发光阶段，第二初始化信号线INT2上的电压为恒定电压，第二初始化信号线INT2和第一导电连接部CP1之间形成第一稳定电容C1，对第一复位晶体管T6的中间节点进行屏蔽，降低第一初始化信号Vinit1跳变对第一复位晶体管T6的中间节点的影响，从而，利于减小第一复位晶体管T6的中间节点的漏电流，减轻漏电流带来的显示闪烁问题，提升显示品质。
例如，参考图7、图11、图13和图15，第一复位晶体管T6的第一栅极T601和第二栅极T602在衬底基板BS上的正投影与第一复位晶体管T6的第一沟道T631和第二沟道T632在衬底基板BS上的正投影分别交叠。
例如，如图10和图11所示，显示面板包括多个电源连接线VDD0，多个电源连接线VDD0呈阵列排列，在第二方向Y上相邻的两个电源连接线VDD0之间设有一个第一连接电极CEa。换句话说，在第二方向Y上相邻的两个第一连接电极CEa之间设有一个电源连接线VDD0。
例如，如图12和图13所示，第一电源线VDD1通过电源连接线VDD0与存储电容Cst的第二极Cb相连。
例如，如图12和图13所示，第一电源线VDD1呈网格状，包括沿第一方向X延伸的第一部分VDDa和沿第二方向Y延伸的第二部分VDDb，第一 部分VDDa和第二部分VDDb交叉。例如，第一部分VDDa和第二部分VDDb一体形成。
例如，参考图13和图15，为了减少第一复位晶体管的漏电流，第一电源线VDD1在衬底基板BS上的正投影与第一导电连接部CP1在衬底基板BS上的正投影至少部分交叠。
例如，参考图13和图15，为了进一步减少第一复位晶体管的漏电流，第一导电连接部CP1在衬底基板BS上的正投影完全落入第一电源线VDD1在衬底基板BS上的正投影内。
例如，参考图13和图15，驱动晶体管T1的栅极T10通过连接线(第二连接电极CEb)与第一复位晶体管T6的第二极T62相连，为了降低数据线上的电压跳变对于驱动晶体管T1的栅极T10的影响，第一电源线VDD1在衬底基板BS上的正投影与连接线(第二连接电极CEb)在衬底基板BS上的正投影至少部分交叠。例如，连接线(第二连接电极CEb)在衬底基板BS上的正投影至少部分落入第一电源线VDD1在衬底基板BS上的正投影内。
例如，参考图13和图15，阈值补偿晶体管T3为双栅晶体管，为了减轻阈值补偿晶体管T3的漏电，第一电源线VDD1在衬底基板BS上的正投影与第二导电连接部CP2在衬底基板BS上的正投影至少部分交叠。第一电源线VDD1与第二导电连接部CP2之间形成稳定电容。
例如，参考图13和图15，为了最大程度的减轻阈值补偿晶体管T3的漏电，第二导电连接部CP2在衬底基板BS上的正投影完全落入第一电源线VDD1在衬底基板BS上的正投影内。
图16为本公开一实施例提供的显示面板的平面图。图16示出了发光元件的第一极201。图17为本公开一实施例提供的显示面板的剖视图。例如，图17为图16中沿MN线的剖视图。图16中省略了发光元件的第一极201之上的膜层。当然，发光元件的第一极201的排布和形状不限于图16所示，本领域技术人员可以根据需要调整发光元件的第一极201的排布和形状。
图15和图17示出了第三方向Z，第三方向Z为垂直于衬底基板BS的方向，第三方向Z为垂直于第一方向X，并且第三方向Z为垂直于第二方向Y。
参考图15和图17，缓冲层BL位于衬底基板BS上，隔离层BR位于缓冲层BL上，晶体管的沟道区、源极和漏极位于隔离层BR上，在晶体管的沟道区、源极和漏极上形成第一栅绝缘层GI1，第一导电图案层LY1位于第一栅绝缘层GI1上，第二栅绝缘层GI2位于第一导电图案层LY1上，第二导电图案层LY2位于第二栅绝缘层GI2上，层间绝缘层ILD位于第二导电图案层LY2上，第三导电图案层LY3位于层间绝缘层ILD上，钝化层PVX位于第一导电图案层LY上，第一平坦化层PLN1位于钝化层PVX上，第四导 电图案层LY4位于第一平坦化层PLN1上。
参考图17，第二平坦化层PLN2位于第四导电图案层LY4上，发光元件20的第一极201位于第二平坦化层PLN2上，像素定义层PDL以及隔垫物PS位于第二平坦化层PLN2上，像素定义层PDL具有开口OPN，开口OPN被配置为限定像素单元的发光面积(出光区域，有效发光面积)。隔垫物PS被配置为在形成发光功能层203时支撑精细金属掩膜。
例如，开口OPN为发光单元的出光区域。发光功能层203位于发光元件20的第一极201之上，发光元件20的第二极202位于发光功能层203上，光元件20上设置封装层CPS。封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。例如，第一极201为发光元件20的阳极，第二电极202为发光元件20的阴极，但不限于此。
例如，发光元件20包括有机发光二极管。发光功能层203位于第二极202和第一极201之间。第二极202位于第一极201的远离衬底基板BS的一侧，发光功能层203至少包括发光层，还可以包括空穴传输层、空穴注入层，电子传输层、电子注入层至少之一。
如图8和图17所示，存储电容的第二极Cb具有开口OPN1，开口OPN1的设置利于第二连接电极CEb与驱动晶体管T1的栅极T10相连。图15示出了连接部Cbs，连接部Cbs用于连接相邻的第二极Cb。
图18为本公开一实施例提供的显示面板的部分电路示意图。图18示出了第一节点N1、第二节点N2、第三节点N3和第四节点N4。第一节点N1的电位对应于驱动晶体管T1的栅极的电位，第三节点N3的电位对应于阈值补偿晶体管T3的中间节点(第二导电连接部CP2)的电位，第四节点N4的电位对应于第一复位晶体管T6的中间节点(第一导电连接部CP1)的电位。参考图15和图18，第一导电连接部CP1与第二初始化信号线INT2形成第二稳定电容C2，以起到减少漏电流的作用。参考图15和图18，第二导电连接部CP2与第一电源线VDD1(挡块BK)形成第一稳定电容C1，以起到减少漏电流的作用。如图18所示，阈值补偿晶体管T3包括两个串联的子TFT：T3a和T3b，第一复位晶体管T6包括两个串联的子TFT：T6a和T6b。
图19为本公开一实施例提供的显示面板的动态产生第一初始化信号和第二初始化信号的电路示意图。当然，本公开的实施例中动态产生第一初始化信号和第二初始化信号的电路不限于图19所示，也可以采用其他结构的电路来动态产生第一初始化信号Vinit1和第二初始化信号Vinit2。
如图19所示，动态产生初始化信号的电路包括GOA(gate driver on array)单元300、反向开关单元(inverse switch unit)400和双初始化信号开关单元(dual Vinit switch unit)500。
如图19所示，GOA单元300包括栅信号GOA单元301、发光信号GOA单元302、复位信号GOA单元303和发光信号GOA单元304。例如，栅信号GOA单元301和复位信号GOA单元303可为同一个单元，发光信号GOA单元302和发光信号GOA单元304可为同一个单元。
如图19所示，反向开关单元400包括两个薄膜晶体管：TFT T01和TFT T02。如图19所示，双初始化信号开关单元500包括两个薄膜晶体管：TFT T03和TFT T04。
如图19所示，TFT T01的第一极与高电平信号线SLH相连以被输入高电平信号VGH，TFT T01的第二极与TFT T02的第一极相连，TFT T02的第二极与低电平信号线SLL相连以被输入低电平信号VGL。TFT T03的第一极与第一电压信号线SL1相连以被输入第一电压V1，TFT T03的第二极与第二电压信号线SL2相连以被输入第二电压V2。例如，第一电压信号线SL1为恒定的电压信号线，第二电压信号线SL2为恒定的电压信号线。
如图19所示，TFT T01的栅极和TFT T03的栅极与发光信号GOA单元304相连，TFT T02的栅极与复位信号GOA单元303相连，TFT T04的栅极与TFT T01的第二极(TFT T02的第一极)相连。
例如，当发光信号EM输出为低，在发光阶段，第一初始化信号Vinit1的输出电压为第一电压V1(较高电压)，当发光信号EM输出为高，复位信号RESET输出为低，为使得第一初始化信号Vinit1的较低电压输出，XEMS_INV为复位信号GOA单元303输出的自举电压，此时第一初始化信号Vinit1的输出电压为第二电压V2。例如，第二电压V2为-3V左右，第一电压V1的范围为1V至3V，但不限于此。例如，XEMS_INV为XEMS的反向信号。
例如，在发光阶段t3，TFT T01和TFT T03开启，TFT T02和TFT T04关闭，在除了发光阶段的其他阶段，TFT T01和TFT T03关闭，TFT T02和TFT T04开启。除了发光阶段的其他阶段可以为第一复位阶段t1，除了发光阶段的其他阶段可以为第一复位阶段t1和数据写入及阈值补偿和第二复位阶段t2。
例如，本公开的实施例的像素电路中的晶体管均为薄膜晶体管。例如，第一导电图案层LY1、第二导电图案层LY2、第三导电图案层LY3、第四导电图案层LY4均采用金属材料制作。例如，第一导电图案层LY1和第二导电图案层LY2采用镍、铝等金属材料形成，但不限于此。例如，第三导电图案层LY3和第四导电图案层LY4采用钛、铝等材料形成，但不限于此。例如，第三导电图案层LY3和第四导电图案层LY4分别为Ti/AL/Ti三个子层形成的结构，但不限于此。例如，衬底基板可以采用玻璃基板或聚酰亚胺基板，但不限于此，可根据需要进行选择。例如，第一栅绝缘层GI1、第二栅 绝缘层GI2、层间绝缘层ILD、钝化层PVX、第一平坦化层PLN1、第二平坦化层PLN2、像素定义层PDL、隔垫物PS均采用绝缘材料制作。发光元件的第一极201和第二极202的材料可根据需要进行选取。一些实施例中，第一极201可采用透明导电金属氧化物和银至少之一，但不限于此。例如，透明导电金属氧化物包括氧化铟锡(ITO)，但不限于此。例如，第一极201可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中，第二极202可以为低功函的金属，可采用镁和银至少之一，但不限于此。
本公开至少一实施例还提供一种显示装置，包括上述任一项显示面板。例如，显示装置包括OLED或包括OLED的低帧频驱动的产品。例如，显示装置包括含有上述显示面板的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
本公开至少一实施例还提供一种显示面板的驱动方法，包括：在复位阶段，对驱动晶体管的栅极进行复位，并对发光元件的第一极进行复位；对所述驱动晶体管的所述栅极进行复位包括：设置复位控制信号为开启电压，开启第一复位晶体管，向所述第一复位晶体管的第一极输入第一电压以通过所述第一复位晶体管将所述第一电压传输到所述驱动晶体管的所述栅极，所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连，所述第一复位晶体管的栅极与复位控制信号线相连，所述复位控制信号线被配置为输入所述复位控制信号；在发光阶段，驱动所述发光元件发光，并向所述第一复位晶体管的所述第一极输入第二电压，所述第二电压大于所述第一电压。
例如，对所述发光元件的所述第一极进行复位包括：通过第二复位晶体管将初始化信号传输到发光元件的第一极。例如，所述初始化信号为直流信号。
以上以7T1C的像素电路为例进行说明，本公开的实施例包括但不限于此。需要说明的是，本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如，在另外的一些实施例中，显示基板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
在本公开的实施例中，位于同一层的元件可由同一膜层经同一构图工艺行程。例如，位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工 艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种显示面板，包括：
    发光单元，包括像素电路和发光元件，所述像素电路被配置为驱动所述发光元件，所述像素电路包括驱动晶体管、第一复位晶体管和第二复位晶体管；所述第一复位晶体管与所述驱动晶体管的栅极相连，并被配置为对所述驱动晶体管的所述栅极进行复位，所述第二复位晶体管与所述发光元件的第一极相连，并被配置为对所述发光元件的所述第一极进行复位；
    第一初始化信号线，通过所述第一复位晶体管与所述驱动晶体管的栅极相连；
    第二初始化信号线，通过所述第二复位晶体管与所述发光元件的所述第一极相连，
    其中，所述第一初始化信号线和所述第二初始化信号线彼此绝缘，并被配置为分别输入信号。
  2. 根据权利要求1所述的显示面板，其中，所述第一复位晶体管的第一极与所述第一初始化信号线相连，所述第一复位晶体管的第二极与所述驱动晶体管的所述栅极相连，所述第二复位晶体管的第一极与所述第二初始化信号线相连，所述第二复位晶体管的第二极与所述发光元件的所述第一极相连。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一初始化信号线被配置为输入交流信号，所述第一初始化信号线被配置为在对所述驱动晶体管的所述栅极进行复位的阶段向所述第一复位晶体管输入第一电压，并被配置为在所述发光元件的发光阶段向所述第一复位晶体管输入第二电压，所述第二电压大于所述第一电压。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述第二初始化信号线被配置为输入直流信号。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述第一初始化信号线与所述第二初始化信号线大致沿相同的方向延伸。
  6. 根据权利要求1-5任一项所述的显示面板，其中，所述第一初始化信号线和所述第二初始化信号线均沿第一方向延伸，所述发光单元包括在第二方向上相邻的第一发光单元和第二发光单元，所述第二方向与所述第一方向相交；
    在所述第二方向上，所述第二发光单元的所述第二初始化信号线和所述第一发光单元的所述第一初始化信号线位于所述第一发光单元的所述驱动晶体管和所述第二发光单元的所述驱动晶体管之间；
    所述第二发光单元的所述第二初始化信号线比所述第一发光单元的所述第一初始化信号线更靠近所述第一发光单元的所述驱动晶体管。
  7. 根据权利要求6所述的显示面板，还包括衬底基板，其中，
    所述第一复位晶体管为双栅晶体管，所述第一复位晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过第一导电连接部相连，所述第一发光单元的所述第一复位晶体管的所述第一导电连接部在所述衬底基板上的正投影至少部分落入所述第二发光单元的所述第二初始化信号线在所述衬底基板上的正投影内。
  8. 根据权利要求7所述的显示面板，其中，所述第一发光单元的所述第一复位晶体管的所述第一导电连接部和所述第二发光单元的所述第二初始化信号线构成稳定电容。
  9. 根据权利要求7或8所述的显示面板，其中，所述第一复位晶体管的第一栅极和第二栅极在所述衬底基板上的正投影与所述第一复位晶体管的所述第一沟道和所述第二沟道在所述衬底基板上的正投影分别交叠。
  10. 根据权利要求7-9任一项所述的显示面板，还包括复位控制信号线，其中，所述第一复位晶体管的第一栅极和第二栅极分别为所述复位控制信号线的一部分。
  11. 根据权利要求7-10任一项所述的显示面板，还包括第一电源线，其中，所述第一电源线被配置为向所述像素电路提供第一电压信号；
    所述像素电路还包括存储电容，所述存储电容的第一极与所述驱动晶体管的栅极相连，所述存储电容的第二极与所述第一电源线相连；
    所述第一电源线在所述衬底基板上的正投影与所述第一导电连接部在所述衬底基板上的正投影至少部分交叠。
  12. 根据权利要求11所述的显示面板，其中，所述第一电源线与所述第一导电连接部构成稳定电容。
  13. 根据权利要求10-12任一项所述的显示面板，其中，所述第一导电连接部在所述衬底基板上的正投影落入所述第一电源线在所述衬底基板上的正投影内。
  14. 根据权利要求13所述的显示面板，其中，所述驱动晶体管的栅极通过连接线与所述第一复位晶体管的第二极相连，所述第一电源线在所述衬底基板上的正投影与所述连接线在所述衬底基板上的正投影至少部分交叠。
  15. 根据权利要求14所述的显示面板，其中，所述连接线在所述衬底基板上的正投影落入所述第一电源线在所述衬底基板上的正投影内。
  16. 根据权利要求11-15任一项所述的显示面板，其中，所述连接线与所述第一电源线构成稳定电容。
  17. 根据权利要求14-16任一项所述的显示面板，其中，所述第一电源线呈网格状，包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一部分和所述第二部分交叉。
  18. 根据权利要求11-17任一项所述的显示面板，还包括电源连接线，其中，所述第一电源线通过所述电源连接线与所述存储电容的第二极相连。
  19. 根据权利要求11-18任一项所述的显示面板，还包括连接电极，其中，所述连接电极的一端与所述第一初始化信号线电连接，所述连接电极的另一端通过与所述第一复位晶体管的第一极相连，提供多个连接电极和多个电源连接线，所述多个连接电极和所述多个电源连接线在第二方向上交替排列。
  20. 根据权利要求11-19任一项所述的显示面板，还包括栅线和数据线，其中，所述栅线被配置为向所述像素电路输入扫描信号，所述数据线被配置为向所述像素电路输入数据信号，
    所述像素电路还包括数据写入晶体管，所述数据写入晶体管的栅极与所述栅线相连，所述数据写入晶体管的第一极与所述数据线相连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
  21. 根据权利要求20所述的显示面板，其中，所述像素电路还包括阈值补偿晶体管，所述阈值补偿晶体管的栅极与所述栅线相连，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连，所述阈值补偿晶体管的第二极与驱动晶体管的栅极相连。
  22. 根据权利要求17所述的显示面板，其中，所述阈值补偿晶体管为双栅晶体管，所述阈值补偿晶体管包括第一沟道和第二沟道，所述阈值补偿晶体管的所述第一沟道和所述第二沟道通过第二导电连接部相连，所述第二导电连接部在所述衬底基板上的正投影与所述第一电源线在所述衬底基板上的正投影至少部分交叠。
  23. 根据权利要求22所述的显示面板，其中，所述第二导电连接部在所述衬底基板上的正投影完全落入所述第一电源线在所述衬底基板上的正投影内。
  24. 根据权利要求22或23所述的显示面板，其中，所述第二导电连接部与所述第一电源线构成稳定电容。
  25. 根据权利要求2-24任一项所述的显示面板，还包括挡块，其中，所述挡块与所述第一电源线相连，所述第二导电连接部在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠，所述挡块与所述第二导电连接部构成稳定电容。
  26. 根据权利要求11-25任一项所述的显示面板，还包括发光控制信号线，所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管，
    所述第一发光控制晶体管的栅极与所述发光控制信号线相连，所述第一发光控制晶体管的第一极与所述第一电源线相连，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连；
    所述第二发光控制晶体管的栅极与所述发光控制信号线相连，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连，所述第二发光控制晶体管的第二极与所述发光元件的所述第一极相连。
  27. 根据权利要求13-26任一项所述的显示面板，还包括第二电源端，其中，所述第二电源端与所述发光元件的第二极相连。
  28. 一种显示装置，包括根据权利要求1-27任一项所述的显示面板。
  29. 一种显示面板的驱动方法，包括：
    在复位阶段，对驱动晶体管的栅极进行复位，并对发光元件的第一极进行复位；对所述驱动晶体管的所述栅极进行复位包括：设置复位控制信号为开启电压，开启第一复位晶体管，向所述第一复位晶体管的第一极输入第一电压以通过所述第一复位晶体管将所述第一电压传输到所述驱动晶体管的所述栅极，所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连，所述第一复位晶体管的栅极与复位控制信号线相连，所述复位控制信号线被配置为输入所述复位控制信号；
    在发光阶段，驱动所述发光元件发光，并向所述第一复位晶体管的所述第一极输入第二电压，所述第二电压大于所述第一电压。
  30. 根据权利要求29所述的显示面板的驱动方法，其中，对所述发光元件的所述第一极进行复位包括：通过第二复位晶体管将初始化信号传输到发光元件的第一极。
  31. 根据权利要求30所述的显示面板的驱动方法，其中，所述初始化信号为直流信号。
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