WO2021189334A9 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021189334A9
WO2021189334A9 PCT/CN2020/081234 CN2020081234W WO2021189334A9 WO 2021189334 A9 WO2021189334 A9 WO 2021189334A9 CN 2020081234 W CN2020081234 W CN 2020081234W WO 2021189334 A9 WO2021189334 A9 WO 2021189334A9
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WO
WIPO (PCT)
Prior art keywords
light
frame area
line
display panel
lines
Prior art date
Application number
PCT/CN2020/081234
Other languages
English (en)
French (fr)
Other versions
WO2021189334A1 (zh
Inventor
周洋
黄耀
张祎杨
张昊
韩林宏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/081234 priority Critical patent/WO2021189334A1/zh
Priority to JP2021577627A priority patent/JP7507800B2/ja
Priority to CN202080000369.6A priority patent/CN114008702B/zh
Priority to EP20927480.2A priority patent/EP4002342A4/en
Priority to US17/628,702 priority patent/US20220271113A1/en
Publication of WO2021189334A1 publication Critical patent/WO2021189334A1/zh
Publication of WO2021189334A9 publication Critical patent/WO2021189334A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly

Definitions

  • Embodiments of the present disclosure relate to a display panel and a display device.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel, including: a light-transmitting area; a display area, disposed around the light-transmitting area or on one side of the light-transmitting area; a frame area, located in the light-transmitting area and between the display areas; a plurality of data lines, located on the base substrate, including a plurality of frame area data lines located in the frame area and a plurality of display area data lines located in the display area, the multiple The frame area data lines are respectively connected to the plurality of display area data lines; and a plurality of gate lines located on the base substrate, including a plurality of frame area gate lines located in the frame area and a plurality of gate lines located in the display area a plurality of display area grid lines in the area, the plurality of border area grid lines and the plurality of display area grid lines are respectively connected; the border area grid lines include a first part, and the border area data lines include a first part, The extension direction of the first part of the frame area gate line is the same as
  • a width of a portion of the border area gate line overlapping with the border area data line is less than or equal to a width of the border area data line.
  • a length of a portion of the frame area gate line overlapping with the frame area data line in its extending direction is smaller than a length of the first portion of the frame area gate line .
  • a portion of the border area gate line overlapping the border area data line has a length in the extending direction greater than the width of the border area data line.
  • the first portion of the bezel area gate line includes a curved portion
  • the first portion of the bezel area data line includes a curved portion
  • a length of a portion of the frame area grid line overlapping the frame area data line gradually increase.
  • adjacent border area data lines are located at different layers.
  • the adjacent border area data lines include a first border area data line and a second border area data line, and the first border area data line is larger than the second border area data line.
  • the area data lines are closer to the base substrate, and a first insulating layer is provided between the first frame area data lines and the second frame area data lines.
  • the first frame area data lines and the display area data lines connected thereto are of an integrated structure, and the second frame area data lines and the display area data lines connected thereto pass through the The via holes of the first insulating layer are connected.
  • the first insulating layer includes a passivation layer and a first planarization layer.
  • the display panel further includes an initialization signal line and a first conductive line, the initialization signal line is located on a side of the gate line away from the base substrate, and the first conductive line Located on the same layer as the second frame area data line, the first wire is connected to the initialization signal line.
  • the first wires are disposed around the light-transmitting area.
  • connection position of the second frame area data line and the display area data line connected thereto is located inside the first wire.
  • the display panel further includes a second wire, the second wire is located on the same layer as the second frame area data wire, and the second wire is arranged around the first wire , the second wire and the first wire are insulated from each other.
  • the second wire has an opening at the light-transmitting region.
  • the display panel further includes a plurality of light-emitting control signal lines, the plurality of light-emitting control signal lines including a plurality of bezel area light-emitting control signal lines located in the bezel area and a plurality of bezel area light-emitting control signal lines located in the bezel area.
  • the border area light-emitting control signal lines include a first part
  • the extension direction of the first portion of the frame area light-emitting control signal line is the same as the extension direction of the first portion of the frame area data line
  • the first portion of the frame area light-emitting control signal line is the same as the multiple frame area light-emitting control signal line.
  • the first portion of one of the strip border area data lines overlaps in a direction perpendicular to the base substrate.
  • one of the frame area gate line and the frame area light-emitting control signal line overlaps the first frame area data line, the frame area gate line and the frame area
  • the other one of the area light-emitting control signal lines overlaps with the second frame area data line.
  • the frame area gate lines overlap with the first frame area data lines
  • the frame area light-emitting control signal lines overlap with the second frame area data lines
  • the frame area light-emitting control signal lines overlap with the second frame area data lines.
  • the thickness of the insulating layer between the frame area gate lines and the first frame area data lines is smaller than the thickness of the insulating layer between the frame area light-emitting control signal lines and the second frame area data lines.
  • the number of the plurality of light-emitting control signal lines is equal to the number of the plurality of gate lines.
  • the frame area light-emitting control signal line and the display area light-emitting control signal line are located in different layers.
  • the frame area gate lines are closer to the base substrate than the frame area light-emitting control signal lines, and the frame area gate lines and the frame area light-emitting control signal lines A gate insulating layer is provided therebetween.
  • an interlayer insulating layer is provided between the light emission control signal line and the first frame area data line.
  • the display panel further includes a second planarization layer covering the second frame area data lines.
  • a material of at least one of the first frame area data line, the second frame area data line, the gate line, and the light-emitting control signal line includes metal or alloy .
  • the display panel further includes a display unit including an organic light emitting diode.
  • the display panel further includes isolation pillars, the isolation pillars are located in the frame area and are disposed around the light-transmitting area, and the isolation pillars are located in the plurality of frame areas On the side of the data line close to the light-transmitting area, the isolation column constitutes the inner boundary of the frame area.
  • the isolation column is made of a metal material.
  • the isolation column is disposed on the same layer as the first frame area data line or the second frame area data line.
  • the isolation pillar includes a first sublayer, a second sublayer, and a third sublayer, the first sublayer being closer to the liner than the second sublayer a base substrate, the second sub-layer is closer to the base substrate than the third sub-layer, and the dimension of the second sub-layer along the radial direction of the light-transmitting region is smaller than that of the first sub-layer
  • the dimension of the layer along the radial direction of the light-transmitting area, and the dimension of the second sub-layer along the radial direction of the light-transmitting area is smaller than that of the third sub-layer along the transmissive area.
  • the organic light emitting diode includes a light-emitting functional layer
  • the light-emitting functional layer includes a first portion of the isolation pillar that is remote from the light-transmitting region and located on the isolation pillar.
  • the second part of the light emitting functional layer and the second part of the light emitting functional layer are broken at the side of the isolation column.
  • the light-transmitting region includes a first light-transmitting region and a second light-transmitting region
  • the border region grid line includes a second portion
  • the second portion of the border region grid line The part is located between the first light-transmitting area and the second light-transmitting area, and the second part of the grid line in the frame area is connected to the first plate of the load capacitor, and the second plate of the load capacitor is connected to the first plate of the load capacitor.
  • the first plates of the load capacitor are arranged oppositely.
  • the second electrode plate of the load capacitor partially overlaps the second portion of the gate line in the frame area.
  • the second portion of the gate line in the frame area and the first plate of the load capacitor are integrally formed.
  • the display panel further includes a first power line configured to provide a constant voltage signal, and the second plate of the load capacitor is connected to the first power line.
  • the power cord is connected.
  • At least one embodiment of the present disclosure also provides a display device including any of the above-mentioned display panels.
  • 1 is a schematic diagram of a display panel
  • FIG. 2 is a schematic diagram of a display panel
  • FIG. 3 is a schematic diagram of a display panel
  • FIG. 4 is a schematic diagram of a display panel
  • FIG. 5 is a partial schematic diagram of a display panel
  • FIG. 6 is a schematic diagram of a signal line providing a signal for each pixel unit in a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a partial plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a plan view of the data line in FIG. 7;
  • FIG. 9 is a plan view of the grid lines and the light emission control signal lines in FIG. 7;
  • FIG. 10 is a cross-sectional view along line A-B of FIG. 7;
  • FIG. 11 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 12 is a plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a plan view of a third conductive pattern layer and a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure
  • FIG. 14 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure.
  • FIG. 15 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • 16 is a plan view of an initialization signal line and a second wire in a display panel according to an embodiment of the present disclosure
  • 17 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 18 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 19 is a partial schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 20 is a partial schematic diagram of a display panel according to an embodiment of the present disclosure.
  • 21 is a partial schematic diagram of a display panel according to an embodiment of the disclosure.
  • FIG. 22 is a schematic diagram of a display panel according to an embodiment of the disclosure.
  • FIG. 23 is a schematic diagram of a display panel according to an embodiment of the disclosure.
  • Figure 24 is a partial schematic view of Figure 23;
  • 25 is a plan view of a dummy pixel unit at the second portion of the border area grid line
  • Fig. 26 is the figure of the active layer of the dummy pixel unit in Fig. 25;
  • Fig. 27 is the pattern of the first conductive pattern layer of the dummy pixel unit in Fig. 25;
  • FIG. 28 is a diagram of the second conductive pattern layer of the dummy pixel unit in FIG. 25;
  • Fig. 29 is the figure of the insulating layer of the dummy pixel unit in Fig. 25;
  • Fig. 30 is the pattern of the third conductive pattern layer of the dummy pixel unit in Fig. 25;
  • FIG. 31 is a schematic diagram of a pixel circuit structure of a display panel according to an embodiment of the disclosure.
  • FIG. 32 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure.
  • 33 is a plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a display panel.
  • the display panel includes a light-transmitting area R1 and a display area R2 .
  • the solution of opening holes in the screen is adopted, at least part of the structure in the light-transmitting area R1 is removed, that is, the solution of opening the holes in the screen needs to sacrifice part of the display area to form the light-transmitting region.
  • the light-transmitting region R1 is circular.
  • the light-transmitting region R1 is the opening region.
  • the size of the opening area determines the number of display pixel units that are missing in the current display pixel unit row. The more the number of display pixel units is missing, the more the load of the gate line (scanning signal) is also missing, and the scanning signal needs to be compensated. more capacitance.
  • FIG. 2 is a schematic diagram of a display panel.
  • the shape of the light-transmitting region R1 of the display panel shown in FIG. 2 is different from that of the light-transmitting region R1 of the display panel shown in FIG. 1 .
  • the light-transmitting region R1 is in the shape of a racetrack.
  • the shape of the light-transmitting region R1 of the display panel provided by the embodiments of the present disclosure is not limited to the shape shown in FIG. 1 and FIG. 2 , and can be set as required.
  • the setting positions of the light-transmitting regions R1 of the display panel provided by the embodiments of the present disclosure are not limited to those shown in the figures, and can be set as required.
  • the following embodiments of the present disclosure are described by taking the shape of the light-transmitting region R1 as a circle.
  • FIG. 3 is a schematic diagram of a display panel. As shown in FIG. 3 , since holes need to be dug in the light-transmitting region R1 , the traces that should have passed through the region without digging holes need to extend along the edge of the light-transmitting region R1 to form a frame region R3 . As shown in FIG. 3 , the frame area R3 is located between the display area R2 and the light-transmitting area R1 . The display region R2 surrounds the light-transmitting region R1, and the frame region R3 surrounds the light-transmitting region R1.
  • the display region R2 may also be located on one side of the light-transmitting region R1, and the frame region R3 may be located between the display region R2 and the light-transmitting region R1.
  • FIG. 3 shows the data line 313 , the gate line 113 , and the light emission control signal line 213 .
  • the gate lines 113 are located in the first conductive pattern layer LY1
  • the light emission control signal lines 213 are located in the second conductive pattern layer LY2
  • the data lines 313 are located in the third conductive pattern layer LY3 .
  • the light emission control signal line 213 may also be located in the first conductive pattern layer LY1.
  • FIG. 3 shows a first direction X and a second direction Y.
  • the data lines 313 extend along the second direction Y
  • the gate lines 113 and the light emission control signal lines 213 both extend along the first direction X.
  • the extension direction of each signal line described here refers to the overall extension trend of the signal line, and it is not excluded that the signal line includes a portion that does not extend in this direction.
  • FIG. 3 does not show all the signal lines, and the display panel provided by the embodiments of the present disclosure may further include other signal lines.
  • the display panel provided by the embodiments of the present disclosure may further include signal lines such as power lines and initialization signal lines.
  • FIG. 4 is a schematic diagram of a display panel.
  • FIG. 4 shows the light-transmitting area R1 , the display area R2 and the frame area R3 , and the signal lines are omitted for the sake of clarity of illustration.
  • FIG. 5 is a partial schematic diagram of a display panel.
  • FIG. 5 shows a schematic diagram of the light-transmitting region R1 and its adjacent structures.
  • FIG. 5 shows four data lines 313 , two gate lines 113 and two light emission control signal lines 213 .
  • the opening in the screen not only causes the loss of the pixel circuit, but also causes the loss of lateral and vertical loading (Loading) in the opening region (transparent region R1).
  • the lack of this part of the load may cause the display difference at the boundary of the missing pixel unit, such as poor display in the horizontal range where the opening is located.
  • the display difference problem of conventional display images may not be exposed, but the display failure will occur under more stringent display conditions (such as high refresh rate).
  • a complete machine manufacturer needs to have more camera sensors in front, and needs to design a runway-type opening at the same position, there will be more load loss, and the display defect will be more exposed.
  • a plurality of signal lines are formed in the frame area, and the space occupied by the signal wires affects the size of the frame area, which is not conducive to increasing the screen ratio.
  • Each display pixel unit P1 includes a light emitting unit and a pixel circuit structure for providing driving current for the light emitting unit.
  • the light emitting unit may be an electroluminescent unit, such as an organic electroluminescent unit, such as an organic light emitting diode (OLED).
  • the display pixel unit P1 is a pixel unit that emits light normally.
  • the display pixel unit P1 is located in the display area R2.
  • FIG. 6 shows the gate line 113 , the data line 313 , the first power supply line 311 , the second power supply line 312 , the light emission control signal line 213 and the initialization signal line 210 .
  • the gate line 113 is configured to provide at least one of the scan signal SCAN or the reset signal RESET to the pixel circuit structure.
  • the gate line 113 can also be referred to as a reset control signal line.
  • the second reset control signal line 112 of the pixel unit of the current row serves as the first reset control signal line 111 of the pixel unit of the next row.
  • the light emission control signal line 213 is configured to provide the light emission control signal EM to the display pixel unit P1.
  • the data line 313 is configured to supply the data signal DATA to the pixel circuit structure 10
  • the first power supply line 311 is configured to supply the constant first voltage signal ELVDD to the pixel circuit structure 10
  • the second power supply line 312 is configured to supply the pixel circuit structure A constant second voltage signal ELVSS is provided, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 210 is configured to provide the initialization signal Vint to the pixel circuit structure.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between, but not limited to, the first voltage signal ELVDD and the second voltage signal ELVSS, for example, the initialization signal Vint may be smaller than or equal to the second voltage signal ELVSS.
  • the pixel circuit structure outputs driving current to drive the light-emitting unit to emit light under the control of scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and lighting control signal EM.
  • the gate line 113 is located in the first conductive pattern layer LY1
  • the initialization signal line 210 is located in the second conductive pattern layer LY2
  • the data line 313 and the first power supply line 311 are located in the third conductive pattern layer LY3
  • the second The power line 312 may also be located on the third conductive pattern layer LY3.
  • FIG. 7 is a partial plan view of a display panel according to an embodiment of the present disclosure.
  • the display panel includes: a light transmission region R1 , a display region R2 , a frame region R3 , a plurality of light emission control signal lines 213 , a plurality of data lines 313 and a plurality of gate lines 113 .
  • the display region R2 is disposed around the light-transmitting region R1 or located on one side of the light-transmitting region R1 .
  • the frame region R3 is located between the light-transmitting region R1 and the display region R2.
  • the number of the plurality of light emission control signal lines 213 is equal to the number of the plurality of gate lines 113 . That is, one light-emitting control signal line 213 is provided for each row of pixel units, and the light-emitting control signal is driven row by row, thereby improving the dimming and flickering problem of low gray scale.
  • the number of horizontal signal lines is equal to the number of vertical signal lines, and when the light-transmitting region R1 is circular, the frame region R3 can be circular, but not limited to this.
  • one gate line 113 overlaps with one data line 313 at a first position, and overlaps with another data line 313 at a second position.
  • one light-emitting control signal line 213 overlaps with one data line 313 at a third position, and overlaps with another data line 313 at a fourth position.
  • one data line 313 overlaps with one light emission control signal line 213 at the fifth position, and overlaps with one gate line 113 at the sixth position.
  • FIG. 8 is a plan view of the data lines in FIG. 7 . 7 and 8, a plurality of data lines 313 are located on the base substrate, including a plurality of border region data lines 313a located in the border region R3 and a plurality of display region data lines 313b located in the display region R2.
  • the area data lines 313a are connected to the plurality of display area data lines 313b, respectively.
  • Each data line 313 includes a border region data line 313a located in the border region R3 and a display region data line 313b located in the display region R2.
  • FIG. 8 also shows a plurality of display area data lines 313c, and the plurality of display area data lines 313c are respectively connected with a plurality of frame area data lines 313a.
  • each data line 313 includes a frame area located in the frame area R3
  • the display area data line 313b and the display area data line 313c are respectively arranged on both sides of the frame area data line 313a.
  • FIG. 9 is a plan view of the gate lines and the light emission control signal lines in FIG. 7 .
  • a plurality of gate lines 113 are located on the base substrate, including a plurality of frame region gate lines 113a located in the frame region R3 and a plurality of display region gate lines 113b located in the display region R2.
  • the area gate lines 113a and the plurality of display area gate lines 113b are respectively connected.
  • Each gate line 113 includes a border region gate line 113a located in the border region R3 and a display region gate line 113b located in the display region R2.
  • each grid line 113 includes a border area located in the border area R3
  • the display area gate line 113b and the display area gate line 113c are respectively disposed on both sides of the frame area gate line 113a.
  • the border area gate line 113a includes a first portion 1131
  • the border area data line 313a includes a first portion 3131
  • the extending direction of the first portion 1131 of the border area gate line 113a is the same as the first portion 3131 of the border area data line 313a.
  • the extending directions are the same, and the first portion 1131 of the frame area gate line 113a overlaps with the first portion 3131 of one of the plurality of frame area data lines 313a in a direction perpendicular to the base substrate.
  • the same direction of extension may mean that two elements have conformal portions, the conformal portions extend in the same direction, or the conformal portions extend in the same direction.
  • extending in the same direction may refer to two elements extending in the same direction at the same point.
  • the extension direction may refer to the general extension trend of the line, and if the line is not a straight line, the direction of the tangent of the line may be its extension direction.
  • the extension direction is the same includes the extension direction being exactly the same and substantially the same.
  • the direction of extension of the overlapping portion of the different elements is schematically depicted in FIG. 7 by a curve with double arrows.
  • FIG. 10 is a cross-sectional view taken along line A-B of FIG. 7 .
  • the display substrate includes a base substrate BS.
  • a barrier layer BR is provided on the base substrate BS, a first gate insulating layer GI1 is provided on the barrier layer BR, a first conductive pattern layer LY1 is provided on the first gate insulating layer GI1, and the first conductive pattern layer LY1 includes gate line 113 .
  • a second gate insulating layer GI2 is provided on the first conductive pattern layer LY1 , a second conductive pattern layer LY2 is provided on the second gate insulating layer GI2 , and the second conductive pattern layer LY2 includes a light emission control signal line 213 .
  • An interlayer insulating layer ILD is provided on the second conductive pattern layer LY2.
  • a third conductive pattern layer LY3 is disposed on the interlayer insulating layer ILD, and the third conductive pattern layer LY3 includes data lines 313 .
  • a passivation layer PVX and a first planarization layer PLN1 are provided on the third conductive pattern layer LY3.
  • Figure 10 shows the third direction Z.
  • the third direction Z is perpendicular to the first direction X.
  • the third direction Z is also perpendicular to the second direction Y.
  • the third direction Z is the direction perpendicular to the base substrate BS. 7 to 10 , the first portion 1131 of the frame area gate line 113a overlaps the first portion 3131 of one of the plurality of frame area data lines 313a in a direction perpendicular to the base substrate BS.
  • the load difference of the gate line has the greatest impact on the display panel, and its load affects the rise and fall time of the scan signal SCAN, thereby affecting the writing time of the data signal DATA and the writing time of the data signal DATA.
  • the difference directly leads to the difference between the brightness and darkness of the display panel. Therefore, the grid lines and the data lines are overlapped to form the two plates of the capacitor respectively, which compensates for the missing load of the grid lines, reduces the brightness difference of the display panel, and improves the display effect. .
  • the display difference of the panel caused by digging holes is corrected, and the display quality is improved.
  • the portion 11 of the border region gate line 113a overlapping with the border region data line 313a is a part of the first portion 1131 of the border region gate line 113a, and the border region gate line 113a and the border region data line 313a are part of the first portion 1131 of the border region gate line 113a.
  • the width of the overlapping portion 11 is smaller than or equal to the width of the frame area data line 313a.
  • the portion 31 of the border region data line 313a overlapping with the border region gate line 113a is a part of the first portion 3131 of the border region data line 313a.
  • the length of the portion 31 of the frame area data line 313a overlapping with the frame area gate line 113a in its extending direction is smaller than the length of the first portion 3131 of the frame area data line 313a.
  • the length of the element may refer to the dimension in the extending direction thereof, and the width of the element may refer to the dimension in the direction perpendicular to the extending direction thereof.
  • the length of the portion 11 of the frame area gate line 113a overlapping with the frame area data line 313a in its extending direction is smaller than the length of the first portion 1131 of the frame area gate line 113a.
  • the length of the portion 11 of the frame area gate line 113a overlapping with the frame area data line 313a in the extending direction thereof is greater than the width of the frame area data line 313a.
  • the first portion 1131 of the frame area gate line 113a includes a bent portion
  • the first portion 3131 of the frame area data line 313a includes a bent portion
  • the shapes of the curved portion of the frame area gate line 113a and the curved portion of the frame area data line 313a both include arc shapes.
  • the length of the overlapping portion of the border region gate lines 113 a and the border region data lines 313 a gradually increases.
  • the display panel further includes a plurality of light-emitting control signal lines 213 , and the plurality of light-emitting control signal lines 213 include a plurality of bezel region light-emitting control signal lines 213 a located in the bezel region R3 and a plurality of bezel region light-emitting control signal lines 213 a located in the display
  • the plurality of display area light-emitting control signal lines 213b in the area R2, the plurality of frame area light-emitting control signal lines 213a and the plurality of display area light-emitting control signal lines 213b are respectively connected, and the border area light-emitting control signal lines 213a include a first part 2131,
  • the extension direction of the first portion 2131 of the light emission control signal line 213a is the same as the extension direction of the first portion 3131 of the frame area data line 313a.
  • the first portion 3131 overlaps in a direction perpendicular to the base substrate BS. Therefore, the light-emitting control signal line and the data line are overlapped to form two polar plates of the capacitor respectively, so as to compensate for the missing load of the light-emitting control signal line and improve the display effect.
  • each light emission control signal line 213 includes a border region light emission control signal line 213a in the border region R3 and a display region light emission control signal line 213b in the display region R2.
  • the plurality of light emission control signal lines 213 further include a plurality of display region light emission control signal lines 213c located in the display region R2, a plurality of display region light emission control signal lines 213c and a plurality of border region light emission control signal lines
  • the lines 213a are connected, respectively.
  • Each light emission control signal line 213 includes a border region light emission control signal line 213a in the border region R3, a display region light emission control signal line 213b in the display region R2, and a display region light emission control signal line 213c in the display region R2.
  • the display area light-emitting control signal line 213b and the display area light-emitting control signal line 213c are respectively disposed on both sides of the frame area light-emitting control signal line 213a.
  • the length of the portion 21 of the frame area light-emitting control signal line 213a overlapping the frame area data line 313a in its extending direction is smaller than the length of the first portion 1131 of the frame area light-emitting control signal line 213a.
  • the portion 21 of the frame area light-emitting control signal line 213a overlapping the frame area data line 313a has a length in the extending direction greater than the width of the frame area data line 313a.
  • the first portion 2131 of the frame area light emission control signal line 213a includes a bent portion.
  • the shapes of the curved portion of the frame area light emission control signal line 213a and the curved portion of the frame area data line 313a both include arc shapes.
  • the length of the overlapping portion 21 of the frame area light-emitting control signal line 213a and the frame area data line 313a gradually increases from the direction away from the light-transmitting area R1 to the direction close to the light-transmitting area R1.
  • the overlapping portions 21 of the frame area light emission control signal lines 213a and the frame area data lines 313a and the portions 11 where the frame area gate lines 113a and the frame area data lines 313a overlap are alternately arranged. That is, the plurality of sections 21 and the plurality of sections 11 are alternately arranged.
  • FIG. 7 illustrates an example in which the first part 1131 of the frame area gate line 113a is a part of the circle, the first part 3131 of the frame area data line 313a is a part of the circle, and the first part 2131 of the frame area light-emitting control signal line 213a is a part of the circle , but not limited thereto, in other embodiments, the first portion 1131 of the gate line 113a in the frame area may also adopt other curved forms, and the first portion 3131 of the data line 313a in the frame area may also adopt other bending forms, and the frame area The first portion 2131 of the light-emitting control signal line 213a may also adopt other curved forms.
  • the adjacent data lines 313 are located in the same layer, that is, the adjacent data lines 313 are located in the third conductive pattern layer LY3, but it is not limited thereto.
  • the adjacent border area data lines 313a shown in FIG. 7 and FIG. 10 may also be located in different layers.
  • the adjacent frame area data lines 313a are located on different layers, thereby reducing the space occupied by the signal lines in the frame area around the light-transmitting area, and achieving a narrow frame and a higher screen ratio.
  • the adjacent border area data lines 313a include a first border area data line 313a1 and a second border area data line 313a2, and the first border area data line 313a1 is closer to the second border area data line 313a2
  • an insulating layer is provided between the first frame area data lines 313a1 and the second frame area data lines 313a2.
  • the insulating layer includes a passivation layer PVX and a first planarization layer PLN1.
  • the light emission control signal line 213 may be located in the second conductive pattern layer LY2, but is not limited thereto.
  • the light-emitting control signal lines 213 may be formed in sections.
  • the light-emitting control signal lines 213a in the frame area are located in the second conductive pattern layer LY2, and the light-emitting control signal lines 213 except for the frame area light-emitting control signal lines 213a are located in the second conductive pattern layer LY2.
  • a part is located in the first conductive pattern layer LY1.
  • the frame area light emission control signal line 213a is located in the second conductive pattern layer LY2.
  • the light-emitting control signal lines 213 near the light-transmitting region R1 are arranged in segments, and the light-emitting control signal lines 213 at other positions may all be located in the first conductive pattern layer LY1.
  • portions of the light emission control signal lines 213 located in different layers are connected through via holes penetrating the insulating layers therebetween.
  • FIG. 12 is a plan view of a display panel according to an embodiment of the disclosure.
  • FIG. 12 shows the first frame area data line 313a1, the second frame area data line 313a2, the frame area light emission control signal line 213a, and the frame area gate line 113a.
  • the first portion 3131 of the first frame area data line 313a1 overlaps with the first portion 1131 of the frame area gate line 113a in a direction perpendicular to the base substrate BS. Because the sum of the thicknesses of the second gate insulating layer GI2 and the interlayer insulating layer ILD between the first portion 3131 of the data line 313a1 in the first frame region and the first portion 1131 of the gate line 113a in the frame region is relatively small, a large The capacitance between the gate lines and the data lines in the border area is increased, the load loss of the gate lines in the border area is reduced, the load of the gate lines in the border area is increased, and the display effect is improved. Generally speaking, the influence of the load loss of the gate line on the display effect is greater than the influence of the load loss of the light emitting control signal line on the display effect.
  • the first portion 3131 of the second frame area data line 313a2 and the first portion 2131 of the frame area light emission control signal line 213a overlap in a direction perpendicular to the base substrate BS. Therefore, the load loss of the light-emitting control signal lines in the frame area is reduced, the load of the light-emitting control signal lines in the frame area is increased, the display effect is improved, the space occupied by the signal lines in the frame area around the light-transmitting area is reduced, and a narrow frame and a more compact frame are realized.
  • High screen-to-body ratio For example, as shown in FIG. 11 , the thickness of the first planarization layer PLN1 is greater than the sum of the thicknesses of the second gate insulating layer GI2 and the interlayer insulating layer ILD.
  • the first frame area data lines 313a1 are located in the third conductive pattern layer LY3, and the second frame area data lines 313a2 are located in the fourth conductive pattern layer LY4.
  • An insulating layer is disposed between the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4, and the insulating layer includes a passivation layer PVX and a first planarization layer PLN1.
  • the frame area gate line 113a is located in the first conductive pattern layer LY1, the frame area light emission control signal line 213a is located in the second conductive pattern layer LY2, and a second gate insulation is provided between the first conductive pattern layer LY1 and the second conductive pattern layer LY2 Layer GI2.
  • An interlayer insulating layer ILD is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3.
  • a barrier layer BR and a first gate insulating layer GI1 are provided between the base substrate BS and the first conductive pattern layer LY1.
  • the first gate insulating layer GI1 is closer to the base substrate BS than the barrier layer BR.
  • a second planarization layer PLN2 is provided on the side of the fourth conductive pattern layer LY4 away from the base substrate BS.
  • the multiple elements are located in the same layer means that the multiple elements are formed from the same film layer by the same patterning process.
  • the elements located in the first conductive pattern layer LY1 are formed by the same patterning process
  • the elements located in the second conductive pattern layer LY2 are formed by the same patterning process
  • the elements located in the third conductive pattern layer LY3 are formed by the same patterning process.
  • the same film layer is formed by the same patterning process
  • the elements located in the fourth conductive pattern layer LY4 are formed by the same film layer and the same patterning process.
  • 11 and 12 also show the portion 11 of the frame area gate line 113a overlapping the frame area data line 313a, the portion 21 of the frame area light emission control signal line 213a overlapping the frame area data line 313a, and the frame area data line 313a
  • the first portion 3131 of the first frame area data line 313a1 partially overlaps with the first portion 1131 of the frame area gate line 113a in the direction perpendicular to the base substrate BS, however, in other embodiments , in order to obtain more overlapping area and increase the value of the compensation capacitor, the orthographic projection of the first part 3131 of the first frame area data line 313a1 on the base substrate BS completely covers the first part 1131 of the frame area gate line 113a on the base substrate Orthographic projection on BS.
  • the orthographic projection of the first portion 3131 of the frame area data line 313a on the base substrate BS completely covers the orthographic projection of the first portion 1131 of the frame area gate line 113a on the base substrate BS.
  • the data lines covering the first portion 1131 of the gate lines 113a in the border region may be disposed at a set layer as required.
  • the first portion 3131 of the second frame area data line 313a2 and the first portion 2131 of the frame area light emission control signal line 213a partially overlap in the direction perpendicular to the base substrate BS, however, in other implementations
  • the orthographic projection of the first portion 3131 of the data line 313a2 in the second frame area on the base substrate BS covers the first portion 2131 of the light-emitting control signal line 213a in the frame area. Orthographic projection on the base substrate BS.
  • the orthographic projection of the first portion 3131 of the frame area data line 313a on the base substrate BS covers the orthographic projection of the first portion 2131 of the frame area light emission control signal line 213a on the base substrate BS.
  • the data lines covering the first part 2131 of the light-emitting control signal lines 213a in the frame area can be arranged in a set layer as required.
  • FIG. 13 is a plan view of a third conductive pattern layer and a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • the second frame area data line 313a2 and the display area data line 313b connected thereto are connected at the connection position CN, and the first frame area data line 313a and the display area data line 313b connected thereto are integrally formed.
  • the fourth conductive pattern layer LY4 includes a first wire 321 , a second frame area data wire 313 a 2 and a second wire 322 .
  • the second wire 322 may be in a grid shape, but is not limited thereto.
  • the first wire 321 is disconnected at the light-transmitting region R1 , that is, the first wire 321 is arranged around the light-transmitting region R1 and has an opening OPN at the light-transmitting region.
  • FIG. 15 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • FIG. 15 may be a cross-sectional view of a part of the structure in the dotted box B1 in FIG. 13 .
  • the second frame area data line 313a2 and one display area data line 313b are connected through a via hole V1 penetrating the first planarization layer PLN1 and the passivation layer PVX.
  • the second conductive pattern layer LY2 includes the initialization signal line 210 , and the first conductive line 321 passes through the via V2 passing through the first planarization layer PLN1 , the passivation layer PVX and the interlayer insulating layer ILD and the initialization signal line 210 connected, the initialization signal line 210 is connected in parallel with the first wire 321 to reduce the resistance of the signal line.
  • the third conductive pattern layer LY3 includes a first power line 311 , and the second wire 322 is connected to the first power line 311 through a via V3 penetrating the first planarization layer PLN1 and the passivation layer PVX.
  • the first frame area data line 313a1 and the display area data line 313b connected to it have an integrated structure, and the second frame area data line 313a2 and the display area data line 313b connected thereto pass through via holes V1 is connected.
  • the initialization signal line 210 is located on the side of the gate line 113 away from the base substrate BS, the first conductive line 321 and the second frame area data line 313a2 are located on the same layer, and the first conductive line 321 and the initialization signal line are located on the same layer. 210 is connected through via V2.
  • FIG. 16 is a plan view of an initialization signal line and a second wire in a display panel according to an embodiment of the present disclosure.
  • the first wires 321 are arranged around the light-transmitting region R1 and constitute the outer boundary of the frame region R3 .
  • the first wire 321 in FIG. 16 is shown as a circle, but the shape of the first wire 321 is not limited to this, and can be set as required.
  • the first wire 321 forms a closed structure, which is a ring structure, but is not limited thereto.
  • connection positions of the second frame area data lines 313 a 2 and the display area data lines 313 b connected thereto are located inside the first wires 321 .
  • the inner side of the first conducting wire 321 refers to being located within the range encircled by the first conducting wire 321 .
  • the second wires 322 are located on the same layer as the second frame area data wires 313 a 2 , the second wires 322 are arranged around the first wires 321 , and the second wires 322 and the first wires 321 are insulated from each other .
  • the first data line DL1 is located in the third conductive pattern layer LY3
  • the second data line DL2 is located in the third conductive pattern layer LY3
  • the second frame area data line 313a2 is located in the fourth conductive pattern layer LY4, and the other part is located in the third conductive pattern layer LY3 for illustration, but not limited to this.
  • the adjacent first data line DL1 and the second data line DL2 may be located in the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4, respectively.
  • the second wires 322 may extend along the second direction Y in the display area.
  • FIG. 15 take the frame area gate line 113a overlapping the first frame area data line 313a1 and the frame area light-emitting control signal line 213a overlapping the second frame area data line 313a2 as an example, but not limited thereto. In other embodiments, other arrangements may also be employed.
  • FIG. 17 is a cross-sectional view of a display panel according to an embodiment of the disclosure. As shown in FIG. 17 , the frame area gate line 113a overlaps with the second frame area data line 313a2, and the frame area light emission control signal line 213a overlaps with the first frame area data line 313a1.
  • one of the frame area gate line 113a and the frame area light emission control signal line 213a overlaps with the first frame area data line 313a1, and the other of the frame area gate line 113a and the frame area light emission control signal line 213a One overlaps with the second frame area data line 313a2.
  • the gate line 113 is closer to the base substrate BS than the light emission control signal line 213 , and the second gate insulating layer GI2 is provided between the gate line 113 and the light emission control signal line 213 . That is, as shown in FIG. 17, the frame area gate line 113a is closer to the base substrate BS than the frame area light emission control signal line 213a, and a second gate insulation is provided between the frame area gate line 113a and the frame area light emission control signal line 213a Layer GI2.
  • an interlayer insulating layer ILD is provided between the light emission control signal line 213 and the first frame region data line 313a1.
  • the display panel further includes a second planarization layer PLN2, and the second planarization layer PLN2 covers the second frame area data line 313a2.
  • the material of at least one of the first frame area data line 313a1, the second frame area data line 313a2, the gate line 113, and the light emission control signal line 213 includes metal or alloy.
  • FIG. 18 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
  • the display panel shown in FIG. 18 is a structure within a display region R2 of the display panel, that is, a structure of a normal light-emitting region.
  • the display panel includes a base substrate BS, a barrier layer BR is provided on the base substrate BS, an active layer ATL is provided on the barrier layer BR, and the active layer ATL includes a source region and a drain electrode.
  • the source region or drain region of the active layer ATL is connected to the connecting electrode CNE1, and the connecting electrode CNE1 passes through the interlayer insulating layer ILD, the second gate insulating layer GI2 and the via hole V4 of the first gate insulating layer GI1 are connected to the active layer ATL.
  • connection electrode CNE1 is located in the third conductive pattern layer LY3, the side of the third conductive pattern layer LY3 away from the base substrate BS is provided with a passivation layer PVX and a first planarization layer PLN1, and the connection electrode CNE2 is located in the fourth conductive pattern layer LY4 , the connection electrode CNE2 is connected to the connection electrode CNE1 through the via hole V5 penetrating the passivation layer PVX and the first planarization layer PLN1.
  • the display panel further includes a light-emitting unit EMU, the light-emitting unit EMU includes an anode ANE, a light-emitting functional layer EML, and a cathode CTE, the anode ANE is disposed on the fourth conductive pattern layer LY4, and the anode ANE penetrates through the second planarization layer.
  • the via hole V6 of PLN2 is connected to the connection electrode CNE2.
  • the display panel further includes an encapsulation layer CPS, and the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers
  • the second encapsulation layer CPS2 is an organic material layer.
  • the display panel further includes a pixel definition layer PDL and a spacer PS.
  • the pixel definition layer PDL includes an opening OPN, the opening OPN is configured to define a light exit area of the display pixel unit, and the spacer PS is configured to support the fine metal mask when the light emitting functional layer EML is formed.
  • the light emitting unit EMU includes an organic light emitting diode.
  • the light-emitting functional layer EML is located between the cathode CTE and the anode ANE.
  • the light-emitting functional layer EML includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.
  • one of the anode and the cathode of the light emitting unit EMU is electrically connected to a driving transistor configured to provide a driving current to the light emitting unit EMU for driving the light emitting unit EMU to emit light.
  • FIG. 19 is a partial schematic diagram of a display panel according to an embodiment of the disclosure.
  • the display panel further includes isolation pillars 34 .
  • the isolation pillars 34 are located in the frame region R3 and are disposed around the light-transmitting region R1 .
  • the isolation pillars 34 are located near the light-transmitting region R1 of the plurality of frame region data lines 313 a
  • the isolation pillars 34 constitute the inner boundary of the frame region R3.
  • the isolation column 34 is made of metal material.
  • the isolation pillars 34 are disposed on the same layer as the first frame area data line 313a1 or the second frame area data line 313a2. That is, the isolation pillars 34 are located in the third conductive pattern layer LY3 or in the fourth conductive pattern layer LY4.
  • FIG. 20 is a partial schematic diagram of a display panel according to an embodiment of the disclosure.
  • the isolation pillar 34 includes a first sublayer 341 , a second sublayer 342 and a third sublayer 343 .
  • the first sublayer 341 is closer to the base substrate than the second sublayer 342
  • the second sublayer 342 The size of the second sub-layer 342 along the radial direction of the light-transmitting region R1 is smaller than the size of the first sub-layer 341 along the radial direction of the light-transmitting region R1, being closer to the base substrate than the third sub-layer 343,
  • the size of the second sub-layer 342 along the radial direction of the light-transmitting region R1 is smaller than the size of the third sub-layer 343 along the radial direction of the light-transmitting region R1 .
  • the materials of the first sub-layer 341 and the third sub-layer 343 both include Ti
  • the material of the second sub-layer 342 includes Al
  • the organic light emitting diode includes a light emitting functional layer EML1
  • the light emitting functional layer EML1 includes a first part EML11 located on the isolation column 34 close to the light-transmitting region R1 and a second part EML12 located on the isolation column 34, and the light emitting function
  • the first part EML11 of the layer EML1 and the second part EML12 of the light emitting functional layer are broken at the sides of the isolation pillar 34 .
  • the light-emitting functional layer EML1 may be a light-emitting functional layer provided in the whole layer, but is not limited thereto.
  • the light-emitting functional layer EML1 can be fabricated by using an open mask, but is not limited thereto.
  • the light-emitting functional layer EML1 Due to the retracted setting of the second sublayer 342 in the isolation column 34, when the light-emitting functional layer EML1 is formed on the isolation column 34, the light-emitting functional layer EML1 is broken, thereby preventing the external environment such as water and oxygen from eroding the light-emitting functional layer EML1.
  • the light emitting function layer EML1 is located in the display region R2 from being eroded, the display effect is prevented from being affected.
  • the light-emitting functional layer EML1 further includes a third portion EML13 located far from the light-transmitting region R1 of the isolation pillar 34 .
  • the display panel further includes a first encapsulation layer CPS1 , a second encapsulation layer CPS2 and a third encapsulation layer CPS3 .
  • the first encapsulation layer CPS1 includes a first portion CPS11 located near the light-transmitting region R1 of the isolation pillar 34 and a second portion CPS12 located on the isolation pillar 34 .
  • the material selection of the first encapsulation layer CPS1, the second encapsulation layer CPS2 and the third encapsulation layer CPS3 can be as described above.
  • the first encapsulation layer CPS1 further includes a third portion CPS13 located away from the light-transmitting region R1 of the isolation pillar 34 .
  • a second encapsulation layer CPS2 is provided between the first part EML11 of the light emitting functional layer EML1 and the second part EML12 of the light emitting functional layer, the third part EML13 of the light emitting functional layer EML1 and the third part EML13 of the light emitting functional layer
  • a second encapsulation layer CPS2 is disposed between the two parts of the EML 12 .
  • FIG. 20 also shows element 115 and element 215 .
  • the element 115 is located in the first conductive pattern layer LY1, and the element 215 is located in the second conductive pattern layer LY2.
  • FIG. 21 is a partial schematic diagram of a display panel according to an embodiment of the disclosure. Compared with FIG. 19 , the display panel shown in FIG. 21 also shows the first wires 321 . As shown in FIG. 21 , the isolation pillars 34 define the inner boundary of the frame region R3 , and the first wires 321 define the outer boundary of the frame region R3 .
  • FIG. 22 is a schematic diagram of a display panel according to an embodiment of the disclosure.
  • the light-transmitting region R1 of the display panel DPN is a hole-drilling region.
  • a sensor 50 is provided in the hole-drilled area.
  • the sensor 50 may be partially arranged in the hole-drilling area, or may be entirely arranged in the hole-drilling area, which is not limited.
  • the sensors include, but are not limited to, cameras.
  • FIG. 23 is a schematic diagram of a display panel according to an embodiment of the disclosure.
  • the light-transmitting region R1 includes a first light-transmitting region R1 and a second light-transmitting region R12 .
  • the first light-transmitting region R1 and the second light-transmitting region R12 are both digging regions. Between the first light-transmitting region R1 and the second light-transmitting region R12 is also a frame region R3.
  • FIG. 24 is a partial schematic view of FIG. 23 .
  • the frame region grid line 113a includes a second portion 1132 located between the first light-transmitting region R1 and the second light-transmitting region R12.
  • the second portion 1132 of the gate line 113a in the border region is provided with dummy pixel units to further increase the load of the gate line, reduce the load loss of the gate line, and reduce or avoid the lateral display (mura) defect.
  • 23 and 24 show a dummy area RD
  • FIG. 24 shows a plurality of dummy pixel units P0 located in the dummy area RD. It should be noted that, the number of the dummy pixel units P0 is not limited to that shown in the figure, and can be set as required.
  • FIG. 25 is a plan view of a dummy pixel unit at a second portion of a border area gate line.
  • the second part 1132 of the gate line 113a in the frame area is connected to the first plate C01 of the load capacitor C0, the second plate C02 of the load capacitor C0 is arranged opposite to the first plate C01, and the load capacitance C0 can greatly improve the gate line
  • the load is equivalent to forming a capacitance larger than the storage capacitance C1 (described later) of the display pixel unit of the display area by the gate line and the second plate C02.
  • the gate line of a dummy pixel unit P0 (scanning signal
  • the load of the SCAN) may be 10 to 20 times the load in the case where the load capacitance C0 is not provided.
  • the overlapping area of the load capacitor C0 of the dummy pixel unit can be designed to the size of the capacitor to be compensated.
  • This design utilizes the original space for placing the dummy pixel unit to effectively compensate the capacitance of the gate line near the hole, and solves the problem of poor lateral display (mura) at the hole.
  • the second portion 1132 of the gate line 113a in the frame region is integrally formed with the first plate C01 of the load capacitor C0, and can be formed by the same film layer using the same patterning process, and both can be located in the first conductive pattern layer LY1.
  • the second portion 1132 of the gate line 113a in the frame region is integrally formed with the first plate C01 of the load capacitor C0.
  • the second plate C02 of the load capacitor C0 is connected to the first power line 311, and the first power line 311 is configured to provide a constant voltage signal.
  • the second plate C02 of the load capacitor C0 partially overlaps the second portion 1132 of the gate line 113 a in the frame region.
  • the light emission control signal line 110 is located in the first conductive pattern layer LY1, but it is not limited thereto. In other embodiments, the light emission control signal line 110 may also be located in the second conductive pattern layer LY2.
  • FIG. 26 is a diagram of the active layer of the dummy pixel unit in FIG. 25 .
  • FIG. 27 is a pattern of the first conductive pattern layer of the dummy pixel unit in FIG. 25 .
  • the second portion 1132 of the gate line 113 is integrally formed with the first plate C01 of the load capacitor C0.
  • FIG. 28 is a pattern of the second conductive pattern layer of the dummy pixel unit in FIG. 25 .
  • the second conductive pattern layer LY2 includes the second plate C02 of the load capacitor C0.
  • the second plate C02 of the load capacitor C0 has an opening at its middle position.
  • FIG. 29 is a diagram of the insulating layer of the dummy pixel cell of FIG. 25, showing via holes penetrating through the insulating layer.
  • the insulating layer includes at least one of a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer.
  • FIG. 30 is a pattern of the third conductive pattern layer of the dummy pixel unit in FIG. 25 .
  • the third conductive pattern layer LY3 includes a first connection electrode 31 a , a second connection electrode 31 b , a third connection electrode 31 c , a fourth connection electrode 31 d , a data line 313 , and a first power supply line 311 .
  • the second connection electrode 31b is connected to the second plate C02 of the load capacitor C0 through a via hole, but it is not limited thereto.
  • FIG. 31 is a schematic diagram of a pixel circuit structure of a display panel according to an embodiment of the disclosure.
  • FIG. 32 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure.
  • 33 is a plan view of a display substrate provided by an embodiment of the present disclosure. Please refer to FIG. 31 and FIG. 6 together.
  • the display panel 100 includes a plurality of display pixel units P1 arranged in a matrix. voltage signal line.
  • the light emitting element 20 is an organic light emitting diode (OLED), and the light emitting element 20 emits red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit structure 10 .
  • the voltage signal line may be one or a plurality of lines.
  • the voltage signal line includes a first power line 311, a second power line 312, a lighting control signal line 110, a first initialization signal line 211, a second initialization signal line 212, and a first reset control signal At least one of the line 111 and the second reset control signal line 112 and the like.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit structure 10 .
  • the data line 313 is configured to provide a data signal DATA to the pixel circuit structure 10 .
  • one pixel includes a plurality of pixel units.
  • One pixel may include a plurality of pixel units that emit light of different colors.
  • one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
  • the number of pixel units included in a pixel and the light output of each pixel unit can be determined as required.
  • the display pixel unit P1 can emit light.
  • the structure of the dummy pixel unit P0 is formed by deleting the circuit structure of the display pixel unit P1.
  • the pixel circuit of the dummy pixel unit P0 is incomplete.
  • the pixel circuit of the dummy pixel unit P0 is incomplete including that the pixel circuit of the dummy pixel unit P0 does not have elements or components of at least one of the pixel circuit structures 10 .
  • the pixel definition layer does not have an opening at the dummy pixel unit P0, or the dummy pixel unit P0 does not have an anode, so that the dummy pixel unit P0 does not emit light.
  • the first power supply line 311 is configured to supply a constant first voltage signal ELVDD to the pixel circuit structure 10
  • the second power supply line 312 is configured to supply a constant second voltage signal ELVSS to the pixel circuit structure 10
  • the first voltage The signal ELVDD is greater than the second voltage signal ELVSS.
  • the light emission control signal line 110 is configured to provide the light emission control signal EM to the pixel circuit structure 10 .
  • the first initialization signal line 211 and the second initialization signal line 212 are configured to provide an initialization signal Vint to the pixel circuit structure 10
  • the first reset control signal line 111 is configured to provide a reset control signal RESET to the pixel circuit structure 10
  • the second reset The control signal line 112 is configured to provide the scan signal SCAN to the pixel circuit structure 10 .
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between, but not limited to, the first voltage signal ELVDD and the second voltage signal ELVSS, for example, the initialization signal Vint may be smaller than or equal to the second voltage signal ELVSS.
  • the pixel circuit structure 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, The second reset transistor T7 and the storage capacitor C1.
  • the driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS and other signals provided by the gate line 113 glow.
  • the driving transistor is connected to the organic light emitting element, and outputs a driving current to the organic light emitting element under the control of data signals, scan signals and other signals, thereby driving the organic light emitting element to emit light.
  • the display panel 100 provided by the embodiment of the present disclosure further includes: a data driving circuit and a scan driving circuit.
  • the data driving circuit is configured to provide the data signal DATA to the display pixel unit P1 according to the instruction of the control circuit;
  • the scanning driving circuit is configured to provide the display pixel unit P1 with the light-emitting control signal EM, the scanning signal SCAN and the reset control signal according to the instruction of the control circuit RESET and other signals.
  • the control circuit includes, but is not limited to, an external integrated circuit (IC).
  • the scan drive circuit is a GOA (Gate On Array) structure mounted on the display panel, or a drive chip (IC) structure that is bonded to the display panel.
  • GOA Gate On Array
  • the display panel 100 further includes a power source (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 311 and the second power line 312 respectively.
  • the initialization signal lines (the first initialization signal line 211 and the second initialization signal line 212 ) provide the display pixel unit P1 with the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint and the like.
  • the second electrode C12 of the storage capacitor C1 is electrically connected to the first power line 311
  • the first electrode C11 of the storage capacitor C1 is electrically connected to the second electrode T32 of the threshold compensation transistor T3
  • the gate T20 of the data writing transistor T2 is electrically connected to the gate line 113
  • the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the driving transistor T1, respectively.
  • the gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first electrode T31 of the threshold compensation transistor T3 is electrically connected to the second electrode T12 of the driving transistor T1, and the second electrode T32 of the threshold compensation transistor T3 is electrically connected to the driving transistor T1.
  • the gate T10 is electrically connected.
  • the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110 .
  • the first electrode T41 and the second electrode T42 of the first light emission control transistor T4 are electrically connected to the first power supply line 311 and the first electrode T11 of the driving transistor T1, respectively.
  • the first electrode T51 and the second electrode T52 of the second light emission control transistor T5 are respectively electrically connected to the second electrode T12 of the driving transistor T1 and the first electrode 201 of the light emitting element 20 .
  • the second electrode 202 of the light-emitting element 20 (which may be a common electrode of the OLED, such as a cathode) is electrically connected to the second power line 312 .
  • the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111
  • the first electrode T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211
  • the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1.
  • the gate T70 of the second reset transistor T7 is electrically connected to the second initialization signal line 212
  • the first electrode T71 of the second reset transistor T7 is electrically connected to the second initialization signal line 212
  • the second electrode T72 of the second reset transistor T7 is electrically connected to the second initialization signal line 212.
  • the first electrode 201 of the light-emitting element 20 is electrically connected.
  • the transistors used in an embodiment of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is the first pole and the other pole is the second pole, so all or part of the first pole of the transistor in the embodiment of the present disclosure and the second pole are interchangeable as required.
  • the first electrode of the transistor described in the embodiments of the present disclosure may be the source electrode, and the second electrode may be the drain electrode; or, the first electrode of the transistor may be the drain electrode and the second electrode may be the source electrode.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the embodiments of the present disclosure are described by taking the transistors all adopting P-type transistors as an example. Based on the description and teachings of the present disclosure, those of ordinary skill in the art can easily imagine that at least some of the transistors in the pixel circuit structure of the embodiments of the present disclosure use N-type transistors, that is, use N-type transistors. Therefore, these implementations are also within the protection scope of the present disclosure.
  • a method for driving a pixel unit in a display panel provided by an embodiment of the present disclosure will be described below with reference to FIG. 6 and FIG. 32 .
  • the driving method of the pixel unit includes a first reset phase t1 , data writing and threshold compensation, a second reset phase t2 and a light-emitting phase t3 .
  • the light emission control signal EM is set to be an off voltage
  • the reset control signal RESET is set to be an on voltage
  • the scan signal SCAN is set to an off voltage
  • the light emission control signal EM is set as the off voltage
  • the reset control signal RESET is set as the off voltage
  • the scan signal SCAN is set as the on voltage.
  • the light-emitting control signal EM is set to be the turn-on voltage
  • the reset control signal RESET is set to be the turn-off voltage
  • the scan signal SCAN is set to be the turn-off voltage.
  • the first voltage signal ELVDD, the second voltage signal ELVSS, and the initialization signal Vint are all constant voltage signals, and the initialization signal Vint is between the first voltage signal ELVDD and the second voltage signal ELVSS.
  • the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first electrode and the second stage of the corresponding transistor
  • the turn-off voltage refers to a voltage that can turn off the first electrode and the second stage of the corresponding transistor.
  • the turn-on voltage is a low voltage (eg, 0V)
  • the turn-off voltage is a high voltage (eg, 5V)
  • the turn-on voltage is a high voltage (eg, 5V)
  • the turn-off voltage is high.
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 32 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (eg, 0V), and the turn-off voltage is a high voltage (eg, 5V).
  • the first reset transistor T6 transmits the initialization signal (initialization voltage) Vint to the gate of the drive transistor T1 and is stored by the storage capacitor C1, resets the drive transistor T1 and erases the data stored in the last (last frame) light emission.
  • the light emission control signal EM is the off voltage
  • the reset control signal RESET is the off voltage
  • the scan signal SCAN is the on voltage.
  • the data writing transistor T2 and the threshold compensation transistor T3 are in the conductive state
  • the second reset transistor T7 is in the conductive state
  • the second reset transistor T7 transmits the initialization signal Vint to the first electrode of the light-emitting element 20 to emit light.
  • the element 20 is reset; while the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the data writing transistor T2 transmits the data signal voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data signal DATA and transmits the voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. Pole write data signal DATA.
  • the threshold compensation transistor T3 is turned on to connect the drive transistor T1 in a diode configuration, thereby charging the gate of the drive transistor T1.
  • the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data signal voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and drives according to the scan signal SCAN.
  • the gate voltage of the transistor T1 performs threshold voltage compensation. At this stage, the voltage difference across the storage capacitor C1 is ELVDD-VDATA-Vth.
  • the light-emitting control signal EM is the turn-on voltage
  • the reset control signal RESET is the turn-off voltage
  • the scan signal SCAN is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is kept as VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1 and the
  • the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light according to the light emission control signal EM.
  • the luminous current I satisfies the following saturation current formula:
  • ⁇ n is the mobility of the driving transistor channel
  • Cox is the drive transistor T1 channel capacitance per unit area
  • W and L are the channel width and channel length of the drive transistor T1
  • Vgs is the gate and source of transistor T1 The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the pixel circuit structure can compensate the threshold voltage of the driving transistor T1 very well.
  • the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted.
  • the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display time period of one frame.
  • the proportion of the duration of the light-emitting phase t3 to the display duration of one frame can be adjusted.
  • the first reset transistor T6 or the second reset transistor T7 may not be provided, that is, the embodiment of the present disclosure is not limited to the specific pixel circuit shown in FIG. Compensated pixel circuit. Based on the description and teaching of the present disclosure, other arrangements that can be easily conceived by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
  • the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole V10, and the first power supply line 311 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole V20.
  • the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 through the via V30, and the first power line 311 is electrically connected to the conductive block BK through the via V0.
  • one end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through the via hole V11, and the other end of the first connection electrode 31a is electrically connected to the first electrode T61 of the first reset transistor T6 through the via hole V12 are connected, so that the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211 .
  • One end of the second connection electrode 31b is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole V21, and the other end of the second connection electrode 31b is electrically connected to the gate T10 (that is, the storage capacitor) of the driving transistor T1 through the via hole V22.
  • the first pole C11) of C1 is electrically connected, so that the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (ie, the first pole C11 of the storage capacitor C1).
  • One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through the via hole V31, and the other end of the third connection electrode 31c is electrically connected to the first electrode T71 of the second reset transistor T7 through the via hole V32, so that the first The first electrodes T71 of the two reset transistors T7 are electrically connected to the second initialization signal line 212 .
  • the fourth connection electrode 31d is electrically connected to the second electrode T52 of the second light-emitting control transistor T5 through the via hole V40.
  • the second electrode C12 of the storage capacitor C1 has an opening OPN1 so that the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 through the via hole V22.
  • the active layer may be formed by first forming a semiconductor pattern layer of semiconductor material. Then, the semiconductor pattern layer is formed by doping the first conductive pattern layer LY1 as a mask. Doping can be heavy doping. The portion of the semiconductor pattern layer covered by the first conductive pattern layer LY1 forms a channel, and the portion of the semiconductor pattern layer not covered by the first conductive pattern layer LY1 is conductorized to form the source and drain of the transistor.
  • the semiconductor material includes, but is not limited to, polysilicon.
  • the first power supply signal line 311 is narrowed at the overlap with the lateral signal line.
  • the first power supply signal line 311 is narrowed where it overlaps with the gate line 113 .
  • FIG. 33 shows an active layer, a first conductive pattern layer LY1, a second conductive pattern layer LY2, a third conductive pattern layer LY3, and vias.
  • a circle with a cross inside it in Figure 33 represents a via.
  • Components in the same conductive pattern layer are formed from the same film layer using the same patterning process.
  • the pixel circuit of the display substrate shown in FIG. 33 may be as shown in FIG. 31 .
  • the embodiment of the present disclosure is described by taking a structure in which the pixel circuit of the display mask is a 7T1C as an example, but is not limited thereto.
  • the pixel circuit of the display substrate may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in this embodiment of the present disclosure.
  • the gate line 113 in the display pixel unit is combined with the first pole C11 of the storage capacitor C11 to form the first plate of the load capacitor in the dummy pixel unit, in order to provide a larger load capacitance.
  • a barrier layer BR and a first gate insulating layer GI1 are provided between the base substrate and the first conductive layer LY1, and a barrier layer BR and a first gate insulating layer GI1 are provided between the first conductive layer LY1 and the second conductive layer LY2.
  • the second gate insulating layer GI2 an interlayer insulating layer is provided between the second conductive layer LY2 and the third conductive layer LY3, and the via hole penetrates through the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD at least one.
  • the barrier layer BR, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD and the passivation layer PVX are made of inorganic insulating materials, the first planarization layer PLN1, the second planarization layer PLN2, The pixel definition layer PDL and the support layer PS can be made of organic insulating materials, but not limited thereto.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • the display device includes an OLED display device or any product or device with a display function, such as a computer, a mobile phone, a watch, an electronic picture frame, and a navigator including an OLED display device.
  • a display function such as a computer, a mobile phone, a watch, an electronic picture frame, and a navigator including an OLED display device.

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Abstract

提供一种显示面板和显示装置。显示面板包括透光区域（R1）；显示区域（R2），围绕透光区域（R1）设置或位于透光区域（R1）的一侧；边框区域（R3），位于透光区域（R1）和显示区域（R2）之间；多条数据线（313），包括位于边框区域（R3）内的多条边框区域数据线（313a）和位于显示区域（R2）内的多条显示区域数据线（313b），多条边框区域数据线（313a）和多条显示区域数据线（313b）分别相连；多条栅线（113），包括位于边框区域（R3）内的多条边框区域栅线（113a）和位于显示区域（R2）内的多条显示区域栅线（113b），多条边框区域栅线（113a）和多条显示区域栅线（113b）分别相连；边框区域栅线（113a）包括第一部分，边框区域数据线（313a）包括第一部分，边框区域栅线（113a）的第一部分与边框区域数据线（313a）的第一部分的延伸方向相同，边框区域栅线（113a）的第一部分与多条边框区域数据线（313a）中的一条的第一部分重叠。

Description

显示面板和显示装置 技术领域
本公开的实施例涉及一种显示面板和显示装置。
背景技术
随着用户对电子设备产品的屏占比要求的日益提高，柔性面板已发展出挖槽、挖孔等多种形式，在正常显示区屏下摄像头技术成熟之前，目前较为成熟的、屏占比最高的技术为屏内开孔技术。
发明内容
本公开的实施例提供一种显示面板和显示装置。
本公开的至少一实施例提供一种显示面板，包括：透光区域；显示区域，围绕所述透光区域设置或位于所述透光区域的一侧；边框区域，位于所述透光区域和所述显示区域之间；多条数据线，位于衬底基板上，包括位于所述边框区域内的多条边框区域数据线和位于所述显示区域内的多条显示区域数据线，所述多条边框区域数据线和所述多条显示区域数据线分别相连；以及多条栅线，位于所述衬底基板上，包括位于所述边框区域内的多条边框区域栅线和位于所述显示区域内的多条显示区域栅线，所述多条边框区域栅线和所述多条显示区域栅线分别相连；所述边框区域栅线包括第一部分，所述边框区域数据线包括第一部分，所述边框区域栅线的所述第一部分的延伸方向与所述边框区域数据线的所述第一部分的延伸方向相同，所述边框区域栅线的所述第一部分与所述多条边框区域数据线中的一条的所述第一部分在垂直于所述衬底基板的方向上重叠。
在本公开的一个或多个实施例中，所述边框区域栅线的与所述边框区域数据线重叠的部分的宽度小于或等于所述边框区域数据线的宽度。
在本公开的一个或多个实施例中，所述边框区域栅线的与所述边框区域数据线重叠的部分在其延伸方向上的长度小于所述边框区域栅线的所述第一部分的长度。
在本公开的一个或多个实施例中，所述边框区域栅线的与所述边框区域数据线重叠的部分在其延伸方向上的长度大于所述边框区域数据线的宽度。
在本公开的一个或多个实施例中，所述边框区域栅线的所述第一部分包括弯曲部，所述边框区域数据线的所述第一部分包括弯曲部。
在本公开的一个或多个实施例中，所述边框区域栅线的所述弯曲部和所述边框区域数据线的所述弯曲部的形状均包括弧形。
在本公开的一个或多个实施例中，从远离所述透光区域的方向到靠近所述透光区域的方向上，所述边框区域栅线与所述边框区域数据线重叠的部分的长度逐渐增大。
在本公开的一个或多个实施例中，相邻的边框区域数据线位于不同的层。
在本公开的一个或多个实施例中，所述相邻的边框区域数据线包括第一边框区域数据线和第二边框区域数据线，所述第一边框区域数据线比所述第二边框区域数据线更靠近所述衬底基板，所述第一边框区域数据线和所述第二边框区域数据线之间设有第一绝缘层。
在本公开的一个或多个实施例中，所述第一边框区域数据线和与其相连的显示区域数据线为一体结构，所述第二边框区域数据线和与其相连的显示区域数据线通过贯穿所述第一绝缘层的过孔相连。
在本公开的一个或多个实施例中，所述第一绝缘层包括钝化层和第一平坦化层。
在本公开的一个或多个实施例中，显示面板还包括初始化信号线以及第一导线，所述初始化信号线位于所述栅线的远离所述衬底基板的一侧，所述第一导线与所述第二边框区域数据线位于同一层，所述第一导线与所述初始化信号线相连。
在本公开的一个或多个实施例中，所述第一导线围绕所述透光区域设置。
在本公开的一个或多个实施例中，所述第二边框区域数据线和与其相连的显示区域数据线的连接位置位于所述第一导线的内侧。
在本公开的一个或多个实施例中，显示面板还包括第二导线，所述第二导线与所述第二边框区域数据线位于同一层，所述第二导线围绕所述第一导线设置，所述第二导线与所述第一导线彼此绝缘。
在本公开的一个或多个实施例中，所述第二导线在所述透光区域处具有开口。
在本公开的一个或多个实施例中，显示面板还包括多条发光控制信号线，所述多条发光控制信号线包括位于所述边框区域内的多条边框区域发光控制信号线和位于所述显示区域内的多条显示区域发光控制信号线，所述多条边框区域发光控制信号线和所述多条显示区域发光控制信号线分别相连，所述边框区域发光控制信号线包括第一部分，所述边框区域发光控制信号线的所述第一部分的延伸方向与所述边框区域数据线的所述第一部分的延伸方向相同，所述边框区域发光控制信号线的所述第一部分与所述多条边框区域数据线中的一条的所述第一部分在垂直于所述衬底基板的方向上重叠。
在本公开的一个或多个实施例中，所述边框区域栅线和所述边框区域发光控制信号线之一与所述第一边框区域数据线重叠，所述边框区域栅线和所述边框区域发光控制信号线之另一与所述第二边框区域数据线重叠。
在本公开的一个或多个实施例中，所述边框区域栅线与所述第一边框区域数据线重叠，所述边框区域发光控制信号线与所述第二边框区域数据线重叠，所述边框区域栅线与所述第一边框区域数据线之间的绝缘层的厚度小于所述边框区域发光控制信号线与所述第二边框区域数据线之间的绝缘层的厚度。
在本公开的一个或多个实施例中，所述多条发光控制信号线的个数与所述多条栅线的个数相等。
在本公开的一个或多个实施例中，所述边框区域发光控制信号线和所述显示区域发光控制信号线位于不同层。
在本公开的一个或多个实施例中，所述边框区域栅线比所述边框区域发光控制信号线更靠近所述衬底基板，所述边框区域栅线和所述边框区域发光控制信号线之间设有栅极绝缘层。
在本公开的一个或多个实施例中，所述发光控制信号线和所述第一边框区域数据线之间设有层间绝缘层。
在本公开的一个或多个实施例中，显示面板还包括第二平坦化层，所述第二平坦化层覆盖所述第二边框区域数据线。
在本公开的一个或多个实施例中，所述第一边框区域数据线、所述第二边框区域数据线、所述栅线、所述发光控制信号线中至少一个的材料包括金属或合金。
在本公开的一个或多个实施例中，显示面板还包括显示单元，所述显示单元包括有机发光二极管。
在本公开的一个或多个实施例中，显示面板还包括隔离柱，所述隔离柱位于所述边框区域内，并围绕所述透光区域设置，所述隔离柱位于所述多条边框区域数据线的靠近所述透光区域的一侧，所述隔离柱构成所述边框区域的内边界。
在本公开的一个或多个实施例中，所述隔离柱采用金属材料制作。
在本公开的一个或多个实施例中，所述隔离柱与所述第一边框区域数据线或所述第二边框区域数据线同层设置。
在本公开的一个或多个实施例中，所述隔离柱包括第一子层、第二子层和第三子层，所述第一子层比所述第二子层更靠近所述衬底基板，所述第二子层比所述第三子层更靠近所述衬底基板，所述第二子层的沿着所述透光区域的径向方向的尺寸小于所述第一子层的沿着所述透光区域的径向方向的尺寸，并且所述第二子层的沿着所述透光区域的径向方向的尺寸小于所述第三子层的沿着所述透光区域的径向方向的尺寸。
在本公开的一个或多个实施例中，所述有机发光二极管包括发光功能层，所述发光功能层包括位于所述隔离柱的远离所述透光区域的第一部分和位于 所述隔离柱上的第二部分，所述发光功能层的第一部分和所述发光功能层的第二部分在所述隔离柱的侧边处断裂。
在本公开的一个或多个实施例中，所述透光区域包括第一透光区域和第二透光区域，所述边框区域栅线包括第二部分，所述边框区域栅线的第二部分位于所述第一透光区域和所述第二透光区域之间，所述边框区域栅线的第二部分与负载电容的第一极板相连，所述负载电容的第二极板与所述负载电容的第一极板相对设置。
在本公开的一个或多个实施例中，所述负载电容的第二极板与所述边框区域栅线的第二部分部分重叠。
在本公开的一个或多个实施例中，所述边框区域栅线的第二部分与负载电容的第一极板为一体结构。
在本公开的一个或多个实施例中，显示面板还包括第一电源线，所述第一电源线被配置为提供恒定的电压信号，所述负载电容的第二极板与所述第一电源线相连。
本公开的至少一个实施例还提供一种显示装置，包括上述任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的示意图；
图2为一种显示面板的示意图；
图3为一种显示面板的示意图；
图4为一种显示面板的示意图；
图5为一种显示面板的局部示意图；
图6为本公开一实施例提供的一种显示面板中为每个像素单元提供信号的信号线的示意图；
图7为本公开一实施例提供的一种显示面板的局部平面图；
图8为图7中的数据线的平面图；
图9为图7中的栅线和发光控制信号线的平面图；
图10为图7的沿A-B线的剖视图；
图11为本公开一实施例提供的显示面板的剖视图；
图12为本公开一实施例提供的显示面板的平面图；
图13为本公开一实施例提供的显示面板中的第三导电图案层和第四导电图案层的平面图；
图14为本公开一实施例提供的显示面板中的第四导电图案层的平面图；
图15为本公开一实施例提供的显示面板的剖视图；
图16为本公开一实施例提供的显示面板中的初始化信号线和第二导线的平面图；
图17为本公开一实施例提供的显示面板的剖视图；
图18为本公开一实施例提供的显示面板的剖视图；
图19为本公开一实施例提供的显示面板的局部示意图；
图20为本公开一实施例提供的显示面板的局部示意图；
图21为本公开一实施例提供的显示面板的局部示意图；
图22为本公开一实施例提供的显示面板的示意图；
图23为本公开一实施例提供的一种显示面板的示意图；
图24为图23的局部示意图；
图25为边框区域栅线的第二部分处的虚设像素单元的平面图；
图26为图25中的虚设像素单元的有源层的图形；
图27为图25中的虚设像素单元的第一导电图案层的图形；
图28为图25中的虚设像素单元的第二导电图案层的图形；
图29为图25中的虚设像素单元的绝缘层的图形；
图30为图25中的虚设像素单元的第三导电图案层的图形；
图31为本公开一实施例提供的一种显示面板的像素电路结构的原理图；
图32为本公开实施例提供的显示面板中一个像素单元的时序信号图；以及
图33为本公开的实施例提供的显示基板的平面图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改 变后，则该相对位置关系也可能相应地改变。
图1为一种显示面板的示意图。如图1所示，显示面板包括透光区域R1和显示区域R2。采用屏内开孔的方案时，透光区域R1内的至少部分结构被去除，即，屏内开孔的方案需牺牲部分的显示区域以形成透光区域。如图1所示，透光区域R1为圆形。透光区域R1即为开孔区域。开孔区域的大小决定当前显示像素单元行缺少的显示像素单元的个数，显示像素单元的个数缺少的越多，栅线(扫描信号)的负载也缺的越多，扫描信号需要补偿的电容也越多。
图2为一种显示面板的示意图。图2所示的显示面板的透光区域R1的形状不同于图1所示的显示面板的透光区域R1。如图2所示，透光区域R1为跑道形。本公开的实施例提供的显示面板的透光区域R1的形状不限于图1和图2所示的形状，可根据需要设置。本公开的实施例提供的显示面板的透光区域R1的设置位置也不限于图中所示，可根据需要设置。本公开的以下实施例以透光区域R1的形状为圆形进行说明。
图3为一种显示面板的示意图。如图3所示，因透光区域R1处需要挖孔，从而不挖孔的情况下原本应该从该区域穿过的走线需要顺着透光区域R1的边缘延伸，从而形成边框区域R3。如图3所示，边框区域R3位于显示区域R2和透光区域R1之间。显示区域R2围绕透光区域R1，边框区域R3围绕透光区域R1。当然，在其他的实施例中，也可以显示区域R2位于透光区域R1的一侧，边框区域R3位于显示区域R2和透光区域R1之间。图3示出了数据线313、栅线113以及发光控制信号线213。
图3所示，栅线113位于第一导电图案层LY1，发光控制信号线213位于第二导电图案层LY2，数据线313位于第三导电图案层LY3。当然，在其他的实施例中，发光控制信号线213也可位于第一导电图案层LY1。
图3示出了第一方向X和第二方向Y。如图3所示，数据线313沿第二方向Y延伸，栅线113和发光控制信号线213均沿第一方向X延伸。此处描述每条信号线的延伸方向是指该信号线的总体延伸趋势，不排除该信号线包括不沿该方向延伸的部分。
图3未示出全部的信号线，本公开的实施例提供的显示面板还可以包括其他信号线。例如，本公开的实施例提供的显示面板还可以包括电源线以及初始化信号线等信号线。
图4为一种显示面板的示意图。图4示出了透光区域R1、显示区域R2和边框区域R3，为了图示清晰，省略了信号线。
图5为一种显示面板的局部示意图。图5示出了透光区域R1及其附近结构的示意图。图5示出了四条数据线313、两条栅线113以及两条发光控制信号线213。
一方面，屏内开孔不仅造成像素电路缺失，还造成了开孔区域(透光区域R1)横向及纵向的负载(Loading)缺失，然而，通常设计并未对此缺失负载进行补偿。根据挖槽异形屏的设计经验，该部分负载的缺失可能会导致像素单元缺失分界处的显示差异，例如开孔所在的横向范围显示偏暗等显示不良。现阶段市场上出现的面板开孔设计由于孔尺寸较小，常规显示画面该显示差异问题可能不会暴露，但在更加严格的显示条件(例如高刷新率)会出现该显示不良。又例如，整机厂商需求前置更多的摄像头传感器，需在同行位置设计跑道型的开孔，则负载缺失更多，该显示不良更易暴露。
另一方面，多条信号线形成在边框区域，信号线所占空间影响了边框区域的尺寸，不利于提高屏占比。
图6为本公开一实施例提供的一种显示面板中为每个像素单元提供信号的信号线的示意图。每个显示像素单元P1包括发光单元和为发光单元提供驱动电流的像素电路结构，发光单元可为电致发光单元，例如，有机电致发光单元，例如可为有机发光二极管(OLED)。显示像素单元P1为正常发光的像素单元。显示像素单元P1位于显示区域R2。
图6示出了栅线113、数据线313、第一电源线311、第二电源线312、发光控制信号线213和初始化信号线210。例如，栅线113被配置为向像素电路结构提供扫描信号SCAN或者复位信号RESET至少之一，当栅线113被配置为向像素电路结构提供复位信号RESET时，也可称作复位控制信号线。例如，在显示面板中，本行的像素单元的第二复位控制信号线112作为下一行的像素单元的第一复位控制信号线111。发光控制信号线213被配置为向显示像素单元P1提供发光控制信号EM。数据线313被配置为向像素电路结构10提供数据信号DATA，第一电源线311被配置为向像素电路结构10提供恒定的第一电压信号ELVDD，第二电源线312被配置为向像素电路结构提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。初始化信号线210被配置为向像素电路结构提供初始化信号Vint。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。例如，像素电路结构在扫描信号SCAN、数据信号DATA、初始化信号Vint、第一电压信号ELVDD、第二电压信号ELVSS、发光控制信号EM等信号的控制下输出驱动电流以驱动发光单元发光。
例如，如图6所示，栅线113位于第一导电图案层LY1，初始化信号线210位于第二导电图案层LY2，数据线313和第一电源线311位于第三导电图案层LY3，第二电源线312也可以位于第三导电图案层LY3。
图7为本公开一实施例提供的一种显示面板的局部平面图。如图7所示， 显示面板包括：透光区域R1、显示区域R2、边框区域R3、多条发光控制信号线213、多条数据线313以及多条栅线113。
如图7所示，显示区域R2围绕透光区域R1设置或位于透光区域R1的一侧。边框区域R3位于透光区域R1和显示区域R2之间。
例如，参考图6和图7，多条发光控制信号线213的个数与多条栅线113的个数相等。即，为每行像素单元设置一条发光控制信号线213，发光控制信号逐行驱动，从而改善低灰阶的调光闪烁问题。此情况下，在边框区域R3，使得横向的信号线的条数与纵向的信号线的条数相等，透光区域R1为圆形的情况下，边框区域R3可呈圆环形，但不限于此。
如图7所示，在边框区域R3内，一条栅线113在第一位置处与一条数据线313重叠，并在第二位置处与另一条数据线313重叠。如图7所示，在边框区域R3内，一条发光控制信号线213在第三位置处与一条数据线313重叠，并在第四位置处与另一条数据线313重叠。如图7所示，在边框区域R3内，一条数据线313在第五位置处与一条发光控制信号线213重叠，并在第六位置处与一条栅线113重叠。
图8为图7中的数据线的平面图。参考图7和图8，多条数据线313位于衬底基板上，包括位于边框区域R3内的多条边框区域数据线313a和位于显示区域R2内的多条显示区域数据线313b，多条边框区域数据线313a和多条显示区域数据线313b分别相连。每条数据线313包括位于边框区域R3内的边框区域数据线313a和位于显示区域R2内的显示区域数据线313b。图8还示出了多条显示区域数据线313c，多条显示区域数据线313c分别与多条边框区域数据线313a相连，此情况下，每条数据线313包括位于边框区域R3内的边框区域数据线313a、位于显示区域R2内的显示区域数据线313b和位于显示区域R2内的显示区域数据线313c。显示区域数据线313b和显示区域数据线313c分设在边框区域数据线313a的两侧。
图9为图7中的栅线和发光控制信号线的平面图。参考图7和图9，多条栅线113位于衬底基板上，包括位于边框区域R3内的多条边框区域栅线113a和位于显示区域R2内的多条显示区域栅线113b，多条边框区域栅线113a和多条显示区域栅线113b分别相连。每条栅线113包括位于边框区域R3内的边框区域栅线113a和位于显示区域R2内的显示区域栅线113b。图9还示出了多条显示区域栅线113c，多条显示区域栅线113c与多条边框区域栅线113a分别相连，此情况下，每条栅线113包括位于边框区域R3内的边框区域栅线113a、位于显示区域R2内的显示区域栅线113b以及位于显示区域R2内的显示区域栅线113c。显示区域栅线113b和显示区域栅线113c分设在边框区域栅线113a的两侧。
参考图7至图9，边框区域栅线113a包括第一部分1131，边框区域数据 线313a包括第一部分3131，边框区域栅线113a的第一部分1131的延伸方向与边框区域数据线313a的第一部分3131的延伸方向相同，边框区域栅线113a的第一部分1131与多条边框区域数据线313a中的一条的第一部分3131在垂直于衬底基板的方向上重叠。例如，延伸方向相同可指两个元件具有共形的部分，共形的部分的延伸方向相同，或者，共形的部分的延伸趋势相同。例如，延伸方向相同可指两个元件在同一点上的延伸方向相同。例如，延伸方向可指该线的总体延伸趋势，在该线不为直线的情况下，该线的切线的方向可为其延伸方向。延伸方向相同包括延伸方向完全相同和大致相同。图7中用双箭头的曲线示意性的描述了不同元件的重叠部分的延伸方向。
图10为图7的沿A-B线的剖视图。如图10所示，显示基板包括衬底基板BS。衬底基板BS上设有阻隔(barrier)层BR，阻隔层BR上设有第一栅绝缘层GI1，第一栅绝缘层GI1上设有第一导电图案层LY1，第一导电图案层LY1包括栅线113。第一导电图案层LY1上设有第二栅绝缘层GI2，在第二栅绝缘层GI2上设有第二导电图案层LY2，第二导电图案层LY2包括发光控制信号线213。第二导电图案层LY2上设有层间绝缘层ILD。层间绝缘层ILD上设有第三导电图案层LY3，第三导电图案层LY3包括数据线313。第三导电图案层LY3上设有钝化层PVX和第一平坦化层PLN1。
图10示出了第三方向Z。第三方向Z垂直于第一方向X。第三方向Z也垂直于第二方向Y。第三方向Z即为垂直于衬底基板BS的方向。参考图7至图10，边框区域栅线113a的第一部分1131与多条边框区域数据线313a中的一条的第一部分3131在垂直于衬底基板BS的方向上重叠。
根据以往测试经验及仿真结果，栅线的负载差异对显示面板的影响最大，其负载影响扫描信号SCAN的上升及下降沿时间，从而影响数据信号DATA的写入时间，数据信号DATA的写入时间的差异直接导致显示面板显示的明暗差异，从而，将栅线与数据线重叠以使其分别构成电容的两个极板，补偿栅线缺失的负载，减小显示面板的明暗差异，提高显示效果。本公开的实施例提供的显示面板，对挖孔造成的面板显示差异进行补正，提高显示质量。
例如，参考图7和图10，边框区域栅线113a的与边框区域数据线313a重叠的部分11为边框区域栅线113a的第一部分1131的一部分，边框区域栅线113a的与边框区域数据线313a重叠的部分11的宽度小于或等于边框区域数据线313a的宽度。
例如，参考图7和图8，边框区域数据线313a的与边框区域栅线113a重叠的部分31为边框区域数据线313a的第一部分3131的一部分。边框区域数据线313a的与边框区域栅线113a重叠的部分31在其延伸方向上的长度小于边框区域数据线313a的第一部分3131的长度。
本公开的实施例中，元件的长度可指在其延伸方向上的尺寸，元件的宽 度可指在垂直于其延伸方向的方向上的尺寸。
例如，参考图7和图9，边框区域栅线113a的与边框区域数据线313a重叠的部分11在其延伸方向上的长度小于边框区域栅线113a的第一部分1131的长度。
例如，参考图7，边框区域栅线113a的与边框区域数据线313a重叠的部分11在其延伸方向上的长度大于边框区域数据线313a的宽度。
例如，参考图7和图9，边框区域栅线113a的第一部分1131包括弯曲部，边框区域数据线313a的第一部分3131包括弯曲部。例如，边框区域栅线113a的弯曲部和边框区域数据线313a的弯曲部的形状均包括弧形。
例如，参考图7，从远离透光区域R1的方向到靠近透光区域R1的方向上，边框区域栅线113a与边框区域数据线313a重叠的部分的长度逐渐增大。
例如，参考图7、图9和图10，显示面板还包括多条发光控制信号线213，多条发光控制信号线213包括位于边框区域R3内的多条边框区域发光控制信号线213a和位于显示区域R2内的多条显示区域发光控制信号线213b，多条边框区域发光控制信号线213a和多条显示区域发光控制信号线213b分别相连，边框区域发光控制信号线213a包括第一部分2131，边框区域发光控制信号线213a的第一部分2131的延伸方向与边框区域数据线313a的第一部分3131的延伸方向相同，边框区域发光控制信号线213a的第一部分2131与多条边框区域数据线313a中的一条的第一部分3131在垂直于衬底基板BS的方向上重叠。从而，将发光控制信号线与数据线重叠以使其分别构成电容的两个极板，补偿发光控制信号线缺失的负载，提高显示效果。
例如，如图9所示，每条发光控制信号线213包括位于边框区域R3内的边框区域发光控制信号线213a和位于显示区域R2内的显示区域发光控制信号线213b。
例如，如图9所示，多条发光控制信号线213还包括位于显示区域R2内的多条显示区域发光控制信号线213c，多条显示区域发光控制信号线213c与多条边框区域发光控制信号线213a分别相连。每条发光控制信号线213包括位于边框区域R3内的边框区域发光控制信号线213a、位于显示区域R2内的显示区域发光控制信号线213b以及位于显示区域R2内的显示区域发光控制信号线213c。显示区域发光控制信号线213b和显示区域发光控制信号线213c分设在边框区域发光控制信号线213a的两侧。
例如，参考图7和图9，边框区域发光控制信号线213a的与边框区域数据线313a重叠的部分21在其延伸方向上的长度小于边框区域发光控制信号线213a的第一部分1131的长度。
例如，如图7所示，边框区域发光控制信号线213a的与边框区域数据线313a重叠的部分21在其延伸方向上的长度大于边框区域数据线313a的宽 度。
例如，参考图7和图9，边框区域发光控制信号线213a的第一部分2131包括弯曲部。例如，边框区域发光控制信号线213a的弯曲部和边框区域数据线313a的弯曲部的形状均包括弧形。
例如，如图7所示，从远离透光区域R1的方向到靠近透光区域R1的方向上，边框区域发光控制信号线213a与边框区域数据线313a重叠的部分21的长度逐渐增大。
例如，如图7所示，多个边框区域发光控制信号线213a与边框区域数据线313a重叠的部分21与多个边框区域栅线113a与边框区域数据线313a重叠的部分11交替设置。即，多个部分21与多个部分11交替设置。
图7以边框区域栅线113a的第一部分1131为圆的一部分、边框区域数据线313a的第一部分3131为圆的一部分以及边框区域发光控制信号线213a的第一部分2131为圆的一部分为例进行说明，但不限于此，在其他的实施例中，边框区域栅线113a的第一部分1131也可采用其他的弯曲形式，边框区域数据线313a的第一部分3131也可采用其他的弯曲形式，并且边框区域发光控制信号线213a的第一部分2131也可采用其他的弯曲形式。
图7和图10以相邻数据线313位于同一层，即，相邻数据线313位于第三导电图案层LY3为例进行说明，但不限于此。例如，在其他的实施例中，图7和图10所示的相邻的边框区域数据线313a也可位于不同的层。
图11为本公开一实施例提供的显示面板的剖视图。如图11所示，相邻的边框区域数据线313a位于不同的层，从而减小透光区域周围的边框区域内的信号线的占用空间，实现窄边框和更高的屏占比。例如，如图11所示，相邻的边框区域数据线313a包括第一边框区域数据线313a1和第二边框区域数据线313a2，第一边框区域数据线313a1比第二边框区域数据线313a2更靠近衬底基板BS，第一边框区域数据线313a1和第二边框区域数据线313a2之间设有绝缘层。例如，绝缘层包括钝化层PVX和第一平坦化层PLN1。
例如，在本公开的实施例中，发光控制信号线213可位于第二导电图案层LY2，但不限于此。在其他的实施例中，发光控制信号线213可分段形成，例如，边框区域发光控制信号线213a位于第二导电图案层LY2，而发光控制信号线213的除了边框区域发光控制信号线213a的部分位于第一导电图案层LY1。例如，图9中示出的显示区域发光控制信号线213b位于第一导电图案层LY1，而边框区域发光控制信号线213a位于第二导电图案层LY2。例如，只在透光区域R1附近的发光控制信号线213进行分段设置，其余位置处的发光控制信号线213可均位于第一导电图案层LY1。例如，发光控制信号线213的位于不同层的部分通过其间的贯穿绝缘层的过孔相连。
图12为本公开一实施例提供的显示面板的平面图。图12示出了第一边 框区域数据线313a1、第二边框区域数据线313a2、边框区域发光控制信号线213a以及边框区域栅线113a。
参考图11和图12，第一边框区域数据线313a1的第一部分3131与边框区域栅线113a的第一部分1131在垂直于衬底基板BS的方向上重叠。因第一边框区域数据线313a1的第一部分3131与边框区域栅线113a的第一部分1131之间的第二栅绝缘层GI2和层间绝缘层ILD的厚度之和相对较小，从而，大幅度的提高边框区域栅线和数据线之间的电容，减小边框区域栅线的负载缺失，增加边框区域栅线的负载，提高显示效果。通常来说，栅线的负载缺失对于显示效果的影响大于发光控制信号线的负载缺失对于显示效果的影响。
参考图11和图12，第二边框区域数据线313a2的第一部分3131和边框区域发光控制信号线213a的第一部分2131在垂直于衬底基板BS的方向上重叠。从而，减小边框区域发光控制信号线的负载缺失，增加边框区域发光控制信号线的负载，提高显示效果，减小透光区域周围的边框区域内的信号线的占用空间，实现窄边框和更高的屏占比。例如，如图11所示，第一平坦化层PLN1的厚度大于第二栅绝缘层GI2和层间绝缘层ILD的厚度之和。
参考图11和图12，第一边框区域数据线313a1位于第三导电图案层LY3，第二边框区域数据线313a2位于第四导电图案层LY4。第三导电图案层LY3和第四导电图案层LY4之间设置有绝缘层，绝缘层包括钝化层PVX和第一平坦化层PLN1。边框区域栅线113a位于第一导电图案层LY1，边框区域发光控制信号线213a位于第二导电图案层LY2，第一导电图案层LY1和第二导电图案层LY2之间设置有第二栅极绝缘层GI2。第二导电图案层LY2和第三导电图案层LY3之间设置有层间绝缘层ILD。衬底基板BS和第一导电图案层LY1之间设置阻隔层BR和第一栅极绝缘层GI1。第一栅极绝缘层GI1比阻隔层BR更靠近衬底基板BS。第四导电图案层LY4的远离衬底基板BS的一侧设置有第二平坦化层PLN2。本公开的实施例中，多个元件位于同一层是指该多个元件由同一膜层采用同一构图工艺形成。例如，位于第一导电图案层LY1的元件由同一膜层采用同一构图工艺形成，位于第二导电图案层LY2的元件由同一膜层采用同一构图工艺形成，位于第三导电图案层LY3的元件由同一膜层采用同一构图工艺形成，位于第四导电图案层LY4的元件由同一膜层采用同一构图工艺形成。
图11和图12还示出了边框区域栅线113a的与边框区域数据线313a重叠的部分11、边框区域发光控制信号线213a的与边框区域数据线313a重叠的部分21、边框区域数据线313a的与边框区域栅线113a重叠的部分31以及边框区域数据线313a的与边框区域发光控制信号线213a重叠的部分31。
在图11和图12中，第一边框区域数据线313a1的第一部分3131与边框 区域栅线113a的第一部分1131在垂直于衬底基板BS的方向上部分重叠，然而，在另一些实施例中，为了获得更多的重叠面积，增加补偿电容的数值，第一边框区域数据线313a1的第一部分3131在衬底基板BS上的正投影完全覆盖边框区域栅线113a的第一部分1131在衬底基板BS上的正投影。例如，在一些实施例中，边框区域数据线313a的第一部分3131在衬底基板BS上的正投影完全覆盖边框区域栅线113a的第一部分1131在衬底基板BS上的正投影。覆盖边框区域栅线113a的第一部分1131的数据线可根据需要设置在设定的层。
在图11和图12中，第二边框区域数据线313a2的第一部分3131和边框区域发光控制信号线213a的第一部分2131在垂直于衬底基板BS的方向上部分重叠，然而，在另一些实施例中，为了获得更多的重叠面积，增加补偿电容的数值，第二边框区域数据线313a2的第一部分3131在衬底基板BS上的正投影覆盖边框区域发光控制信号线213a的第一部分2131在衬底基板BS上的正投影。例如，在一些实施例中，边框区域数据线313a的第一部分3131在衬底基板BS上的正投影覆盖边框区域发光控制信号线213a的第一部分2131在衬底基板BS上的正投影。覆盖边框区域发光控制信号线213a的第一部分2131的数据线可根据需要设置在设定的层。
图13为本公开一实施例提供的显示面板中的第三导电图案层和第四导电图案层的平面图。如图13所示，第二边框区域数据线313a2和与其相连的显示区域数据线313b在连接位置CN相连，第一边框区域数据线313a和与其相连的显示区域数据线313b一体形成。
图14为本公开一实施例提供的显示面板中的第四导电图案层的平面图。如图14所示，第四导电图案层LY4包括第一导线321、第二边框区域数据线313a2以及第二导线322。第二导线322可呈网格状，但不限于此。如图14所示，第一导线321在透光区域R1处断开，即，第一导线321围绕透光区域R1设置，并在透光区域处具有开口OPN。
图15为本公开一实施例提供的显示面板的剖视图。例如，图15可为图13中的虚线框B1中的部分结构的截面图。如图13和图15所示，第二边框区域数据线313a2和一条显示区域数据线313b通过贯穿第一平坦化层PLN1以及钝化层PVX的过孔V1相连。
如图15所示，第二导电图案层LY2包括初始化信号线210，第一导线321通过贯穿第一平坦化层PLN1、钝化层PVX以及层间绝缘层ILD的过孔V2与初始化信号线210相连，初始化信号线210与第一导线321并联以减小信号线的电阻。
如图15所示，第三导电图案层LY3包括第一电源线311，第二导线322通过贯穿第一平坦化层PLN1以及钝化层PVX的过孔V3与第一电源线311 相连。
例如，如图13和图15所示，第一边框区域数据线313a1和与其相连的显示区域数据线313b为一体结构，第二边框区域数据线313a2和与其相连的显示区域数据线313b通过过孔V1相连。
例如，如图15所示，初始化信号线210位于栅线113的远离衬底基板BS的一侧，第一导线321与第二边框区域数据线313a2位于同一层，第一导线321与初始化信号线210通过过孔V2相连。
图16为本公开一实施例提供的显示面板中的初始化信号线和第二导线的平面图。例如，如图14和图16所示，第一导线321围绕透光区域R1设置，并构成边框区域R3的外边界。图16中的第一导线321以圆形示出，但第一导线321的形状不限于此，可根据需要设置。第一导线321构成封闭的结构，为环形结构，但不限于此。
例如，参考图13、图14和图16，第二边框区域数据线313a2和与其相连的显示区域数据线313b的连接位置位于第一导线321的内侧。第一导线321的内侧是指位于第一导线321所圈定的范围内。
例如，参考图13、图14和图15，第二导线322与第二边框区域数据线313a2位于同一层，第二导线322围绕第一导线321设置，第二导线322与第一导线321彼此绝缘。
图11至图15以相邻的第一数据线DL1(参照图13)和第二数据线DL2(参照图13)中第一数据线DL1位于第三导电图案层LY3，第二数据线DL2的第二边框区域数据线313a2位于第四导电图案层LY4，而其他部分位于第三导电图案层LY3为例进行说明，但不限于此。在其他的实施例中，相邻的第一数据线DL1和第二数据线DL2可分别位于第三导电图案层LY3和第四导电图案层LY4。此情况下，第二导线322在显示区域可沿第二方向Y延伸。
图11至图15以边框区域栅线113a与第一边框区域数据线313a1重叠，边框区域发光控制信号线213a与第二边框区域数据线313a2重叠为例进行说明，但不限于此。在其他的实施例中，也可以采用其他设置。
图17为本公开一实施例提供的显示面板的剖视图。如图17所示，边框区域栅线113a与第二边框区域数据线313a2重叠，边框区域发光控制信号线213a与第一边框区域数据线313a1重叠。
从而，在本公开的实施例中，边框区域栅线113a和边框区域发光控制信号线213a之一与第一边框区域数据线313a1重叠，边框区域栅线113a和边框区域发光控制信号线213a之另一与第二边框区域数据线313a2重叠。
例如，如图17所示，在边框区域R3，栅线113比发光控制信号线213更靠近衬底基板BS，栅线113和发光控制信号线213之间设有第二栅极绝缘层GI2。即，如图17所示，边框区域栅线113a比边框区域发光控制信号线 213a更靠近衬底基板BS，边框区域栅线113a和边框区域发光控制信号线213a之间设有第二栅极绝缘层GI2。
例如，如图17所示，发光控制信号线213和第一边框区域数据线313a1之间设有层间绝缘层ILD。
例如，如图17所示，显示面板还包括第二平坦化层PLN2，第二平坦化层PLN2覆盖第二边框区域数据线313a2。
例如，第一边框区域数据线313a1、第二边框区域数据线313a2、栅线113、发光控制信号线213中至少一个的材料包括金属或合金。
图18为本公开一实施例提供的显示面板的剖视图。图18所示的显示面板为显示面板的显示区域R2内的结构，即，正常发光区域的结构。例如，如图18所示，显示面板包括衬底基板BS，在衬底基板BS上设有阻隔层BR，在阻隔层BR上设置有源层ATL，有源层ATL包括源极区、漏极区以及位于源极区和漏极区之间的沟道，有源层ATL的源极区或漏极区与连接电极CNE1相连，连接电极CNE1通过贯穿层间绝缘层ILD、第二栅绝缘层GI2以及第一栅绝缘层GI1的过孔V4与有源层ATL相连。连接电极CNE1位于第三导电图案层LY3，第三导电图案层LY3的远离衬底基板BS的一侧设有钝化层PVX和第一平坦化层PLN1，连接电极CNE2位于第四导电图案层LY4，连接电极CNE2通过贯穿钝化层PVX和第一平坦化层PLN1的过孔V5与连接电极CNE1相连。
如图18所示，显示面板还包括发光单元EMU，发光单元EMU包括阳极ANE、发光功能层EML和阴极CTE，阳极ANE设置在第四导电图案层LY4上，阳极ANE通过贯穿第二平坦化层PLN2的过孔V6与连接电极CNE2相连。显示面板还包括封装层CPS，封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。
如图18所示，显示面板还包括像素定义层PDL和隔垫物PS。像素定义层PDL包括开口OPN，开口OPN被配置为限定显示像素单元的出光面积，隔垫物PS被配置为在形成发光功能层EML时支撑精细金属掩膜。
发光单元EMU包括有机发光二极管。发光功能层EML位于阴极CTE和阳极ANE之间。发光功能层EML至少包括发光层，还可以包括空穴传输层、空穴注入层，电子传输层、电子注入层至少之一。
例如，发光单元EMU的阳极和阴极之一与驱动晶体管电连接，驱动晶体管被配置为向发光单元EMU提供驱动发光单元EMU发光的驱动电流。
图19为本公开一实施例提供的显示面板的局部示意图。例如，如图19所示，显示面板还包括隔离柱34，隔离柱34位于边框区域R3内，并围绕透光区域R1设置，隔离柱34位于多条边框区域数据线313a的靠近透光区域 R1的一侧，隔离柱34构成边框区域R3的内边界。例如，隔离柱34采用金属材料制作。
例如，隔离柱34与第一边框区域数据线313a1或第二边框区域数据线313a2同层设置。即，隔离柱34位于第三导电图案层LY3，或者位于第四导电图案层LY4。
图20为本公开一实施例提供的显示面板的局部示意图。如图20所示，隔离柱34包括第一子层341、第二子层342和第三子层343，第一子层341比第二子层342更靠近衬底基板，第二子层342比第三子层343更靠近衬底基板，第二子层342的沿着透光区域R1的径向方向的尺寸小于第一子层341的沿着透光区域R1的径向方向的尺寸，并且第二子层342的沿着透光区域R1的径向方向的尺寸小于第三子层343的沿着透光区域R1的径向方向的尺寸。例如，第一子层341和第三子层343的材料均包括Ti，第二子层342的材料包括Al，但不限于此。
例如，如图20所示，有机发光二极管包括发光功能层EML1，发光功能层EML1包括位于隔离柱34的靠近透光区域R1的第一部分EML11和位于隔离柱34上的第二部分EML12，发光功能层EML1的第一部分EML11和发光功能层的第二部分EML12在隔离柱34的侧边处断裂。发光功能层EML1可为整层设置的发光功能层，但不限于此。发光功能层EML1可采用开口掩膜版制作，但不限于此。
因隔离柱34中的第二子层342的内缩设置，从而，发光功能层EML1形成在隔离柱34上时，使得发光功能层EML1断裂，进而避免外界环境例如水氧等侵蚀发光功能层EML1时，避免发光功能层EML1的位于显示区域R2内的部分被侵蚀，避免影响显示效果。
例如，如图20所示，发光功能层EML1还包括位于隔离柱34的远离透光区域R1的第三部分EML13，第三部分EML13与第二部分EML12在隔离柱34的侧边处断裂。
例如，如图20所示，显示面板还包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。第一封装层CPS1包括位于隔离柱34的靠近透光区域R1的第一部分CPS11和位于隔离柱34上的第二部分CPS12，第一部分CPS11和第二部分CPS12在隔离柱34的侧边处断裂。第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3的材质选择可如前所述。
例如，如图20所示，第一封装层CPS1还包括位于隔离柱34的远离透光区域R1的第三部分CPS13，第三部分CPS13和第二部分CPS12在隔离柱34的侧边处断裂。
例如，如图20所示，发光功能层EML1的第一部分EML11和发光功能层的第二部分EML12之间设置有第二封装层CPS2，发光功能层EML1的第 三部分EML13和发光功能层的第二部分EML12之间设置有第二封装层CPS2。
图20还示出了元件115和元件215。元件115位于第一导电图案层LY1，元件215位于第二导电图案层LY2。
图21为本公开一实施例提供的显示面板的局部示意图。与图19相比，图21所示的显示面板还示出了第一导线321。如图21所示，隔离柱34限定边框区域R3的内边界，第一导线321限定边框区域R3的外边界。
图22为本公开一实施例提供的显示面板的示意图。如图4和图22所示，显示面板DPN的透光区域R1为挖孔区域。如图22所示在挖孔区域内设置传感器50。例如，传感器50可以部分设置在挖孔区域，也可以全部设置在挖孔区域，对此不作限定。例如，传感器包括摄像头，但不限于此。在形成封装层之后，进行挖孔去除显示面板的位于透光区域R1的部分，以形成显示面板。
图23为本公开一实施例提供的一种显示面板的示意图。如图23所示，透光区域R1包括第一透光区域R1和第二透光区域R12。第一透光区域R1和第二透光区域R12均为挖孔区域。第一透光区域R1和第二透光区域R12之间也为边框区域R3。
图24为图23的局部示意图。如图24所示，边框区域栅线113a包括位于第一透光区域R1和第二透光区域R12之间的第二部分1132。边框区域栅线113a的第二部分1132设置虚设像素单元以进一步增加栅线的负载，减小栅线的负载缺失，减轻或避免横向显示(mura)不良。图23和图24示出了虚设区域RD，图24示出了位于虚设区域RD内的多个虚设像素单元P0。需要说明的是，虚设像素单元P0的个数不限于图中所示，可根据需要设置。
图25为边框区域栅线的第二部分处的虚设像素单元的平面图。边框区域栅线113a的第二部分1132与负载电容C0的第一极板C01相连，负载电容C0的第二极板C02与第一极板C01相对设置，负载电容C0可大幅度的提高栅线的负载，相当于将栅线与第二极板C02形成了一个比显示区域的显示像素单元的存储电容C1(后续描述)还大的电容，这样，一个虚设像素单元P0的栅线(扫描信号SCAN)的负载可为不设置负载电容C0的情况下的负载的10～20倍。例如，根据需要补偿的电容大小，以及虚设像素单元的个数，可以将虚设像素单元的负载电容C0的交叠面积设计成需要补偿的电容大小。
这种设计利用原来放置虚设像素单元的空间，对挖孔附近的栅线的电容进行了很有效的补偿，解决了挖孔处的横向显示不良(mura)的问题。
例如，如图25所示，边框区域栅线113a的第二部分1132与负载电容C0的第一极板C01一体形成，可由同一膜层采用同一构图工艺形成，可均位于第一导电图案层LY1。例如，如图25所示，边框区域栅线113a的第二 部分1132与负载电容C0的第一极板C01为一体结构。
例如，如图25所示，负载电容C0的第二极板C02与第一电源线311相连，第一电源线311被配置为提供恒定的电压信号。
例如，如图25所示，负载电容C0的第二极板C02与边框区域栅线113a的第二部分1132部分重叠。
在图25中，发光控制信号线110位于第一导电图案层LY1，但不限于此。在其他的实施例中，发光控制信号线110也可位于第二导电图案层LY2。
图26为图25中的虚设像素单元的有源层的图形。图27为图25中的虚设像素单元的第一导电图案层的图形。如图27所示，在第一导电图案层LY1中，栅线113的第二部分1132与负载电容C0的第一极板C01一体形成。图28为图25中的虚设像素单元的第二导电图案层的图形。第二导电图案层LY2包括负载电容C0的第二极板C02。如图28所示，负载电容C0的第二极板C02在其中间位置处具有开口。图29为图25中的虚设像素单元的绝缘层的图形，图中示出了贯穿绝缘层中的过孔。绝缘层包括第一栅绝缘层、第二栅绝缘层和层间绝缘层至少之一。图30为图25中的虚设像素单元的第三导电图案层的图形。第三导电图案层LY3包括第一连接电极31a、第二连接电极31b、第三连接电极31c、第四连接电极31d、数据线313、第一电源线311。例如，为了增加栅线的负载，第二连接电极31b通过过孔与负载电容C0的第二极板C02相连，但不限于此。
图31为本公开一实施例提供的一种显示面板的像素电路结构的原理图。图32为本公开实施例提供的显示面板中一个像素单元的时序信号图。图33为本公开的实施例提供的显示基板的平面图。请一并参阅图31和图6，显示面板100包括呈矩阵排布的多个显示像素单元P1，每个显示像素单元P1包括像素电路结构10、发光元件20以及栅线113、数据线313及电压信号线。例如，发光元件20为有机发光二极管(OLED)，发光元件20在其对应的像素电路结构10的驱动下发出红光、绿光、蓝光，或者白光等。该电压信号线可以是一条也可以包括多条。例如，如图31所示，该电压信号线包括第一电源线311、第二电源线312、发光控制信号线110、第一初始化信号线211、第二初始化信号线212、第一复位控制信号线111和第二复位控制信号线112等中的至少之一。栅线113被配置为向像素电路结构10提供扫描信号SCAN。数据线313被配置为向像素电路结构10提供数据信号DATA。例如，一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如，一个像素包括出射红光的像素单元，出射绿光的像素单元和出射蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
显示像素单元P1能发光。虚设像素单元P0的结构为显示像素单元P1 的线路结构删减形成。例如，虚设像素单元P0的像素电路不完整。虚设像素单元P0的像素电路不完整包括虚设像素单元P0的像素电路不具有像素电路结构10中至少之一的元件或部件。像素定义层在虚设像素单元P0处不具有开口，或者虚设像素单元P0不具有阳极，以使得虚设像素单元P0不发光。
例如，第一电源线311被配置为向像素电路结构10提供恒定的第一电压信号ELVDD，第二电源线312被配置为向像素电路结构10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。发光控制信号线110被配置为向像素电路结构10提供发光控制信号EM。第一初始化信号线211和第二初始化信号线212被配置为向像素电路结构10提供初始化信号Vint，第一复位控制信号线111被配置为向像素电路结构10提供复位控制信号RESET，第二复位控制信号线112被配置为向像素电路结构10提供扫描信号SCAN。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。
如图31和图33所示，该像素电路结构10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。驱动晶体管T1与发光元件20电连接，并在由栅线113提供的扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
在有机发光二极管显示面板的像素单元中，驱动晶体管与有机发光元件连接，在数据信号、扫描信号等信号的控制下向有机发光元件输出驱动电流，从而驱动有机发光元件发光。
例如，本公开实施例提供的显示面板100还包括：数据驱动电路和扫描驱动电路。数据驱动电路被配置为根据控制电路的指令向显示像素单元P1提供数据信号DATA；扫描驱动电路被配置为根据控制电路的指令向显示像素单元P1提供发光控制信号EM、扫描信号SCAN以及复位控制信号RESET等信号。例如，控制电路包括外部集成电路(IC)，但不限于此。例如，扫描驱动电路为安装于该显示面板上的GOA(Gate On Array)结构，或者为与该显示面板进行绑定(Bonding)的驱动芯片(IC)结构。例如，还可以采用不同的驱动电路分别提供发光控制信号EM和扫描信号SCAN。例如，显示面板100还包括电源(图中未示出)以提供上述电压信号，根据需要可以为电压源或电流源，所述电源被配置为分别通过第一电源线311、第二电源线312、以及初始化信号线(第一初始化信号线211和第二初始化信号线212)向显示像素单元P1提供第一电压信号ELVDD、第二电源电压ELVSS、以及初始化信号Vint等。
如图31和图33所示，存储电容C1的第二极C12与第一电源线311电连接，存储电容C1的第一极C11与阈值补偿晶体管T3的第二极T32电连接。数据写入晶体管T2的栅极T20与栅线113电连接，数据写入晶体管T2的第一极T21与第二极T22分别与数据线313、驱动晶体管T1的第一极T11电连接。阈值补偿晶体管T3的栅极T30与栅线113电连接，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12电连接，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10电连接。
例如，如图31和图33所示，第一发光控制晶体管T4的栅极T40和第二发光控制晶体管T5的栅极T50均与发光控制信号线110相连。
例如，如图31和图33所示，第一发光控制晶体管T4的第一极T41与第二极T42分别与第一电源线311和驱动晶体管T1的第一极T11电连接。第二发光控制晶体管T5的第一极T51与第二极T52分别与驱动晶体管T1的第二极T12、发光元件20的第一电极201电连接。发光元件20的第二电极202(可为OLED的公共电极，例如阴极)与第二电源线312电连接。
例如，如图31和图33所示，第一复位晶体管T6的栅极T60与第一复位控制信号线111电连接，第一复位晶体管T6的第一极T61与第一初始化信号线211电连接，第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10电连接。第二复位晶体管T7的栅极T70与第二初始化信号线212电连接，第二复位晶体管T7的第一极T71与第二初始化信号线212电连接，第二复位晶体管T7的第二极T72与发光元件20的第一电极201电连接。
需要说明的是，本公开一实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开一实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
以下将结合图6和图32对本公开实施例提供的显示面板中一个像素单元的驱动方法进行说明。
如图32所示，在一帧显示时间段内，像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2和发光阶段t3。
在第一复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为开启电压，设置扫描信号SCAN为关闭电压。
在数据写入及阈值补偿和第二复位阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为开启电压。
在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为关闭电压。
如图32所示，第一电压信号ELVDD、第二电压信号ELVSS、以及初始化信号Vint均为恒定的电压信号，初始化信号Vint介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如，本公开实施例中的开启电压是指能使相应晶体管的第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图32所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
请一并参阅图6和图32，在第一复位阶段t1，发光控制信号EM为关闭电压，复位控制信号RESET为开启电压，扫描信号SCAN为关闭电压。此时，第一复位晶体管T6处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将初始化信号(初始化电压)Vint传输到驱动晶体管T1的栅极并被存储电容C1存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2，发光控制信号EM为关闭电压，复位控制信号RESET为关闭电压，扫描信号SCAN为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，第二复位晶体管T7处于导通状态，第二复位晶体管T7将初始化信号Vint传输到发光元件20的第一电极，以将发光元件20复位；而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。此时，数据写入晶体管T2将数据信号电压VDATA传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号SCAN和数据信号DATA并根据扫描信号SCAN向驱动晶体管T1的第一极写入数据信号DATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶 体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为VDATA+Vth，其中，VDATA为数据信号电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容C1两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号RESET为关闭电压，扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电压信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为VDATA+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20，发光元件20发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制有发光元件20发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(VDATA+Vth-ELVDD-Vth) 2＝K(VDATA-ELVDD) 2
其中，
Figure PCTCN2020081234-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路结构非常好的补偿了驱动晶体管T1的阈值电压。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动电路103或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如，在其他实施例中，可以不提供第一复位晶体管T6或第二复位晶体管T7等，也即本公开实施例不限于图6所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
如图33所示，数据线313通过过孔V10与数据写入晶体管T2的第一极T21电连接，第一电源线311通过过孔V20与第一发光控制晶体管T4的第一极T41电连接，第一电源线311通过过孔V30与存储电容C1的第二极C12 电连接，第一电源线311通过过孔V0与导电块BK电连接。
如图33所示，第一连接电极31a的一端通过过孔V11与第一初始化信号线211电连接，第一连接电极31a的另一端通过过孔V12与第一复位晶体管T6的第一极T61相连，进而使得第一复位晶体管T6的第一极T61与第一初始化信号线211电连接。第二连接电极31b的一端通过过孔V21与第一复位晶体管T6的第二极T62电连接，第二连接电极31b的另一端通过过孔V22与驱动晶体管T1的栅极T10(也即存储电容C1的第一极C11)电连接，从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10(也即存储电容C1的第一极C11)电连接。第三连接电极31c的一端通过过孔V31与第二初始化信号线212电连接，第三连接电极31c的另一端通过过孔V32与第二复位晶体管T7的第一极T71电连接，从而使得第二复位晶体管T7的第一极T71与第二初始化信号线212电连接。第四连接电极31d通过过孔V40与第二发光控制晶体管T5的第二极T52电连接。形成第三导电图案层后，即可得到如图3所示的显示基板。
如图33所示，存储电容C1的第二极C12具有开口OPN1以便于第二连接电极31b的另一端通过过孔V22与驱动晶体管T1的栅极T10电连接。
形成有源层可通过先形成半导体材料的半导体图案层。再以第一导电图案层LY1为掩膜版对半导体图案层进行掺杂形成。掺杂可采用重掺杂。半导体图案层的被第一导电图案层LY1覆盖的部分形成沟道，而半导体图案层的未被第一导电图案层LY1覆盖的部分被导体化，形成晶体管的源极和漏极。例如，半导体材料包括多晶硅，但不限于此。
如图33所示，为了减小寄生电容，第一电源信号线311在与横向的信号线的交叠处收窄。例如，第一电源信号线311在其与栅线113的交叠处收窄。
图33示出了有源层、第一导电图案层LY1、第二导电图案层LY2、第三导电图案层LY3以及过孔。图33中内含叉号的圆圈表示过孔。同一导电图案层中的元件由同一膜层采用同一构图工艺形成。
图33所示的显示基板的像素电路可如图31所示。本公开的实施例以显示面膜的像素电路为7T1C的结构为例进行说明，但不限于此。显示基板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
结合图25和图33，可知在虚设像素单元中，相当于显示像素单元中的栅线113与存储电容C11的第一极C11结合在一起形成虚设像素单元中的负载电容的第一极板，以便于提供较大的负载电容。
例如，图33所示的显示面板中，衬底基板和第一导电层LY1之间设置有阻隔层BR和第一栅绝缘层GI1，第一导电层LY1和第二导电层LY2之间设置有第二栅绝缘层GI2，第二导电层LY2和第三导电层LY3之间设置有层 间绝缘层，过孔贯穿第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD至少之一。
本公开的实施例中，阻隔层BR、第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD、钝化层PVX、第一平坦化层PLN1、第二平坦化层PLN2、像素定义层PDL和支撑层PS均采用绝缘材料制作。例如，阻隔层BR、第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD和钝化层PVX采用无机绝缘材料制作，第一平坦化层PLN1、第二平坦化层PLN2、像素定义层PDL和支撑层PS可采用有机绝缘材料制作，但不限于此。
本公开至少一实施例还提供一种显示装置，包括上述任一显示面板。
例如，显示装置包括OLED显示装置或包括OLED显示装置的电脑、手机、手表、电子画框、导航仪等任何具有显示功能的产品或器件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

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  1. 一种显示面板，包括：
    透光区域；
    显示区域，围绕所述透光区域设置或位于所述透光区域的一侧；
    边框区域，位于所述透光区域和所述显示区域之间；
    多条数据线，位于衬底基板上，包括位于所述边框区域内的多条边框区域数据线和位于所述显示区域内的多条显示区域数据线，所述多条边框区域数据线和所述多条显示区域数据线分别相连；以及
    多条栅线，位于所述衬底基板上，包括位于所述边框区域内的多条边框区域栅线和位于所述显示区域内的多条显示区域栅线，所述多条边框区域栅线和所述多条显示区域栅线分别相连，
    其中，所述边框区域栅线包括第一部分，所述边框区域数据线包括第一部分，所述边框区域栅线的所述第一部分的延伸方向与所述边框区域数据线的所述第一部分的延伸方向相同，所述边框区域栅线的所述第一部分与所述多条边框区域数据线中的一条的所述第一部分在垂直于所述衬底基板的方向上重叠。
  2. 根据权利要求1所述的显示面板，其中，所述边框区域栅线的与所述边框区域数据线重叠的部分的宽度小于或等于所述边框区域数据线的宽度。
  3. 根据权利要求1或2所述的显示面板，其中，所述边框区域栅线的与所述边框区域数据线重叠的部分在其延伸方向上的长度小于所述边框区域栅线的所述第一部分的长度。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述边框区域栅线的与所述边框区域数据线重叠的部分在其延伸方向上的长度大于所述边框区域数据线的宽度。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述边框区域栅线的所述第一部分包括弯曲部，所述边框区域数据线的所述第一部分包括弯曲部。
  6. 根据权利要求5所述的显示面板，其中，所述边框区域栅线的所述弯曲部和所述边框区域数据线的所述弯曲部的形状均包括弧形。
  7. 根据权利要求1-6任一项所述的显示面板，其中，从远离所述透光区域的方向到靠近所述透光区域的方向上，所述边框区域栅线与所述边框区域数据线重叠的部分的长度逐渐增大。
  8. 根据权利要求1-7任一项所述的显示面板，其中，相邻的边框区域数据线位于不同的层。
  9. 根据权利要求1-8任一项所述的显示面板，其中，所述相邻的边框区 域数据线包括第一边框区域数据线和第二边框区域数据线，所述第一边框区域数据线比所述第二边框区域数据线更靠近所述衬底基板，所述第一边框区域数据线和所述第二边框区域数据线之间设有第一绝缘层。
  10. 根据权利要求9所述的显示面板，其中，所述第一边框区域数据线和与其相连的显示区域数据线为一体结构，所述第二边框区域数据线和与其相连的显示区域数据线通过贯穿所述第一绝缘层的过孔相连。
  11. 根据权利要求9或10所述的显示面板，其中，所述第一绝缘层包括钝化层和第一平坦化层。
  12. 根据权利要求9-11任一项所述的显示面板，还包括初始化信号线以及第一导线，其中，所述初始化信号线位于所述栅线的远离所述衬底基板的一侧，所述第一导线与所述第二边框区域数据线位于同一层，所述第一导线与所述初始化信号线相连。
  13. 根据权利要求12所述的显示面板，其中，所述第一导线围绕所述透光区域设置。
  14. 根据权利要求13所述的显示面板，其中，所述第二边框区域数据线和与其相连的显示区域数据线的连接位置位于所述第一导线的内侧。
  15. 根据权利要求9-14任一项所述的显示面板，还包括第二导线，其中，所述第二导线与所述第二边框区域数据线位于同一层，所述第二导线围绕所述第一导线设置，所述第二导线与所述第一导线彼此绝缘。
  16. 根据权利要求15所述的显示面板，其中，所述第二导线在所述透光区域处具有开口。
  17. 根据权利要求9-16任一项所述的显示面板，还包括多条发光控制信号线，其中，所述多条发光控制信号线包括位于所述边框区域内的多条边框区域发光控制信号线和位于所述显示区域内的多条显示区域发光控制信号线，所述多条边框区域发光控制信号线和所述多条显示区域发光控制信号线分别相连，所述边框区域发光控制信号线包括第一部分，所述边框区域发光控制信号线的所述第一部分的延伸方向与所述边框区域数据线的所述第一部分的延伸方向相同，所述边框区域发光控制信号线的所述第一部分与所述多条边框区域数据线中的一条的所述第一部分在垂直于所述衬底基板的方向上重叠。
  18. 根据权利要求17所述的显示面板，其中，所述边框区域栅线和所述边框区域发光控制信号线之一与所述第一边框区域数据线重叠，所述边框区域栅线和所述边框区域发光控制信号线之另一与所述第二边框区域数据线重叠。
  19. 根据权利要求17所述的显示面板，其中，所述边框区域栅线与所述第一边框区域数据线重叠，所述边框区域发光控制信号线与所述第二边框区 域数据线重叠，所述边框区域栅线与所述第一边框区域数据线之间的绝缘层的厚度小于所述边框区域发光控制信号线与所述第二边框区域数据线之间的绝缘层的厚度。
  20. 根据权利要求17-19任一项所述的显示面板，其中，所述多条发光控制信号线的个数与所述多条栅线的个数相等。
  21. 根据权利要求17-20任一项所述的显示面板，其中，所述边框区域发光控制信号线和所述显示区域发光控制信号线位于不同层。
  22. 根据权利要求17-21任一项所述的显示面板，其中，所述边框区域栅线比所述边框区域发光控制信号线更靠近所述衬底基板，所述边框区域栅线和所述边框区域发光控制信号线之间设有栅极绝缘层。
  23. 根据权利要求17-22任一项所述的显示面板，其中，所述发光控制信号线和所述第一边框区域数据线之间设有层间绝缘层。
  24. 根据权利要求9-23任一项所述的显示面板，还包括第二平坦化层，其中，所述第二平坦化层覆盖所述第二边框区域数据线。
  25. 根据权利要求9-24任一项所述的显示面板，其中，所述第一边框区域数据线、所述第二边框区域数据线、所述栅线、所述发光控制信号线中至少一个的材料包括金属或合金。
  26. 根据权利要求9-25任一项所述的显示面板，还包括显示单元，其中，所述显示单元包括有机发光二极管。
  27. 根据权利要求26所述的显示面板，还包括隔离柱，其中，所述隔离柱位于所述边框区域内，并围绕所述透光区域设置，所述隔离柱位于所述多条边框区域数据线的靠近所述透光区域的一侧，所述隔离柱构成所述边框区域的内边界。
  28. 根据权利要求27所述的显示面板，其中，所述隔离柱采用金属材料制作。
  29. 根据权利要求28所述的显示面板，其中，所述隔离柱与所述第一边框区域数据线或所述第二边框区域数据线同层设置。
  30. 根据权利要求27-29任一项所述的显示面板，其中，所述隔离柱包括第一子层、第二子层和第三子层，所述第一子层比所述第二子层更靠近所述衬底基板，所述第二子层比所述第三子层更靠近所述衬底基板，所述第二子层的沿着所述透光区域的径向方向的尺寸小于所述第一子层的沿着所述透光区域的径向方向的尺寸，并且所述第二子层的沿着所述透光区域的径向方向的尺寸小于所述第三子层的沿着所述透光区域的径向方向的尺寸。
  31. 根据权利要求30所述的显示面板，其中，所述有机发光二极管包括发光功能层，所述发光功能层包括位于所述隔离柱的远离所述透光区域的第一部分和位于所述隔离柱上的第二部分，所述发光功能层的第一部分和所述 发光功能层的第二部分在所述隔离柱的侧边处断裂。
  32. 根据权利要求1-31任一项所述的显示面板，其中，所述透光区域包括第一透光区域和第二透光区域，所述边框区域栅线包括第二部分，所述边框区域栅线的第二部分位于所述第一透光区域和所述第二透光区域之间，所述边框区域栅线的第二部分与负载电容的第一极板相连，所述负载电容的第二极板与所述负载电容的第一极板相对设置。
  33. 根据权利要求32所述的显示面板，其中，所述负载电容的第二极板与所述边框区域栅线的第二部分部分重叠。
  34. 根据权利要求32或33所述的显示面板，其中，所述边框区域栅线的第二部分与所述负载电容的第一极板为一体结构。
  35. 根据权利要求32-34任一项所述的显示面板，还包括第一电源线，其中，所述第一电源线被配置为提供恒定的电压信号，所述负载电容的第二极板与所述第一电源线相连。
  36. 一种显示装置，包括权利要求1-35任一项所述的显示面板。
PCT/CN2020/081234 2020-03-25 2020-03-25 显示面板和显示装置 WO2021189334A1 (zh)

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