WO2023221747A9 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

Info

Publication number
WO2023221747A9
WO2023221747A9 PCT/CN2023/090332 CN2023090332W WO2023221747A9 WO 2023221747 A9 WO2023221747 A9 WO 2023221747A9 CN 2023090332 W CN2023090332 W CN 2023090332W WO 2023221747 A9 WO2023221747 A9 WO 2023221747A9
Authority
WO
WIPO (PCT)
Prior art keywords
pixel circuit
transistor
node
light
coupled
Prior art date
Application number
PCT/CN2023/090332
Other languages
English (en)
French (fr)
Other versions
WO2023221747A1 (zh
Inventor
曹丹
舒晓青
高文辉
郭永林
肖云升
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023221747A1 publication Critical patent/WO2023221747A1/zh
Publication of WO2023221747A9 publication Critical patent/WO2023221747A9/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED display technology is a technology that uses luminescent materials to emit light driven by current to achieve display.
  • OLED displays are ultra-light, ultra-thin, high brightness, wide viewing angle, low voltage, low power consumption, fast response, high definition, shock-resistant, bendable, low cost, simple process, use less raw materials, high luminous efficiency and temperature range wide advantages.
  • a display substrate includes: a plurality of pixel circuits and a plurality of light-emitting devices; the pixel circuit includes: a driving transistor and a compensation transistor coupled to the driving transistor.
  • the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits.
  • the plurality of light-emitting devices include: a plurality of first light-emitting devices and a plurality of second light-emitting devices.
  • the first pixel circuit is coupled to the first light-emitting device, and the first pixel circuit and the first light-emitting device are arranged at least partially facing each other.
  • the second pixel circuit is coupled to the second light-emitting device; the orthographic projection of the second pixel circuit on the plane of the display substrate does not overlap with the orthographic projection of the second light-emitting device on the plane of the display substrate.
  • the channel width-to-length ratio of the driving transistor in the first pixel circuit is greater than the channel width-to-length ratio of the driving transistor in the second pixel circuit.
  • the channel capacitance of the compensation transistor in the first pixel circuit is greater than the channel capacitance of the compensation transistor in the second pixel circuit.
  • the channel width of the driving transistor in the first pixel circuit is greater than the channel width of the driving transistor in the second pixel circuit.
  • the difference between the channel width of the driving transistor in the first pixel circuit and the channel width of the driving transistor in the second pixel circuit is less than or equal to 0.6 ⁇ m.
  • the ratio of the channel width of the driving transistor in the first pixel circuit to the channel width of the driving transistor in the second pixel circuit is greater than 1 and less than or equal to 1.21.
  • the channel length of the driving transistor in the first pixel circuit is smaller than the channel length of the driving transistor in the second pixel circuit.
  • the difference between the channel length of the driving transistor in the first pixel circuit and the channel length of the driving transistor in the second pixel circuit is less than or equal to 1.4 ⁇ m.
  • the ratio of the channel length of the driving transistor in the first pixel circuit to the channel length of the driving transistor in the second pixel circuit is less than 1 and greater than or equal to 0.94.
  • the channel width of the compensation transistor in the first pixel circuit is greater than the channel width of the compensation transistor in the second pixel circuit.
  • the difference between the channel width of the compensation transistor in the first pixel circuit and the channel width of the compensation transistor in the second pixel circuit is less than or equal to 0.3 ⁇ m.
  • the ratio of the channel width of the compensation transistor in the first pixel circuit to the channel width of the compensation transistor in the second pixel circuit is greater than 1 and less than or equal to 1.14.
  • the channel length of the compensation transistor in the first pixel circuit is greater than the channel length of the compensation transistor in the second pixel circuit.
  • the difference between the channel length of the compensation transistor in the first pixel circuit and the channel length of the compensation transistor in the second pixel circuit is less than or equal to 0.8 ⁇ m.
  • the ratio of the channel length of the compensation transistor in the first pixel circuit to the channel length of the compensation transistor in the second pixel circuit is greater than 1 and less than or equal to 1.15.
  • the display substrate further includes: a plurality of leads.
  • the second pixel circuit and the second light-emitting device are coupled through wires.
  • the channel width-to-length ratio of the driving transistor in the second pixel circuit is negatively correlated with the length ratio of the leads connected to the second pixel circuit. And/or, there is a negative correlation between the channel capacitance of the compensation transistor in the second pixel circuit and the length ratio of the lead connected to the second pixel circuit.
  • the pixel circuit further includes: a first reset transistor, a first emission control transistor, a second emission control transistor, a second reset transistor, a switching transistor, and a storage capacitor.
  • the gate of the first reset transistor is coupled to the first reset signal line, the first electrode of the first reset transistor is coupled to the first initial signal line, and the second electrode of the first reset transistor is coupled to the first reset signal line.
  • Node coupled; the first reset transistor is configured to transmit the first initial signal provided by the first initial signal line to the first reset signal under the control of the first reset signal provided by the first reset signal line.
  • the gate of the switching transistor is coupled to the scan signal line, the first pole of the switching transistor is coupled to the data signal line, and the second pole of the switching transistor is coupled to the second node; the switching transistor is configured To transmit the data signal provided by the data signal line to the second node under the control of the scanning signal provided by the scanning signal line.
  • the gate of the first light-emitting control transistor is coupled to the enable signal line, the first electrode of the first light-emitting control transistor is coupled to the first voltage signal line, and the second electrode of the first light-emitting control transistor is coupled to the enable signal line.
  • the second node is coupled; the first light emitting control transistor is configured to, under the control of the enable signal provided by the enable signal line, convert the first voltage provided by the first voltage signal line The signal is transmitted to the second node.
  • the gate of the driving transistor is coupled to the first node, the first pole of the driving transistor is coupled to the second node, and the second pole of the driving transistor is coupled to the third node;
  • the drive transistor is configured to transmit the electrical signal of the second node to the third node under the control of the electrical signal of the first node.
  • the gate electrode of the compensation transistor is coupled to the first node, the first electrode of the compensation transistor is coupled to the third node, and the second electrode of the compensation transistor is coupled to the scan signal line;
  • the compensation transistor is configured to transmit an electrical signal of the third node to the first node under control of the scan signal.
  • a first pole of the storage capacitor is coupled to the first voltage signal line, and a second pole of the storage capacitor is coupled to the first node.
  • the gate of the second light-emitting control transistor is coupled to the enable signal line, the first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to the enable signal line.
  • the fourth node is coupled; the second light emitting control transistor is configured to transmit the electrical signal of the third node to the fourth node under the control of the enable signal.
  • the gate of the second reset transistor is coupled to the second reset signal line, the first electrode of the second reset transistor is coupled to the second initial signal line, and the second electrode of the second reset transistor is coupled to the second reset signal line.
  • the fourth node is coupled; the second reset transistor is configured to transmit the second initial signal provided by the second initial signal line to the second reset transistor under the control of the second reset signal provided by the second reset signal line. Describe the fourth node.
  • a display device which includes: the display substrate according to any one of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments of the present invention.
  • Figure 2 is a structural diagram of a display substrate according to some embodiments of the present invention.
  • Figure 3 is a structural diagram of a pixel circuit according to some embodiments of the present invention.
  • Figure 4 is a structural diagram of another display substrate according to some embodiments of the present invention.
  • Figure 5a is a structural diagram of another display device according to some embodiments of the present invention.
  • Figure 5b is a structural diagram of another display substrate according to some embodiments of the present invention.
  • Figure 5c is a structural diagram of another display device according to some embodiments of the present invention.
  • Figure 5d is a structural diagram of another display device according to some embodiments of the present invention.
  • Figure 6a is a partial structural diagram of a display substrate in an implementation manner
  • Figure 6b is a graph of driving current, fourth node voltage and enable signal versus time in one implementation
  • Figure 7a is a partial structural view of a display substrate according to some embodiments of the present invention.
  • Figure 7b is a partial structural view of a display substrate according to some embodiments of the present invention.
  • Figure 8a is a partial structural diagram of a driving transistor according to some embodiments of the present invention.
  • Figure 8b is a partial structural diagram of another driving transistor according to some embodiments of the present invention.
  • Figure 9 is a partial structural diagram of another driving transistor according to some embodiments of the present invention.
  • Figure 10 is a partial structural diagram of another driving transistor according to some embodiments of the present invention.
  • Figure 11a is a partial structural diagram of a compensation transistor according to some embodiments of the present invention.
  • Figure 11b is a partial structural diagram of another compensation transistor according to some embodiments of the present invention.
  • Figure 12 is a partial structural diagram of another compensation transistor according to some embodiments of the present invention.
  • Figure 13 is a partial structural diagram of yet another compensation transistor according to some embodiments of the present invention.
  • Figure 14a is a graph of driving current, first node voltage and enable signal versus time in the first pixel circuit and the second pixel circuit in a display substrate according to some embodiments of the present invention
  • Figure 14b is a graph of driving current, first node voltage and enable signal versus time in the first pixel circuit and the second pixel circuit in another display substrate according to some embodiments of the present invention
  • Figure 14c is a graph of driving current, first node voltage and enable signal versus time in the first pixel circuit and the second pixel circuit in another display substrate according to some embodiments of the present invention.
  • Figure 14d is a graph of driving current, first node voltage and enable signal versus time in the first pixel circuit and the second pixel circuit in another display substrate according to some embodiments of the present invention
  • Figure 15a is a graph illustrating the current difference of second sub-pixels of different colors in a display substrate and the channel variation of the second pixel circuit in some embodiments of the present invention
  • Figure 15b is a graph illustrating the current difference of second sub-pixels of different colors in another display substrate and the channel variation of the second pixel circuit in some embodiments of the present invention
  • Figure 15c is a graph illustrating the current difference of second sub-pixels of different colors in another display substrate and the channel variation of the second pixel circuit according to some embodiments of the present invention.
  • Figure 15d is a graph illustrating the current difference of second sub-pixels of different colors in another display substrate and the channel variation of the second pixel circuit according to some embodiments of the present invention.
  • Figure 16 is a diagram showing calculation results of current differences of second sub-pixels of different colors when the preset gray level is L255 in some embodiments of the present invention.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used can be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short), or other devices with the same characteristics.
  • the switching device is described in the embodiments of the present invention by taking a thin film transistor as an example.
  • the first electrode of each transistor used is one of the source electrode and the drain electrode
  • the second electrode of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first and third electrodes of the transistor in the embodiment of the present invention The two poles can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the transistor is an N-type transistor
  • the first electrode of the transistor is the drain electrode
  • the second electrode is the source electrode.
  • nodes such as the first node and the second node do not represent actual existing components, but represent the meeting points of relevant couplings in the circuit diagram. That is to say, these nodes are formed by the relevant couplings in the circuit diagram.
  • the P-type transistor can be turned on under the control of a low-level signal
  • the N-type transistor can be turned on under the control of a high-level signal
  • some embodiments of the present invention provide a display device 1000.
  • the above-described display device 1000 may be any display device that displays text or images, whether moving (eg, video) or stationary (eg, still images). More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • the display device 1000 includes: a frame, a display driver IC (Integrated Circuit), and other electronic accessories.
  • IC Integrated Circuit
  • the above-mentioned display device 1000 further includes: a display substrate 100 .
  • the display substrate 100 includes: a substrate, a pixel circuit layer, and a light-emitting device layer that are stacked in sequence.
  • the above-mentioned substrate may be a flexible substrate or a rigid substrate.
  • the material of the substrate may be dimethylsiloxane, PI (Polyimide, polyimide), PET (Polyethylene terephthalate, polyethylene terephthalate) ) and other highly elastic materials.
  • the material of the substrate may be glass or the like.
  • the pixel circuit layer includes a plurality of pixel circuits 10 and the light-emitting device layer 20 includes a plurality of light-emitting devices 20 . That is, as shown in FIG. 2 , the display substrate 100 may include a plurality of pixel circuits 10 and a plurality of light emitting devices 20 .
  • the above-mentioned pixel circuits 10 may be arranged in an array.
  • the pixel circuit 10 may include a circuit composed of some transistors and some capacitors.
  • the above-mentioned light-emitting device 20 may be an OLED light-emitting device.
  • the light-emitting device 20 may include a first electrode, a light-emitting functional layer, a second electrode, etc. that are stacked in sequence.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light-emitting functional layer may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • the first electrode may be one of the anode and the cathode
  • the second electrode may be the other of the anode and the cathode, which is not limited by the present invention.
  • the first electrode is an anode and the second electrode is a cathode.
  • the above-mentioned plurality of pixel circuits 10 and the plurality of light-emitting devices 20 may be coupled in one-to-one correspondence.
  • one pixel circuit 10 can be coupled with multiple light-emitting devices 20 , or multiple pixel circuits 10 can be coupled with one light-emitting device 20 .
  • the present invention schematically explains the structure of the display substrate 100 by taking the coupling of a pixel circuit 10 and a light-emitting device 20 as an example.
  • the circuit in the pixel circuit 10 can generate a driving signal (for example, a driving current).
  • a driving signal for example, a driving current.
  • Each light-emitting device 20 can emit light under the driving action of the driving signal generated by the pixel circuit 10 to which it belongs.
  • the light emitted by the multiple light-emitting devices 20 cooperates with each other, so that the display substrate 100 and the display device 1000 realize the display function.
  • the pixel circuit 10 may have a variety of structures, and the configuration may be selected according to actual needs.
  • the structure of the pixel circuit may include a "2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structure.
  • T represents a transistor
  • the number in front of “T” represents the number of transistors
  • C represents a storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the structure and working process of the pixel circuit 10 will be schematically explained below with reference to FIG. 3 , taking the structure of the pixel circuit 10 as “7T1C” as an example. It should be noted that there may also be other coupling relationships between the seven transistors and one storage capacitor included in the pixel circuit 10, and are not limited to the coupling relationship shown in this example.
  • the display substrate 100 further includes a first initial signal line Vinit1 for transmitting a first initial signal, a second initial signal line Vinit2 for transmitting a second initial signal, and a scanning signal line for transmitting a scanning signal.
  • a first initial signal line Vinit1 for transmitting a first initial signal
  • a second initial signal line Vinit2 for transmitting a second initial signal
  • a scanning signal line for transmitting a scanning signal.
  • the first reset signal line Reset1 for transmitting the first reset signal
  • the second reset signal line Reset2 for transmitting the second reset signal
  • the enable signal line EM for transmitting the enable signal
  • the data signal for transmitting
  • the data line Data the voltage signal line VDD used to transmit the first voltage signal
  • the common voltage signal line VSS used to transmit the common voltage signal.
  • the pixel circuit 10 includes: a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a switching transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second Reset transistor T7 and storage capacitor Cst.
  • the gate of the first reset transistor T1 is coupled to the first reset signal line Reset1, the first electrode of the first reset transistor T1 is coupled to the first initial signal line Vinit1, and the second stage of the first reset transistor T1 coupled to the first node N1.
  • the first reset transistor T1 is configured to transmit the first initial signal to the first node N1 under the control of the first initial signal.
  • the first reset transistor T1 is turned on and transmits the first initial signal from the first initial signal line Vinit1 to the first node N1. N1 is reset.
  • the “operating level” in the present invention refers to the level that enables the transistor to turn on.
  • the “operating level” is high level.
  • the transistor is a P-type transistor, the “operating level” is low level.
  • the first plate of the storage capacitor Cst is coupled to the first voltage signal line VDD, and the second plate of the storage capacitor Cst is coupled to the first node N1.
  • the gate of the switching transistor T4 is coupled to the scanning signal line Gate
  • the first pole of the switching transistor T4 is coupled to the data signal line Data
  • the second stage of the switching transistor T4 is coupled to the second node N2.
  • the switching transistor T4 is configured to transmit the data signal to the second node N2 under the control of the scan signal.
  • the switching transistor T4 is turned on to transmit the data signal from the data signal line Data to the second node N2.
  • the gate of the driving transistor T3 is coupled to the first node N1
  • the first pole of the driving transistor T3 is coupled to the second node N2
  • the second stage of the driving transistor T3 is coupled to the third node N3.
  • the driving transistor T3 is configured to transmit the electrical signal of the second node N2 to the third node N3 under the control of the electrical signal of the first node N1.
  • the driving transistor T3 is turned on to transmit the electrical signal (for example, a data signal) from the second node N2 to the third node N3.
  • the electrical signal for example, a data signal
  • the gate of the compensation transistor T2 is coupled to the scanning signal line Gate
  • the first electrode of the compensation transistor T2 is coupled to the third node N3
  • the second stage of the compensation transistor T2 is coupled to the first node N1.
  • the compensation transistor T2 is configured to, under the control of the scan signal, transmit the electrical signal of the third node N3 to the first node N1, compensate the threshold voltage of the driving transistor T3, and compensate the storage device coupled to the first node N1. Capacitor Cst is charged.
  • the compensation transistor T2 is turned on to transmit the electrical signal (for example, a data signal) from the third node N3 to the first node N1.
  • the electrical signal for example, a data signal
  • the gate of the second reset transistor T7 is coupled to the second reset signal line Reset2, the first electrode of the second reset transistor T7 is coupled to the second initial signal line Vinit2, and the second stage of the second reset transistor T7 coupled to the fourth node N4.
  • the second reset transistor T7 is configured to transmit the second initial signal to the fourth node N4 under the control of the second initial signal.
  • the second reset transistor T7 is turned on and transmits the second initial signal from the second initial signal line Vinit2 to the fourth node N4. N4 is reset.
  • the gate of the first light-emitting control transistor T5 is coupled to the enable signal line EM
  • the first electrode of the first light-emitting control transistor T5 is coupled to the first voltage signal line VDD
  • the first light-emitting control transistor T5 has a gate electrode coupled to the enable signal line EM.
  • the second level is coupled to the second node N2.
  • the first light emission control transistor T5 is configured to transmit the first voltage signal to the second node N2 under the control of the enable signal.
  • the first light emitting control transistor T5 when the level of the enable signal is the working level, the first light emitting control transistor T5 is turned on and transmits the first voltage signal from the first voltage signal line VDD to the second node N2.
  • the gate of the second light-emitting control transistor T6 is coupled to the enable signal line EM
  • the first electrode of the second light-emitting control transistor T6 is coupled to the third node N3
  • the second stage of the second light-emitting control transistor T6 coupled to the fourth node N4.
  • the second light emission control transistor T6 is configured to transmit the electrical signal of the third node N3 to the fourth node N4 under the control of the enable signal.
  • the second light emitting control transistor T6 is turned on and transmits the electrical signal (eg, the driving signal) from the third node N3 to the fourth node N4.
  • the electrical signal eg, the driving signal
  • one end of the light-emitting device 20 is coupled to the fourth node N4, and the other end of the light-emitting device 20 is coupled to the common voltage signal line VSS.
  • the light-emitting device 20 emits light under the action of the electrical signal of the fourth node N4 and the common voltage signal provided by the common voltage signal line VSS.
  • the working process of the pixel circuit 10 includes a reset phase, a data writing and compensation phase, and a light emitting phase in sequence.
  • the first reset transistor T1 under the control of the reset signal, the first reset transistor T1 is turned on, transmits the first initial signal to the first node N1, and resets the first node N1. Since the first node N1 is coupled to the storage capacitor Cst, the gate of the driving transistor T3 and the second pole of the compensation transistor T2, when the first node N1 is reset, the storage capacitor Cst and the gate of the driving transistor T3 can be reset. pole and the second pole of compensation transistor T2 to reset. Wherein, the driving transistor T3 can be turned on under the control of the first initial signal.
  • the switching transistor T4 and the compensation transistor T2 are turned on at the same time under the control of the scanning signal.
  • the switching transistor T4 transmits the data signal to the second node N2, and the driving transistor T3 is turned on under the control of the first node N1 to transmit the data signal from the second node N2 to the third node N3.
  • the compensation transistor T2 transmits the data signal from the third node N3 to the first node N1, and charges the driving transistor T3 until the driving transistor T3 is in an off state, thereby completing the compensation for the threshold voltage of the driving transistor T3.
  • the second reset transistor T7 transmits the second start signal to the fourth node N4. Since the fourth node N4 is coupled to the first electrode of the light-emitting device 20, when the fourth node N4 is reset, the first electrode of the light-emitting device 20 can be reset.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on at the same time under the control of the enable signal.
  • the first light emission control transistor T5 transmits the first voltage signal to the second node N2.
  • the driving transistor T3 transmits the electrical signal from the second node N2 to the third node N3.
  • the second light emission control transistor T6 transmits the voltage signal from the third node N3 to the fourth node N4.
  • the light-emitting device 20 emits light under the action of the electrical signal from the fourth node N4 and the common voltage signal from the common voltage line VSS.
  • the fourth node N4 of the pixel circuit 10 needs to be precharged for a certain period of time in order to reach the preset light-emitting voltage, and the light-emitting device 20 can It emits light under the action of preset lighting voltage and common voltage signal.
  • the above-mentioned pixel circuit layer includes: a semiconductor layer PO, a gate conductive layer GT and a source-drain conductive layer SD sequentially stacked on one side of the substrate.
  • FIG. 4 only illustrates a partial pattern of the semiconductor layer PO, a partial pattern of the gate conductive layer GT, and a partial pattern of the source-drain conductive layer SD.
  • the above-mentioned source-drain conductive layer SD can be one film layer disposed on one side of the gate conductive layer GT, or two layers disposed on one side of the gate conductive layer GT.
  • the specific selection can be made according to actual needs. , the present invention does not limit this.
  • the material of the semiconductor layer PO may include amorphous silicon, monocrystalline silicon, polycrystalline silicon and other materials, and may also include metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the materials of the gate conductive layer GT and the source-drain conductive layer SD are both conductive materials.
  • the above-mentioned conductive material may be a metal material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.
  • a first insulating layer is provided between the semiconductor layer PO and the gate conductive layer GT.
  • the first insulating layer is used to isolate the semiconductor layer PO and the gate conductive layer GT to avoid short circuit.
  • a second insulating layer is provided between the gate conductive layer GT and the source-drain conductive layer SD. The second insulating layer is used to isolate the gate conductive layer GT and the source-drain conductive layer SD to avoid short circuit.
  • the materials of the first insulating layer and the second insulating layer may be silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the orthographic projection of the semiconductor layer PO on the substrate overlaps with the orthographic projection of the gate conductive layer GT on the substrate.
  • the gate conductive layer GT can be used as a mask to perform doping treatment on the semiconductor layer PO, so that the semiconductor layer PO is not covered by the gate conductive layer GT. part to form a conductor, which may constitute the first pole or the second pole of part of the transistor, so that the part of the semiconductor layer PO covered by the gate conductive layer GT constitutes the channel part of part of the transistor, in the gate conductive layer GT, and
  • the overlapping portions of the semiconductor layers PO constitute the gate pattern of part of the transistor, and the gate pattern constitutes the gate electrode of the transistor.
  • the channel portion has a channel length and a channel width.
  • the channel length of the channel portion refers to the size of the portion of the channel portion located between the first pole and the second pole of the transistor along the connecting direction of the first pole and the second pole of the transistor.
  • the channel width of the channel portion refers to the size of the channel portion in a direction perpendicular to the connecting direction of the first pole and the second pole of the transistor.
  • the display substrate 100 has a display area A and a frame area B. As shown in FIG. 5a , the display substrate 100 has a display area A and a frame area B. As shown in FIG. 5a , the display substrate 100 has a display area A and a frame area B. As shown in FIG. 5a , the display substrate 100 has a display area A and a frame area B. As shown in FIG. 5a , the display substrate 100 has a display area A and a frame area B.
  • the above-mentioned display A refers to an area of the display substrate 100 used to display a screen.
  • the display area A may have a variety of shapes, and may be selected and set according to actual needs, and the present invention does not limit this.
  • the shape of the display area A may be a rectangle, an approximately rectangle, a circle, an ellipse, etc.
  • the approximate rectangle is a rectangle in a non-strict sense, and its four inner corners may be rounded corners, for example, or a certain side may not be a straight line, for example.
  • the present invention takes the shape of the display area A as a rectangle as an example.
  • multiple pixel circuits 10 and multiple light-emitting devices 20 are disposed in the display area A.
  • the light-emitting devices 20 can be evenly distributed in the display area A, thereby ensuring the uniformity of the images displayed by the display substrate 100 and the display device 1000 to a certain extent.
  • the frame area B may be arranged around the display area A.
  • the part of the display substrate 100 located in the display area A there are many ways to set the part of the display substrate 100 located in the display area A.
  • at least one of the shift register GOA, the fan-out unit Fanout and the optical element can be set.
  • the optical element such as a camera, an infrared sensor or a fingerprint sensor
  • specific settings can be made according to actual needs, and the present invention does not limit this.
  • the display substrate 100 further includes: at least one shift register GOA located in the display area A. At least one shift register GOA is located between the substrate and the light-emitting device layer, and the orthographic projection of the at least one shift register GOA on the substrate does not overlap with the orthographic projection of the pixel circuit layer on the substrate.
  • the display area A is provided with one or more shift register circuits GOA.
  • the shift register GOA may be located in the display substrate 100 close to the boundary line of the display area A and the frame area B.
  • a plurality of shift registers GOA may be arranged along the second direction Y on both sides of the display area A along the first direction X.
  • the above “no overlap” means that at least one shift register GOA and the pixel circuit 10 in the pixel circuit layer do not overlap each other along the thickness direction of the display substrate 100 .
  • the above-mentioned at least one shift register GOA and the pixel circuit layer are both located between the substrate and the light-emitting device layer, and the orthographic projections on the substrate do not overlap, the above-mentioned at least one shift register can be formed in the same set of preparation processes.
  • the register GOA and the pixel circuit 10 in the pixel circuit layer are both located between the substrate and the light-emitting device layer, and the orthographic projections on the substrate do not overlap.
  • the shift register GOA may include a first shift register, and the first shift register may be electrically connected to the scanning signal line Gate, and provide scanning signals to the pixel circuit 10 electrically connected to the scanning signal line Gate.
  • the shift register circuit GOA may also include a second shift register, and the second shift register may be electrically connected to the enable signal line EM to provide an enable signal for the pixel circuit 10 electrically connected to the enable signal line EM.
  • arranging the shift register GOA in the display area A can reduce the number of shift registers GOA arranged in the frame area B, thereby reducing the area of the frame area B in the display substrate 100, thereby increasing the display area.
  • the area ratio of area A in the display substrate 100 is further beneficial to realizing the narrow frame design of the display substrate 100 and the display device 1000 .
  • the orthographic projection of the shift register GOA on the substrate does not overlap with the orthographic projection of the above-mentioned pixel circuit layer on the substrate, , and the area of the display area A is certain, so that the area occupied by at least one shift register circuit GOA will compress the area occupied by multiple pixel circuits 10 in the pixel circuit layer, and the area occupied by the multiple pixel circuits 10 If the area occupied by the multiple light-emitting devices 20 of the driven light-emitting device layer is not reduced, misalignment will occur between part of the pixel circuit 10 and the light-emitting devices 20 it drives. That is to say, this part of the display substrate 100 The pixel circuit 10 and the light-emitting device 20 it drives are not arranged facing each other, or the distance between the part of the pixel circuit 10 and the light-emitting device 20 it drives is relatively far.
  • the shift register GOA can also be set in the border area B.
  • the display substrate 100 further includes: a fan-out unit Fanout located in the display area A.
  • the fan-out unit Fanout is located between the substrate and the light-emitting device layer, and the orthographic projection of the fan-out unit Fanout on the substrate does not overlap with the orthographic projection of the pixel circuit layer on the substrate.
  • the above-mentioned “no overlap” means that the fan-out unit Fanout and the pixel circuit 10 in the pixel circuit layer do not overlap each other in the thickness direction of the display substrate 100 .
  • the fan-out unit Fanout may be located in an area in the display area A close to the display driver IC.
  • the fan-out unit Fanout and the pixel circuit layer are located between the substrate and the light-emitting device layer, and there is no overlap in the orthographic projection on the substrate, the fan-out unit Fanout and the pixel circuit can be formed in the same set of preparation processes. Pixel circuit 10 in layer.
  • the fan-out unit Fanout may be coupled with the display driving IC of the display device 1000 .
  • the fan-out unit Fanout may include a data fan-out line, a first voltage fan-out line, etc.
  • the display driver IC may provide a data signal for a data fan-out line of the fan-out unit Fanout, a first voltage signal for a first voltage fan-out line of the fan-out unit Fanout, and so on.
  • the data fan-out line can be coupled to the data signal line Data, and can thereby transmit the data signal to the pixel circuit 10 .
  • the first voltage fan-out line may be coupled to the first voltage signal line VDD, thereby transmitting the first voltage signal to the pixel circuit 10 .
  • arranging the fan-out unit Fanout in the display area A can save the area of the frame area B occupied by it, thereby reducing the area of the frame area B in the display substrate 100, and thereby increasing the area of the display area A.
  • the area ratio in the display substrate 100 is further conducive to realizing the narrow frame design of the display substrate 100 and the display device 1000 .
  • the display The area of area A is certain, so that the area occupied by the fan-out unit Fanout will compress the area occupied by the multiple pixel circuits 10 in the pixel circuit layer, and the area occupied by the multiple light-emitting devices 20 in the light-emitting device layer If the area is not reduced, the part of the pixel circuit 10 and the light-emitting device 20 it drives will be misaligned. That is to say, the part of the pixel circuit 10 in the display substrate 100 and the light-emitting device 20 it drives are not facing each other. or the distance between this part of the pixel circuit 10 and the light-emitting device 20 it drives is relatively long.
  • the fan-out unit Fanout may also be located in the frame area B of the display substrate 100 .
  • the display substrate 100 further includes an optical element region OC and an optical element 200 .
  • the orthographic projection of the optical element 200 on the plane where the display substrate 100 is located is located in the optical element area OC of the display substrate 100 .
  • the light transmittance of the area of the display substrate 100 located in the optical element area OC is greater than the light transmittance of the area of the display substrate 100 located in the display area A.
  • the optical element area OC can also be used to display a picture.
  • the above-mentioned optical element 200 can be a camera, a fingerprint recognition sensor, an infrared sensor, etc.
  • the optical element 200 can collect light, thus ensuring that the optical element 200 can work normally, and also increasing the area ratio of the area used to display the image in the display substrate 100 (for example, the above-mentioned display area A) in the display substrate 100 , and thus It is beneficial to realize the full-screen design of the display substrate 100 and the display device 1000 .
  • the density of the light-emitting devices 20 in the optical element area OC is the same as the density of all the light-emitting devices 20 in the display area A, and in order to ensure that the optical element 200 can receive enough light, in the area of the display substrate 100 located in the optical element area OC, only a small number of pixel circuits 10 or no pixel circuits 10 can be provided, thus making the number of light-emitting devices 20 located in the optical element area OC larger than that in the optical element area OC.
  • the distance between the light emitting devices 20 is relatively long.
  • the shift register or fan-out unit of the display substrate is provided in the display area, or if only a few or no pixel circuits are provided in the optical element area of the display substrate, some pixel circuits 10' will appear and emit light accordingly.
  • the devices 20' are not arranged facing each other, and the distance between this part of the pixel circuit 10' and its corresponding light-emitting device 20' is relatively far, as shown in Figure 6a. Therefore, as shown in FIG. 6b, during the light-emitting phase of the pixel circuit, the load of the fourth node N4 in the above-mentioned partial pixel circuit 10' is relatively large (relative to the pixel circuit and the light-emitting device that are arranged oppositely).
  • the four-node N4 is precharged to the preset light-emitting voltage for a long time, which in turn causes the driving current of the light-emitting device 20' in this part of the pixel circuit 10' to be smaller, so that the light-emitting device 20' of this part of the pixel circuit 10' turns on slowly or
  • the luminous brightness is low, which makes the display substrate and the display device prone to uneven luminescence as a whole. This phenomenon is particularly obvious in the case of low grayscale.
  • a plurality of pixel circuits 10 include a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12.
  • the above-mentioned plurality of light-emitting devices 20 include: a plurality of first light-emitting devices 21 and a plurality of second light-emitting devices 22.
  • the first pixel circuit 11 is coupled to the first light emitting device 21 .
  • the first pixel circuit 11 is at least partially disposed facing the first light-emitting device 21 .
  • the above-mentioned "at least partially facing arrangement” refers to the orthogonal projection of the first pixel circuit 11 on the plane of the display substrate 100 and the orthogonal projection of the first light-emitting device 21 driven by it on the plane of the display substrate 100 . Projection, partial or complete overlap.
  • Adopting the above setting method can make the load of the fourth node N4 in the first pixel circuit 11 smaller, and then during the light-emitting phase, the charging of the fourth node N4 can be completed in a shorter time, thus making the fourth node N4 smaller.
  • the first light-emitting device 21 can be turned on quickly, and can emit light consistent with the preset gray scale at the preset voltage, thereby slowing down or even avoiding the occurrence of uneven brightness in the display substrate 100 and the display device 1000 Phenomenon.
  • FIG. 2 only illustrates the relative positional relationship of the first pixel circuit 11, the second pixel circuit 12, the first light-emitting device 21, the second light-emitting device 22 and the shift register GOA in the display substrate 100. , the connection relationship between the above structures is not illustrated.
  • the second pixel circuit 12 is coupled to the second light emitting device 22 .
  • the orthographic projection of the second pixel circuit 12 on the plane of the display substrate 100 does not overlap with the orthographic projection of the second light-emitting device 22 it drives on the plane of the display substrate 100 .
  • the second pixel circuit 12 and the second light-emitting device 22 it drives are designed to be offset, and there is no facing portion between them. There is no overlap between the boundary line of the orthographic projection of the second pixel circuit 12 on the plane of the display substrate 100 and the boundary line of the orthographic projection of the driven second light-emitting device 22 on the plane of the display substrate 100 .
  • the display area A of the display substrate 100 includes a shift register GOA located between the substrate and the pixel circuit layer, and/or a fan-out unit Fanout, and/or the display area A includes an optical element area OC.
  • the second pixel circuit 12 is generally located close to the area where the above-mentioned shift register GOA, and/or the fan-out unit Fanout, and/or the optical element area OC is located.
  • the display substrate 100 shown in FIG. 2 includes the shift register GOA located in the display area A
  • the second pixel circuit 12 is located in an area close to the boundary line between the frame area B and the display area A.
  • the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11 is greater than the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 .
  • FIG. 9( a ) illustrates a partial structural diagram of the driving transistor T3 in the first pixel circuit 11
  • FIG. 9( b ) illustrates a partial structural diagram of the driving transistor T3 in the second pixel circuit 12 .
  • the channel width-to-length ratio of the driving transistor T3 refers to the ratio of the channel width of the channel portion of the driving transistor T3 to the length of the channel portion.
  • width-to-length ratio of a transistor is related to the on-state current when the transistor is turned on. The greater the width-to-length ratio of a transistor, the greater its corresponding on-state current.
  • the driving transistor in the second pixel circuit 12 since the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 is smaller than the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11, the driving transistor in the second pixel circuit 12 The on-state current of T3 is smaller than the on-state current of the driving transistor T3 in the first pixel circuit 11. Therefore, during the data writing and compensation stages of the pixel circuit, the driving transistor T3 in the second pixel circuit 12 is connected by the compensation transistor T2. The charging of the first node N1 is insufficient. After the charging is completed, the potential of the first node N1 in the second pixel circuit 12 is lower than the potential of the first node N1 of the first pixel circuit 11.
  • the driving transistor T3 controlled by the first node N1 is more fully turned on, thereby causing the starting value of the driving current passing through the driving transistor T3 of the second pixel circuit 12
  • the starting value of the driving current here refers to the size of the driving current when the value of the driving current tends to be stable, such as the size of the driving current corresponding to t1 or t2 in Figure 14a of the present invention
  • the driving current (the driving current here, refers to (the average value of the driving current in a light-emitting stage) increases, so that the luminous brightness of the second light-emitting device 22 is improved, and thus the second light-emitting device 22 and the first light-emitting device 21 can be
  • the channel capacitance of the compensation transistor T2 in the first pixel circuit 11 is greater than the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 .
  • the channel capacitance of the compensation transistor T2 refers to the capacitance of the capacitor formed by the channel portion of the compensation transistor T2 and the gate of the compensation transistor T2.
  • the gate of the compensation transistor T2 and the scanning signal line Gate have an integrated structure.
  • the size of the channel area is the size of the channel capacitor of the channel portion. Therefore, the larger the channel area, the larger the capacitance of the channel capacitor in the channel portion.
  • the compensation transistor T2 when the compensation transistor T2 is turned off, the level of the scanning signal transmitted by the scanning signal line Gate changes from low level to high level, that is to say, the gate voltage of the compensation transistor T2 increases. In turn, the voltage of the second pole of the compensation transistor T2 connected to the first node N1 will also increase accordingly.
  • the second pixel circuit 12 Since the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is smaller than the channel capacitance of the compensation transistor T2 in the first pixel circuit 11, when the gate voltage of the compensation transistor T2 increases, the second pixel circuit 12 The voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11 is smaller than the voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11, because the channel portion of the compensation transistor T2 passes through the second voltage of the compensation transistor T2.
  • the pole is connected to the first node N1, that is, the voltage increase of the first node N1 in the second pixel circuit 12 is smaller than the voltage increase of the first node N1 in the first pixel circuit 11, that is, the second pixel circuit
  • the potential of the first node N1 of 12 is less affected by the channel capacitor of its corresponding compensation transistor T2, and the potential of the first node N1 in the second pixel circuit 12 is lower than the potential of the first node N1 in the first pixel circuit 11 , thus making the driving transistor T3 of the second pixel circuit 12 controlled by the first node N1 more fully conductive during the light-emitting phase, thereby making the starting value of the driving current through the driving transistor T3 of the second pixel circuit 12 larger.
  • the driving current here refers to a The average value of the driving current in the light-emitting stage
  • the difference improves the uniformity of the display substrate 100 and the display device 1000 under low grayscale display conditions.
  • the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11 is greater than the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 . Furthermore, the channel capacitance of the compensation transistor T2 in the first pixel circuit 11 is greater than the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 .
  • the channel width to length ratio of the driving transistor T3 in the second pixel circuit 12 is relatively small, The smaller the on-state current of the driving transistor T3 in the second pixel circuit 12 is, therefore, during the data writing and compensation stages of the pixel circuit, the charging of the first node N1 by the driving transistor T3 via the compensation transistor T2 is insufficient, and the charging After completion, the potential of the first node N1 in the second pixel circuit 12 is less than the preset potential value.
  • the compensation transistor T2 when the compensation transistor T2 is turned off, the scanning signal transmitted by the scanning signal line Gate changes from low level to high level, that is to say, the gate voltage of the compensation transistor T2 increases, which in turn causes the compensation transistor T2 to The voltage of the first node N1 connected to the second pole will also increase accordingly.
  • the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is relatively small, when the gate voltage of the compensation transistor T2 increases, the voltage of the second electrode of the compensation transistor T2 increases to a small extent, that is, Therefore, the potential of the first node N1 is less affected by the channel capacitor, the potential increase of the first node N1 in the second pixel circuit 12 is relatively small, and the potential of the first node N1 in the second pixel circuit 12 is low.
  • the driving transistor T3 controlled by the first node N1 is more fully conductive, thereby making the starting value of the driving current through the driving transistor T3 larger, thereby compensating for the above-mentioned precharge time of the fourth node N4.
  • the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the difference in luminous brightness of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray level, and improving the performance of the display substrate 100 and the display device 1000 at low gray levels.
  • the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11 is greater than the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 , the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11
  • the driving transistor T3 and the driving transistor T3 in the second pixel circuit 12 can be set according to actual needs, and the present invention does not limit this.
  • the channel width of the driving transistor T3 in the first pixel circuit 11 is larger than the channel width of the driving transistor T3 in the second pixel circuit 12 .
  • FIG. 9( a ) illustrates a partial structural diagram of the driving transistor T3 in the first pixel circuit 11
  • FIG. 9( b ) illustrates a partial structural diagram of the driving transistor T3 in the second pixel circuit 12 .
  • the shape of the channel of the driving transistor T3 is a polygonal line, and the polygonal channel includes a portion extending along the first direction X and a portion extending along the second direction Y.
  • the channel width of the driving transistor T3 is the size of the widths W31, W32, and W33 of the channel extending in the first direction X, and the width of the channel extending in the second direction Y.
  • the channel width of the driving transistor T3 in the first pixel circuit 11 is set to be larger than the channel width of the driving transistor T3 in the second pixel circuit 12, so that the channel width of the driving transistor T3 in the first pixel circuit 11 is
  • the channel width to length ratio is greater than the channel width to length ratio of the driving transistor T3 in the second pixel circuit 12, so that the on-state current of the driving transistor T3 in the second pixel circuit 12 is smaller. Therefore, in the second pixel circuit 12, the channel width to length ratio is smaller. In 12, the charging of the first node N1 by the driving transistor T3 through the compensation transistor T2 is insufficient.
  • the potential of the first node N1 in the second pixel circuit 12 is smaller than the potential of the first node N1 of the first pixel circuit 11.
  • the driving transistor T3 controlled by the first node N1 is more fully turned on, thereby making the light passing through the second pixel circuit 12
  • the starting value of the driving current of the driving transistor T3 is relatively large, which can compensate for the above-mentioned overall lowering of the driving current value due to the long precharge time of the fourth node N4, so that the driving of the driving transistor T3 by the second pixel circuit 12
  • the current increases, so that the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the difference in luminous brightness of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray scale, thereby improving the performance of the display substrate 100 and the display Device 1000 displays uniformity in low gray
  • the channel width of the driving transistor T3 in the first pixel circuit 11 is greater than the channel width of the driving transistor T3 in the second pixel circuit 12
  • the channel width of the driving transistor T3 in the first pixel circuit 11 The channel length may be the same as the channel length of the driving transistor T3 in the second pixel circuit 12, or may be different.
  • the difference between the channel width of the driving transistor T3 in the first pixel circuit 11 and the channel width of the driving transistor T3 in the second pixel circuit 12 is less than or equal to 0.6 ⁇ m.
  • the difference between the channel width of the driving transistor T3 in the first pixel circuit 11 and the channel width of the driving transistor T3 in the second pixel circuit 12 may be 0.6 ⁇ m, 0.5 ⁇ m, 0.4 ⁇ m, or 0.3 ⁇ m. , 0.2 ⁇ m or 0.1 ⁇ m, etc.
  • the channel width-to-length ratio of the driving transistor T3 of the second pixel circuit 12 is smaller than that of the first pixel circuit 11
  • the channel width-to-length ratio of the driving transistor T3, the on-state current of the driving transistor T3 in the second pixel circuit 12 is smaller than the on-state current of the driving transistor T3 in the first pixel circuit 11. Therefore, in the data writing of the pixel circuit Entering the compensation stage, the charging of the first node N1 by the driving transistor T3 through the compensation transistor T2 in the second pixel circuit 12 is insufficient.
  • the potential of the first node N1 in the second pixel circuit 12 is smaller than that of the first pixel circuit.
  • the driving current of the driving transistor T3 of the pixel circuit 12 increases, so that the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the luminescence of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray level.
  • the brightness difference improves the uniformity of the display substrate 100 and the display device 1000 in low grayscale display conditions.
  • the ratio of the channel width of the driving transistor T3 in the first pixel circuit 11 to the channel width of the driving transistor T3 in the second pixel circuit 12 is greater than 1 and less than or equal to 1.21.
  • the channel width of the driving transistor T3 in the first pixel circuit 11 is 3.5 ⁇ m
  • the channel width of the driving transistor T3 in the second pixel circuit 12 may be 3.4 ⁇ m, 3.3 ⁇ m, or 3.2 ⁇ m. , 3.1 ⁇ m or 2.9 ⁇ m.
  • the ratios of the channel width of the driving transistor T3 in the first pixel circuit 11 to the channel width of the driving transistor T3 in the second pixel circuit 12 are 1.02, 1.06, 1.09, respectively. 1.13, 1.21.
  • the channel length of the driving transistor T3 in the first pixel circuit 11 is greater than the channel length of the driving transistor T3 in the second pixel circuit 12 .
  • FIG. 10( a ) illustrates a partial structural diagram of the driving transistor T3 in the first pixel circuit 11
  • FIG. 10( b ) illustrates a partial structural diagram of the driving transistor T3 in the second pixel circuit 12 .
  • the shape of the channel portion of the driving transistor T3 is a polygonal line, and the polygonal channel portion includes a portion extending along the first direction X and a portion extending along the second direction Y. part.
  • the channel length of the driving transistor T3 is the sum of the lengths L31, L32, and L33 of the three extending portions of the channel extending along the first direction X, and the length of the channel along the first direction X.
  • the channel width-to-length ratio of the driving transistor T3 in the first pixel circuit 11 can be larger than the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12.
  • the driving transistor T3 in the second pixel circuit 12 can The on-state current of the transistor T3 is smaller than the on-state current of the driving transistor T3 in the first pixel circuit 11. Therefore, during the data writing and compensation stages of the pixel circuit, the driving transistor T3 in the second pixel circuit 12 is compensated by the compensation transistor T2.
  • the charging of the first node N1 is insufficient. After the charging is completed, the potential of the first node N1 in the second pixel circuit 12 is smaller than the potential of the first node N1 of the first pixel circuit 11.
  • the driving transistor T3 controlled by the first node N1 is more fully turned on, thereby causing the starting value of the driving current passing through the driving transistor T3 of the second pixel circuit 12 is larger, which can compensate for the above-mentioned overall lowering of the driving current value due to the longer precharge time of the fourth node N4, thereby increasing the driving current through the driving transistor T3 of the second pixel circuit 12, so that the second light-emitting device 22
  • the luminous brightness is improved, thereby reducing the difference in luminous brightness of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray scale, and improving the uniformity of the display substrate 100 and the display device 1000 under low gray scale display conditions. sex.
  • the channel width may be the same as the channel width of the driving transistor T3 in the second pixel circuit 12, or may be different.
  • the difference between the channel length of the driving transistor T3 in the first pixel circuit 11 and the channel length of the driving transistor T3 in the second pixel circuit 12 is less than or equal to 1.4 ⁇ m.
  • the difference between the channel length of the driving transistor T3 in the first pixel circuit 11 and the channel length of the driving transistor T3 in the second pixel circuit 12 may be 0.4 ⁇ m, 0.7 ⁇ m, 1.0 ⁇ m, or 1.2 ⁇ m. , 1.4 ⁇ m, etc.
  • the channel width to length ratio of the driving transistor T3 of the second pixel circuit 12 is small, thereby making the second pixel
  • the on-state current of the driving transistor T3 of the circuit 12 is small, and the charging of the first node N1 is insufficient, which in turn causes the driving transistor T3 in the second pixel circuit 12 to conduct more fully during the light-emitting phase, so that the voltage through the driving transistor T3
  • the driving current is increased to a certain extent, so that the difference in luminous brightness of the second light-emitting device 22 and that of the first light-emitting device 21 is small or even close to the same, thereby improving the display substrate 100 and the display device 1000 in low grayscale display. Lower uniformity.
  • the ratio of the channel length of the driving transistor T3 in the first pixel circuit 11 to the channel length of the driving transistor T3 in the second pixel circuit 12 is less than 1 and greater than or equal to 0.94.
  • the channel length of the driving transistor T3 in the first pixel circuit 11 is 24 ⁇ m
  • the channel length of the driving transistor T3 in the second pixel circuit 12 may be 24.3 ⁇ m, 24.6 ⁇ m, 24.9 ⁇ m, 25.1 ⁇ m or 25.4 ⁇ m.
  • the ratios of the channel length of the driving transistor T3 in the first pixel circuit 11 to the channel length of the driving transistor T3 in the second pixel circuit 12 are 0.99, 0.98, 0.96, respectively. 0.95, 0.94.
  • the channel width of the compensation transistor T2 in the first pixel circuit 11 is larger than the channel width of the compensation transistor T2 in the second pixel circuit 12 .
  • FIG. 12( a ) illustrates a partial structural diagram of the driving transistor T3 in the first pixel circuit 11
  • FIG. 12( b ) illustrates a partial structural diagram of the driving transistor T3 in the second pixel circuit 12 .
  • compensation transistor T2 is a double-gate transistor. As shown in Figure 11a, the compensation transistor T2 includes a first sub-compensation transistor T21 and a second sub-compensation transistor T22.
  • the channel capacitance of the compensation transistor T2 in the first pixel circuit 11 can be made smaller than the channel capacitance of the compensation transistor T2 in the second pixel circuit 12. Therefore, when the compensation transistor T2 is turned off, The level of the scanning signal transmitted by the scanning signal line Gate changes from low level to high level, that is to say, the gate voltage of the compensation transistor T2 increases, which in turn causes the gate voltage of the compensation transistor T2 connected to the first node N1 to The voltage of the diode will also increase accordingly.
  • the second pixel circuit 12 Since the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is smaller than the channel capacitance of the compensation transistor T2 in the first pixel circuit 11, when the gate voltage of the compensation transistor T2 increases, the second pixel circuit 12 The voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11 is smaller than the voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11, because the channel portion of the compensation transistor T2 passes through the second voltage of the compensation transistor T2.
  • the pole is connected to the first node N1, that is, the voltage increase of the first node N1 in the second pixel circuit 12 is smaller than the voltage increase of the first node N1 in the first pixel circuit 11, that is, the second pixel circuit
  • the potential of the first node N1 of 12 is less affected by the channel capacitor of its corresponding compensation transistor T2, and the potential of the first node N1 in the second pixel circuit 12 is lower than the potential of the first node N1 in the first pixel circuit 11 , thus making the driving transistor T3 of the second pixel circuit 12 controlled by the first node N1 more fully conductive during the light-emitting phase, thereby making the starting value of the driving current through the driving transistor T3 of the second pixel circuit 12 larger.
  • the difference in luminance of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray level can be reduced, and the uniformity of the display substrate 100 and the display device 1000 in low gray level display can be improved.
  • the difference between the channel width of the compensation transistor T2 in the first pixel circuit 11 and the channel width of the compensation transistor T2 in the second pixel circuit 12 is less than or equal to 0.3 ⁇ m.
  • the difference between the channel width of the compensation transistor T2 in the first pixel circuit 11 and the channel width of the compensation transistor T2 in the second pixel circuit 12 may be 0.11 ⁇ m, 0.15 ⁇ m, 0.21 ⁇ m, or 0.27 ⁇ m. or 0.30 ⁇ m.
  • the channel capacitance of the compensation transistor T2 of the second pixel circuit 12 is relatively small. Therefore, when the compensation transistor When T2 is turned off, the gate voltage of the compensation transistor T2 increases, thereby causing the voltage of the second electrode of the compensation transistor T2 connected to the first node N1 to increase accordingly.
  • the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is relatively small, when the gate voltage of the compensation transistor T2 increases, the voltage of the second electrode of the compensation transistor T2 increases to a small extent, that is, So that the potential of the first node N1 is less affected by the channel capacitor, the potential increase of the first node N1 in the second pixel circuit 12 is relatively small, and the potential of the first node N1 in the second pixel circuit 12 is low,
  • the driving transistor T3 controlled by the first node N1 is more fully turned on, which in turn causes the driving current through the driving transistor T3 to be larger, so that the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the
  • the difference in luminance of the second light-emitting device 22 and the first light-emitting device 21 under the same preset gray scale improves the display uniformity of the display substrate 100 and the display device 1000 .
  • the ratio of the channel width of the compensation transistor T2 in the first pixel circuit 11 to the channel width of the compensation transistor T2 in the second pixel circuit 12 is greater than 1 and less than or equal to 1.14.
  • the channel width of the compensation transistor T2 in the first pixel circuit 11 is 2.5 ⁇ m
  • the channel width of the compensation transistor T2 in the second pixel circuit 12 may be 2.2 ⁇ m, 2.3 ⁇ m, or 2.4 ⁇ m.
  • the ratios of the channel width of the compensation transistor T2 in the first pixel circuit 11 to the channel width of the compensation transistor T2 in the second pixel circuit 12 are 1.14, 1.09, and 1.04 respectively.
  • the channel length of the compensation transistor T2 in the first pixel circuit 11 is smaller than the channel length of the compensation transistor T2 in the second pixel circuit 12 .
  • FIG. 13( a ) illustrates a partial structural diagram of the driving transistor T3 in the first pixel circuit 11
  • FIG. 13( b ) illustrates a partial structural diagram of the driving transistor T3 in the second pixel circuit 12 .
  • the compensation transistor in the first pixel circuit 11 when the channel width of the compensation transistor T2 in the first pixel circuit 11 is the same as the channel width of the compensation transistor T2 in the second pixel circuit 12, the compensation transistor in the first pixel circuit 11
  • the channel capacitance of T2 is smaller than the channel capacitance of the compensation transistor T2 in the second pixel circuit 12. Therefore, at the moment when the compensation transistor T2 is turned off, the gate voltage of the compensation transistor T2 increases, thereby causing the connection with the first node N1
  • the voltage of the second pole of the connected compensation transistor T2 will also increase accordingly.
  • the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is relatively small, when the gate voltage of the compensation transistor T2 increases, the voltage of the second electrode of the compensation transistor T2 increases to a small extent, that is, So that the potential of the first node N1 is less affected by the channel capacitor, the potential increase of the first node N1 in the second pixel circuit 12 is relatively small, and the potential of the first node N1 in the second pixel circuit 12 is low,
  • the driving transistor T3 controlled by the first node N1 is more fully turned on, which in turn causes the driving current through the driving transistor T3 to be larger, so that the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the
  • the difference in luminance of the second light-emitting device 22 and the first light-emitting device 21 under the same preset gray scale improves the display uniformity of the display substrate 100 and the display device 1000 .
  • the difference between the channel length of the compensation transistor T2 in the first pixel circuit 11 and the channel length of the compensation transistor T2 in the second pixel circuit 12 is less than or equal to 0.8 ⁇ m.
  • the difference between the channel length of the compensation transistor T2 in the first pixel circuit 11 and the channel length of the compensation transistor T2 in the second pixel circuit 12 may be 0.1 ⁇ m, 0.2 ⁇ m, 0.5 ⁇ m, or 0.7 ⁇ m. or 0.8 ⁇ m.
  • the channel capacitance of the compensation transistor T2 of the second pixel circuit 12 is relatively small. Therefore, when the compensation transistor When T2 is turned off, the level of the scanning signal transmitted by the scanning signal line Gate changes from low level to high level, that is to say, the gate voltage of the compensation transistor T2 increases, thereby connecting it to the first node N1 The voltage of the second pole of the compensation transistor T2 will also increase accordingly.
  • the second pixel circuit 12 Since the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is smaller than the channel capacitance of the compensation transistor T2 in the first pixel circuit 11, when the gate voltage of the compensation transistor T2 increases, the second pixel circuit 12 The voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11 is smaller than the voltage increase amplitude of the channel portion of the compensation transistor T2 in the first pixel circuit 11, because the channel portion of the compensation transistor T2 passes through the second voltage of the compensation transistor T2.
  • the pole is connected to the first node N1, that is, the voltage increase of the first node N1 in the second pixel circuit 12 is smaller than the voltage increase of the first node N1 in the first pixel circuit 11, that is, the second pixel circuit
  • the potential of the first node N1 of 12 is less affected by the channel capacitor of its corresponding compensation transistor T2, and the potential of the first node N1 in the second pixel circuit 12 is lower than the potential of the first node N1 in the first pixel circuit 11 , thus making the driving transistor T3 of the second pixel circuit 12 controlled by the first node N1 more fully conductive during the light-emitting phase, thereby making the starting value of the driving current through the driving transistor T3 of the second pixel circuit 12 larger.
  • the difference in luminance of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray level can be reduced, and the uniformity of the display substrate 100 and the display device 1000 in low gray level display can be improved.
  • the ratio of the channel length of the compensation transistor T2 in the first pixel circuit 11 to the channel length of the compensation transistor T2 in the second pixel circuit 12 is greater than 1 and less than or equal to 1.15.
  • the channel length of the compensation transistor T2 in the first pixel circuit 11 when the channel length of the compensation transistor T2 in the first pixel circuit 11 is 6.2 ⁇ m, the channel length of the compensation transistor T2 in the second pixel circuit 12 may be 5.4 ⁇ m, 5.5 ⁇ m, or 5.7 ⁇ m. , 5.8 ⁇ m or 6.1 ⁇ m.
  • the ratios of the channel length of the compensation transistor T2 in the first pixel circuit 11 to the channel length of the compensation transistor T2 in the second pixel circuit 12 are 1.15, 1.13, 1.09, respectively. 1.07, 1.02.
  • the display substrate 100 further includes: a plurality of leads 30 .
  • the second pixel circuit 12 and the second light-emitting device 22 are coupled through wires.
  • one end of the plurality of leads 30 is coupled to the fourth node N4 of the second pixel circuit 12 , and the other end of the plurality of leads 30 is coupled to the first electrode of the second light-emitting device 22 , thereby realizing the second pixel.
  • the circuit 12 is coupled to the second light emitting device 22 .
  • the lead since the lead has a certain length, the lead will cross over at least part of the pixel circuit or across part of the shift register unit or part of the fan-out unit and other circuit structures, and the lead will be in contact with the above circuit structure. A parasitic capacitor is formed between them, so that the electrical signal transmitted on the lead is affected by the parasitic capacitance, which makes it take a long time for the electrical signal on the lead to be transmitted to the first electrode of the light-emitting device, or the existence of a longer lead
  • the transmitted electrical signal is transmitted to the first electrode of the light-emitting device after a certain amount of loss, and then it takes a longer time for the first electrode of the light-emitting device to reach the preset potential, causing the light-emitting device to turn on later or emit brightness. lower.
  • the channel width to length ratio of the driving transistor T3 in the second pixel circuit 12 connected to the lead 30 is set to be smaller than the channel width to length ratio of the driving transistor T3 in the first pixel circuit 11, and/or , the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 is smaller than the channel capacitance of the compensation transistor T2 in the first pixel circuit 11, so that after the data writing and compensation stages of the pixel circuit are completed, the second pixel circuit
  • the potential of the first node N1 in 12 is less than the preset potential value, which makes the driving transistor T3 controlled by the first node N1 conduct more fully during the light-emitting phase, thereby causing the start of the driving current through the driving transistor T3.
  • the value is larger, which can compensate for the overall lowering of the driving current value due to the longer precharge time of the fourth node N4, thereby increasing the driving current through the driving transistor T3 of the second pixel circuit 12, so that the second light-emitting device
  • the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the difference in luminous brightness of the second light-emitting device 22 and the first light-emitting device 21 under the same preset low gray level, and improving the low gray level display performance of the display substrate 100 and the display device 1000
  • the display below shows uniformity.
  • the longer the length of the lead 30 the larger the facing area between the lead 30 and circuit structures such as pixel circuits, shift register units, or fan-out units, and the greater the capacitance of the parasitic capacitor formed by the lead 30 and the above circuit structures.
  • the longer the lead 30 the greater the loss of the electrical signal on the lead 30, resulting in a longer precharge time of the fourth node N4 or a lower initial value of the drive current, thus causing the drive current transmitted by the lead 30 to The smaller.
  • the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 and the length of the lead 30 connected to the second pixel circuit 12 are negatively correlated.
  • the lengths of the corresponding leads 30 are also different. The larger the distance between the plurality of second pixel circuits 12 and the second light-emitting devices 22 they drive, the longer the length of the corresponding lead 30 is.
  • the length of the lead 30 may be 34 ⁇ m, 80 ⁇ m, 100 ⁇ m, 150 ⁇ m, 195 ⁇ m, etc.
  • the plurality of leads 30 may be located on the light emitting device layer of the display substrate 100 .
  • the “negative correlation” here means that the longer the length of the lead 30 connected to the second pixel circuit 12 , the smaller the channel width-to-length ratio of the driving transistor T3 in the second pixel circuit 12 .
  • the channel width to length ratio of the driving transistor T3 in the second pixel circuit 12 is set to be smaller, thereby making the second pixel circuit.
  • the parasitic capacitance formed by the structure and the length of the lead 30 reduce the initial value of the driving current caused by the loss of the electrical signal, so that the luminous brightness of the second light-emitting device 22 is improved, and thus the second light-emitting device 22 can be reduced in size under the same preset gray scale.
  • the difference in luminance of the light-emitting device 22 and the first light-emitting device 21 improves the display uniformity of the display substrate 100 and the display device 1000 .
  • the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 and the length of the lead 30 connected to the second pixel circuit 12 are negatively correlated.
  • the “negative correlation” here means that the longer the length of the lead 30 connected to the second pixel circuit 12 , the smaller the channel capacitance of the compensation transistor T2 in the second pixel circuit 12 .
  • the channel capacitance of the compensation transistor T2 of the second pixel circuit 12 is smaller, thereby making the second pixel circuit 12 have a smaller channel capacitance.
  • the parasitic capacitance and the length of the lead 30 reduce the initial value of the driving current caused by the loss of the electrical signal, so that the luminous brightness of the second light-emitting device 22 is improved, thereby reducing the size of the second light-emitting device 22 under the same preset gray scale.
  • the difference in luminance from the first light-emitting device 21 improves the display uniformity of the display substrate 100 and the display device 1000 .
  • the display substrate 100 includes a shift register GOA
  • a plurality of first pixel circuits 11 a plurality of second pixel circuits 12 and a plurality of shift registers GOA are in the display area A.
  • the plurality of light-emitting devices 20 are arranged in multiple rows and multiple columns. Taking the area on the right side of the center line NN' of the display substrate 100 as an example, the distance between the second pixel circuit 12 in the nth column and the second light-emitting device 22 it drives in the top view (FIG. 7a) is the same as that in the n+1th column.
  • the distance between the two pixel circuits and the second light-emitting device 22 they drive in the top view (FIG. 7a), and the distance between the n+2th column pixel circuit and the second light-emitting device 22 they drive in the top view (FIG. 7a),... ..., increases gradually, then the channel width-to-length ratio of the corresponding driving transistor T3 of the second pixel circuit 12 decreases gradually, or the channel capacitance of the compensation transistor T2 of the corresponding second pixel circuit 12 Decreases gradually.
  • the present invention sets the channel width of the driving transistor T3 of the second pixel circuit 12 to be reduced by 0.6 ⁇ m relative to the channel width of the driving transistor T3 of the first pixel circuit 11, and in this case, the first pixel circuit 11 Simulation calculations were performed on the electrical signal and driving current I of the first node N1 and the electrical signal and driving current I of the first node N1 of the second pixel circuit 12. The simulation results are shown in Figure 14a.
  • the present invention sets the channel length of the driving transistor T3 of the second pixel circuit 12 to be increased by 1.4 ⁇ m relative to the channel length of the driving transistor T3 of the first pixel circuit 11, and in this case, the first pixel circuit 11 Simulation calculations were performed on the electrical signal and driving current I of a node N1, and the electrical signal and driving current of the first node N1 of the second pixel circuit 12. The simulation results are shown in Figure 14b.
  • the present invention sets the channel width of the compensation transistor T2 of the second pixel circuit 12 to be reduced by 0.3 ⁇ m relative to the channel width of the compensation transistor T2 of the first pixel circuit 11, and in this case, the first pixel circuit 11 Simulation calculations were performed on the electrical signal and driving current I of the first node N1, and the electrical signal and driving current I of the first node N1 of the second pixel circuit 12. The simulation results are shown in Figure 14c.
  • the present invention sets the channel length of the compensation transistor T2 of the second pixel circuit 12 to be reduced by 0.8 ⁇ m relative to the channel length of the compensation transistor T2 of the first pixel circuit 11, and in this case, the first pixel circuit 11 Simulation calculations were performed on the electrical signal and driving current I of the first node N1, and the electrical signal and driving current I of the first node N1 of the second pixel circuit 12. The simulation results are shown in Figure 14d.
  • the channel width of the drive transistor T3 of the second pixel circuit 12 is reduced by 0.6 ⁇ m or the channel length is increased by 1.4 ⁇ m compared to the drive transistor T3 of the first pixel circuit 11.
  • the voltage UN12 of the first node N1 in the second pixel circuit 12 is less than the voltage UN11 of the first node N1 in the first pixel circuit 11, and the turn-on time t2 of the second pixel circuit 12 is later than the turn-on time t2 of the first pixel circuit 11.
  • the starting value of the driving current I2 of the second pixel circuit 12 is greater than the starting value of the driving current I1 of the first pixel circuit 11.
  • the turn-on time of the pixel circuit refers to the time when the driving current is generated and the magnitude of the driving current becomes approximately stable.
  • the size of the driving current of the pixel circuit is the average value of the driving current in one light-emitting stage.
  • the driving current I2 of the second pixel circuit 12 is within the effective level range of the enable signal EM (between the two corresponding square waves in the figure, approximately 16.8ms to 33.5ms) , the average value of the driving current.
  • the channel width of the compensation transistor T2 of the second pixel circuit 12 is reduced by 0.3 ⁇ m or the channel length is reduced by 0.8 ⁇ m compared to the compensation transistor T2 of the first pixel circuit 11.
  • the voltage UN12 of the first node N1 in the second pixel circuit 12 is less than the voltage UN11 of the first node N1 in the first pixel circuit 11, and the turn-on time of the second pixel circuit 12 is later than the turn-on time of the first pixel circuit 11.
  • the starting value of the driving current I2 of the second pixel circuit 12 is greater than the starting value of the driving current I1 of the first pixel circuit 11 .
  • the second pixel circuit 12 can be The voltage of the first node N1 decreases, causing the driving transistor T3 of the second pixel circuit 12 to conduct more fully, thereby causing the driving current of the second pixel circuit 12 to increase to a certain extent, making up for part of the delay in the turn-on time.
  • Lowering the driving current value causes the driving current of the second pixel circuit 12 to increase to a certain extent, so that the driving current of the second pixel circuit 12 and the driving current of the first pixel circuit 11 tend to be consistent, and thus the driving current can be
  • the display uniformity of the display substrate 100 and the display device 1000 is improved.
  • the pixel circuit 10 and the driven light-emitting device 20 constitute a sub-pixel.
  • the first pixel circuit 11 and the first light-emitting device 21 it drives form a first sub-pixel
  • the second pixel circuit 12 and the second light-emitting device 22 it drives form a second sub-pixel.
  • the colors of light emitted by sub-pixels are different, and the driving currents required are also different.
  • the present invention calculates the current difference ⁇ I/I1 of the driving currents of the second sub-pixels of different colors corresponding to the driving transistor T3 of the different second pixel circuit 12 and the compensation transistor T2 of the different second pixel circuit 12 , and draw, specifically, as shown in Figures 15a to 15d.
  • I1 is the driving current of the first pixel circuit 11.
  • ⁇ I is the difference between the driving current I2 of the second pixel circuit 12 and the driving current I1 of the first pixel circuit 11 .
  • the channel width W of the driving transistor T3 of the second pixel circuit 12 is set to be sequentially reduced by 0.2 ⁇ m, 0.4 ⁇ m, and 0.6 ⁇ m relative to the channel width of the driving transistor T3 of the first pixel circuit 11, and then The above-mentioned progressive reduction of the channel width is plotted against the current difference in the drive current in the second sub-pixel of different colors, resulting in Figure 15a.
  • the channel length L of the driving transistor T3 of the second pixel circuit 12 is set to increase in order by 0.4 ⁇ m, 0.8 ⁇ m, 1.2 ⁇ m, and 1.4 ⁇ m relative to the channel length of the driving transistor T3 of the first pixel circuit 11, and then the above
  • the progressive increase in channel length is plotted against the current difference in the drive current in the second sub-pixel of different colors, resulting in Figure 15b.
  • the channel width W of the compensation transistor T2 of the second pixel circuit 12 is set to be sequentially reduced by 0.1 ⁇ m, 0.2 ⁇ m, and 0.3 ⁇ m relative to the channel width of the compensation transistor T2 of the first pixel circuit 11, and then the above-mentioned channel is
  • the progressive reduction in width is plotted against the current difference in drive current in second sub-pixels of different colors, resulting in Figure 15c.
  • the channel length L of the compensation transistor T2 of the second pixel circuit 12 is set to be sequentially reduced by 0.2 ⁇ m, 0.4 ⁇ m, 0.6 ⁇ m, and 0.8 ⁇ m relative to the channel length of the compensation transistor T2 of the first pixel circuit 11, and then The above-mentioned progressive reduction of the channel length is plotted against the current difference in the drive current in the second sub-pixel of different colors, resulting in Figure 15d.
  • R represents the red second sub-pixel
  • G represents the green second sub-pixel
  • B represents the blue second sub-pixel
  • ⁇ W in Figure 15a represents the second pixel circuit 12
  • ⁇ L in FIG. 15b represents the difference between the channel length of the driving transistor T3 of the second pixel circuit 12 and the first pixel circuit 11.
  • the difference in channel length of the driving transistor T3 of the pixel circuit 11, ⁇ W in FIG. 15c represents the channel width of the compensation transistor T2 of the second pixel circuit 12 relative to the channel width of the compensation transistor T2 of the first pixel circuit 11.
  • the 15d represents the difference between the channel length of the compensation transistor T2 of the second pixel circuit 12 and the channel length of the compensation transistor T2 of the first pixel circuit 11.
  • the differences in the channel length and channel width of the driving transistor T3 and the compensation transistor T2 of the second pixel circuit 12 and the first pixel circuit 11 are collectively referred to as the channel variation of the second pixel circuit 12 below. .
  • the current difference ⁇ I/I1 of the driving current of the second pixel circuit 12 shows a gradually decreasing trend.
  • the green second sub-pixel G in FIG. 15a when the channel change amount of the second pixel circuit 12 gradually changes from 0 ⁇ m to -0.6 ⁇ m, the second pixel circuit 12 in the green second sub-pixel G The current difference ⁇ I/I1 of the driving current changes from -40% to close to 0%.
  • the drive current of the second pixel circuit 12 is different from the channel width of the first pixel circuit 11 .
  • the driving currents of the circuit 11 are nearly equal, thereby greatly improving the display uniformity of the display substrate 100 and the display device 1000 .
  • FIGS. 15 a to 15 d it can be seen from FIGS. 15 a to 15 d that as the channel change amount of the second pixel circuit 12 increases, the change trends of the second sub-pixels of different colors are consistent.
  • FIG. 15b when the channel change amount of the second pixel circuit 12 gradually changes from 0 ⁇ m to 1.6 ⁇ m, the current difference ⁇ I of the driving current of the second pixel circuit 12 in the green second sub-pixel G is /I1 changes from -40% to approximately 0%, the current difference ⁇ I/I1 of the driving current of the second pixel circuit 12 in the red second sub-pixel R changes from -25% to approximately 0%, and the blue The current difference ⁇ I/I1 of the driving current of the second pixel circuit 12 in the second sub-pixel B changes from -25% to approximately 0%.
  • the channel variation of the second sub-pixels of different colors is applicable to the above channel variation range, that is, 0 ⁇ m ⁇ 1.6 ⁇ m, and when the channel variation is 1.6 ⁇ m, for the driving current of the second pixel circuit 12
  • the improvement effect of the current difference with the driving current of the first pixel circuit 11 is the best, and the display uniformity of the display substrate 100 and the display device 1000 can be greatly improved.
  • Figures 14a to 14d and Figures 15a to 15d are all simulations and calculations carried out under the condition of preset low gray scale. Since the current difference of the driving current will be different under different preset gray scales, the present invention At a higher gray level (the default gray level is L255), the current difference corresponding to the channel variation of the above-mentioned second pixel circuit 12 was calculated, and the calculated results are shown in FIG. 16 .
  • T3W-0.6 ⁇ m indicates that the difference between the channel width of the driving transistor T3 of the second pixel circuit 12 and the channel width of the driving transistor T3 of the first pixel circuit 11 is -0.6 ⁇ m
  • T3L+1.4 ⁇ m indicates that the difference between the channel length of the driving transistor T3 of the second pixel circuit 12 and the channel length of the driving transistor T3 of the first pixel circuit 11 is +1.4 ⁇ m
  • T2W-0.3 ⁇ m indicates that the second pixel circuit 12
  • the difference between the channel width of the compensation transistor T2 and the channel width of the compensation transistor T2 of the first pixel circuit 11 is -0.3 ⁇ m
  • “T2L-0.8 ⁇ m” represents the channel length of the compensation transistor T2 of the second pixel circuit 12
  • the difference from the channel length of the compensation transistor T2 of the first pixel circuit 11 is -0.8 ⁇ m.
  • “R” represents the red second sub-pixel
  • “G” represents the green second sub-pixel
  • both the low gray scale display and the high gray scale display of the display substrate 100 can achieve a relatively uniform display effect, which significantly improves the performance of the display substrate. 100 and display uniformity of the display device 1000 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

显示基板包括：像素电路及发光器件；像素电路包括：第一像素电路和第二像素电路。发光器件包括：第一发光器件和第二发光器件。第一像素电路与第一发光器件耦接，第一像素电路与第一发光器件部分正对设置；第二像素电路与第二发光器件耦接；第二像素电路在显示基板所在平面的正投影，与第二发光器件在显示基板所在平面的正投影无交叠；第一像素电路中的驱动晶体管的沟道宽长比，大于第二像素电路中的驱动晶体管的沟道宽长比；第一像素电路中的补偿晶体管的沟道电容，大于第二像素电路中的补偿晶体管的沟道电容。

Description

显示基板及显示装置
本申请要求于2022年05月18日提交的、申请号为202210540045.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)显示技术是一种利用发光材料在电流的驱动下发光来实现显示的技术。OLED显示器具有超轻、超薄、高亮度、大视角、低电压、低功耗、快响应、高清晰度、抗震、可弯曲、低成本、工艺简单、使用原材料少、发光效率高和温度范围宽等优点。
发明内容
一方面，提供了一种显示基板，所述显示基板包括：多个像素电路及多个发光器件；像素电路包括：驱动晶体管以及与所述驱动晶体管耦接的补偿晶体管。所述多个像素电路包括：多个第一像素电路和多个第二像素电路。所述多个发光器件包括：多个第一发光器件和多个第二发光器件。其中，第一像素电路与第一发光器件耦接，所述第一像素电路与所述第一发光器件至少部分正对设置。第二像素电路与第二发光器件耦接；所述第二像素电路在所述显示基板所在平面的正投影，与所述第二发光器件在所述显示基板所在平面的正投影无交叠。所述第一像素电路中的驱动晶体管的沟道宽长比，大于所述第二像素电路中的驱动晶体管的沟道宽长比。和/或，所述第一像素电路中的补偿晶体管的沟道电容，大于所述第二像素电路中的补偿晶体管的沟道电容。
在一些实施例中，所述第一像素电路中的驱动晶体管的沟道宽度，大于所述第二像素电路中的驱动晶体管的沟道宽度。
在一些实施例中，所述第一像素电路中的驱动晶体管的沟道宽度，与所述第二像素电路中的驱动晶体管的沟道宽度的差值小于或等于0.6μm。
在一些实施例中，所述第一像素电路中的驱动晶体管的沟道宽度，与所述第二像素电路中的驱动晶体管的沟道宽度的比值，大于1小于或等于1.21。
在一些实施例中，所述第一像素电路中的驱动晶体管的沟道长度，小于所述第二像素电路中的驱动晶体管的沟道长度。
在一些实施例中所述第一像素电路中的驱动晶体管的沟道长度，与所述第二像素电路中的驱动晶体管的沟道长度的差值小于或等于1.4μm。
在一些实施例中，所述第一像素电路中的驱动晶体管的沟道长度，与所述第二像素电路中的驱动晶体管的沟道长度的比值，小于1且大于或等于0.94。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道宽度，大于所述第二像素电路中的补偿晶体管的沟道宽度。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道宽度，与所述第二像素电路中的补偿晶体管的沟道宽度的差值小于或等于0.3μm。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道宽度，与所述第二像素电路中的补偿晶体管的沟道宽度的比值，大于1且小于或等于1.14。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道长度，大于所述第二像素电路中的补偿晶体管的沟道长度。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道长度，与所述第二像素电路中的补偿晶体管的沟道长度的差值小于或等于0.8μm。
在一些实施例中，所述第一像素电路中的补偿晶体管的沟道长度，与所述第二像素电路中的补偿晶体管的沟道长度的比值，大于1且小于或等于1.15。
在一些实施例中，所述显示基板还包括：多条引线。所述第二像素电路与所述第二发光器件之间通过引线耦接。
在一些实施例中，所述第二像素电路中的驱动晶体管的沟道宽长比，及所述第二像素电路连接的引线的长度比呈负相关。和/或，所述第二像素电路中的补偿晶体管的沟道电容，及所述第二像素电路连接的引线的长度比呈负相关。
在一些实施例中，所述像素电路还包括：第一复位晶体管、第一发光控制晶体管、第二发光控制晶体管、第二复位晶体管、开关晶体管和存储电容器。所述第一复位晶体管的栅极与第一复位信号线耦接，所述第一复位晶体管的第一极与第一初始信号线耦接，所述第一复位晶体管的第二极与第一节点耦接；所述第一复位晶体管被配置为，在第一复位信号线所提供的第一复位信号的控制下，将所述第一初始信号线提供的第一初始信号传输至所述第一节点。所述开关晶体管的栅极与扫描信号线耦接，所述开关晶体管的第一极与数据信号线耦接，所述开关晶体管的第二极与第二节点耦接；所述开关晶体管被配置为，在所述扫描信号线所提供的扫描信号的控制下，将所述数据信号线所提供的数据信号传输至所述第二节点。所述第一发光控制晶体管的栅极与使能信号线耦接，所述第一发光控制晶体管的第一极与第一电压信号线耦接，所述第一发光控制晶体管的第二极与所述第二节点耦接；所述第一发光控制晶体管被配置为，在所述使能信号线所提供的使能信号的控制下，将所述第一电压信号线所提供的第一电压信号传输至所述第二节点。所述驱动晶体管的栅极与所述第一节点耦接，所述驱动晶体管的第一极与所述第二节点耦接，所述驱动晶体管的第二极与第三节点耦接；所述驱动晶体管被配置为，在所述第一节点的电信号的控制下，将所述第二节点的电信号传输至所述第三节点。所述补偿晶体管的栅极与所述第一节点耦接，所述补偿晶体管的第一极与所述第三节点耦接，所述补偿晶体管的第二极与所述扫描信号线耦接；所述补偿晶体管被配置为，在所述扫描信号的控制下，将所述第三节点的电信号传输至所述第一节点。所述存储电容器的第一极与所述第一电压信号线耦接，所述存储电容器的第二极与所述第一节点耦接。所述第二发光控制晶体管的栅极与所述使能信号线耦接，所述第二发光控制晶体管的第一极与所述第三节点，所述第二发光控制晶体管的第二极与第四节点耦接；所述第二发光控制晶体管被配置为，在使能信号的控制下，将所述第三节点的电信号传输至所述第四节点。所述第二复位晶体管的栅极与第二复位信号线耦接，所述第二复位晶体管的第一极与第二初始信号线耦接，所述第二复位晶体管的第二极与所述第四节点耦接；所述第二复位晶体管被配置为，在第二复位信号线所提供的第二复位信号的控制下，将所述第二初始信号线提供的第二初始信号传输至所述第四节点。
另一方面，提供了一种显示装置，所述显示装置包括：如上述实施例中任一项所述的显示基板。
附图说明
为了更清楚地说明本发明中的技术方案，下面将对本发明一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本发明实施例所涉及的产品的实际尺寸等的限制。
图1为根据本发明一些实施例中一种显示装置的结构图；
图2为根据本发明一些实施例中一种显示基板的结构图；
图3为根据本发明一些实施例中一种像素电路的结构图；
图4为根据本发明一些实施例中另一种显示基板的结构图；
图5a为根据本发明一些实施例中另一种显示装置的结构图；
图5b为根据本发明一些实施例中又一种显示基板的结构图；
图5c为根据本发明一些实施例中又一种显示装置的结构图；
图5d为根据本发明一些实施例中又一种显示装置的结构图；
图6a为一种实现方式中一种显示基板的局部结构图；
图6b为一种实现方式中驱动电流、第四节点电压及使能信号对时间的曲线图；
图7a为根据本发明一些实施例中一种显示基板的局部结构图；
图7b为根据本发明一些实施例中一种显示基板的局部结构图；
图8a为根据本发明一些实施例中一种驱动晶体管的局部结构图；
图8b为根据本发明一些实施例中另一种驱动晶体管的局部结构图；
图9为根据本发明一些实施例中又一种驱动晶体管的局部结构图；
图10为根据本发明一些实施例中又一种驱动晶体管的局部结构图；
图11a为根据本发明一些实施例中一种补偿晶体管的局部结构图；
图11b为根据本发明一些实施例中另一种补偿晶体管的局部结构图；
图12为根据本发明一些实施例中又一种补偿晶体管的局部结构图；
图13为根据本发明一些实施例中又一种补偿晶体管的局部结构图；
图14a为根据本发明一些实施例中一种显示基板中第一像素电路及第二像素电路中驱动电流、第一节点电压及使能信号对时间的曲线图；
图14b为根据本发明一些实施例中另一种显示基板中第一像素电路及第二像素电路中驱动电流、第一节点电压及使能信号对时间的曲线图；
图14c为根据本发明一些实施例中又一种显示基板中第一像素电路及第二像素电路中驱动电流、第一节点电压及使能信号对时间的曲线图；
图14d为根据本发明一些实施例中又一种显示基板中第一像素电路及第二像素电路中驱动电流、第一节点电压及使能信号对时间的曲线图；
图15a为根据本发明一些实施例中一种显示基板中不同颜色的第二子像素的电流差异与第二像素电路的沟道变化量的曲线图；
图15b为根据本发明一些实施例中另一种显示基板中不同颜色的第二子像素的电流差异与第二像素电路的沟道变化量的曲线图；
图15c为根据本发明一些实施例中又一种显示基板中不同颜色的第二子像素的电流差异与第二像素电路的沟道变化量的曲线图；
图15d为根据本发明一些实施例中又一种显示基板中不同颜色的第二子像素的电流差异与第二像素电路的沟道变化量的曲线图；
图16为根据本发明一些实施例中预设灰阶为L255情况下不同颜色的第二子像素的电流差异的计算结果图。
具体实施方式
下面将结合附图，对本发明一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本发明的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文中术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本发明的实施例提供的各电路结构(例如像素电路)中，所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本发明的实施例中均以薄膜晶体管为例进行说明。
在本发明的实施例提供的电路结构中，所采用的各晶体管的第一极为源极和漏极中一者，各晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本发明的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极。示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本发明的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关耦接的汇合点，也就是说，这些节点是由电路图中相关耦接的汇合点等效而成的节点。
在本发明中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，本发明以像素电路所包括的晶体管均为P型晶体管为例进行说明。
如图1所示，本发明的一些实施例提供了一种显示装置1000。
在一些示例中，上述显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字的还是图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
示例性的，显示装置1000包括：框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
在一些实施例中，上述显示装置1000还包括：显示基板100。
在一些示例中，显示基板100包括：依次层叠设置的衬底、像素电路层、发光器件层。
示例性的，上述衬底可以为柔性衬底，也可以为刚性衬底。
例如，在衬底为柔性衬底的情况下，衬底的材料可以为二甲基硅氧烷、PI(Polyimide，聚酰亚胺)、PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)等具有高弹性的材料。又如，在衬底为刚性衬底的情况下，衬底的材料可以为玻璃等。
示例性，像素电路层包括多个像素电路10，发光器件层20包括多个发光器件20。也就是说，如图2所示，显示基板100可以包括多个像素电路10和多个发光器件20。
示例性的，上述像素电路10可以呈阵列状排布。
示例性的，像素电路10可以包括由一些晶体管及一些电容器组成的电路等。
示例性的，上述发光器件20可以为OLED发光器件。
例如，发光器件20可以包括依次层叠设置的第一电极、发光功能层、第二电极等。其中，发光功能层可以包括发光层。可选地，发光功能层还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层中的至少一者。
例如，第一电极可以为阳极和阴极中的一者，第二电极可以为阳极和阴极中的另一者，本发明对此不作限制。
为方便描述，本发明中以第一电极为阳极，第二电极为阴极为例进行说明。
例如，上述多个像素电路10和多个发光器件20可以一一对应耦接。又如，在本发明中，一个像素电路10可以与多个发光器件20耦接，或者，多个像素电路10可以与一个发光器件20耦接。
下面，本发明以一个像素电路10与一个发光器件20耦接为例，对显示基板100的结构进行示意性说明。
示例性的，显示基板100中，像素电路10中的电路可以生成驱动信号(例如驱动电流为例)。各发光器件20可以在其所属的像素电路10所生成的驱动信号的驱动作用下发出光，多个发光器件20发出的光相互配合，从而使得显示基板100及显示装置1000实现显示功能。
示例性的，像素电路10的结构可以包括多种，可以根据实际需要选择设置。例如，像素电路的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
下面结合图3，以像素电路10的结构为“7T1C”的结构为例，对像素电路10的结构及工作过程进行示意性说明。需要说明的是，像素电路10所包括的七个晶体管和一个存储电容器之间，还可以具有其他的耦接关系，并不局限于本示例中所示的耦接关系。
可以理解的是，在像素电路10工作的过程中，需要多种信号线为其提供相应的电信号。因此，示例性的，显示基板100还包括用于传输第一初始信号的第一初始信号线Vinit1、用于传输第二初始信号的第二初始信号线Vinit2、用于传输扫描信号的扫描信号线Gate、用于传输第一复位信号的第一复位信号线Reset1、用于传输第二复位信号的第二复位信号线Reset2、用于传输使能信号的使能信号线EM、用于传输数据信号的数据线Data、用于传输第一电压信号的电压信号线VDD，用于传输公共电压信号的公共电压信号线VSS。
在一些示例中，如图3所示，像素电路10包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、开关晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7和存储电容器Cst。
示例性的，第一复位晶体管T1的栅极与第一复位信号线Reset1耦接，第一复位晶体管T1的第一极与第一初始信号线Vinit1耦接，第一复位晶体管T1的第二级与第一节点N1耦接。第一复位晶体管T1被配置为，在第一初始信号的控制下，将第一初始信号传输至第一节点N1。
例如，在第一初始信号的电平为工作电平的情况下，第一复位晶体管T1导通，将来自第一初始信号线Vinit1的第一初始信号传输至第一节点N1，对第一节点N1进行复位。
需要说明的是，本发明中的“工作电平”指的是能够使得晶体管导通的电平。在晶体管为N型晶体管的情况下，“工作电平”则为高电平。在晶体管为P型晶体管的情况下，“工作电平”则为低电平。以下各实施例与此相同，不再赘述。
示例性的，存储电容器Cst的第一极板与第一电压信号线VDD耦接，存储电容器Cst的第二极板与第一节点N1耦接。
示例性的，开关晶体管T4的栅极与扫描信号线Gate耦接，开关晶体管T4的第一极与数据信号线Data耦接，开关晶体管T4的第二级与第二节点N2耦接。开关晶体管T4被配置为，在扫描信号的控制下，将数据信号传输至第二节点N2。
例如，在扫描信号的电平为工作电平的情况下，开关晶体管T4导通，将来自数据信号线Data的数据信号传输至第二节点N2。
示例性的，驱动晶体管T3的栅极与第一节点N1耦接，驱动晶体管T3的第一极与第二节点N2耦接，驱动晶体管T3的第二级与第三节点N3耦接。驱动晶体管T3被配置为，在第一节点N1的电信号的控制下，将第二节点N2的电信号传输至第三节点N3。
例如，在第一节点N1的电信号的电平为工作电平的情况下，驱动晶体管T3导通，将来自第二节点N2的电信号(例如为数据信号)传输至第三节点N3。
示例性的，补偿晶体管T2的栅极与扫描信号线Gate耦接，补偿晶体管T2的第一极与第三节点N3耦接，补偿晶体管T2的第二级与第一节点N1耦接。补偿晶体管T2被配置为，在扫描信号的控制下，将第三节点N3的电信号传输至第一节点N1，对驱动晶体管T3的阈值电压进行补偿，且对与第一节点N1耦接的存储电容器Cst进行充电。
例如，在扫描信号的电平为工作电平的情况下，补偿晶体管T2导通，将来自第三节点N3的电信号(例如为数据信号)传输至第一节点N1。
示例性的，第二复位晶体管T7的栅极与第二复位信号线Reset2耦接，第二复位晶体管T7的第一极与第二初始信号线Vinit2耦接，第二复位晶体管T7的第二级与第四节点N4耦接。第二复位晶体管T7被配置为，在第二初始信号的控制下，将第二初始信号传输至第四节点N4。
例如，在第二初始信号的电平为工作电平的情况下，第二复位晶体管T7导通，将来自第二初始信号线Vinit2的第二初始信号传输至第四节点N4，对第四节点N4进行复位。
示例性的，第一发光控制晶体管T5的栅极与使能信号线EM耦接，第一发光控制晶体管T5的第一极与第一电压信号线VDD耦接，第一发光控制晶体管T5的第二级与第二节点N2耦接。第一发光控制晶体管T5被配置为，在使能信号的控制下，将第一电压信号传输至第二节点N2。
例如，在使能信号的电平为工作电平的情况下，第一发光控制晶体管T5导通，将来自第一电压信号线VDD的第一电压信号传输至第二节点N2。
示例性的，第二发光控制晶体管T6的栅极与使能信号线EM耦接，第二发光控制晶体管T6的第一极与第三节点N3耦接，第二发光控制晶体管T6的第二级与第四节点N4耦接。第二发光控制晶体管T6被配置为，在使能信号的控制下，将第三节点N3的电信号传输至第四节点N4。
例如，在使能信号的电平为工作电平的情况下，第二发光控制晶体管T6导通，将来自第三节点N3的电信号(例如驱动信号)传输至第四节点N4。
例如，发光器件20的一端与第四节点N4耦接，发光器件20的另一端与公共电压信号线VSS耦接。发光器件20在第四节点N4的电信号及公共电压信号线VSS提供的公共电压信号的作用下发光。
示例性的，像素电路10的工作过程包括依次进行的复位阶段、数据写入及补偿阶段、发光阶段。
例如，在复位阶段，在复位信号的控制下，第一复位晶体管T1导通，将第一初始信号传输至第一节点N1，对第一节点N1进行复位。由于第一节点N1与存储电容器Cst、驱动晶体管T3的栅极及补偿晶体管T2的第二极耦接，因此，在对第一节点N1复位时，便可以对存储电容器Cst、驱动晶体管T3的栅极及补偿晶体管T2的第二极进行复位。其中，驱动晶体管T3可以在第一初始信号的控制下导通。
例如，在数据写入及补偿阶段，开关晶体管T4和补偿晶体管T2，在扫描信号的控制下同时导通。开关晶体管T4将数据信号传输至第二节点N2，驱动晶体管T3在第一节点N1的控制下导通，将来自第二节点N2的数据信号传输至第三节点N3。补偿晶体管T2将来自第三节点N3的数据信号传输至第一节点N1，对驱动晶体管T3进行充电，直至驱动晶体管T3处于截止状态，完成对驱动晶体管T3的阈值电压的补偿。第二复位晶体管T7将第二始信号传输至第四节点N4。由于第四节点N4与发光器件20的第一电极耦接，因此，在对第四节点N4进行复位时，便可以对发光器件20的第一电极进行复位。
例如，在发光阶段，第一发光控制晶体管T5和第二发光控制晶体管T6在使能信号的控制下同时导通。第一发光控制晶体管T5将第一电压信号传输至第二节点N2。驱动晶体管T3将来自第二节点N2的电信号传输至第三节点N3。第二发光控制晶体管T6将来自第三节点N3的电压信号传输至第四节点N4。发光器件20在来自第四节点N4的电信号和来自公共电压线VSS的公共电压信号的作用下，发光。
需要说明的是，在预设灰阶为低灰阶的情况下，在发光阶段，像素电路10的第四节点N4需要经过一定时间的预充电，才能达到预设发光电压，发光器件20才能在预设发光电压和公共电压信号的作用下发光。
在一些实施例中，如图4所示，上述像素电路层包括：依次层叠在衬底一侧的半导体层PO、栅导电层GT和源漏导电层SD。
需要说明的是，图4中仅示意出了半导体层PO的部分图案、栅导电层GT的部分图案、以及源漏导电层SD的部分图案。
示例性的，上述源漏导电层SD可以为设置在栅导电层GT一侧的一层膜层，也可以为设置在栅导电层GT一侧的两层膜层，具体可以根据实际需要进行选择，本发明对此不作限制。
在一些示例中，半导体层PO的材料可以包括非晶硅、单晶硅、多晶硅等材料，也可以包括金属氧化物半导体材料，例如铟镓锌氧化物(Indium gallium zinc oxide，简称IGZO)等。
在一些示例中，上述栅导电层GT和源漏导电层SD的材料均为可导电材料。例如，上述可导电材料可以为金属材料，该金属材料例如为Al(铝)、Ag(银)、Cu(铜)、Cr(铬)等。
示例性的，在半导体层PO与栅导电层GT之间设置有第一绝缘层，第一绝缘层用于对半导体层PO与栅导电层GT之间进行隔离，避免短接。在栅导电层GT与源漏导电层SD之间设置有第二绝缘层。第二绝缘层用于对栅导电层GT与源漏导电层SD之间进行隔离，避免短接。
例如，第一绝缘层和第二绝缘层的材料可以为氧化硅、氮化硅、氮氧化硅等。
需要说明的是，半导体层PO在衬底上的正投影，与栅导电层GT在衬底上的正投影具有交叠。其中，在半导体层PO远离衬底的一侧形成栅导电层GT后，可以以栅导电层GT为掩膜，对半导体层PO进行掺杂处理，使得半导体层PO中未被栅导电层GT覆盖的部分，形成导体，该导体可以构成部分晶体管的第一极或第二极，使得半导体层PO中被栅导电层GT覆盖的部分，构成部分晶体管的沟道部，栅导电层GT中，与半导体层PO交叠的部分，构成部分晶体管的栅极图案，该栅极图案构成晶体管的栅极。沟道部具有沟道长度和沟道宽度。例如，沟道部的沟道长度指的是，沿晶体管的第一极和第二极的连线方向，沟道部位于晶体管的第一极和第二极之间部分的尺寸。沟道部的沟道宽度指的是，在垂直于晶体管的第一极和第二极的连线方向的方向上，沟道部的尺寸。
在一些示例中，如图5a所示，显示基板100具有显示区A和边框区B。
例如，上述显示A指的是显示基板100用于显示画面的区域。
示例性的，显示区A的形状可以包括多种，可以根据实际需要选择设置，本发明对此不作限制。
例如，显示区A的形状可以为矩形、近似矩形、圆形或椭圆形等。其中，近似矩形为非严格意义上的矩形，其四个内角例如可以为圆角，或者某条边例如不是直线。
为方便描述，本发明中以显示区A的形状为矩形为例进行说明。
示例性的，多个像素电路10及多个发光器件20均设置在显示区A。
例如，发光器件20可以均匀地分布在显示区A，从而在一定程度上保证显示基板100及显示装置1000所显示的画面的均一性。
示例性的，边框区B可以围绕显示区A设置。
显示基板100中位于显示区A的部分的设置方式有多种，例如，移位寄存器GOA、扇出单元Fanout和光学元件(如摄像头、红外传感器或指纹传感器)等其中的至少一者，可以设置在显示区A，具体可以根据实际需要进行设置，本发明对此不作限制。
在一些示例中，如图5a及图5b所示，显示基板100还包括：位于显示区A的至少一个移位寄存器GOA。至少一个移位寄存器GOA位于上述衬底与发光器件层之间，且至少一个移位寄存器GOA在衬底上的正投影与上述像素电路层在衬底上的正投影无交叠。
示例性的，显示区A设置有一个或多个移位寄存器电路GOA。
示例性的，移位寄存器GOA可以位于显示基板100中靠近显示区A和边框区B的边界线的位置。
例如，如图5b所示，多个移位寄存器GOA可以沿第二方向Y排列在显示区A沿第一方向X的两侧。
例如，上述“无交叠”指的是，至少一个移位寄存器GOA与像素电路层中的像素电路10在沿显示基板100的厚度方向上，没有相互覆盖的部分。
由于上述至少一个移位寄存器GOA与像素电路层均位于衬底与发光器件层之间，且在衬底上的正投影无交叠，因此，可以在同一套制备工艺中形成上述至少一个移位寄存器GOA与像素电路层中的像素电路10。
示例性的，移位寄存器GOA可以包括第一移位寄存器，第一移位寄存器可以与扫描信号线Gate电连接，为与该扫描信号线Gate电连接的像素电路10提供扫描信号。移位寄存器电路GOA也可以包括第二移位寄存器，第二移位寄存器可以与使能信号线EM电连接，为与该使能信号线EM电连接的像素电路10提供使能信号。
采用上述设置方式，将移位寄存器GOA设置在显示区A，可以减少边框区B内设置的移位寄存器GOA的数量，进而可以减小显示基板100中边框区B的面积，进而可以增大显示区A在显示基板100中的面积比例，进而有利于实现显示基板100及显示装置1000的窄边框设计。
示例性的，由于至少一个移位寄存器GOA设置在衬底与发光器件层之间，且该移位寄存器GOA在衬底上的正投影与上述像素电路层在衬底上的正投影无交叠，而显示区A的面积是一定的，从而使得至少一个移位寄存器电路GOA所占用的面积会对像素电路层中的多个像素电路10所占用的面积进行压缩，而多个像素电路10所驱动的发光器件层的多个发光器件20所占用的面积未发生减少，就会使得部分像素电路10与其所驱动的发光器件20之间会发生错位，也就是说，显示基板100中的该部分像素电路10与其所驱动的发光器件20未进行正对设置，或该部分像素电路10与其所驱动的发光器件20之间的距离较远。
示例性的，移位寄存器GOA也可以设置在边框区B。
在一些示例中，如图5a及图5c所示，显示基板100还包括：位于显示区A的扇出单元Fanout。扇出单元Fanout位于上述衬底与发光器件层之间，且扇出单元Fanout在衬底上的正投影与上述像素电路层在衬底上的正投影无交叠。
示例性的，上述“无交叠”指的是，扇出单元Fanout与像素电路层中的像素电路10在沿显示基板100的厚度方向上，没有相互覆盖的部分。
示例性的，扇出单元Fanout可以位于显示区A中靠近显示驱动IC的区域。
由于上述扇出单元Fanout与像素电路层均位于衬底与发光器件层之间，且在衬底上的正投影无交叠，因此，可以在同一套制备工艺中形成扇出单元Fanout与像素电路层中的像素电路10。
例如，扇出单元Fanout可以与显示装置1000的显示驱动IC耦接。
示例性的，扇出单元Fanout可以包括数据扇出线、第一电压扇出线等。
例如，显示驱动IC可以为扇出单元Fanout的数据扇出线提供数据信号，为扇出单元Fanout的第一电压扇出线提供第一电压信号等。数据扇出线可以与数据信号线Data耦接，进而可以向像素电路10传输数据信号。第一电压扇出线可以与第一电压信号线VDD耦接，进而可以向像素电路10传输第一电压信号。
采用上述设置方式，将扇出单元Fanout设置在显示区A，可以节省其所占据的边框区B的面积，进而可以减小显示基板100中边框区B的面积，进而可以增大显示区A在显示基板100中的面积比例，进而有利于实现显示基板100及显示装置1000的窄边框设计。
示例性的，由于扇出单元Fanout位于上述衬底与发光器件层之间，且扇出单元Fanout在衬底上的正投影与上述像素电路层在衬底上的正投影无交叠，而显示区A的面积是一定的，从而使得扇出单元Fanout所占用的面积会对像素电路层中的多个像素电路10所占用的面积进行压缩，而发光器件层的多个发光器件20所占用的面积未发生减少，就会使得部分像素电路10与其所驱动的发光器件20之间的发生错位，也就是说，显示基板100中的该部分像素电路10与其所驱动的发光器件20未进行正对设置，或该部分像素电路10与其所驱动的发光器件20之间的距离较远。
示例性的，扇出单元Fanout也可以位于显示基板100的边框区B。
在一些示例中，如图5a及图5d所示，显示基板100还包括：光学元件区OC及光学元件200。
示例性的，光学元件200在显示基板100所在平面的正投影，位于显示基板100的光学元件区OC内。
示例性的，光学元件区OC中可以仅设置少量像素电路10或不设置像素电路10。这样可以使得显示基板100中位于光学元件区OC的区域的透光率，大于显示基板100中位于显示区A的区域的透光率。
例如，光学元件区OC也可以用于显示画面。
例如，上述光学元件200可以为摄像头、指纹识别传感器以及红外传感器等。
采用上述设置方式，可以确保有足够的光线可以透过光学器件区OC到达光学元件200， 使得光学元件200能够采集到光线，进而保证光学元件200能够正常工作，又能够提高显示基板100中用于显示画面的区域(例如上述显示区A)的面积在显示基板100中的面积比例，进而有利于实现显示基板100及显示装置1000的全面屏设计。
示例性的，为保证显示基板100显示效果的均一性，光学元件区OC的发光器件20的密度与显示区A的所有发光器件20的密度是相同的，而为保证光学元件200能够接收到足够的光线，在显示基板100中位于光学元件区OC的区域，可以仅设置少量像素电路10或不设置像素电路10，由此，就会使得位于光学元件区OC的发光器件20的数量大于位于光学元件区OC的像素电路10的数量，进而使得光学元件区OC的部分发光器件20所对应的部分像素电路10设置在显示区A中除光学元件区OC以外的区域，就会使得该部分像素电路10与其所驱动的发光器件20之间发生错位，也就是说，显示基板100中的该部分像素电路10与其所驱动的发光器件20未进行正对设置，或该部分像素电路10与其所驱动的发光器件20之间的距离较远。
在一种实现方式中，显示基板的移位寄存器或扇出单元设置在显示区，或者显示基板中的光学元件区仅设置少量或不设置像素电路，就会出现部分像素电路10’与其相应发光器件20’未正对设置，该部分像素电路10’与其相应的发光器件20’之间的距离较远，如图6a所示。由此，如图6b所示，在像素电路的发光阶段，上述部分像素电路10’中的第四节点N4的负载较大(相对于正对设置的像素电路与发光器件来说)，对第四节点N4预充电至预设发光电压的时间较长，进而使得该部分像素电路10’中驱动发光器件20’发光的驱动电流较小，从而使得该部分发光器件20’的启亮较慢或者发光亮度较低，从而使得显示基板及显示装置容易出现整体发光不均一的现象，这种现象在低灰阶的情况下尤为明显。
基于此，本发明的一些实施例提供了一种显示基板100，如图2所示，显示基板100中，多个像素电路10包括多个第一像素电路11和多个第二像素电路12。上述多个发光器件20包括：多个第一发光器件21和多个第二发光器件22。
在一些示例中，如图2及图7a所示，第一像素电路11与第一发光器件21耦接。第一像素电路11与第一发光器件21至少部分正对设置。
示例性的，上述“至少部分正对设置”指的是，第一像素电路11在显示基板100所在平面上的正投影，与其所驱动的第一发光器件21在显示基板100所在平面上的正投影，部分重合或完全重合。
采用上述设置方式，可以使得第一像素电路11中第四节点N4的负载较小，进而在发光阶段，较短的时间即可完成对第四节点N4的充电，从而可以使得第四节点N4较快地到达预设电压，使得第一发光器件21能够迅速启亮，且能够在预设电压下发出与预设灰阶相符的光，减缓甚至避免显示基板100及显示装置1000出现亮度不均一的现象。
需要说明的是，图2中仅示意出了显示基板100中第一像素电路11、第二像素电路12、第一发光器件21、第二发光器件22及移位寄存器GOA等结构的相对位置关系，未对上述结构相互之间的连接关系进行示意。
在一些示例中，如图2及图7b所示，第二像素电路12与第二发光器件22耦接。第二像素电路12在显示基板100所在平面的正投影，与其所驱动的第二发光器件22在显示基板100所在平面的正投影无交叠。
示例性的，沿显示基板100厚度的方向，第二像素电路12与其所驱动的第二发光器件22为错位设计，二者没有正对的部分。第二像素电路12在显示基板100所在平面上的正投影的边界线，与其所驱动的第二发光器件22在显示基板100所在平面的正投影的边界线，没有重合的部分。
示例性的，在显示基板100的显示区A包括位于衬底和像素电路层之间的移位寄存器GOA，和/或，扇出单元Fanout，和/或，显示区A包括光学元件区OC的情况下，第二像素电路12一般位于靠近上述移位寄存器GOA，和/或，扇出单元Fanout，和/或，光学元件区OC所在的区域。以图2所示的显示基板100包括位于显示区A的移位寄存器GOA的情况下，第二像素电路12位于靠近边框区B与显示区A的边界线的区域。
像素电路10中的驱动晶体管T3和补偿晶体管T2的设置方式有多种，可以根据实际需要进行设置，本发明对此不作限制。
在一些示例中，如图9所示，第一像素电路11中的驱动晶体管T3的沟道宽长比，大于第二像素电路12中的驱动晶体管T3的沟道宽长比。
图9中(a)示意的是第一像素电路11中的驱动晶体管T3的部分结构图，图9中(b)示意的是第二像素电路12中的驱动晶体管T3的部分结构图。
示例性的，驱动晶体管T3的沟道宽长比，指的是，驱动晶体管T3的沟道部的沟道宽度，与该沟道部的长度的比值。
需要说明的是，晶体管的宽长比与晶体管导通情况下的开态电流相关。晶体管的宽长比越大，其对应的开态电流越大。
采用上述设置方式，由于第二像素电路12中的驱动晶体管T3的沟道宽长比小于第一像素电路11中的驱动晶体管T3的沟道宽长比，使得第二像素电路12中的驱动晶体管T3的开态电流小于第一像素电路11中的驱动晶体管T3的开态电流，由此，在像素电路的数据写入及补偿阶段，第二像素电路12中由驱动晶体管T3经补偿晶体管T2对第一节点N1的充电欠充分，充电结束后，第二像素电路12中的第一节点N1的电位小于第一像素电路11的第一节点N1的电位，这样，在预设灰阶为低灰阶的情况下，第二像素电路12的发光阶段中，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值(此处的驱动电流的起始值，指的是，驱动电流的值趋于稳定时的驱动电流的大小，如本发明图14a中t1或t2对应的驱动电流的大小) 较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流(此处的驱动电流，指的是在一个发光阶段中驱动电流的平均值)增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
在一些示例中，如图12所示，第一像素电路11中的补偿晶体管T2的沟道电容，大于第二像素电路12中的补偿晶体管T2的沟道电容。
示例性的，上述补偿晶体管T2的沟道电容，指的是，补偿晶体管T2的沟道部，与补偿晶体管T2的栅极所构成的电容器的电容。补偿晶体管T2的栅极与扫描信号线Gate为一体结构。
需要说明的是，由于沟道部为半导体层中与栅极正对的部分，因此，沟道面积的大小，即为沟道部的沟道电容器的大小。由此，沟道面积越大，沟道部的沟道电容器的电容越大。
采用上述设置方式，在补偿晶体管T2关闭的情况下，扫描信号线Gate所传输的扫描信号的电平由低电平变为高电平，也就是说，补偿晶体管T2的栅极电压增大，进而使得与第一节点N1连接的补偿晶体管T2的第二极的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的沟道电容小于第一像素电路11中的补偿晶体管T2的沟道电容，在补偿晶体管T2的栅极电压增大的情况下，第二像素电路12中的补偿晶体管T2的沟道部的电压增加的幅度小于第一像素电路11中的补偿晶体管T2的沟道部的电压增加的幅度，由于补偿晶体管T2的沟道部通过补偿晶体管T2的第二极与第一节点N1连接，也就是使得第二像素电路12中第一节点N1的电压增加的幅度小于第一像素电路11中第一节点N1的电压增加的幅度，也就使得第二像素电路12的第一节点N1的电位受到其相应的补偿晶体管T2的沟道电容器的影响较小，第二像素电路12中第一节点N1的电位低于第一像素电路11中第一节点N1的电位，进而使得在发光阶段，受第一节点N1控制的第二像素电路12的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，使得通过第二像素电路12的驱动晶体管T3的驱动电流(此处的驱动电流，指的是在一个发光阶段中驱动电流的平均值)增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下的均一性。
在一些示例中，第一像素电路11中的驱动晶体管T3的沟道宽长比，大于第二像素电路12中的驱动晶体管T3的沟道宽长比。并且，第一像素电路11中的补偿晶体管T2的沟道电容，大于第二像素电路12中的补偿晶体管T2的沟道电容。
采用上述设置方式，由于第二像素电路12中的驱动晶体管T3的沟道宽长比相对较小， 第二像素电路12中的驱动晶体管T3的开态电流越小，由此，在像素电路的数据写入及补偿阶段，由驱动晶体管T3经补偿晶体管T2对第一节点N1的充电欠充分，充电结束后第二像素电路12中的第一节点N1的电位小于预设的电位值。并且，在补偿晶体管T2关闭的情况下，扫描信号线Gate所传输的扫描信号由低电平变为高电平，也就是说，补偿晶体管T2的栅极电压增大，进而使得与补偿晶体管T2的第二极连接的第一节点N1的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的沟道电容相对较小，在补偿晶体管T2的栅极电压增大的情况下，补偿晶体管T2的第二极的电压增加的幅度较小，也就使得第一节点N1的电位受到沟道电容器的影响较小，第二像素电路12中第一节点N1的电位增加的幅度相对较小，第二像素电路12中第一节点N1的电位较低。进而使得在发光阶段，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流(此处的驱动电流，指的是在一个发光阶段中驱动电流的平均值)增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
需要说明的是，在第一像素电路11中的驱动晶体管T3的沟道宽长比，大于第二像素电路12中的驱动晶体管T3的沟道宽长比的情况下，第一像素电路11中的驱动晶体管T3和第二像素电路12中的驱动晶体管T3的设置方式有多种，可以根据实际需要进行设置，本发明对此不作限制。
在一些实施例中，如图9所示，第一像素电路11中的驱动晶体管T3的沟道宽度，大于第二像素电路12中的驱动晶体管T3的沟道宽度。
图9中(a)示意的是第一像素电路11中的驱动晶体管T3的部分结构图，图9中(b)示意的是第二像素电路12中的驱动晶体管T3的部分结构图。
在一些示例中，如图4及图9所示，驱动晶体管T3的沟道的形状为折线形，该折线形的沟道包括沿第一方向X延伸的部分和沿第二方向Y延伸的部分。如图8a所示，该驱动晶体管T3的沟道宽度为，该沟道在沿第一方向X延伸部分的宽度W31、W32、W33的尺寸，与该沟道在第二方向Y延伸部分的宽度W34、W35的尺寸的平均值，即W3＝(W31+W32+W33+W34+W35)/5。
采用上述设置方式，设置第一像素电路11中的驱动晶体管T3的沟道宽度，大于第二像素电路12中的驱动晶体管T3的沟道宽度，从而使得第一像素电路11中的驱动晶体管T3的沟道宽长比，大于第二像素电路12中的驱动晶体管T3的沟道宽长比，使得第二像素电路12中的驱动晶体管T3的开态电流越小，由此，在第二像素电路12中由驱动晶体管T3经补偿晶体管T2对第一节点N1的充电欠充分，充电结束后第二像素电路12中的第一节点N1的电位小于第一像素电路11的第一节点N1的电位，这样，在预设灰阶为低灰阶的情况下，第二像素电路12的发光阶段中，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
示例性的，在第一像素电路11中的驱动晶体管T3的沟道宽度，大于第二像素电路12中的驱动晶体管T3的沟道宽度的情况下，第一像素电路11中的驱动晶体管T3的沟道长度，与第二像素电路12中的驱动晶体管T3的沟道长度，可以相同，也可以不同。
在一些示例中，第一像素电路11中的驱动晶体管T3的沟道宽度，与第二像素电路12中的驱动晶体管T3的沟道宽度的差值小于或等于0.6μm。
示例性的，第一像素电路11中的驱动晶体管T3的沟道宽度，与第二像素电路12中的驱动晶体管T3的沟道宽度的差值可以为0.6μm、0.5μm、0.4μm、0.3μm、0.2μm或0.1μm等。
采用上述设置方式，在第一发光器件21和第二发光器件22的预设灰阶相同的情况下，使得第二像素电路12的驱动晶体管T3的沟道宽长比小于第一像素电路11中的驱动晶体管T3的沟道宽长比，第二像素电路12中的驱动晶体管T3的开态电流小于第一像素电路11中的驱动晶体管T3的开态电流，由此，在像素电路的数据写入及补偿阶段，第二像素电路12中由驱动晶体管T3经补偿晶体管T2对第一节点N1的充电欠充分，充电结束后第二像素电路12中的第一节点N1的电位小于第一像素电路11的第一节点N1的电位，这样，在预设灰阶为低灰阶的情况下，第二像素电路12的发光阶段中，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
在一些示例中，第一像素电路11中的驱动晶体管T3的沟道宽度，与第二像素电路12中的驱动晶体管T3的沟道宽度的比值，大于1小于或等于1.21。
示例性的，在第一像素电路11中的驱动晶体管T3的沟道宽度为3.5μm的情况下，第二像素电路12中的驱动晶体管T3的沟道宽度可以为3.4μm、3.3μm、3.2μm、3.1μm或2.9μm，此时，第一像素电路11中的驱动晶体管T3的沟道宽度，与第二像素电路12中的 驱动晶体管T3的沟道宽度的比值分别为1.02、1.06、1.09、1.13、1.21。
在一些实施例中，如图10所示，第一像素电路11中的驱动晶体管T3的沟道长度，大于第二像素电路12中的驱动晶体管T3的沟道长度。
图10中(a)示意的是第一像素电路11中的驱动晶体管T3的部分结构图，图10中(b)示意的是第二像素电路12中的驱动晶体管T3的部分结构图。
在一些示例中，如图4及图8b所示，驱动晶体管T3的沟道部的形状为折线形，该折线形的沟道部包括沿第一方向X延伸的部分和沿第二方向Y延伸的部分。如图8b所示，该驱动晶体管T3的沟道长度为，该沟道的沿第一方向X延伸的三个延伸部分的长度L31、L32、L33之和的尺寸，与该沟道的沿第二方向Y延伸部分的延伸长度L34、L35的尺寸之和，即L3＝L31+L32+L33+L34+L35。
采用上述设置方式，可以使得第一像素电路11中的驱动晶体管T3的沟道宽长比，大于第二像素电路12中的驱动晶体管T3的沟道宽长比，第二像素电路12中的驱动晶体管T3的开态电流小于第一像素电路11中的驱动晶体管T3的开态电流，由此，在像素电路的数据写入及补偿阶段，第二像素电路12中由驱动晶体管T3经补偿晶体管T2对第一节点N1的充电欠充分，充电结束后第二像素电路12中的第一节点N1的电位小于第一像素电路11的第一节点N1的电位，这样，在预设灰阶为低灰阶的情况下，第二像素电路12的发光阶段中，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
示例性的，在第一像素电路11中的驱动晶体管T3的沟道长度，大于第二像素电路12中的驱动晶体管T3的沟道长度的情况下，第一像素电路11中的驱动晶体管T3的沟道宽度，与第二像素电路12中的驱动晶体管T3的沟道宽度，可以相同，也可以不同。
在一些示例中，第一像素电路11中的驱动晶体管T3的沟道长度，与第二像素电路12中的驱动晶体管T3的沟道长度的差值小于或等于1.4μm。
示例性的，第一像素电路11中的驱动晶体管T3的沟道长度，与第二像素电路12中的驱动晶体管T3的沟道长度的差值可以为0.4μm、0.7μm、1.0μm、1.2μm、1.4μm等。
采用上述设置方式，在第一发光器件21和第二发光器件22的预设灰阶相同的情况下，使得第二像素电路12的驱动晶体管T3的沟道宽长比较小，进而使得第二像素电路12的驱动晶体管T3的开态电流较小，对于第一节点N1的充电欠充分，进而在发光阶段使得第二像素电路12中的驱动晶体管T3的导通更充分，使得通过驱动晶体管T3的驱动电流得到一定程度的增大，使得第二发光器件22的发光亮度与第一发光器件21的发光亮度差异较小甚至趋于相同，从而提高显示基板100及显示装置1000在低灰阶显示情况下均一性。
在一些示例中，第一像素电路11中的驱动晶体管T3的沟道长度，与第二像素电路12中的驱动晶体管T3的沟道长度的比值，小于1且大于或等于0.94。
示例性的，在第一像素电路11中的驱动晶体管T3的沟道长度为24μm的情况下，第二像素电路12中的驱动晶体管T3的沟道长度可以为24.3μm、24.6μm、24.9μm、25.1μm、或25.4μm，此时，第一像素电路11中的驱动晶体管T3的沟道长度，与第二像素电路12中的驱动晶体管T3的沟道长度的比值分别为0.99、0.98、0.96、0.95、0.94。
在一些实施例中，如图12所示，第一像素电路11中的补偿晶体管T2的沟道宽度，大于第二像素电路12中的补偿晶体管T2的沟道宽度。
图12中(a)示意的是第一像素电路11中的驱动晶体管T3的部分结构图，图12中(b)示意的是第二像素电路12中的驱动晶体管T3的部分结构图。
在一些示例中，如图4所示，补偿晶体管T2为双栅型晶体管。如图11a所示，补偿晶体管T2包括第一子补偿晶体管T21和第二子补偿晶体管T22。补偿晶体管T2沟道宽度为，第一子补偿晶体管T21的沟道宽度W21和第二子补偿晶体管T22的沟道宽度W22的平均值，即W2＝(W21+W22)/2。
采用上述设置方式，可以使得第一像素电路11中的补偿晶体管T2的沟道电容，小于第二像素电路12中的补偿晶体管T2的沟道电容，由此，在补偿晶体管T2关闭的情况下，扫描信号线Gate所传输的扫描信号的电平由低电平变为高电平，也就是说，补偿晶体管T2的栅极电压增大，进而使得与第一节点N1连接的补偿晶体管T2的第二极的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的沟道电容小于第一像素电路11中的补偿晶体管T2的沟道电容，在补偿晶体管T2的栅极电压增大的情况下，第二像素电路12中的补偿晶体管T2的沟道部的电压增加的幅度小于第一像素电路11中的补偿晶体管T2的沟道部的电压增加的幅度，由于补偿晶体管T2的沟道部通过补偿晶体管T2的第二极与第一节点N1连接，也就是使得第二像素电路12中第一节点N1的电压增加的幅度小于第一像素电路11中第一节点N1的电压增加的幅度，也就使得第二像素电路12的第一节点N1的电位受到其相应的补偿晶体管T2的沟道电容器的影响较小，第二像素电路12中第一节点N1的电位低于第一像素电路11中第一节点N1的电位，进而使得在发光阶段，受第一节点N1控制的第二像素电路12的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下的均一性。
在一些示例中，第一像素电路11中的补偿晶体管T2的沟道宽度，与第二像素电路12中的补偿晶体管T2的沟道宽度的差值小于或等于0.3μm。
示例性的，第一像素电路11中的补偿晶体管T2的沟道宽度，与第二像素电路12中的补偿晶体管T2的沟道宽度的差值可以为0.11μm、0.15μm、0.21μm、0.27μm或0.30μm。
采用上述设置方式，在第一发光器件21和第二发光器件22的预设灰阶相同的情况下，使得第二像素电路12的补偿晶体管T2的沟道电容比较小，由此，在补偿晶体管T2关闭的情况下，补偿晶体管T2的栅极电压增大，进而使得与第一节点N1连接的补偿晶体管T2的第二极的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的沟道电容相对较小，在补偿晶体管T2的栅极电压增大的情况下，补偿晶体管T2的第二极的电压增加的幅度较小，也就使得第一节点N1的电位受到沟道电容器的影响较小，第二像素电路12中第一节点N1的电位增加的幅度相对较小，第二像素电路12中第一节点N1的电位较低，进而使得在发光阶段，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流较大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000的显示均一性。
在一些示例中，第一像素电路11中的补偿晶体管T2的沟道宽度，与第二像素电路12中的补偿晶体管T2的沟道宽度的比值,大于1且小于等于1.14。
示例性的，在第一像素电路11中的补偿晶体管T2的沟道宽度为2.5μm的情况下，第二像素电路12中的补偿晶体管T2的沟道宽度可以为2.2μm、2.3μm或2.4μm，此时，第一像素电路11中的补偿晶体管T2的沟道宽度，与第二像素电路12中的补偿晶体管T2的沟道宽度的比值分别为1.14、1.09、1.04。
在一些示例中，如图13所示，第一像素电路11中的补偿晶体管T2的沟道长度，小于第二像素电路12中的补偿晶体管T2的沟道长度。
图13中(a)示意的是第一像素电路11中的驱动晶体管T3的部分结构图，图13中(b)示意的是第二像素电路12中的驱动晶体管T3的部分结构图。
如图11b所示，该补偿晶体管T2的沟道长度为，第一子补偿晶体管T21的沟道长度L21和第二子补偿晶体管T22的沟道长度L22的尺寸之和，即L2＝L21+L32。
采用上述设置方式，在第一像素电路11中的补偿晶体管T2的沟道宽度，与第二像素电路12中的补偿晶体管T2的沟道宽度相同的情况下，第一像素电路11中的补偿晶体管T2的沟道电容，小于第二像素电路12中的补偿晶体管T2的沟道电容，由此，在补偿晶体管T2关闭的瞬间，补偿晶体管T2的栅极电压增大，进而使得与第一节点N1连接的补偿晶体管T2的第二极的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的 沟道电容相对较小，在补偿晶体管T2的栅极电压增大的情况下，补偿晶体管T2的第二极的电压增加的幅度较小，也就使得第一节点N1的电位受到沟道电容器的影响较小，第二像素电路12中第一节点N1的电位增加的幅度相对较小，第二像素电路12中第一节点N1的电位较低，进而使得在发光阶段，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流较大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000的显示均一性。
在一些示例中，第一像素电路11中的补偿晶体管T2的沟道长度，与第二像素电路12中的补偿晶体管T2的沟道长度的差值小于或等于0.8μm。
示例性的，第一像素电路11中的补偿晶体管T2的沟道长度，与第二像素电路12中的补偿晶体管T2的沟道长度的差值可以为0.1μm、0.2μm、0.5μm、0.7μm或0.8μm。
采用上述设置方式，在第一发光器件21和第二发光器件22的预设灰阶相同的情况下，使得第二像素电路12的补偿晶体管T2的沟道电容比较小，由此，在补偿晶体管T2关闭的情况下，扫描信号线Gate所传输的扫描信号的电平由低电平变为高电平，也就是说，补偿晶体管T2的栅极电压增大，进而使得与第一节点N1连接的补偿晶体管T2的第二极的电压也会相应的增大。由于第二像素电路12中的补偿晶体管T2的沟道电容小于第一像素电路11中的补偿晶体管T2的沟道电容，在补偿晶体管T2的栅极电压增大的情况下，第二像素电路12中的补偿晶体管T2的沟道部的电压增加的幅度小于第一像素电路11中的补偿晶体管T2的沟道部的电压增加的幅度，由于补偿晶体管T2的沟道部通过补偿晶体管T2的第二极与第一节点N1连接，也就是使得第二像素电路12中第一节点N1的电压增加的幅度小于第一像素电路11中第一节点N1的电压增加的幅度，也就使得第二像素电路12的第一节点N1的电位受到其相应的补偿晶体管T2的沟道电容器的影响较小，第二像素电路12中第一节点N1的电位低于第一像素电路11中第一节点N1的电位，进而使得在发光阶段，受第一节点N1控制的第二像素电路12的驱动晶体管T3的导通更加充分，进而使得通过第二像素电路12的驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000在低灰阶显示情况下的均一性。
在一些示例中，第一像素电路11中的补偿晶体管T2的沟道长度，与第二像素电路12中的补偿晶体管T2的沟道长度的比值，大于1且小于等于1.15。
示例性的，在第一像素电路11中的补偿晶体管T2的沟道长度为6.2μm的情况下，第二像素电路12中的补偿晶体管T2的沟道长度可以为5.4μm、5.5μm、5.7μm、5.8μm或6.1μm，此时，第一像素电路11中的补偿晶体管T2的沟道长度，与第二像素电路12中的补偿晶体管T2的沟道长度的比值分别为1.15、1.13、1.09、1.07、1.02。
在一些实施例中，如图7b所示，显示基板100还包括：多条引线30。第二像素电路12与第二发光器件22之间通过引线耦接。
在一些示例中，多条引线30的一端与第二像素电路12的第四节点N4耦接，多条引线30的另一端与第二发光器件22的第一电极耦接，从而实现第二像素电路12与第二发光器件22的耦接。
在一种实现方式中，由于引线具有一定的长度，引线会跨过至少部分像素电路的上方或跨过部分移位寄存器单元或跨过部分扇出单元等电路结构，引线就会与上述电路结构之间形成寄生电容器，从而使得引线上传输的电信号受到该寄生电容的影响，进而使得引线上的电信号需要经过较长的时间才能传输至发光器件的第一电极，或者较长引线的存在使得传输的电信号经过一定的损耗后才传输至发光器件的第一电极，进而使得发光器件的第一电极经过较长的时间才能达到预设电位，使得发光器件的启亮较晚或发光亮度较低。
而在本发明中，设置与引线30相连接的第二像素电路12中的驱动晶体管T3的沟道宽长比小于第一像素电路11中的驱动晶体管T3的沟道宽长比，和/或,第二像素电路12中的补偿晶体管T2的沟道电容小于第一像素电路11中的补偿晶体管T2的沟道电容，从而使得在像素电路的数据写入及补偿阶段结束后，第二像素电路12中的第一节点N1的电位小于预设的电位值，进而使得在发光阶段，受第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流的起始值较大，从而可以补偿上述由于第四节点N4预充电时间较长对驱动电流值的整体拉低，从而使得通过第二像素电路12的驱动晶体管T3的驱动电流增大，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设低灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000的在低灰阶显示情况下的显示均一性。
需要说明的是，引线30的长度越长，引线30与像素电路或移位寄存器单元或扇出单元等电路结构的正对面积越大，引线30与上述电路结构形成的寄生电容器的电容越大，且引线30越长，电信号在引线30上的损耗量越大，从而造成第四节点N4的预充电时间越长或驱动电流的起始值越低，进而使得该引线30传输的驱动电流越小。
在一些示例中，第二像素电路12中的驱动晶体管T3的沟道宽长比，和，与该第二像素电路12连接的引线30的长度，呈负相关。
示例性的，由于多个第二像素电路12与其所驱动的第二发光器件22之间的间距不同，相应的引线30的长度也不相同。多个第二像素电路12与其所驱动的第二发光器件22之间的间距越大，相应的引线30的长度越长。
例如，引线30的长度可以为34μm、80μm、100μm、150μm、195μm等。
例如，多条引线30可以位于显示基板100的发光器件层。
此处的“负相关”指的是，与第二像素电路12连接的引线30的长度越长，该第二像素电路12中的驱动晶体管T3的沟道宽长比越小。
采用上述设置方式，在与第二像素电路12连接的引线30的长度越长的情况下，设置第二像素电路12中的驱动晶体管T3的沟道宽长比越小，进而使得第二像素电路12的第一节点N1的电位越低，使得第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流的起始值较大，弥补由于引线30与上述电路结构形成的寄生电容及引线30的长度使电信号损耗而造成的驱动电流起始值的下降，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000的显示均一性。
在一些示例中，第二像素电路12中的补偿晶体管T2的沟道电容，和，与第二像素电路12连接的引线30的长度，呈负相关。
此处的“负相关”指的是，与第二像素电路12连接的引线30的长度越长，该第二像素电路12中的补偿晶体管T2的沟道电容越小。
采用上述设置方式，在与第二像素电路12连接的引线30的长度越长的情况下，设置第二像素电路12的补偿晶体管T2的沟道电容越小，进而使得第二像素电路12的第一节点N1的电位越低，使得第一节点N1控制的驱动晶体管T3的导通更加充分，进而使得通过驱动晶体管T3的驱动电流的起始值较大，弥补由于引线30与上述电路结构形成的寄生电容及引线30的长度使电信号损耗而造成的驱动电流起始值的下降，使得第二发光器件22的发光亮度得到提升，进而可以缩小在相同的预设灰阶下第二发光器件22与第一发光器件21的发光亮度差异，提高显示基板100及显示装置1000的显示均一性。
示例性的，如图2所示，以显示基板100包括移位寄存器GOA的情况为例，多个第一像素电路11、多个第二像素电路12及多个移位寄存器GOA在显示区A呈多行多列排布，多个发光器件20呈多行多列排布。以显示基板100的中心线NN’右侧的区域为例，第n列第二像素电路12与其所驱动的第二发光器件22在俯视图(图7a)中的间距，与第n+1列第二像素电路与其所驱动的第二发光器件22在俯视图(图7a)中的间距，与第n+2列像素电路与其所驱动的第二发光器件22在俯视图(图7a)中的间距，……，呈渐进式增大，则其所对应第二像素电路12的驱动晶体管T3的沟道宽长比呈渐进式减小，或者其所对应第二像素电路12的补偿晶体管T2的沟道电容呈渐进式减小。
本发明将第二像素电路12的驱动晶体管T3的沟道宽度设置为，相对于第一像素电路11的驱动晶体管T3的沟道宽度减小0.6μm，并对此情况下的第一像素电路11第一节点N1的电信号及驱动电流，和第二像素电路12的第一节点N1的电信号及驱动电流I进行了仿真计算，仿真结果如图14a所示。
本发明将第二像素电路12的驱动晶体管T3的沟道长度设置为，相对于第一像素电路11的驱动晶体管T3的沟道长度增加1.4μm，并对此情况下的第一像素电路11第一节点N1的电信号及驱动电流I，和第二像素电路12的第一节点N1的电信号及驱动电流进行了仿真计算，仿真结果如图14b所示。
本发明将第二像素电路12的补偿晶体管T2的沟道宽度设置为，相对于第一像素电路11的补偿晶体管T2的沟道宽度减小0.3μm，并对此情况下的第一像素电路11第一节点N1的电信号及驱动电流I，和第二像素电路12的第一节点N1的电信号及驱动电流进行了仿真计算，仿真结果如图14c所示。
本发明将第二像素电路12的补偿晶体管T2的沟道长度设置为，相对于第一像素电路11的补偿晶体管T2的沟道长度减小0.8μm，并对此情况下的第一像素电路11第一节点N1的电信号及驱动电流I，和第二像素电路12的第一节点N1的电信号及驱动电流进行了仿真计算，仿真结果如图14d所示。
由图14a～图14b可知，对第二像素电路12的驱动晶体管T3，相对于第一像素电路11的驱动晶体管T3的沟道宽度减小0.6μm或沟道长度增加1.4μm，经过仿真检测及计算，第二像素电路12中第一节点N1的电压UN12小于第一像素电路11中第一节点N1的电压UN11，且第二像素电路12的启亮时间t2晚于第一像素电路11的启亮时间t1，第二像素电路12的驱动电流I2的起始值大于第一像素电路11的驱动电流I1的起始值。
需要说明的是，像素电路的启亮时间，指的是有驱动电流产生且驱动电流的大小大致趋于平稳的时间。像素电路的驱动电流的大小为一个发光阶段中的驱动电流的平均值。以图14a为例，第二像素电路12的驱动电流I2为，在使能信号EM的有效电平范围内(图中对应的两个方波之间，约为16.8ms～33.5ms区间内)，驱动电流的平均值。
由此可见，将第二像素电路12的驱动晶体管T3，相对于第一像素电路11的驱动晶体管T3的沟道宽度减小0.6μm或沟道长度增加1.4μm，可以使得第二像素电路12的第一节点N1的电压降低，使得第二像素电路12驱动晶体管T3的导通更加充分，从而使得第二像素电路12的驱动电流的起始值得到一定程度的增大，弥补部分由于启亮时间较晚对驱动电流值的拉低，使得第二像素电路12的驱动电流得到一定程度的增大，使得第二像素电路12的驱动电流与第一像素电路11的驱动电流的大小趋于一致，进而可以提高显示基板100及显示装置1000的显示均一性。
由图14c～图14d可知，对第二像素电路12的补偿晶体管T2，相对于第一像素电路11的补偿晶体管T2的沟道宽度减小0.3μm或沟道长度减小0.8μm，经过仿真检测及计算，第二像素电路12中第一节点N1的电压UN12小于第一像素电路11中第一节点N1的电压UN11，且第二像素电路12的启亮时间晚于第一像素电路11的启亮时间，第二像素电路12的驱动电流I2的起始值大于第一像素电路11的驱动电流I1的起始值。
由此可见，将第二像素电路12的补偿晶体管T2，相对于第一像素电路11的补偿晶体管T2的沟道宽度减小0.3μm或沟道长度减小0.8μm，可以使得第二像素电路12的第一节点N1的电压降低，使得第二像素电路12的驱动晶体管T3的导通更加充分，从而使得第二像素电路12的驱动电流得到一定程度的增大，弥补部分由于启亮时间较晚对驱动电流值的拉低，使得第二像素电路12的驱动电流得到一定程度的增大，使得第二像素电路12的驱动电流与第一像素电路11的驱动电流的大小趋于一致，进而可以提高显示基板100及显示装置1000的显示均一性。
需要说明的是，像素电路10与所驱动的发光器件20构成子像素。第一像素电路11与其所驱动的第一发光器件21构成第一子像素，第二像素电路12与其所驱动的第二发光器件22构成第二子像素。在相同的预设灰阶下，子像素所发出的光的颜色不同，其所需要的驱动电流也不相同。
因此，本发明将不同颜色的第二子像素的驱动电流的电流差异△I/I1，对应不同的第二像素电路12的驱动晶体管T3、不同的第二像素电路12的补偿晶体管T2进行了计算，并作图，具体地，如图15a～图15d所示。
需要说明的是，上述驱动电流的电流差异△I/I1中，I1为第一像素电路11的驱动电流。△I为第二像素电路12的驱动电流I2与第一像素电路11的驱动电流I1的差值。
具体地，将第二像素电路12的驱动晶体管T3的沟道宽度W设置为，相对于第一像素电路11的驱动晶体管T3的沟道宽度依次减小0.2μm、0.4μm、0.6μm，然后将上述沟道宽度的渐进式减小对不同颜色第二子像素中驱动电流的电流差异作图，得到图15a。将第二像素电路12的驱动晶体管T3的沟道长度L设置为，相对于第一像素电路11的驱动晶体管T3的沟道长度依次增加0.4μm、0.8μm、1.2μm、1.4μm，然后将上述沟道长度的渐进式增加对不同颜色第二子像素中的驱动电流的电流差异作图，得到图15b。将第二像素电路12的补偿晶体管T2的沟道宽度W设置为，相对于第一像素电路11的补偿晶体管T2的沟道宽度依次减小0.1μm、0.2μm、0.3μm，然后将上述沟道宽度的渐进式减小对不同颜色第二子像素中的驱动电流的电流差异作图，得到图15c。将第二像素电路12的补偿晶体管T2的沟道长度L设置为，相对于第一像素电路11的补偿晶体管T2的沟道长度依次减小0.2μm、0.4μm、0.6μm、0.8μm，然后将上述沟道长度的渐进式减小对不同颜色第二子像素中的驱动电流的电流差异作图，得到图15d。
需要说明的是，图15a～图15d中，R表示红色第二子像素，G表示绿色第二子像素，B表示蓝色第二子像素，图15a中的△W表示第二像素电路12的驱动晶体管T3的沟道宽度相对于第一像素电路11的驱动晶体管T3的沟道宽度的差值，图15b中的△L表示第二像素电路12的驱动晶体管T3的沟道长度相对于第一像素电路11的驱动晶体管T3的沟道长度的差值，图15c中的△W表示第二像素电路12的补偿晶体管T2的沟道宽度相对于第一像素电路11的补偿晶体管T2的沟道宽度的差值，图15d中的△L表示第二像素电路12的补偿晶体管T2的沟道长度相对于第一像素电路11的补偿晶体管T2的沟道长度的差值。为方便描述，以下将上述第二像素电路12与第一像素电路11的驱动晶体管T3、补偿晶体管T2的沟道长度及沟道宽度的差值，统称为第二像素电路12的沟道变化量。
由图15a～图15d可知，随着第二像素电路12的沟道变化量的增大，第二像素电路12的驱动电流的电流差异△I/I1呈逐渐减小的趋势。以图15a中绿色第二子像素G为例，在第二像素电路12的沟道变化量从0μm渐进式地变化至-0.6μm的过程中，绿色第二子像素G中第二像素电路12的驱动电流的电流差异△I/I1由-40％变化至接近于0％左右。在第二像素电路12的驱动晶体管T3的沟道宽度与第一像素电路11的驱动晶体管T3的沟道宽度的差值为0.6μm的情况下，第二像素电路12的驱动电流与第一像素电路11的驱动电流接近于相等，由此，可以极大地提高显示基板100及显示装置1000的显示均一性。
此外，由图15a～图15d可知，随着第二像素电路12的沟道变化量的增大，不同颜色的第二子像素的变化趋势一致。以图15b为例，在第二像素电路12的沟道变化量从0μm渐进式地变化至1.6μm的过程中，绿色第二子像素G中第二像素电路12的驱动电流的电流差异△I/I1由-40％变化至接近于0％左右，红色第二子像素R中第二像素电路12的驱动电流的电流差异△I/I1由-25％变化至接近于0％左右，蓝色第二子像素B中第二像素电路12的驱动电流的电流差异△I/I1由-25％变化至接近于0％左右。在沟道变化量为1.6μm的情况下，绿色第二子像素G、红色第二子像素R、蓝色第二子像素B对应的驱动电流的电流差异△I/I1均趋于0，可见，不同颜色的第二子像素的沟道变化量均适用于上述沟道变化量范围即0μm～1.6μm，且在沟道变化量为1.6μm的情况下，对于第二像素电路12的驱动电流与第一像素电路11的驱动电流的电流差异的改善效果最佳，可以极大地提高显示基板100及显示装置1000的显示均一性。
上述图14a～图14d及图15a～图15d均为在预设低灰阶的情况下进行的仿真及计算，由于驱动电流的电流差异在不同的预设灰阶下会有不同，本发明对较高灰阶下(预设灰阶为L255)，上述第二像素电路12的沟道变化量对应的电流差异进行了计算，得到的计算结果如图16所示。
图16中，“T3W-0.6μm”表示第二像素电路12的驱动晶体管T3的沟道宽度与第一像素电路11的驱动晶体管T3的沟道宽度的差值为-0.6μm，“T3L+1.4μm”表示第二像素电路12的驱动晶体管T3的沟道长度与第一像素电路11的驱动晶体管T3的沟道长度的差值为+1.4μm，“T2W-0.3μm”表示第二像素电路12的补偿晶体管T2的沟道宽度与第一像素电路11的补偿晶体管T2的沟道宽度的差值为-0.3μm，“T2L-0.8μm”表示第二像素电路12的补偿晶体管T2的沟道长度与第一像素电路11的补偿晶体管T2的沟道长度的差值为-0.8μm。“R”表示红色第二子像素，“G”表示绿色第二子像素，“B”表示蓝色第二子像素。
由图16可知，在预设灰阶为L255的情况下，不同颜色的第二子像素的驱动电流的电流差异较小，趋近于0。由此可知，在本发明中设置的第二像素电路12的沟道变化量范围内，显示基板100的低灰阶显示和高灰阶显示均能够实现较为均一的显示效果，明显提高了显示基板100及显示装置1000的显示均一性。
以上，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，包括：多个像素电路及多个发光器件；像素电路包括：驱动晶体管以及与所述驱动晶体管耦接的补偿晶体管；
    所述多个像素电路包括：多个第一像素电路和多个第二像素电路；
    所述多个发光器件包括：多个第一发光器件和多个第二发光器件；
    其中，第一像素电路与第一发光器件耦接，所述第一像素电路与所述第一发光器件至少部分正对设置；
    第二像素电路与第二发光器件耦接；所述第二像素电路在所述显示基板所在平面的正投影，与所述第二发光器件在所述显示基板所在平面的正投影无交叠；
    所述第一像素电路中的驱动晶体管的沟道宽长比，大于所述第二像素电路中的驱动晶体管的沟道宽长比；
    和/或，
    所述第一像素电路中的补偿晶体管的沟道电容，大于所述第二像素电路中的补偿晶体管的沟道电容。
  2. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的驱动晶体管的沟道宽度，大于所述第二像素电路中的驱动晶体管的沟道宽度。
  3. 根据权利要求2所述的显示基板，其中，
    所述第一像素电路中的驱动晶体管的沟道宽度，与所述第二像素电路中的驱动晶体管的沟道宽度的差值小于或等于0.6μm。
  4. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的驱动晶体管的沟道宽度与所述第二像素电路中的驱动晶体管的沟道宽度的比值，大于1、且小于或等于1.21。
  5. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的驱动晶体管的沟道长度，小于所述第二像素电路中的驱动晶体管的沟道长度。
  6. 根据权利要求5所述的显示基板，其中，所述第一像素电路中的驱动晶体管的沟道长度，与所述第二像素电路中的驱动晶体管的沟道长度的差值小于或等于1.4μm。
  7. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的驱动晶体管的沟道长度与所述第二像素电路中的驱动晶体管的沟道长度的比值，小于1、且大于或等于0.94。
  8. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道宽度，大于所述第二像素电路中的补偿晶体管的沟道宽度。
  9. 根据权利要求8所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道宽度，与所述第二像素电路中的补偿晶体管的沟道宽度的差值小于或等于0.3μm。
  10. 根据权利要求8所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道宽度与所述第二像素电路中的补偿晶体管的沟道宽度的比值，大于1、且小于或等于1.14。
  11. 根据权利要求1所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道长度，大于所述第二像素电路中的补偿晶体管的沟道长度。
  12. 根据权利要求11所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道长度，与所述第二像素电路中的补偿晶体管的沟道长度的差值小于或等于0.8μm。
  13. 根据权利要求11所述的显示基板，其中，所述第一像素电路中的补偿晶体管的沟道长度与所述第二像素电路中的补偿晶体管的沟道长度的比值，大于1、且小于或等于1.15。
  14. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：多条引线；
    所述第二像素电路与所述第二发光器件之间通过引线耦接。
  15. 根据权利要求14所述的显示基板，其中，所述第二像素电路中的驱动晶体管的沟道宽长比，及与所述第二像素电路连接的引线的长度，呈负相关；
    和/或，所述第二像素电路中的补偿晶体管的沟道电容，及与所述第二像素电路连接的引线的长度，呈负相关。
  16. 根据权利要求1所述的显示基板，其中，所述像素电路还包括：第一复位晶体管、第一发光控制晶体管、第二发光控制晶体管、第二复位晶体管、开关晶体管和存储电容器；
    所述第一复位晶体管的栅极与第一复位信号线耦接，所述第一复位晶体管的第一极与第一初始信号线耦接，所述第一复位晶体管的第二极与第一节点耦接；所述第一复位晶体管被配置为，在第一复位信号线所提供的第一复位信号的控制下，将所述第一初始信号线提供的第一初始信号传输至所述第一节点；
    所述开关晶体管的栅极与扫描信号线耦接，所述开关晶体管的第一极与数据信号线耦接，所述开关晶体管的第二极与第二节点耦接；所述开关晶体管被配置为，在所述扫描信号线所提供的扫描信号的控制下，将所述数据信号线所提供的数据信号传输至所述第二节点；
    所述第一发光控制晶体管的栅极与使能信号线耦接，所述第一发光控制晶体管的第一极与第一电压信号线耦接，所述第一发光控制晶体管的第二极与所述第二节点耦接；所述第一发光控制晶体管被配置为，在所述使能信号线所提供的使能信号的控制下，将所述第一电压信号线所提供的第一电压信号传输至所述第二节点；
    所述驱动晶体管的栅极与所述第一节点耦接，所述驱动晶体管的第一极与所述第二节点耦接，所述驱动晶体管的第二极与第三节点耦接；所述驱动晶体管被配置为，在所述第一节点的电信号的控制下，将所述第二节点的电信号传输至所述第三节点；
    所述补偿晶体管的栅极与所述第一节点耦接，所述补偿晶体管的第一极与所述第三节点耦接，所述补偿晶体管的第二极与所述扫描信号线耦接；所述补偿晶体管被配置为，在所述扫描信号的控制下，将所述第三节点的电信号传输至所述第一节点；
    所述存储电容器的第一极与所述第一电压信号线耦接，所述存储电容器的第二极与所述第一节点耦接；
    所述第二发光控制晶体管的栅极与所述使能信号线耦接，所述第二发光控制晶体管的第一极与所述第三节点，所述第二发光控制晶体管的第二极与第四节点耦接；所述第二发光控制晶体管被配置为，在使能信号的控制下，将所述第三节点的电信号传输至所述第四节点；
    所述第二复位晶体管的栅极与第二复位信号线耦接，所述第二复位晶体管的第一极与第二初始信号线耦接，所述第二复位晶体管的第二极与所述第四节点耦接；所述第二复位晶体管被配置为，在第二复位信号线所提供的第二复位信号的控制下，将所述第二初始信号线提供的第二初始信号传输至所述第四节点。
  17. 一种显示装置，包括如权利要求1～16中任一项所述的显示基板。
PCT/CN2023/090332 2022-05-18 2023-04-24 显示基板及显示装置 WO2023221747A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210540045.2A CN114843288A (zh) 2022-05-18 2022-05-18 显示基板及显示装置
CN202210540045.2 2022-05-18

Publications (2)

Publication Number Publication Date
WO2023221747A1 WO2023221747A1 (zh) 2023-11-23
WO2023221747A9 true WO2023221747A9 (zh) 2024-02-01

Family

ID=82568983

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/090332 WO2023221747A1 (zh) 2022-05-18 2023-04-24 显示基板及显示装置

Country Status (2)

Country Link
CN (1) CN114843288A (zh)
WO (1) WO2023221747A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114843288A (zh) * 2022-05-18 2022-08-02 京东方科技集团股份有限公司 显示基板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444125B (zh) * 2019-06-25 2022-03-08 荣耀终端有限公司 显示屏、终端
US11735108B2 (en) * 2019-07-31 2023-08-22 Boe Technology Group Co., Ltd. Display substrate and preparation method thereof, display panel, and display device
JP7472124B2 (ja) * 2019-11-29 2024-04-22 京東方科技集團股▲ふん▼有限公司 アレイ基板及びその製作方法、表示装置及び表示基板
CN113725274A (zh) * 2021-09-03 2021-11-30 成都京东方光电科技有限公司 像素电路、显示面板和显示装置
CN114843288A (zh) * 2022-05-18 2022-08-02 京东方科技集团股份有限公司 显示基板及显示装置

Also Published As

Publication number Publication date
WO2023221747A1 (zh) 2023-11-23
CN114843288A (zh) 2022-08-02

Similar Documents

Publication Publication Date Title
US11545088B2 (en) Display panel and display device
US11551617B2 (en) Display device, electronic device, and driving method of display device
WO2019137105A1 (zh) 像素电路、驱动方法、电致发光显示面板及显示装置
US11721282B2 (en) Display substrate and display device
TWI696990B (zh) 像素驅動電路及其驅動方法和電晶體的版圖結構
US11335757B2 (en) Organic light emitting display device
US10770000B2 (en) Pixel circuit, driving method, display panel and display device
WO2022237095A1 (zh) 发光控制移位寄存器、栅极驱动电路、显示装置及方法
WO2021139774A1 (zh) 像素电路及其驱动方法、阵列基板及显示装置
WO2022170792A1 (zh) 显示面板及其制备方法、显示装置
WO2023221747A9 (zh) 显示基板及显示装置
CN113936606A (zh) 显示装置
CN115812233A (zh) 一种显示面板及显示装置
WO2023231742A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
CN111724743A (zh) 像素驱动电路及其驱动方法、显示装置
CN115911056A (zh) 阵列基板及显示装置
WO2022041227A1 (zh) 显示面板及显示装置
WO2023206167A1 (zh) 显示基板及显示装置
WO2022227043A1 (zh) 显示基板及显示装置
US20230306904A1 (en) Display panel and display device
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023035138A1 (zh) 显示面板和显示装置
WO2023226023A1 (zh) 显示面板及显示装置
WO2022133978A1 (zh) 显示面板、像素电路及显示装置
CN116682365A (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23806700

Country of ref document: EP

Kind code of ref document: A1