WO2019137105A1 - 像素电路、驱动方法、电致发光显示面板及显示装置 - Google Patents

像素电路、驱动方法、电致发光显示面板及显示装置 Download PDF

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Publication number
WO2019137105A1
WO2019137105A1 PCT/CN2018/117758 CN2018117758W WO2019137105A1 WO 2019137105 A1 WO2019137105 A1 WO 2019137105A1 CN 2018117758 W CN2018117758 W CN 2018117758W WO 2019137105 A1 WO2019137105 A1 WO 2019137105A1
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Prior art keywords
switching transistor
signal line
transistor
pole
coupled
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PCT/CN2018/117758
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English (en)
French (fr)
Inventor
董甜
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京东方科技集团股份有限公司
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Priority to JP2019563824A priority Critical patent/JP2021510207A/ja
Priority to EP18899135.0A priority patent/EP3739565A4/en
Priority to US16/617,565 priority patent/US20200184893A1/en
Publication of WO2019137105A1 publication Critical patent/WO2019137105A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method, an electroluminescent display panel, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • OLED display has low energy consumption, low production cost, self-illumination and wide viewing angle. And the speed of response is fast.
  • OLED displays have begun to replace traditional LCD displays. Unlike LCDs that use a stable voltage to control brightness, OLEDs are current driven and require a constant current to control their illumination. The OLED illumination is typically driven by setting a pixel circuit. At present, when the pixel circuit drives the OLED to emit light, the voltages of the first pole and the second pole of the driving transistor are affected by the voltage when the previous frame is displayed, and there is a problem that the brightness is inconsistent.
  • the driving transistor is configured to generate a driving current to drive the light emitting device to emit light during an emission phase; wherein a gate of the driving transistor is coupled to a capacitor circuit and a data writing circuit, respectively, a first pole of the driving transistor The second pole of the driving transistor is coupled to the reset circuit and the first electrode of the light emitting device, respectively;
  • the capacitor circuit is configured to store a voltage of a gate of the driving transistor
  • the data write circuit is configured to provide a data signal to a gate of the drive transistor during a data write phase
  • the reset circuit is configured to reset the first and second poles of the drive transistor during a reset phase.
  • the reset circuit is further coupled to a gate of the driving transistor, configured to reset a gate of the driving transistor in the reset phase, and configured to The threshold voltage of the drive transistor is compensated during a threshold compensation phase.
  • the reset circuit includes: a first switching transistor, a second switching transistor, and a third switching transistor;
  • a gate of the first switching transistor is coupled to the first scan signal line, a first pole of the first switching transistor is coupled to the first reference signal line, and a second pole of the first switching transistor is a second pole of the driving transistor is coupled;
  • a gate of the second switching transistor is coupled to a second scan signal line, a first pole of the second switching transistor is coupled to a second reference signal line, and a second pole of the second switching transistor is a first pole of the driving transistor is coupled;
  • a gate of the third switching transistor is coupled to a third scan signal line, a first pole of the third switching transistor is coupled to a third reference signal line, and a second pole of the third switching transistor is The gate of the driving transistor is coupled.
  • a material of the active layers of the first switching transistor and the third switching transistor includes a metal oxide semiconductor material
  • the material of the active layer of the second switching transistor comprises a low temperature polysilicon material.
  • the signal of the first scan signal line is the same as the signal of the third scan signal line.
  • the signal of the first reference signal line is the same as the signal of the third reference signal line.
  • the capacitor circuit includes: a storage capacitor and a voltage dividing capacitor:
  • the storage capacitor is coupled between the gate of the driving transistor and the first pole;
  • the voltage dividing capacitor is coupled between the first pole of the driving transistor and the second reference signal line.
  • the data writing circuit includes a fourth switching transistor
  • a gate of the fourth switching transistor is coupled to a fourth scan signal line, and a first pole of the fourth switching transistor is coupled to the data signal line for receiving the data signal, and the fourth switching transistor is A diode is coupled to a gate of the drive transistor.
  • a material of the active layer of the fourth switching transistor includes a metal oxide semiconductor material.
  • the pixel circuit further includes: an illumination control circuit; the second pole of the driving transistor and the reset circuit respectively pass through the illumination control circuit and the first of the light emitting device An electrode coupling; wherein the light emission control circuit is configured to control a second electrode of the driving transistor to be turned on or off from a first electrode of the light emitting device.
  • the illumination control circuit includes: a fifth switching transistor
  • a gate of the fifth switching transistor is coupled to the light emission control signal line, a first pole of the fifth switching transistor is coupled to a second electrode of the driving transistor, and a second pole of the fifth switching transistor is The first electrode of the light emitting device is coupled.
  • the material of the active layer of the fifth switching transistor comprises a low temperature polysilicon material.
  • the signal of the illumination control signal line is the same as the signal of the second scan signal line.
  • the material of the active layer of the driving transistor comprises a low temperature polysilicon material.
  • the embodiment of the present disclosure further provides a pixel circuit, including:
  • a gate of the first switching transistor is coupled to a first scan signal line, a first pole of the first switching transistor is coupled to a first reference signal line, and a first switch transistor a diode is coupled to the second pole of the driving transistor;
  • a gate of the second switching transistor is coupled to a second scan signal line, a first pole of the second switching transistor is coupled to a second reference signal line, and a second switching transistor is a diode is coupled to the first pole of the driving transistor;
  • a gate of the third switching transistor is coupled to a third scan signal line, a first pole of the third switching transistor is coupled to a third reference signal line, and a third switching transistor is a diode is coupled to a gate of the driving transistor;
  • a gate of the fourth switching transistor is coupled to a fourth scan signal line, a first pole of the fourth switching transistor is coupled to a data signal line, and a second pole of the fourth switching transistor Coupling with a gate of the driving transistor;
  • a gate of the fifth switching transistor is coupled to the light emission control signal line, and a first electrode of the fifth switching transistor is respectively connected to a second electrode of the driving transistor and the first switching transistor a second pole is coupled, and a second pole of the fifth switching transistor is coupled to the first electrode of the light emitting device;
  • a storage capacitor coupled between the gate of the driving transistor and the first pole
  • materials of the active layers of the first switching transistor, the third switching transistor, and the fourth switching transistor comprise a metal oxide semiconductor material
  • the materials of the second switching transistor, the fifth switching transistor, and the active layer of the driving transistor include a low temperature polysilicon material.
  • the signal of the first scan signal line is the same as the signal of the third scan signal line.
  • the signal of the first reference signal line is the same as the signal of the third reference signal line.
  • the signal of the illumination control signal line is the same as the signal of the second scan signal line.
  • the electroluminescent display panel provided by the embodiment of the present disclosure includes: a pixel circuit, a data signal line, a first scan signal line, a second scan signal line, a third scan signal line, and a fourth scan signal line, a light emission control signal line, a first reference voltage line, a second reference voltage line, and a third reference voltage line;
  • the pixel circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a driving transistor, a storage capacitor, a voltage dividing capacitor, and a light emitting device;
  • a gate of the first switching transistor is coupled to a first scan signal line to which a current corresponding signal is applied, and a first pole of the first switching transistor is coupled to the first reference signal line, the first a second pole of the switching transistor is coupled to the second pole of the driving transistor;
  • a gate of the second switching transistor is coupled to a second scan signal line to which a current corresponding signal is applied, and a first pole of the second switching transistor is coupled to the second reference signal line, the second a second pole of the switching transistor is coupled to the first pole of the driving transistor;
  • a gate of the third switching transistor is coupled to a third scan signal line to which a current corresponding signal is applied, and a first pole of the third switching transistor is coupled to the third reference signal line, the third a second pole of the switching transistor is coupled to a gate of the driving transistor;
  • a gate of the fourth switching transistor is coupled to a fourth scan signal line to which a current corresponding signal is applied, and a first pole of the fourth switching transistor is coupled to a data signal line to which a current corresponding signal is applied, a second pole of the fourth switching transistor is coupled to a gate of the driving transistor;
  • a gate of the fifth switching transistor is coupled to an emission control signal line to which a current corresponding signal is applied, a first pole of the fifth switching transistor and a second electrode of the driving transistor and the first switch a second pole of the transistor is coupled, and a second pole of the fifth switching transistor is coupled to the first electrode of the light emitting device;
  • the storage capacitor is coupled between the gate of the driving transistor and the first pole;
  • the voltage dividing capacitor is coupled between the first pole of the driving transistor and the second reference signal line.
  • the signals of the first scan signal line and the third scan signal line coupled to the same pixel circuit are the same.
  • the signal of the first reference signal line is the same as the signal of the third reference signal line.
  • the light emission control signal line coupled to the same pixel circuit is the same as the signal of the second scan signal line.
  • the display device provided by the embodiment of the present disclosure includes the electroluminescent display panel according to any one of claims 20-23.
  • the driving method of the above pixel circuit includes:
  • the reset circuit resets the first pole and the second pole of the driving transistor
  • the data writing circuit providing the data signal to a gate of the driving transistor
  • the capacitor circuit stores a voltage of a gate of the driving transistor, and the driving transistor generates a driving current to drive the light emitting device to emit light.
  • the method further includes: in the resetting phase, the reset circuit resets a gate of the driving transistor;
  • the method further includes a threshold compensation phase that compensates for a threshold voltage of the drive transistor.
  • the second switching transistor in the resetting phase, respectively controlling a first switching transistor in the reset circuit to be turned on and providing a signal of the first reference signal line to the driving transistor a second pole, the second switching transistor is turned on and supplies a signal of the second reference signal line to a first pole of the driving transistor, and the third switching transistor is turned on and provides a signal of the third reference signal line a gate of the driving transistor;
  • the second switching transistor in the reset circuit is turned off, the first switching transistor is turned on and supplies the signal of the first reference signal line to the second pole of the driving transistor,
  • the three-switch transistor is turned on and supplies a signal of the third reference signal line to a gate of the driving transistor; the driving transistor is turned on for threshold compensation.
  • the method further includes: in the resetting phase and the illuminating phase, the illuminating control circuit is to use the second pole of the driving transistor and the first of the illuminating device The electrodes are turned on.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3b is a second schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4a is a third schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • 4b is a fourth schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • Figure 5a is one of the circuit timing diagrams in the embodiment of the present disclosure.
  • Figure 5b is a second circuit timing diagram in the embodiment of the present disclosure.
  • Figure 5c is a third circuit diagram of the embodiment of the present disclosure.
  • Figure 5d is a fourth circuit diagram of the embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a second schematic structural diagram of an electroluminescent display panel according to an embodiment of the present disclosure.
  • a pixel circuit provided by an embodiment of the present disclosure, as shown in FIG. 1 includes:
  • the driving transistor M0 is configured to generate a driving current to drive the light emitting device L to emit light during the light emitting phase; wherein the gate G of the driving transistor M0 is coupled to the capacitor circuit 3 and the data writing circuit 2, and the first pole S of the driving transistor M0 The second pole D of the driving transistor M0 is coupled to the reset circuit 1 and the first electrode of the light emitting device L, respectively;
  • the capacitor circuit 3 is configured to store a voltage of the gate G of the driving transistor M0;
  • the data writing circuit 2 is configured to supply a data signal (Data) to the gate G of the driving transistor M0 in the data writing phase;
  • the reset circuit 1 is configured to reset the first pole S and the second pole D of the driving transistor M0 in the reset phase.
  • the pixel circuit provided by the embodiment of the present disclosure can reset the first pole and the second pole of the driving transistor in the reset phase by the reset circuit, and then write the data signal to the gate of the driving transistor through the data writing circuit, and by driving The transistor generates a drive current to drive the light emitting device to emit light.
  • the voltage of the first pole of the driving transistor can be set to a fixed voltage and the voltage of the second pole of the driving transistor can be set to a fixed voltage before each writing of the data signal, so that the residual voltage of the previous frame can be avoided.
  • the illumination causes an influence, which in turn can improve the uniformity of illumination of the display panel.
  • the reset circuit 1 is also coupled to the gate G of the driving transistor M0, and is configured to gate the driving transistor M0 in the reset phase.
  • the pole G is reset and configured to compensate for the threshold voltage of the drive transistor M0 during the threshold compensation phase. This can reset the voltage of the gate G of the driving transistor M0 before the data signal of each frame is written, even if the voltage of the gate G thereof becomes a fixed voltage, and the first pole S of the driving transistor M0 is made.
  • the voltage becomes a fixed voltage
  • the voltage of the second pole D of the driving transistor M0 becomes a fixed voltage
  • the gate G of the driving transistor M0 can be hopped by the same voltage each time the data signal Data is written, and
  • the voltage of the first pole S is hopped by the same voltage, so that the problem of short-term afterimage caused by the hysteresis effect can be improved.
  • a low temperature poly-Silicon (LTPS) material is used as an active layer, and the mobility of the transistor is high and can be made thinner and smaller, and the power consumption is lower.
  • the active layer of the driving transistor is driven.
  • the material may include a low temperature polysilicon material.
  • the driving transistor M0 may be a P-type transistor; wherein the first pole S of the driving transistor M0 is used as Its source, the second pole D of the driving transistor M0 serves as its drain. And when the driving transistor M0 is in a saturated state, current flows from the source of the driving transistor M0 to its drain.
  • the second electrode of the light emitting device L is coupled to the low voltage power supply terminal (ELVSS).
  • the voltage of the low-voltage power supply terminal ELVSS is generally grounded or has a negative value, and the specific voltage value needs to be determined according to the actual application environment, which is not limited herein.
  • the light emitting device may be an electroluminescent diode, wherein the anode of the electroluminescent diode is the first electrode of the light emitting device, and the cathode of the electroluminescent diode is illuminated.
  • the second electrode of the device and which illuminates under the action of a current generated when the drive transistor is in a saturated state.
  • the general light-emitting device has a light-emission threshold voltage V L and emits light when the voltage difference between the two electrodes of the light-emitting device is greater than or equal to the light-emitting threshold voltage V L .
  • the electroluminescent diode may include an organic light emitting diode or a quantum dot light emitting diode, which is not limited herein.
  • the data writing circuit 2 may include: a fourth switching transistor M4; wherein, the gate of the fourth switching transistor M4 The fourth scan signal line (Scan4) is coupled, the first pole of the fourth switching transistor M4 is coupled to the data signal line (DATA) for receiving the data signal, and the second pole of the fourth switching transistor M4 is coupled to the gate of the driving transistor M0.
  • the pole G is coupled.
  • the fourth switching transistor is in an on state by the control of the signal of the fourth scanning signal line in the data writing phase, and the data signal of the data signal line can be written.
  • the gate of the drive transistor is in a specific implementation, in the pixel circuit provided by the embodiment of the present disclosure.
  • the leakage current of the transistor using the metal oxide semiconductor material as the active layer is small. Therefore, in order to reduce the leakage current, in a specific implementation, in the pixel circuit provided by the embodiment of the present disclosure, the active layer of the fourth switching transistor
  • the material may include a metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials, which are not limited herein.
  • IGZO Indium Gallium Zinc Oxide
  • the above is only a specific structure of the data writing circuit in the pixel circuit provided by the embodiment of the present disclosure.
  • the specific structure of the data writing circuit is not limited to the above structure provided by the embodiment of the present disclosure, and may also be in the field. Other structures known to the skilled person are not limited herein.
  • the reset circuit 1 may include: a first switching transistor M1, a second switching transistor M2, and a third switching transistor M3;
  • the gate of the first switching transistor M1 is coupled to the first scan signal line (Scan1), the first pole of the first switching transistor M1 is coupled to the first reference signal line (Vref1), and the second pole of the first switching transistor M1 Coupling with the second pole D of the driving transistor M0;
  • the gate of the second switching transistor M2 is coupled to the second scan signal line (Scan2), the first pole of the second switching transistor M2 is coupled to the second reference signal line (Vref2), and the second pole of the second switching transistor M2 Coupling with the first pole S of the driving transistor M0;
  • the gate of the third switching transistor M3 is coupled to the third scan signal line (Scan3), the first pole of the third switching transistor M3 is coupled to the third reference signal line (Vref3), and the second pole of the third switching transistor M3 It is coupled to the gate G of the driving transistor M0.
  • the first switching transistor is controlled to be in a conducting state by the signal of the first scanning signal line in the reset phase, and the signal of the first reference signal line may be provided to the driving.
  • the second pole of the transistor resets the second pole of the drive transistor during the reset phase.
  • the second switching transistor is in an on state by the control of the signal of the second scanning signal line in the reset phase, and the signal of the second reference signal line may be supplied to the first pole of the driving transistor to be the first to the driving transistor in the reset phase The pole is reset.
  • the third switching transistor is in an on state by the control of the signal of the third scanning signal line in the reset phase, and the signal of the third reference signal line may be supplied to the gate of the driving transistor to perform the gate of the driving transistor in the reset phase. Reset.
  • the third switching transistor is in an on state by the control of the signal of the third scanning signal line in the threshold compensation phase, and the signal of the third reference signal line can be supplied to the gate of the driving transistor; the first switching transistor is subjected to the threshold compensation stage
  • the control of the signal of the scan signal line is in an on state, and the signal of the first reference signal line may be supplied to the second pole of the drive transistor; the drive transistor is turned on during the threshold compensation phase to implement threshold compensation.
  • the material of the active layer of the first switching transistor may include a metal oxide semiconductor material.
  • the leakage current when the first switching transistor is turned off can be reduced, thereby facilitating the reduction of the leakage current of the first switching transistor to the driving transistor when the light emitting device emits light, thereby avoiding the driving current that affects the driving of the driving transistor to drive the light emitting device.
  • the material of the active layer of the third switching transistor may include a metal oxide semiconductor material.
  • the leakage current when the third switching transistor is turned off can be reduced, thereby facilitating the reduction of the leakage current of the third switching transistor to the driving transistor when the light emitting device emits light, thereby avoiding the driving current that affects the driving of the driving transistor to drive the light emitting device.
  • the material of the active layer of the second switching transistor may include a low temperature polysilicon material, so that the mobility of the second switching transistor is high and can be made thinner. Small, lower power consumption, etc.
  • the signal of the first reference signal line and the signal of the third reference signal line can be set.
  • the first reference signal line and the third reference signal line are set as one signal line.
  • the first pole of the first switching transistor M1 and the first pole of the third switching transistor M3 may both be coupled to the first reference signal line Vref1.
  • the first poles of the first switching transistor and the first pole of the third switching transistor may also be coupled to the third reference signal line, which is not limited herein.
  • the signal of the first scanning signal line and the signal of the third scanning signal line can be set.
  • the first scan signal line and the third scan signal line are set as one signal line.
  • the gate of the first switching transistor M1 and the gate of the third switching transistor M3 may both be coupled to the first scanning signal line Scan1.
  • the first switching transistor M1 and The third switching transistor M3 is a transistor of the same type, that is, it may be an N-type transistor, which is not limited herein.
  • the gate of the first switching transistor and the gate of the third switching transistor may be coupled to the third scanning signal line, which is not limited herein.
  • the number of the signal lines is saved, and the wiring space is saved.
  • the signal of the first scanning signal line and the signal of the third scanning signal line are set.
  • the signal of the first reference signal line and the signal of the third reference signal line are set to be the same.
  • the first poles of the first switching transistor M1 and the first pole of the third switching transistor M3 may both be coupled to the first reference signal line Vref1, and the first switching transistor M1
  • the gate of the gate and the third switching transistor M3 may both be coupled to the first scan signal line Scan1.
  • the voltage V ref2 of the signal of the second reference signal line is generally a positive value, for example, the signal of the second reference signal line may be a signal of the high voltage power supply terminal ELVDD.
  • the voltage V ref1 of the signal of the first reference signal line is preferably a negative value
  • the voltage V ref3 of the signal of the third reference signal line is generally a negative value, wherein the voltage V ref1 of the first reference signal line and the voltage V of the low voltage power supply terminal Ss generally satisfies the formula: V ref1 -V ss ⁇ V L .
  • the specific voltage value of the signal of the signal line needs to be determined according to the actual application environment, which is not limited herein.
  • the above is only a specific structure of the reset circuit in the pixel circuit provided by the embodiment of the present disclosure.
  • the specific structure of the reset circuit is not limited to the above structure provided by the embodiment of the present disclosure, and may also be known to those skilled in the art. Other structures are not limited herein.
  • the capacitor circuit 3 may include: a storage capacitor C1 and a voltage dividing capacitor C2:
  • the storage capacitor C1 is coupled between the gate G of the driving transistor M0 and the first pole S;
  • the voltage dividing capacitor C2 is coupled between the first pole S of the driving transistor M0 and the second reference signal line Vref2.
  • the storage capacitor can keep the voltage of the gate of the driving transistor and the first electrode of the driving transistor stable, and can be at the gate of the input driving transistor and the first of the driving transistor.
  • the charge and discharge may be performed by the action of the pole signal, and the voltage difference of the gate of the drive transistor may be coupled to the first pole of the drive transistor when the first pole of the drive transistor is in the floating state.
  • the above is only to exemplify the specific structure of the capacitor circuit in the pixel circuit provided by the embodiment of the present disclosure.
  • the specific structure of the capacitor circuit is not limited to the above structure provided by the embodiment of the present disclosure, and may also be known to those skilled in the art. Other structures are not limited herein.
  • the pixel circuit may further include: a light-emitting control circuit 4; a driving transistor M0.
  • the second pole D and the reset circuit 1 are respectively coupled to the first electrode of the light emitting device L through the light emission control circuit 4; wherein the light emission control circuit 4 is configured to control the second pole D of the driving transistor M0 and the light emitting device L One electrode is turned on or off.
  • the illumination control circuit 4 may include: a fifth switching transistor M5;
  • the gate of the fifth switching transistor M5 is coupled to the emission control signal line (EMIT), and the first electrode of the fifth switching transistor M5 is coupled to the second electrode D of the driving transistor M0 and the first electrode of the first switching transistor, respectively.
  • the second pole of the fifth switching transistor M5 is coupled to the first electrode of the light emitting device L.
  • the fifth switching transistor may be in an on state by the control of the signal of the light emission control signal line during the reset phase, so as to drive the second electrode of the transistor and the light emitting device.
  • the first electrode is turned on to reset the light emitting device.
  • the fifth switching transistor may be in an on state by the control of the signal of the light emission control signal line during the light emitting phase to turn on the second electrode of the driving transistor and the first electrode of the light emitting device to output the driving current generated by the driving transistor to A light emitting device that drives the light emitting device to emit light.
  • the material of the active layer of the fifth switching transistor may include a low temperature polysilicon material, so that the fifth switching transistor can be made thinner and smaller, and the power consumption is lower. Wait.
  • the number of the signal lines is saved, and the wiring space is saved.
  • the signal of the light-emitting control signal line and the signal of the second scanning signal line can be set.
  • the light emission control signal line and the second scan signal line are set as one signal line.
  • the gate of the second switching transistor M2 and the gate of the fifth switching transistor M5 are both coupled to the light emission control signal line EMIT.
  • the gate of the second switching transistor and the gate of the fifth switching transistor may also be coupled to the second scanning signal line, which is not limited herein.
  • the above is only a specific structure of the illuminating control circuit in the pixel circuit provided by the embodiment of the present disclosure.
  • the specific structure of the illuminating control circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the active layer may be ion-doped by a doping process so that the type of the formed transistor is P-type or N-type.
  • each of the switching transistors may be configured as a P-type transistor or an N-type transistor according to an actual application environment, which is not limited herein.
  • the first switching transistor M1, the third switching transistor M3, and the fourth switching transistor M4 may be set as The N-type transistor has the second switching transistor M2 and the fifth switching transistor M5 as P-type transistors.
  • the switching transistor can be made to have a double gate structure.
  • the first switching transistor, the third switching transistor, and the fourth switching transistor may be preferably configured as a dual gate structure. This can reduce the interference to the driving transistor when the light emitting device emits light, thereby avoiding the driving current that affects the driving of the driving transistor to drive the light emitting device.
  • any switching transistor may be configured as a dual gate structure from the viewpoint of reducing leakage current, which is not limited herein.
  • the P-type transistor is turned on under the action of the low potential signal, and is turned off under the action of the high potential signal; the N-type transistor is turned on under the action of the high potential signal, and the low potential signal is turned on.
  • the cutoff is under effect.
  • the first pole of each of the switching transistors may serve as a source thereof, the second pole as a drain thereof, or the first pole of each of the switching transistors may serve as a drain thereof.
  • the second pole serves as its source and is not specifically distinguished here.
  • the materials of the active layers of the first switching transistor, the third switching transistor, and the fourth switching transistor may be set as metal oxide semiconductor materials. That is, the first switching transistor, the third switching transistor, and the fourth switching transistor are each disposed as an oxide transistor, so that leakage currents of the first switching transistor, the third switching transistor, and the fourth switching transistor are small.
  • the process of using a metal oxide semiconductor material as an active layer to prepare a transistor may be the same as the process of preparing an oxide-type transistor (Oxide Thin Film Transistor) in the prior art, and details are not described herein.
  • the material of the active layers of the second switching transistor, the fifth switching transistor, and the driving transistor to a low temperature polysilicon material, that is, the driving transistor, the second switching transistor, and the fifth switching transistor are all set as LTPS transistors, so that The second switching transistor, the fifth switching transistor, and the driving transistor have higher mobility and can be made thinner and smaller, and have lower power consumption.
  • the process of using low-temperature polysilicon as the active layer to prepare the transistor can be the same as the process of preparing the LTPS transistor in the prior art, and will not be described herein.
  • the leakage current of the gate of the driving transistor can be made small, and power consumption can be made low. Therefore, the pixel circuit should be configured as an electroluminescent display panel, and when the display panel reduces the refresh frequency for display, the uniformity of the display can be ensured.
  • the corresponding input timing diagram is as shown in FIG. 5a.
  • the reset phase T1, the data writing phase T2, and the lighting phase T3 in the input timing chart shown in FIG. 5a are mainly selected in three stages.
  • the first scan signal Scan1 1
  • the second scan signal Scan2 0
  • the fourth scan signal Scan4 0.
  • both the first switching transistor M1 and the third switching transistor M3 are turned on.
  • the turned-on first switching transistor M1 supplies the signal of the first reference signal line Vref1 to the second pole D of the driving transistor M0 to reset the second pole D of the driving transistor M0 and the light emitting device L to avoid adjacent two Shows luminescence interference between frames.
  • the turned-on third switching transistor M3 supplies the signal of the first reference signal line Vref1 to the gate G of the driving transistor M0 to reset the gate G of the driving transistor M0.
  • V th is a threshold voltage of the driving transistor M0
  • K is a structural parameter
  • ⁇ n represents the mobility of the driving transistor M0
  • C ox is the gate oxide capacitance per unit area. In order to drive the width to length ratio of the transistor M0, these values are relatively stable in the same structure and can be counted as a constant.
  • the data signal is written to the gate of the drive transistor during the data write phase, and the illumination device is driven to emit light by the drive transistor during the illumination phase.
  • the voltage of the first pole of the driving transistor can be set to a fixed voltage and the voltage of the second pole of the driving transistor can be set to a fixed voltage before each writing of the data signal, so that the residual voltage of the previous frame can be avoided.
  • the illumination causes an influence, which in turn can improve the uniformity of illumination of the display panel.
  • the threshold voltage Vth of the driving transistor is shifted, which causes the driving current flowing through each of the light-emitting devices to be changed by the Vth drift to cause uneven display brightness, thereby Affects the display of the entire image.
  • the driving current flowing through each of the light emitting devices is related to the voltage V ref2 of the second reference voltage signal line connected to the first electrode of the driving transistor, the driving current is also subjected to the IR Drop of the second reference signal line. The effect is that the brightness of the light-emitting devices in different regions is uneven.
  • the working process is illustrated by taking the pixel circuit shown in FIG. 3b as an example, and the corresponding input timing diagram is shown in FIG. 5b.
  • the reset phase T1, the threshold compensation phase T2, the data writing phase T3, and the lighting phase T4 in the input timing chart shown in FIG. 5b are mainly selected in four stages.
  • both the first switching transistor M1 and the third switching transistor M3 are turned on.
  • the turned-on first switching transistor M1 supplies the signal of the first reference signal line Vref1 to the second pole D of the driving transistor M0 to reset the second pole D of the driving transistor M0 and the light emitting device L to avoid two adjacent Shows luminescence interference between frames.
  • the turned-on third switching transistor M3 supplies the signal of the first reference signal line Vref1 to the gate G of the driving transistor M0 to reset the gate G of the driving transistor M0.
  • both the first switching transistor M1 and the third switching transistor M3 are turned on.
  • the turned-on third switching transistor M3 supplies the signal of the first reference signal line Vref1 to the gate of the driving transistor M0 such that the gate voltage of the driving transistor M0 is Vref1 .
  • the storage capacitor C1 can instantaneously maintain the voltage V ref2 of the first pole of the driving transistor M0, so that the driving transistor M0 is turned on under the action of V ref1 and V ref2 , so that the voltage of the first pole S of the driving transistor M0 is turned on.
  • the fourth switching transistor M4 is turned on to supply the voltage V data of the data signal to the gate G of the driving transistor M0, so that the voltage of the gate G of the driving transistor M0 becomes Vdata .
  • the voltage of the gate G of the drive transistor M0 becomes: Therefore, the driving transistor M0 is in a saturated state, and according to the saturation state current characteristic, the driving transistor M0 generates a driving current I L that drives the light emitting device L to emit light to satisfy the formula:
  • V gs is the gate-source voltage of the driving transistor M0, that is,
  • K is a structural parameter
  • ⁇ n represents the mobility of the driving transistor M0
  • C ox is the gate oxide capacitance per unit area.
  • these values are relatively stable in the same structure and can be counted as a constant.
  • the driving current I L generated by the driving transistor M0 is supplied to the light emitting device L to drive the light emitting device L to emit light.
  • the driving current by the equation I L satisfies seen, the driving transistor drives the light emitting element L M0 light emission drive current I L is only the data signal Data voltage V data signal line and the first reference voltage Vref1 is V ref1, whereas the driving transistor M0 is the threshold voltage V th and a second reference signal line Vref2 voltage V ref2 independent, can be solved since the operation of the driving transistor M0 process technology and time caused by the threshold voltage V th of drift, and IR Drop of L of driving the light emitting device
  • the influence of the current I L is such that the driving current I L of the light-emitting device L is kept stable, thereby ensuring the normal operation of the light-emitting device L.
  • the working process is illustrated by taking the pixel circuit shown in FIG. 4a as an example, and the corresponding input timing chart is shown in FIG. 5c.
  • the reset phase T1, the threshold compensation phase T2, the data writing phase T3, and the lighting phase T4 in the input timing chart shown in FIG. 5c are mainly selected in four stages.
  • the fifth switching transistor M5 is turned on, and the second electrode D of the driving transistor M0 is electrically connected to the first electrode of the light emitting device L to supply the signal of the first reference signal line Vref1 to the light emitting device L.
  • the storage capacitor C1 can instantaneously maintain the voltage V ref2 of the first pole of the driving transistor M0, so that the driving transistor M0 is turned on under the action of V ref3 and V ref2 , so that the voltage of the first pole S of the driving transistor M0 is turned on.
  • the fourth switching transistor M4 is turned on to supply the voltage V data of the data signal to the gate G of the driving transistor M0, so that the voltage of the gate G of the driving transistor M0 becomes Vdata .
  • the second switching transistor M2 is turned off.
  • the voltage of the gate G of the drive transistor M0 becomes: Therefore, the driving transistor M0 is in a saturated state, and according to the saturation state current characteristic, the driving transistor M0 generates a driving current I L that drives the light emitting device L to emit light to satisfy the formula:
  • V gs is the gate-source voltage of the driving transistor M0, that is,
  • K is a structural parameter
  • ⁇ n represents the mobility of the driving transistor M0
  • C ox is the gate oxide capacitance per unit area.
  • these values are relatively stable in the same structure and can be counted as a constant.
  • the fifth switching transistor M5 is turned on, and the second electrode D of the driving transistor M0 is turned on to the light emitting device L to supply the driving current I L generated by the driving transistor M0 to the light emitting device L to drive the light.
  • Device L illuminates.
  • the driving transistor drives the light emitting element L M0 light emission drive current I L is only the data signal Data voltage V data signal line and the first reference voltage Vref1 is V ref1, whereas the driving transistor M0 is the threshold voltage V th and a second reference signal line Vref2 voltage V ref2 independent, can be solved since the operation of the driving transistor M0 process technology and time caused by the threshold voltage V th of drift, and IR Drop of L of driving the light emitting device
  • the influence of the current I L is such that the driving current I L of the light-emitting device L is kept stable, thereby ensuring the normal operation of the light-emitting device L.
  • the signal of the third scan signal line may also be changed to control the third switching transistor to be turned on to reset the gate of the driving transistor so that the voltage of the gate thereof becomes V ref3 .
  • the voltage of the gate of the driving transistor is V ref3
  • the voltage of the second pole is V ref1
  • the voltage of the first pole is V ref2
  • the three poles of the driving transistor can be simultaneously reset.
  • the voltage of the gate of the driving transistor is V ref3
  • the voltage of the second pole is V ref1
  • the voltage of the first pole of the driving transistor becomes V ref3 -V th , that is, data is written in each frame.
  • the gate of the driving transistor may be a fixed voltage V ref3 such that the first pole of the driving transistor may be a fixed voltage V ref3 - V th and the second pole of the driving transistor may be a fixed voltage V ref1 . Therefore, each time the data signal is written, the gate of the driving transistor can be jumped by the same fixed voltage, and the voltage of the first pole is hopped by the same fixed voltage, thereby improving the short-term caused by the hysteresis effect. The problem of afterimages.
  • the working process is illustrated by taking the pixel circuit shown in FIG. 4b as an example, and the corresponding input timing chart is shown in FIG. 5d.
  • the reset phase T1, the threshold compensation phase T2, the data writing phase T3, and the lighting phase T4 in the input timing chart shown in FIG. 5d are mainly selected in four stages.
  • both the first switching transistor M1 and the third switching transistor M3 are turned on.
  • the turned-on first switching transistor M1 supplies a signal of the first reference signal line Vref1 to the second electrode D of the driving transistor M0 to reset the second pole D of the driving transistor M0.
  • the turned-on second switching transistor M2 supplies the signal of the second reference signal line Vref2 to the first pole S of the driving transistor M0 to reset the first pole S of the driving transistor M0, and stores the second reference through the storage capacitor C1.
  • both the first switching transistor M1 and the third switching transistor M3 are turned on.
  • the turned-on third switching transistor M3 supplies the signal of the first reference signal line Vref1 to the gate of the driving transistor M0 such that the gate voltage of the driving transistor M0 is Vref1 .
  • the turned-on first switching transistor M1 supplies the signal of the first reference signal line Vref1 to the second pole D of the driving transistor M0 such that the voltage of the second pole D of the driving transistor M0 is V ref1 .
  • the storage capacitor C1 can instantaneously maintain the voltage V ref2 of the first pole of the driving transistor M0, so that the driving transistor M0 is turned on under the action of V ref1 and V ref2 , so that the voltage of the first pole S of the driving transistor M0 is turned on.
  • both the second switching transistor M2 and the fifth switching transistor M5 are turned on.
  • the turned-on second switching transistor M2 supplies the voltage V ref2 of the second reference signal line Vref2 to the first pole S of the driving transistor M0 such that the voltage of the first pole S of the driving transistor M0 is V ref2 .
  • the voltage of the gate G of the drive transistor M0 becomes: Therefore, the driving transistor M0 is in a saturated state, and according to the saturation state current characteristic, the driving transistor M0 generates a driving current I L that drives the light emitting device L to emit light to satisfy the formula:
  • V gs is the gate-source voltage of the driving transistor M0, that is,
  • K is a structural parameter
  • ⁇ n represents the mobility of the driving transistor M0
  • C ox is the gate oxide capacitance per unit area.
  • these values are relatively stable in the same structure and can be counted as a constant.
  • the turned-on fifth switching transistor M5 turns on the second electrode D of the driving transistor M0 and the light emitting device L to supply the driving current I L generated by the driving transistor M0 to the light emitting device L, and drives the light emitting device L to emit light.
  • the driving current by the equation I L satisfies seen, the driving transistor drives the light emitting element L M0 light emission drive current I L is only the data signal Data voltage V data signal line and the first reference voltage Vref1 is V ref1, whereas the driving transistor M0 is the threshold voltage V th and a second reference signal line Vref2 voltage V ref2 independent, can be solved since the operation of the driving transistor M0 process technology and time caused by the threshold voltage V th of drift, and IR Drop of L of driving the light emitting device The influence of the current I L is such that the driving current I L of the light-emitting device L is kept stable, thereby ensuring the normal operation of the light-emitting device L.
  • the voltage of the gate and the second electrode of the driving transistor becomes V ref2 , and the three poles of the driving transistor can be simultaneously reset.
  • the voltages of the gate and the second pole of the driving transistor are respectively V ref1 , and the voltage of the first pole of the driving transistor becomes V ref1 -V th , that is, before each data writing phase of the frame,
  • the gate of the driving transistor may be a fixed voltage V ref1 such that the first pole of the driving transistor may be a fixed voltage V ref1 - V th and the second pole of the driving transistor may be a fixed voltage V ref1 .
  • the gate of the driving transistor can be jumped by the same fixed voltage, and the voltage of the first pole is hopped by the same fixed voltage, thereby improving the short-term caused by the hysteresis effect.
  • an embodiment of the present disclosure further provides a driving method of the above pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 6, the method includes:
  • the data writing circuit supplies the data signal to the gate of the driving transistor
  • the capacitor circuit stores a voltage of a gate of the driving transistor, and the driving transistor generates a driving current to drive the illuminating device to emit light.
  • the first pole and the second pole of the driving transistor may be reset in the reset phase by the reset circuit, and then the data signal is written into the gate of the driving transistor through the data writing circuit, and passed through
  • the driving transistor generates a driving current to drive the light emitting device to emit light.
  • the voltage of the first pole of the driving transistor can be set to a fixed voltage and the voltage of the second pole of the driving transistor can be set to a fixed voltage before each writing of the data signal, so that the residual voltage of the previous frame can be avoided.
  • the illumination causes an influence, which in turn can improve the uniformity of illumination of the display panel.
  • the driving method may further include: in a reset phase, the reset circuit resets a gate of the driving transistor.
  • the above driving method provided by the embodiment of the present disclosure may further include: a threshold compensation phase, the reset circuit compensates a threshold voltage of the driving transistor.
  • the reset circuit when the reset circuit includes the first switching transistor, the second switching transistor, and the third switching transistor, in the above driving method provided by the embodiment of the present disclosure, in the reset phase, the first switch in the reset circuit is separately controlled.
  • the transistor is turned on and supplies a signal on the first reference signal line to the second pole of the driving transistor, and the second switching transistor is turned on and supplies the signal on the second reference signal line to the first pole of the driving transistor, the third switch The transistor is turned on and supplies a signal on the third reference signal line to the gate of the drive transistor.
  • the second switching transistor in the reset circuit is respectively controlled to be turned off, the first switching transistor is turned on and the signal on the first reference signal line is supplied to the second electrode of the driving transistor, and the third switching transistor is turned on. And providing a signal on the third reference signal line to the gate of the driving transistor; the driving transistor is turned on for threshold compensation.
  • the above driving method provided by the embodiment of the present disclosure may further include: in the reset phase and the light emitting phase, the light emitting control circuit turns on the second electrode of the driving transistor and the first electrode of the light emitting device.
  • the driving current of the driving transistor to drive the illuminating device to emit light can be only the voltage of the data signal and the voltage of the signal of the first reference signal line. Regardless of, regardless of the threshold voltage of the driving transistor and the voltage of the signal of the second reference signal line, the influence of the threshold voltage of the driving transistor and the IR Drop of the signal of the second reference signal line on the driving current flowing through the light emitting device can be avoided, thereby The operating current for driving the light-emitting device is kept stable, thereby improving the uniformity of the brightness of the display screen in the display panel.
  • an embodiment of the present disclosure further provides an electroluminescent display panel, as shown in FIG. 7, which may include: a pixel circuit (PX), a data signal line DATA, a first scan signal line Scan1, and a second scan.
  • PX pixel circuit
  • the pixel circuit PX may include: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a driving transistor M0, a storage capacitor C1, a voltage dividing capacitor C2, and a light emitting Device L; wherein
  • the gate of the first switching transistor M1 is coupled to the first scan signal line Scan1 to which the current corresponding signal is applied, and the first pole of the first switching transistor M1 is coupled to the first reference signal line Vref1, and the first switching transistor M1
  • the second pole is coupled to the second pole D of the driving transistor M0;
  • the gate of the second switching transistor M2 is coupled to the second scanning signal line Scan2 to which the current corresponding signal is applied, the first pole of the second switching transistor M2 is coupled to the second reference signal line Vref2, and the second switching transistor M2 is coupled The second pole is coupled to the first pole S of the driving transistor M0;
  • the gate of the third switching transistor M3 is coupled to the third scanning signal line Scan3 to which the current corresponding signal is applied, the first pole of the third switching transistor M3 is coupled to the third reference signal line Vref3, and the third switching transistor M3 is coupled The second pole is coupled to the gate G of the driving transistor M0;
  • the gate of the fourth switching transistor M4 is coupled to the fourth scanning signal line Scan4 to which the current corresponding signal is applied, and the first pole of the fourth switching transistor M4 is coupled to the data signal line DATA to which the current corresponding signal is applied.
  • the second pole of the four-switch transistor M4 is coupled to the gate G of the driving transistor M0;
  • the gate of the fifth switching transistor M5 is coupled to the light emission control signal line EMIT to which the current corresponding signal is applied, and the first pole of the fifth switching transistor M5 and the second pole D of the driving transistor M0 and the first switching transistor M1, respectively The second pole is coupled, and the second pole of the fifth switching transistor M5 is coupled to the first electrode of the light emitting device L;
  • the storage capacitor C1 is coupled between the gate G of the driving transistor M0 and the first pole S;
  • the voltage dividing capacitor C2 is coupled between the first pole S of the driving transistor M0 and the second reference signal line Vref2.
  • the electroluminescent display panel inputs a corresponding signal through each signal line to control the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor in the pixel circuit.
  • the driving transistor, the storage capacitor, the voltage dividing capacitor, and the light emitting device work together to realize the light emitting display of the electroluminescent display panel.
  • a gate driving circuit may be further included; wherein, the first scanning signal line, the second scanning signal line, and the third scanning are performed by the gate driving circuit
  • the signal line and the fourth scan signal line provide corresponding gate scan signals.
  • an illumination control circuit may be further included; wherein the illumination control signal is provided with a corresponding illumination control signal by the illumination control circuit.
  • a source driving circuit may be further included; wherein the data signal line is provided with a corresponding data signal through the source driving circuit.
  • the working process of the pixel circuit in the electroluminescent display panel provided by the embodiment of the present disclosure can be referred to the implementation of the foregoing pixel circuit, and the repeated description is not repeated herein.
  • the electroluminescent display panel provided by the embodiment of the present disclosure combines a process of preparing a transistor by using an LTPS type transistor and an oxide type transistor, and can ensure display uniformity when displaying a refresh frequency for display. .
  • the data signal line and the second reference signal line may be the same material and the same layer as the first pole and the second pole of the switching transistor in the pixel circuit, respectively.
  • the first to fourth scan signal lines, the light emission control signal lines, and the first and third reference signal lines may be respectively disposed in the same material and in the same layer as the gates of the switching transistors in the pixel circuits.
  • a pattern of the data signal line, the second reference signal line, and the first and second poles of the switching transistor in the pixel circuit can be simultaneously formed by using one patterning process, and each scanning signal line is simultaneously formed by another patterning process, and the first
  • the pattern of the third reference signal line, the light emission control signal line, and the gate of the switching transistor in the pixel circuit can simplify the fabrication process and reduce the thickness of the electroluminescent display panel.
  • the electroluminescent display panel when the data signal line and the second reference signal line and the first and second poles of the switching transistor in the pixel circuit are of the same material and disposed in the same layer, the electroluminescent display panel provided by the embodiment of the present disclosure
  • the data signal line may extend along a column direction of the pixel unit formed by the pixel circuit
  • the second reference signal line may extend along a column direction of the pixel unit.
  • the second reference signal line can also be disposed in the electroluminescent display panel in a grid structure.
  • the electroluminescent display panel when the scanning signal lines, the reference signal lines, the light-emitting control signal lines, and the gates of the switching transistors in the pixel circuits are of the same material and disposed in the same layer, the electroluminescent display panel provided by the embodiment of the present disclosure
  • the scan signal lines, the first and third reference signal lines, and the light emission control signal lines may extend in a row direction of the pixel unit.
  • the gap between the adjacent two rows of pixel units is generally larger than the gap between the adjacent two columns of pixel units, the reference signal lines are respectively extended along the row direction of the pixel unit, and the electroluminescent display panel can be further optimized. Layout design.
  • the first scan signal line and the third scan signal coupled to the same pixel circuit may be The signal of the line is set to be the same.
  • the first scan signal line and the third scan signal line coupled to the same pixel circuit are set as one signal line. This further optimizes the layout of the electroluminescent display panel. Specifically, as shown in FIG. 8, the gate of the first switching transistor M1 and the gate of the third switching transistor M3 are coupled to the first scanning signal line Scan1.
  • the illumination control signal line and the second scan signal line coupled to the same pixel circuit can be The signals are set to the same.
  • the illumination control signal line and the second scan signal line coupled to the same pixel circuit are set as one signal line. This further optimizes the layout of the electroluminescent display panel. Specifically, as shown in FIG. 8, the second switching transistor M2 and the fifth switching transistor M5 are both coupled to the light emission control signal line EMIT.
  • the wiring space is saved.
  • the signal of the first reference signal line and the signal of the third reference signal line may be set to the same.
  • the first reference signal line and the third reference signal line are also set as one signal line. This further optimizes the layout of the electroluminescent display panel. Specifically, as shown in FIG. 8, the first switching transistor M1 and the third switching transistor M3 are both coupled to the first reference signal line Vref1.
  • the cathode of the light-emitting device in the electroluminescent display panel provided by the embodiment of the present disclosure may be the same as the design in the prior art, for example, a full-surface cathode layer design may be used, and details are not described herein.
  • the electroluminescent display panel provided by the embodiment of the present disclosure may be an organic light emitting display panel; or may be a quantum dot light emitting display panel, which is not limited herein.
  • an embodiment of the present disclosure further provides a display device including the above-described electroluminescent display panel provided by an embodiment of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
  • the pixel circuit, the driving method, the electroluminescence display panel and the display device provided by the embodiment of the present disclosure can reset the first pole and the second pole of the driving transistor in the reset phase by the reset circuit, and then the data is written through the data writing circuit.
  • a signal is written to the gate of the driving transistor, and a driving current is generated by the driving transistor to drive the light emitting device to emit light.
  • the voltage of the first pole of the driving transistor can be set to a fixed voltage and the voltage of the second pole of the driving transistor can be set to a fixed voltage before each writing of the data signal, so that the residual voltage of the previous frame can be avoided.
  • the illumination causes an influence, which in turn can improve the uniformity of illumination of the display panel.

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Abstract

一种像素电路(PX)、驱动方法、电致发光显示面板及显示装置，像素电路(PX)包括：发光器件(L)；驱动晶体管(M0)被配置为在发光阶段生成驱动电流(I L)以驱动发光器件(L)发光；其中，驱动晶体管(M0)的栅极(G)分别与电容电路(3)以及数据写入电路(2)耦接，驱动晶体管(M0)的第一极(S)与复位电路(1)耦接，驱动晶体管(M0)的第二极(D)分别与复位电路(1)以及发光器件(L)的第一电极耦接；电容电路(3)，被配置为存储驱动晶体管(M0)的栅极(G)的电压；数据写入电路(2)，被配置为在数据写入阶段将数据信号(Data)提供给驱动晶体管(M0)的栅极(G)；复位电路(1)，被配置为在复位阶段对驱动晶体管(M0)的第一极(S)与第二极(D)进行复位。

Description

像素电路、驱动方法、电致发光显示面板及显示装置
本申请要求在2018年1月11日提交中国专利局、申请号为201810026813.6、公开名称为“像素电路、驱动方法、电致发光显示面板及显示装置”的中国专利申请的优先权，其全部内容以引入的方式并入本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路、驱动方法、电致发光显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是当今平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、平板电脑、数码相机等显示领域，OLED显示器已经开始取代传统的LCD显示器。与LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制其发光。一般通过设置像素电路以驱动OLED发光。目前，在像素电路驱动OLED发光时，驱动晶体管的第一极与第二极的电压会受上一帧显示时电压的影响，存在亮度不一致的问题。
发明内容
本公开实施例提供的像素电路，其中，包括：
发光器件；
所述驱动晶体管被配置为在发光阶段生成驱动电流以驱动所述发光器件发光；其中，所述驱动晶体管的栅极分别与电容电路以及数据写入电路耦接，所述驱动晶体管的第一极与复位电路耦接，所述驱动晶体管的第二极分别与所述复位电路以及所述发光器件的第一电极耦接；
所述电容电路，被配置为存储所述驱动晶体管的栅极的电压；
所述数据写入电路，被配置为在数据写入阶段将数据信号提供给所述驱动晶体管的栅极；
所述复位电路，被配置为在复位阶段对所述驱动晶体管的第一极与第二极进行复位。
可选地，在本公开实施例中，所述复位电路还与所述驱动晶体管的栅极耦接，被配置为在所述复位阶段对所述驱动晶体管的栅极进行复位，以及被配置为在阈值补偿阶段对所述驱动晶体管的阈值电压进行补偿。
可选地，在本公开实施例中，所述复位电路包括：第一开关晶体管、第二开关晶体管以及第三开关晶体管；
所述第一开关晶体管的栅极与第一扫描信号线耦接，所述第一开关晶体管的第一极与第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
所述第二开关晶体管的栅极与第二扫描信号线耦接，所述第二开关晶体管的第一极与第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第三开关晶体管的栅极与第三扫描信号线耦接，所述第三开关晶体管的第一极与第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接。
可选地，在本公开实施例中，所述第一开关晶体管与所述第三开关晶体管的有源层的材料包括金属氧化物半导体材料；
所述第二开关晶体管的有源层的材料包括低温多晶硅材料。
可选地，在本公开实施例中，所述第一扫描信号线的信号与所述第三扫描信号线的信号相同。
可选地，在本公开实施例中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
可选地，在本公开实施例中，所述电容电路包括：存储电容与分压电容：
所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
所述分压电容耦接于所述驱动晶体管的第一极与第二参考信号线之间。
可选地，在本公开实施例中，所述数据写入电路包括第四开关晶体管；
所述第四开关晶体管的栅极与第四扫描信号线耦接，所述第四开关晶体管的第一极与数据信号线耦接用于接收所述数据信号，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接。
可选地，在本公开实施例中，所述第四开关晶体管的有源层的材料包括金属氧化物半导体材料。
可选地，在本公开实施例中，所述像素电路还包括：发光控制电路；所述驱动晶体管的第二极与所述复位电路分别通过所述发光控制电路与所述发光器件的第一电极耦接；其中，所述发光控制电路用于控制所述驱动晶体管的第二极与所述发光器件的第一电极导通或断开。
可选地，在本公开实施例中，所述发光控制电路包括：第五开关晶体管；
所述第五开关晶体管的栅极与发光控制信号线耦接，所述第五开关晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接。
可选地，在本公开实施例中，所述第五开关晶体管的有源层的材料包括低温多晶硅材料。
可选地，在本公开实施例中，所述发光控制信号线的信号与第二扫描信号线的信号相同。
可选地，在本公开实施例中，所述驱动晶体管的有源层的材料包括低温多晶硅材料。
相应地，本公开实施例还提供了像素电路，其中，包括：
发光器件；
第一开关晶体管，所述第一开关晶体管的栅极与第一扫描信号线耦接，所述第一开关晶体管的第一极与第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
第二开关晶体管，所述第二开关晶体管的栅极与第二扫描信号线耦接，所述第二开关晶体管的第一极与第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
第三开关晶体管，所述第三开关晶体管的栅极与第三扫描信号线耦接，所述第三开关晶体管的第一极与第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
第四开关晶体管，所述第四开关晶体管的栅极与第四扫描信号线耦接，所述第四开关晶体管的第一极与数据信号线藕接，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接；
第五开关晶体管，所述第五开关晶体管的栅极与发光控制信号线耦接，所述第五开关晶体管的第一极分别与所述驱动晶体管的第二极以及所述第一开关晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接；
存储电容，所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
分压电容，所述分压电容耦接于所述驱动晶体管的第一极与第二参考信号线之间。
可选地，在本公开实施例中，所述第一开关晶体管、所述第三开关晶体管以及所述第四开关晶体管的有源层的材料包括金属氧化物半导体材料；
所述第二开关晶体管、所述第五开关晶体管以及所述驱动晶体管的有源层的材料包括低温多晶硅材料。
可选地，在本公开实施例中，所述第一扫描信号线的信号与所述第三扫描信号线的信号相同。
可选地，在本公开实施例中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
可选地，在本公开实施例中，所述发光控制信号线的信号与所述第二扫描信号线的信号相同。
相应地，本公开实施例提供的电致发光显示面板，其中，包括：像素电 路、数据信号线、第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制信号线、第一参考电压线、第二参考电压线、第三参考电压线；
所述像素电路包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、驱动晶体管、存储电容、分压电容以及发光器件；其中，
所述第一开关晶体管的栅极与向其施加当前对应信号的第一扫描信号线耦接，所述第一开关晶体管的第一极与所述第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
所述第二开关晶体管的栅极与向其施加当前对应信号的第二扫描信号线耦接，所述第二开关晶体管的第一极与所述第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第三开关晶体管的栅极与向其施加当前对应信号的第三扫描信号线耦接，所述第三开关晶体管的第一极与所述第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四开关晶体管的栅极与向其施加当前对应信号的第四扫描信号线耦接，所述第四开关晶体管的第一极与向其施加当前对应信号的数据信号线耦接，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第五开关晶体管的栅极与向其施加当前对应信号的发光控制信号线耦接，所述第五开关晶体管的第一极分别与所述驱动晶体管的第二极以及所述第一开关晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接；
所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
所述分压电容耦接于所述驱动晶体管的第一极与所述第二参考信号线之间。
可选地，在本公开实施例中，与同一所述像素电路耦接的第一扫描信号线与第三扫描信号线的信号相同。
可选地，在本公开实施例中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
可选地，在本公开实施例中，与同一所述像素电路耦接的发光控制信号线与第二扫描信号线的信号相同。
相应地，本公开实施例提供的显示装置，其中，包括如权利要求20-23任一项所述的电致发光显示面板。
相应地，本公开实施例提供的上述像素电路的驱动方法，其中，包括：
复位阶段，所述复位电路对所述驱动晶体管的第一极与第二极进行复位；
数据写入阶段，所述数据写入电路将所述数据信号提供给所述驱动晶体管的栅极；
发光阶段，所述电容电路存储所述驱动晶体管的栅极的电压，所述驱动晶体管生成驱动电流以驱动所述发光器件发光。
可选地，在本公开实施例中，所述方法还包括：在所述复位阶段，所述复位电路对所述驱动晶体管的栅极进行复位；
在所述复位阶段之后，且在所述数据写入阶段之前，所述方法还包括：阈值补偿阶段，所述复位电路对所述驱动晶体管的阈值电压进行补偿。
可选地，在本公开实施例中，在所述复位阶段，分别控制所述复位电路中的第一开关晶体管导通并将所述第一参考信号线的信号提供给所述驱动晶体管的第二极，第二开关晶体管导通并将所述第二参考信号线的信号提供给所述驱动晶体管的第一极，第三开关晶体管导通并将所述第三参考信号线的信号提供给所述驱动晶体管的栅极；
在所述阈值补偿阶段，分别控制所述复位电路中的第二开关晶体管截止，第一开关晶体管导通并将所述第一参考信号线的信号提供给所述驱动晶体管的第二极，第三开关晶体管导通并将所述第三参考信号线的信号提供给所述驱动晶体管的栅极；所述驱动晶体管导通进行阈值补偿。
可选地，在本公开实施例中，所述方法还包括：在所述复位阶段与所述发光阶段，所述发光控制电路将所述驱动晶体管的第二极与所述发光器件的 第一电极导通。
附图说明
图1为本公开实施例提供的像素电路的结构示意图之一；
图2为本公开实施例提供的像素电路的结构示意图之二；
图3a为本公开实施例提供的像素电路的具体结构示意图之一；
图3b为本公开实施例提供的像素电路的具体结构示意图之二；
图4a为本公开实施例提供的像素电路的具体结构示意图之三；
图4b为本公开实施例提供的像素电路的具体结构示意图之四；
图5a为本公开实施例中的电路时序图之一；
图5b为本公开实施例中的电路时序图之二；
图5c为本公开实施例中的电路时序图之三；
图5d为本公开实施例中的电路时序图之四；
图6为本公开实施例提供的驱动方法的流程图；
图7为本公开实施例提供的电致发光显示面板的结构示意图之一；
图8为本公开实施例提供的电致发光显示面板的结构示意图之二。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的像素电路、驱动方法、电致发光显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本公开实施例提供的一种像素电路，如图1所示，包括：
发光器件L；
驱动晶体管M0，被配置为在发光阶段生成驱动电流以驱动发光器件L发光；其中，驱动晶体管M0的栅极G与电容电路3以及数据写入电路2耦接， 驱动晶体管M0的第一极S与复位电路1耦接，驱动晶体管M0的第二极D分别与复位电路1以及发光器件L的第一电极耦接；
电容电路3，被配置为存储驱动晶体管M0的栅极G的电压；
数据写入电路2，被配置为在数据写入阶段将数据信号(Data)提供给驱动晶体管M0的栅极G；
复位电路1，被配置为在复位阶段对驱动晶体管M0的第一极S与第二极D进行复位。
本公开实施例提供的像素电路，可以通过复位电路在复位阶段对驱动晶体管的第一极与第二极进行复位，之后通过数据写入电路将数据信号写入驱动晶体管的栅极，以及通过驱动晶体管生成驱动电流以驱动发光器件发光。这样可以在每次写入数据信号之前使驱动晶体管的第一极的电压设置为固定电压，以及使驱动晶体管的第二极的电压设置为固定电压，从而可以避免上一帧残留的电压对本帧发光造成影响，进而可以提高显示面板的发光均一性。
一般驱动晶体管驱动发光器件在某一灰阶下发光一段时间后，由于偏压应力会使驱动晶体管的特性，例如阈值电压与迁移率等发生偏移。然而，驱动晶体管在不同灰阶下驱动发光器件发光时的偏压应力不尽相同，导致驱动晶体管的特性在不同灰阶下偏移不同，这样导致在高低灰阶切换显示时，会由于迟滞效应而导致短期残像问题出现。在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，复位电路1还与驱动晶体管M0的栅极G耦接，被配置为在复位阶段对驱动晶体管M0的栅极G进行复位，以及被配置为在阈值补偿阶段对驱动晶体管M0的阈值电压进行补偿。这样可以在每一帧的数据信号写入之前，通过使驱动晶体管M0的栅极G的电压进行复位，即使其栅极G的电压变为固定电压，并且使驱动晶体管M0的第一极S的电压变为固定电压，以及使驱动晶体管M0的第二极D的电压变为固定电压，可以在每次写入数据信号Data时，使驱动晶体管M0的栅极G通过同一电压进行跳变，以及使其第一极S的电压通过同一电压进行跳变，从而可以改善因迟滞效应导致的短期残像的问题。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例中是为了更好的解释本公开，但不限制本公开。
一般采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等，在具体实施时，驱动晶体管的有源层的材料可以包括低温多晶硅材料。
可选地，在具体实施时，在本公开实施例提供的上述像素电路中，如图1至图4b所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的第一极S作为其源极，驱动晶体管M0的第二极D作为其漏极。并且在驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。
在具体实施时，在本公开实施例提供的上述像素电路中，如图1至图4b所示，发光器件L的第二电极与低电压电源端(ELVSS)耦接。该低电压电源端ELVSS的电压一般接地或为负值，其具体电压值需要根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例提供的上述像素电路中，发光器件可以为电致发光二极管，其中，电致发光二极管的阳极为发光器件的第一电极，电致发光二极管的阴极为发光器件的第二电极，并且其在驱动晶体管处于饱和状态时产生的电流的作用下实现发光。另外，一般发光器件具有发光阈值电压V L，在发光器件两极的电压差大于或等于发光阈值电压V L时进行发光。其中，电致发光二极管可以包括：有机发光二极管或量子点发光二极管，在此不作限定。
在具体实施时，在本公开实施例提供的像素电路中，如图3a至图4b所示，数据写入电路2可以包括：第四开关晶体管M4；其中，第四开关晶体管M4的栅极与第四扫描信号线(Scan4)耦接，第四开关晶体管M4的第一极与数据信号线(DATA)耦接用于接收数据信号，第四开关晶体管M4的第二极与驱动晶体管M0的栅极G耦接。
在具体实施时，在本公开实施例提供的像素电路中，第四开关晶体管在数据写入阶段受第四扫描信号线的信号的控制处于导通状态，可以将数据信 号线的数据信号写入驱动晶体管的栅极。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小，因此为了降低漏电流，在具体实施时，在本公开实施例提供的像素电路中，第四开关晶体管的有源层的材料可以包括金属氧化物半导体材料，例如可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，当然，也可以为其他金属氧化物半导体材料，在此不作限定。这样可以减少第四开关晶体管M4截止时的漏电流，从而在发光器件L发光时，有利于减少第四开关晶体管M4的漏电流对驱动晶体管M0的干扰，进而可以避免影响驱动晶体管M0驱动发光器件发光的驱动电流。
以上仅是举例说明本公开实施例提供的像素电路中数据写入电路的具体结构，在具体实施时，数据写入电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，在本公开实施例提供的像素电路中，如图3a至图4b所示，复位电路1可以包括：第一开关晶体管M1、第二开关晶体管M2以及第三开关晶体管M3；
第一开关晶体管M1的栅极与第一扫描信号线(Scan1)耦接，第一开关晶体管M1的第一极与第一参考信号线(Vref1)耦接，第一开关晶体管M1的第二极与驱动晶体管M0的第二极D耦接；
第二开关晶体管M2的栅极与第二扫描信号线(Scan2)耦接，第二开关晶体管M2的第一极与第二参考信号线(Vref2)耦接，第二开关晶体管M2的第二极与驱动晶体管M0的第一极S耦接；
第三开关晶体管M3的栅极与第三扫描信号线(Scan3)耦接，第三开关晶体管M3的第一极与第三参考信号线(Vref3)耦接，第三开关晶体管M3的第二极与驱动晶体管M0的栅极G耦接。
在具体实施时，在本公开实施例提供的像素电路中，第一开关晶体管在复位阶段受第一扫描信号线的信号的控制处于导通状态，可以将第一参考信号线的信号提供给驱动晶体管的第二极，以在复位阶段对驱动晶体管的第二 极进行复位。第二开关晶体管在复位阶段受第二扫描信号线的信号的控制处于导通状态，可以将第二参考信号线的信号提供给驱动晶体管的第一极，以在复位阶段对驱动晶体管的第一极进行复位。第三开关晶体管在复位阶段受第三扫描信号线的信号的控制处于导通状态，可以将第三参考信号线的信号提供给驱动晶体管的栅极，以在复位阶段对驱动晶体管的栅极进行复位。第三开关晶体管在阈值补偿阶段受第三扫描信号线的信号的控制处于导通状态，可以将第三参考信号线的信号提供给驱动晶体管的栅极；第一开关晶体管在阈值补偿阶段受第一扫描信号线的信号的控制处于导通状态，可以将第一参考信号线的信号提供给驱动晶体管的第二极；驱动晶体管在阈值补偿阶段导通以实现阈值补偿。
在具体实施时，在本公开实施例提供的像素电路中，第一开关晶体管的有源层的材料可以包括金属氧化物半导体材料。这样可以减少第一开关晶体管截止时的漏电流，从而在发光器件发光时，有利于减少第一开关晶体管的漏电流对驱动晶体管的干扰，进而可以避免影响驱动晶体管驱动发光器件发光的驱动电流。
在具体实施时，在本公开实施例提供的像素电路中，第三开关晶体管的有源层的材料可以包括金属氧化物半导体材料。这样可以减少第三开关晶体管截止时的漏电流，从而在发光器件发光时，有利于减少第三开关晶体管的漏电流对驱动晶体管的干扰，进而可以避免影响驱动晶体管驱动发光器件发光的驱动电流。
在具体实施时，在本公开实施例提供的像素电路中，第二开关晶体管的有源层的材料可以包括低温多晶硅材料，这样可以使第二开关晶体管的迁移率高且可以做得更薄更小、功耗更低等。
为了减少信号线的设置，节省信号线数量，节省布线空间，在具体实施时，在本公开实施例提供的像素电路中，可以使第一参考信号线的信号与第三参考信号线的信号设置为相同。可选地，使第一参考信号线与第三参考信号线设置为一条信号线。具体地，如图3b与图4b所示，第一开关晶体管M1 的第一极与第三开关晶体管M3的第一极可以均与第一参考信号线Vref1耦接。当然，第一开关晶体管的第一极与第三开关晶体管的第一极也可以均与第三参考信号线耦接，在此不作限定。
为了减少信号线的设置，节省信号线数量，节省布线空间，在具体实施时，在本公开实施例提供的像素电路中，可以使第一扫描信号线的信号与第三扫描信号线的信号设置为相同。可选地，使第一扫描信号线与第三扫描信号线设置为一条信号线。具体地，如图3b与图4b所示，第一开关晶体管M1的栅极与第三开关晶体管M3的栅极可以均与第一扫描信号线Scan1耦接，此时，第一开关晶体管M1与第三开关晶体管M3为同一类型晶体管，即可以均为N型晶体管，在此不作限定。当然，第一开关晶体管的栅极与第三开关晶体管的栅极也可以均与第三扫描信号线耦接，在此不作限定。
为了进一步减少信号线的设置，节省信号线数量，节省布线空间，在具体实施时，在本公开实施例提供的像素电路中，使第一扫描信号线的信号与第三扫描信号线的信号设置为相同，并且，使第一参考信号线的信号与第三参考信号线的信号设置为相同。具体地，如图3b与图4b所示，第一开关晶体管M1的第一极与第三开关晶体管M3的第一极可以均与第一参考信号线Vref1耦接，并且，第一开关晶体管M1的栅极与第三开关晶体管M3的栅极可以均与第一扫描信号线Scan1耦接。
在具体实施时，在本公开实施例提供的上述像素电路中，第二参考信号线的信号的电压V ref2一般为正值，例如第二参考信号线的信号可以为高电压电源端ELVDD的信号。第一参考信号线的信号的电压V ref1优选为负值，第三参考信号线的信号的电压V ref3一般为负值，其中，第一参考信号线的电压V ref1与低电压电源端的电压V ss一般满足公式：V ref1-V ss<V L。并且，上述信号线的信号的具体电压值需要根据实际应用环境来设计确定，在此不作限定。
以上仅是举例说明本公开实施例提供的像素电路中复位电路的具体结构，在具体实施时，复位电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，在本公开实施例提供的像素电路中，如图3a至图4b所示，电容电路3可以包括：存储电容C1与分压电容C2：
存储电容C1耦接于驱动晶体管M0的栅极G与第一极S之间；
分压电容C2耦接于驱动晶体管M0的第一极S与第二参考信号线Vref2之间。
在具体实施时，在本公开实施例提供的像素电路中，存储电容可以保持驱动晶体管的栅极与驱动晶体管的第一极的电压稳定，可以在输入驱动晶体管的栅极与驱动晶体管的第一极的信号的作用下进行充放电，也可以在驱动晶体管的第一极处于浮接状态时，将驱动晶体管的栅极变化的电压差耦合至驱动晶体管的第一极。
以上仅是举例说明本公开实施例提供的像素电路中电容电路的具体结构，在具体实施时，电容电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
为了避免阈值补偿阶段对发光器件的性能的影响，在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，像素电路还可以包括：发光控制电路4；驱动晶体管M0的第二极D与复位电路1分别通过发光控制电路4与发光器件L的第一电极耦接；其中，发光控制电路4被配置为控制驱动晶体管M0的第二极D与发光器件L的第一电极导通或断开。这样可以在复位阶段对发光器件L进行复位，以及在发光阶段使驱动晶体管M0产生的驱动电流流向发光器件L，以驱动发光器件L发光。
在具体实施时，在本公开实施例提供的像素电路中，如图4a与图4b所示，发光控制电路4可以包括：第五开关晶体管M5；
第五开关晶体管M5的栅极与发光控制信号线(EMIT)耦接，第五开关晶体管M5的第一极分别与驱动晶体管M0的第二极D以及第一开关晶体管的第一极耦接，第五开关晶体管M5的第二极与发光器件L的第一电极耦接。
在具体实施时，在本公开实施例提供的像素电路中，第五开关晶体管可以在复位阶段受发光控制信号线的信号的控制处于导通状态，以将驱动晶体 管的第二极与发光器件的第一电极导通，以对发光器件进行复位。第五开关晶体管可以在发光阶段受发光控制信号线的信号的控制处于导通状态，以将驱动晶体管的第二极与发光器件的第一电极导通，以将驱动晶体管产生的驱动电流输出给发光器件，驱动发光器件发光。
在具体实施时，在本公开实施例提供的像素电路中，第五开关晶体管的有源层的材料可以包括低温多晶硅材料，以使第五开关晶体管可以做得更薄更小、功耗更低等。
为了进一步减少信号线的设置，节省信号线数量，节省布线空间，在具体实施时，在本公开实施例提供的像素电路中，可以使发光控制信号线的信号与第二扫描信号线的信号设置为相同。可选地，使发光控制信号线与第二扫描信号线设置为一条信号线。具体地，如图4b所示，第二开关晶体管M2的栅极与第五开关晶体管M5的栅极均与发光控制信号线EMIT耦接。当然，第二开关晶体管的栅极与第五开关晶体管的栅极也可以均与第二扫描信号线耦接，在此不作限定。
以上仅是举例说明本公开实施例提供的像素电路中发光控制电路的具体结构，在具体实施时，发光控制电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
一般采用金属氧化物半导体材料或低温多晶硅材料作为有源层时，可以采用掺杂工艺对有源层进行离子掺杂，以使形成的晶体管的类型为P型或N型。在具体实施时，在本公开实施例提供的像素电路中，可以根据实际应用环境将上述各开关晶体管设置为P型晶体管或N型晶体管，在此不作限定。
可选地，在具体实施时，在本公开实施例提供的像素电路中，如图3a至图4b所示，可以将第一开关晶体管M1、第三开关晶体管M3以及第四开关晶体管M4设置为N型晶体管，将第二开关晶体管M2与第五开关晶体管M5设置为P型晶体管。
为了进一步降低漏电流，可以使开关晶体管采用双栅极结构。在具体实施时，可以将第一开关晶体管、第三开关晶体管以及第四开关晶体管优选设 置为双栅极结构。这样可以在发光器件发光时，减少对驱动晶体管的干扰，从而可以避免影响驱动晶体管驱动发光器件发光的驱动电流。并且，在本公开实施例提供的像素电路中，从降低漏电流的角度考虑，任意开关晶体管可以设置为双栅极结构，在此不作限定。
具体地，在本公开实施例提供的像素电路中，P型晶体管在低电位信号作用下导通，在高电位信号作用下截止；N型晶体管在高电位信号作用下导通，在低电位信号作用下截止。
具体地，在本公开实施例提供的像素电路中，上述各开关晶体管的第一极可以作为其源极，第二极作为其漏极，或者上述各开关晶体管的第一极可以作为其漏极，第二极作为其源极，在此不作具体区分。
进一步地，在具体实施时，在本公开实施例提供的像素电路中，可以使第一开关晶体管、第三开关晶体管以及第四开关晶体管的有源层的材料均设置为金属氧化物半导体材料，即将第一开关晶体管、第三开关晶体管以及第四开关晶体管均设置为氧化物型晶体管，这样可以使第一开关晶体管、第三开关晶体管以及第四开关晶体管漏电流较小。并且，采用金属氧化物半导体材料作为有源层以制备晶体管的工艺可以与现有技术中制备氧化物型晶体管(Oxide Thin Film Transistor)的工艺相同，在此不作赘述。以及使第二开关晶体管、第五开关晶体管以及驱动晶体管的有源层的材料设置为低温多晶硅材料，即将驱动晶体管、第二开关晶体管以及第五开关晶体管均设置为LTPS型晶体管，这样可以使其第二开关晶体管、第五开关晶体管以及驱动晶体管迁移率较高且可以做得更薄更小、功耗更低等。并且，采用低温多晶硅作为有源层以制备晶体管的工艺可以与现有技术中制备LTPS型晶体管的工艺相同，在此不作赘述。这样通过将LTPS型晶体管与氧化物型晶体管这两种制备晶体管的工艺进行结合制备低温多晶硅氧化物的LTPO像素电路，可以使驱动晶体管的栅极的漏电流较小，以及使功耗较低。从而将该像素电路应被配置为电致发光显示面板中，在显示面板降低刷新频率进行显示时，可以保证显示的均一性。
下面结合电路时序图对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电位，0表示低电位。需要说明的是，1和0是逻辑电位，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
在一些实施例中，以图3b所示的像素电路为例，对应的输入时序图如图5a所示。具体地，主要选取如图5a所示的输入时序图中的复位阶段T1、数据写入阶段T2和发光阶段T3共三个阶段。
在复位阶段T1，第一扫描信号Scan1＝1，第二扫描信号Scan2＝0，第四扫描信号Scan4＝0。
由于Scan1＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。导通的第一开关晶体管M1将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，以对驱动晶体管M0的第二极D以及发光器件L进行复位，以避免相邻两个显示帧之间的发光干扰。导通的第三开关晶体管M3将第一参考信号线Vref1的信号提供给驱动晶体管M0的栅极G，以对驱动晶体管M0的栅极G进行复位。由于Scan2＝0，因此第二开关晶体管M2导通，以将第二参考信号线Vref2的信号提供给驱动晶体管M0的第一极S，以对驱动晶体管M0的第一极S进行复位。当然，在复位电路仅对驱动晶体管M0的第一极S与第二极D复位时，可以不设置第三开关晶体管M3。由于Scan4＝0，因此第四开关晶体管M4截止。
在数据写入阶段T2，Scan1＝0，Scan2＝1，Scan4＝1。
由于Scan4＝1，因此第四开关晶体管M4导通，以将数据信号线DATA的数据信号写入驱动晶体管M0的栅极G，使驱动晶体管M0的栅极G的电压为数据信号的电压V data，并通过存储电容C1进行存储。由于Scan1＝0，因此第一开关晶体管M1与第三开关晶体管M3均截止。由于Scan2＝1，因此第二开关晶体管M2截止。
在发光阶段T3，Scan1＝0，Scan2＝0，Scan4＝0。
由于Scan2＝0，因此第二开关晶体管M2导通，以将第二参考信号线Vref2 的信号提供给驱动晶体管M0的第一极S，使其第一极S的电压为V ref2。驱动晶体管M0在其第一极S的电压V ref2与其栅极G的电压V data的控制下产生驱动电流I L，且I L＝K[V data－V ref2－V th] 2，以通过驱动电流I L驱动发光器件L发光。并且，V th为驱动晶体管M0的阈值电压，K为结构参数，且
Figure PCTCN2018117758-appb-000001
μ n代表驱动晶体管M0的迁移率，C ox为单位面积栅氧化层电容，
Figure PCTCN2018117758-appb-000002
为驱动晶体管M0的宽长比，相同结构中这些数值相对稳定，可以算作常量。
在复位阶段中通过对驱动晶体管的第一极与第二极进行复位，在数据写入阶段将数据信号写入驱动晶体管的栅极，以及在发光阶段通过驱动晶体管驱动发光器件发光。这样可以在每次写入数据信号之前使驱动晶体管的第一极的电压设置为固定电压，以及使驱动晶体管的第二极的电压设置为固定电压，从而可以避免上一帧残留的电压对本帧发光造成影响，进而可以提高显示面板的发光均一性。
由于工艺制程和器件老化等原因，会使驱动晶体管的阈值电压V th产生漂移，这样就导致了流过每个发光器件的驱动电流受V th漂移的影响而发生变化导致显示亮度不均，从而影响整个图像的显示效果。并且由于流过每个发光器件的驱动电流与驱动晶体管的第一极连接的第二参考电压信号线的电压V ref2相关，使得驱动电流还受第二参考信号线的IR Drop(压降)的影响，造成不同区域的发光器件出现亮度不均匀现象。
以下通过实施例对改善驱动晶体管的阈值电压V th与IR Drop的影响的具体实现方式进行说明。但读者应知，其具体实现方式不局限于此。
在另一些实施例中，以图3b所示的像素电路为例对其工作过程进行说明，其对应的输入时序图如图5b所示。具体地，主要选取如图5b所示的输入时序图中的复位阶段T1、阈值补偿阶段T2、数据写入阶段T3和发光阶段T4共四个阶段。
在复位阶段T1，Scan1＝1，Scan2＝0，Scan4＝0。
由于Scan1＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。 导通的第一开关晶体管M1将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，以对驱动晶体管M0的第二极D与发光器件L进行复位，以避免相邻两个显示帧之间的发光干扰。导通的第三开关晶体管M3将第一参考信号线Vref1的信号提供给驱动晶体管M0的栅极G，以对驱动晶体管M0的栅极G进行复位。由于Scan2＝0，因此第二开关晶体管M2导通，并将第二参考信号线Vref2的信号提供给驱动晶体管M0的第一极S，以对驱动晶体管M0的第一极S进行复位，以及通过存储电容C1存储第二参考信号线Vref2的信号的电压V ref2。由于Scan4＝0，因此第四开关晶体管M4截止。
在阈值补偿阶段T2，Scan1＝1，Scan2＝1，Scan4＝0。
由于Scan1＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。导通的第三开关晶体管M3将第一参考信号线Vref1的信号提供给驱动晶体管M0的栅极，使驱动晶体管M0的栅极电压为V ref1。导通的第一开关晶体管M1将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，使驱动晶体管M0的第二极D的电压为V ref1。由于Scan2＝1，因此第二开关晶体管M2截止。存储电容C1可以瞬间保持驱动晶体管M0的第一极的电压V ref2，从而使驱动晶体管M0在V ref1与V ref2的作用下导通，以使驱动晶体管M0的第一极S的电压通过导通的驱动晶体管M0放电，直至驱动晶体管M0的第一极S的电压变为：V ref1－V th时，驱动晶体管M0截止，将驱动晶体管M0的阈值电压V th写入存储电容C1。从而实现对驱动晶体管M0的阈值电压V th的补偿，且该补偿过程亦不会对发光器件L造成影响。由于Scan4＝0，因此第四开关晶体管M4截止。
在数据写入阶段T3，Scan1＝0，Scan2＝1，Scan4＝1。
由于Scan4＝1，因此第四开关晶体管M4导通，以将数据信号的电压V data提供给驱动晶体管M0的栅极G，使驱动晶体管M0的栅极G的电压变为V data。由于Scan2＝1，因此第二开关晶体管M2截止。因此驱动晶体管M0的第一极S处于浮接状态，由于存储电容C1的耦合作用以及分压电容C2的分压作用， 可以使驱动晶体管M0的第一极S的电压变为：
Figure PCTCN2018117758-appb-000003
其中c 1代表存储电容C1的电容值，c 2代表分压电容C2的电容值。由于Scan1＝0，因此第一开关晶体管M1与第三开关晶体管M3均截止。
在发光阶段T4，Scan1＝0，Scan2＝0，Scan4＝0。
由于Scan2＝0，因此第二开关晶体管M2导通，并将第二参考信号线Vref2的电压V ref2提供给驱动晶体管M0的第一极S，使驱动晶体管M0的第一极S的电压为V ref2。根据存储电容C的电荷在跳变前后的电荷守恒原则，驱动晶体管M0的栅极G的电压变为：
Figure PCTCN2018117758-appb-000004
因此，驱动晶体管M0处于饱和状态，根据饱和状态电流特性，驱动晶体管M0产生驱动发光器件L发光的驱动电流I L满足公式：
Figure PCTCN2018117758-appb-000005
其中，V gs为驱动晶体管M0的栅源电压，即
Figure PCTCN2018117758-appb-000006
并且，K为结构参数，且
Figure PCTCN2018117758-appb-000007
μ n代表驱动晶体管M0的迁移率，C ox为单位面积栅氧化层电容，
Figure PCTCN2018117758-appb-000008
为驱动晶体管M0的宽长比，相同结构中这些数值相对稳定，可以算作常量。驱动晶体管M0产生的驱动电流I L提供给发光器件L，驱动发光器件L发光。通过上述驱动电流I L满足的公式可知，驱动晶体管M0驱动发光器件L发光的驱动电流I L仅与数据信号Data的电压V data以及第一参考信号线Vref1的电压V ref1有关，而与驱动晶体管M0的阈值电压V th以及第二参考信号线Vref2的电压V ref2无关，可以解决由于驱动晶体管M0的工艺制程以及长时间的操作造成的阈值电压V th漂移以及IR Drop对驱动发光器件L的驱动电流I L的影响，从而使发光器件L的驱动电流I L保持稳定，进而保证了发光器件L的正常工作。
图3a所示的像素电路的工作过程可以参考图3b所示的像素电路的工作过程，在此不作赘述。
在另一些实施例中，以图4a所示的像素电路为例对其工作过程进行说明， 其对应的输入时序图如图5c所示。具体地，主要选取如图5c所示的输入时序图中的复位阶段T1、阈值补偿阶段T2、数据写入阶段T3和发光阶段T4共四个阶段。
在复位阶段T1，Scan1＝1，Scan2＝0，第三扫描信号Scan3＝0，Scan4＝0，发光控制信号EM＝0。
由于Scan1＝1，因此第一开关晶体管M1导通，并将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，以对驱动晶体管M0的第二极D进行复位。由于Scan2＝0，因此第二开关晶体管M2导通，并将第二参考信号线Vref2的信号提供给驱动晶体管M0的第一极S，以对驱动晶体管M0的第一极S进行复位，以及通过存储电容C1存储第二参考信号线Vref2的信号的电压V ref2。由于EM＝0，因此第五开关晶体管M5导通，并将驱动晶体管M0的第二极D与发光器件L的第一电极导通，以将第一参考信号线Vref1的信号提供给发光器件L，对发光器件L进行复位，以避免相邻两个显示帧之间的发光干扰。由于Scan4＝0，因此第四开关晶体管M4截止。由于Scan3＝0，因此第三开关晶体管M3截止。
在阈值补偿阶段T2，Scan1＝1，Scan2＝1，Scan3＝1，Scan4＝0，EM＝1。
由于Scan3＝1，因此第三开关晶体管M3导通，并将第三参考信号线Vref3的信号提供给驱动晶体管M0的栅极G，使驱动晶体管M0的栅极电压为V ref3。由于Scan1＝1，因此第一开关晶体管M1导通，并将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，使驱动晶体管M0的第二极D的电压为V ref1。由于Scan2＝1，因此第二开关晶体管M2截止。由于EM＝1，因此第五开关晶体管M5截止。存储电容C1可以瞬间保持驱动晶体管M0的第一极的电压V ref2，从而使驱动晶体管M0在V ref3与V ref2的作用下导通，以使驱动晶体管M0的第一极S的电压通过导通的驱动晶体管M0放电，直至驱动晶体管M0的第一极S的电压变为：V ref3－V th时，驱动晶体管M0截止，将驱动晶体管M0的阈值电压V th写入存储电容C1。从而实现对驱动晶体管M0的阈 值电压V th的补偿，且该补偿过程亦不会对发光器件L造成影响。由于Scan4＝0，因此第四开关晶体管M4截止。
在数据写入阶段T3，Scan1＝0，Scan2＝1，Scan3＝0，Scan4＝1，EM＝1。
由于Scan4＝1，因此第四开关晶体管M4导通，以将数据信号的电压V data提供给驱动晶体管M0的栅极G，使驱动晶体管M0的栅极G的电压变为V data。由于Scan2＝1，因此第二开关晶体管M2截止。由于Scan3＝0，因此第三开关晶体管M3截止。因此驱动晶体管M0的第一极S处于浮接状态，由于存储电容C1的耦合作用以及分压电容C2的分压作用，可以使驱动晶体管M0的第一极S的电压变为：
Figure PCTCN2018117758-appb-000009
其中c 1代表存储电容C1的电容值，c 2代表分压电容C2的电容值。由于Scan1＝0，因此第一开关晶体管M1截止。由于EM＝1，因此第五开关晶体管M5截止。
在发光阶段T4，Scan1＝0，Scan2＝0，Scan3＝0，Scan4＝0，EM＝0。
由于Scan2＝0，因此第二开关晶体管M2导通，并将第二参考信号线Vref2的电压V ref2提供给驱动晶体管M0的第一极S，使驱动晶体管M0的第一极S的电压为V ref2。根据存储电容C的电荷在跳变前后的电荷守恒原则，驱动晶体管M0的栅极G的电压变为：
Figure PCTCN2018117758-appb-000010
因此，驱动晶体管M0处于饱和状态，根据饱和状态电流特性，驱动晶体管M0产生驱动发光器件L发光的驱动电流I L满足公式：
Figure PCTCN2018117758-appb-000011
其中，V gs为驱动晶体管M0的栅源电压，即
Figure PCTCN2018117758-appb-000012
并且，K为结构参数，且
Figure PCTCN2018117758-appb-000013
μ n代表驱动晶体管M0的迁移率，C ox为单位面积栅氧化层电容，
Figure PCTCN2018117758-appb-000014
为驱动晶体管M0的宽长比，相同结构中这些数值相对稳定，可以算作常量。由于EM＝0，因此第五开关晶体管M5导通，并将驱动晶体管M0的第二极D与发光器件L导通，以将驱动晶体管M0产生的驱动电流I L提供给发光器件L，驱动发光器 件L发光。通过上述驱动电流I L满足的公式可知，驱动晶体管M0驱动发光器件L发光的驱动电流I L仅与数据信号Data的电压V data以及第一参考信号线Vref1的电压V ref1有关，而与驱动晶体管M0的阈值电压V th以及第二参考信号线Vref2的电压V ref2无关，可以解决由于驱动晶体管M0的工艺制程以及长时间的操作造成的阈值电压V th漂移以及IR Drop对驱动发光器件L的驱动电流I L的影响，从而使发光器件L的驱动电流I L保持稳定，进而保证了发光器件L的正常工作。
当然，在复位阶段中，还可以改变第三扫描信号线的信号，以控制第三开关晶体管导通，以对驱动晶体管的栅极进行复位，使其栅极的电压变为V ref3。这样在复位阶段中使驱动晶体管的栅极的电压为V ref3，第二极的电压为V ref1，第一极的电压为V ref2，可以同时对驱动晶体管的三个极进行复位。在阈值补偿阶段，使驱动晶体管的栅极的电压为V ref3，使其第二极的电压为V ref1，驱动晶体管的第一极的电压变为V ref3－V th，即在每帧数据写入阶段之前，使驱动晶体管的栅极可以为固定电压V ref3，使驱动晶体管的第一极可以为固定电压V ref3－V th，以及使驱动晶体管的第二极可以为固定电压V ref1。从而在每次写入数据信号时，可以使驱动晶体管的栅极通过同一固定电压进行跳变，以及使其第一极的电压通过同一固定电压进行跳变，进而可以改善因迟滞效应导致的短期残像的问题。
在另一些实施例中，以图4b所示的像素电路为例对其工作过程进行说明，其对应的输入时序图如图5d所示。具体地，主要选取如图5d所示的输入时序图中的复位阶段T1、阈值补偿阶段T2、数据写入阶段T3和发光阶段T4共四个阶段。
在复位阶段T1，Scan1＝1，Scan4＝0，EM＝0。
由于Scan1＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。导通的第一开关晶体管M1将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，以对驱动晶体管M0的第二极D进行复位。导通的第三开关 晶体管M3将第一参考信号线Vref1的信号提供给驱动晶体管M0的栅极G，以对驱动晶体管M0的栅极G进行复位。由于EM＝0，因此第二开关晶体管M2与第五开关晶体管M5均导通。导通的第二开关晶体管M2将第二参考信号线Vref2的信号提供给驱动晶体管M0的第一极S，以对驱动晶体管M0的第一极S进行复位，以及通过存储电容C1存储第二参考信号线Vref2的信号的电压V ref2。导通的第五开关晶体管M5将驱动晶体管M0的第二极D与发光器件L的第一电极导通，以将第一参考信号线Vref1的信号提供给发光器件L，对发光器件L进行复位，以避免相邻两个显示帧之间的发光干扰。由于Scan4＝0，因此第四开关晶体管M4截止。
在阈值补偿阶段T2，Scan1＝1，Scan4＝0，EM＝1。
由于Scan1＝1，因此第一开关晶体管M1与第三开关晶体管M3均导通。导通的第三开关晶体管M3将第一参考信号线Vref1的信号提供给驱动晶体管M0的栅极，使驱动晶体管M0的栅极电压为V ref1。导通的第一开关晶体管M1将第一参考信号线Vref1的信号提供给驱动晶体管M0的第二极D，使驱动晶体管M0的第二极D的电压为V ref1。由于EM＝1，因此第二开关晶体管M2与第五开关晶体管M5均截止。存储电容C1可以瞬间保持驱动晶体管M0的第一极的电压V ref2，从而使驱动晶体管M0在V ref1与V ref2的作用下导通，以使驱动晶体管M0的第一极S的电压通过导通的驱动晶体管M0放电，直至驱动晶体管M0的第一极S的电压变为：V ref1－V th时，驱动晶体管M0截止，从而将驱动晶体管M0的阈值电压V th写入存储电容C1。从而实现对驱动晶体管M0的阈值电压V th的补偿，且该补偿过程亦不会对发光器件L造成影响。由于Scan4＝0，因此第四开关晶体管M4截止。
在数据写入阶段T3，Scan1＝0，Scan4＝1，EM＝1。
由于Scan4＝1，因此第四开关晶体管M4导通，以将数据信号Data的电压V data提供给驱动晶体管M0的栅极G，使驱动晶体管M0的栅极G的电压变为V data。由于EM＝1，因此第二开关晶体管M2与第五开关晶体管M5均截 止。因此驱动晶体管M0的第一极S处于浮接状态，由于存储电容C1的耦合作用以及分压电容C2的分压作用，可以使驱动晶体管M0的第一极S的电压变为：
Figure PCTCN2018117758-appb-000015
其中c 1代表存储电容C1的电容值，c 2代表分压电容C2的电容值。由于Scan1＝0，因此第一开关晶体管M1与第三开关晶体管M3均截止。
在发光阶段T4，Scan1＝0，Scan4＝0，EM＝0。
由于EM＝0，因此第二开关晶体管M2与第五开关晶体管M5均导通。导通的第二开关晶体管M2将第二参考信号线Vref2的电压V ref2提供给驱动晶体管M0的第一极S，使驱动晶体管M0的第一极S的电压为V ref2。根据存储电容C的电荷在跳变前后的电荷守恒原则，驱动晶体管M0的栅极G的电压变为：
Figure PCTCN2018117758-appb-000016
因此，驱动晶体管M0处于饱和状态，根据饱和状态电流特性，驱动晶体管M0产生驱动发光器件L发光的驱动电流I L满足公式：
Figure PCTCN2018117758-appb-000017
其中，V gs为驱动晶体管M0的栅源电压，即
Figure PCTCN2018117758-appb-000018
并且，K为结构参数，且
Figure PCTCN2018117758-appb-000019
μ n代表驱动晶体管M0的迁移率，C ox为单位面积栅氧化层电容，
Figure PCTCN2018117758-appb-000020
为驱动晶体管M0的宽长比，相同结构中这些数值相对稳定，可以算作常量。导通的第五开关晶体管M5将驱动晶体管M0的第二极D与发光器件L导通，以将驱动晶体管M0产生的驱动电流I L提供给发光器件L，驱动发光器件L发光。通过上述驱动电流I L满足的公式可知，驱动晶体管M0驱动发光器件L发光的驱动电流I L仅与数据信号Data的电压V data以及第一参考信号线Vref1的电压V ref1有关，而与驱动晶体管M0的阈值电压V th以及第二参考信号线Vref2的电压V ref2无关，可以解决由于驱动晶体管M0的工艺制程以及长时间的操作造成的阈值电压V th漂移以及IR Drop对驱动发光器件L 的驱动电流I L的影响，从而使发光器件L的驱动电流I L保持稳定，进而保证了发光器件L的正常工作。
在复位阶段中，通过使驱动晶体管的栅极与第二极的电压分别变为V ref1，驱动晶体管的第一极的电压变为V ref2，可以同时对驱动晶体管的三个极进行复位。在阈值补偿阶段，使驱动晶体管的栅极与第二极的电压分别均为V ref1，驱动晶体管的第一极的电压变为V ref1－V th，即在每帧数据写入阶段之前，使驱动晶体管的栅极可以为固定电压V ref1，使驱动晶体管的第一极可以为固定电压V ref1－V th，以及使驱动晶体管的第二极可以为固定电压V ref1。从而在每次写入数据信号时，可以使驱动晶体管的栅极通过同一固定电压进行跳变，以及使其第一极的电压通过同一固定电压进行跳变，进而可以改善因迟滞效应导致的短期残像的问题。
基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的上述像素电路的驱动方法，如图6所示，包括：
S601、复位阶段，复位电路对驱动晶体管的第一极与第二极进行复位；
S602、数据写入阶段，数据写入电路将数据信号提供给驱动晶体管的栅极；
S603、发光阶段，电容电路存储驱动晶体管的栅极的电压，驱动晶体管生成驱动电流以驱动发光器件发光。
本公开实施例提供的上述驱动方法，可以通过复位电路在复位阶段对驱动晶体管的第一极与第二极进行复位，之后通过数据写入电路将数据信号写入驱动晶体管的栅极，以及通过驱动晶体管生成驱动电流以驱动发光器件发光。这样可以在每次写入数据信号之前使驱动晶体管的第一极的电压设置为固定电压，以及使驱动晶体管的第二极的电压设置为固定电压，从而可以避免上一帧残留的电压对本帧发光造成影响，进而可以提高显示面板的发光均一性。
在具体实施时，在本公开实施例提供的上述驱动方法中，还可以包括： 在复位阶段，复位电路对驱动晶体管的栅极进行复位。
并且在复位阶段之后，且在数据写入阶段之前，本公开实施例提供的上述驱动方法还可以包括：阈值补偿阶段，复位电路对驱动晶体管的阈值电压进行补偿。
在具体实施时，在复位电路包括第一开关晶体管、第二开关晶体管以及第三开关晶体管时，在本公开实施例提供的上述驱动方法中，在复位阶段，分别控制复位电路中的第一开关晶体管导通并将第一参考信号线上的信号提供给驱动晶体管的第二极，第二开关晶体管导通并将第二参考信号线上的信号提供给驱动晶体管的第一极，第三开关晶体管导通并将第三参考信号线上的信号提供给驱动晶体管的栅极。
并且，在阈值补偿阶段，分别控制复位电路中的第二开关晶体管截止，第一开关晶体管导通并将第一参考信号线上的信号提供给驱动晶体管的第二极，第三开关晶体管导通并将第三参考信号线上的信号提供给驱动晶体管的栅极；驱动晶体管导通进行阈值补偿。
在具体实施时，本公开实施例提供的上述驱动方法还可以包括：在复位阶段与发光阶段，发光控制电路将驱动晶体管的第二极与发光器件的第一电极导通。
在具体实施时，通过复位阶段、阈值补偿阶段、数据写入阶段以及发光阶段的作用，可以使驱动晶体管驱动发光器件发光的驱动电流仅与数据信号的电压以及第一参考信号线的信号的电压有关，而与驱动晶体管的阈值电压以及第二参考信号线的信号的电压无关，可以避免驱动晶体管的阈值电压以及第二参考信号线的信号的IR Drop对流过发光器件的驱动电流的影响，从而使驱动发光器件发光的工作电流保持稳定，进而可以提高显示面板中显示画面亮度的均匀性。
基于同一发明构思，本公开实施例还提供了一种电致发光显示面板，如图7所示，可以包括：像素电路(PX)、数据信号线DATA、第一扫描信号线Scan1、第二扫描信号线Scan2、第三扫描信号线Scan3、第四扫描信号线Scan4、 发光控制信号线EMIT、第一参考电压线Vref1、第二参考电压线Vref2、第三参考电压线Vref3；
像素电路PX可以包括：第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第四开关晶体管M4、第五开关晶体管M5、驱动晶体管M0、存储电容C1、分压电容C2以及发光器件L；其中，
第一开关晶体管M1的栅极与向其施加当前对应信号的第一扫描信号线Scan1耦接，第一开关晶体管M1的第一极与第一参考信号线Vref1耦接，第一开关晶体管M1的第二极与驱动晶体管M0的第二极D耦接；
第二开关晶体管M2的栅极与向其施加当前对应信号的第二扫描信号线Scan2耦接，第二开关晶体管M2的第一极与第二参考信号线Vref2耦接，第二开关晶体管M2的第二极与驱动晶体管M0的第一极S耦接；
第三开关晶体管M3的栅极与向其施加当前对应信号的第三扫描信号线Scan3耦接，第三开关晶体管M3的第一极与第三参考信号线Vref3耦接，第三开关晶体管M3的第二极与驱动晶体管M0的栅极G耦接；
第四开关晶体管M4的栅极与向其施加当前对应信号的第四扫描信号线Scan4耦接，第四开关晶体管M4的第一极与向其施加当前对应信号的数据信号线DATA耦接，第四开关晶体管M4的第二极与驱动晶体管M0的栅极G耦接；
第五开关晶体管M5的栅极与向其施加当前对应信号的发光控制信号线EMIT耦接，第五开关晶体管M5的第一极分别与驱动晶体管M0的第二极D以及第一开关晶体管M1的第二极耦接，第五开关晶体管M5的第二极与发光器件L的第一电极耦接；
存储电容C1耦接于驱动晶体管M0的栅极G与第一极S之间；
分压电容C2耦接于驱动晶体管M0的第一极S与第二参考信号线Vref2之间。
本公开实施例提供的电致发光显示面板，通过各信号线输入对应的信号，以控制像素电路中第一开关晶体管、第二开关晶体管、第三开关晶体管、第 四开关晶体管、第五开关晶体管、驱动晶体管、存储电容、分压电容以及发光器件相互配合工作，从而可以实现电致发光显示面板的发光显示。
在具体实施时，在本公开实施例提供的电致发光显示面板中，还可以包括栅极驱动电路；其中，通过栅极驱动电路向第一扫描信号线、第二扫描信号线，第三扫描信号线以及第四扫描信号线提供对应的栅极扫描信号。
在具体实施时，在本公开实施例提供的电致发光显示面板中，还可以包括发光控制电路；其中，通过发光控制电路向发光控制信号线提供对应的发光控制信号。
在具体实施时，在本公开实施例提供的电致发光显示面板中，还可以包括源极驱动电路；其中，通过源极驱动电路向数据信号线提供对应的数据信号。
在具体实施时，本公开实施例提供的电致发光显示面板中的像素电路的工作过程可以参见前述像素电路的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的电致发光显示面板通过将LTPS型晶体管与氧化物型晶体管这两种制备晶体管的工艺进行结合，在降低刷新频率进行显示时，可以保证显示的均一性。
在具体实施时，在本公开实施例提供的电致发光显示面板中，数据信号线与第二参考信号线可以分别与像素电路中的开关晶体管的第一极和第二极同材质且同层设置；并且，第一至第四扫描信号线、发光控制信号线、第一与第三参考信号线可以分别与像素电路中的开关晶体管的栅极同材质且同层设置。这样可以采用一次构图工艺同时形成数据信号线、第二参考信号线以及像素电路中的开关晶体管的第一极和第二极的图形，以及采用另一次构图工艺同时形成各扫描信号线、第一与第三参考信号线、发光控制信号线以及像素电路中的开关晶体管的栅极的图形，可以简化制备工艺，降低电致发光显示面板的厚度。
在具体实施时，在数据信号线与第二参考信号线以及像素电路中的开关晶体管的第一极和第二极同材质且同层设置时，在本公开实施例提供的电致 发光显示面板中，数据信号线可以沿像素电路形成的像素单元的列方向延伸，第二参考信号线沿像素单元的列方向延伸。当然，第二参考信号线也可以采用网格状结构设置在电致发光显示面板中。
在具体实施时，在各扫描信号线、各参考信号线、发光控制信号线以及像素电路中的开关晶体管的栅极同材质且同层设置时，在本公开实施例提供的电致发光显示面板中，各扫描信号线、第一与第三参考信号线、发光控制信号线可以沿像素单元的行方向延伸。并且，由于相邻两行像素单元之间的间隙一般比相邻两列像素单元之间的间隙大，因此将各参考信号线分别沿像素单元的行方向延伸，可以进一步优化电致发光显示面板的版图设计。
为了进一步减少信号线的设置，节省布线空间，在具体实施时，在本公开实施例提供的电致发光显示面板中，可以使与同一像素电路耦接的第一扫描信号线与第三扫描信号线的信号设置为相同。可选地，使与同一像素电路耦接的第一扫描信号线与第三扫描信号线设置为一条信号线。这样可以进一步优化电致发光显示面板的版图设计。具体地，如图8所示，第一开关晶体管M1的栅极与第三开关晶体管M3的栅极均与第一扫描信号线Scan1耦接。
为了进一步减少信号线的设置，节省布线空间，在具体实施时，在本公开实施例提供的电致发光显示面板中，可以使与同一像素电路耦接的发光控制信号线与第二扫描信号线的信号设置为相同。可选地，使与同一像素电路耦接的发光控制信号线与第二扫描信号线设置为一条信号线。这样可以进一步优化电致发光显示面板的版图设计。具体地，如图8所示，第二开关晶体管M2与第五开关晶体管M5均与发光控制信号线EMIT耦接。
为了进一步减少信号线的设置，节省布线空间，在具体实施时，在本公开实施例提供的电致发光显示面板中，可以使第一参考信号线的信号与第三参考信号线的信号设置为相同。可选地，使第一参考信号线与第三参考信号线也设置为一条信号线。这样可以进一步优化电致发光显示面板的版图设计。具体地，如图8所示，第一开关晶体管M1与第三开关晶体管M3均与第一参考信号线Vref1耦接。
本公开实施例提供的电致发光显示面板中的发光器件的阴极可以与现有技术中的设计相同，例如可以是采用一整面的阴极层设计，在此不作赘述。
在具体实施时，本公开实施例提供的电致发光显示面板可以为有机发光显示面板；或者，也可以为量子点发光显示面板，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述电致发光显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述像素电路的实施例，重复之处不再赘述。
本公开实施例提供的像素电路、驱动方法、电致发光显示面板及显示装置，可以通过复位电路在复位阶段对驱动晶体管的第一极与第二极进行复位，之后通过数据写入电路将数据信号写入驱动晶体管的栅极，以及通过驱动晶体管生成驱动电流以驱动发光器件发光。这样可以在每次写入数据信号之前使驱动晶体管的第一极的电压设置为固定电压，以及使驱动晶体管的第二极的电压设置为固定电压，从而可以避免上一帧残留的电压对本帧发光造成影响，进而可以提高显示面板的发光均一性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (28)

  1. 一种像素电路，其中，包括：
    发光器件；
    所述驱动晶体管，被配置为在发光阶段生成驱动电流以驱动所述发光器件发光；其中，所述驱动晶体管的栅极分别与电容电路以及数据写入电路耦接，所述驱动晶体管的第一极与复位电路耦接，所述驱动晶体管的第二极分别与所述复位电路以及所述发光器件的第一电极耦接；
    所述电容电路，被配置为存储所述驱动晶体管的栅极的电压；
    所述数据写入电路，被配置为在数据写入阶段将数据信号提供给所述驱动晶体管的栅极；
    所述复位电路，被配置为在复位阶段对所述驱动晶体管的第一极与第二极进行复位。
  2. 如权利要求1所述的像素电路，其中，所述复位电路还与所述驱动晶体管的栅极耦接，被配置为在所述复位阶段对所述驱动晶体管的栅极进行复位，以及被配置为在阈值补偿阶段对所述驱动晶体管的阈值电压进行补偿。
  3. 如权利要求2所述的像素电路，其中，所述复位电路包括：第一开关晶体管、第二开关晶体管以及第三开关晶体管；
    所述第一开关晶体管的栅极与第一扫描信号线耦接，所述第一开关晶体管的第一极与第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第二开关晶体管的栅极与第二扫描信号线耦接，所述第二开关晶体管的第一极与第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第三开关晶体管的栅极与第三扫描信号线耦接，所述第三开关晶体管的第一极与第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接。
  4. 如权利要求3所述的像素电路，其中，所述第一开关晶体管与所述第三开关晶体管的有源层的材料包括金属氧化物半导体材料；
    所述第二开关晶体管的有源层的材料包括低温多晶硅材料。
  5. 如权利要求3所述的像素电路，其中，所述第一扫描信号线的信号与所述第三扫描信号线的信号相同。
  6. 如权利要求3所述的像素电路，其中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
  7. 如权利要求1所述的像素电路，其中，所述电容电路包括：存储电容与分压电容：
    所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
    所述分压电容耦接于所述驱动晶体管的第一极与第二参考信号线之间。
  8. 如权利要求1所述的像素电路，其中，所述数据写入电路包括第四开关晶体管；
    所述第四开关晶体管的栅极与第四扫描信号线耦接，所述第四开关晶体管的第一极与数据信号线耦接被配置为接收所述数据信号，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接。
  9. 如权利要求8所述的像素电路，其中，所述第四开关晶体管的有源层的材料包括金属氧化物半导体材料。
  10. 如权利要求1所述的像素电路，其中，所述像素电路还包括：发光控制电路；所述驱动晶体管的第二极与所述复位电路分别通过所述发光控制电路与所述发光器件的第一电极耦接；其中，所述发光控制电路被配置为控制所述驱动晶体管的第二极与所述发光器件的第一电极导通或断开。
  11. 如权利要求10所述的像素电路，其中，所述发光控制电路包括：第五开关晶体管；
    所述第五开关晶体管的栅极与发光控制信号线耦接，所述第五开关晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接。
  12. 如权利要求11所述的像素电路，其中，所述第五开关晶体管的有源层的材料包括低温多晶硅材料。
  13. 如权利要求11所述的像素电路，其中，所述发光控制信号线的信号与第二扫描信号线的信号相同。
  14. 如权利要求1-13任一项所述的像素电路，其中，所述驱动晶体管的有源层的材料包括低温多晶硅材料。
  15. 一种像素电路，其中，包括：
    发光器件；
    第一开关晶体管，所述第一开关晶体管的栅极与第一扫描信号线耦接，所述第一开关晶体管的第一极与第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
    第二开关晶体管，所述第二开关晶体管的栅极与第二扫描信号线耦接，所述第二开关晶体管的第一极与第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
    第三开关晶体管，所述第三开关晶体管的栅极与第三扫描信号线耦接，所述第三开关晶体管的第一极与第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
    第四开关晶体管，所述第四开关晶体管的栅极与第四扫描信号线耦接，所述第四开关晶体管的第一极与数据信号线藕接，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接；
    第五开关晶体管，所述第五开关晶体管的栅极与发光控制信号线耦接，所述第五开关晶体管的第一极分别与所述驱动晶体管的第二极以及所述第一开关晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接；
    存储电容，所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
    分压电容，所述分压电容耦接于所述驱动晶体管的第一极与第二参考信号线之间。
  16. 如权利要求15所述的像素电路，其中，所述第一开关晶体管、所述第三开关晶体管以及所述第四开关晶体管的有源层的材料包括金属氧化物半导体材料；
    所述第二开关晶体管、所述第五开关晶体管以及所述驱动晶体管的有源层的材料包括低温多晶硅材料。
  17. 如权利要求15所述的像素电路，其中，所述第一扫描信号线的信号与所述第三扫描信号线的信号相同。
  18. 如权利要求15所述的像素电路，其中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
  19. 如权利要求15所述的像素电路，其中，所述发光控制信号线的信号与所述第二扫描信号线的信号相同。
  20. 一种电致发光显示面板，其中，包括：像素电路、数据信号线、第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制信号线、第一参考电压线、第二参考电压线、第三参考电压线；
    所述像素电路包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、驱动晶体管、存储电容、分压电容以及发光器件；其中，
    所述第一开关晶体管的栅极与向其施加当前对应信号的第一扫描信号线耦接，所述第一开关晶体管的第一极与所述第一参考信号线耦接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第二开关晶体管的栅极与向其施加当前对应信号的第二扫描信号线耦接，所述第二开关晶体管的第一极与所述第二参考信号线耦接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第三开关晶体管的栅极与向其施加当前对应信号的第三扫描信号线耦接，所述第三开关晶体管的第一极与所述第三参考信号线耦接，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第四开关晶体管的栅极与向其施加当前对应信号的第四扫描信号线 耦接，所述第四开关晶体管的第一极与向其施加当前对应信号的数据信号线耦接，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第五开关晶体管的栅极与向其施加当前对应信号的发光控制信号线耦接，所述第五开关晶体管的第一极分别与所述驱动晶体管的第二极以及所述第一开关晶体管的第二极耦接，所述第五开关晶体管的第二极与所述发光器件的第一电极耦接；
    所述存储电容耦接于所述驱动晶体管的栅极与第一极之间；
    所述分压电容耦接于所述驱动晶体管的第一极与所述第二参考信号线之间。
  21. 如权利要求20所述的电致发光显示面板，其中，与同一所述像素电路耦接的第一扫描信号线与第三扫描信号线的信号相同。
  22. 如权利要求20所述的电致发光显示面板，其中，所述第一参考信号线的信号与所述第三参考信号线的信号相同。
  23. 如权利要求20所述的电致发光显示面板，其中，与同一所述像素电路耦接的发光控制信号线与第二扫描信号线的信号相同。
  24. 一种显示装置，其中，包括如权利要求20-23任一项所述的电致发光显示面板。
  25. 一种如权利要求1-14任一项所述的像素电路的驱动方法，其中，包括：
    复位阶段，所述复位电路对所述驱动晶体管的第一极与第二极进行复位；
    数据写入阶段，所述数据写入电路将所述数据信号提供给所述驱动晶体管的栅极；
    发光阶段，所述电容电路存储所述驱动晶体管的栅极的电压，所述驱动晶体管生成驱动电流以驱动所述发光器件发光。
  26. 如权利要求25所述的方法，其中，所述方法还包括：在所述复位阶段，所述复位电路对所述驱动晶体管的栅极进行复位；
    在所述复位阶段之后，且在所述数据写入阶段之前，所述方法还包括： 阈值补偿阶段，所述复位电路对所述驱动晶体管的阈值电压进行补偿。
  27. 如权利要求26所述的方法，其中，在所述复位阶段，分别控制所述复位电路中的第一开关晶体管导通并将所述第一参考信号线的信号提供给所述驱动晶体管的第二极，第二开关晶体管导通并将所述第二参考信号线的信号提供给所述驱动晶体管的第一极，第三开关晶体管导通并将所述第三参考信号线的信号提供给所述驱动晶体管的栅极；
    在所述阈值补偿阶段，分别控制所述复位电路中的第二开关晶体管截止，第一开关晶体管导通并将所述第一参考信号线的信号提供给所述驱动晶体管的第二极，第三开关晶体管导通并将所述第三参考信号线的信号提供给所述驱动晶体管的栅极；所述驱动晶体管导通进行阈值补偿。
  28. 如权利要求25所述的方法，其中，所述方法还包括：在所述复位阶段与所述发光阶段，所述发光控制电路将所述驱动晶体管的第二极与所述发光器件的第一电极导通。
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