WO2019047701A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019047701A1
WO2019047701A1 PCT/CN2018/100818 CN2018100818W WO2019047701A1 WO 2019047701 A1 WO2019047701 A1 WO 2019047701A1 CN 2018100818 W CN2018100818 W CN 2018100818W WO 2019047701 A1 WO2019047701 A1 WO 2019047701A1
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Prior art keywords
circuit
sub
signal
transistor
driving
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PCT/CN2018/100818
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English (en)
French (fr)
Inventor
盖翠丽
林奕呈
张保侠
王玲
李全虎
徐攀
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京东方科技集团股份有限公司
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Priority to US16/331,673 priority Critical patent/US11217160B2/en
Publication of WO2019047701A1 publication Critical patent/WO2019047701A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • OLED has low energy consumption, low production cost, self-luminous, wide viewing angle. And the corresponding speed and other advantages.
  • the pixel circuit design is the core technology content of OLED display, which has important research significance.
  • Some embodiments of the present disclosure provide a pixel circuit including: a data writing sub-circuit, a compensation sub-circuit, a driving sub-circuit, an emission control sub-circuit, and an illuminating sub-circuit.
  • the data writing sub-circuit is connected to the compensation sub-circuit, the driving sub-circuit, the first signal end, and the second signal end.
  • the data writing sub-circuit is configured to input a signal output by the second signal terminal to the compensation sub-circuit and the driving sub-circuit under the control of a signal from the first signal terminal.
  • the compensation sub-circuit is further connected to the driving sub-circuit and the third signal end.
  • the compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit according to a signal output by the data writing sub-circuit under the control of a signal from the third signal end.
  • the illumination control sub-circuit is further connected to the compensation sub-circuit, the driving sub-circuit, the fourth signal end, and the first voltage end.
  • the illumination control sub-circuit is configured to input a signal of the first voltage terminal to the driving sub-circuit and the compensation sub-circuit under control of a signal from the fourth signal terminal.
  • the drive subcircuit is also connected to the illuminating subcircuit.
  • the driving sub-circuit is configured to generate a driving current and input to the illuminating sub-circuit according to a signal output by the illuminating control sub-circuit and a signal output by the data writing sub-circuit.
  • the illuminating subcircuit is also connected to the second voltage terminal.
  • the illuminating sub-circuit is configured to emit light according to a driving current output by the driving sub-circuit under the control of a power supply voltage outputted by the second voltage terminal.
  • the data write subcircuit includes a first transistor. a gate of the first transistor is connected to the first signal end, a first pole of the first transistor is connected to the second signal end, and a second pole of the first transistor is connected to the compensator a circuit and the driver subcircuit.
  • the compensation subcircuit includes a second transistor and a first capacitor.
  • a first end of the first capacitor is coupled to the data write subcircuit, and a second end of the first capacitor is coupled to a first pole of the second transistor.
  • a gate of the second transistor is coupled to the third signal terminal, and a second terminal of the second transistor is coupled to the driver subcircuit.
  • the driver subcircuit includes a third transistor and a second capacitor.
  • the first end of the second capacitor is connected to the first end of the first capacitor, and the second end of the second capacitor is connected to the second pole of the third transistor.
  • a gate of the third transistor is connected to a second end of the first capacitor, a first pole of the third transistor is connected to a second pole of the second transistor, and a second pole of the third transistor Also connected to the illuminating sub-circuit.
  • the illuminating subcircuit includes a light emitting device.
  • An anode of the light emitting device is coupled to the driver subcircuit, and a cathode of the light emitting device is coupled to the second voltage terminal.
  • the light emitting device is an OLED.
  • the illumination control subcircuit includes a fourth transistor.
  • a gate of the fourth transistor is connected to the fourth signal terminal, a first electrode of the fourth transistor is connected to the first voltage terminal, and a second pole of the fourth transistor is connected to the driver a circuit and the compensation subcircuit.
  • the transistors included in the pixel circuit are all N-type transistors.
  • Some embodiments of the present disclosure provide a display device including a plurality of the above-described pixel circuits.
  • the third signal terminals of the plurality of pixel circuits are connected to the same signal input end, and the fourth signal terminals of the plurality of pixel circuits are connected to the same signal input end.
  • Some embodiments of the present disclosure provide a driving method of a pixel circuit, including:
  • the data writing sub-circuit inputs the reset control signal outputted by the second signal terminal to the compensation sub-circuit and the driving sub-circuit under the control of the signal from the first signal end, and the compensation sub-circuit Initializing with the driver subcircuit.
  • the data writing sub-circuit inputs a compensation control signal output by the second signal terminal to the compensation sub-circuit under the control of a signal from the first signal terminal; the compensation The sub-circuit compensates the threshold voltage of the driving sub-circuit under the control of a signal from the third signal terminal.
  • the data writing sub-circuit inputs a data signal output by the second signal terminal to the driving sub-circuit under the control of a signal from the first signal terminal and stores the data signal to the driving sub-circuit The drive subcircuit.
  • the illumination control sub-circuit inputs the power supply voltage outputted from the first voltage terminal to the drive sub-circuit under the control of the signal from the fourth signal terminal, so that the drive sub-circuit generates a drive current.
  • the illuminating sub-circuit emits light according to the driving current under the control of the power supply voltage outputted by the second voltage terminal.
  • the method further includes: controlling, by the illumination control sub-circuit, a signal from the third signal end of the compensation sub-circuit under control of a signal from the fourth signal terminal
  • the reset voltage outputted by the first voltage terminal is input to the driving sub-circuit through the compensation sub-circuit, and the driving sub-circuit is initialized.
  • the data write subcircuit includes a first transistor; the compensation subcircuit includes a second transistor and a first capacitor; and the drive subcircuit includes a third transistor and a second capacitor.
  • the data writing sub-circuit inputs the reset control signal outputted by the second signal terminal to the compensation sub-circuit and the driving sub-circuit under the control of the signal from the first signal end,
  • the compensating subcircuit and the driving subcircuit are initialized, including:
  • the first signal terminal inputs an enable signal to control the first transistor to be turned on, and the reset control signal output by the second signal terminal is output to the first capacitor through the first transistor.
  • the second capacitor initializing the first capacitor and the second capacitor.
  • the data writing sub-circuit inputs a compensation control signal output by the second signal terminal to the compensation under the control of a signal from the first signal terminal.
  • the compensation sub-circuit compensates the threshold voltage of the driving sub-circuit under the control of a signal from the third signal end, including:
  • the first signal terminal inputs an enable signal to control the first transistor to be turned on, and the compensation control signal outputted by the second signal terminal is output to the compensation sub-circuit through the first transistor;
  • the third signal terminal inputs an enable signal, controls the second transistor to be turned on, and performs compensation of a threshold voltage on the driving sub-circuit.
  • the data writing sub-circuit inputs a data signal output by the second signal terminal to the data under the control of a signal from the first signal terminal during a data writing phase of a frame.
  • Driving the sub-circuit and storing to the driving sub-circuit comprising:
  • the first signal terminal inputs an enable signal to control the first transistor to be turned on, and the data signal output by the second signal terminal is output to the second capacitor through the first transistor. And storing to the second capacitor.
  • the illumination control subcircuit includes a fourth transistor; the illumination subcircuit includes a light emitting device. Based on this, in the illumination phase of one frame, the illumination control sub-circuit inputs the power supply voltage outputted by the first voltage terminal to the drive sub-circuit under the control of the signal from the fourth signal terminal, so that the drive sub-circuit is generated.
  • Drive current including:
  • the fourth signal terminal inputs an enable signal to control the fourth transistor to be turned on, and the power voltage outputted by the first voltage terminal is input to the driving sub-circuit through the fourth transistor to The drive subcircuit is caused to generate a drive current.
  • the data writing subcircuit includes a first transistor; the compensation subcircuit includes a second transistor and a first capacitor; the driving subcircuit includes a third transistor and a second capacitor; The subcircuit includes a fourth transistor. Based on this, the illumination control sub-circuit outputs the weight of the first voltage terminal under the control of the signal from the fourth signal terminal under the control of the signal from the third signal terminal.
  • the voltage is input to the driving sub-circuit through the compensation sub-circuit, and the driving sub-circuit is initialized, including:
  • the fourth signal terminal inputs an enable signal to control the fourth transistor to be turned on, and the reset voltage outputted by the first voltage terminal is output to the gate of the third transistor through the fourth transistor, The three transistors are initialized.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram showing a specific structure of each sub-circuit of the pixel circuit shown in FIG. 1;
  • 3(a) is a timing diagram showing various signals used in driving the pixel circuit shown in FIG. 2 according to some embodiments;
  • FIG. 3(b) is a timing diagram showing another signal used in driving the pixel circuit shown in FIG. 2 according to another embodiment
  • 4 to 7 are equivalent circuit diagrams of the pixel circuit shown in FIG. 2 corresponding to different situations;
  • FIG. 8 is a schematic diagram of a pixel circuit simulation effect according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic flowchart of a pixel circuit driving method according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic flow chart of another pixel circuit driving method according to some embodiments of the present disclosure.
  • AMOLED uses a Thin Film Transistor (TFT) to construct a pixel circuit to provide a corresponding current for the OLED device.
  • TFT Thin Film Transistor
  • Low temperature polysilicon thin film transistors (LTPS TFTs) or oxide thin film transistors (Oxide TFTs) are often used.
  • LTPS TFT or Oxide TFT fabricated on a large-area glass substrate often has a problem of threshold voltage drift. Since the threshold drift of each part of the TFT of the display panel is different, the difference in display brightness is caused, and the brightness between the pixel and the pixel is caused. Non-uniformity.
  • some embodiments of the present disclosure provide a pixel circuit, as shown in FIG. 1, including: a data writing sub-circuit 10, a compensation sub-circuit 20, a driving sub-circuit 30, an illumination control sub-circuit 40, and a illuminating sub-circuit 50.
  • the data writing sub-circuit 10 is connected to the compensating sub-circuit 20, the driving sub-circuit 30, the first signal terminal S1, and the second signal terminal S2.
  • the data writing sub-circuit 10 is configured to input the signal output from the second signal terminal S2 to the compensating sub-circuit 20 and the driving sub-circuit 30 under the control of the signal from the first signal terminal S1.
  • the compensation sub-circuit 20 is also connected to the driving sub-circuit 30 and the third signal terminal S3.
  • the compensating sub-circuit 20 is configured to compensate the driving sub-circuit 30 for the threshold voltage based on the signal output from the data writing sub-circuit 10 under the control of the signal from the third signal terminal S3.
  • the illumination control sub-circuit 40 is further connected to the compensation sub-circuit 20, the drive sub-circuit 30, the fourth signal terminal S4, and the first voltage terminal V1.
  • the illumination control sub-circuit 40 is configured to input the signal of the first voltage terminal V1 to the drive sub-circuit 30 and the compensation sub-circuit 20 under the control of the signal from the fourth signal terminal S4.
  • the driving sub-circuit 30 is also connected to the illuminating sub-circuit 50.
  • the drive sub-circuit 30 is configured to generate a drive current based on the signal output from the light emission control sub-circuit 40 and the signal output from the data write sub-circuit 10, and input it to the light-emitting sub-circuit 50.
  • the illuminating sub-circuit 50 is also connected to the second voltage terminal V2.
  • the illuminating sub-circuit 50 is configured to emit light according to the driving current output from the driving sub-circuit 30 under the control of the second voltage terminal V2.
  • the compensation sub-circuit 20 by adding the compensation sub-circuit 20 in the pixel circuit, the threshold voltage generated by the driving sub-circuit 30 is compensated, thereby avoiding different TFTs of the display panel due to different threshold voltage drifts.
  • the problem of the difference in brightness is displayed, thereby improving the uniformity of brightness between pixels and pixels.
  • the data write subcircuit 10 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the first signal terminal S1, the first electrode of the first transistor T1 is connected to the second signal terminal S2, and the second electrode of the first transistor T1 is connected to the compensation sub-circuit 20 and the driving sub-circuit 30 .
  • the data writing sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the first transistor T1.
  • the foregoing is only an example of the data writing sub-circuit 10.
  • the other structures having the same functions as the data writing sub-circuit 10 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the compensation sub-circuit 20 includes a second transistor T2 and a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the data writing sub-circuit 10, and the second end of the first capacitor C1 is connected to the first pole of the second transistor T2.
  • the gate of the second transistor T2 is connected to the third signal terminal S3, and the second electrode of the second transistor T2 is connected to the driving sub-circuit 30.
  • the data write subcircuit 10 includes the first transistor T1
  • the first end of the first capacitor C1 is connected to the second pole of the first transistor T1.
  • the compensation sub-circuit 20 further includes a plurality of switching transistors connected in parallel with the second transistor T2.
  • the above is only an example of the compensating sub-circuit 20, and other structures having the same function as the compensating sub-circuit 20 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the driving sub-circuit 30 includes a third transistor T3 and a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the first end of the first capacitor C1 and the data writing sub-circuit 10, and the second end of the second capacitor C2 is connected to the second pole of the third transistor T3.
  • the gate of the third transistor T3 is connected to the second end of the first capacitor C1, the first pole of the third transistor T3 is connected to the second pole of the second transistor T2 and the light-emitting control sub-circuit 40, and the second of the third transistor T3
  • the illuminating sub-circuit 50 is also connected to the pole.
  • the third transistor T3 is a drive transistor.
  • the first end of the second capacitor C2 is coupled to the second terminal of the first transistor T1 and the first end of the first capacitor C1.
  • the driving sub-circuit 30 further includes a plurality of driving transistors in parallel with the third transistor T3.
  • the above is merely an example of the driving sub-circuit 30.
  • Other structures having the same functions as those of the driving sub-circuit 30 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the illumination control sub-circuit 40 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the fourth signal terminal S4, the first electrode of the fourth transistor T4 is connected to the first voltage terminal V1, and the second electrode of the fourth transistor T4 is connected to the driving sub-circuit 30 and the compensation sub-circuit 20 .
  • the compensation sub-circuit 20 includes the second transistor T2 and the first capacitor C1
  • the driving sub-circuit 30 includes the third transistor T3 and the second capacitor C2
  • the second pole of the fourth transistor T4 is connected to the third transistor T3. a pole and a second pole of the second transistor T2.
  • the illumination control sub-circuit 40 further includes a plurality of switching transistors connected in parallel with the fourth transistor T4.
  • the foregoing is merely an illustration of the illumination control sub-circuit 40.
  • Other structures having the same functions as those of the illumination control sub-circuit 40 are not described herein again, but are all within the scope of the present disclosure.
  • the illuminating sub-circuit 50 includes a light emitting device L.
  • the anode of the light-emitting device L is connected to the driving sub-circuit 30, and the cathode of the light-emitting device L is connected to the second voltage terminal V2.
  • the light emitting device L is an OLED.
  • the driving sub-circuit 30 includes the third transistor T3
  • the anode of the light emitting device L is connected to the second electrode of the third transistor T3.
  • the embodiment of the present disclosure does not limit the types of transistors in each sub-circuit.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type.
  • Transistor, in other embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type transistors.
  • the first pole of the transistor is the drain and the second pole is the source. In other embodiments, the first pole is the source and the second pole is the drain.
  • the transistors in the pixel circuit described above can be classified into an enhancement transistor and a depletion transistor depending on the manner in which the transistors are electrically conductive.
  • the public embodiment does not limit this.
  • the above-described transistors are all N-type transistors as an example.
  • the high voltage is input to the first voltage terminal V1, the second voltage terminal V2 is input to the low level, or the second voltage terminal V2 is grounded as an example. It can be understood that the high and low here only indicate the relative magnitude relationship between the input voltages.
  • the display process of the pixel circuit in each frame is divided into an initialization phase P1, a compensation phase P2, a data writing phase P3, and an illumination phase P4.
  • the first signal terminal S1 and the third signal terminal S3 input a high level ON signal
  • the fourth signal terminal S4 inputs a low level. Cutoff signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 2 is as shown in FIG. 4, the first transistor T1, the second transistor T2, and the third transistor T3 are both turned on, and the fourth transistor T4 is turned off, wherein the transistor in the off state is turned on. Expressed by "X”.
  • the reset control signal S2(x) outputted by the second signal terminal S2 is output to the first of the first capacitor C1 through the first transistor T1.
  • the first signal terminal S1, the third signal terminal S3, and the fourth signal terminal S4 each input a high-level on signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 2 is as shown in FIG. 5.
  • the first transistor T1, the second transistor T2, and the fourth transistor T4 are both turned on, and the third transistor T3 is turned off.
  • the reset control signal S2(x) outputted by the second signal terminal S2 is output to the first of the first capacitor C1 through the first transistor T1.
  • the fourth signal terminal S4 inputs a high-level on signal and controls the fourth transistor T4 to be turned on
  • the reset voltage V1(x) outputted by the first voltage terminal V1 is output to the third transistor T3 through the fourth transistor T4.
  • the gate that is, the point g in FIG. 5, initializes the third transistor T3.
  • the reset voltage V1(x) outputted by the first voltage terminal V1 should control the third transistor T3 to be turned off.
  • the first signal terminal S1 and the third signal terminal S3 input a high level ON signal
  • the fourth signal terminal S4 inputs a low level. Cutoff signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 2 is as shown in FIG. 4, the first transistor T1, the second transistor T2, and the third transistor T3 are both turned on, and the fourth transistor T4 is turned off.
  • the compensation control signal S2(y) outputted by the second signal terminal S2 is output to the compensation sub-circuit 20 through the first transistor T1.
  • the third signal terminal S3 inputs an enable signal to control the second transistor T2 to be turned on
  • the second transistor T2 electrically connects the gate of the third transistor T3 and the first electrode, and releases the voltages of the g and s points.
  • the voltage at the s point is VSS+Voled0
  • the voltage at the point g is VSS+Voled0+Vth
  • the threshold voltage is compensated for the driving sub-circuit 30.
  • VSS is the power supply voltage of the second voltage terminal V2
  • Voled0 is the voltage when the light emitting device does not emit light
  • Vth is the threshold voltage of the third transistor T3.
  • the reset control signal S2(x) output by the second signal terminal S2 is the same as the compensation control signal S2(y).
  • the fourth signal terminal S4 is not input high.
  • the level-on signal ie, as shown in FIG. 3(a)
  • the fourth signal terminal S4 inputs a low-level off signal
  • the voltage at point n is Vref
  • the voltage at point s is VSS+Voled0
  • the voltage at point g is VSS+Voled0+Vth.
  • Vref is the voltage that compensates for the control signal.
  • the first signal terminal S1 inputs a high level on signal
  • the third voltage terminal S3 and the fourth voltage terminal S4 are input low.
  • Level cutoff signal Based on this, the equivalent circuit diagram of the pixel circuit shown in FIG. 2 is as shown in FIG. 6.
  • the first transistor T1 and the third transistor T3 are both turned on, and the second transistor T2 and the fourth transistor T4 are turned off.
  • the data signal S2(z) outputted by the second signal terminal S2 is output to the second capacitor C2 through the first transistor T1 and stored to the second Capacitor C2.
  • the n-point voltage jumps to Vdata
  • the jump variable ⁇ V Vdata-Vref
  • the g-point voltage becomes VSS+Voled0+Vth+Vdata-Vref due to the C2 capacitive coupling action.
  • the voltage at point n is Vdata
  • the voltage at point s is VSS+Voled0
  • the voltage at point g is VSS+Voled0+Vth+Vdata-Vref.
  • Vdata is the voltage of the data signal.
  • the first signal terminal S1 of the pixel circuit located in each row is connected to one gate line, and the gate line inputs the signal row by row, so that in the data writing phase P3, A signal terminal S1 inputs a high level on signal.
  • the fourth signal terminal S4 inputs a high-level turn-on signal, and the third voltage terminal S3 and the first signal terminal S1 are input with a low level. Cutoff signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 2 is as shown in FIG. 7, the third transistor T3 and the fourth transistor T4 are both turned on, and the first transistor T1 and the second transistor T2 are turned off.
  • the fourth signal terminal S4 When the fourth signal terminal S4 inputs a high-level on signal and controls the fourth transistor T4 to be turned on, the power supply voltage VDD outputted from the first voltage terminal V1 is input to the driving sub-circuit 30 through the fourth transistor T4.
  • the driving sub-circuit 30 generates a driving current based on the power supply voltage VDD and the data signal and inputs it to the light emitting device L to drive the light emitting device L to emit light.
  • the voltage at point g is VSS+Voled0+Vth+Vdata-Vref, and the voltage at point s is VSS+Voled.
  • Voled is the voltage when the light emitting device emits light.
  • the third transistor T3 After the third transistor T3 is turned on, when the value of the gate-source voltage Vgs of the third transistor T3 minus the threshold voltage Vth of the third transistor T3 is less than or equal to the drain-source voltage Vds of the third transistor T3, that is, Vgs-Vth ⁇ At Vds, the third transistor T3 can be in a saturated on state. At this time, the driving current I flowing through the third transistor T3 is:
  • K W/L ⁇ C ⁇ u
  • W/L is the aspect ratio of the driving transistor Td
  • C is the dielectric constant of the channel insulating layer
  • u is the channel carrier mobility
  • the driving current I flowing through the third transistor T3 is only related to the structure of the third transistor T3, the data signal outputted by the second signal terminal S2, and the compensation control signal outputted by the second signal terminal S2, and the third transistor T3.
  • the threshold voltage Vth is independent, thereby eliminating the influence of the threshold voltage Vth of the third transistor T3 on the luminance of the light-emitting device L, and improving the uniformity of the luminance of the light-emitting device L.
  • the driving current of the third transistor T3 is independent of VSS, the problem of display unevenness caused by the influence of the voltage drop on the VSS line can be solved, and the driving current of the third transistor T3 is related to Voled0-Voled, and can be to some extent The problem of uneven display caused by aging of the light-emitting device L is compensated.
  • Some embodiments of the present disclosure provide a display device including a plurality of the above-described pixel circuits.
  • the display device may be a product or component having any display function, such as an OLED display, a digital photo frame, a mobile phone, a tablet computer, a navigator, and the like.
  • Some embodiments of the present disclosure provide a display device including any of the pixel circuits described above.
  • the display device includes a plurality of pixel cell arrays, each of which includes any one of the pixel circuits as described above.
  • the display device provided by some embodiments of the present disclosure has the same beneficial effects as the pixel circuits provided by some embodiments of the present disclosure, and details are not described herein again.
  • the third signal terminal S3 of the plurality of pixel circuits is connected to the same signal input terminal, and the fourth signal terminal S4 of the plurality of pixel circuits is connected to the same signal input terminal.
  • the initialization phase P1, the compensation phase P2, and the data writing phase P3 do not emit light in full screen, wherein the initialization phase P1 and the compensation phase P2 are simultaneously performed.
  • the data writing phase P3 is performed in full screen line by line. After the data is written, all the first signal terminal S1 and the third signal terminal S3 are at a low level in the light-emitting phase P4, and the fourth signal terminal S4 is at a high level, and the full screen starts to emit light.
  • each pixel only needs one first signal terminal S1 and one second signal terminal S2, the others are common signals. Therefore, the circuit driving structure is simple, and the cost of the driving IC (Integrated Circuit Integrated Circuit) can be greatly saved.
  • Some embodiments of the present disclosure further provide a driving method of a pixel circuit.
  • the driving method of the pixel circuit includes:
  • the data writing sub-circuit 10 inputs the reset control signal outputted by the second signal terminal S2 to the compensation sub-circuit 20 and the driver under the control of the signal from the first signal terminal S1.
  • the circuit 30 initializes the compensation sub-circuit 20 and the drive sub-circuit 30.
  • the data writing sub-circuit 10 includes a first transistor T1
  • the compensation sub-circuit 20 includes a second transistor T2 and a first capacitor C1
  • the driving sub-circuit 30 includes a third transistor T3 and Two capacitors C2.
  • the data writing sub-circuit 10 inputs the reset control signal output from the second signal terminal S2 to the compensation sub-circuit 20 and the driver under the control of the signal from the first signal terminal S1.
  • the circuit 30 initializes the compensation sub-circuit 20 and the driving sub-circuit 30, including:
  • the first signal terminal S1 inputs a high voltage turn-on signal, controls the first transistor T1 to be turned on, and the reset control signal outputted by the second signal terminal S2 is output to the first capacitor C1 and the second through the first transistor T1.
  • the capacitor C2 initializes the first capacitor C1 and the second capacitor C2.
  • the method of the pixel circuit further includes: S60, the illumination control sub-circuit 40 is compensated under the control of the signal from the fourth signal terminal S4.
  • the sub-circuit 20 inputs the reset voltage output from the first voltage terminal V1 to the driving sub-circuit 30 via the compensating sub-circuit 20 under the control of the signal from the third signal terminal S3, and initializes the driving sub-circuit 30.
  • the data writing sub-circuit 10 includes a first transistor T1
  • the compensation sub-circuit 20 includes a second transistor T2 and a first capacitor C1
  • the driving sub-circuit 30 includes a third transistor T3 and The second capacitor C2
  • the light emission control sub-circuit 40 includes a fourth transistor T4.
  • the illumination control sub-circuit 40 controls the sub-circuit 20 to output the reset voltage of the first voltage terminal V1 under the control of the signal from the third signal terminal S4 under the control of the signal from the third signal terminal S3.
  • the compensation sub-circuit 20 is input to the driving sub-circuit 30 to initialize the driving sub-circuit 30, including
  • the fourth signal terminal S4 inputs an enable signal, controls the fourth transistor T4 to be turned on, and the reset voltage outputted by the first voltage terminal V1 is output to the gate of the third transistor T3 through the fourth transistor T4 to initialize the third transistor T3.
  • the data writing sub-circuit 10 inputs the compensation control signal outputted by the second signal terminal S2 to the compensation sub-circuit 20 under the control from the first signal terminal S1; the compensation sub-circuit 20 is The drive sub-circuit 30 is compensated for the threshold voltage under the control of the signal from the third signal terminal S3.
  • the data writing sub-circuit 10 includes a first transistor T1
  • the compensation sub-circuit 20 includes a second transistor T2 and a first capacitor C1
  • the driving sub-circuit 30 includes a third transistor T3 and Two capacitors C2.
  • the data writing sub-circuit 10 inputs the compensation control signal outputted by the second signal terminal S2 to the compensation sub-circuit 20 under the control from the first signal terminal S1; the compensation sub-circuit 20 Under the control of the signal from the third signal terminal S3, the threshold voltage is compensated for the driving sub-circuit 30, including:
  • the first signal terminal S1 inputs an enable signal to control the first transistor T1 to be turned on, and the compensation control signal outputted by the second signal terminal S2 is output to the compensation sub-circuit 20 through the first transistor T1;
  • the third signal terminal S3 inputs an enable signal, controls the second transistor T2 to be turned on, and compensates the driving sub-circuit 30 for the threshold voltage.
  • the data writing sub-circuit 10 inputs the data signal outputted by the second signal terminal S2 to the driving sub-circuit 30 under the control of the signal from the first signal terminal S1 and stores it to the The sub-circuit 30 is driven.
  • the data writing sub-circuit 10 includes a first transistor T1
  • the compensation sub-circuit 20 includes a second transistor T2 and a first capacitor C1
  • the driving sub-circuit 30 includes a third transistor T3 and Two capacitors C2.
  • the data writing sub-circuit 10 inputs the data signal output from the second signal terminal S2 to the driving sub-circuit 30 and stores it under the control of the signal from the first signal terminal S1.
  • the driver sub-circuit 30 comprising:
  • the first signal terminal S1 inputs an enable signal, controls the first transistor T1 to be turned on, and the data signal outputted by the second signal terminal S2 is output to the second capacitor C2 through the first transistor T1 and stored to the first Two capacitors C2.
  • the lighting control sub-circuit 40 inputs the power voltage outputted by the first voltage terminal V1 to the driving sub-circuit 30 under the control of the signal from the fourth signal terminal S4, so that the driving sub-circuit 30 generates a drive current.
  • the illumination control subcircuit 40 includes a fourth transistor.
  • the lighting control sub-circuit 40 inputs the power supply voltage outputted from the first voltage terminal V1 to the driving sub-circuit 30 under the control of the signal from the fourth signal terminal S4, so that the driver Circuit 30 generates a drive current comprising:
  • the fourth signal terminal S4 inputs an enable signal, and the fourth transistor T4 is controlled to be turned on, and the power supply voltage outputted from the first voltage terminal V1 is input to the driving sub-circuit 30 through the fourth transistor T4 to drive the sub-circuit. 30 generates a drive current.
  • the illuminating sub-circuit 50 includes the light-emitting device L
  • the illuminating sub-circuit 50 emits light according to the driving current output from the driving sub-circuit 30 under the control of the power supply voltage outputted from the second voltage terminal V2.
  • the illuminating sub-circuit 50 emits light according to the driving current output from the driving sub-circuit 30 under the control of the power supply voltage outputted from the second voltage terminal V2.
  • the driving method of the pixel circuit compensates the threshold voltage generated by the driving sub-circuit 30 by adding the compensation sub-circuit 20 in the pixel circuit, thereby preventing the TFT of each part of the display panel from being different in threshold voltage drift. , resulting in a difference in display brightness, which improves the uniformity of brightness between pixels and pixels.

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Abstract

一种像素电路及其驱动方法、显示装置，涉及显示技术领域。该像素电路，包括：数据写入子电路(10)，配置为在来自第一信号端(S1)的信号的控制下，将第二信号端(S2)输出的信号输入至补偿子电路(20)和驱动子电路(30)。补偿子电路(20)，配置为在来自第三信号端(S3)的信号的控制下，根据数据写入子电路(10)输出的信号对驱动子电路(30)进行阈值电压的补偿。发光控制子电路(40)，配置为在来自第四信号端(S4)的信号的控制下，将第一电压端(V1)的信号输入至驱动子电路(30)和补偿子电路(20)。驱动子电路(30)，配置为根据发光控制子电路(40)输出的信号以及数据写入子电路(10)输出的信号，生成驱动电流并输入至发光子电路(50)；发光子电路(50)，配置为在第二电压端(V2)的控制下，根据驱动电流进行发光。

Description

像素电路及其驱动方法、显示装置
本申请要求于2017年9月5日提交中国专利局、申请号为201710792864.5、申请名称为“一种像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示器是目前研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED具有低能耗、生产成本低、自发光、宽视角及相应速度快等优点。其中，像素电路设计是OLED显示器核心技术内容，具有重要的研究意义。
发明内容
本公开的一些实施例提供一种像素电路，包括：数据写入子电路、补偿子电路、驱动子电路、发光控制子电路以及发光子电路。
所述数据写入子电路，连接到所述补偿子电路、所述驱动子电路、第一信号端以及第二信号端。所述数据写入子电路配置为在来自所述第一信号端的信号的控制下，将所述第二信号端输出的信号输入至所述补偿子电路和所述驱动子电路。
所述补偿子电路，还连接到所述驱动子电路以及第三信号端。所述补偿子电路配置为在来自所述第三信号端的信号的控制下，根据所述数据写入子电路输出的信号对所述驱动子电路进行阈值电压的补偿。
所述发光控制子电路，还连接到所述补偿子电路、所述驱动子电路、第四信号端以及第一电压端。所述发光控制子电路配置为在来自所述第四信号端的信号的控制下，将所述第一电压端的信号输入至所述驱动子电路和所述补偿子电路。
所述驱动子电路，还连接到发光子电路。所述驱动子电路配置为根据所述发光控制子电路输出的信号以及所述数据写入子电路输出的信号，生成驱动电流并输入至所述发光子电路。
所述发光子电路，还连接到第二电压端。所述发光子电路配置为在所述第二电压端输出的电源电压的控制下，根据所述驱动子电路输出的驱动电流进行发光。
在一些实施例中，所述数据写入子电路包括第一晶体管。所述第一晶体管的栅极 连接到所述第一信号端，所述第一晶体管的第一极连接到所述第二信号端，所述第一晶体管的第二极连接到所述补偿子电路和所述驱动子电路。
在一些实施例中，所述补偿子电路包括第二晶体管和第一电容。
所述第一电容的第一端连接到所述数据写入子电路，所述第一电容的第二端连接到所述第二晶体管的第一极。所述第二晶体管的栅极连接到所述第三信号端，所述第二晶体管的第二极连接到所述驱动子电路。
在一些实施例中，所述驱动子电路包括第三晶体管和第二电容。
所述第二电容的第一端连接到所述第一电容的第一端，所述第二电容的第二端连接到所述第三晶体管的第二极。所述第三晶体管的栅极连接到所述第一电容的第二端，所述第三晶体管的第一极连接到所述第二晶体管的第二极，所述第三晶体管的第二极还连接到所述发光子电路。
在一些实施例中，所述发光子电路包括发光器件。所述发光器件的阳极连接到所述驱动子电路，所述发光器件的阴极连接到所述第二电压端。
在一些实施例中，所述发光器件为OLED。
在一些实施例中，所述发光控制子电路包括第四晶体管。
所述第四晶体管的栅极连接到所述第四信号端，所述第四晶体管的第一极连接到所述第一电压端，所述第四晶体管的第二极连接到所述驱动子电路和所述补偿子电路。
在一些实施例中，所述像素电路包含的晶体管均为N型晶体管。
本公开的一些实施例提供一种显示装置，包括多个上述的像素电路。
在一些实施例中，多个所述像素电路中的第三信号端连接同一信号输入端，多个所述像素电路中的第四信号端连接同一信号输入端。
本公开的一些实施例提供一种像素电路的驱动方法，包括：
在一帧的初始化阶段，数据写入子电路在来自第一信号端的信号的控制下，将第二信号端输出的重置控制信号输入至补偿子电路和驱动子电路，对所述补偿子电路和所述驱动子电路进行初始化。
在一帧的补偿阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的补偿控制信号输入至所述补偿子电路；所述补偿子电路在来自第三信号端的信号的控制下，对所述驱动子电路进行阈值电压的补偿。
在一帧的数据写入阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的数据信号输入至所述驱动子电路并存储至所述驱动子电路。
在一帧的发光阶段，发光控制子电路在来自第四信号端的信号的控制下，将第一 电压端输出的电源电压输入至所述驱动子电路，以使所述驱动子电路生成驱动电流。
发光子电路在第二电压端输出的电源电压的控制下，根据所述驱动电流发光。
在一些实施例中，在一帧的初始化阶段，所述方法还包括：所述发光控制子电路在来自第四信号端的信号的控制下、所述补偿子电路在来自第三信号端的信号的控制下，将所述第一电压端输出的重置电压经所述补偿子电路输入至所述驱动子电路，对所述驱动子电路进行初始化。
在一些实施例中，所述数据写入子电路包括第一晶体管；所述补偿子电路包括第二晶体管和第一电容；所述驱动子电路包括第三晶体管和第二电容。
在此基础上，在一帧的初始化阶段，数据写入子电路在来自第一信号端的信号的控制下，将第二信号端输出的重置控制信号输入至补偿子电路和驱动子电路，对所述补偿子电路和所述驱动子电路进行初始化，包括：
在一帧的初始化阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的重置控制信号通过所述第一晶体管输出至所述第一电容和所述第二电容，对所述第一电容和所述第二电容进行初始化。
在一些实施例中，在一帧的补偿阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的补偿控制信号输入至所述补偿子电路；所述补偿子电路在来自第三信号端的信号的控制下，对所述驱动子电路进行阈值电压的补偿，包括：
在一帧的补偿阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的补偿控制信号通过所述第一晶体管输出至所述补偿子电路；所述第三信号端输入开启信号，控制所述第二晶体管开启，对所述驱动子电路进行阈值电压的补偿。
在一些实施例中，在一帧的数据写入阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的数据信号输入至所述驱动子电路并存储至所述驱动子电路，包括：
在一帧的数据写入阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的数据信号通过所述第一晶体管输出至所述第二电容并存储至所述第二电容。
在一些实施例中，所述发光控制子电路包括第四晶体管；所述发光子电路包括发光器件。基于此，在一帧的发光阶段，发光控制子电路在来自第四信号端的信号的控制下，将第一电压端输出的电源电压输入至所述驱动子电路，以使所述驱动子电路生成驱动电流，包括：
在一帧的发光阶段，所述第四信号端输入开启信号，控制所述第四晶体管开启，所述第一电压端输出的电源电压通过所述第四晶体管输入至所述驱动子电路，以使所述驱动子电路生成驱动电流。
在一些实施例中，所述数据写入子电路包括第一晶体管；所述补偿子电路包括第二晶体管和第一电容；所述驱动子电路包括第三晶体管和第二电容；所述发光控制子电路包括第四晶体管。基于此，所述发光控制子电路在来自所述第四信号端的信号的控制下、所述补偿子电路在来自所述第三信号端的信号的控制下，将所述第一电压端输出的重置电压经所述补偿子电路输入至所述驱动子电路，对所述驱动子电路进行初始化，包括：
所述第四信号端输入开启信号，控制所述第四晶体管开启，所述第一电压端输出的重置电压通过所述第四晶体管输出至所述第三晶体管的栅极，对所述第三晶体管进行初始化。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对本公开的实施例或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例提供的一种像素电路的结构示意图；
图2为图1所示像素电路的各个子电路的一种具体结构示意图；
图3(a)为公开一些实施例提供的一种用于驱动图2所示的像素电路时采用的各个信号的时序图；
图3(b)为公开一些实施例提供的另一种用于驱动图2所示的像素电路时采用的各个信号的时序图；
图4-图7为图2所示的像素电路对应不同情况时的等效电路图；
图8为本公开一些实施例提供的一种像素电路模拟效果图；
图9为本公开一些实施例提供的一种像素电路驱动方法流程示意图；
图10为本公开一些实施例提供的另一种像素电路驱动方法流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
AMOLED采用薄膜晶体管(Thin Film Transistor，TFT)构建像素电路为OLED器件提供相应的电流。多采用低温多晶硅薄膜晶体管(LTPS TFT)或氧化物薄膜晶体管(Oxide TFT)。然而，在大面积玻璃基板上制作的LTPS TFT或Oxide TFT，常常存在阈值电压漂移的问题，由于显示面板各部分TFT的阈值漂移量不同，会造成显示亮度差异，使得像素和像素之间的亮度非均匀性。
基于此，本公开一些实施例提供一种像素电路，如图1所示，包括：数据写入子电路10、补偿子电路20、驱动子电路30、发光控制子电路40以及发光子电路50。
数据写入子电路10，连接到补偿子电路20、驱动子电路30、第一信号端S1以及第二信号端S2。数据写入子电路10配置为在来自第一信号端S1的信号的控制下，将第二信号端S2输出的信号输入至补偿子电路20和驱动子电路30。
补偿子电路20，还连接到驱动子电路30以及第三信号端S3。补偿子电路20配置为在来自第三信号端S3的信号的控制下，根据数据写入子电路10输出的信号对驱动子电路30进行阈值电压的补偿。
发光控制子电路40，还连接到补偿子电路20、驱动子电路30、第四信号端S4以及第一电压端V1。发光控制子电路40配置为在来自第四信号端S4的信号的控制下，将第一电压端V1的信号输入至驱动子电路30和补偿子电路20。
驱动子电路30，还连接到发光子电路50。驱动子电路30配置为根据发光控制子电路40输出的信号以及数据写入子电路10输出的信号，生成驱动电流并输入至发光子电路50。
发光子电路50，还连接到第二电压端V2。发光子电路50配置为在第二电压端V2的控制下，根据驱动子电路30输出的驱动电流进行发光。
在本公开一些实施例提供的像素电路中，通过在像素电路中增加补偿子电路20，对驱动子电路30产生的阈值电压进行补偿，避免了显示面板各部分TFT因阈值电压漂移量不同，造成的显示亮度差异的问题，从而提高了像素和像素之间亮度的均匀性。
在一些实施例中，如图2所示，数据写入子电路10包括第一晶体管T1。
第一晶体管T1的栅极连接到第一信号端S1，第一晶体管T1的第一极连接到第二信号端S2，第一晶体管T1的第二极连接到补偿子电路20和驱动子电路30。
需要说明的是，在另一些实施例中，所述数据写入子电路10还包括与第一晶体管T1并联的多个开关晶体管。上述仅仅是对数据写入子电路10的举例说明，其它与该数据写入子电路10功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图2所示，补偿子电路20包括第二晶体管T2和第一电容C1。
第一电容C1的第一端连接到数据写入子电路10，第一电容C1的第二端连接到第二晶体管T2的第一极。
第二晶体管T2的栅极连接到第三信号端S3，第二晶体管T2的第二极连接到驱动子电路30。
在数据写入子电路10包括第一晶体管T1的情况下，第一电容C1的第一端连接到第一晶体管T1的第二极。
需要说明的是，在另一些实施例中，所述补偿子电路20还包括与第二晶体管T2并联的多个开关晶体管。上述仅仅是对补偿子电路20的举例说明，其它与补偿子电路20功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图2所示，驱动子电路30包括第三晶体管T3和第二电容C2。
第二电容C2的第一端连接到第一电容C1的第一端和数据写入子电路10，第二电容C2的第二端连接到第三晶体管T3的第二极。
第三晶体管T3的栅极连接到第一电容C1的第二端，第三晶体管T3的第一极连接到第二晶体管T2的第二极和发光控制子电路40，第三晶体管T3的第二极还连接发光子电路50。
此处，第三晶体管T3为驱动晶体管。
在数据写入子电路10包括第一晶体管T1的情况下，第二电容C2的第一端连接到第一晶体管T1的第二极和第一电容C1的第一端。
需要说明的是，在另一些实施例中，所述驱动子电路30还包括与第三晶体管T3并联的多个驱动晶体管。上述仅仅是对驱动子电路30的举例说明，其它与驱动子电路30功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图2所示，发光控制子电路40包括第四晶体管T4。
第四晶体管T4的栅极连接到第四信号端S4，第四晶体管T4的第一极连接到第一电压端V1，第四晶体管T4的第二极连接到驱动子电路30和补偿子电路20。
在补偿子电路20包括第二晶体管T2和第一电容C1，驱动子电路30包括第三晶体管T3和第二电容C2的情况下，第四晶体管T4的第二极连接到第三晶体管T3的第一极和第二晶体管T2的第二极。
需要说明的是，在另一些实施例中，所述发光控制子电路40还包括与第四晶体管T4并联的多个开关晶体管。上述仅仅是对发光控制子电路40的举例说明，其它与发光控制子电路40功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图2所示，发光子电路50包括发光器件L。发光器件L的阳 极连接到驱动子电路30，发光器件L的阴极连接到第二电压端V2。
在一些实施例中，发光器件L为OLED。
在驱动子电路30包括第三晶体管T3的情况下，发光器件L的阳极连接到第三晶体管T3的第二极。
基于上述对各子电路具体电路的描述，以下结合图2、图3(a)和图3(b)对上述的像素驱动电路的具体驱动过程进行详细的说明。
需要说明的是，本公开实施例对各个子电路中的晶体管的类型不做限定，在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4为N型晶体管，在另一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4为P型晶体管。
在一些实施例中，晶体管的第一极是漏极、第二极是源极。在另一些实施例中，第一极是源极、第二极是漏极。
此外，根据晶体管导电方式的不同，可以将上述的像素电路中的晶体管分为增强型晶体管和耗尽型晶体管。本公共的实施例对此不作限制。
以下实施例以上述的晶体管(第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4)均为N型晶体管为例进行的说明。此外，以第一电压端V1输入高电平，第二电压端V2输入低电平，或将第二电压端V2接地处理为例进行的说明。可以理解的是，这里的高、低仅表示输入的电压之间的相对大小关系。
如图3(a)和图3(b)所示，该像素电路在每一帧的显示过程分为初始化阶段P1、补偿阶段P2、数据写入阶段P3、发光阶段P4。
在一些实施例中，如图3(a)所示，在一帧的初始化阶段P1，第一信号端S1、第三信号端S3输入高电平开启信号，第四信号端S4输入低电平截止信号。基于此，图2所示的像素电路的等效电路图如图4所示，第一晶体管T1、第二晶体管T2以及第三晶体管T3均开启，第四晶体管T4截止，其中，处于截止状态的晶体管以打“×”表示。
当第一信号端S1输入高电平开启信号，控制第一晶体管T1开启时，第二信号端S2输出的重置控制信号S2(x)通过第一晶体管T1输出至第一电容C1的第一端和第二电容C2的第一端，也就是图4中的n点，对第一电容C1和第二电容C2进行初始化。
在另一些实施例中，如图3(b)所示，在一帧的初始化阶段P1，第一信号端S1、第三信号端S3以及第四信号端S4均输入高电平开启信号。基于此，图2所示的像素电路的等效电路图如图5所示，第一晶体管T1、第二晶体管T2以及第四晶体管T4均开启，第三晶体管T3截止。
当第一信号端S1输入高电平开启信号，控制第一晶体管T1开启时，第二信号端S2输出的重置控制信号S2(x)通过第一晶体管T1输出至第一电容C1的第一端和第二电容C2的第一端，也就是图5中的n点，对第一电容C1和第二电容C2进行初始化。与此同时，当第四信号端S4输入高电平开启信号，控制第四晶体管T4开启时，第一电压端V1输出的重置电压V1(x)通过第四晶体管T4输出至第三晶体管T3的栅极，也就是图5中的g点，对第三晶体管T3进行初始化。在此情况下，为避免发光子电路50发光，第一电压端V1输出的重置电压V1(x)应控制第三晶体管T3截止。
如图3(a)和图3(b)所示，在一帧的补偿阶段P2，第一信号端S1、第三信号端S3输入高电平开启信号，第四信号端S4输入低电平截止信号。基于此，图2所示的像素电路的等效电路图如图4所示，第一晶体管T1、第二晶体管T2以及第三晶体管T3均开启，第四晶体管T4截止。
当第一信号端S1输入高电平开启信号，控制第一晶体管T1开启时，第二信号端S2输出的补偿控制信号S2(y)通过第一晶体管T1输出至补偿子电路20。与此同时，当第三信号端S3输入开启信号，控制第二晶体管T2开启时，第二晶体管T2将第三晶体管T3的栅极和第一极电连接，将g点和s点的电压释放，使得s点的电压为VSS+Voled0，g点的电压为VSS+Voled0+Vth，对驱动子电路30进行阈值电压的补偿。其中，VSS为第二电压端V2的电源电压，Voled0为发光器件不发光时的电压，Vth为第三晶体管T3的阈值电压。
在一些实施例中，第二信号端S2输出的重置控制信号S2(x)和补偿控制信号S2(y)相同，在此基础上，若在初始化阶段P1，第四信号端S4不输入高电平开启信号(即，如图3(a)所示，第四信号端S4输入低电平截止信号)，这样一来，如图3(a)中的初始化阶段P1和补偿阶段P2可以合并为一个阶段来完成。
如此，在补偿阶段P2结束时，n点的电压为Vref，s点的电压为VSS+Voled0，g点的电压为VSS+Voled0+Vth。Vref为补偿控制信号的电压。
如图3(a)和图3(b)所示，在一帧的数据写入阶段P3，第一信号端S1输入高电平开启信号，第三电压端S3和第四电压端S4输入低电平截止信号。基于此，图2所示的像素电路的等效电路图如图6所示，第一晶体管T1以及第三晶体管T3均开启，第二晶体管T2以及第四晶体管T4截止。
当第一信号端S1输入高电平开启信号，控制第一晶体管T1开启时，第二信号端S2输出的数据信号S2(z)通过第一晶体管T1输出至第二电容C2并存储至第二电容C2。此时，n点电压跳变到Vdata，跳变量ΔV＝Vdata-Vref，g点电压由于C2电容耦合作用，变为VSS+Voled0+Vth+Vdata-Vref。
如此，在补偿阶段P2结束时，n点的电压为Vdata，s点的电压为VSS+Voled0，g点的电压为VSS+Voled0+Vth+Vdata-Vref。Vdata为数据信号的电压。
需要说明的是，当该像素电路应用于显示面板时，位于每行的像素电路的第一信号端S1与一根栅线连接，栅线逐行输入信号，使得在数据写入阶段P3，第一信号端S1输入高电平开启信号。
如图3(a)和图3(b)所示，在一帧的发光阶段P4，第四信号端S4输入高电平开启信号，第三电压端S3和第一信号端S1输入低电平截止信号。基于此，图2所示的像素电路的等效电路图如图7所示，第三晶体管T3以及第四晶体管T4均开启，第一晶体管T1以及第二晶体管T2截止。
当第四信号端S4输入高电平开启信号，控制第四晶体管T4开启时，第一电压端V1输出的电源电压VDD通过第四晶体管T4输入至驱动子电路30。驱动子电路30根据电源电压VDD以及数据信号，生成驱动电流并输入至发光器件L，以驱动发光器件L发光。
在发光阶段P4，g点电压为VSS+Voled0+Vth+Vdata-Vref，s点电压为VSS+Voled。其中，Voled是发光器件发光时的电压。
第三晶体管T3开启后，当第三晶体管T3的栅-源电压Vgs减去第三晶体管T3的阈值电压Vth得到的值小于等于第三晶体管T3的漏-源电压Vds时，即Vgs-Vth≤Vds时，第三晶体管T3能够处于饱和开启状态。此时，流过第三晶体管T3的驱动电流I为：
Figure PCTCN2018100818-appb-000001
其中，K＝W/L×C×u，W/L为驱动晶体管Td的宽长比，C为沟道绝缘层的介电常数，u为沟道载流子迁移率。
由此可知，流过第三晶体管T3的驱动电流I只与第三晶体管T3的结构、第二信号端S2输出的数据信号和第二信号端S2输出的补偿控制信号有关，与第三晶体管T3的阈值电压Vth无关，从而消除了第三晶体管T3的阈值电压Vth对发光器件L发光亮度的影响，提高了发光器件L亮度的均一性。此外，由于第三晶体管T3的驱动电流与VSS无关，因此可以解决VSS线上压降影响造成的显示不均匀的问题，而第三晶体管T3的驱动电流与Voled0-Voled有关，可以在一定程度上补偿发光器件L老化带来的显示不均匀的问题。
图8为本公开一些实施例提供的像素电路在进行仿真实验后的仿真效果图。从图8可以看出，在Vth不同时，例如Vth＝1v和Vth＝2v，发光电流相同。由此可知，本公开一些实施例提供的像素电路很好的补偿了第三晶体管T3的Vth不均匀性。
本公开一些实施例提供一种显示装置，包括多个上述的像素电路。
其中，显示装置可以是OLED显示器、数码相框、手机、平板电脑、导航仪等具有任何显示功能的产品或者部件。
本公开的一些实施例提供一种显示装置，包括如上所述的任意一种像素电路。所述显示装置包括多个像素单元阵列，每一个像素单元包括如上所述的任意一个像素电路。本公开的一些实施例提供的显示装置具有与本公开的一些实施例提供的像素电路相同的有益效果，此处不再赘述。
在一些实施例中，多个像素电路中的第三信号端S3连接同一信号输入端，多个像素电路中的第四信号端S4连接同一信号输入端。
像素电路的各阶段中，初始化阶段P1、补偿阶段P2和数据写入阶段P3全屏不发光，其中，初始化阶段P1和补偿阶段P2同时进行。数据写入阶段P3全屏逐行进行。当写完数据之后，在发光阶段P4所有第一信号端S1和第三信号端S3处于低电平，第四信号端S4为高电平，全屏开始发光。
由于每个像素只需一个第一信号端S1，一个第二信号端S2，其它均为公共信号，因而，该电路驱动结构简单，可以大大节省驱动IC(Integrated Circuit集成电路)的成本。
本公开一些实施例还提供一种像素电路的驱动方法，如图9所示，该像素电路的驱动方法包括：
S10、在一帧的初始化阶段P1，数据写入子电路10在来自第一信号端S1的信号的控制下，将第二信号端S2输出的重置控制信号输入至补偿子电路20和驱动子电路30，对补偿子电路20和驱动子电路30进行初始化。
在一些实施例中，如图2所示，数据写入子电路10包括第一晶体管T1，补偿子电路20包括第二晶体管T2和第一电容C1，驱动子电路30包括第三晶体管T3和第二电容C2。
基于此，在一帧的初始化阶段，数据写入子电路10在来自第一信号端S1的信号的控制下，将第二信号端S2输出的重置控制信号输入至补偿子电路20和驱动子电路30，对补偿子电路20和驱动子电路30进行初始化，包括：
在一帧的初始化阶段P1，第一信号端S1输入高压开启信号，控制第一晶体管T1开启，第二信号端S2输出的重置控制信号通过第一晶体管T1输出至第一电容C1和 第二电容C2，对第一电容C1和第二电容C2进行初始化。
在一些实施例中，如图10所示，在一帧的初始化阶段P1，所述像素电路的方法还包括：S60、发光控制子电路40在来自第四信号端S4的信号的控制下、补偿子电路20在来自第三信号端S3的信号的控制下，将第一电压端V1输出的重置电压经补偿子电路20输入至驱动子电路30，对驱动子电路30进行初始化。
在一些实施例中，如图2所示，数据写入子电路10包括第一晶体管T1，补偿子电路20包括第二晶体管T2和第一电容C1，驱动子电路30包括第三晶体管T3和第二电容C2，发光控制子电路40包括第四晶体管T4。
基于此，发光控制子电路40在来自第四信号端S4的信号的控制下、补偿子电路20在来自第三信号端S3的信号的控制下，将第一电压端V1输出的重置电压经补偿子电路20输入至驱动子电路30，对驱动子电路30进行初始化，包括
第四信号端S4输入开启信号，控制第四晶体管T4开启，第一电压端V1输出的重置电压通过第四晶体管T4输出至第三晶体管T3的栅极，对第三晶体管T3进行初始化。
S20、在一帧的补偿阶段P2，数据写入子电路10在来自第一信号端S1的控制下，将第二信号端S2输出的补偿控制信号输入至补偿子电路20；补偿子电路20在来自第三信号端S3的信号的控制下，对驱动子电路30进行阈值电压的补偿。
在一些实施例中，如图2所示，数据写入子电路10包括第一晶体管T1，补偿子电路20包括第二晶体管T2和第一电容C1，驱动子电路30包括第三晶体管T3和第二电容C2。
基于此，在一帧的补偿阶段P2，数据写入子电路10在来自第一信号端S1的控制下，将第二信号端S2输出的补偿控制信号输入至补偿子电路20；补偿子电路20在来自第三信号端S3的信号的控制下，对驱动子电路30进行阈值电压的补偿，包括：
在一帧的补偿阶段P2，第一信号端S1输入开启信号，控制第一晶体管T1开启，第二信号端S2输出的补偿控制信号通过第一晶体管T1输出至补偿子电路20；第三信号端S3输入开启信号，控制第二晶体管T2开启，对驱动子电路30进行阈值电压的补偿。
S30、在一帧的数据写入阶段P3，数据写入子电路10在来自第一信号端S1的信号的控制下，将第二信号端S2输出的数据信号输入至驱动子电路30并存储至驱动子电路30。
在一些实施例中，如图2所示，数据写入子电路10包括第一晶体管T1，补偿子电路20包括第二晶体管T2和第一电容C1，驱动子电路30包括第三晶体管T3和第二 电容C2。
基于此，在一帧的数据写入阶段P3，数据写入子电路10在来自第一信号端S1的信号的控制下，将第二信号端S2输出的数据信号输入至驱动子电路30并存储至驱动子电路30，包括：
在一帧的数据写入阶段P3，第一信号端S1输入开启信号，控制第一晶体管T1开启，第二信号端S2输出的数据信号通过第一晶体管T1输出至第二电容C2并存储至第二电容C2。
S40、在一帧的发光阶段P4，发光控制子电路40在来自第四信号端S4的信号的控制下，将第一电压端V1输出的电源电压输入至驱动子电路30，以使驱动子电路30生成驱动电流。
在一些实施例中，发光控制子电路40包括第四晶体管。
基于此，在一帧的发光阶段P4，发光控制子电路40在来自第四信号端S4的信号的控制下，将第一电压端V1输出的电源电压输入至驱动子电路30，以使驱动子电路30生成驱动电流，包括：
在一帧的发光阶段P4，第四信号端S4输入开启信号，控制第四晶体管T4开启，第一电压端V1输出的电源电压通过第四晶体管T4输入至驱动子电路30，以使驱动子电路30生成驱动电流。
在此基础上，在发光子电路50包括发光器件L的情况下，在第二电压端V2输出的电源电压的控制下，发光子电路50根据驱动子电路30输出的驱动电流发光。
S50、发光子电路50在第二电压端V2输出的电源电压的控制下，根据驱动子电路30输出的驱动电流发光。
本公开一些实施例提供的像素电路的驱动方法，通过在像素电路中增加补偿子电路20，对驱动子电路30产生的阈值电压进行补偿，从而可以避免显示面板各部分TFT因阈值电压漂移量不同，造成的显示亮度差异，可提高像素和像素之间亮度的均匀性。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种像素电路，包括：数据写入子电路、补偿子电路、驱动子电路、发光控制子电路以及发光子电路；
    所述数据写入子电路，连接到所述补偿子电路、所述驱动子电路、第一信号端以及第二信号端；所述数据写入子电路配置为在来自所述第一信号端的信号的控制下，将所述第二信号端输出的信号输入至所述补偿子电路和所述驱动子电路；
    所述补偿子电路，还连接到所述驱动子电路以及第三信号端；所述补偿子电路配置为在来自所述第三信号端的信号的控制下，根据所述数据写入子电路输出的信号对所述驱动子电路进行阈值电压的补偿；
    所述发光控制子电路，还连接到所述补偿子电路、所述驱动子电路、第四信号端以及第一电压端；所述发光控制子电路配置为在来自所述第四信号端的信号的控制下，将所述第一电压端的信号输入至所述驱动子电路和所述补偿子电路；
    所述驱动子电路，还连接到发光子电路；所述驱动子电路配置为根据所述发光控制子电路输出的信号以及所述数据写入子电路输出的信号，生成驱动电流并输入至所述发光子电路；
    所述发光子电路，还连接到第二电压端；所述发光子电路配置为在所述第二电压端输出的电源电压的控制下，根据所述驱动子电路输出的所述驱动电流进行发光。
  2. 根据权利要求1所述的像素电路，其中，所述数据写入子电路包括第一晶体管；
    所述第一晶体管的栅极连接到所述第一信号端，所述第一晶体管的第一极连接到所述第二信号端，所述第一晶体管的第二极连接到所述补偿子电路和所述驱动子电路。
  3. 根据权利要求1所述的像素电路，其中，所述补偿子电路包括第二晶体管和第一电容；
    所述第一电容的第一端连接到所述数据写入子电路，所述第一电容的第二端连接到所述第二晶体管的第一极；
    所述第二晶体管的栅极连接到所述第三信号端，所述第二晶体管的第二极连接到所述驱动子电路。
  4. 根据权利要求3所述的像素电路，其中，所述驱动子电路包括第三晶体管和第二电容；
    所述第二电容的第一端连接到所述第一电容的第一端，所述第二电容的第二端连接到所述第三晶体管的第二极；
    所述第三晶体管的栅极连接到所述第一电容的第二端，所述第三晶体管的第一极连接到所述第二晶体管的第二极，所述第三晶体管的第二极还连接到所述发光子电路。
  5. 根据权利要求4所述的像素电路，其中，所述发光子电路包括发光器件；
    所述发光器件的阳极连接到所述驱动子电路，所述发光器件的阴极连接到所述第二电压端。
  6. 根据权利要求5所述的像素电路，其中，所述发光器件为OLED。
  7. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括第四晶体管；
    所述第四晶体管的栅极连接到所述第四信号端，所述第四晶体管的第一极连接到所述第一电压端，所述第四晶体管的第二极连接到所述驱动子电路和所述补偿子电路。
  8. 根据权利要求1所述的像素电路，其中，所述像素电路包含的晶体管均为N型晶体管。
  9. 一种显示装置，包括多个权利要求1所述的像素电路。
  10. 根据权利要求9所述的显示装置，其中，多个所述像素电路中的第三信号端连接同一信号输入端，多个所述像素电路中的第四信号端连接同一信号输入端。
  11. 一种像素电路的驱动方法，包括：
    在一帧的初始化阶段，数据写入子电路在来自第一信号端的信号的控制下，将第二信号端输出的重置控制信号输入至补偿子电路和驱动子电路，对所述补偿子电路和所述驱动子电路进行初始化；
    在一帧的补偿阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的补偿控制信号输入至所述补偿子电路；所述补偿子电路在来自第三信号端的信号的控制下，对所述驱动子电路进行阈值电压的补偿；
    在一帧的数据写入阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的数据信号输入至所述驱动子电路并存储至所述驱动子电路；
    在一帧的发光阶段，发光控制子电路在来自第四信号端的信号的控制下，将第一电压端输出的电源电压输入至所述驱动子电路，以使所述驱动子电路生成驱动电流；
    发光子电路在第二电压端输出的电源电压的控制下，根据所述驱动电流发光。
  12. 根据权利要求11所述的像素电路的驱动方法，其中，在一帧的初始化阶段，所述驱动方法还包括：
    所述发光控制子电路在来自所述第四信号端的信号的控制下、所述补偿子电路在来自所述第三信号端的信号的控制下，将所述第一电压端输出的重置电压经所述补偿子电路输入至所述驱动子电路，对所述驱动子电路进行初始化。
  13. 根据权利要求11所述的像素电路的驱动方法，其中，所述数据写入子电路包括第一晶体管；所述补偿子电路包括第二晶体管和第一电容；所述驱动子电路包括第 三晶体管和第二电容；
    在一帧的初始化阶段，数据写入子电路在来自第一信号端的信号的控制下，将第二信号端输出的重置控制信号输入至补偿子电路和驱动子电路，对所述补偿子电路和所述驱动子电路进行初始化，包括：
    在一帧的初始化阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的重置控制信号通过所述第一晶体管输出至所述第一电容和所述第二电容，对所述第一电容和所述第二电容进行初始化。
  14. 根据权利要求13所述的像素电路的驱动方法，其中，在一帧的补偿阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的补偿控制信号输入至所述补偿子电路；所述补偿子电路在来自第三信号端的信号的控制下，对所述驱动子电路进行阈值电压的补偿，包括：
    在一帧的补偿阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的补偿控制信号通过所述第一晶体管输出至所述补偿子电路；所述第三信号端输入开启信号，控制所述第二晶体管开启，对所述驱动子电路进行阈值电压的补偿。
  15. 根据权利要求13所述的像素电路的驱动方法，其中，在一帧的数据写入阶段，所述数据写入子电路在来自所述第一信号端的信号的控制下，将所述第二信号端输出的数据信号输入至所述驱动子电路并存储至所述驱动子电路，包括：
    在一帧的数据写入阶段，所述第一信号端输入开启信号，控制所述第一晶体管开启，所述第二信号端输出的数据信号通过所述第一晶体管输出至所述第二电容并存储至所述第二电容。
  16. 根据权利要求13所述的像素电路的驱动方法，其中，所述发光控制子电路包括第四晶体管；
    在一帧的发光阶段，发光控制子电路在来自第四信号端的信号的控制下，将第一电压端输出的电源电压输入至所述驱动子电路，以使所述驱动子电路生成驱动电流，包括：
    在一帧的发光阶段，所述第四信号端输入开启信号，控制所述第四晶体管开启，所述第一电压端输出的电源电压通过所述第四晶体管输入至所述驱动子电路，以使所述驱动子电路生成驱动电流。
  17. 根据权利要求12所述的像素电路的驱动方法，其中，所述数据写入子电路包括第一晶体管；所述补偿子电路包括第二晶体管和第一电容；所述驱动子电路包括第三晶体管和第二电容；所述发光控制子电路包括第四晶体管；
    所述发光控制子电路在来自所述第四信号端的信号的控制下、所述补偿子电路在来自所述第三信号端的信号的控制下，将所述第一电压端输出的重置电压经所述补偿子电路输入至所述驱动子电路，对所述驱动子电路进行初始化，包括：
    所述第四信号端输入开启信号，控制所述第四晶体管开启，所述第一电压端输出的重置电压通过所述第四晶体管输出至所述第三晶体管的栅极，对所述第三晶体管进行初始化。
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CN103531151A (zh) * 2013-11-04 2014-01-22 京东方科技集团股份有限公司 Oled像素电路及驱动方法、显示装置
CN103594059A (zh) * 2013-11-29 2014-02-19 中国科学院上海高等研究院 有源矩阵有机发光二极管像素驱动电路及其驱动方法
CN104700778A (zh) * 2015-03-27 2015-06-10 深圳市华星光电技术有限公司 Amoled像素驱动电路及像素驱动方法
CN107369412A (zh) * 2017-09-05 2017-11-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN207115975U (zh) * 2017-09-05 2018-03-16 京东方科技集团股份有限公司 一种像素电路、显示装置

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