WO2022133978A1 - 显示面板、像素电路及显示装置 - Google Patents

显示面板、像素电路及显示装置 Download PDF

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Publication number
WO2022133978A1
WO2022133978A1 PCT/CN2020/139265 CN2020139265W WO2022133978A1 WO 2022133978 A1 WO2022133978 A1 WO 2022133978A1 CN 2020139265 W CN2020139265 W CN 2020139265W WO 2022133978 A1 WO2022133978 A1 WO 2022133978A1
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Prior art keywords
transistor
sub
electrically connected
circuit
electrode
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PCT/CN2020/139265
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English (en)
French (fr)
Inventor
王文涛
史大为
赵东升
杨璐
王培�
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/620,599 priority Critical patent/US11915645B2/en
Priority to PCT/CN2020/139265 priority patent/WO2022133978A1/zh
Priority to CN202080003677.4A priority patent/CN115280405A/zh
Publication of WO2022133978A1 publication Critical patent/WO2022133978A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a pixel circuit and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED display devices are widely used because of their self-luminescence, fast response, wide viewing angle and can be fabricated on flexible substrates, etc.
  • OLED display devices include multiple sub-pixels, Each sub-pixel includes a pixel circuit and a light-emitting device, and the pixel circuit drives the light-emitting device to emit light, thereby realizing display.
  • a display panel comprising: a substrate, a plurality of sub-pixels disposed on the substrate, and a plurality of gate control lines.
  • Each sub-pixel includes a pixel circuit; the pixel circuit includes a drive transistor and at least one first switch transistor, and the first switch transistor is electrically connected to a control electrode of the drive transistor.
  • Each pixel circuit is electrically connected to at least two gate control lines.
  • the first switching transistor includes an active layer, the active layer includes an active layer body and at least one extension, and the active layer body includes at least one channel region and at least one conductive region.
  • the extension portion is electrically connected to the conductive region of the active layer body; the orthographic projection of the extension portion on the substrate at least partially overlaps the orthographic projection of a gate control line on the substrate, and two The overlapping part of the two forms a voltage stabilizer capacitor.
  • the active layer of the first switch transistor includes at least one first extension;
  • the body of the active layer of the first switch transistor includes two channel regions and three conductive regions, the conductive regions and The channel regions are alternately connected in sequence, and one of the conductive regions is located between the two channel regions, and the orthographic projection of a gate control line on the substrate is connected to the two channels of the first switching transistor.
  • the orthographic projections of the regions on the substrate overlap.
  • the first extension of the first switching transistor is electrically connected to a conductive region between two channel regions of the first transistor, and the first extension of the first switching transistor is on the substrate
  • the orthographic projection of at least partially overlaps the orthographic projection of a gate control line on the substrate.
  • the three conductive regions of the first switching transistor are respectively a first conductive region, a second conductive region and a third conductive region, and the second conductive region is located at two conductive regions of the first switching transistor. between the channel regions.
  • One end of the extension portion is electrically connected to the second conductive region, and the other end extends away from the second conductive region; the first extension portion is located in the first conductive region and the third conductive region between, or on one side of the main body of the active layer of the first transistor.
  • the active layer of the first switch transistor further includes at least one second extension; one of the three conductive regions of the first switch transistor is electrically connected to the control electrode of the driving transistor connection; the second extension of the first switch transistor is electrically connected to one of the three conductive regions that is electrically connected to the control electrode of the drive transistor, and the second extension of the first switch transistor is in the
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the gate control line on the substrate.
  • the three conductive regions of the first switching transistor are respectively a first conductive region, a second conductive region and a third conductive region, and the second conductive region is located at two conductive regions of the first switching transistor. between each channel region; the first conductive region is electrically connected to the control electrode of the driving transistor. One end of the second extension portion is electrically connected to the first conductive region, and the other end extends away from the first conductive region; the second extension portion is located between the first conductive region and the third conductive region between the conductive regions, or on one side of the main body of the active layer of the first switching transistor.
  • the active layer of the first switching transistor includes at least one third extension;
  • the active layer body of the first switching transistor includes a channel region, a fourth conductive region and a fifth conductive region, The fourth conductive region and the fifth conductive region are respectively located on both sides of the channel region; wherein, the fourth conductive region is electrically connected to the control electrode of the driving transistor; the third extension is connected to The fourth conductive region is connected, and the orthographic projection of the third extension on the substrate at least partially overlaps the orthographic projection of the gate control line on the substrate.
  • the active layer of the first switching transistor further includes a fourth extension part; the fourth extension part is electrically connected to the fifth conductive region, and the fourth extension part is on the substrate
  • the orthographic projection on the bottom at least partially overlaps the orthographic projection of the gate control lines on the substrate.
  • the display panel further includes: a plurality of initialization signal lines, and each pixel circuit is further electrically connected to at least one initialization signal line.
  • the gate control line electrically connected to the pixel circuit includes a first reset signal line;
  • the at least one first switch transistor includes a first transistor;
  • the control electrode of the first transistor is connected to the first reset signal line Electrically connected, the first electrode of the first transistor is electrically connected to an initialization signal line, and the second electrode of the first transistor is electrically connected to the control electrode of the driving transistor.
  • the orthographic projection of the extension of the first transistor on the substrate at least partially overlaps the orthographic projection of the first reset signal line on the substrate.
  • the gate control line electrically connected to the pixel circuit further includes a gate scan line; the at least one first switch transistor further includes a second transistor; the control electrode of the second transistor is connected to the control electrode of the second transistor.
  • the gate scan line is electrically connected, the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to the control electrode of the driving transistor.
  • the orthographic projection of the extension of the second transistor on the substrate at least partially overlaps with the orthographic projection of the gate scan line on the substrate; or, the extension of the second transistor is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the first reset signal line on the substrate.
  • the display panel further includes: a plurality of first voltage signal lines, a plurality of light-emitting control lines, and a plurality of data lines.
  • the gate control line electrically connected to the pixel circuit further includes a second reset signal line.
  • Each pixel circuit is also electrically connected to a first voltage signal line.
  • the pixel circuit further includes a storage capacitor; the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely; the first electrode plate and the plurality of gate control lines are arranged in the same layer, and the first electrode plate and the plurality of gate control lines are arranged in the same layer.
  • the electrode plate is electrically connected to the control electrode of the driving transistor; the second electrode plate is arranged on the side of the first electrode plate away from the substrate; the second electrode plate is connected to the first voltage signal line electrical connection.
  • Each pixel circuit is electrically connected with a light-emitting control line, a data line, and the second reset signal line; the pixel circuit further includes at least one second switch transistor, each of which is connected to the driving transistor. The first pole or the second pole is electrically connected.
  • a pixel circuit comprising: a driving sub-circuit, a storage sub-circuit, a first reset sub-circuit, a compensation sub-circuit, a first voltage-stabilizing sub-circuit and a second voltage-stabilizing sub-circuit.
  • the drive subcircuit is configured to generate a drive current.
  • the storage sub-circuit is electrically connected to the driving sub-circuit and the first voltage signal line; the storage sub-circuit is configured to store the received signal and maintain the connection between the storage sub-circuit and the connection end of the driving sub-circuit potential.
  • the first reset subcircuit is electrically connected to a first reset signal line, the drive subcircuit and an initialization signal line; the reset subcircuit is configured to respond to a first reset signal received at the first reset signal line
  • the gate signal transmits the initialization signal received at the initialization signal line to the driving sub-circuit.
  • the compensation sub-circuit is electrically connected to the driving sub-circuit and the gate scan line; the compensation sub-circuit is configured to, in response to a gate scan signal received at the gate scan line, perform an operation on the driver sub-circuit
  • the circuit performs threshold compensation.
  • the first voltage regulator sub-circuit is electrically connected to the first reset sub-circuit, the first reset signal line or the gate scan line; the first voltage regulator sub-circuit is configured to suppress the first voltage regulator Reset subcircuit leakage.
  • the second voltage regulator sub-circuit is electrically connected to the compensation sub-circuit, the first reset signal line or the gate scan line; the first voltage regulator sub-circuit is configured to suppress leakage of the compensation sub-circuit .
  • the driving sub-circuit includes a driving transistor; and the first voltage regulator sub-circuit includes at least one first voltage regulator capacitor.
  • the first reset subcircuit includes a first transistor, and the first transistor is a double-gate transistor.
  • the first transistor includes a first sub-transistor and a second sub-transistor; a control electrode of the first sub-transistor is electrically connected to the first reset signal line, and a first electrode of the first sub-transistor is connected to the initialization
  • the signal line is electrically connected, the second electrode of the first sub-transistor is electrically connected to the first electrode of the second sub-transistor; the control electrode of the second sub-transistor is electrically connected to the first reset signal line, so
  • the second electrode of the second sub-transistor is electrically connected to the control electrode of the driving transistor; the first end of the first voltage stabilization capacitor is electrically connected to the second electrode of the first sub-transistor, and the first voltage stabilization capacitor is electrically connected to the second electrode of the first
  • the first voltage stabilization sub-circuit further includes at least one second voltage stabilization capacitor; the first end of the second voltage stabilization capacitor is electrically connected to the second electrode of the second sub-transistor, so The second end of the second voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line.
  • the driving sub-circuit includes a driving transistor; and the first voltage stabilization sub-circuit includes at least one third voltage stabilization capacitor and at least one fourth voltage stabilization capacitor.
  • the first reset sub-circuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first reset signal line, and a first electrode of the first transistor is electrically connected to the initialization signal line, so The second electrode of the first transistor is electrically connected to the control electrode of the driving transistor.
  • the first end of the third voltage stabilization capacitor is electrically connected to the second electrode of the first transistor, and the second end of the third voltage stabilization capacitor is connected to the first reset signal line or the gate scan line electrical connection.
  • the first end of the fourth voltage stabilization capacitor is electrically connected to the first electrode of the first transistor, and the second end of the fourth voltage stabilization capacitor is connected to the first reset signal line or the gate scan line electrical connection.
  • the driving sub-circuit includes a driving transistor; and the second voltage regulator sub-circuit includes at least one fifth voltage regulator capacitor.
  • the compensation sub-circuit includes a second transistor, and the second transistor is a double-gate transistor; the second transistor includes a third sub-transistor and a fourth sub-transistor; the control electrode of the third sub-transistor and the gate electrode
  • the scan line is electrically connected, the first electrode of the third sub-transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third sub-transistor is electrically connected to the first electrode of the fourth sub-transistor ;
  • the control electrode of the fourth sub-transistor is electrically connected to the gate scan line, and the second electrode of the fourth sub-transistor is electrically connected to the control electrode of the driving transistor.
  • the first end of the fifth voltage stabilization capacitor is electrically connected to the second electrode of the third sub-transistor, and the second end of the fifth voltage stabilization capacitor is electrically connected to the first reset signal
  • the second voltage regulator sub-circuit further includes at least one sixth voltage regulator capacitor.
  • the first end of the sixth voltage stabilization capacitor is electrically connected to the second electrode of the fourth sub-transistor, and the second end of the sixth voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line electrical connection.
  • the driving sub-circuit includes a driving transistor; the second voltage stabilization sub-circuit includes at least one seventh voltage stabilization capacitor and at least one eighth voltage stabilization capacitor.
  • the compensation sub-circuit includes a second transistor, the control electrode of the second transistor is electrically connected to the gate scan line, the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the The second electrode of the second transistor is electrically connected to the control electrode of the driving transistor.
  • the first end of the seventh voltage stabilization capacitor is electrically connected to the second electrode of the second transistor, and the second end of the seventh voltage stabilization capacitor is connected to the first reset signal line or the gate scan line electrical connection.
  • the first end of the eighth voltage stabilization capacitor is electrically connected to the first electrode of the second transistor, and the second end of the eighth voltage stabilization capacitor is connected to the first reset signal line or the gate scan line electrical connection.
  • the pixel circuit further includes: a data writing subcircuit, a second reset subcircuit, a first light emission control subcircuit, and a second light emission control subcircuit.
  • the data writing subcircuit is electrically connected to the gate scan line, the data line and the driving subcircuit; the data writing subcircuit is configured to respond to a gate received at the gate scan line A polar scan signal is used to transmit the data signal received at the data line to the driving sub-circuit.
  • the driver subcircuit and the compensation subcircuit are also configured to transmit the data signal to the storage subcircuit.
  • the second reset subcircuit is electrically connected to the second reset signal line, the initialization signal line and the light emitting device; the second reset subcircuit is configured to respond to the gate received at the gate scan line A scan signal to transmit the initialization signal received at the initialization signal line to the light emitting device.
  • the first lighting control sub-circuit is electrically connected to the lighting control line, the first voltage signal line and the driving sub-circuit, the first lighting control sub-circuit is configured to respond at the lighting control line
  • the received light-emitting control signal transmits the first voltage signal received at the first voltage signal line to the driving sub-circuit.
  • the second light-emitting control sub-circuit is electrically connected to the light-emitting control line, the driving sub-circuit and the light-emitting device; the second light-emitting control sub-circuit is configured to transmit the driving current generated by the driving sub-circuit to the light emitting device to control the light emitting device to emit light.
  • a display device including the display panel according to any one of the foregoing embodiments.
  • FIG. 1 is a block diagram of a display device according to some embodiments.
  • FIG. 2 is a structural diagram of a display panel according to some embodiments.
  • 3A is a structural diagram of a pixel circuit according to some embodiments.
  • 3B is a structural diagram of another pixel circuit according to some embodiments.
  • FIG. 4 is a timing diagram of a pixel circuit according to some embodiments.
  • FIG. 5 is a film layer structure diagram of a display panel according to some embodiments.
  • FIG. 6 is a structural diagram of a semiconductor layer according to some embodiments.
  • FIG. 7 is a structural diagram of another semiconductor layer according to some embodiments.
  • FIG. 8 is a structural diagram of a first gate layer according to some embodiments.
  • FIG. 9 is a structural diagram of a second gate layer according to some embodiments.
  • FIG. 10 is a structural diagram of a source-drain metal layer according to some embodiments.
  • FIG. 11 is an overall layout diagram of a pixel circuit according to some embodiments.
  • FIG. 12 is an overall layout diagram of another pixel circuit according to some embodiments.
  • FIG. 13 is a structural diagram of yet another semiconductor layer according to some embodiments.
  • FIG. 14 is a structural diagram of a semiconductor layer and a first gate layer according to some embodiments.
  • 15 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments.
  • 16 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 17 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • FIG. 18 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 19 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 20 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 21 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 22 is an overall layout diagram of yet another pixel circuit according to some embodiments.
  • FIG. 23 is a structural diagram of yet another semiconductor layer according to some embodiments.
  • 24 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 25 is a structural diagram of yet another semiconductor layer and a first gate layer according to some embodiments.
  • 26 is an overall layout diagram of yet another pixel circuit according to some embodiments.
  • FIG. 27 is a structural diagram of yet another pixel circuit according to some embodiments.
  • FIG. 28A is a schematic diagram according to the ON state of the second transistor in the pixel circuit of FIG. 27;
  • FIG. 28B is a schematic diagram of the off state of the second transistor in the pixel circuit according to FIG. 27;
  • 29 is a structural diagram of yet another pixel circuit according to some embodiments.
  • FIG. 30A is a schematic diagram according to the on-state of the second transistor in the pixel circuit of FIG. 29;
  • FIG. 30B is a schematic diagram of the off-state of the second transistor in the pixel circuit according to FIG. 29;
  • FIG. 31 is a structural diagram of yet another pixel circuit according to some embodiments.
  • 32 is a structural diagram of yet another pixel circuit according to some embodiments.
  • FIG. 33A is a schematic diagram according to the on-state of the second transistor in the pixel circuit of FIG. 32;
  • FIG. 33B is a schematic diagram of the second transistor in the off state of the pixel circuit according to FIG. 32 .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • Some embodiments of the present disclosure provide a display device, which can be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable display device, etc., for example, can be watch.
  • the display device 1000 may be a mobile phone.
  • the embodiments of the present disclosure do not specifically limit the specific form of the above-mentioned display device.
  • the display device may also be an electroluminescent display device or a photoluminescent display device.
  • the electroluminescence display device may be an organic electroluminescence display device (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescence display device (Quantum Dot Light Emitting). Diodes, referred to as QLED).
  • the display device is a photoluminescence display device
  • the photoluminescence display device may be a quantum dot photoluminescence display device.
  • the display device 1000 includes a display panel 01. As shown in FIG. 2, the display panel 01 includes a display area AA (Active Area, AA area for short; also called an active display area) and a peripheral area BB located on at least one side of the display area AA. .
  • AA Active Area, AA area for short; also called an active display area
  • BB peripheral area
  • the display panel includes a substrate 201, a plurality of sub pixels 10 disposed on the substrate 201, a plurality of gate control lines GL, a plurality of data lines DL, a plurality of initialization signal lines VINT and A plurality of first voltage signal lines VDD.
  • the plurality of gate control lines GL and the plurality of initialization signal lines Vint extend in the horizontal direction X
  • the plurality of data lines DL and the plurality of first voltage signal lines VDD extend in the vertical direction Y.
  • a plurality of sub-pixels 10, a plurality of gate control lines GL, a plurality of data lines DL, a plurality of initialization signal lines Vint and a plurality of first voltage signal lines VDD are all disposed in the display area AA.
  • the above-mentioned plurality of sub-pixels 10 in the present disclosure are described by taking the arrangement of the plurality of sub-pixels 10 as an example, and exemplarily, the plurality of sub-pixels 10 are arranged in N rows and M columns.
  • the sub-pixels 10 arranged in a row along the horizontal direction X are called a row of sub-pixels
  • the sub-pixels 10 arranged in a row along the vertical direction Y are called a column of sub-pixels.
  • the pixel circuit 100 for the device to emit light is provided on the substrate 201 of the display panel 01 .
  • a row of sub-pixels may be coupled to one or two gate control lines GL.
  • each pixel circuit 100 is electrically connected to at least two gate control lines GL.
  • a row of sub-pixels may also be coupled to one or two light-emitting timing lines.
  • the signal lines EL are coupled to each other, and a column of sub-pixels can be coupled to a data signal line DL.
  • the above-mentioned display panel 01 can be: an organic light-emitting diode (Organic Light Emitting Diode, OLED for short) display panel, a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, abbreviated as QLED) display panel, etc., which are not specifically limited in this disclosure.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the pixel circuit 100 generally includes elements such as switching transistors, driving transistors, and storage capacitors.
  • the opposite ends of the storage capacitor are respectively the reference potential terminal and the signal holding terminal.
  • the reference potential terminal of the storage capacitor is electrically connected to the first voltage signal line VDD, and the signal holding terminal of the storage capacitor is connected to the control of the driving transistor. pole (gate) coupling.
  • the storage capacitor is used to hold the voltage signal, so that the potential of its signal holding terminal can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a voltage.
  • the driving current drives the light-emitting diode to emit light.
  • the switching transistor electrically connected to the control electrode of the driving transistor is in the off state, and no current will flow through, so that the potential of the signal holding terminal can be kept stable. However, in the actual circuit, the switching transistor is in the off state.
  • some embodiments of the present disclosure provide a pixel circuit 100 , the pixel circuit 100 includes a storage sub-circuit 101 , a driving sub-circuit 102 , a first reset sub-circuit 103 , a compensation sub-circuit 100 , a Subcircuit 104 , data writing subcircuit 105 , first lighting control subcircuit 106 , second lighting control subcircuit 107 and second reset subcircuit 108 .
  • the drive subcircuit 102 is configured to generate drive current.
  • the storage sub-circuit 101 is electrically connected to the driving sub-circuit 102 and the first voltage signal line VDD;
  • the first reset sub-circuit 103 is electrically connected to the driving sub-circuit 102, the first reset signal line Reset1 and the initialization signal line Vint; the reset sub-circuit is configured to respond to the first gate signal received at the first reset signal line Reset1 , the initialization signal received at the initialization signal line Vint is transmitted to the driving sub-circuit 102 .
  • the compensation sub-circuit 104 is electrically connected with the driving sub-circuit 102 and the gate scanning line Gate; the compensation sub-circuit 104 is configured to perform threshold compensation on the driving sub-circuit 102 in response to the gate scanning signal received at the gate scanning line Gate .
  • the node where the driving sub-circuit 102 is electrically connected with the storage sub-circuit 101 , the first reset sub-circuit 103 and the compensation sub-circuit 104 is referred to as the first node N1 hereinafter.
  • the first reset sub-circuit 103 can transmit an initialization signal to the first node N1 to reset the first node N1.
  • the storage sub-circuit 101 includes a storage capacitor Cst, a first terminal of the storage capacitor Cst is electrically connected to the first voltage signal line VDD, and a second terminal of the storage capacitor Cst is electrically connected to the first node N1.
  • the driving sub-circuit 102 includes a driving transistor Td, and the control electrode of the driving transistor Td is electrically connected to the first node N1.
  • the first reset sub-circuit 103 includes a first transistor T1, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the initialization signal line Vint, and the control electrode of the first transistor T1 is electrically connected to the initialization signal line Vint.
  • the second pole is electrically connected to the first node N1.
  • the first transistor T1 is a dual-gate transistor, and the first transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12 .
  • the control electrode of the first sub-transistor T11 is electrically connected to the first reset signal line Reset1
  • the first electrode of the first sub-transistor T11 is electrically connected to the initialization signal line Vint
  • the second electrode of the first sub-transistor T11 is electrically connected to the second sub-transistor T12
  • the first electrode of the second sub-transistor T12 is electrically connected to the first reset signal line Reset1
  • the second electrode of the second sub-transistor T12 is electrically connected to the control electrode of the driving transistor Td.
  • control electrode of the first transistor T1 is the control electrode of the first sub-transistor T11 and the second sub-transistor T12
  • first electrode of the first transistor T1 is the first electrode of the first sub-transistor T11
  • the first electrode of the first transistor T1 is the first electrode of the first sub-transistor T11
  • the diode is the second pole of the second sub-transistor T12.
  • the compensation sub-circuit 104 includes a second transistor T2, the control electrode of the second transistor T2 is electrically connected to the gate scan line Gate, the first electrode of the second transistor T2 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the second transistor T2 is electrically connected.
  • the second pole is electrically connected to the first node N1.
  • the second transistor T2 is a dual-gate transistor, and the second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22 .
  • the control electrode of the third sub-transistor T21 is electrically connected to the gate scanning line Gate, the first electrode of the third sub-transistor T21 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the third sub-transistor T21 is electrically connected to the fourth sub-transistor T21
  • the first electrode of the transistor T22 is electrically connected; the control electrode of the fourth sub-transistor T22 is electrically connected to the gate scanning line Gate, and the second electrode of the fourth sub-transistor T22 is electrically connected to the control electrode of the driving transistor Td.
  • control electrode of the second transistor T2 is the control electrode of the second sub-transistor T12 and the fourth sub-transistor T22
  • first electrode of the second transistor T2 is the first electrode of the third sub-transistor T21
  • first electrode of the second transistor T2 is the first electrode of the third sub-transistor T21.
  • the diode is the second pole of the fourth sub-transistor T22.
  • the node where the first electrode of the second transistor T2 and the second electrode of the driving transistor Td are electrically connected is referred to as the second node N2.
  • the data write subcircuit 105 is electrically connected to the gate scan line Gate, the drive subcircuit 102 and the data line DL, and the data write subcircuit 105 is configured to respond to the gate scan received at the gate scan line Gate signal to transmit the data signal received at the data line DL to the driving sub-circuit 102 .
  • the first lighting control sub-circuit 106 is electrically connected to the lighting control line EL, the first voltage signal line VDD, and the driving sub-circuit 102, the first lighting control sub-circuit 106 being configured to respond to a signal received at the lighting control line EL
  • the light-emitting control signal transmits the first voltage signal received at the first voltage signal line VDD to the driving sub-circuit 102 .
  • the node where the driving sub-circuit 102 is electrically connected with the data writing sub-circuit 105 and the first light-emitting control sub-circuit 106 is referred to as the third node N3.
  • the data writing sub-circuit 105 includes a third transistor T3, the control electrode of the third transistor T3 is electrically connected to the gate scan line Gate, the first electrode of the third transistor T3 is electrically connected to the data line DL, and the third transistor T3 is electrically connected to the data line DL.
  • the second pole of T3 is electrically connected to the third node N3.
  • the first light-emitting control sub-circuit 106 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is electrically connected to the light-emitting control line EL, the first electrode of the fourth transistor T4 is electrically connected to the first voltage signal line VDD, and the fourth transistor T4 The second pole of is electrically connected to the third node N3.
  • the second reset sub-circuit 108 is electrically connected to the second reset signal line Reset2, the initialization signal line Vint, and the light emitting device 109, and the second reset sub-circuit 108 is configured to respond to a signal received at the second reset signal line Reset2
  • the second reset signal transmits the initialization signal received at the initialization signal line Vint to the light emitting device 109 to reset the light emitting device 109 .
  • the second lighting control subcircuit 107 is electrically connected to the lighting control line EL, the driving subcircuit 102 and the lighting device 109, and the second lighting control subcircuit 107 is configured to, in response to the lighting control signal received at the lighting control line EL, receive The driving signal output by the sub-circuit 102 is driven, and the driving signal is transmitted to the light-emitting device 109 to control the light-emitting device 109 to emit light.
  • the second reset subcircuit 108 and the second lighting control subcircuit 107 are both coupled to the anode of the light emitting device 109, and the cathode of the light emitting device 109 is electrically connected to the second voltage signal line VSS.
  • the light emitting device 109 is a light emitting diode.
  • the node where the light-emitting device 109 is electrically connected to the second reset sub-circuit 108 and the second light-emitting control sub-circuit 107 is hereinafter referred to as the fourth node N4.
  • the second reset sub-circuit 108 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is electrically connected to the second reset signal line Reset2, the first electrode of the fifth transistor T5 is electrically connected to the initialization signal line Vint, and the first electrode of the fifth transistor T5 is electrically connected to the initialization signal line Vint.
  • the second pole of the five transistors T5 is electrically connected to the fourth node N4.
  • the second light-emitting control sub-circuit 107 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is electrically connected to the light-emitting control line EL, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the first electrode of the sixth transistor T6 is electrically connected to the third node N3.
  • the diode is electrically connected to the fourth node N4.
  • the gate scan line Gate and the second reset signal line Reset2 to which the pixel circuit 100 in one sub-pixel is electrically connected are the same gate control line GL, that is, the gate scan signal and the second reset signal are For the same signal, when the sub-pixels are arranged in an array with N rows and M columns, the first reset signal line Reset1 electrically connected to the pixel circuit 100 of the sub-pixels in one row is the gate scan line electrically connected to the sub-pixels in the previous row.
  • Line Gate
  • the on/off types of the transistors included in the sub-circuits are the same.
  • the first transistor T1 to the sixth transistor T6 and the driving transistor Td are all P-type transistors or N-type transistors
  • the above transistors are all low temperature polysilicon thin film transistors (Low Temperature Poly-silicon Thin Film Transistor). In the present disclosure, the above transistors are all P-type transistors as an example for description.
  • one frame period includes a reset phase P1 , an input and compensation phase P2 and a light-emitting phase P3 .
  • the first reset subcircuit 103 transmits the initialization signal received at the initialization signal line Vint to the first node N1 to reset the first node N1 in response to the first reset signal received at the first reset signal line Reset1.
  • Both the energy storage sub-circuit and the driving sub-circuit 102 are electrically connected to the first node N1, and in the reset stage, the energy storage sub-circuit and the driving sub-circuit 102 are reset.
  • the reset phase P1 when each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor, the reset phase P1 includes:
  • each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor
  • the energy storage sub-circuit includes a storage capacitor Cst
  • the driving sub-circuit 102 includes a driving transistor Td
  • the first reset sub-circuit 103 includes a first transistor T1
  • the compensation sub-circuit 104 includes a second transistor T2
  • the data sub-circuit includes a second transistor T2
  • the data writing sub-circuit 105 includes a third transistor T3
  • the first light-emitting control sub-circuit 106 includes a fourth crystal
  • the second light-emitting control sub-circuit 107 includes the case of the sixth transistor T6.
  • 0 represents that the level of a certain signal is a low level
  • "1" represents that the level of a certain signal is a high level.
  • the first reset signal is 0, the gate scan signal (the second reset signal) is 1, and the light emission control signal is 1.
  • the first transistor T1 is turned on under the control of the first reset signal, and transmits the initialization signal to the first node N1.
  • the second transistor T2 to the sixth transistor T6 and the driving transistor Td are all turned off.
  • the first transistor T1 when the first transistor T1 is a dual-gate transistor, and the first transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12, the first transistor T1 is turned on under the control of the first reset signal. That is, the first sub-transistor T11 and the second sub-transistor T12 are both turned on under the control of the first reset signal to transmit the initialization signal.
  • the second reset subcircuit 108 transmits the initialization signal received at the initialization signal line Vint to the fourth node N4 in response to the second reset signal received at the second reset signal line Reset2 to reset the light emitting device 109 .
  • the data writing subcircuit 105 transmits the data signal received at the data line DL to the third node N3 in response to the gate scan signal received at the gate scan line Gate.
  • the driving sub-circuit 102 transmits the data signal at the third node N3 to the second node N2 under the action of the voltages of the first node N1 and the third node N3.
  • the compensation sub-circuit 104 transmits the data signal received at the second node N2 to the first node N1 in response to the gate scanning signal received at the gate scanning line Gate, and performs threshold compensation on the driving sub-circuit 102 .
  • the tank sub-circuit receives and stores the voltage of the first node N1.
  • the input and compensation stage P2 includes:
  • the first reset signal is 1
  • the gate scan signal (the second reset signal)
  • the light emission control signal is 1.
  • the fifth transistor T5 is turned on under the control of the second reset signal, and transmits the initialization signal to the fourth node N4 to reset the anode of the light emitting device 109 .
  • the third transistor T3 is turned on under the control of the gate scan signal, and transmits the data signal to the third node N3.
  • the potential of the control electrode (gate) of the driving transistor Td is the potential of the first node N1, that is, the potential of the initialization signal, and the potential of the first electrode (source) of the driving transistor Td is the potential of the third node N3, that is, the data signal.
  • the voltage difference between the gate and the source of the driving transistor Td is less than the threshold voltage V th , the driving transistor Td is turned on, and the data signal is transmitted from the third node N3 to the second node N2 .
  • the second transistor T2 is turned on under the control of the gate scan line Gate, and transmits the data signal at the second node N2 to the first node N1, thereby writing the data signal into the storage capacitor Cst.
  • the storage capacitor Cst maintains the potential of the first node N1.
  • the second transistor T2 is a dual-gate transistor, and the second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22
  • the conduction of the second transistor T2 under the control of the gate scan line Gate means that the third sub-transistor T2 is turned on under the control of the gate scan line Gate.
  • Both the sub-transistor T21 and the fourth sub-transistor T22 are turned on under the control of the gate scan line Gate.
  • the potential of the first node N1 is gradually increased by the potential V int of the initialization signal.
  • the driving transistor Td is turned off, and the input and compensation phase ends, thereby changing the data signal
  • the voltage and threshold voltage are written into the storage capacitor Cst.
  • the first light emission control sub-circuit 106 transmits the first voltage signal received at the first voltage signal line VDD to the third node N3 in response to the light emission control signal received at the light emission control line EL.
  • the driving sub-circuit 102 generates a driving current under the control of the voltages of the first node N1 and the third node N3, and outputs the driving current to the second node N2.
  • the second light-emitting control sub-circuit 107 transmits the driving signal received at the second node N2 to the fourth node N4, that is, the anode of the light-emitting device 109, in response to the light-emitting control signal received at the light-emitting signal line, so that the light-emitting device 109 is at Lights up under the control of the driving signal.
  • the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the light-emitting stage P3 when each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor, the light-emitting stage P3 includes:
  • the first reset signal is 1
  • the gate scan signal (second reset signal) is 1
  • the light-emitting control signal is 0.
  • the fourth transistor T4 transmits the first voltage signal to the third node N3 under the control of the lighting control signal.
  • the potential of the third node N3 is the voltage of the first voltage signal
  • the potential of the first node N1 is V data +V th
  • the driving transistor Td generates a driving current under the control of the voltages of the first node N1 and the third node N3, and
  • the driving transistor Td works in the saturation region. According to the saturation current formula, the driving current (current input to the light-emitting device 109 ) generated by the driving transistor Td is:
  • W/L is the channel width to length ratio of the driving transistor Td; ⁇ is the carrier mobility; C ox is the channel capacitance per unit area of the driving transistor Td; V gs is the gate-source voltage difference of the driving transistor Td; V th is the threshold voltage of the driving transistor Td.
  • the magnitude of the current I oled input to the light-emitting device 109 is related to the voltage V data of the written data signal and the first voltage signal, and has nothing to do with the threshold voltage V th of the driving transistor Td. Differences in the threshold voltages of the driving transistors Td of the pixel circuit 100 affect the magnitude of the driving current, which in turn affects the display effect.
  • the driving signal generated by the driving transistor Td in the driving sub-circuit 102 is the driving current. That is to say, the driving signal formed by it is related to the potential of the control electrode (gate) of the difference between the gate-source voltage difference of the driving transistor Td and the threshold voltage (V gs - V th ), and the potential of the control electrode of the driving transistor Td (ie The stability of the potential of the first node N1 ) can affect the stability and effective value of the formed driving signal, thereby affecting the stability and continuity of light emission of the light emitting device 109 .
  • the first transistor T1, the second transistor T2 and the third transistor T3 are all in the off state, and no current will flow through, so that the potential of the first node N1 can be maintained.
  • the switching transistor will have leakage current in the off state, and due to process abnormality, the leakage current of the switching transistor will be large, so that the potentials of the first node N1 and the third node N3 change during the light-emitting stage and cannot be kept stable.
  • the potential changes of the first node N1 and the third node N3 in different pixel circuits 100 are different, which leads to the driving transistor Td
  • the gate-source voltage difference changes significantly, and the magnitude of the current formed by the driving transistor Td fluctuates, which cannot drive the light-emitting device 109 to emit light stably, thereby making the pixels brighter or darker, and poor bright and dark spots.
  • the transistor electrically connected to the control electrode (first node N1 ) of the driving transistor Td is referred to as the first switching transistor, and is referred to as the first electrode or the first switching transistor connected to the driving transistor Td.
  • the transistor whose diodes are electrically connected is the second switching transistor.
  • the inventors of the present disclosure have found through research that, in addition to the reasons described above, the leakage current of the switching transistor in the off state is also affected by the voltage difference between the source and drain of the switching transistor.
  • the voltage of the drain and the drain of the switching transistor are basically equal, there is basically no leakage current flowing, and the potential of the first pole of the switching transistor is greater than the potential of the second pole of the switching transistor. In this case, the leakage current basically cannot flow from the second pole of the switching transistor to the first pole, and vice versa.
  • the inventors of the present disclosure redesign the patterns of the active layers of the first switching transistors (ie, the first transistor T1 and the second transistor T2 ) to make the active layers of the first switching transistors Part of the structure and the gate control line GL can overlap to form a capacitor, so as to add a voltage regulator sub-circuit in the pixel circuit 100, the voltage regulator sub-circuit can keep the voltage of the source and the drain of the first switching transistor stable , the source-drain voltage difference is reduced, so as to reduce the leakage of the first light-emitting transistor in the light-emitting stage and keep the potential of the first node N1 stable.
  • the display panel 01 has the following structure.
  • the display panel 01 includes a substrate 201, a semiconductor layer 202, a first gate insulating layer 203, a first gate layer 204, The second gate insulating layer 205, the second gate layer 206, the interlayer insulating layer 207, and the source-drain metal layer.
  • FIGS. 6 to 9 respectively illustrate the semiconductor layer 202 , the first gate layer 204 , the second gate layer 206 and the source-drain metal layer corresponding to the pixel circuit 100 shown in FIGS. 3A and 3B .
  • 11 and 12 are overall layout diagrams of each film layer in the pixel circuit 100 (wherein the first gate insulating layer 203 , the first gate insulating layer 203 and the interlayer insulating layer 207 are transparent).
  • 6 is a structural diagram corresponding to the semiconductor layer 202 of the pixel circuit 100 shown in FIG. 3A
  • FIG. 7 is a structural diagram corresponding to the semiconductor layer 202 of the pixel circuit 100 shown in FIG. 3B .
  • the semiconductor layer 202 is disposed on the substrate 201, the semiconductor layer 202 has a predetermined pattern, and the semiconductor layer 202 includes the active layer of each transistor in each pixel circuit 100, referred to herein as the active layer body.
  • the semiconductor layer 202 includes the active layer body td of the driving transistor Td, the active layer body t1 of the first transistor T1, and the active layer body of the second transistor T2 t2, the active layer body t3 of the third transistor T3, the active layer body t4 of the fourth transistor T4, the active layer body t5 of the fifth transistor T5, and the active layer body t6 of the sixth transistor T6.
  • the active layer body of each transistor may include at least one channel region and at least one conductive region, wherein the conductive region is a source region or a drain region.
  • the active region of the transistor is the portion of the active layer body that overlaps with the corresponding gate control line GL.
  • the portion of the dotted line in FIGS. 6 and 7 is the active region of each transistor.
  • the active layers of the respective transistors are integrally provided.
  • the semiconductor layer 202 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the preparation of the semiconductor layer 202 is, for example, by depositing a semiconductor material on the surface of the substrate 201, and forming the semiconductor layer 202 through an etching process, so that the semiconductor layer 202 has a predetermined pattern.
  • the first gate insulating layer 203 is disposed on the side of the semiconductor layer 202 away from the substrate 201 , the first gate layer 204 is disposed on the side of the first gate insulating layer 203 away from the substrate 201 , and the first gate insulating layer 203 It is configured to isolate the semiconductor layer 202 and the first gate layer 204 from each other and to protect the semiconductor layer 202 .
  • the first gate layer 204 includes a plurality of gate control lines GL, a plurality of light emission control lines EL and a plurality of first plates Cst1 of the storage capacitors Cst, specifically, the first The gate layer 204 includes a first reset signal line Reset1, a second reset signal line Reset2, a gate scan line Gate, and a light emission control line EL.
  • the portion of the signal line in the first gate layer 204 and the active layer of the transistor in the semiconductor layer 202 overlaps as the gate of the transistor, and the portion of the active layer of the transistor opposite to the gate is used as the gate of the transistor. for the channel region.
  • the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1 at two places, and the gate of the first transistor T1 is the first reset signal line Reset1 and the first transistor T1
  • the active layers of the first transistor T1 have overlapping parts, and the active layer of the first transistor T1 includes two channel regions. It is understood that the first transistor T1 is a double-gate transistor.
  • FIG. 11 the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1 at two places, and the gate of the first transistor T1 is the first reset signal line Reset1 and the first transistor T1
  • the active layers of the first transistor T1 have overlapping parts, and the active layer of the first transistor T1 includes two channel regions. It is understood that the first transistor T1 is a double-gate transistor.
  • FIG. 11 the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1 at two places, and the gate of the first transistor T1 is the first reset signal line Re
  • the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1, and the gate of the first transistor T1 is the gate of the first reset signal line Reset1 and the first transistor T1
  • the active layers have overlapping portions, and the active layer of the first transistor T1 includes a channel region. It can be understood that the first transistor T1 is a single-gate transistor.
  • the main body of the active layer of the second transistor T2 overlaps with the gate scanning line Gate at two places, and the gate of the second transistor T2 is the gate scanning line Gate that overlaps the gate scanning line Gate and the gate scanning line Gate of the second transistor T2.
  • the active layer has overlapping parts, and the active layer of the second transistor T2 includes two channel regions. It can be understood that the second transistor T2 is a double-gate transistor.
  • FIG. 11 the main body of the active layer of the second transistor T2 overlaps with the gate scanning line Gate at two places, and the gate of the second transistor T2 is the gate scanning line Gate that overlaps the gate scanning line Gate and the gate scanning line Gate of the second transistor T2.
  • the active layer has overlapping parts, and the active layer of the second transistor T2 includes two channel regions. It can be understood that the second transistor T2 is a double-gate transistor.
  • FIG. 11 the main body of the active layer of the second transistor T2 overlaps with the gate scanning line Gate at two places, and the gate of the second transistor T2 is the gate scanning
  • the main body of the active layer of the second transistor T2 overlaps with the gate scan line Gate, and the gate of the second transistor T2 is the gate scan line Gate and the active gate of the second transistor T2
  • the layers have overlapping portions, and the active layer of the second transistor T2 includes a channel region. It can be understood that the second transistor T2 is a single-gate transistor.
  • each dotted rectangle in FIG. 6 and FIG. 7 shows each part where the active layer of each transistor in the pixel circuit 100 overlaps with the first gate layer 204 .
  • the second gate insulating layer 205 is disposed on the side of the first gate layer 204 away from the substrate 201 , the second gate layer 206 is disposed on the side of the second gate insulating layer 205 away from the substrate 201 , the second gate The insulating layer 205 is configured to isolate the first gate layer 204 and the second gate layer 206 from each other and to protect the first gate layer 204 .
  • the second gate layer 206 includes a plurality of initialization signal lines Vint and a plurality of second plates of the storage capacitors Cst.
  • Each initialization signal line Vint is electrically connected to the conductive regions of the first transistor T1 and the seventh transistor through a via hole, and the orthographic projection of the first plate of the storage capacitor Cst on the substrate 201 and the second plate of the storage capacitor Cst on the substrate 201 The orthographic projection of has an overlapping portion that forms the storage capacitor Cst.
  • the interlayer insulating layer 207 is disposed on the side of the second gate layer 206 away from the substrate 201, the source-drain electrode layer 208 is disposed on the side of the interlayer insulating layer 207 away from the substrate 201, and the interlayer insulating layer 207 is configured to The second gate layer 206 and the source-drain electrode layer 208 are isolated from each other and protect the second gate layer 206 .
  • the source-drain electrode layer 208 includes a plurality of first voltage signal lines VDD, a plurality of data lines DL, and at least one connection part 2081 , one first voltage signal line VDD is connected to a The second plate of the storage capacitor Cst is electrically connected, and a data line DL is electrically connected to the conductive area of the fourth transistor T4 through a via hole.
  • the connection portion 2081 is configured to electrically connect the transistors to the signal lines, or to electrically connect the transistors to the transistors.
  • the pattern of the active layer of the first switching transistor has a redesigned pattern.
  • the pattern of the first gate insulating layer 203, the first gate electrode layer 204, the second gate insulating layer 205, the second gate electrode layer 206, the interlayer insulating layer 207 and the source and drain layers included in the display panel 01 are introduced.
  • film layers such as metal layers, please refer to the above introduction.
  • the following first switching transistors refer to the first transistor T1 and the second transistor T2.
  • the first switching transistor includes an active layer including an active layer body and at least one extension, the active layer body including at least one channel region and at least one conductive layer Area.
  • the extension portion is electrically connected to the conductive region of the active layer body.
  • the first switching transistor is a first transistor T1
  • the first transistor T1 includes an active layer T1'
  • the active layer T1' includes an active layer body t1 and at least one extension p
  • the active layer body including at least one channel region and at least one conductive region
  • the first switching transistor is a second transistor T2
  • the second transistor T2 includes an active layer T2'
  • the active layer T2' includes an active layer body t2 and at least one extension
  • the active layer body includes at least one channel region and at least one conductive region, wherein the part of the dashed frame in the active layer body is the channel region, and the other regions are the conductive regions.
  • the orthographic projection of each extension on the substrate 201 at least partially overlaps with the orthographic projection of a gate control line GL on the substrate 201 , and the overlapping portion of the two forms a stabilizing capacitor.
  • the orthographic projection of the extension p of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201, and the overlapping portion of the two forms a stabilizing capacitor.
  • the active layer of the first switching transistor also includes at least one extension portion electrically connected to the conductive region of the active layer body, and the extension portion is connected to a gate control line GL
  • the positional relationship is such that the orthographic projection of the extension portion on the substrate 201 at least partially overlaps the orthographic projection of one gate control line GL on the substrate 201 .
  • the semiconductor layer 202 has a specially designed pattern, that is, the pattern of the active layer of the first switching transistor of each pixel circuit 100 is designed to include an active layer. a layer body and at least one extension part, the at least one extension part is electrically connected to the conductive region of the active layer body, and the orthographic projection of the extension part on the substrate 201 and the orthographic projection of a gate control line GL on the substrate 201 At least part of the overlap, and the overlapping part of the two forms a stabilizing capacitor, which is equivalent to connecting the first switching transistor and the stabilizing capacitor in parallel.
  • Setting the voltage stabilization capacitor can make the voltages of the drain and the drain of the first switching transistor substantially equal, thereby reducing the leakage current of the first switching transistor and increasing the potential of the control electrode of the driving transistor Td generated by the driving transistor Td (ie, The stability of the potential of the first node N1), thereby improving the stability of the driving signal, thereby improving the stability and continuity of light emission of the light emitting device 109, and improving the poor bright and dark spots of the display screen caused by the leakage of the first switching transistor.
  • the semiconductor layer 202 in the above-mentioned display panel 01 can be prepared by depositing a semiconductor material first and then forming a pattern through an etching process to obtain the semiconductor layer 202.
  • the other film layers are not changed, and there is no need to add an additional mask. Therefore, the above-mentioned display panel 01 Under the premise of not increasing the difficulty of the manufacturing process, the defective bright and dark spots of the display screen caused by the leakage of the first switching transistor are improved.
  • the pixel circuit 100 includes the storage sub-circuit mentioned above in addition to the above-mentioned pattern design. 101. Outside the driving sub-circuit 102, the first reset sub-circuit 103, the second reset sub-circuit 108, the compensation sub-circuit 104, the data writing sub-circuit 105, the first light-emitting control sub-circuit 106 and the second light-emitting control sub-circuit 107 , and also includes a first voltage regulator sub-circuit 110 and a second voltage regulator sub-circuit 111 .
  • the first voltage regulator sub-circuit 110 is electrically connected to the first reset sub-circuit 103 , the first reset signal line Reset1 or the gate scan line Gate; the first voltage regulator sub-circuit 110 is configured to suppress the leakage of the first reset sub-circuit 103 .
  • the second voltage regulator sub-circuit 111 is electrically connected to the compensation sub-circuit 104 , the first reset signal line Reset1 or the gate scan line Gate; the first voltage regulator sub-circuit 110 is configured to suppress the leakage of the compensation sub-circuit 104 .
  • the first voltage regulator sub-circuit 110 and the second voltage regulator sub-circuit 111 by setting the first voltage regulator sub-circuit 110 and the second voltage regulator sub-circuit 111, it is possible to suppress the leakage of the first reset sub-circuit 103 and the compensation sub-circuit 104 during the light-emitting stage, thereby increasing the potential of the first node N1.
  • This improves the stability of the driving signal generated by the driving sub-circuit 102, thereby improving the stability and continuity of the light emission of the light-emitting device 109, and improving the display caused by the leakage of the first reset sub-circuit 103 and the compensation sub-circuit 104.
  • the light and dark points of the screen are poor.
  • the structure of the active layer of the first switching transistor will be introduced respectively in the case that the first switching transistor is a double-gate transistor or a single-gate transistor.
  • the active layer body (t1 or t2) of the first switching transistor (T1 or T2) includes two channel regions and three conductive regions, and the conductive regions and the channel regions The channel regions are alternately electrically connected in sequence, and one of the conductive regions is located between the two channel regions.
  • the orthographic projection of one gate control line GL on the substrate 201 overlaps with the orthographic projections of the two channel regions of the first switching transistor on the substrate 201 . That is, the first switching transistor is a double-gate transistor.
  • the active layer (T1' or T2') of the first switching transistor (T1 or T2) includes at least one first extension (p1 or p1').
  • the first extension (p1 or p1') of the first switching transistor (T1 or T2) is electrically connected to a conductive region located between the two channel regions of the first switching transistor (T1 or T2), and the first switching transistor (T1 or T2)
  • the orthographic projection of the first extension (p1 or p1') of (T1 or T2) on the substrate 201 and the orthographic projection of a gate control line GL on the substrate 201 are at least partially, and the overlapping portion of the two forms a stable piezo capacitor (C1 or C5).
  • the gate control line GL includes a first reset signal line Reset1 or a gate scan line Gate.
  • the active layer of the first switch transistor includes one first extension portion, or two first extension portions, or three first extension portions, and the first extension portion of the first switch transistor is connected to the gate control line GL.
  • the overlapping parts form one stabilizing capacitor, two stabilizing capacitors, or three stabilizing capacitors.
  • the active layer of the first switching transistor includes a plurality of first extension parts, and the overlapping part of the plurality of first extension parts of the first switching transistor and the gate control line GL forms a plurality of stabilizing capacitors, it is possible to enhance the The voltage stability of one end of the plurality of voltage stabilizing capacitors that are electrically connected to the first switching transistor, thereby further enhancing the effect of improving the leakage of the first switching transistor.
  • the following embodiments of the present disclosure are described by taking as an example that the active layer of the first switching transistor includes a first extension.
  • the three conductive regions of the first switching transistor ( T1 or T2 ) are the first conductive region ( t13 or t23 ), the second conductive region ( t14 or t24 ) and the The third conductive region (t15 or t25) and the second conductive region (t14 or t24) are located between the two channel regions of the first switching transistor (T1 or T2).
  • first extension (p1 or p1') is electrically connected to the second conductive region (t14 or t24), and the other end extends away from the second conductive region (t14 or t24); the first extension (p1 or p1) ') is located between the first conductive region and the third conductive region, or is located on one side of the main body of the active layer of the first switching transistor.
  • the active layer of the first switching transistor is introduced by taking the first switching transistor as the first transistor T1 or the second transistor T2 as an example.
  • the first switching transistor is a first transistor T1
  • the first transistor T1 is a double-gate transistor
  • the active layer body t1 of the first transistor T1 is U-shaped
  • the first transistor T1 has a U-shape.
  • the active layer body t1 includes a first channel region t11, a second channel region t12, a first conductive region t13, a second conductive region t14 and a third conductive region t15, and one end of the first extension p1 of the first transistor T1 It is electrically connected to the second conductive region t14, and the other end extends away from the second conductive region t14.
  • the orthographic projection of the first extension p1 of the first transistor T1 on the substrate 201 is the same as the first reset signal line Reset1 on the substrate.
  • the orthographic projections on 201 overlap at least in part, and the overlapping part of the two forms the first voltage stabilization capacitor C1.
  • the first extension of the first transistor T1 is located between the first conductive region t13 and the third conductive region t15 ; or, as shown in FIGS.
  • the first extension of the first transistor T1 An extension p1 is located on one side of the active layer body t1 of the first transistor T1, for example, the first extension p1 of the first transistor T1 is located on a side of the first conductive region t13 away from the third conductive region t15.
  • the overlapping portion of at least one first extension p1 of the first transistor T1 and the first reset signal line Reset1 forms at least one first voltage stabilization capacitor C1. That is, the number of the first extension parts p1 of the first transistor T1 is the same as the number of the first voltage stabilization capacitors C1.
  • the first switching transistor is the second transistor T2
  • the second transistor T2 is a double-gate transistor
  • the main body t2 of the active layer of the second transistor T2 is L-shaped
  • the The active layer body t2 includes a first channel region t21, a second channel region t22, a first conductive region t23, a second conductive region t24 and a third conductive region t25
  • the first extension p1' of the second transistor T2 is One end is electrically connected to the second conductive region t24, and the other end extends away from the second conductive region t24.
  • the orthographic projection of the first extension p1' of the second transistor T2 on the substrate 201 is connected to the first reset signal line Reset1 or
  • the orthographic projections of the gate scanning line Gate on the substrate 201 overlap at least in part, and the overlapping part of the two forms the fifth voltage stabilization capacitor C5 .
  • the first extension p1 ′ of the second transistor T2 is located between the first conductive region t23 and the third conductive region t25 , and the first extension p1 ′ of the second transistor T2 is on the positive side of the substrate 201
  • the projection at least partially overlaps the orthographic projection of the gate scan line Gate on the substrate 201 .
  • the first extension p1 ′ of the second transistor T2 is located at one side of the active layer body t2 of the second transistor T2 , and the first extension p1 of the second transistor T2 'The orthographic projection on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 or the gate scan line Gate on the substrate 201.
  • the second transistor T2 The first extension p1' is located on the side of the second conductive region t24 away from the first conductive region t23, and the orthographic projection of the first extension p1' of the second transistor T2 on the substrate 201 is lined with the gate scan line Gate.
  • the orthographic projections on the base 201 overlap at least partially.
  • the first extension p1 ′ of the second transistor T2 is located on the side of the second conductive region t24 away from the first conductive region t23 , and the first extension p1 ′ of the second transistor T2 is on the substrate 201
  • the orthographic projection of at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201 .
  • At least one first extension of the second transistor T2 overlaps with the first reset signal line Reset1 or the gate scan line Gate to form at least one fifth voltage-stabilizing capacitor C5, that is, the first part of the second transistor T2.
  • the number of an extension portion is the same as the number of the fifth voltage stabilization capacitor C5.
  • the first voltage regulator sub-circuit 110 includes at least one first voltage regulator sub-circuit 110.
  • a stabilizing capacitor C1 and the second stabilizing sub-circuit 111 includes at least one fifth stabilizing capacitor C5.
  • the first transistor T1 when the first reset sub-circuit 103 includes a first transistor T1, and the first transistor T1 is a dual-gate transistor, the first transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12;
  • the control electrode of a sub-transistor T11 is electrically connected to the first reset signal line Reset1, the first electrode of the first sub-transistor T11 is electrically connected to the initialization signal line Vint, and the second electrode of the first sub-transistor T11 is electrically connected to the second sub-transistor T12
  • the first electrode is electrically connected; the control electrode of the second sub-transistor T12 is electrically connected, and the second electrode of the second sub-transistor T12 is electrically connected to the control electrode of the driving transistor Td, that is, the second electrode of the second sub-transistor T12 is electrically connected to the first electrode Node N1 is electrically connected.
  • the first end of the first voltage stabilization capacitor C1 is electrically connected to the second pole of the first sub-transistor T11, that is, the first end of the first voltage stabilization capacitor C1 is electrically connected to the first node N1, and the first end of the first voltage stabilization capacitor C1 is electrically connected to the first node N1.
  • the two terminals are electrically connected to the first reset signal line Reset1.
  • the second transistor T2 When the compensation sub-circuit 104 includes the second transistor T2, and the second transistor T2 is a dual-gate transistor, the second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22; the control electrode of the third sub-transistor T21 is the same as the The gate scanning line Gate is electrically connected, the first pole of the third sub-transistor T21 is electrically connected with the second pole of the driving transistor Td, and the second pole of the third sub-transistor T21 is electrically connected with the first pole of the fourth sub-transistor T22;
  • the control electrode of the fourth sub-transistor T22 is electrically connected to the gate scanning line Gate, and the second electrode of the fourth sub-transistor T22 is electrically connected to the control electrode of the driving transistor Td, that is, the second electrode of the fourth sub-transistor T22 is electrically connected to the first node N1 is electrically connected.
  • the first end of the fifth voltage stabilization capacitor C5 is electrically connected to the second pole of the third sub-transistor T21, that is, the first end of the fifth voltage stabilization capacitor C5 is electrically connected to the first node N1, and the first end of the fifth voltage stabilization capacitor C5 is electrically connected to the first node N1.
  • the two terminals are electrically connected to the first reset signal line Reset1 or the gate scan line Gate.
  • the principle of suppressing the leakage of the second transistor T2 by the fifth voltage stabilization capacitor C5 is described below by taking the working process of the second transistor T2 and the fifth voltage stabilization capacitor C5 as an example. Since the structures of the first transistor T1 and the first voltage stabilization capacitor C1 are similar to that of the second transistor T2 and the fifth voltage stabilization capacitor C5, the principle of suppressing the leakage of the first transistor T1 by the first voltage stabilization capacitor C1 can refer to the following description. It is not repeated here.
  • the second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22 , which are described below.
  • the potential of the first electrode of the third sub-transistor T21 is V s
  • the potential of the second electrode of the third sub-transistor T21 is V d'
  • the potential of the first electrode of the fourth sub-transistor T22 is V s'
  • the potential of the first electrode of the fourth sub-transistor T22 is V s'
  • the potential of the second pole of the four-sub-transistor T22 is V d
  • the potential of the first end of the fifth stabilizing capacitor C5 is V c5 .
  • the third sub-transistor T21 and the fourth sub-transistor T22 are both turned on under the control of the gate scan signal, and transmit the electrical signal I from the second node N2 to the first node N1, and the input and compensation After phase P2, Vs is greater than Vd ' , Vd ' is equal to or approximately equal to Vs ' , and Vs ' is greater than Vd , and Vc5 is equal to or approximately equal to Vs ' , that is, and due to the voltage holding effect of the capacitor, The potential V c5 of the first end of the fifth voltage stabilization capacitor C5 remains stable.
  • the third sub-transistor T21 and the fourth sub-transistor T22 are both turned off under the control of the gate scan signal. Since the potential V c5 of the first end of the fifth voltage stabilization capacitor C5 is maintained, V s' and V d' remains roughly unchanged, and V s' is still greater than V d . In this way, current cannot flow from the second pole of the fourth sub-transistor T22 to the first pole, and the reverse leakage of the first node N1 through the fourth sub-transistor T22 can be suppressed.
  • V s is still greater than V d' , in this way, the current cannot flow from the second pole of the third sub-transistor T21 to the first pole, and the reverse leakage of the third sub-transistor T21 can be suppressed.
  • C5 can effectively reduce the leakage of the third sub-transistor T21 and the fourth sub-transistor T22 in the light-emitting stage P3, so that the voltage of the first node N1 can be maintained.
  • the active layer of the first switch transistor when the first switch transistor is a dual-gate transistor, the active layer of the first switch transistor ( T1 or T2 ) includes at least one first extension ( In addition to p1 or p1'), at least one second extension (p2 or p2') is also included.
  • One of the three conductive regions of the first switching transistor (T1 or T2) is electrically connected to the control electrode of the driving transistor Td; the second extension of the first switching transistor is electrically connected to one of the three conductive regions of the driving transistor Td.
  • the gate control line GL includes a first reset signal line Reset1 or a gate scan line Gate.
  • the active layer of the first switch transistor includes one second extension portion, or two second extension portions, or three second extension portions, and the second extension portion of the first switch transistor is connected to the gate control line GL.
  • the overlapping parts form one stabilizing capacitor, two stabilizing capacitors, or three stabilizing capacitors.
  • the active layer of the first switching transistor includes a plurality of second extension parts, and the overlapping part of the plurality of second extension parts of the first switching transistor and the gate control line GL forms a plurality of stabilizing capacitors, it is possible to enhance the The voltage stability of one end of the plurality of voltage stabilizing capacitors that are electrically connected to the first switching transistor, thereby further enhancing the effect of improving the leakage of the first switching transistor.
  • the following embodiments of the present disclosure are described by taking as an example that the active layer of the first switching transistor includes a second extension.
  • the three conductive regions of the first switching transistor are a first conductive region ( t13 or t23 ), a second conductive region ( t14 or t24 ), and a third conductive region ( t14 or t24 ), respectively.
  • the second conductive region (t14 or t24) is located between the two channel regions of the first switching transistor (T1 or T2); the first conductive region (t13 or t23) and the control electrode of the driving transistor Td electrical connection.
  • One end of the second extension portion (p2 or p2') is electrically connected to the first conductive region (t13 or t23), and the other end extends away from the first conductive region (t13 or t23).
  • the second extension is located between the first conductive region and the third conductive region, or is located on one side of the active layer body of the first switching transistor.
  • the active layer of the first switching transistor is introduced by taking the first switching transistor as the first transistor T1 or the second transistor T2 as an example.
  • the first switching transistor is a first transistor T1
  • the first transistor T1 is a double-gate transistor
  • the active layer body t1 of the first transistor T1 is U-shaped
  • the first transistor T1 has a U-shape.
  • the active layer body t1 includes a first channel region t11, a second channel region t12, a first conductive region t13, a second conductive region t14 and a third conductive region t15, and one end of the second extension p2 of the first transistor T1 It is electrically connected to the first conductive region t13, and the other end extends away from the first conductive region t13.
  • the orthographic projection of the second extension p2 of the first transistor T1 on the substrate 201 is connected to the first reset signal line Reset1 or the gate.
  • the orthographic projections of the scan line Gate on the substrate 201 overlap at least in part, and the overlapping part of the two forms the second voltage stabilization capacitor C2 .
  • the second extension p2 of the first transistor T1 is located between the first conductive region t13 and the third conductive region t15 , and the orthographic projection of the second extension p2 of the first transistor T1 on the substrate 201 is the same as the The orthographic projections of the first reset signal line Reset1 on the substrate 201 at least partially overlap.
  • the second extension p2 of the first transistor T1 is located on one side of the main body of the active layer of the first transistor T1 , exemplarily, as shown in FIG.
  • the two extensions p2 are located on the side of the first conductive region t13 away from the third conductive region t15 and close to the first reset signal line Reset1.
  • the orthographic projection of the second extension p2 of the first transistor T1 on the substrate 201 is the same as that of the first reset signal line Reset1.
  • the orthographic projections of the reset signal line Reset1 on the substrate 201 at least partially overlap.
  • the second extension p2 of the first transistor T1 is located on the side of the first conductive region t13 away from the third conductive region t15 and close to the gate scan line Gate, and the second extension p2 of the first transistor T1 is on the side of the first conductive region t13.
  • the orthographic projection on the bottom 201 at least partially overlaps the orthographic projection of the gate scan line Gate on the substrate 201 .
  • At least one second voltage-stabilizing capacitor C2 is formed by the overlapping portion of at least one second extension p2 of the first transistor T1 and the first reset signal line Reset1 or the gate scan line Gate. That is, the number of the second extension portions of the first transistor T1 is the same as the number of the second voltage stabilization capacitors C2.
  • the first switching transistor is the second transistor T2
  • the second transistor T2 is a double-gate transistor
  • the main body of the active layer of the second transistor T2 is L-shaped
  • the second transistor T2 has
  • the source layer body t2 includes a first channel region t21, a second channel region t22, a first conductive region t23, a second conductive region t24 and a third conductive region t25, and one end of the second extension p2' of the second transistor T2 It is electrically connected to the second conductive region t24, and the other end extends away from the second conductive region t24.
  • the orthographic projection of the second extension p2' of the second transistor T2 on the substrate 201 is connected to the first reset signal line Reset1 or the gate.
  • the orthographic projections of the polar scanning line Gate on the substrate 201 at least partially overlap, and the overlapping portion of the two forms the sixth voltage stabilization capacitor C6.
  • the second extension p2' of the second transistor T2 is located at one side of the active layer body t2 of the first transistor T1, and the second extension p2' of the second transistor T2
  • the orthographic projection on the substrate 201 at least partially overlaps the orthographic projection of the gate scan line Gate on the substrate 201 .
  • the orthographic projection of the second extension p2' of the second transistor T2 on the substrate 201 at least partially overlaps the orthographic projection of the first reset signal line Reset1 on the substrate 201.
  • the overlapping portion of at least one second extension p2' of the second transistor T2 and the first reset signal line Reset1 or the gate scan line Gate forms at least one sixth voltage stabilization capacitor C6, that is, the second transistor T2
  • the number of the first extension parts is the same as the number of the fifth voltage stabilization capacitor C5.
  • the first voltage regulator sub-circuit 110 includes at least one first voltage regulator capacitor. Based on C1, it also includes at least one second voltage stabilization capacitor C2, and the second voltage stabilization sub-circuit 111 further includes at least one sixth voltage stabilization capacitor C6 in addition to at least one fifth voltage stabilization capacitor C5.
  • the first end of the second voltage stabilization capacitor C2 is electrically connected to the second electrode of the second sub-transistor T12, and the second end of the second voltage stabilization capacitor C2 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. Since the second pole of the second sub-transistor T12 is electrically connected to the first node N1, that is to say, the first end of the second voltage stabilization capacitor C2 is electrically connected to the first node N1.
  • the first end of the sixth voltage stabilization capacitor C6 is electrically connected to the second pole of the fourth sub-transistor T22, and the second end of the sixth voltage stabilization capacitor C6 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. Since the second pole of the fourth sub-transistor T22 is electrically connected to the first node N1, that is to say, the first end of the second voltage stabilization capacitor C2 is electrically connected to the first node N1.
  • the sixth voltage stabilization capacitor C6 is electrically connected to the first node N1, which is equivalent to the sixth voltage stabilization capacitor C6 and the storage capacitor Cst being connected in parallel.
  • the sixth voltage stabilization capacitor C6 is also charged at the same time, that is, the potential of the first end of the sixth voltage stabilization capacitor C6 is consistent with the potential of the first end of the storage capacitor Cst.
  • the charge stored in the sixth voltage stabilization capacitor C6 can provide a part of the charge to the first node N1, which can be used to make up for the second transistor
  • the voltage drop caused by the leakage of T2 is equivalent to enhancing the charge storage capacity of the storage capacitor Cst by setting the sixth voltage stabilization capacitor C6, which can keep the potential of the first node N1 stable, and can make the first electrode of the second transistor T2 stable.
  • the voltage difference between the second electrode and the second electrode is reduced, thereby reducing the leakage of the second transistor T2.
  • the working principle of the second stabilizing capacitor C2 can be referred to the description of the working principle of the sixth stabilizing capacitor C6, which will not be repeated here.
  • FIGS. 15 to 21 provide various pattern designs of the semiconductor layer 202 , and the present disclosure may also include other embodiments, as long as the function of suppressing the leakage of the first switching transistor can be realized.
  • 22 is an overall structural diagram of the semiconductor layer 202, the first gate layer 204, the second gate layer 206 and the source-drain metal layer.
  • the active layer of the first transistor T1 includes: The main body of the active layer and the extension part, the active layer of the second transistor T2 includes the main body of the active layer and the extension part, and the pattern of the remaining film layers has not changed from that in FIG.
  • the overall structure diagrams of various structures can be obtained.
  • the first switching transistor is a single-gate transistor.
  • the active layer body (t1 or t2) of the first switching transistor (T1 or T2) includes a channel region (t11 or t22), a fourth conductive region (t16) or t26) and the fifth conductive region (t17 or t27), the fourth conductive region (t16 or t26) and the fifth conductive region (t17 or t27) are located on both sides of the channel region (t11 or t22), respectively; a gate
  • the orthographic projection of the control line GL on the substrate 201 overlaps with the orthographic projection of the channel region of the first switching transistor on the substrate 201 .
  • the fourth conductive region (t16 or t26) is electrically connected to the control electrode of the driving transistor Td.
  • the active layer (T1' or T2') of the first switching transistor (T1 or T2) includes at least one third extension (p3 or p3'); the third extension (p3 or p3') and the fourth conductive region ( t16 or t26) are electrically connected, and the orthographic projection of the third extension (p3 or p3') on the substrate 201 at least partially overlaps with the orthographic projection of the gate control line GL on the substrate 201, and the overlapping portion of the two form a stabilizing capacitor.
  • the gate control line GL includes a first reset signal line Reset1 or a gate scan line Gate.
  • the active layer (T1' or T2') of the first switching transistor (T1 or T2) further includes a fourth extension (p4 or p4'); the fourth extension (p4 or p4') and The fifth conductive region ( t17 or t27 ) is electrically connected, and the orthographic projection of the fourth extension ( p4 or p4 ′) on the substrate 201 at least partially overlaps the orthographic projection of the gate control line GL on the substrate 201 .
  • the active layer of the first switching transistor includes one third extension/fourth extension, or two third/fourth extension, or three third/fourth extension,
  • the overlapping portion of the third extension of the first switching transistor and the gate control line GL forms one voltage stabilization capacitor, two voltage stabilization capacitors, or three voltage stabilization capacitors.
  • the active layer of the first switch transistor includes a plurality of third extension parts/fourth extension parts, and the overlapping part of the plurality of second extension parts of the first switch transistor and the gate control line GL forms a plurality of voltage stabilizing capacitors.
  • the voltage stability of one end of the plurality of voltage stabilizing capacitors electrically connected to the first switching transistor can be enhanced, thereby further enhancing the effect of improving the leakage of the first switching transistor.
  • the embodiments of the present disclosure are described by taking as an example that the active layer of the first switching transistor includes a third extension portion and a fourth extension portion.
  • the active layer of the first switching transistor is introduced by taking the first switching transistor as the first transistor T1 or the second transistor T2 as an example.
  • the first switching transistor is a first transistor T1
  • the first transistor T1 is a single-gate transistor
  • the active layer body t1 of the first transistor T1 includes a channel region t11, a fourth conductive region t16 and The fifth conductive region t17, the fourth conductive region t16 and the fifth conductive region t17 are respectively located on both sides of the channel region t11
  • the fourth conductive region t16 is electrically connected to the control electrode of the driving transistor Td
  • the third extension of the first transistor T1 The portion p3 is electrically connected to the fourth conductive region t16 of the first transistor T1, and the orthographic projection of the third extension portion p3 of the first transistor T1 on the substrate 201 and the orthographic projection of the first reset signal line Reset1 on the substrate 201 At least partially overlapping, and the overlapping part of the two forms the third voltage stabilization capacitor C3.
  • the first transistor T1 further includes a fourth extension p4, the fourth extension p4 of the first transistor T1 is electrically connected to the fifth conductive region t17 of the first transistor T1, and the first The orthographic projection of the fourth extension p4 of the transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201, and the overlapping portion of the two forms a fourth voltage stabilization capacitor C4.
  • the first switching transistor is a second transistor T2
  • the second transistor T2 is a single-gate transistor
  • the active layer body of the second transistor T2 includes a channel region t22, a fourth conductive region t26 and a second transistor T2.
  • Five conductive regions t27, the fourth conductive region t26 and the fifth conductive region t27 are respectively located on both sides of the channel region t22, the fourth conductive region t26 is electrically connected to the control electrode of the driving transistor Td, and the third extension of the second transistor T2 p3' is connected to the fourth conductive region t26 of the second transistor T2, and the orthographic projection of the third extension t26 of the second transistor T2 on the substrate 201 and the orthographic projection of the gate scan line Gate on the substrate 201 are at least partially Overlapping, the overlapping part of the two forms the seventh stabilizing capacitor C7.
  • the second transistor T2 further includes a fourth extension p4 ′, the fourth extension p4 ′ of the second transistor T2 is electrically connected to the fifth conductive region t27 of the second transistor T2 , and The orthographic projection of the fourth extension p4' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scanning line Gate on the substrate 201, and the overlapping portion of the two forms the eighth voltage stabilization capacitor C8 .
  • a voltage stabilization sub-circuit 110 includes at least one third voltage stabilization capacitor C3, the second voltage stabilization sub-circuit 111 includes at least one seventh voltage stabilization capacitor C7, or the first voltage stabilization sub-circuit 110 includes at least one third voltage stabilization capacitor C3 and at least one fourth voltage stabilization capacitor C4, the second voltage stabilization sub-circuit 111 includes at least one seventh voltage stabilization capacitor C7 and at least one eighth voltage stabilization capacitor C8.
  • the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, and the first electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1. It is electrically connected to the initialization signal line Vint, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the driving transistor Td.
  • One end of the third voltage stabilization capacitor C3 is electrically connected to the second electrode of the first transistor T1, and the second end of the third voltage stabilization capacitor C3 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.
  • One end of the fourth voltage stabilization capacitor C4 is electrically connected to the first electrode of the first transistor T1, and the second end of the fourth voltage stabilization capacitor C4 is electrically connected to the first reset signal line Reset1 or the gate scanning line Gate.
  • the compensation sub-circuit 104 includes a second transistor T2, and the second transistor T2 is a single-gate transistor, the control electrode of the second transistor T2 is electrically connected to the gate scan line Gate, and the first electrode of the second transistor T2 is connected to the driving transistor
  • the second electrode of Td is electrically connected, and the second electrode of the second transistor T2 is electrically connected to the control electrode of the driving transistor Td.
  • the first end of the seventh voltage stabilization capacitor C7 is electrically connected to the second electrode of the second transistor T2, and the second end of the seventh voltage stabilization capacitor C7 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.
  • the first end of the eighth voltage stabilization capacitor C8 is electrically connected to the first electrode of the second transistor T2, and the second end of the fourth voltage stabilization capacitor C4 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.
  • the principle of suppressing the leakage of the second transistor T2 by the seventh stabilizing capacitor C7 and the eighth stabilizing capacitor C8 is described below by taking the working process of the second transistor T2, the seventh stabilizing capacitor C7 and the eighth stabilizing capacitor C8 as an example. Since the structures of the first transistor T1, the third voltage stabilization capacitor C3 and the fourth voltage stabilization capacitor C4 are similar to those of the second transistor T2, the seventh voltage stabilization capacitor C7 and the eighth voltage stabilization capacitor C8, the third voltage stabilization capacitor C3 and The principle of suppressing the leakage of the first transistor T1 by the fourth voltage-stabilizing capacitor C4 can be referred to the following description, which will not be repeated here.
  • the potential of the first electrode of the second transistor T2 is V s
  • the potential of the second electrode of the second sub-transistor T12 is V d
  • the seventh voltage regulator The potential of the first end of the capacitor C7 is V c7
  • the potential of the first end of the eighth voltage stabilization capacitor C8 is V c8 .
  • the second transistor T2 is turned on under the control of the gate scan signal, and transmits the electrical signal I from the second node N2 to the first node N1.
  • V s is greater than V d
  • V c7 are equal to or approximately equal to V d
  • V c8 is equal to or approximately equal to V s
  • the potential V c8 at the first end can be kept stable.
  • the second sub-transistor T12 is turned off under the control of the gate scanning signal, and the potential V c7 at the first end of the seventh voltage stabilization capacitor C7 and the potential V c8 at the first end of the eighth voltage stabilization capacitor C8 are maintained , so V s and V d remain roughly unchanged, and V s is still greater than V d .
  • the current cannot flow from the second pole of the second transistor T2 to the first pole, which can prevent the first node N1 from being reversed through the second transistor T2. leakage, so that the voltage of the first node N1 is maintained.
  • the seventh voltage stabilization capacitor C7 is electrically connected to the first node N1, which is equivalent to the seventh voltage stabilization capacitor C7 and the storage capacitor Cst being connected in parallel.
  • the seventh voltage stabilization capacitor C7 is also charged at the same time, that is, the potential of the first end of the seventh voltage stabilization capacitor C7 is consistent with the potential of the first end of the storage capacitor Cst.
  • the charge stored in the seventh voltage stabilization capacitor C7 can provide a part of the charge to the first node N1, which can be used to make up for the voltage drop caused by the leakage of the second transistor T2, which is equivalent to passing Setting the seventh voltage stabilization capacitor C7 enhances the charge storage capability of the storage capacitor Cst, can keep the potential of the first node N1 stable, and can reduce the voltage difference between the first pole and the second pole of the second transistor T2, Thereby, the leakage of the second transistor T2 is reduced.
  • the third stabilizing capacitor C3 reference may be made to the description of the working principle of the seventh stabilizing capacitor C7, which will not be repeated here.
  • FIG. 26 is an overall structural diagram of the semiconductor layer 202, the first gate layer 204, the second gate layer 206 and the source-drain metal layer, wherein in the semiconductor layer 202, the active layer of the first transistor T1 includes: The main body of the active layer and the extension part, the active layer of the second transistor T2 includes the main body of the active layer and the extension part, and the pattern of the remaining film layers has not changed compared with that in FIG.
  • Various overall structure diagrams can be obtained by replacing the layer 202 with the semiconductor layer 202 in FIG. 26 .

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Abstract

一种显示面板（01），包括：衬底（201）、设置于衬底（201）上的多个子像素（10）和多条栅极控制线（GL）；每个子像素（10）包括像素电路（100）；像素电路（100）包括驱动晶体管（Td）和至少一个第一开关晶体管（T1），第一开关晶体管（T1）与驱动晶体管（Td）的控制极电连接；每个像素电路（100）与至少两条栅极控制线（GL）电连接。其中，第一开关晶体管（T1）包括有源层（T1'），有源层（T1'）包括有源层主体（t1）和至少一个延伸部（p），有源层主体（t1）包括至少一个沟道区和至少一个导电区；延伸部（p）与有源层主体（t1）的导电区电连接；延伸部（p）在衬底（201）上的正投影与一条栅极控制线（GL）在衬底（201）上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。

Description

显示面板、像素电路及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、像素电路及显示装置。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置因其具有自发光、快速响应、宽视角和可制作在柔性衬底上等特点，受到广泛应用，OLED显示装置包括多个子像素，各子像素包括像素电路和发光器件，通过像素电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种显示面板，包括：衬底、设置于所述衬底上的多个子像素和多条栅极控制线。每个子像素包括像素电路；所述像素电路包括驱动晶体管和至少一个第一开关晶体管，所述第一开关晶体管与所述驱动晶体管的控制极电连接。每个像素电路与至少两条栅极控制线电连接。其中，所述第一开关晶体管包括有源层，所述有源层包括有源层主体和至少一个延伸部，所述有源层主体包括至少一个沟道区和至少一个导电区。所述延伸部与所述有源层主体的导电区电连接；所述延伸部在所述衬底上的正投影与一条栅极控制线在所述衬底上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。
在一些实施例中，所述第一开关晶体管的有源层包括至少一个第一延伸部；所述第一开关晶体管的有源层主体包括两个沟道区和三个导电区，导电区与沟道区依次交替电连接，且其中一个导电区位于所述两个沟道区之间，一条栅极控制线在所述衬底上的正投影与所述第一开关晶体管的两个沟道区在所述衬底上的正投影重叠。所述第一开关晶体管的第一延伸部与位于所述第一晶体管的两个沟道区之间的导电区电连接，且所述第一开关晶体管的第一延伸部在所述衬底上的正投影与一条栅极控制线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一开关晶体管的三个导电区分别为第一导电区、第二导电区和第三导电区，所述第二导电区位于位于所述第一开关晶体管的两个沟道区之间。所述延伸部的一端与所述第二导电区电连接，另一端向远离所述第二导电区的方向延伸；所述第一延伸部位于所述第一导电区与所述第三导电区之间，或者位于所述第一晶体管的有源层主体的一侧。
在一些实施例中，所述第一开关晶体管的有源层还包括至少一个第二延伸部；所述第一开关晶体管的三个导电区中的一个导电区与所述驱动晶体管的控制极电连接；所述第一开关晶体管的第二延伸部与所述三个导电区中电连接所述驱动晶体管的控制极的一个导电区电连接，且所述第一开关晶体管的第二延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一开关晶体管的三个导电区分别为第一导电区、第二导电区和第三导电区，所述第二导电区位于位于所述第一开关晶体管的两个沟道区之间；所述第一导电区与所述驱动晶体管的控制极电连接。所述第二延伸部的一端与所述第一导电区电连接，另一端向远离所述第一导电区的方向延伸；所述第二延伸部位于所述第一导电区与所述第三导电区之间，或者位于所述第一开关晶体管的有源层主体的一侧。
在一些实施例中，所述第一开关晶体管的有源层包括至少一个第三延伸部；所述第一开关晶体管的有源层主体包括沟道区、第四导电区和第五导电区，所述第四导电区和所述第五导电区分别位于所述沟道区的两侧；其中，所述第四导电区与所述驱动晶体管的控制极电连接；所述第三延伸部与所述第四导电区连接，且所述第三延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一开关晶体管的有源层还包括第四延伸部；所述第四延伸部与所述第五导电区电连接，且所述第四延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
在一些实施例中，显示面板还包括：多条初始化信号线，每个像素电路还与至少一条初始化信号线电连接。其中，与所述像素电路电连接的栅极控制线包括第一复位信号线；所述至少一个第一开关晶体管包括第一晶体管；所述第一晶体管的控制极与所述第一复位信号线电连接，所述第一晶体管的第一极与一条初始化信号线电连接，所述第一晶体管的第二极与所述驱动晶体管的控制极电连接。所述第一晶体管的延伸部在所述衬底上的正投影与所述第一复位信号线在所述衬底上的正投影至少部分重叠。
在一些实施例中，与所述像素电路电连接的栅极控制线还包括栅极扫描线；所述至少一个第一开关晶体管还包括第二晶体管；所述第二晶体管的控制极与所述栅极扫描线电连接，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接。所述第二晶体管的延伸部在所述衬底上的正投影与所述栅极扫描线在所 述衬底上的正投影至少部分重叠；或者，所述第二晶体管的延伸部在所述衬底上的正投影与所述第一复位信号线在所述衬底上的正投影至少部分重叠。
在一些实施例中，显示面板还包括：多条第一电压信号线、多条发光控制线和多条数据线。与所述像素电路电连接的栅极控制线还包括第二复位信号线。每个像素电路还与一条第一电压信号线电连接。
所述像素电路还包括存储电容器；所述存储电容器包括相对设置的第一极板和第二极板；所述第一极板与所述多条栅极控制线同层设置，所述第一极板与所述驱动晶体管的控制极电连接；所述第二极板设置于所述第一极板远离所述衬底的一侧；所述第二极板与所述第一电压信号线电连接。
每个像素电路与一条发光控制线、一条数据线、和所述第二复位信号线电连接；所述像素电路还包括至少一个第二开关晶体管，每个第二开关晶体管与所述驱动晶体管的第一极或第二极电连接。
另一方面，提供一种像素电路，包括：驱动子电路、存储子电路、第一复位子电路、补偿子电路、第一稳压子电路和第二稳压子电路。
所述驱动子电路被配置为产生驱动电流。所述存储子电路与所述驱动子电路和第一电压信号线电连接；所述存储子电路被配置为存储所接收的信号，并保持所述存储子电路与所述驱动子电路的连接端的电位。所述第一复位子电路与第一复位信号线、所述驱动子电路和初始化信号线电连接；所述复位子电路被配置为，响应于在所述第一复位信号线处接收的第一栅极信号，将在所述初始化信号线处接收的初始化信号传输至所述驱动子电路。所述补偿子电路与所述驱动子电路和栅极扫描线电连接；所述补偿子电路被配置为，响应于在所述栅极扫描线处接收的栅极扫描信号，对所述驱动子电路进行阈值补偿。
所述第一稳压子电路与所述第一复位子电路、所述第一复位信号线或所述栅极扫描线电连接；所述第一稳压子电路被配置为抑制所述第一复位子电路漏电。所述第二稳压子电路与所述补偿子电路、所述第一复位信号线或所述栅极扫描线电连接；所述第一稳压子电路被配置为抑制所述补偿子电路漏电。
在一些实施例中，所述驱动子电路包括驱动晶体管；所述第一稳压子电路包括至少一个第一稳压电容器。所述第一复位子电路包括第一晶体管，所述第一晶体管为双栅晶体管。所述第一晶体管包括第一子晶体管和第二子晶体管；所述第一子晶体管的控制极与所述第一复位信号线电连接，所述第一子晶体管的第一极与所述初始化信号线电连接，所述第一子晶体管的第二极 与所述第二子晶体管的第一极电连接；所述第二子晶体管的控制极与所述第一复位信号线电连接，所述第二子晶体管的第二极与所述驱动晶体管的控制极电连接；所述第一稳压电容器的第一端与所述第一子晶体管的第二极电连接，所述第一稳压电容器的第二端与所述第一复位信号线电连接。
在一些实施例中，所述第一稳压子电路还包括至少一个第二稳压电容器；所述第二稳压电容器的第一端与所述第二子晶体管的第二极电连接，所述第二稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
在一些实施例中，所述驱动子电路包括驱动晶体管；所述第一稳压子电路包括至少一个第三稳压电容器和至少一个第四稳压电容器。所述第一复位子电路包括第一晶体管，所述第一晶体管的控制极与所述第一复位信号线电连接，所述第一晶体管的第一极与所述初始化信号线电连接，所述第一晶体管的第二极与所述驱动晶体管的控制极电连接。所述第三稳压电容器的第一端与所述第一晶体管的第二极电连接，所述第三稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。所述第四稳压电容器的第一端与所述第一晶体管的第一极电连接，所述第四稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
在一些实施例中，所述驱动子电路包括驱动晶体管；所述第二稳压子电路包括至少一个第五稳压电容器。所述补偿子电路包括第二晶体管，所述第二晶体管为双栅晶体管；所述第二晶体管包括第三子晶体管和第四子晶体管；所述第三子晶体管的控制极与所述栅极扫描线电连接，所述第三子晶体管的第一极与所述驱动晶体管的第二极电连接，所述第三子晶体管的第二极与所述第四子晶体管的第一极电连接；所述第四子晶体管的控制极与所述栅极扫描线电连接，所述第四子晶体管的第二极与所述驱动晶体管的控制极电连接。所述第五稳压电容器的第一端与所述第三子晶体管的第二极电连接，所述第五稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
在一些实施例中，所述第二稳压子电路还包括至少一个第六稳压电容器。所述第六稳压电容器的第一端与所述第四子晶体管的第二极电连接，所述第六稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
在一些实施例中，所述驱动子电路包括驱动晶体管；所述第二稳压子电路包括至少一个第七稳压电容器和至少一个第八稳压电容器。所述补偿子电路包括第二晶体管，所述第二晶体管的控制极与所述栅极扫描线电连接，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接。所述第七稳压电容器的第一端 与所述第二晶体管的第二极电连接，所述第七稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。所述第八稳压电容器的第一端与所述第二晶体管的第一极电连接，所述第八稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
在一些实施例中，像素电路还包括：数据写入子电路、第二复位子电路、第一发光控制子电路和第二发光控制子电路。所述数据写入子电路与所述栅极扫描线、数据线和所述驱动子电路电连接；所述数据写入子电路被配置为，响应于在所述栅极扫描线处接收的栅极扫描信号，将在所述数据线处接收的数据信号传输至所述驱动子电路。所述驱动子电路和所述补偿子电路还被配置为将所述数据信号传输至所述存储子电路。
所述第二复位子电路与第二复位信号线、所述初始化信号线和发光器件电连接；所述第二复位子电路被配置为，响应于在所述栅极扫描线处接收的栅极扫描信号，将在所述初始化信号线处接收的初始化信号传输至所述发光器件。所述第一发光控制子电路与发光控制线、所述第一电压信号线和所述驱动子电路电连接，所述第一发光控制子电路被配置为，响应于在所述发光控制线处接收的发光控制信号，将在所述第一电压信号线处接收的第一电压信号传输至所述驱动子电路。所述第二发光控制子电路与所述发光控制线、所述驱动子电路和所述发光器件电连接；所述第二发光控制子电路被配置为将所述驱动子电路产生的驱动电流传输至所述发光器件，以控制所述发光器件发光。
再一方面，提供一种显示装置，包括如上述实施例中任一项所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示面板的结构图；
图3A为根据一些实施例的一种像素电路的结构图；
图3B为根据一些实施例的另一种像素电路的结构图；
图4为根据一些实施例的像素电路的时序图；
图5为根据一些实施例的显示面板的膜层结构图；
图6为根据一些实施例的一种半导体层的结构图；
图7为根据一些实施例的另一种半导体层的结构图；
图8为根据一些实施例的第一栅极层的结构图；
图9为根据一些实施例的第二栅极层的结构图；
图10为根据一些实施例的源漏金属层的结构图；
图11为根据一些实施例的一种像素电路的整体布局图；
图12为根据一些实施例的另一种像素电路的整体布局图；
图13为根据一些实施例的又一种半导体层的结构图；
图14为根据一些实施例的一种半导体层与第一栅极层的结构图；
图15为根据一些实施例的另一种半导体层与第一栅极层的结构图；
图16为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图17为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图18为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图19为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图20为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图21为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图22为根据一些实施例的又一种像素电路的整体布局图；
图23为根据一些实施例的又一种半导体层的结构图；
图24为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图25为根据一些实施例的又一种半导体层与第一栅极层的结构图；
图26为根据一些实施例的又一种像素电路的整体布局图；
图27为根据一些实施例的又一种像素电路的结构图；
图28A为根据图27中像素电路中第二晶体管在导通状态的示意图；
图28B为根据图27中像素电路中第二晶体管在截止状态的示意图；
图29为根据一些实施例的又一种像素电路的结构图；
图30A为根据图29中像素电路中第二晶体管在导通状态的示意图；
图30B为根据图29中像素电路中第二晶体管在截止状态的示意图；
图31为根据一些实施例的又一种像素电路的结构图；
图32为根据一些实施例的又一种像素电路的结构图；
图33A为根据图32中像素电路中第二晶体管在导通状态的示意图；
图33B为根据图32中像素电路中第二晶体管在截止状态的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本公开的一些实施例提供了一种显示装置，该显示装置例如可以是手机、平板电脑、个人数字助理(personal digital assistant，PDA)、电视机、车载电脑、可穿戴显示设备等，例如可以为手表。如图1所示，显示装置1000可以为手机。本公开实施例对上述显示装置的具体形式不做特殊限制。
在一些示例中，该显示装置也可以为电致发光显示装置或光致发光显示装置。在该显示装置为电致发光显示装置的情况下，电致发光显示装置可以为有机电致发光显示装置(Organic Light-Emitting Diode，简称OLED)或量子点电致发光显示装置(Quantum Dot Light Emitting Diodes，简称QLED)。在该显示装置为光致发光显示装置的情况下，光致发光显示装置可以为量子点光致发光显示装置。
显示装置1000包括显示面板01，如图2所示，该显示面板01包括显示区AA(Active Area，简称AA区；也可称为有效显示区)和位于显示区AA至少一侧的周边区BB。
在一些实施例中，显示面板包括衬底201、设置于衬底201上的多个子像素(sub pixel)10，多条栅极控制线GL、多条数据线DL、多条初始化信号线VINT和多条第一电压信号线VDD。示例性地，多条栅极控制线GL和多条初始化信号线Vint沿水平方向X延伸，多条数据线DL和多条第一电压信号线VDD沿竖直方向Y延伸。多个子像素10、多条栅极控制线GL、多条数据线DL和多条初始化信号线Vint和多条第一电压信号线VDD均设置于显示区AA。
为了方便说明，本公开中上述多个子像素10是以矩阵形式排列为例进行的说明，示例性地，多个子像素10排成N行M列。此时，沿水平方向X排列成一排的子像素10称为一行子像素，沿竖直方向Y排列成一排的子像素10称为一列子像素，每个子像素10包括发光器件和用于控制发光器件发光的像素电路100，像素电路100设置在显示面板01的衬底201上。一行子像素可以与一条或两条栅极控制线GL耦接，示例性地，每个像素电路100与至少 两条栅极控制线GL电连接，一行子像素还可以与一条或两条发光时序信号线EL耦接，一列子像素可以与一条数据信号线DL耦接。
上述显示面板01可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板等，本公开对此不做具体限定。
本公开以下实施例均是以上述显示面板01为有机发光二极管显示面板为例，对本公开进行说明的。
示例性的，像素电路100通常包括开关晶体管、驱动晶体管和存储电容器等元件。其中，存储电容器的相对的两端分别为基准电位端和信号保持端，示例性地，存储电容器的基准电位端与第一电压信号线VDD电连接，存储电容器的信号保持端与驱动晶体管的控制极(栅极)耦接。
在像素电路100的驱动过程中，在发光阶段，存储电容器用以保持电压信号，使其信号保持端的电位得以保持恒定，在驱动晶体管的栅极-源极之间形成电压，从而控制驱动晶体管形成驱动电流，进而驱动发光二极管发光。在该过程中，理性情况下，与驱动晶体管的控制极电连接的开关晶体管处于截止状态，不会有电流通过，这样信号保持端的电位能够保持稳定，然而在实际电路中，开关晶体管在截止状态下本身存在漏电流，且受工艺异常的影响，开光晶体管的漏电流较明显，这样就会使得存储电容器的信号保持端的电位无法长时间保持恒定，从而导致驱动晶体管所形成的驱动电流不稳定，影响发光器件的发光亮度，进而影响显示装置的显示效果。
具体来说，如图3A和图3B所示，本公开的一些实施例提供了一种像素电路100，该像素电路100包括存储子电路101、驱动子电路102、第一复位子电路103、补偿子电路104、数据写入子电路105、第一发光控制子电路106、第二发光控制子电路107和第二复位子电路108。
驱动子电路102被配置为产生驱动电流。
存储子电路101与驱动子电路102和第一电压信号线VDD电连接；存储子电路101被配置为存储所接收的信号，并保持存储子电路101与驱动子电路102的连接端的电位。
第一复位子电路103与驱动子电路102、第一复位信号线Reset1和初始化信号线Vint电连接；复位子电路被配置为，响应于在第一复位信号线Reset1处接收的第一栅极信号，将在初始化信号线Vint处接收的初始化信号传输至驱动子电路102。
补偿子电路104与驱动子电路102和栅极扫描线Gate电连接；补偿子电 路104被配置为，响应于在栅极扫描线Gate处接收的栅极扫描信号，对驱动子电路102进行阈值补偿。
如图3A和图3B，以下称驱动子电路102与存储子电路101、第一复位子电路103和补偿子电路104所共同电连接的节点为第一节点N1。第一复位子电路103能够将初始化信号传输至第一节点N1，以对第一节点N1进行复位。
示例性地，存储子电路101包括存储电容器Cst，存储电容器Cst的第一端与第一电压信号线VDD电连接，存储电容器Cst的第二端与第一节点N1电连接。
驱动子电路102包括驱动晶体管Td，驱动晶体管Td的控制极与第一节点N1电连接。
第一复位子电路103包括第一晶体管T1，第一晶体管T1的控制极与第一复位信号线Reset1电连接，第一晶体管T1的第一极与初始化信号线Vint电连接，第一晶体管T1的第二极与第一节点N1电连接。
在一些示例中，如图3B所示，第一晶体管T1为双栅晶体管，第一晶体管T1包括第一子晶体管T11和第二子晶体管T12。第一子晶体管T11的控制极与第一复位信号线Reset1电连接，第一子晶体管T11的第一极与初始化信号线Vint电连接，第一子晶体管T11的第二极与第二子晶体管T12的第一极电连接；第二子晶体管T12的控制极与第一复位信号线Reset1电连接，第二子晶体管T12的第二极与驱动晶体管Td的控制极电连接。可以理解为，第一晶体管T1的控制极为第一子晶体管T11和第二子晶体管T12的控制极，第一晶体管T1的第一极为第一子晶体管T11的第一极，第一晶体管T1的第二极为第二子晶体管T12的第二极。
补偿子电路104包括第二晶体管T2，第二晶体管T2的控制极与栅极扫描线Gate电连接，第二晶体管T2的第一极与驱动晶体管Td的第二极电连接，第二晶体管T2的第二极与第一节点N1电连接。
在一些示例中，如图3B所示，第二晶体管T2为双栅晶体管，第二晶体管T2包括第三子晶体管T21和第四子晶体管T22。第三子晶体管T21的控制极与栅极扫描线Gate电连接，第三子晶体管T21的第一极与驱动晶体管Td的第二极电连接，第三子晶体管T21的第二极与第四子晶体管T22的第一极电连接；第四子晶体管T22的控制极与栅极扫描线Gate电连接，第四子晶体管T22的第二极与驱动晶体管Td的控制极电连接。可以理解为，第二晶体管T2的控制极为第二子晶体管T12和第四子晶体管T22的控制极，第二晶体管T2的第一极为第三子晶体管T21的第一极，第二晶体管T2的第二极为第四 子晶体管T22的第二极。
以下称第二晶体管T2的第一极与驱动晶体管Td的第二极电连接的节点为第二节点N2。
数据写入子电路105与栅极扫描线Gate、驱动子电路102和数据线DL电连接，数据写入子电路105被配置为，响应于在所述栅极扫描线Gate处接收的栅极扫描信号，将在数据线DL处接收的数据信号传输至驱动子电路102。
第一发光控制子电路106与发光控制线EL、第一电压信号线VDD和驱动子电路102电连接，所述第一发光控制子电路106被配置为，响应于在发光控制线EL处接收的发光控制信号，将在第一电压信号线VDD处接收的第一电压信号传输至驱动子电路102。
以下称驱动子电路102与数据写入子电路105和第一发光控制子电路106电连接的节点为第三节点N3。
示例性地，数据写入子电路105包括第三晶体管T3，第三晶体管T3的控制极与栅极扫描线Gate电连接，第三晶体管T3的第一极与数据线DL电连接，第三晶体管T3的第二极与第三节点N3电连接。
第一发光控制子电路106包括第四晶体管T4，第四晶体管T4的控制极与发光控制线EL电连接，第四晶体管T4的第一极与第一电压信号线VDD电连接，第四晶体管T4的第二极与第三节点N3电连接。
第二复位子电路108与第二复位信号线Reset2、初始化信号线Vint和发光器件109电连接，的第二复位子电路108被配置为，响应于在所述第二复位信号线Reset2处接收的第二复位信号，将在初始化信号线Vint处接收的初始化信号传输至发光器件109，以对发光器件109进行复位。
第二发光控制子电路107与发光控制线EL、驱动子电路102和发光器件109电连接，第二发光控制子电路107被配置为，响应于在发光控制线EL处接收的发光控制信号，接收驱动子电路102输出的驱动信号，并将驱动信号传输至发光器件109，以控制发光器件109发光。
在一些示例中，第二复位子电路108和第二发光控制子电路107均与发光器件109的阳极耦接，发光器件109的阴极与第二电压信号线VSS电连接。示例性地，发光器件109为发光二极管。
以下称发光器件109与第二复位子电路108、第二发光控制子电路107电连接的节点为第四节点N4。
示例性地，第二复位子电路108包括第五晶体管T5，第五晶体管T5的控制极与第二复位信号线Reset2电连接，第五晶体管T5的第一极与初始化信 号线Vint电连接，第五晶体管T5的第二极与第四节点N4电连接。
第二发光控制子电路107包括第六晶体管T6，第六晶体管T6的控制极与发光控制线EL电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接。
在一些实施例中，一个子像素中的像素电路100所电连接的栅极扫描线Gate和第二复位信号线Reset2为同一条栅极控制线GL，即栅极扫描信号和第二复位信号为相同的信号，在子像素以N行M列进行阵列式排布的情况下，一行子像素的像素电路100所电连接的第一复位信号线Reset1为上一行子像素所电连接的栅极扫描线Gate。
在一些实施例中，上述各子电路所包括的晶体管的导通/截止类型均相同，示例性地，上述第一晶体管T1～第六晶体管T6、驱动晶体管Td均为P型晶体管或者N型晶体管，例如，上述晶体管均为低温多晶硅薄膜晶体管(Low Temperature Poly-silicon Thin Film Transistor)。本公开以上述晶体管均为P型晶体管为例进行说明。
请参见图4，上述像素电路100的驱动过程为，一个帧周期包括复位阶段P1、输入与补偿阶段P2和发光阶段P3。
其中，在复位阶段P1：
第一复位子电路103响应于在第一复位信号线Reset1处接收的第一复位信号，将在初始化信号线Vint处接收的初始化信号传输至第一节点N1，以对第一节点N1进行复位。
储能子电路和驱动子电路102均与第一节点N1电连接，在复位阶段，对储能子电路和驱动子电路102进行复位。
示例性地，如图3A和图3B所示，在像素电路100中的各子电路包括晶体管或电容器的情况下，复位阶段P1包括：
在本公开中“像素电路100中的各子电路包括晶体管或电容器的情况”为储能子电路包括存储电容器Cst、驱动子电路102包括驱动晶体管Td、第一复位子电路103包括第一晶体管T1、补偿子电路104包括第二晶体管T2、数据子电路包括第二晶体管T2、数据写入子电路105包括第三晶体管T3、第一发光控制子电路106包括第四晶体、第二发光控制子电路107包括第六晶体管T6的情况。以下以“0”代表某个信号的电平为低电平，以“1”代表某个信号的电平为高电平。
在复位阶段P1，第一复位信号为0，栅极扫描信号(第二复位信号)为1，发光控制信号为1。
第一晶体管T1在第一复位信号的控制下导通，将初始化信号传输至第一节点N1。第二晶体管T2～第六晶体管T6和驱动晶体管Td均截止。
在一些示例中，在第一晶体管T1为双栅晶体管，第一晶体管T1包括第一子晶体管T11和第二子晶体管T12的情况下，第一晶体管T1在第一复位信号的控制下导通是指，第一子晶体管T11和第二子晶体管T12均在第一复位信号的控制下导通，以传输初始化信号。
在输入与补偿阶段P2：
第二复位子电路108响应于在第二复位信号线Reset2处接收的第二复位信号，将在初始化信号线Vint处接收的初始化信号传输至第四节点N4，以对发光器件109进行复位。
数据写入子电路105响应于在栅极扫描线Gate处接收的栅极扫描信号，将在数据线DL处接收的数据信号传输至第三节点N3。
驱动子电路102在第一节点N1和第三节点N3的电压的作用下，将第三节点N3处的数据信号传输至第二节点N2。
补偿子电路104响应于在栅极扫描线Gate处接收的栅极扫描信号，将在第二节点N2处接收的数据信号传输至第一节点N1，并对驱动子电路102进行阈值补偿。
储能子电路接收并存储第一节点N1的电压。
示例性地，如图3A和图3B所示，在像素电路100中的各子电路包括晶体管或电容器的情况下，输入与补偿阶段P2包括：
在输入与补偿阶段P2，第一复位信号为1，栅极扫描信号(第二复位信号)为0，发光控制信号为1。
第五晶体管T5在第二复位信号的控制下导通，将初始化信号传输至第四节点N4，以对发光器件109的阳极进行复位。
第三晶体管T3在栅极扫描信号的控制下导通，将数据信号传输至第三节点N3。
驱动晶体管Td的控制极(栅极)的电位为第一节点N1的电位，即初始化信号的电位，驱动晶体管Td的第一极(源极)的电位为第三节点N3的电位，即数据信号的电位V data，驱动晶体管Td的栅源电压差小于其阈值电压V th，驱动晶体管Td导通，将数据信号由第三节点N3传输至第二节点N2。
第二晶体管T2在栅极扫描线Gate的控制下导通，将第二节点N2处的数据信号传输至第一节点N1，从而将数据信号写入存储电容器Cst。存储电容器Cst保持第一节点N1的电位。在第二晶体管T2为双栅晶体管，第二晶体 管T2包括第三子晶体管T21和第四子晶体管T22的情况下，第二晶体管T2在栅极扫描线Gate的控制下导通是指，第三子晶体管T21和第四子晶体管T22在栅极扫描线Gate的控制下均导通。
第一节点N1的电位由初始化信号的电位V int逐渐升高，当第一节点N1的电位升高至V data+V th时，驱动晶体管Td截止，输入与补偿阶段结束，从而将数据信号的电压和阈值电压写入存储电容器Cst。
在发光阶段P3：
第一发光控制子电路106响应于在发光控制线EL处接收的发光控制信号，将在第一电压信号线VDD处接收的第一电压信号传输至第三节点N3。
驱动子电路102在第一节点N1和第三节点N3的电压的控制下，产生驱动电流，并将驱动电流输出至第二节点N2。
第二发光控制子电路107响应与在发光信号线处接收的发光控制信号，将在第二节点N2处接收的驱动信号传输至第四节点N4，即发光器件109的阳极，从而发光器件109在驱动信号的控制下发光。
第一晶体管T1、第四晶体管T4和第六晶体管T6截止。
示例性地，如图3A和图3B所示，在像素电路100中的各子电路包括晶体管或电容器的情况下，发光阶段P3包括：
在发光阶段P3，第一复位信号为1，栅极扫描信号(第二复位信号)为1，发光控制信号为0。
第四晶体管T4在发光控制信号的控制下，将第一电压信号传输至第三节点N3。
第三节点N3的电位为第一电压信号的电压，第一节点N1的电位为V data+V th，驱动晶体管Td在第一节点N1和第三节点N3的电压的控制下产生驱动电流，且驱动晶体管Td工作在饱和区，根据饱和电流公式，驱动晶体管Td所产生的驱动电流(输入至发光器件109的电流)为：
Figure PCTCN2020139265-appb-000001
其中，W/L为驱动晶体管Td的沟道宽长比；μ为载流子迁移率；C ox为驱动晶体管Td的单位面积沟道电容；V gs为驱动晶体管Td的栅源电压差；V th为驱动晶体管Td的阈值电压。
可见，输入发光器件109的电流I oled的大小与所写入的数据信号的电压V data和第一电压信号有关，与驱动晶体管Td的阈值电压V th无关，这样就避免因制备工艺引起的各像素电路100的驱动晶体管Td的阈值电压的不同影响驱动电流的大小，进而影响显示效果的问题。
在一个帧周期的整个发光阶段P3，在发光器件109108的发光过程中，驱动子电路102中的驱动晶体管Td所产生的驱动信号为驱动电流，根据驱动电流的计算公式可知，对于驱动晶体管Td来说，其所形成的驱动信号与驱动晶体管Td栅源电压差与阈值电压的差值(V gs-V th)的控制极(栅极)的电位相关，驱动晶体管Td的控制极的电位(即第一节点N1的电位)的稳定性能够影响所形成的驱动信号的稳定性和有效值，从而影响发光器件109的发光的稳定性和持续性。
在发光阶段P3，理想情况下，第一晶体管T1、第二晶体管T2和第三晶体管T3均处于截止状态，不会有电流通过，从而第一节点N1的电位能够保持，然而在实际情况下，开关晶体管在截止状态会存在漏电流，且受工艺异常影响，开关晶体管的漏电流会较大，使得第一节点N1和第三节点N3的电位在发光阶段发生变化，无法保持稳定。受不同像素电路100中第一晶体管T1、第二晶体管T2和第三晶体管T3的差异性影响，不同像素电路100中第一节点N1和第三节点N3的电位变化不同，这样就导致驱动晶体管Td的栅源电压差出现较明显的变化，驱动晶体管Td所形成的电流大小出现波动，无法驱动发光器件109稳定发光，进而使得像素变亮或变暗，出现亮暗点不良等现象。
在本公开的一些实施例所提供的像素电路100中，称与驱动晶体管Td的控制极(第一节点N1)电连接的晶体管为第一开关晶体管，称与驱动晶体管Td的第一极或第二极电连接的晶体管为第二开关晶体管。
本公开的发明人经研究发现，开关晶体管在截止状态下存在漏电流除上述描述的原因外，还受开关晶体管的源极和漏极的电压差的影响，当开关晶体管的源漏电压差越大，漏电越严重，当开关晶体管的漏极和漏极的电压基本相等时，基本不会有漏电流流过，并且，在开关晶体管的第一极的电位大于其第二极的电位的情况下，漏电流基本无法从开关晶体管的第二极流向第一极，反之亦然。基于此，在一些实施例中，本公开的发明人通过重新设计第一开关晶体管(即第一晶体管T1和第二晶体管T2)的有源层的图案，使第一开关晶体管的有源层的部分结构与栅极控制线GL之间能够交叠形成电容，以在像素电路100中增加设置稳压子电路，该稳压子电路能够使得第一 开关晶体管的源极和漏极的电压保持稳定，降低源漏电压差，从而实现降低第一开光晶体管在发光阶段的漏电，使第一节点N1的电位保持稳定的效果。
以下首先介绍显示面板01所包括的各膜层结构。
在一些实施例中，如图5所示，显示面板01具有如下结构，显示面板01包括依次层叠设置的衬底201、半导体层202、第一栅极绝缘层203、第一栅极层204、第二栅极绝缘层205、第二栅极层206、层间绝缘层207和源漏金属层。图6～图9分别示出了对应图3A和图3B所示的像素电路100的半导体层202、第一栅极层204、第二栅极层206和源漏金属层。图11和图12为像素电路100中各膜层的整体布局图(其中，第一栅极绝缘层203、第一栅极绝缘层203和层间绝缘层207为透明色)。其中，图6为对应图3A所示的像素电路100的半导体层202的结构图，图7为对应图3B所示的像素电路100的半导体层202的结构图。
在一些示例中，半导体层202设置在衬底201上，半导体层202具有设定图案，半导体层202包括各像素电路100中各晶体管的有源层，此处称为有源层主体。如图6和图7所示，在一个子像素区域内，半导体层202包括驱动晶体管Td的有源层主体td、第一晶体管T1的有源层主体t1、第二晶体管T2的有源层主体t2、第三晶体管T3的有源层主体t3、第四晶体管T4的有源层主体t4、第五晶体管T5的有源层主体t5和第六晶体管T6的有源层主体t6。各晶体管的有源层主体可包括至少一个沟道区和至少一个导电区，其中，导电区为源极区域或者漏极区域。晶体管的有源区为有源层主体中与对应的栅极控制线GL有交叠的部分，例如图6和图7中虚线框的部分为个晶体管的有源区。例如，各晶体管的有源层一体设置。
示例性地，半导体层202可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。半导体层202的制备例如为在衬底201的表面沉积半导体材料，经过刻蚀工艺形成半导体层202，使半导体层202具有设定图案。
第一栅极绝缘层203设置于半导体层202远离衬底201的一侧，第一栅极层204设置于第一栅极绝缘层203远离衬底201的一侧，第一栅极绝缘层203被配置为将半导体层202和第一栅极层204彼此隔绝，并保护半导体层202。
在一些示例中，如图8所示，第一栅极层204包括多条栅极控制线GL、多条发光控制线EL和多个存储电容器Cst的第一极板Cst1，具体的，第一栅极层204包括第一复位信号线Reset1、第二复位信号线Reset2、栅极扫描线 Gate和发光控制线EL。示例性地，第一栅极层204中的信号线与半导体层202中的晶体管的有源层有交叠的部分作为该晶体管的栅极，晶体管的有源层中与栅极正对的部分为沟道区。
例如，如图11所示，第一晶体管T1的有源层主体与第一复位信号线Reset1有两处交叠，则第一晶体管T1的栅极为第一复位信号线Reset1中与第一晶体管T1的有源层有交叠的部分，第一晶体管T1的有源层包括两个沟道区，理解的是，第一晶体管T1为双栅晶体管。或者，如图12所示，第一晶体管T1的有源层主体与第一复位信号线Reset1有一处交叠，则第一晶体管T1的栅极为第一复位信号线Reset1中与第一晶体管T1的有源层有交叠的部分，第一晶体管T1的有源层包括一个沟道区，可以理解的是，第一晶体管T1为单栅晶体管。
例如，如图11所示，第二晶体管T2的有源层主体与栅极扫描线Gate有两处交叠，则第二晶体管T2的栅极为栅极扫描线Gate中与第二晶体管T2的有源层有交叠的部分，第二晶体管T2的有源层包括两个沟道区，可以理解的是，第二晶体管T2为双栅晶体管。或者，如图12所示，第二晶体管T2的有源层主体与栅极扫描线Gate有一处交叠，则第二晶体管T2的栅极为栅极扫描线Gate中与第二晶体管T2的有源层有交叠的部分，第二晶体管T2的有源层包括一个沟道区，可以理解的是，第二晶体管T2为单栅晶体管。
以上仅是第一晶体管T1和第二晶体管T2的有源层和栅极的一种示例，其他晶体管的栅极和有源层的沟道区可以参考附图以及上述对于第一晶体管T1和第二晶体管T2的描述，此处不再赘述。
需要说明的是，图6和图7中的各虚线矩形框示出了像素电路100中各晶体管的有源层与第一栅极层204交叠的各个部分。
第二栅极绝缘层205设置于第一栅极层204远离衬底201的一侧，第二栅极层206设置于第二栅极绝缘层205远离衬底201的一侧，第二栅极绝缘层205被配置为将第一栅极层204和第二栅极层206彼此隔绝，并保护第一栅极层204。
在一些示例中，如图9所示，第二栅极层206包括多条初始化信号线Vint和多个存储电容器Cst的第二极板。每条初始化信号线Vint通过过孔与第一晶体管T1和第七晶体管的导电区电连接，存储电容器Cst的第一极板在衬底201上的正投影与其第二极板在衬底201上的正投影具有交叠部分，该交叠部分形成存储电容器Cst。
层间绝缘层207设置在第二栅极层206远离衬底201的一侧，源漏电极 层208设置于层间绝缘层207远离衬底201的一侧，层间绝缘层207被配置为将第二栅极层206和源漏电极层208彼此隔绝，并保护第二栅极层206。
在一些示例中，如图10所示，源漏电极层208包括多条第一电压信号线VDD、多条数据线DL和至少一个连接部2081，一条第一电压信号线VDD通过过孔与一个存储电容器Cst的第二极板电连接，一条数据线DL通过过孔与第四晶体管T4的导电区电连接。连接部2081被配置为使晶体管与信号线实现电连接，或者使晶体管与晶体管实现电连接。
为解决像素电路100中的第一开关晶体管在发光阶段的漏电问题，在一些实施例中，第一开关晶体管的有源层的图案具有重新设计的图案，以下对第一开关晶体管的有源层的图案进行介绍，对于显示面板01所包括的第一栅极绝缘层203、第一栅极层204、第二栅极绝缘层205、第二栅极层206、层间绝缘层207和源漏金属层等膜层可参见上述介绍。需要说明的是，以下第一开关晶体管均指第一晶体管T1和第二晶体管T2。
如图13所示，在一些实施例中，第一开关晶体管包括有源层，该有源层包括有源层主体和至少一个延伸部，有源层主体包括至少一个沟道区和至少一个导电区。延伸部与有源层主体的导电区电连接。例如，请参见图13，第一开关晶体管为第一晶体管T1，第一晶体管T1包括有源层T1’，有源层T1’包括有源层主体t1和至少一个延伸部p，有源层主体包括至少一个沟道区和至少一个导电区，或者，第一开关晶体管为第二晶体管T2，第二晶体管T2包括有源层T2’，有源层T2’包括有源层主体t2和至少一个延伸部p’，有源层主体包括至少一个沟道区和至少一个导电区，其中，有源层主体中虚线框的部分为沟道区，其他区域为导电区。
如图14所示，每个延伸部在衬底201上的正投影与一条栅极控制线GL在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。例如，第一晶体管T1的延伸部p在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。即第一开关晶体管的有源层除上述提到的有源层主体之外，还包括与有源层主体的导电区电连接的至少一个延伸部，且该延伸部与一条栅极控制线GL的位置关系为，延伸部在衬底201上的正投影与一条栅极控制线GL在衬底201上的正投影至少部分重叠。
本公开的一些实施例提供的显示面板01中，半导体层202具有经过特殊设计的图案，即通过对每个像素电路100的第一开关晶体管的有源层的图案进行设计，使其包括有源层主体和至少一个延伸部，该至少一个延伸部与有 源层主体的导电区电连接，且延伸部在衬底201上的正投影与一条栅极控制线GL在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器，相当于将第一开关晶体管与稳压电容器并联，根据电容器的特性，电容器具有储存电荷的能力，能够保持其两端的电压稳定，因此通过设置稳压电容器能够使第一开关晶体管的漏极和漏极的电压基本相等，从而使第一开关晶体管的漏电流减小，提高驱动晶体管Td所生成的驱动晶体管Td的控制极的电位(即第一节点N1的电位)的稳定性，进而提高驱动信号的稳定性，从而提高发光器件109的发光的稳定性和持续性，改善由于第一开关晶体管漏电引起的显示画面的亮暗点不良。
并且，上述显示面板01中半导体层202的制备可以为先沉积半导体材料再通过刻蚀工艺形成图案，得到半导体层202，其他膜层并未发生改变，无需增加额外的掩模板，因此上述显示面板01在没有增加制备工艺难度的前提下，改善了由于第一开关晶体管漏电引起的显示画面的亮暗点不良。
如图27、图29、图31和图32所示，对应上述第一开关晶体管的有源层的图案设计，本公开的一些实施例所提供的像素电路100除包括前述提到的存储子电路101、驱动子电路102、第一复位子电路103、第二复位子电路108、补偿子电路104、数据写入子电路105、第一发光控制子电路106和第二发光控制子电路107之外，还包括第一稳压子电路110和第二稳压子电路111。
其中，第一稳压子电路110与第一复位子电路103、第一复位信号线Reset1或栅极扫描线Gate电连接；第一稳压子电路110被配置为抑制第一复位子电路103漏电。第二稳压子电路111与补偿子电路104、第一复位信号线Reset1或栅极扫描线Gate电连接；第一稳压子电路110被配置为抑制补偿子电路104漏电。
上述像素电路100中，通过设置第一稳压子电路110和第二稳压子电路111，能够抑制第一复位子电路103和补偿子电路104在发光阶段漏电，从而提高第一节点N1的电位的稳定性，进而提高驱动子电路102所生成的驱动信号的稳定性，从而提高发光器件109的发光的稳定性和持续性，改善由于第一复位子电路103和补偿子电路104漏电引起的显示画面的亮暗点不良。
以下分别就第一开关晶体管为双栅晶体管或者单栅晶体管的情况，第一第一开关晶体管的有源层的结构进行介绍。下面首先介绍第一开关晶体管为双栅晶体管的情况。
在一些实施例中，如图13～图21所示，第一开关晶体管(T1或T2)的有源层主体(t1或t2)包括两个沟道区和三个导电区，导电区与沟道区依次交替 电连接，且其中一个导电区位于两个沟道区之间。一条栅极控制线GL在衬底201上的正投影与第一开关晶体管的两个沟道区在衬底201上的正投影重叠。即第一开关晶体管为双栅晶体管。
第一开关晶体管(T1或T2)的有源层(T1’或T2’)包括至少一个第一延伸部(p1或p1’)。第一开关晶体管(T1或T2)的第一延伸部(p1或p1’)与位于第一开关晶体管(T1或T2)的两个沟道区之间的导电区电连接，且第一开关晶体管(T1或T2)的第一延伸部(p1或p1’)在衬底201上的正投影与一条栅极控制线GL在衬底201上的正投影至少部分，二者相互重叠的部分形成稳压电容器(C1或C5)。其中，栅极控制线GL包括第一复位信号线Reset1或栅极扫描线Gate。
示例性地，第一开关晶体管的有源层包括一个第一延伸部、或者两个第一延伸部，或者三个第一延伸部，第一开关晶体管的第一延伸部与栅极控制线GL交叠的部分形成一个稳压电容器、两个稳压电容器或三个稳压电容器。在第一开关晶体管的有源层包括多个第一延伸部，第一开关晶体管的多个第一延伸部与栅极控制线GL交叠的部分形成多个稳压电容器的情况下，能够增强多个稳压电容器与第一开关晶体管电连接的一端的电压稳定性，从而进一步增强对第一开关晶体管的漏电的改善效果。本公开的以下实施例以第一开关晶体管的有源层包括一个第一延伸部为例进行介绍。
如图15～图21所示，在一些示例中，第一开关晶体管(T1或T2)的三个导电区分别为第一导电区(t13或t23)、第二导电区(t14或t24)和第三导电区(t15或t25)，第二导电区(t14或t24)位于位于第一开关晶体管(T1或T2)的两个沟道区之间。第一延伸部(p1或p1’)的一端与第二导电区(t14或t24)电连接，另一端向远离第二导电区(t14或t24)的方向延伸；第一延伸部(p1或p1’)位于第一导电区与第三导电区之间，或者位于第一开关晶体管的有源层主体的一侧。
以下分别以第一开关晶体管为第一晶体管T1或第二晶体管T2为例，对第一开关晶体管的有源层进行介绍。
例如，如图15～图18所示，第一开关晶体管为第一晶体管T1，且第一晶体管T1为双栅晶体管，第一晶体管T1的有源层主体t1呈U型，第一晶体管T1的有源层主体t1包括第一沟道区t11、第二沟道区t12、第一导电区t13、第二导电区t14和第三导电区t15，第一晶体管T1的第一延伸部p1的一端与第二导电区t14电连接，另一端向远离第二导电区t14的方向延伸，第一晶体管T1的第一延伸部p1在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第一稳压电容器C1。如图16和图17所示，第一晶体管T1的第一延伸部位于第一导电区t13 与第三导电区t15之间；或者，如图15和图18所示，第一晶体管T1的第一延伸部p1位于第一晶体管T1的有源层主体t1的一侧，例如第一晶体管T1的第一延伸部p1位于第一导电区t13的远离第三导电区t15的一侧。
需要说明的是，第一晶体管T1的至少一个第一延伸部p1与第一复位信号线Reset1交叠的部分形成至少一个第一稳压电容器C1。即第一晶体管T1的第一延伸部p1的数量与第一稳压电容器C1的数量一致。
例如，如图15～图18所示，第一开关晶体管为第二晶体管T2，且第二晶体管T2为双栅晶体管，第二晶体管T2的有源层主体t2呈L型，第二晶体管T2的有源层主体t2包括第一沟道区t21、第二沟道区t22、第一导电区t23、第二导电区t24和第三导电区t25，第二晶体管T2的第一延伸部p1’的一端与第二导电区t24电连接，另一端向远离第二导电区t24的方向延伸，第二晶体管T2的第一延伸部p1’在衬底201上的正投影与第一复位信号线Reset1或者栅极扫描线Gate在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第五稳压电容器C5。
如图16所示，第二晶体管T2的第一延伸部p1’位于第一导电区t23与第三导电区t25之间，第二晶体管T2的第一延伸部p1’在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠。或者，如图15、图17和图18所示，第二晶体管T2的第一延伸部p1’位于第二晶体管T2的有源层主体t2的一侧，第二晶体管T2的第一延伸部p1’在衬底201上的正投影与第一复位信号线Reset1或栅极扫描线Gate在衬底201上的正投影至少部分重叠，例如，如图15和图17所示，第二晶体管T2的第一延伸部p1’位于第二导电区t24的远离第一导电区t23的一侧，第二晶体管T2的第一延伸部p1’在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠。如图18所示，第二晶体管T2的第一延伸部p1’位于第二导电区t24的远离第一导电区t23的一侧，第二晶体管T2的第一延伸部p1’在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠。
需要说明的是，第二晶体管T2的至少一个第一延伸部与第一复位信号线Reset1或栅极扫描线Gate交叠的部分形成至少一个第五稳压电容器C5，即第二晶体管T2的第一延伸部的数量与第五稳压电容器C5的数量一致。
如图27所示，对应上述第一开关晶体管(T1或T2)的有源层的图案设计，本公开的一些实施例所提供的像素电路100中，第一稳压子电路110包括至少一个第一稳压电容器C1，第二稳压子电路111包括至少一个第五稳压电容器C5。
如图27所示，在第一复位子电路103包括第一晶体管T1，且第一晶体管T1为双栅晶体管的情况下，第一晶体管T1包括第一子晶体管T11和第二子晶体管T12；第一子晶体管T11的控制极与第一复位信号线Reset1电连接，第一子晶体管T11的第一极与初始化信号线Vint电连接，第一子晶体管T11的第二极与第二子晶体管T12的第一极电连接；第二子晶体管T12的控制极与电连接，第二子晶体管T12的第二极与驱动晶体管Td的控制极电连接，即第二子晶体管T12的第二极与第一节点N1电连接。第一稳压电容器C1的第一端与第一子晶体管T11的第二极电连接，即第一稳压电容器C1的第一端与第一节点N1电连接，第一稳压电容器C1的第二端与第一复位信号线Reset1电连接。
在补偿子电路104包括第二晶体管T2，且第二晶体管T2为双栅晶体管的情况下，第二晶体管T2包括第三子晶体管T21和第四子晶体管T22；第三子晶体管T21的控制极与栅极扫描线Gate电连接，第三子晶体管T21的第一极与驱动晶体管Td的第二极电连接，第三子晶体管T21的第二极与第四子晶体管T22的第一极电连接；第四子晶体管T22的控制极与栅极扫描线Gate电连接，第四子晶体管T22的第二极与驱动晶体管Td的控制极电连接，即第四子晶体管T22的第二极与第一节点N1电连接。第五稳压电容器C5的第一端与第三子晶体管T21的第二极电连接，即第五稳压电容器C5的第一端与第一节点N1电连接，第五稳压电容器C5的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。
以下以第二晶体管T2和第五稳压电容器C5的工作过程为例，介绍第五稳压电容器C5抑制第二晶体管T2漏电的原理。由于第一晶体管T1和第一稳压电容器C1与第二晶体管T2与第五稳压电容器C5的结构类似，因此第一稳压电容器C1抑制第一晶体管T1漏电的原理可以参考下述描述，此处不再赘述。
如图28A和图28B所示，为方便说明，将第五稳压电容器C5和第二晶体管T2的等效图简化，第二晶体管T2包括第三子晶体管T21和第四子晶体管T22，以下描述中，第三子晶体管T21的第一极的电位为V s，第三子晶体管T21的第二极的电位为V d’，第四子晶体管T22的第一极的电位为V s’，第四子晶体管T22的第二极的电位为V d，第五稳压电容器C5的第一端的电位为V c5。
在输入与补偿阶段P2，第三子晶体管T21和第四子晶体管T22均在栅极扫描信号的控制下导通，将电信号I由第二节点N2传输至第一节点N1，在 输入与补偿阶段P2结束后，V s大于V d’，V d’等于或大约等于V s’，且V s’大于V d，V c5等于或大约等于V s’，即且由于电容器的电压保持作用，第五稳压电容器C5的第一端的电位V c5保持稳定。在发光阶段P3，第三子晶体管T21和第四子晶体管T22均在栅极扫描信号的控制下截止，由于第五稳压电容器C5的第一端的电位V c5得以保持，因此V s’和V d’大致保持不变，V s’依旧大于V d，这样，电流无法由第四子晶体管T22的第二极流向第一极，可以抑制第一节点N1通过第四子晶体管T22反向漏电，同理，V s依旧大于V d’，这样，电流无法由第三子晶体管T21的第二极流向第一极，可以抑制第三子晶体管T21反向漏电，从而通过设置第五稳压电容器C5能够有效降低第三子晶体管T21和第四子晶体管T22在发光阶段P3的漏电，从而第一节点N1的电压得以保持。
在一些实施例中，如图19～图21所示，在第一开关晶体管为双栅晶体管的情况下，第一开关晶体管(T1或T2)的有源层除包括至少一个第一延伸部(p1或p1’)之外，还包括至少一个第二延伸部(p2或p2’)。第一开关晶体管(T1或T2)的三个导电区中的一个导电区与驱动晶体管Td的控制极电连接；第一开关晶体管的第二延伸部与三个导电区中电连接驱动晶体管Td的控制极的一个导电区电连接，且第一开关晶体管的第二延伸部(p2或p2’)在衬底201上的正投影与一条栅极控制线GL在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。其中，栅极控制线GL包括第一复位信号线Reset1或栅极扫描线Gate。
示例性地，第一开关晶体管的有源层包括一个第二延伸部、或者两个第二延伸部，或者三个第二延伸部，第一开关晶体管的第二延伸部与栅极控制线GL交叠的部分形成一个稳压电容器、两个稳压电容器或三个稳压电容器。在第一开关晶体管的有源层包括多个第二延伸部，第一开关晶体管的多个第二延伸部与栅极控制线GL交叠的部分形成多个稳压电容器的情况下，能够增强多个稳压电容器与第一开关晶体管电连接的一端的电压稳定性，从而进一步增强对第一开关晶体管的漏电的改善效果。本公开的以下实施例以第一开关晶体管的有源层包括一个第二延伸部为例进行介绍。
如图19～图21所示，在一些示例中，第一开关晶体管的三个导电区分别为第一导电区(t13或t23)、第二导电区(t14或t24)和第三导电区(t15或t25)，第二导电区(t14或t24)位于位于第一开关晶体管(T1或T2)的两个沟道区之间；第一导电区(t13或t23)与驱动晶体管Td的控制极电连接。第二延伸部(p2或p2’)的一端与第一导电区(t13或t23)电连接，另一端向远离第一导电区(t13 或t23)的方向延伸。第二延伸部位于第一导电区与第三导电区之间，或者位于第一开关晶体管的有源层主体的一侧。
以下分别以第一开关晶体管为第一晶体管T1或第二晶体管T2为例，对第一开关晶体管的有源层进行介绍。
例如，如图19～图21所示，第一开关晶体管为第一晶体管T1，且第一晶体管T1为双栅晶体管，第一晶体管T1的有源层主体t1呈U型，第一晶体管T1的有源层主体t1包括第一沟道区t11、第二沟道区t12、第一导电区t13、第二导电区t14和第三导电区t15，第一晶体管T1的第二延伸部p2的一端与第一导电区t13电连接，另一端向远离第一导电区t13的方向延伸，第一晶体管T1的第二延伸部p2在衬底201上的正投影与第一复位信号线Reset1或栅极扫描线Gate在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第二稳压电容器C2。
如图19所示，第一晶体管T1的第二延伸p2部位于第一导电区t13与第三导电区t15之间，第一晶体管T1的第二延伸部p2在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠。或者，如图20和图21所示第一晶体管T1的第二延伸部p2位于第一晶体管T1的有源层主体的一侧，示例性地，如图20所示，第一晶体管T1的第二延伸部p2位于第一导电区t13的远离第三导电区t15的一侧且靠近第一复位信号线Reset1，第一晶体管T1的第二延伸部p2在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠。示例性地，第一晶体管T1的第二延伸部p2位于第一导电区t13的远离第三导电区t15的一侧且靠近栅极扫描线Gate，第一晶体管T1的第二延伸部p2在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠。
需要说明的是，第一晶体管T1的至少一个第二延伸部p2与第一复位信号线Reset1或栅极扫描线Gate交叠的部分形成至少一个第二稳压电容器C2。即第一晶体管T1的第二延伸部的数量与第二稳压电容器C2的数量一致。
例如，如图19和图20所示，第一开关晶体管为第二晶体管T2，且第二晶体管T2为双栅晶体管，第二晶体管T2的有源层主体呈L型，第二晶体管T2的有源层主体t2包括第一沟道区t21、第二沟道区t22、第一导电区t23、第二导电区t24和第三导电区t25，第二晶体管T2的第二延伸部p2’的一端与第二导电区t24电连接，另一端向远离第二导电区t24的方向延伸，第二晶体管T2的第二延伸部p2’在衬底201上的正投影与第一复位信号线Reset1或者栅极扫描线Gate在衬底201上的正投影至少部分重叠，二者相互重叠的部分 形成第六稳压电容器C6。
示例性地，如图19和图20所示，第二晶体管T2的第二延伸部p2’位于第一晶体管T1的有源层主体t2的一侧，第二晶体管T2的第二延伸部p2’在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠。或者，第二晶体管T2的第二延伸部p2’在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠。
需要说明的是，第二晶体管T2的至少一个第二延伸部p2’与第一复位信号线Reset1或栅极扫描线Gate交叠的部分形成至少一个第六稳压电容器C6，即第二晶体管T2的第一延伸部的数量与第五稳压电容器C5的数量一致。
如图29所示，对应上述第一开关晶体管的有源层的图案设计，本公开的一些实施例所提供的像素电路100中，第一稳压子电路110在包括至少一个第一稳压电容器C1的基础上，还包括至少一个第二稳压电容器C2，第二稳压子电路111在包括至少一个第五稳压电容器C5的基础上，还包括至少一个第六稳压电容器C6。
第二稳压电容器C2的第一端与第二子晶体管T12的第二极电连接，第二稳压电容器C2的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。由于第二子晶体管T12的第二极与第一节点N1电连接，也就是说第二稳压电容器C2的第一端与第一节点N1电连接。
第六稳压电容器C6的第一端与第四子晶体管T22的第二极电连接，第六稳压电容器C6的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。由于第四子晶体管T22的第二极与第一节点N1电连接，也就是说第二稳压电容器C2的第一端与第一节点N1电连接。
如图30A和图30B所示，上述第六稳压电容器C6与第一节点N1电连接，相当于第六稳压电容器C6与存储电容器Cst并联，在复位阶段以及输入与补偿阶段P2，在存储电容器Cst被充电的过程中，同时第六稳压电容器C6也被充电，即第六稳压电容器C6的第一端的电位与存储电容器Cst的第一端的电位保持一致，当进入发光阶段时，即便第二晶体管T2(第三子晶体管T21和第四子晶体管T22)存在漏电，第六稳压电容器C6所存储的电荷可以向第一节点N1提供一部分电荷，这样可以用来弥补第二晶体管T2漏电所导致的压降，相当于通过设置第六稳压电容器C6增强了存储电容器Cst的电荷储存能力，能够使第一节点N1的电位保持稳定，并且可以使第二晶体管T2的第一极和第二极之间的电压差降低，从而减轻第二晶体管T2的漏电。第二稳压电容器C2的工作原理可以参照对于第六稳压电容器C6的工作原理的描述，此 处不再赘述。
需要说明的是，本公开的上述实施例以及图15～图21提供了半导体层202的多种图案设计，本公开还可以包括其他的实施例，只要能实现抑制第一开关晶体管漏电的功能即可，图22为半导体层202、第一栅极层204、第二栅极层206和源漏金属层的一种整体结构图，其中半导体层202中，第一晶体管T1的有源层包括有源层主体和延伸部，第二晶体管T2的有源层包括有源层主体和延伸部，其余膜层的图案相对于图11并未发生改变，只需将图15～图21所示的半导体层202与图22中的半导体层202替换即可得到多种结构整体结构图。
以下介绍第一开关晶体管为单栅晶体管的情况。
如图23～图25所示，在一些实施例中，第一开关晶体管(T1或T2)的有源层主体(t1或t2)包括沟道区(t11或t22)、第四导电区(t16或t26)和第五导电区(t17或t27)，第四导电区(t16或t26)和第五导电区(t17或t27)分别位于沟道区(t11或t22)的两侧；一条栅极控制线GL在衬底201上的正投影与第一开关晶体管的沟道区在衬底201上的正投影重叠。其中，第四导电区(t16或t26)与驱动晶体管Td的控制极电连接。
第一开关晶体管(T1或T2)的有源层(T1’或T2’)包括至少一个第三延伸部(p3或p3’)；第三延伸部(p3或p3’)与第四导电区(t16或t26)电连接，且第三延伸部(p3或p3’)在衬底201上的正投影与栅极控制线GL在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。其中，栅极控制线GL包括第一复位信号线Reset1或者栅极扫描线Gate。
在一些实施例中，第一开关晶体管(T1或T2)的有源层(T1’或T2’)还包括第四延伸部(p4或p4’)；第四延伸部(p4或p4’)与第五导电区(t17或t27)电连接，且第四延伸部(p4或p4’)在衬底201上的正投影与栅极控制线GL在衬底201上的正投影至少部分重叠。
示例性地，第一开关晶体管的有源层包括一个第三延伸部/第四延伸部、或者两个第三延伸部/第四延伸部，或者三个第三延伸部/第四延伸部，第一开关晶体管的第三延伸部与栅极控制线GL交叠的部分形成一个稳压电容器、两个稳压电容器或三个稳压电容器。在第一开关晶体管的有源层包括多个第三延伸部/第四延伸部，第一开关晶体管的多个第二延伸部与栅极控制线GL交叠的部分形成多个稳压电容器的情况下，能够增强多个稳压电容器与第一开关晶体管电连接的一端的电压稳定性，从而进一步增强对第一开关晶体管的漏电的改善效果。本公开的实施例以第一开关晶体管的有源层包括一个第三 延伸部以及一个第四延伸部为例进行介绍。
以下分别以第一开关晶体管为第一晶体管T1或第二晶体管T2为例，对第一开关晶体管的有源层进行介绍。
例如，如图24所示，第一开关晶体管为第一晶体管T1，且第一晶体管T1为单栅晶体管，第一晶体管T1的有源层主体t1包括沟道区t11、第四导电区t16和第五导电区t17，第四导电区t16和第五导电区t17分别位于沟道区t11的两侧，第四导电区t16与驱动晶体管Td的控制极电连接，第一晶体管T1的第三延伸部p3与第一晶体管T1的第四导电区t16电连接，且第一晶体管T1的第三延伸部p3在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第三稳压电容器C3。
在一些示例中，如图25所示，第一晶体管T1还包括第四延伸部p4，第一晶体管T1的第四延伸部p4与第一晶体管T1的第五导电区t17电连接，且第一晶体管T1的第四延伸部p4在衬底201上的正投影与第一复位信号线Reset1在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第四稳压电容器C4。
例如，如图24所示，第一开关晶体管为第二晶体管T2，且第二晶体管T2为单栅晶体管，第二晶体管T2的有源层主体包括沟道区t22、第四导电区t26和第五导电区t27，第四导电区t26和第五导电区t27分别位于沟道区t22的两侧，第四导电区t26与驱动晶体管Td的控制极电连接，第二晶体管T2的第三延伸部p3’与第二晶体管T2的第四导电区t26连接，且第二晶体管T2的第三延伸部t26在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第七稳压电容器C7。
在一些示例中，如图25所示，第二晶体管T2还包括第四延伸部p4’，第二晶体管T2的第四延伸部p4’与第二晶体管T2的第五导电区t27电连接，且第二晶体管T2的第四延伸部p4’在衬底201上的正投影与栅极扫描线Gate在衬底201上的正投影至少部分重叠，二者相互重叠的部分形成第八稳压电容器C8。
如图31和图32所示，对应上述第一开关晶体管的有源层的图案设计，本公开的一些实施例所提供的像素电路100中，对于第一开关晶体管为单栅晶体管的情况，第一稳压子电路110包括至少一个第三稳压电容器C3，第二稳压子电路111包括至少一个第七稳压电容器C7，或者，第一稳压子电路110包括至少一个第三稳压电容器C3和至少一个第四稳压电容器C4，第二稳压子电路111包括至少一个第七稳压电容器C7和至少一个第八稳压电容器C8。
在第一复位子电路103包括第一晶体管T1，第一晶体管T1为单栅晶体管的情况下，第一晶体管T1的控制极与第一复位信号线Reset1电连接，第一晶体管T1的第一极与初始化信号线Vint电连接，第一晶体管T1的第二极与驱动晶体管Td的控制极电连接。第三稳压电容器C3的一端与第一晶体管T1的第二极电连接，第三稳压电容器C3的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。第四稳压电容器C4的一端与第一晶体管T1的第一极电连接，第四稳压电容器C4的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。
在补偿子电路104包括第二晶体管T2，第二晶体管T2为单栅晶体管的情况下，第二晶体管T2的控制极与栅极扫描线Gate电连接，第二晶体管T2的第一极与驱动晶体管Td的第二极电连接，第二晶体管T2的第二极与驱动晶体管Td的控制极电连接。第七稳压电容器C7的第一端与第二晶体管T2的第二极电连接，第七稳压电容器C7的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。第八稳压电容器C8的第一端与第二晶体管T2的第一极电连接，第四稳压电容器C4的第二端与第一复位信号线Reset1或栅极扫描线Gate电连接。
以下以第二晶体管T2和第七稳压电容器C7、第八稳压电容器C8的工作过程为例，介绍第七稳压电容器C7、第八稳压电容器C8抑制第二晶体管T2漏电的原理。由于第一晶体管T1、第三稳压电容器C3和第四稳压电容器C4与第二晶体管T2、第七稳压电容器C7和第八稳压电容器C8的结构类似，因此第三稳压电容器C3和第四稳压电容器C4抑制第一晶体管T1漏电的原理可以参考下述描述，此处不再赘述。
如图33A和图33B所示，为方便说明，以下描述中，第二晶体管T2的第一极的电位为V s，第二子晶体管T12的第二极的电位为V d，第七稳压电容器C7的第一端的电位为V c7，第八稳压电容器C8的第一端的电位为V c8。
在输入与补偿阶段P2，第二晶体管T2在栅极扫描信号的控制下导通，将电信号I由第二节点N2传输至第一节点N1，在输入与补偿阶段P2结束后，V s大于V d，V c7等于或大约等于V d，V c8等于或大约等于V s，且由于电容器的电压保持作用，第七稳压电容器C7第一端的电位V c7和第八稳压电容器C8的第一端的电位V c8均能保持稳定。在发光阶段P3，第二子晶体管T12在栅极扫描信号的控制下截止，第七稳压电容器C7第一端的电位V c7和第八稳压电容器C8的第一端的电位V c8得以保持，因此V s和V d大致保持不变，V s依旧大于V d，这样，电流无法由第二晶体管T2的第二极流向第一极，可以抑制 第一节点N1通过第二晶体管T2反向漏电，从而第一节点N1的电压得以保持。
并且，如图33A和图33B所示，上述第七稳压电容器C7与第一节点N1电连接，相当于第七稳压电容器C7与存储电容器Cst并联，在复位阶段以及输入与补偿阶段P2，在存储电容器Cst被充电的过程中，同时第七稳压电容器C7也被充电，即第七稳压电容器C7的第一端的电位与存储电容器Cst的第一端的电位保持一致，当进入发光阶段时，即便第二晶体管T2存在漏电，第七稳压电容器C7所存储的电荷可以向第一节点N1提供一部分电荷，这样可以用来弥补第二晶体管T2漏电所导致的压降，相当于通过设置第七稳压电容器C7增强了存储电容器Cst的电荷储存能力，能够使第一节点N1的电位保持稳定，并且可以使第二晶体管T2的第一极和第二极之间的电压差降低，从而减轻第二晶体管T2的漏电。第三稳压电容器C3的工作原理可以参照对于第七稳压电容器C7的工作原理的描述，此处不再赘述。
需要说明的是，本公开的上述实施例以及图23～图25提供了半导体层202的多种图案设计，本公开还可以包括其他的实施例，只要能实现抑制第一开关晶体管漏电的功能即可，图26为半导体层202、第一栅极层204、第二栅极层206和源漏金属层的一种整体结构图，其中半导体层202中，第一晶体管T1的有源层包括有源层主体和延伸部，第二晶体管T2的有源层包括有源层主体和延伸部，其余膜层的图案相对于图12并未发生改变，只需将图23～图25所示的半导体层202与图26中的半导体层202替换即可得到多种整体结构图。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示面板，包括：
    衬底；
    设置于所述衬底上的多个子像素；每个子像素包括像素电路；所述像素电路包括驱动晶体管和至少一个第一开关晶体管，所述第一开关晶体管与所述驱动晶体管的控制极电连接；和
    设置于所述衬底上的多条栅极控制线；每个像素电路与至少两条栅极控制线电连接；
    其中，所述第一开关晶体管包括有源层，所述有源层包括有源层主体和至少一个延伸部，所述有源层主体包括至少一个沟道区和至少一个导电区；
    所述延伸部与所述有源层主体的导电区电连接；所述延伸部在所述衬底上的正投影与一条栅极控制线在所述衬底上的正投影至少部分重叠，二者相互重叠的部分形成稳压电容器。
  2. 根据权利要求1所述的显示面板，其中，所述第一开关晶体管的有源层包括至少一个第一延伸部；
    所述第一开关晶体管的有源层主体包括两个沟道区和三个导电区，导电区与沟道区依次交替电连接，且其中一个导电区位于所述两个沟道区之间；
    一条栅极控制线在所述衬底上的正投影与所述第一开关晶体管的两个沟道区在所述衬底上的正投影重叠；
    所述第一开关晶体管的第一延伸部与位于所述第一晶体管的两个沟道区之间的导电区电连接，且所述第一开关晶体管的第一延伸部在所述衬底上的正投影与一条栅极控制线在所述衬底上的正投影至少部分重叠。
  3. 根据权利要求2所述的显示面板，其中，所述第一开关晶体管的三个导电区分别为第一导电区、第二导电区和第三导电区，所述第二导电区位于位于所述第一开关晶体管的两个沟道区之间；
    所述延伸部的一端与所述第二导电区电连接，另一端向远离所述第二导电区的方向延伸；
    所述第一延伸部位于所述第一导电区与所述第三导电区之间，或者位于所述第一晶体管的有源层主体的一侧。
  4. 根据权利要求2或3所述的显示面板，其中，所述第一开关晶体管的有源层还包括至少一个第二延伸部；
    所述第一开关晶体管的三个导电区中的一个导电区与所述驱动晶体管的控制极电连接；
    所述第一开关晶体管的第二延伸部与所述三个导电区中电连接所述驱动晶体管的控制极的一个导电区电连接，且所述第一开关晶体管的第二延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
  5. 根据权利要求4所述的显示面板，其中，所述第一开关晶体管的三个导电区分别为第一导电区、第二导电区和第三导电区，所述第二导电区位于位于所述第一开关晶体管的两个沟道区之间；所述第一导电区与所述驱动晶体管的控制极电连接；
    所述第二延伸部的一端与所述第一导电区电连接，另一端向远离所述第一导电区的方向延伸；
    所述第二延伸部位于所述第一导电区与所述第三导电区之间，或者位于所述第一开关晶体管的有源层主体的一侧。
  6. 根据权利要求1所述的显示面板，其中，所述第一开关晶体管的有源层包括至少一个第三延伸部；
    所述第一开关晶体管的有源层主体包括沟道区、第四导电区和第五导电区，所述第四导电区和所述第五导电区分别位于所述沟道区的两侧；其中，所述第四导电区与所述驱动晶体管的控制极电连接；
    所述第三延伸部与所述第四导电区连接，且所述第三延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
  7. 根据权利要求6所述的显示面板，其中，所述第一开关晶体管的有源层还包括第四延伸部；
    所述第四延伸部与所述第五导电区电连接，且所述第四延伸部在所述衬底上的正投影与所述栅极控制线在所述衬底上的正投影至少部分重叠。
  8. 根据权利要求1～7中任一项所述的显示面板，还包括：
    多条初始化信号线，每个像素电路还与至少一条初始化信号线电连接；
    其中，与所述像素电路电连接的栅极控制线包括第一复位信号线；
    所述至少一个第一开关晶体管包括第一晶体管；所述第一晶体管的控制极与所述第一复位信号线电连接，所述第一晶体管的第一极与一条初始化信号线电连接，所述第一晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第一晶体管的延伸部在所述衬底上的正投影与所述第一复位信号线在所述衬底上的正投影至少部分重叠。
  9. 根据权利要求8所述的显示面板，其中，与所述像素电路电连接的栅极控制线还包括栅极扫描线；
    所述至少一个第一开关晶体管还包括第二晶体管；所述第二晶体管的控制极与所述栅极扫描线电连接，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第二晶体管的延伸部在所述衬底上的正投影与所述栅极扫描线在所述衬底上的正投影至少部分重叠；或者，所述第二晶体管的延伸部在所述衬底上的正投影与所述第一复位信号线在所述衬底上的正投影至少部分重叠。
  10. 根据权利要求1～9中任一项所述的显示面板，还包括：多条第一电压信号线、多条发光控制线和多条数据线；
    与所述像素电路电连接的栅极控制线还包括第二复位信号线；
    每个像素电路还与一条第一电压信号线电连接；
    所述像素电路还包括存储电容器；
    所述存储电容器包括相对设置的第一极板和第二极板；
    所述第一极板与所述多条栅极控制线同层设置，所述第一极板与所述驱动晶体管的控制极电连接；
    所述第二极板设置于所述第一极板远离所述衬底的一侧；所述第二极板与所述第一电压信号线电连接；
    每个像素电路与一条发光控制线、一条数据线、和所述第二复位信号线电连接；
    所述像素电路还包括至少一个第二开关晶体管，每个第二开关晶体管与所述驱动晶体管的第一极或第二极电连接。
  11. 一种像素电路，包括：
    驱动子电路；所述驱动子电路被配置为产生驱动电流；
    存储子电路；所述存储子电路与所述驱动子电路和第一电压信号线电连接；所述存储子电路被配置为存储所接收的信号，并保持所述存储子电路与所述驱动子电路的连接端的电位；
    第一复位子电路；所述第一复位子电路与第一复位信号线、所述驱动子电路和初始化信号线电连接；所述复位子电路被配置为，响应于在所述第一复位信号线处接收的第一栅极信号，将在所述初始化信号线处接收的初始化信号传输至所述驱动子电路；
    补偿子电路；所述补偿子电路与所述驱动子电路和栅极扫描线电连接；所述补偿子电路被配置为，响应于在所述栅极扫描线处接收的栅极扫描信号，对所述驱动子电路进行阈值补偿；
    第一稳压子电路；所述第一稳压子电路与所述第一复位子电路、所述第一复位信号线或所述栅极扫描线电连接；所述第一稳压子电路被配置为抑制所述第一复位子电路漏电；和
    第二稳压子电路；所述第二稳压子电路与所述补偿子电路、所述第一复位信号线或所述栅极扫描线电连接；所述第一稳压子电路被配置为抑制所述补偿子电路漏电。
  12. 根据权利要求11所述的像素电路，其中，所述驱动子电路包括驱动晶体管；所述第一稳压子电路包括至少一个第一稳压电容器；
    所述第一复位子电路包括第一晶体管，所述第一晶体管为双栅晶体管；
    所述第一晶体管包括第一子晶体管和第二子晶体管；所述第一子晶体管的控制极与所述第一复位信号线电连接，所述第一子晶体管的第一极与所述初始化信号线电连接，所述第一子晶体管的第二极与所述第二子晶体管的第一极电连接；所述第二子晶体管的控制极与所述第一复位信号线电连接，所述第二子晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第一稳压电容器的第一端与所述第一子晶体管的第二极电连接，所述第一稳压电容器的第二端与所述第一复位信号线电连接。
  13. 根据权利要求12所述的像素电路，其中，所述第一稳压子电路还包括至少一个第二稳压电容器；
    所述第二稳压电容器的第一端与所述第二子晶体管的第二极电连接，所述第二稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
  14. 根据权利要求11所述的像素电路，其中，所述驱动子电路包括驱动晶体管；所述第一稳压子电路包括至少一个第三稳压电容器和至少一个第四稳压电容器；
    所述第一复位子电路包括第一晶体管，所述第一晶体管的控制极与所述第一复位信号线电连接，所述第一晶体管的第一极与所述初始化信号线电连接，所述第一晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第三稳压电容器的第一端与所述第一晶体管的第二极电连接，所述第三稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接；
    所述第四稳压电容器的第一端与所述第一晶体管的第一极电连接，所述第四稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
  15. 根据权利要求11～14中任一项所述的像素电路，其中，所述驱动子电路包括驱动晶体管；所述第二稳压子电路包括至少一个第五稳压电容器；
    所述补偿子电路包括第二晶体管，所述第二晶体管为双栅晶体管；
    所述第二晶体管包括第三子晶体管和第四子晶体管；所述第三子晶体管的控制极与所述栅极扫描线电连接，所述第三子晶体管的第一极与所述驱动晶体管的第二极电连接，所述第三子晶体管的第二极与所述第四子晶体管的第一极电连接；所述第四子晶体管的控制极与所述栅极扫描线电连接，所述第四子晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第五稳压电容器的第一端与所述第三子晶体管的第二极电连接，所述第五稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
  16. 根据权利要求15所述的像素电路，其中，所述第二稳压子电路还包括至少一个第六稳压电容器；
    所述第六稳压电容器的第一端与所述第四子晶体管的第二极电连接，所述第六稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
  17. 根据权利要求11～14中任一项所述的像素电路，其中，所述驱动子电路包括驱动晶体管；所述第二稳压子电路包括至少一个第七稳压电容器和至少一个第八稳压电容器；
    所述补偿子电路包括第二晶体管，所述第二晶体管的控制极与所述栅极扫描线电连接，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第七稳压电容器的第一端与所述第二晶体管的第二极电连接，所述第七稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接；
    所述第八稳压电容器的第一端与所述第二晶体管的第一极电连接，所述第八稳压电容器的第二端与所述第一复位信号线或所述栅极扫描线电连接。
  18. 根据权利要求11～17中任一项所述的像素电路，还包括：
    数据写入子电路；所述数据写入子电路与所述栅极扫描线、数据线和所述驱动子电路电连接；所述数据写入子电路被配置为，响应于在所述栅极扫描线处接收的栅极扫描信号，将在所述数据线处接收的数据信号传输至所述驱动子电路；
    所述驱动子电路和所述补偿子电路还被配置为将所述数据信号传输至所述存储子电路；
    第二复位子电路；所述第二复位子电路与第二复位信号线、所述初始化信号线和发光器件电连接；所述第二复位子电路被配置为，响应于在所述栅 极扫描线处接收的栅极扫描信号，将在所述初始化信号线处接收的初始化信号传输至所述发光器件；
    第一发光控制子电路；所述第一发光控制子电路与发光控制线、所述第一电压信号线和所述驱动子电路电连接，所述第一发光控制子电路被配置为，响应于在所述发光控制线处接收的发光控制信号，将在所述第一电压信号线处接收的第一电压信号传输至所述驱动子电路；
    第二发光控制子电路；所述第二发光控制子电路与所述发光控制线、所述驱动子电路和所述发光器件电连接；所述第二发光控制子电路被配置为将所述驱动子电路产生的驱动电流传输至所述发光器件，以控制所述发光器件发光。
  19. 一种显示装置，包括如权利要求1～10中任一项所述的显示面板。
PCT/CN2020/139265 2020-12-25 2020-12-25 显示面板、像素电路及显示装置 WO2022133978A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120019504A1 (en) * 2010-07-20 2012-01-26 Sam-Il Han Pixel and organic light emitting display device using the same
CN110992880A (zh) * 2019-12-19 2020-04-10 武汉天马微电子有限公司 一种显示面板及显示装置
CN111477179A (zh) * 2020-05-20 2020-07-31 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111613177A (zh) * 2020-06-28 2020-09-01 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN111627387A (zh) * 2020-06-24 2020-09-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102491117B1 (ko) * 2015-07-07 2023-01-20 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102434370B1 (ko) * 2015-08-27 2022-08-19 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US10490128B1 (en) * 2018-06-05 2019-11-26 Apple Inc. Electronic devices having low refresh rate display pixels with reduced sensitivity to oxide transistor threshold voltage

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120019504A1 (en) * 2010-07-20 2012-01-26 Sam-Il Han Pixel and organic light emitting display device using the same
CN110992880A (zh) * 2019-12-19 2020-04-10 武汉天马微电子有限公司 一种显示面板及显示装置
CN111477179A (zh) * 2020-05-20 2020-07-31 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111627387A (zh) * 2020-06-24 2020-09-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111613177A (zh) * 2020-06-28 2020-09-01 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板和显示装置

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